diff --git a/Cargo.lock b/Cargo.lock index ffa9a6302ef84..99e9765171c4a 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -78,9 +78,9 @@ dependencies = [ [[package]] name = "dlmalloc" -version = "0.2.11" +version = "0.2.13" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "06cdfe340b16dd990c54cce79743613fa09fbb16774f33a77c9fd196f8f3fa30" +checksum = "9f5b01c17f85ee988d832c40e549a64bd89ab2c9f8d8a613bdf5122ae507e294" dependencies = [ "cfg-if", "libc", @@ -125,9 +125,9 @@ dependencies = [ [[package]] name = "hashbrown" -version = "0.16.1" +version = "0.17.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100" +checksum = "ed5909b6e89a2db4456e54cd5f673791d7eca6732202bbf2a9cc504fe2f9b84a" dependencies = [ "foldhash", "rustc-std-workspace-alloc", @@ -146,9 +146,9 @@ dependencies = [ [[package]] name = "libc" -version = "0.2.183" +version = "0.2.185" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b5b646652bf6661599e1da8901b3b9522896f01e736bad5f723fe7a3a27f899d" +checksum = "52ff2c0fe9bc6cb6b14a0592c2ff4fa9ceb83eea9db979b0487cd054946a2b8f" dependencies = [ "rustc-std-workspace-core", ] @@ -344,9 +344,10 @@ dependencies = [ "std_detect", "unwind", "vex-sdk", - "wasi 0.11.1+wasi-snapshot-preview1", - "wasi 0.14.4+wasi-0.2.4", - "windows-link 0.0.0", + "wasip1", + "wasip2", + "wasip3", + "windows-link", ] [[package]] @@ -407,20 +408,20 @@ dependencies = [ ] [[package]] -name = "wasi" -version = "0.11.1+wasi-snapshot-preview1" +name = "wasip1" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b" +checksum = "b5e26842486624357dbeb8f0381cf1fb42f022291fd787d4a816768fec8cc760" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", ] [[package]] -name = "wasi" -version = "0.14.4+wasi-0.2.4" +name = "wasip2" +version = "1.0.3+wasi-0.2.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "88a5f4a424faf49c3c2c344f166f0662341d470ea185e939657aaff130f0ec4a" +checksum = "20064672db26d7cdc89c7798c48a0fdfac8213434a1186e5ef29fd560ae223d6" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", @@ -428,94 +429,29 @@ dependencies = [ ] [[package]] -name = "windows-link" -version = "0.0.0" - -[[package]] -name = "windows-link" -version = "0.2.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5" - -[[package]] -name = "windows-sys" -version = "0.60.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2f500e4d28234f72040990ec9d39e3a6b950f9f22d3dba18416c35882612bcb" -dependencies = [ - "windows-targets", -] - -[[package]] -name = "windows-targets" -version = "0.53.5" +name = "wasip3" +version = "0.6.0+wasi-0.3.0-rc-2026-03-15" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4945f9f551b88e0d65f3db0bc25c33b8acea4d9e41163edf90dcd0b19f9069f3" +checksum = "ed83456dd6a0b8581998c0365e4651fa2997e5093b49243b7f35391afaa7a3d9" dependencies = [ - "windows-link 0.2.1", - "windows_aarch64_gnullvm", - "windows_aarch64_msvc", - "windows_i686_gnu", - "windows_i686_gnullvm", - "windows_i686_msvc", - "windows_x86_64_gnu", - "windows_x86_64_gnullvm", - "windows_x86_64_msvc", + "rustc-std-workspace-alloc", + "rustc-std-workspace-core", + "wit-bindgen", ] [[package]] -name = "windows_aarch64_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a9d8416fa8b42f5c947f8482c43e7d89e73a173cead56d044f6a56104a6d1b53" - -[[package]] -name = "windows_aarch64_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b9d782e804c2f632e395708e99a94275910eb9100b2114651e04744e9b125006" - -[[package]] -name = "windows_i686_gnu" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "960e6da069d81e09becb0ca57a65220ddff016ff2d6af6a223cf372a506593a3" - -[[package]] -name = "windows_i686_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fa7359d10048f68ab8b09fa71c3daccfb0e9b559aed648a8f95469c27057180c" - -[[package]] -name = "windows_i686_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1e7ac75179f18232fe9c285163565a57ef8d3c89254a30685b57d83a38d326c2" - -[[package]] -name = "windows_x86_64_gnu" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9c3842cdd74a865a8066ab39c8a7a473c0778a3f29370b5fd6b4b9aa7df4a499" - -[[package]] -name = "windows_x86_64_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0ffa179e2d07eee8ad8f57493436566c7cc30ac536a3379fdf008f47f6bb7ae1" +name = "windows-link" +version = "0.0.0" [[package]] -name = "windows_x86_64_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d6bbff5f0aada427a1e5a6da5f1f98158182f26556f345ac9e04d36d0ebed650" +name = "windows-sys" +version = "0.61.100" [[package]] name = "wit-bindgen" -version = "0.45.1" +version = "0.57.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5c573471f125075647d03df72e026074b7203790d41351cd6edc96f46bcccd36" +checksum = "1ebf944e87a7c253233ad6766e082e3cd714b5d03812acc24c318f549614536e" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", diff --git a/Cargo.toml b/Cargo.toml index 87df966bb6b87..788c990c16344 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -85,3 +85,6 @@ rustflags = [ rustc-std-workspace-core = { path = 'rustc-std-workspace-core' } rustc-std-workspace-alloc = { path = 'rustc-std-workspace-alloc' } rustc-std-workspace-std = { path = 'rustc-std-workspace-std' } + +# See comments in `library/windows-sys/Cargo.toml` for why this is patched +windows-sys = { path = 'windows-sys' } diff --git a/alloc/src/alloc.rs b/alloc/src/alloc.rs index 52f099e77255b..8729e98278a82 100644 --- a/alloc/src/alloc.rs +++ b/alloc/src/alloc.rs @@ -204,12 +204,12 @@ impl Global { #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces fn alloc_impl_runtime(layout: Layout, zeroed: bool) -> Result, AllocError> { match layout.size() { - 0 => Ok(NonNull::slice_from_raw_parts(layout.dangling_ptr(), 0)), + 0 => Ok(layout.dangling_ptr().cast_slice(0)), // SAFETY: `layout` is non-zero in size, size => unsafe { let raw_ptr = if zeroed { alloc_zeroed(layout) } else { alloc(layout) }; let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; - Ok(NonNull::slice_from_raw_parts(ptr, size)) + Ok(ptr.cast_slice(size)) }, } } @@ -261,7 +261,7 @@ impl Global { if zeroed { raw_ptr.add(old_size).write_bytes(0, new_size - old_size); } - Ok(NonNull::slice_from_raw_parts(ptr, new_size)) + Ok(ptr.cast_slice(new_size)) }, // SAFETY: because `new_layout.size()` must be greater than or equal to `old_size`, @@ -297,7 +297,7 @@ impl Global { // SAFETY: conditions must be upheld by the caller 0 => unsafe { self.deallocate(ptr, old_layout); - Ok(NonNull::slice_from_raw_parts(new_layout.dangling_ptr(), 0)) + Ok(new_layout.dangling_ptr().cast_slice(0)) }, // SAFETY: `new_size` is non-zero. Other conditions must be upheld by the caller @@ -307,7 +307,7 @@ impl Global { let raw_ptr = realloc_nonnull(ptr, old_layout, new_size); let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; - Ok(NonNull::slice_from_raw_parts(ptr, new_size)) + Ok(ptr.cast_slice(new_size)) }, // SAFETY: because `new_size` must be smaller than or equal to `old_layout.size()`, @@ -388,7 +388,7 @@ impl Global { #[rustc_const_unstable(feature = "const_heap", issue = "79597")] const fn alloc_impl_const(layout: Layout, zeroed: bool) -> Result, AllocError> { match layout.size() { - 0 => Ok(NonNull::slice_from_raw_parts(layout.dangling_ptr(), 0)), + 0 => Ok(layout.dangling_ptr().cast_slice(0)), // SAFETY: `layout` is non-zero in size, size => unsafe { let raw_ptr = core::intrinsics::const_allocate(layout.size(), layout.align()); @@ -397,7 +397,7 @@ impl Global { // SAFETY: the pointer returned by `const_allocate` is valid to write to. ptr.write_bytes(0, size); } - Ok(NonNull::slice_from_raw_parts(ptr, size)) + Ok(ptr.cast_slice(size)) }, } } @@ -442,7 +442,7 @@ impl Global { #[unstable(feature = "allocator_api", issue = "32838")] #[rustc_const_unstable(feature = "const_heap", issue = "79597")] -unsafe impl const Allocator for Global { +const unsafe impl Allocator for Global { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces fn allocate(&self, layout: Layout) -> Result, AllocError> { diff --git a/alloc/src/boxed.rs b/alloc/src/boxed.rs index ae16a8401552d..bd3f10a16dd9b 100644 --- a/alloc/src/boxed.rs +++ b/alloc/src/boxed.rs @@ -695,6 +695,15 @@ impl Box { /// does the same as [Box::into_pin]\([Box::new_in]\(x, alloc)). Consider using /// [`into_pin`](Box::into_pin) if you already have a `Box`, or if you want to /// construct a (pinned) `Box` in a different way than with [`Box::new_in`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(allocator_api)] + /// use std::alloc::System; + /// + /// let x = Box::pin_in(1, System); + /// ``` #[cfg(not(no_global_oom_handling))] #[unstable(feature = "allocator_api", issue = "32838")] #[must_use] @@ -997,26 +1006,6 @@ impl Box<[T]> { }; unsafe { Ok(RawVec::from_raw_parts_in(ptr.as_ptr(), len, Global).into_box(len)) } } - - /// Converts the boxed slice into a boxed array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *mut [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Box::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Box<[T], A> { @@ -1148,6 +1137,38 @@ impl Box<[T], A> { }; unsafe { Ok(RawVec::from_raw_parts_in(ptr.as_ptr(), len, alloc).into_box(len)) } } + + /// Converts the boxed slice into a boxed array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// # Errors + /// + /// Returns the original `Box<[T]>` in the `Err` variant if `self.len()` does not equal `N`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// let box_slice: Box<[i32]> = Box::new([1, 2, 3]); + /// + /// let box_array: Box<[i32; 3]> = box_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Result, Self> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *mut [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Box::from_raw_in(ptr, alloc) }; + Ok(me) + } else { + Err(self) + } + } } impl Box, A> { @@ -1268,6 +1289,7 @@ impl Box { /// The raw pointer must point to a block of memory allocated by the global allocator. /// /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. /// /// # Examples /// @@ -1293,6 +1315,7 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[stable(feature = "box_raw", since = "1.4.0")] #[inline] #[must_use = "call `drop(Box::from_raw(ptr))` if you intend to drop the `Box`"] @@ -1317,6 +1340,7 @@ impl Box { /// The non-null pointer must point to a block of memory allocated by the global allocator. /// /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. /// /// # Examples /// @@ -1347,6 +1371,7 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[unstable(feature = "box_vec_non_null", issue = "130364")] #[inline] #[must_use = "call `drop(Box::from_non_null(ptr))` if you intend to drop the `Box`"] @@ -1407,9 +1432,13 @@ impl Box { pub fn into_raw(b: Self) -> *mut T { // Avoid `into_raw_with_allocator` as that interacts poorly with Miri's Stacked Borrows. let mut b = mem::ManuallyDrop::new(b); - // We go through the built-in deref for `Box`, which is crucial for Miri to recognize this - // operation for it's alias tracking. - &raw mut **b + // We need to give Miri (specifically, Stacked Borrows) a chance to recognize this as a + // safe-to-raw-pointer cast. To achieve this, we first create a mutable reference, and then + // cast that to a raw pointer -- this cast is recognized by the aliasing model and leads to + // a suitable retag. + // It would be wrong for `into_raw_with_allocator` to do the same as that would induce + // uniqueness assumptions (from the `&mut`) that we only want with the default allocator. + (&mut **b) as *mut T } /// Consumes the `Box`, returning a wrapped `NonNull` pointer. @@ -1490,6 +1519,9 @@ impl Box { /// /// The raw pointer must point to a block of memory allocated by `alloc`. /// + /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. + /// /// # Examples /// /// Recreate a `Box` which was previously converted to a raw pointer @@ -1521,6 +1553,7 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[unstable(feature = "allocator_api", issue = "32838")] #[inline] pub unsafe fn from_raw_in(raw: *mut T, alloc: A) -> Self { @@ -1543,6 +1576,9 @@ impl Box { /// /// The non-null pointer must point to a block of memory allocated by `alloc`. /// + /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. + /// /// # Examples /// /// Recreate a `Box` which was previously converted to a `NonNull` pointer @@ -1573,6 +1609,7 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[unstable(feature = "allocator_api", issue = "32838")] // #[unstable(feature = "box_vec_non_null", issue = "130364")] #[inline] diff --git a/alloc/src/boxed/thin.rs b/alloc/src/boxed/thin.rs index 2a34537f58e31..22c3d89e3ccdb 100644 --- a/alloc/src/boxed/thin.rs +++ b/alloc/src/boxed/thin.rs @@ -10,7 +10,8 @@ use core::marker::PhantomData; #[cfg(not(no_global_oom_handling))] use core::marker::Unsize; #[cfg(not(no_global_oom_handling))] -use core::mem::{self, SizedTypeProperties}; +use core::mem; +use core::mem::SizedTypeProperties; use core::ops::{Deref, DerefMut}; use core::ptr::{self, NonNull, Pointee}; @@ -112,7 +113,7 @@ impl ThinBox { where T: Unsize, { - if size_of::() == 0 { + if T::IS_ZST { let ptr = WithOpaqueHeader::new_unsize_zst::(value); ThinBox { ptr, _marker: PhantomData } } else { @@ -281,7 +282,7 @@ impl WithHeader { let ptr = if layout.size() == 0 { // Some paranoia checking, mostly so that the ThinBox tests are // more able to catch issues. - debug_assert!(value_offset == 0 && size_of::() == 0 && size_of::() == 0); + debug_assert!(value_offset == 0 && T::IS_ZST && H::IS_ZST); layout.dangling_ptr() } else { let ptr = alloc::alloc(layout); @@ -311,7 +312,7 @@ impl WithHeader { Dyn: Pointee + ?Sized, T: Unsize, { - assert!(size_of::() == 0); + assert!(T::IS_ZST); const fn max(a: usize, b: usize) -> usize { if a > b { a } else { b } diff --git a/alloc/src/collections/binary_heap/mod.rs b/alloc/src/collections/binary_heap/mod.rs index d46b1972b5b00..34de563fe4f33 100644 --- a/alloc/src/collections/binary_heap/mod.rs +++ b/alloc/src/collections/binary_heap/mod.rs @@ -549,8 +549,8 @@ impl BinaryHeap { /// /// use std::alloc::System; /// use std::collections::BinaryHeap; - /// let mut heap = BinaryHeap::new_in(System); - /// heap.push(4); + /// + /// let heap : BinaryHeap = BinaryHeap::new_in(System); /// ``` #[unstable(feature = "allocator_api", issue = "32838")] #[must_use] @@ -573,8 +573,8 @@ impl BinaryHeap { /// /// use std::alloc::System; /// use std::collections::BinaryHeap; - /// let mut heap = BinaryHeap::with_capacity_in(10, System); - /// heap.push(4); + /// + /// let heap: BinaryHeap = BinaryHeap::with_capacity_in(10, System); /// ``` #[unstable(feature = "allocator_api", issue = "32838")] #[must_use] diff --git a/alloc/src/collections/btree/map.rs b/alloc/src/collections/btree/map.rs index e3a6e90566f5e..7d994359ed48b 100644 --- a/alloc/src/collections/btree/map.rs +++ b/alloc/src/collections/btree/map.rs @@ -684,13 +684,11 @@ impl BTreeMap { /// ``` /// # #![feature(allocator_api)] /// # #![feature(btreemap_alloc)] + /// /// use std::collections::BTreeMap; /// use std::alloc::Global; /// - /// let mut map = BTreeMap::new_in(Global); - /// - /// // entries can now be inserted into the empty map - /// map.insert(1, "a"); + /// let map: BTreeMap = BTreeMap::new_in(Global); /// ``` #[unstable(feature = "btreemap_alloc", issue = "32838")] #[must_use] @@ -1061,7 +1059,7 @@ impl BTreeMap { /// a mutable reference to the value in the entry. /// /// If the map already had this key present, nothing is updated, and - /// an error containing the occupied entry and the value is returned. + /// an error containing the occupied entry, key, and the value is returned. /// /// # Examples /// @@ -1076,6 +1074,7 @@ impl BTreeMap { /// let err = map.try_insert(37, "b").unwrap_err(); /// assert_eq!(err.entry.key(), &37); /// assert_eq!(err.entry.get(), &"a"); + /// assert_eq!(err.key, 37); /// assert_eq!(err.value, "b"); /// ``` #[unstable(feature = "map_try_insert", issue = "82766")] @@ -1083,10 +1082,30 @@ impl BTreeMap { where K: Ord, { - match self.entry(key) { - Occupied(entry) => Err(OccupiedError { entry, value }), - Vacant(entry) => Ok(entry.insert(value)), - } + let (map, dormant_map) = DormantMutRef::new(self); + let handle = match map.root { + Some(ref mut root) => match root.borrow_mut().search_tree(&key) { + Found(handle) => { + let entry = OccupiedEntry { + handle, + dormant_map, + alloc: (*map.alloc).clone(), + _marker: PhantomData, + }; + return Err(OccupiedError { entry, key, value }); + } + GoDown(handle) => Some(handle), + }, + None => None, + }; + let entry = VacantEntry { + key, + handle, + dormant_map, + alloc: (*map.alloc).clone(), + _marker: PhantomData, + }; + Ok(entry.insert(value)) } /// Removes a key from the map, returning the value at the key if the key diff --git a/alloc/src/collections/btree/map/entry.rs b/alloc/src/collections/btree/map/entry.rs index add8782a9499a..b99fbb5e84bd6 100644 --- a/alloc/src/collections/btree/map/entry.rs +++ b/alloc/src/collections/btree/map/entry.rs @@ -97,8 +97,9 @@ impl Debug for OccupiedEntry<'_, /// The error returned by [`try_insert`](BTreeMap::try_insert) when the key already exists. /// -/// Contains the occupied entry, and the value that was not inserted. +/// Contains the occupied entry, key, and the value that was not inserted. #[unstable(feature = "map_try_insert", issue = "82766")] +#[non_exhaustive] pub struct OccupiedError< 'a, K: 'a, @@ -107,6 +108,8 @@ pub struct OccupiedError< > { /// The entry in the map that was already occupied. pub entry: OccupiedEntry<'a, K, V, A>, + /// The key which was not inserted, because the entry was already occupied. + pub key: K, /// The value which was not inserted, because the entry was already occupied. pub value: V, } @@ -116,33 +119,13 @@ impl Debug for OccupiedError<'_, fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("OccupiedError") .field("key", self.entry.key()) + .field("uninserted_key", &self.key) .field("old_value", self.entry.get()) .field("new_value", &self.value) .finish() } } -#[unstable(feature = "map_try_insert", issue = "82766")] -impl<'a, K: Debug + Ord, V: Debug, A: Allocator + Clone> fmt::Display - for OccupiedError<'a, K, V, A> -{ - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - write!( - f, - "failed to insert {:?}, key {:?} already exists with value {:?}", - self.value, - self.entry.key(), - self.entry.get(), - ) - } -} - -#[unstable(feature = "map_try_insert", issue = "82766")] -impl<'a, K: core::fmt::Debug + Ord, V: core::fmt::Debug> core::error::Error - for crate::collections::btree_map::OccupiedError<'a, K, V> -{ -} - impl<'a, K: Ord, V, A: Allocator + Clone> Entry<'a, K, V, A> { /// Ensures a value is in the entry by inserting the default if empty, and returns /// a mutable reference to the value in the entry. diff --git a/alloc/src/collections/btree/set.rs b/alloc/src/collections/btree/set.rs index db8007834432c..2a483b3d3982e 100644 --- a/alloc/src/collections/btree/set.rs +++ b/alloc/src/collections/btree/set.rs @@ -355,10 +355,11 @@ impl BTreeSet { /// # #![allow(unused_mut)] /// # #![feature(allocator_api)] /// # #![feature(btreemap_alloc)] + /// /// use std::collections::BTreeSet; /// use std::alloc::Global; /// - /// let mut set: BTreeSet = BTreeSet::new_in(Global); + /// let set: BTreeSet = BTreeSet::new_in(Global); /// ``` #[unstable(feature = "btreemap_alloc", issue = "32838")] #[must_use] diff --git a/alloc/src/collections/linked_list.rs b/alloc/src/collections/linked_list.rs index 1816349e45f4f..ca3b2eab30402 100644 --- a/alloc/src/collections/linked_list.rs +++ b/alloc/src/collections/linked_list.rs @@ -509,7 +509,7 @@ impl LinkedList { /// use std::alloc::System; /// use std::collections::LinkedList; /// - /// let list: LinkedList = LinkedList::new_in(System); + /// let list: LinkedList = LinkedList::new_in(System); /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] diff --git a/alloc/src/collections/mod.rs b/alloc/src/collections/mod.rs index d306d2016ea28..2cc6b8e894664 100644 --- a/alloc/src/collections/mod.rs +++ b/alloc/src/collections/mod.rs @@ -19,6 +19,7 @@ pub mod vec_deque; pub mod btree_map { //! An ordered map based on a B-Tree. #[stable(feature = "rust1", since = "1.0.0")] + #[cfg(not(test))] pub use super::btree::map::*; } @@ -128,7 +129,7 @@ pub enum TryReserveErrorKind { )] #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[cfg(not(test))] -impl const Clone for TryReserveErrorKind { +const impl Clone for TryReserveErrorKind { fn clone(&self) -> Self { match self { TryReserveErrorKind::CapacityOverflow => TryReserveErrorKind::CapacityOverflow, @@ -149,7 +150,7 @@ pub use realalloc::collections::TryReserveErrorKind; )] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[cfg(not(test))] -impl const From for TryReserveError { +const impl From for TryReserveError { #[inline] fn from(kind: TryReserveErrorKind) -> Self { Self { kind } @@ -159,7 +160,7 @@ impl const From for TryReserveError { #[unstable(feature = "try_reserve_kind", issue = "48043")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[cfg(not(test))] -impl const From for TryReserveErrorKind { +const impl From for TryReserveErrorKind { /// Always evaluates to [`TryReserveErrorKind::CapacityOverflow`]. #[inline] fn from(_: LayoutError) -> Self { diff --git a/alloc/src/collections/vec_deque/drain.rs b/alloc/src/collections/vec_deque/drain.rs index a43853604a2d2..da4b803c64d56 100644 --- a/alloc/src/collections/vec_deque/drain.rs +++ b/alloc/src/collections/vec_deque/drain.rs @@ -5,6 +5,7 @@ use core::ptr::NonNull; use core::{fmt, ptr}; use super::VecDeque; +use super::index::WrappedIndex; use crate::alloc::{Allocator, Global}; /// A draining iterator over the elements of a `VecDeque`. @@ -203,11 +204,11 @@ impl Drop for Drain<'_, T, A> { let (src, dst, len); if head_len < tail_len { src = source_deque.head; - dst = source_deque.to_physical_idx(drain_len); + dst = source_deque.to_wrapped_index(drain_len); len = head_len; } else { - src = source_deque.to_physical_idx(head_len + drain_len); - dst = source_deque.to_physical_idx(head_len); + src = source_deque.to_wrapped_index(head_len + drain_len); + dst = source_deque.to_wrapped_index(head_len); len = tail_len; }; @@ -220,10 +221,10 @@ impl Drop for Drain<'_, T, A> { if new_len == 0 { // Special case: If the entire deque was drained, reset the head back to 0, // like `.clear()` does. - source_deque.head = 0; + source_deque.head = WrappedIndex::zero(); } else if head_len < tail_len { // If we moved the head above, then we need to adjust the head index here. - source_deque.head = source_deque.to_physical_idx(drain_len); + source_deque.head = source_deque.to_wrapped_index(drain_len); } source_deque.len = new_len; } @@ -240,7 +241,7 @@ impl Iterator for Drain<'_, T, A> { if self.remaining == 0 { return None; } - let wrapped_idx = unsafe { self.deque.as_ref().to_physical_idx(self.idx) }; + let wrapped_idx = unsafe { self.deque.as_ref().to_wrapped_index(self.idx) }; self.idx += 1; self.remaining -= 1; Some(unsafe { self.deque.as_mut().buffer_read(wrapped_idx) }) @@ -261,7 +262,8 @@ impl DoubleEndedIterator for Drain<'_, T, A> { return None; } self.remaining -= 1; - let wrapped_idx = unsafe { self.deque.as_ref().to_physical_idx(self.idx + self.remaining) }; + let wrapped_idx = + unsafe { self.deque.as_ref().to_wrapped_index(self.idx + self.remaining) }; Some(unsafe { self.deque.as_mut().buffer_read(wrapped_idx) }) } } diff --git a/alloc/src/collections/vec_deque/extract_if.rs b/alloc/src/collections/vec_deque/extract_if.rs index 437f0d6dd5eb3..19439dfb4f05d 100644 --- a/alloc/src/collections/vec_deque/extract_if.rs +++ b/alloc/src/collections/vec_deque/extract_if.rs @@ -83,8 +83,8 @@ where // // Note: we can't use `vec.get_mut(i).unwrap()` here since the precondition for that // function is that i < vec.len, but we've set vec's length to zero. - let idx = self.vec.to_physical_idx(i); - let cur = unsafe { &mut *self.vec.ptr().add(idx) }; + let idx = self.vec.to_wrapped_index(i); + let cur = unsafe { &mut *self.vec.ptr().add(idx.as_index()) }; let drained = (self.pred)(cur); // Update the index *after* the predicate is called. If the index // is updated prior and the predicate panics, the element at this @@ -95,7 +95,7 @@ where // SAFETY: We never touch this element again after returning it. return Some(unsafe { ptr::read(cur) }); } else if self.del > 0 { - let hole_slot = self.vec.to_physical_idx(i - self.del); + let hole_slot = self.vec.to_wrapped_index(i - self.del); // SAFETY: `self.del` > 0, so the hole slot must not overlap with current element. // We use copy for move, and never touch this element again. unsafe { self.vec.wrap_copy(idx, hole_slot, 1) }; @@ -113,8 +113,8 @@ where impl Drop for ExtractIf<'_, T, F, A> { fn drop(&mut self) { if self.del > 0 { - let src = self.vec.to_physical_idx(self.idx); - let dst = self.vec.to_physical_idx(self.idx - self.del); + let src = self.vec.to_wrapped_index(self.idx); + let dst = self.vec.to_wrapped_index(self.idx - self.del); let len = self.old_len - self.idx; // SAFETY: Trailing unchecked items must be valid since we never touch them. unsafe { self.vec.wrap_copy(src, dst, len) }; @@ -131,7 +131,7 @@ where { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { let peek = if self.idx < self.end { - let idx = self.vec.to_physical_idx(self.idx); + let idx = self.vec.to_wrapped_index(self.idx); // This has to use pointer arithmetic as `self.vec[self.idx]` or // `self.vec.get_unchecked(self.idx)` wouldn't work since we // temporarily set the length of `self.vec` to zero. @@ -141,7 +141,7 @@ where // smaller than `self.old_len`, `idx` is valid for indexing the // buffer. Also, per the invariant of `self.idx`, this element // has not been inspected/moved out yet. - Some(unsafe { &*self.vec.ptr().add(idx) }) + Some(unsafe { &*self.vec.ptr().add(idx.as_index()) }) } else { None }; diff --git a/alloc/src/collections/vec_deque/into_iter.rs b/alloc/src/collections/vec_deque/into_iter.rs index 2b09a5e7ddc58..e18b85dd4b694 100644 --- a/alloc/src/collections/vec_deque/into_iter.rs +++ b/alloc/src/collections/vec_deque/into_iter.rs @@ -5,6 +5,7 @@ use core::ops::Try; use core::{array, fmt, ptr}; use super::VecDeque; +use super::index::WrappedIndex; use crate::alloc::{Allocator, Global}; /// An owning iterator over the elements of a `VecDeque`. @@ -86,7 +87,7 @@ impl Iterator for IntoIter { impl<'a, T, A: Allocator> Drop for Guard<'a, T, A> { fn drop(&mut self) { self.deque.len -= self.consumed; - self.deque.head = self.deque.to_physical_idx(self.consumed); + self.deque.head = self.deque.to_wrapped_index(self.consumed); } } @@ -140,7 +141,7 @@ impl Iterator for IntoIter { // SAFETY: By manually adjusting the head and length of the deque, we effectively // make it forget the first `N` elements, so taking ownership of them is safe. unsafe { ptr::copy_nonoverlapping(head.as_ptr(), raw_arr_ptr, N) }; - self.inner.head = self.inner.to_physical_idx(N); + self.inner.head = self.inner.to_wrapped_index(N); self.inner.len -= N; // SAFETY: We initialized the entire array with items from `head` return Ok(unsafe { raw_arr.transpose().assume_init() }); @@ -155,7 +156,7 @@ impl Iterator for IntoIter { unsafe { ptr::copy_nonoverlapping(tail.as_ptr(), raw_arr_ptr.add(head.len()), remaining) }; - self.inner.head = self.inner.to_physical_idx(N); + self.inner.head = self.inner.to_wrapped_index(N); self.inner.len -= N; // SAFETY: We initialized the entire array with items from `head` and `tail` Ok(unsafe { raw_arr.transpose().assume_init() }) @@ -166,7 +167,7 @@ impl Iterator for IntoIter { }; let init = head.len() + tail.len(); // We completely drained all the deques elements. - self.inner.head = 0; + self.inner.head = WrappedIndex::zero(); self.inner.len = 0; // SAFETY: We copied all elements from both slices to the beginning of the array, so // the given range is initialized. diff --git a/alloc/src/collections/vec_deque/mod.rs b/alloc/src/collections/vec_deque/mod.rs index 3185fd56d8c08..5a900db9d1ce8 100644 --- a/alloc/src/collections/vec_deque/mod.rs +++ b/alloc/src/collections/vec_deque/mod.rs @@ -107,7 +107,7 @@ pub struct VecDeque< > { // `self[0]`, if it exists, is `buf[head]`. // `head < buf.capacity()`, unless `buf.capacity() == 0` when `head == 0`. - head: usize, + head: WrappedIndex, // the number of initialized elements, starting from the one at `head` and potentially wrapping around. // if `len == 0`, the exact value of `head` is unimportant. // if `T` is zero-Sized, then `self.len <= usize::MAX`, otherwise `self.len <= isize::MAX as usize`. @@ -183,7 +183,7 @@ impl VecDeque { unsafe fn push_unchecked(&mut self, element: T) { // SAFETY: Because of the precondition, it's guaranteed that there is space // in the logical array after the last element. - unsafe { self.buffer_write(self.to_physical_idx(self.len), element) }; + unsafe { self.buffer_write(self.to_wrapped_index(self.len), element) }; // This can't overflow because `deque.len() < deque.capacity() <= usize::MAX`. self.len += 1; } @@ -205,8 +205,8 @@ impl VecDeque { /// Moves an element out of the buffer #[inline] - unsafe fn buffer_read(&mut self, off: usize) -> T { - unsafe { ptr::read(self.ptr().add(off)) } + unsafe fn buffer_read(&mut self, off: WrappedIndex) -> T { + unsafe { ptr::read(self.ptr().add(off.as_index())) } } /// Writes an element into the buffer, moving it and returning a pointer to it. @@ -214,9 +214,9 @@ impl VecDeque { /// /// May only be called if `off < self.capacity()`. #[inline] - unsafe fn buffer_write(&mut self, off: usize, value: T) -> &mut T { + unsafe fn buffer_write(&mut self, off: WrappedIndex, value: T) -> &mut T { unsafe { - let ptr = self.ptr().add(off); + let ptr = self.ptr().add(off.as_index()); ptr::write(ptr, value); &mut *ptr } @@ -226,9 +226,7 @@ impl VecDeque { /// `range` must lie inside `0..self.capacity()`. #[inline] unsafe fn buffer_range(&self, range: Range) -> *mut [T] { - unsafe { - ptr::slice_from_raw_parts_mut(self.ptr().add(range.start), range.end - range.start) - } + unsafe { self.ptr().add(range.start).cast_slice(range.end - range.start) } } /// Returns `true` if the buffer is at full capacity. @@ -240,20 +238,23 @@ impl VecDeque { /// Returns the index in the underlying buffer for a given logical element /// index + addend. #[inline] - fn wrap_add(&self, idx: usize, addend: usize) -> usize { - wrap_index(idx.wrapping_add(addend), self.capacity()) + fn wrap_add(&self, idx: WrappedIndex, addend: usize) -> WrappedIndex { + wrap_index(idx.as_index().wrapping_add(addend), self.capacity()) } #[inline] - fn to_physical_idx(&self, idx: usize) -> usize { + fn to_wrapped_index(&self, idx: usize) -> WrappedIndex { self.wrap_add(self.head, idx) } /// Returns the index in the underlying buffer for a given logical element /// index - subtrahend. #[inline] - fn wrap_sub(&self, idx: usize, subtrahend: usize) -> usize { - wrap_index(idx.wrapping_sub(subtrahend).wrapping_add(self.capacity()), self.capacity()) + fn wrap_sub(&self, idx: WrappedIndex, subtrahend: usize) -> WrappedIndex { + wrap_index( + idx.as_index().wrapping_sub(subtrahend).wrapping_add(self.capacity()), + self.capacity(), + ) } /// Get source, destination and count (like the arguments to [`ptr::copy_nonoverlapping`]) @@ -273,7 +274,7 @@ impl VecDeque { src: usize, dst: usize, count: usize, - head: usize, + head: WrappedIndex, ) -> [(*const T, *mut T, usize); 2] { // "`src` and `dst` must be at least as far apart as `count`" debug_assert!( @@ -289,8 +290,8 @@ impl VecDeque { let wrapped_src = self.wrap_add(head, src); let wrapped_dst = self.wrap_add(head, dst); - let room_after_src = self.capacity() - wrapped_src; - let room_after_dst = self.capacity() - wrapped_dst; + let room_after_src = self.capacity() - wrapped_src.as_index(); + let room_after_dst = self.capacity() - wrapped_dst.as_index(); let src_wraps = room_after_src < count; let dst_wraps = room_after_dst < count; @@ -305,8 +306,8 @@ impl VecDeque { unsafe { let ptr = self.ptr(); - let src_ptr = ptr.add(wrapped_src); - let dst_ptr = ptr.add(wrapped_dst); + let src_ptr = ptr.add(wrapped_src.as_index()); + let dst_ptr = ptr.add(wrapped_dst.as_index()); if src_wraps { [ @@ -330,7 +331,7 @@ impl VecDeque { /// Copies a contiguous block of memory len long from src to dst #[inline] - unsafe fn copy(&mut self, src: usize, dst: usize, len: usize) { + unsafe fn copy(&mut self, src: WrappedIndex, dst: WrappedIndex, len: usize) { debug_assert!( dst + len <= self.capacity(), "cpy dst={} src={} len={} cap={}", @@ -348,13 +349,13 @@ impl VecDeque { self.capacity() ); unsafe { - ptr::copy(self.ptr().add(src), self.ptr().add(dst), len); + ptr::copy(self.ptr().add(src.as_index()), self.ptr().add(dst.as_index()), len); } } /// Copies a contiguous block of memory len long from src to dst #[inline] - unsafe fn copy_nonoverlapping(&mut self, src: usize, dst: usize, len: usize) { + unsafe fn copy_nonoverlapping(&mut self, src: WrappedIndex, dst: WrappedIndex, len: usize) { debug_assert!( dst + len <= self.capacity(), "cno dst={} src={} len={} cap={}", @@ -372,14 +373,18 @@ impl VecDeque { self.capacity() ); unsafe { - ptr::copy_nonoverlapping(self.ptr().add(src), self.ptr().add(dst), len); + ptr::copy_nonoverlapping( + self.ptr().add(src.as_index()), + self.ptr().add(dst.as_index()), + len, + ); } } /// Copies a potentially wrapping block of memory len long from src to dest. /// (abs(dst - src) + len) must be no larger than capacity() (There must be at /// most one continuous overlapping region between src and dest). - unsafe fn wrap_copy(&mut self, src: usize, dst: usize, len: usize) { + unsafe fn wrap_copy(&mut self, src: WrappedIndex, dst: WrappedIndex, len: usize) { debug_assert!( cmp::min(src.abs_diff(dst), self.capacity() - src.abs_diff(dst)) + len <= self.capacity(), @@ -395,10 +400,10 @@ impl VecDeque { return; } - let dst_after_src = self.wrap_sub(dst, src) < len; + let dst_after_src = self.wrap_sub(dst, src.as_index()) < len; - let src_pre_wrap_len = self.capacity() - src; - let dst_pre_wrap_len = self.capacity() - dst; + let src_pre_wrap_len = self.capacity() - src.as_index(); + let dst_pre_wrap_len = self.capacity() - dst.as_index(); let src_wraps = src_pre_wrap_len < len; let dst_wraps = dst_pre_wrap_len < len; @@ -426,7 +431,11 @@ impl VecDeque { // unsafe { self.copy(src, dst, dst_pre_wrap_len); - self.copy(src + dst_pre_wrap_len, 0, len - dst_pre_wrap_len); + self.copy( + src.add(dst_pre_wrap_len), + WrappedIndex::zero(), + len - dst_pre_wrap_len, + ); } } (true, false, true) => { @@ -439,7 +448,11 @@ impl VecDeque { // . . D . // unsafe { - self.copy(src + dst_pre_wrap_len, 0, len - dst_pre_wrap_len); + self.copy( + src.add(dst_pre_wrap_len), + WrappedIndex::zero(), + len - dst_pre_wrap_len, + ); self.copy(src, dst, dst_pre_wrap_len); } } @@ -454,7 +467,11 @@ impl VecDeque { // unsafe { self.copy(src, dst, src_pre_wrap_len); - self.copy(0, dst + src_pre_wrap_len, len - src_pre_wrap_len); + self.copy( + WrappedIndex::zero(), + dst.add(src_pre_wrap_len), + len - src_pre_wrap_len, + ); } } (true, true, false) => { @@ -467,7 +484,11 @@ impl VecDeque { // D . . . // unsafe { - self.copy(0, dst + src_pre_wrap_len, len - src_pre_wrap_len); + self.copy( + WrappedIndex::zero(), + dst.add(src_pre_wrap_len), + len - src_pre_wrap_len, + ); self.copy(src, dst, src_pre_wrap_len); } } @@ -485,8 +506,12 @@ impl VecDeque { let delta = dst_pre_wrap_len - src_pre_wrap_len; unsafe { self.copy(src, dst, src_pre_wrap_len); - self.copy(0, dst + src_pre_wrap_len, delta); - self.copy(delta, 0, len - dst_pre_wrap_len); + self.copy(WrappedIndex::zero(), dst.add(src_pre_wrap_len), delta); + self.copy( + WrappedIndex::from_arbitrary_number(delta), + WrappedIndex::zero(), + len - dst_pre_wrap_len, + ); } } (true, true, true) => { @@ -502,8 +527,16 @@ impl VecDeque { debug_assert!(src_pre_wrap_len > dst_pre_wrap_len); let delta = src_pre_wrap_len - dst_pre_wrap_len; unsafe { - self.copy(0, delta, len - src_pre_wrap_len); - self.copy(self.capacity() - delta, 0, delta); + self.copy( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(delta), + len - src_pre_wrap_len, + ); + self.copy( + WrappedIndex::from_arbitrary_number(self.capacity() - delta), + WrappedIndex::zero(), + delta, + ); self.copy(src, dst, dst_pre_wrap_len); } } @@ -513,17 +546,17 @@ impl VecDeque { /// Copies all values from `src` to `dst`, wrapping around if needed. /// Assumes capacity is sufficient. #[inline] - unsafe fn copy_slice(&mut self, dst: usize, src: &[T]) { + unsafe fn copy_slice(&mut self, dst: WrappedIndex, src: &[T]) { debug_assert!(src.len() <= self.capacity()); - let head_room = self.capacity() - dst; + let head_room = self.capacity() - dst.as_index(); if src.len() <= head_room { unsafe { - ptr::copy_nonoverlapping(src.as_ptr(), self.ptr().add(dst), src.len()); + ptr::copy_nonoverlapping(src.as_ptr(), self.ptr().add(dst.as_index()), src.len()); } } else { let (left, right) = src.split_at(head_room); unsafe { - ptr::copy_nonoverlapping(left.as_ptr(), self.ptr().add(dst), left.len()); + ptr::copy_nonoverlapping(left.as_ptr(), self.ptr().add(dst.as_index()), left.len()); ptr::copy_nonoverlapping(right.as_ptr(), self.ptr(), right.len()); } } @@ -533,7 +566,7 @@ impl VecDeque { /// Assumes capacity is sufficient. /// Equivalent to calling [`VecDeque::copy_slice`] with a [reversed](https://doc.rust-lang.org/std/primitive.slice.html#method.reverse) slice. #[inline] - unsafe fn copy_slice_reversed(&mut self, dst: usize, src: &[T]) { + unsafe fn copy_slice_reversed(&mut self, dst: WrappedIndex, src: &[T]) { /// # Safety /// /// See [`ptr::copy_nonoverlapping`]. @@ -544,15 +577,23 @@ impl VecDeque { } debug_assert!(src.len() <= self.capacity()); - let head_room = self.capacity() - dst; + let head_room = self.capacity() - dst.as_index(); if src.len() <= head_room { unsafe { - copy_nonoverlapping_reversed(src.as_ptr(), self.ptr().add(dst), src.len()); + copy_nonoverlapping_reversed( + src.as_ptr(), + self.ptr().add(dst.as_index()), + src.len(), + ); } } else { let (left, right) = src.split_at(src.len() - head_room); unsafe { - copy_nonoverlapping_reversed(right.as_ptr(), self.ptr().add(dst), right.len()); + copy_nonoverlapping_reversed( + right.as_ptr(), + self.ptr().add(dst.as_index()), + right.len(), + ); copy_nonoverlapping_reversed(left.as_ptr(), self.ptr(), left.len()); } } @@ -567,12 +608,12 @@ impl VecDeque { #[inline] unsafe fn write_iter( &mut self, - dst: usize, + dst: WrappedIndex, iter: impl Iterator, written: &mut usize, ) { iter.enumerate().for_each(|(i, element)| unsafe { - self.buffer_write(dst + i, element); + self.buffer_write(dst.add(i), element); *written += 1; }); } @@ -587,7 +628,7 @@ impl VecDeque { /// Assumes capacity is sufficient. unsafe fn write_iter_wrapping( &mut self, - dst: usize, + dst: WrappedIndex, mut iter: impl Iterator, len: usize, ) -> usize { @@ -602,7 +643,7 @@ impl VecDeque { } } - let head_room = self.capacity() - dst; + let head_room = self.capacity() - dst.as_index(); let mut guard = Guard { deque: self, written: 0 }; @@ -615,7 +656,7 @@ impl VecDeque { ByRefSized(&mut iter).take(head_room), &mut guard.written, ); - guard.deque.write_iter(0, iter, &mut guard.written) + guard.deque.write_iter(WrappedIndex::zero(), iter, &mut guard.written) }; } @@ -652,16 +693,20 @@ impl VecDeque { // A // Nop } else { - let head_len = old_capacity - self.head; + let head_len = old_capacity - self.head.as_index(); let tail_len = self.len - head_len; if head_len > tail_len && new_capacity - old_capacity >= tail_len { // B unsafe { - self.copy_nonoverlapping(0, old_capacity, tail_len); + self.copy_nonoverlapping( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(old_capacity), + tail_len, + ); } } else { // C - let new_head = new_capacity - head_len; + let new_head = WrappedIndex::from_arbitrary_number(new_capacity - head_len); unsafe { // can't use copy_nonoverlapping here, because if e.g. head_len = 2 // and new_capacity = old_capacity + 1, then the heads overlap. @@ -780,7 +825,7 @@ impl VecDeque { #[must_use] pub const fn new() -> VecDeque { // FIXME(const-hack): This should just be `VecDeque::new_in(Global)` once that hits stable. - VecDeque { head: 0, len: 0, buf: RawVec::new() } + VecDeque { head: WrappedIndex::zero(), len: 0, buf: RawVec::new() } } /// Creates an empty deque with space for at least `capacity` elements. @@ -790,7 +835,7 @@ impl VecDeque { /// ``` /// use std::collections::VecDeque; /// - /// let deque: VecDeque = VecDeque::with_capacity(10); + /// let deque: VecDeque = VecDeque::with_capacity(10); /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] @@ -820,7 +865,11 @@ impl VecDeque { #[inline] #[unstable(feature = "try_with_capacity", issue = "91913")] pub fn try_with_capacity(capacity: usize) -> Result, TryReserveError> { - Ok(VecDeque { head: 0, len: 0, buf: RawVec::try_with_capacity_in(capacity, Global)? }) + Ok(VecDeque { + head: WrappedIndex::zero(), + len: 0, + buf: RawVec::try_with_capacity_in(capacity, Global)?, + }) } } @@ -830,14 +879,17 @@ impl VecDeque { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] + /// /// use std::collections::VecDeque; + /// use std::alloc::Global; /// - /// let deque: VecDeque = VecDeque::new(); + /// let deque: VecDeque = VecDeque::new_in(Global); /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] pub const fn new_in(alloc: A) -> VecDeque { - VecDeque { head: 0, len: 0, buf: RawVec::new_in(alloc) } + VecDeque { head: WrappedIndex::zero(), len: 0, buf: RawVec::new_in(alloc) } } /// Creates an empty deque with space for at least `capacity` elements. @@ -845,13 +897,20 @@ impl VecDeque { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] + /// /// use std::collections::VecDeque; + /// use std::alloc::Global; /// - /// let deque: VecDeque = VecDeque::with_capacity(10); + /// let deque: VecDeque = VecDeque::with_capacity_in(10, Global); /// ``` #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_capacity_in(capacity: usize, alloc: A) -> VecDeque { - VecDeque { head: 0, len: 0, buf: RawVec::with_capacity_in(capacity, alloc) } + VecDeque { + head: WrappedIndex::zero(), + len: 0, + buf: RawVec::with_capacity_in(capacity, alloc), + } } /// Creates a `VecDeque` from a raw allocation, when the initialized @@ -880,7 +939,7 @@ impl VecDeque { // and that the allocation is valid for use in `RawVec`. unsafe { VecDeque { - head: initialized.start, + head: WrappedIndex::from_arbitrary_number(initialized.start), len: initialized.end.unchecked_sub(initialized.start), buf: RawVec::from_raw_parts_in(ptr, capacity, alloc), } @@ -906,8 +965,8 @@ impl VecDeque { #[stable(feature = "rust1", since = "1.0.0")] pub fn get(&self, index: usize) -> Option<&T> { if index < self.len { - let idx = self.to_physical_idx(index); - unsafe { Some(&*self.ptr().add(idx)) } + let idx = self.to_wrapped_index(index); + unsafe { Some(&*self.ptr().add(idx.as_index())) } } else { None } @@ -936,8 +995,8 @@ impl VecDeque { #[stable(feature = "rust1", since = "1.0.0")] pub fn get_mut(&mut self, index: usize) -> Option<&mut T> { if index < self.len { - let idx = self.to_physical_idx(index); - unsafe { Some(&mut *self.ptr().add(idx)) } + let idx = self.to_wrapped_index(index); + unsafe { Some(&mut *self.ptr().add(idx.as_index())) } } else { None } @@ -970,9 +1029,9 @@ impl VecDeque { pub fn swap(&mut self, i: usize, j: usize) { assert!(i < self.len()); assert!(j < self.len()); - let ri = self.to_physical_idx(i); - let rj = self.to_physical_idx(j); - unsafe { ptr::swap(self.ptr().add(ri), self.ptr().add(rj)) } + let ri = self.to_wrapped_index(i); + let rj = self.to_wrapped_index(j); + unsafe { ptr::swap(self.ptr().add(ri.as_index()), self.ptr().add(rj.as_index())) } } /// Returns the number of elements the deque can hold without @@ -1223,8 +1282,8 @@ impl VecDeque { let old_head = self.head; if self.len == 0 { - self.head = 0; - } else if self.head >= target_cap && tail_outside { + self.head = WrappedIndex::zero(); + } else if self.head.as_index() >= target_cap && tail_outside { // Head and tail are both out of bounds, so copy all of them to the front. // // H := head @@ -1235,9 +1294,9 @@ impl VecDeque { // [o o o o o o o . ] unsafe { // nonoverlapping because `self.head >= target_cap >= self.len`. - self.copy_nonoverlapping(self.head, 0, self.len); + self.copy_nonoverlapping(self.head, WrappedIndex::zero(), self.len); } - self.head = 0; + self.head = WrappedIndex::zero(); } else if self.head < target_cap && tail_outside { // Head is in bounds, tail is out of bounds. // Copy the overflowing part to the beginning of the @@ -1250,8 +1309,13 @@ impl VecDeque { // L H // [o o . o o o o o ] let len = self.head + self.len - target_cap; + // Safety: head is < target_cap, so the index is wrapped unsafe { - self.copy_nonoverlapping(target_cap, 0, len); + self.copy_nonoverlapping( + WrappedIndex::from_arbitrary_number(target_cap), + WrappedIndex::zero(), + len, + ); } } else if !self.is_contiguous() { // The head slice is at least partially out of bounds, tail is in bounds. @@ -1264,8 +1328,10 @@ impl VecDeque { // [o o o o o . . . . . . . . . o o ] // L H // [o o o o o . o o ] - let head_len = self.capacity() - self.head; - let new_head = target_cap - head_len; + let head_len = self.capacity() - self.head.as_index(); + + // head_len is at least one, so new_head will be < target_cap + let new_head = WrappedIndex::from_arbitrary_number(target_cap - head_len); unsafe { // can't use `copy_nonoverlapping()` here because the new and old // regions for the head might overlap. @@ -1276,7 +1342,7 @@ impl VecDeque { struct Guard<'a, T, A: Allocator> { deque: &'a mut VecDeque, - old_head: usize, + old_head: WrappedIndex, target_cap: usize, } @@ -1308,7 +1374,7 @@ impl VecDeque { /// /// `old_head` refers to the head index before `shrink_to` was called. `target_cap` /// is the capacity that it was trying to shrink to. - unsafe fn abort_shrink(&mut self, old_head: usize, target_cap: usize) { + unsafe fn abort_shrink(&mut self, old_head: WrappedIndex, target_cap: usize) { // Moral equivalent of self.head + self.len <= target_cap. Won't overflow // because `self.len <= target_cap`. if self.head <= target_cap - self.len { @@ -1317,7 +1383,7 @@ impl VecDeque { } // `shrink_to` already copied the head to fit into the new capacity, so this won't overflow. - let head_len = target_cap - self.head; + let head_len = target_cap - self.head.as_index(); // `self.head > target_cap - self.len` => `self.len > target_cap - self.head =: head_len` so this must be positive. let tail_len = self.len - head_len; @@ -1328,7 +1394,11 @@ impl VecDeque { unsafe { // The old tail and the new tail can't overlap because the head slice lies between them. The // head slice ends at `target_cap`, so that's where we copy to. - self.copy_nonoverlapping(0, target_cap, tail_len); + self.copy_nonoverlapping( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(target_cap), + tail_len, + ); } } else { // Either there's not enough spare capacity to make the deque contiguous, or the head is shorter than the tail @@ -1453,7 +1523,7 @@ impl VecDeque { // and end < front.len() let end = front.len() - (len - back.len()); let drop_front = front.get_unchecked_mut(..end) as *mut _; - self.head += end; + self.head = self.head.add(end); self.len = len; ptr::drop_in_place(drop_front); } else { @@ -1461,7 +1531,7 @@ impl VecDeque { // 'end' is non-negative by the condition above let end = back.len() - len; let drop_back = back.get_unchecked_mut(..end) as *mut _; - self.head = self.to_physical_idx(self.len - len); + self.head = self.to_wrapped_index(self.len - len); self.len = len; // Make sure the second half is dropped even when a destructor @@ -1676,20 +1746,20 @@ impl VecDeque { // `slice::range` guarantees that `start <= end <= len`. // because `len != 0`, we know that `start < end`, so `start < len` // and the indexing is valid. - let wrapped_start = self.to_physical_idx(start); + let wrapped_start = self.to_wrapped_index(start); // this subtraction can never overflow because `wrapped_start` is // at most `self.capacity()` (and if `self.capacity != 0`, then `wrapped_start` is strictly less // than `self.capacity`). - let head_len = self.capacity() - wrapped_start; + let head_len = self.capacity() - wrapped_start.as_index(); if head_len >= len { // we know that `len + wrapped_start <= self.capacity <= usize::MAX`, so this addition can't overflow - (wrapped_start..wrapped_start + len, 0..0) + (wrapped_start.as_index()..wrapped_start + len, 0..0) } else { // can't overflow because of the if condition let tail_len = len - head_len; - (wrapped_start..self.capacity(), 0..tail_len) + (wrapped_start.as_index()..self.capacity(), 0..tail_len) } } } @@ -1920,7 +1990,7 @@ impl VecDeque { pub fn clear(&mut self) { self.truncate(0); // Not strictly necessary, but leaves things in a more consistent/predictable state. - self.head = 0; + self.head = WrappedIndex::zero(); } /// Returns `true` if the deque contains an element equal to the @@ -2066,7 +2136,7 @@ impl VecDeque { None } else { let old_head = self.head; - self.head = self.to_physical_idx(1); + self.head = self.to_wrapped_index(1); self.len -= 1; unsafe { core::hint::assert_unchecked(self.len < self.capacity()); @@ -2097,7 +2167,7 @@ impl VecDeque { self.len -= 1; unsafe { core::hint::assert_unchecked(self.len < self.capacity()); - Some(self.buffer_read(self.to_physical_idx(self.len))) + Some(self.buffer_read(self.to_wrapped_index(self.len))) } } } @@ -2227,7 +2297,7 @@ impl VecDeque { let len = self.len; self.len += 1; - unsafe { self.buffer_write(self.to_physical_idx(len), value) } + unsafe { self.buffer_write(self.to_wrapped_index(len), value) } } /// Prepends all contents of the iterator to the front of the deque. @@ -2441,9 +2511,9 @@ impl VecDeque { // and panicked. unsafe { // see `remove()` for explanation why this wrap_copy() call is safe. - self.wrap_copy(self.to_physical_idx(index), self.to_physical_idx(index + 1), k); + self.wrap_copy(self.to_wrapped_index(index), self.to_wrapped_index(index + 1), k); self.len += 1; - self.buffer_write(self.to_physical_idx(index), value) + self.buffer_write(self.to_wrapped_index(index), value) } } else { let old_head = self.head; @@ -2451,7 +2521,7 @@ impl VecDeque { unsafe { self.wrap_copy(old_head, self.head, index); self.len += 1; - self.buffer_write(self.to_physical_idx(index), value) + self.buffer_write(self.to_wrapped_index(index), value) } } } @@ -2484,7 +2554,7 @@ impl VecDeque { return None; } - let wrapped_idx = self.to_physical_idx(index); + let wrapped_idx = self.to_wrapped_index(index); let elem = unsafe { Some(self.buffer_read(wrapped_idx)) }; @@ -2497,7 +2567,7 @@ impl VecDeque { self.len -= 1; } else { let old_head = self.head; - self.head = self.to_physical_idx(1); + self.head = self.to_wrapped_index(1); unsafe { self.wrap_copy(old_head, self.head, index) }; self.len -= 1; } @@ -2601,23 +2671,23 @@ impl VecDeque { if T::IS_ZST { self.len = self.len.checked_add(other.len).expect("capacity overflow"); other.len = 0; - other.head = 0; + other.head = WrappedIndex::zero(); return; } self.reserve(other.len); unsafe { let (left, right) = other.as_slices(); - self.copy_slice(self.to_physical_idx(self.len), left); + self.copy_slice(self.to_wrapped_index(self.len), left); // no overflow, because self.capacity() >= old_cap + left.len() >= self.len + left.len() - self.copy_slice(self.to_physical_idx(self.len + left.len()), right); + self.copy_slice(self.to_wrapped_index(self.len + left.len()), right); } // SAFETY: Update pointers after copying to avoid leaving doppelganger // in case of panics. self.len += other.len; // Now that we own its values, forget everything in `other`. other.len = 0; - other.head = 0; + other.head = WrappedIndex::zero(); } /// Retains only the elements specified by the predicate. @@ -2825,11 +2895,13 @@ impl VecDeque { #[stable(feature = "deque_make_contiguous", since = "1.48.0")] pub fn make_contiguous(&mut self) -> &mut [T] { if T::IS_ZST { - self.head = 0; + self.head = WrappedIndex::zero(); } if self.is_contiguous() { - unsafe { return slice::from_raw_parts_mut(self.ptr().add(self.head), self.len) } + unsafe { + return slice::from_raw_parts_mut(self.ptr().add(self.head.as_index()), self.len); + } } let &mut Self { head, len, .. } = self; @@ -2837,9 +2909,13 @@ impl VecDeque { let cap = self.capacity(); let free = cap - len; - let head_len = cap - head; - let tail = len - head_len; - let tail_len = tail; + let head_len = cap - head.as_index(); + + // tail <= head < capacity + // head cannot be <= capacity, because we know that VecDeque is non-empty, since it is not + // contiguous at this point + let tail = WrappedIndex::from_arbitrary_number(len - head_len); + let tail_len = tail.as_index(); if free >= head_len { // there is enough free space to copy the head in one go, @@ -2849,13 +2925,17 @@ impl VecDeque { // from: DEFGH....ABC // to: ABCDEFGH.... unsafe { - self.copy(0, head_len, tail_len); + self.copy( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(head_len), + tail_len, + ); // ...DEFGH.ABC - self.copy_nonoverlapping(head, 0, head_len); + self.copy_nonoverlapping(head, WrappedIndex::zero(), head_len); // ABCDEFGH.... } - self.head = 0; + self.head = WrappedIndex::zero(); } else if free >= tail_len { // there is enough free space to copy the tail in one go, // this means that we first shift the head forwards, and then @@ -2866,7 +2946,7 @@ impl VecDeque { unsafe { self.copy(head, tail, head_len); // FGHABCDE.... - self.copy_nonoverlapping(0, tail + head_len, tail_len); + self.copy_nonoverlapping(WrappedIndex::zero(), tail.add(head_len), tail_len); // ...ABCDEFGH. } @@ -2902,7 +2982,11 @@ impl VecDeque { // because we only move the tail forward as much as there's free space // behind it, we don't overwrite any elements of the head slice, and // the slices end up right next to each other. - self.copy(0, free, tail_len); + self.copy( + WrappedIndex::zero(), + WrappedIndex::from_arbitrary_number(free), + tail_len, + ); } // We just copied the tail right next to the head slice, @@ -2915,7 +2999,7 @@ impl VecDeque { // the used part of the buffer now is `free..self.capacity()`, so set // `head` to the beginning of that range. - self.head = free; + self.head = WrappedIndex::from_arbitrary_number(free); } } else { // head is shorter so: @@ -2928,7 +3012,11 @@ impl VecDeque { // right next to each other and we don't need to move any memory. if free != 0 { // copy the head slice to lie right behind the tail slice. - self.copy(self.head, tail_len, head_len); + self.copy( + self.head, + WrappedIndex::from_arbitrary_number(tail_len), + head_len, + ); } // because we copied the head slice so that both slices lie right @@ -2941,12 +3029,12 @@ impl VecDeque { // the used part of the buffer now is `0..self.len`, so set // `head` to the beginning of that range. - self.head = 0; + self.head = WrappedIndex::zero(); } } } - unsafe { slice::from_raw_parts_mut(ptr.add(self.head), self.len) } + unsafe { slice::from_raw_parts_mut(ptr.add(self.head.as_index()), self.len) } } /// Rotates the double-ended queue `n` places to the left. @@ -3046,16 +3134,16 @@ impl VecDeque { unsafe fn rotate_left_inner(&mut self, mid: usize) { debug_assert!(mid * 2 <= self.len()); unsafe { - self.wrap_copy(self.head, self.to_physical_idx(self.len), mid); + self.wrap_copy(self.head, self.to_wrapped_index(self.len), mid); } - self.head = self.to_physical_idx(mid); + self.head = self.to_wrapped_index(mid); } unsafe fn rotate_right_inner(&mut self, k: usize) { debug_assert!(k * 2 <= self.len()); self.head = self.wrap_sub(self.head, k); unsafe { - self.wrap_copy(self.to_physical_idx(self.len), self.head, k); + self.wrap_copy(self.to_wrapped_index(self.len), self.head, k); } } @@ -3456,7 +3544,7 @@ impl SpecExtendFromWithin for VecDeque { let (src, dst, count) = ranges[1]; for offset in (0..count).rev() { dst.add(offset).write((*src.add(offset)).clone()); - self.head -= 1; + self.head = self.head.sub(1); self.len += 1; } @@ -3466,16 +3554,18 @@ impl SpecExtendFromWithin for VecDeque { if let Some(offset) = iter.next() { dst.add(offset).write((*src.add(offset)).clone()); // After the first clone of the second range, wrap `head` around - if self.head == 0 { - self.head = cap; + if self.head.is_zero() { + // SAFETY: the wrapped index may be temporarily equal to the capacity even if it + // is not zero, because we subtract it one line below. + self.head = WrappedIndex::from_arbitrary_number(cap); } - self.head -= 1; + self.head = self.head.sub(1); self.len += 1; // Continue like normal for offset in iter { dst.add(offset).write((*src.add(offset)).clone()); - self.head -= 1; + self.head = self.head.sub(1); self.len += 1; } } @@ -3529,15 +3619,109 @@ impl SpecExtendFromWithin for VecDeque { } } -/// Returns the index in the underlying buffer for a given logical element index. -#[inline] -fn wrap_index(logical_index: usize, capacity: usize) -> usize { - debug_assert!( - (logical_index == 0 && capacity == 0) - || logical_index < capacity - || (logical_index - capacity) < capacity - ); - if logical_index >= capacity { logical_index - capacity } else { logical_index } +use index::{WrappedIndex, wrap_index}; + +// The code is separated into a module to make it harder to construct a BufferIndex without +// going through wrapping. +mod index { + use core::cmp::Ordering; + + /// Returns the index in the underlying buffer for a given logical element index. + #[inline] + pub(super) fn wrap_index(logical_index: usize, capacity: usize) -> WrappedIndex { + debug_assert!( + (logical_index == 0 && capacity == 0) + || logical_index < capacity + || (logical_index - capacity) < capacity + ); + if logical_index >= capacity { + WrappedIndex(logical_index - capacity) + } else { + WrappedIndex(logical_index) + } + } + + /// Represents an index that can be safely used to index the VecDeque buffer. + /// It exists as a separate type to avoid passing logical (unwrapped) indices to various + /// VecDeque functions by accident. + /// + /// The invariant of this index is that it is always < VecDeque capacity, unless the VecDeque + /// is empty (in that case the index can be 0 when the capacity is 0). + #[derive(Copy, Clone, Debug, PartialOrd, Ord, PartialEq, Eq)] + #[repr(transparent)] + pub(super) struct WrappedIndex(usize); + + impl WrappedIndex { + /// The newly constructed index has to be in-bounds for the VecDeque + /// that uses the index. + #[inline(always)] + pub(super) fn from_arbitrary_number(index: usize) -> Self { + Self(index) + } + + /// Safety invariant: the newly constructed index must still be in-bounds for the VecDeque + #[inline(always)] + pub(super) unsafe fn add(self, offset: usize) -> Self { + Self(self.0 + offset) + } + + /// Safety invariant: the newly constructed index must still be in-bounds for the VecDeque + #[inline(always)] + pub(super) unsafe fn sub(self, offset: usize) -> Self { + debug_assert!(self.0 >= offset); + Self(self.0 - offset) + } + + #[inline(always)] + pub(super) const fn zero() -> Self { + Self(0) + } + + #[inline(always)] + pub(super) fn abs_diff(self, other: Self) -> usize { + self.0.abs_diff(other.0) + } + + #[inline(always)] + pub(super) fn as_index(self) -> usize { + self.0 + } + + #[inline(always)] + pub(super) fn is_zero(self) -> bool { + self.0 == 0 + } + } + + impl core::ops::Add for WrappedIndex { + // The output might not be wrapped anymore + type Output = usize; + + #[inline(always)] + fn add(self, rhs: usize) -> Self::Output { + self.0 + rhs + } + } + + impl core::fmt::Display for WrappedIndex { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.0.fmt(f) + } + } + + impl core::cmp::PartialEq for WrappedIndex { + #[inline(always)] + fn eq(&self, other: &usize) -> bool { + self.0.eq(other) + } + } + + impl core::cmp::PartialOrd for WrappedIndex { + #[inline(always)] + fn partial_cmp(&self, other: &usize) -> Option { + self.0.partial_cmp(other) + } + } } #[stable(feature = "rust1", since = "1.0.0")] @@ -3745,7 +3929,11 @@ impl From> for VecDeque { #[inline] fn from(other: Vec) -> Self { let (ptr, len, cap, alloc) = other.into_raw_parts_with_alloc(); - Self { head: 0, len, buf: unsafe { RawVec::from_raw_parts_in(ptr, cap, alloc) } } + Self { + head: WrappedIndex::zero(), + len, + buf: unsafe { RawVec::from_raw_parts_in(ptr, cap, alloc) }, + } } } @@ -3790,8 +3978,8 @@ impl From> for Vec { let cap = other.capacity(); let alloc = ptr::read(other.allocator()); - if other.head != 0 { - ptr::copy(buf.add(other.head), buf, len); + if !other.head.is_zero() { + ptr::copy(buf.add(other.head.as_index()), buf, len); } Vec::from_raw_parts_in(buf, len, cap, alloc) } @@ -3818,7 +4006,7 @@ impl From<[T; N]> for VecDeque { ptr::copy_nonoverlapping(arr.as_ptr(), deq.ptr(), N); } } - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = N; deq } diff --git a/alloc/src/collections/vec_deque/spec_extend.rs b/alloc/src/collections/vec_deque/spec_extend.rs index 184e8b769347d..0699d403d9de5 100644 --- a/alloc/src/collections/vec_deque/spec_extend.rs +++ b/alloc/src/collections/vec_deque/spec_extend.rs @@ -58,7 +58,7 @@ where self.reserve(additional); let written = unsafe { - self.write_iter_wrapping(self.to_physical_idx(self.len), iter, additional) + self.write_iter_wrapping(self.to_wrapped_index(self.len), iter, additional) }; debug_assert_eq!( @@ -78,15 +78,15 @@ where #[cfg(not(test))] impl SpecExtend> for VecDeque { - fn spec_extend(&mut self, mut iterator: vec::IntoIter) { + fn spec_extend(&mut self, iterator: vec::IntoIter) { let slice = iterator.as_slice(); self.reserve(slice.len()); unsafe { - self.copy_slice(self.to_physical_idx(self.len), slice); + self.copy_slice(self.to_wrapped_index(self.len), slice); self.len += slice.len(); } - iterator.forget_remaining_elements(); + iterator.forget_remaining_elements_and_dealloc(); } } @@ -109,7 +109,7 @@ where self.reserve(slice.len()); unsafe { - self.copy_slice(self.to_physical_idx(self.len), slice); + self.copy_slice(self.to_wrapped_index(self.len), slice); self.len += slice.len(); } } @@ -155,12 +155,12 @@ where #[cfg(not(test))] impl SpecExtendFront> for VecDeque { #[track_caller] - fn spec_extend_front(&mut self, mut iterator: vec::IntoIter) { + fn spec_extend_front(&mut self, iterator: vec::IntoIter) { let slice = iterator.as_slice(); self.reserve(slice.len()); // SAFETY: `slice.len()` space was just reserved and elements in the slice are forgotten after this call unsafe { prepend_reversed(self, slice) }; - iterator.forget_remaining_elements(); + iterator.forget_remaining_elements_and_dealloc(); } } @@ -170,12 +170,12 @@ impl SpecExtendFront>) { - let mut iterator = iterator.into_inner(); + let iterator = iterator.into_inner(); let slice = iterator.as_slice(); self.reserve(slice.len()); // SAFETY: `slice.len()` space was just reserved and elements in the slice are forgotten after this call unsafe { prepend(self, slice) }; - iterator.forget_remaining_elements(); + iterator.forget_remaining_elements_and_dealloc(); } } diff --git a/alloc/src/collections/vec_deque/splice.rs b/alloc/src/collections/vec_deque/splice.rs index b82f9fba7ceb3..a29e9c3742564 100644 --- a/alloc/src/collections/vec_deque/splice.rs +++ b/alloc/src/collections/vec_deque/splice.rs @@ -120,7 +120,7 @@ impl Drain<'_, T, A> { for idx in range_start..range_end { if let Some(new_item) = replace_with.next() { - let index = deque.to_physical_idx(idx); + let index = deque.to_wrapped_index(idx); unsafe { deque.buffer_write(index, new_item) }; deque.len += 1; self.drain_len -= 1; @@ -184,8 +184,8 @@ impl Drain<'_, T, A> { let new_tail_start = tail_start + additional; unsafe { deque.wrap_copy( - deque.to_physical_idx(tail_start), - deque.to_physical_idx(new_tail_start), + deque.to_wrapped_index(tail_start), + deque.to_wrapped_index(new_tail_start), self.tail_len, ); } diff --git a/alloc/src/collections/vec_deque/tests.rs b/alloc/src/collections/vec_deque/tests.rs index dc50cc34d9dac..d9cf56de7bb6b 100644 --- a/alloc/src/collections/vec_deque/tests.rs +++ b/alloc/src/collections/vec_deque/tests.rs @@ -12,7 +12,7 @@ fn bench_push_back_100(b: &mut test::Bencher) { for i in 0..100 { deq.push_back(i); } - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = 0; }) } @@ -24,7 +24,7 @@ fn bench_push_front_100(b: &mut test::Bencher) { for i in 0..100 { deq.push_front(i); } - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = 0; }) } @@ -38,7 +38,7 @@ fn bench_pop_back_100(b: &mut test::Bencher) { unsafe { deq.ptr().write_bytes(0u8, size + 1) }; b.iter(|| { - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = 100; while !deq.is_empty() { test::black_box(deq.pop_back()); @@ -88,7 +88,7 @@ fn bench_pop_front_100(b: &mut test::Bencher) { unsafe { deq.ptr().write_bytes(0u8, size + 1) }; b.iter(|| { - deq.head = 0; + deq.head = WrappedIndex::zero(); deq.len = 100; while !deq.is_empty() { test::black_box(deq.pop_front()); @@ -109,7 +109,7 @@ fn test_swap_front_back_remove() { let expected: VecDeque<_> = if back { (0..len).collect() } else { (0..len).rev().collect() }; for head_pos in 0..usable_cap { - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; if back { for i in 0..len * 2 { @@ -127,7 +127,7 @@ fn test_swap_front_back_remove() { assert_eq!(tester.swap_remove_front(idx), Some(len * 2 - 1 - i)); } } - assert!(tester.head <= tester.capacity()); + assert!(tester.head.as_index() <= tester.capacity()); assert!(tester.len <= tester.capacity()); assert_eq!(tester, expected); } @@ -155,7 +155,7 @@ fn test_insert() { let expected = (0..).take(len).collect::>(); for head_pos in 0..cap { for to_insert in 0..len { - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; for i in 0..len { if i != to_insert { @@ -636,7 +636,7 @@ fn test_remove() { let expected = (0..).take(len).collect::>(); for head_pos in 0..cap { for to_remove in 0..=len { - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; for i in 0..len { if i == to_remove { @@ -666,7 +666,7 @@ fn test_range() { for head in 0..=cap { for start in 0..=len { for end in start..=len { - tester.head = head; + tester.head = WrappedIndex::from_arbitrary_number(head); tester.len = 0; for i in 0..len { tester.push_back(i); @@ -691,7 +691,7 @@ fn test_range_mut() { for head in 0..=cap { for start in 0..=len { for end in start..=len { - tester.head = head; + tester.head = WrappedIndex::from_arbitrary_number(head); tester.len = 0; for i in 0..len { tester.push_back(i); @@ -725,7 +725,7 @@ fn test_drain() { for head in 0..cap { for drain_start in 0..=len { for drain_end in drain_start..=len { - tester.head = head; + tester.head = WrappedIndex::from_arbitrary_number(head); tester.len = 0; for i in 0..len { tester.push_back(i); @@ -782,7 +782,7 @@ fn test_shrink_to() { assert_eq!(deque.capacity(), cap); // we can let the head point anywhere in the buffer since the deque is empty. - deque.head = head; + deque.head = WrappedIndex::from_arbitrary_number(head); deque.extend(1..=len); deque.shrink_to(target_cap); @@ -811,7 +811,7 @@ fn test_shrink_to_fit() { let expected = (0..).take(len).collect::>(); for head_pos in 0..=max_cap { tester.reserve(head_pos); - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; tester.reserve(63); for i in 0..len { @@ -848,7 +848,7 @@ fn test_split_off() { let expected_other = (at..).take(len - at).collect::>(); for head_pos in 0..cap { - tester.head = head_pos; + tester.head = WrappedIndex::from_arbitrary_number(head_pos); tester.len = 0; for i in 0..len { tester.push_back(i); diff --git a/alloc/src/ffi/c_str.rs b/alloc/src/ffi/c_str.rs index b2f4277458f1c..e6e6fcf5420f3 100644 --- a/alloc/src/ffi/c_str.rs +++ b/alloc/src/ffi/c_str.rs @@ -1077,9 +1077,17 @@ impl ToOwned for CStr { } fn clone_into(&self, target: &mut CString) { - let mut b = mem::take(&mut target.inner).into_vec(); - self.to_bytes_with_nul().clone_into(&mut b); - target.inner = b.into_boxed_slice(); + let src = self.to_bytes_with_nul(); + // If the lengths match, we can reuse the existing allocation without any overhead. + if target.inner.len() == src.len() { + target.inner.copy_from_slice(src); + } else { + // Reuse the existing allocation's capacity by converting to a Vec. + // We temporarily replace `target` with a valid dummy to remain panic-safe. + let mut b = mem::replace(&mut target.inner, Box::new([0])).into_vec(); + self.to_bytes_with_nul().clone_into(&mut b); + target.inner = b.into_boxed_slice(); + } } } diff --git a/alloc/src/lib.rs b/alloc/src/lib.rs index bcd9e092a310f..3f0c0ab3080c5 100644 --- a/alloc/src/lib.rs +++ b/alloc/src/lib.rs @@ -93,6 +93,7 @@ #![feature(async_iterator)] #![feature(bstr)] #![feature(bstr_internals)] +#![feature(case_ignorable)] #![feature(cast_maybe_uninit)] #![feature(cell_get_cloned)] #![feature(char_internals)] @@ -105,12 +106,15 @@ #![feature(const_destruct)] #![feature(const_eval_select)] #![feature(const_heap)] +#![feature(const_index)] #![feature(const_option_ops)] +#![feature(const_result_trait_fn)] #![feature(const_try)] #![feature(copied_into_inner)] #![feature(core_intrinsics)] #![feature(deprecated_suggestion)] #![feature(deref_pure_trait)] +#![feature(diagnostic_on_move)] #![feature(dispatch_from_dyn)] #![feature(ergonomic_clones)] #![feature(error_generic_member_access)] @@ -136,10 +140,12 @@ #![feature(pattern)] #![feature(pin_coerce_unsized_trait)] #![feature(ptr_alignment_type)] +#![feature(ptr_cast_slice)] #![feature(ptr_internals)] #![feature(ptr_metadata)] #![feature(rev_into_inner)] #![feature(set_ptr_value)] +#![feature(share_trait)] #![feature(sized_type_properties)] #![feature(slice_from_ptr_range)] #![feature(slice_index_methods)] @@ -170,6 +176,7 @@ #![feature(allocator_internals)] #![feature(allow_internal_unstable)] #![feature(cfg_sanitize)] +#![feature(const_closures)] #![feature(const_precise_live_drops)] #![feature(const_trait_impl)] #![feature(coroutine_trait)] diff --git a/alloc/src/raw_vec/mod.rs b/alloc/src/raw_vec/mod.rs index cabf6accf3b53..2f7d26c7a9724 100644 --- a/alloc/src/raw_vec/mod.rs +++ b/alloc/src/raw_vec/mod.rs @@ -244,7 +244,7 @@ impl RawVec { let me = ManuallyDrop::new(self); unsafe { - let slice = ptr::slice_from_raw_parts_mut(me.ptr() as *mut MaybeUninit, len); + let slice = me.ptr().cast::>().cast_slice(len); Box::from_raw_in(slice, ptr::read(&me.inner.alloc)) } } @@ -898,9 +898,5 @@ const fn layout_array(cap: usize, elem_layout: Layout) -> Result Ok(layout), - Err(_) => Err(CapacityOverflow.into()), - } + elem_layout.repeat_packed(cap).map_err(const |_| CapacityOverflow.into()) } diff --git a/alloc/src/rc.rs b/alloc/src/rc.rs index cfca2d9ec970e..523c9b8b15858 100644 --- a/alloc/src/rc.rs +++ b/alloc/src/rc.rs @@ -245,7 +245,7 @@ use core::any::Any; use core::cell::{Cell, CloneFromCell}; #[cfg(not(no_global_oom_handling))] use core::clone::TrivialClone; -use core::clone::{CloneToUninit, UseCloned}; +use core::clone::{CloneToUninit, Share, UseCloned}; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; use core::intrinsics::abort; @@ -311,6 +311,12 @@ fn rc_inner_layout_for_value_layout(layout: Layout) -> Layout { #[rustc_diagnostic_item = "Rc"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_insignificant_dtor] +#[diagnostic::on_move( + message = "the type `{Self}` does not implement `Copy`", + label = "this move could be avoided by cloning the original `{Self}`, which is inexpensive", + note = "consider using `Rc::clone`" +)] + pub struct Rc< T: ?Sized, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global, @@ -737,6 +743,7 @@ impl Rc { /// /// ``` /// #![feature(allocator_api)] + /// /// use std::rc::Rc; /// use std::alloc::System; /// @@ -1153,33 +1160,10 @@ impl Rc<[T]> { Rc::from_ptr(Rc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| Global.allocate_zeroed(layout), - |mem| { - ptr::slice_from_raw_parts_mut(mem.cast::(), len) - as *mut RcInner<[mem::MaybeUninit]> - }, + |mem| mem.cast::().cast_slice(len) as *mut RcInner<[mem::MaybeUninit]>, )) } } - - /// Converts the reference-counted slice into a reference-counted array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *const [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Rc::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Rc<[T], A> { @@ -1244,15 +1228,46 @@ impl Rc<[T], A> { Rc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| alloc.allocate_zeroed(layout), - |mem| { - ptr::slice_from_raw_parts_mut(mem.cast::(), len) - as *mut RcInner<[mem::MaybeUninit]> - }, + |mem| mem.cast::().cast_slice(len) as *mut RcInner<[mem::MaybeUninit]>, ), alloc, ) } } + + /// Converts the reference-counted slice into a reference-counted array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// # Errors + /// + /// Returns the original `Rc<[T]>` in the `Err` variant if `self.len()` does not equal `N`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// use std::rc::Rc; + /// + /// let rc_slice: Rc<[i32]> = Rc::new([1, 2, 3]); + /// + /// let rc_array: Rc<[i32; 3]> = rc_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Result, Self> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *const [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Rc::from_raw_in(ptr, alloc) }; + Ok(me) + } else { + Err(self) + } + } } impl Rc, A> { @@ -1562,7 +1577,7 @@ impl Rc { /// /// # Safety /// - /// The pointer must have been obtained through `Rc::into_raw`and must satisfy the + /// The pointer must have been obtained through `Rc::into_raw` and must satisfy the /// same layout requirements specified in [`Rc::from_raw_in`][from_raw_in]. /// The associated `Rc` instance must be valid (i.e. the strong count must be at /// least 1) when invoking this method, and `ptr` must point to a block of memory @@ -2306,7 +2321,7 @@ impl Rc<[T]> { Self::allocate_for_layout( Layout::array::(len).unwrap(), |layout| Global.allocate(layout), - |mem| ptr::slice_from_raw_parts_mut(mem.cast::(), len) as *mut RcInner<[T]>, + |mem| mem.cast::().cast_slice(len) as *mut RcInner<[T]>, ) } } @@ -2383,7 +2398,7 @@ impl Rc<[T], A> { Rc::<[T]>::allocate_for_layout( Layout::array::(len).unwrap(), |layout| alloc.allocate(layout), - |mem| ptr::slice_from_raw_parts_mut(mem.cast::(), len) as *mut RcInner<[T]>, + |mem| mem.cast::().cast_slice(len) as *mut RcInner<[T]>, ) } } @@ -2506,6 +2521,9 @@ impl Clone for Rc { #[unstable(feature = "ergonomic_clones", issue = "132290")] impl UseCloned for Rc {} +#[unstable(feature = "share_trait", issue = "156756")] +impl Share for Rc {} + #[cfg(not(no_global_oom_handling))] #[stable(feature = "rust1", since = "1.0.0")] impl Default for Rc { @@ -2596,7 +2614,7 @@ impl RcEqIdent for Rc { #[rustc_unsafe_specialization_marker] pub(crate) trait MarkerEq: PartialEq {} -impl MarkerEq for T {} +impl MarkerEq for T {} /// We're doing this specialization here, and not as a more general optimization on `&T`, because it /// would otherwise add a cost to all equality checks on refs. We assume that `Rc`s are used to @@ -2609,12 +2627,12 @@ impl MarkerEq for T {} impl RcEqIdent for Rc { #[inline] fn eq(&self, other: &Rc) -> bool { - Rc::ptr_eq(self, other) || **self == **other + ptr::eq(self.ptr.as_ptr(), other.ptr.as_ptr()) || **self == **other } #[inline] fn ne(&self, other: &Rc) -> bool { - !Rc::ptr_eq(self, other) && **self != **other + !ptr::eq(self.ptr.as_ptr(), other.ptr.as_ptr()) && **self != **other } } @@ -3494,7 +3512,13 @@ impl Weak { /// Attempts to upgrade the `Weak` pointer to an [`Rc`], delaying /// dropping of the inner value if successful. /// - /// Returns [`None`] if the inner value has since been dropped. + /// Returns [`None`] in the following cases: + /// + /// 1. The inner value has since been dropped or moved out. + /// + /// 2. This `Weak` does not point to an allocation. + /// + /// 3. The owning reference this `Weak` is associated with is either not fully-constructed or does not allow an upgrade. /// /// # Examples /// diff --git a/alloc/src/str.rs b/alloc/src/str.rs index 8a3326c7d76a7..cf04402e3d984 100644 --- a/alloc/src/str.rs +++ b/alloc/src/str.rs @@ -126,6 +126,22 @@ macro_rules! copy_slice_and_advance { // the bounds for String-join are S: Borrow and for Vec-join Borrow<[T]> // [T] and str both impl AsRef<[T]> for some T // => s.borrow().as_ref() and we always have slices +// +// # Safety notes +// +// `Borrow` is a safe trait, and implementations are not required +// to be deterministic. An inconsistent `Borrow` implementation could return slices +// of different lengths on consecutive calls (e.g. by using interior mutability). +// +// This implementation calls `borrow()` multiple times: +// 1. To calculate `reserved_len`, all elements are borrowed once. +// 2. All elements, except the first, are borrowed a second time when building the mapped iterator. +// +// Risks and Mitigations: +// - If elements 2..N GROW on their second borrow, the target slice bounds set by `checked_sub` +// means that `split_at_mut` inside `copy_slice_and_advance!` will correctly panic. +// - If elements SHRINK on their second borrow, the spare space is never written, and the final +// length set via `set_len` masks trailing uninitialized bytes. #[cfg(not(no_global_oom_handling))] fn join_generic_copy(slice: &[S], sep: &[T]) -> Vec where @@ -137,8 +153,10 @@ where let mut iter = slice.iter(); // the first slice is the only one without a separator preceding it + // we take care to only borrow this once during the length calculation + // to avoid inconsistent Borrow implementations from breaking our assumptions let first = match iter.next() { - Some(first) => first, + Some(first) => first.borrow().as_ref(), None => return vec![], }; @@ -148,8 +166,11 @@ where // the entire Vec pre-allocated for safety let reserved_len = sep_len .checked_mul(iter.len()) + .and_then(|n| n.checked_add(first.len())) .and_then(|n| { - slice.iter().map(|s| s.borrow().as_ref().len()).try_fold(n, usize::checked_add) + // iter starts from the second element as we've already taken the first + // it's cloned so we can reuse the same iterator below + iter.clone().map(|s| s.borrow().as_ref().len()).try_fold(n, usize::checked_add) }) .expect("attempt to join into collection with len > usize::MAX"); @@ -157,23 +178,25 @@ where let mut result = Vec::with_capacity(reserved_len); debug_assert!(result.capacity() >= reserved_len); - result.extend_from_slice(first.borrow().as_ref()); + result.extend_from_slice(first); unsafe { let pos = result.len(); + debug_assert!(reserved_len >= pos); let target = result.spare_capacity_mut().get_unchecked_mut(..reserved_len - pos); // Convert the separator and slices to slices of MaybeUninit - // to simplify implementation in specialize_for_lengths + // to simplify implementation in specialize_for_lengths. let sep_uninit = core::slice::from_raw_parts(sep.as_ptr().cast(), sep.len()); let iter_uninit = iter.map(|it| { let it = it.borrow().as_ref(); core::slice::from_raw_parts(it.as_ptr().cast(), it.len()) }); - // copy separator and slices over without bounds checks - // generate loops with hardcoded offsets for small separators - // massive improvements possible (~ x2) + // copy separator and slices over without bounds checks. + // `specialize_for_lengths!` internally calls `s.borrow()`, but because it uses + // the bounds-checked `split_at_mut` any misbehaving implementation + // will not write out of bounds. let remain = specialize_for_lengths!(sep_uninit, target, iter_uninit; 0, 1, 2, 3, 4); // A weird borrow implementation may return different @@ -185,6 +208,23 @@ where result } +/// Helper for final sigma lowercase +#[cfg(not(no_global_oom_handling))] +fn map_uppercase_sigma(from: &str, i: usize) -> char { + fn case_ignorable_then_cased>(iter: I) -> bool { + match iter.skip_while(|&c| c.is_case_ignorable()).next() { + Some(c) => c.is_cased(), + None => false, + } + } + + // See https://www.unicode.org/versions/latest/core-spec/chapter-3/#G54277 + // for the definition of `Final_Sigma`. + let is_word_final = case_ignorable_then_cased(from[..i].chars().rev()) + && !case_ignorable_then_cased(from[i + const { 'Σ'.len_utf8() }..].chars()); + if is_word_final { 'ς' } else { 'σ' } +} + #[stable(feature = "rust1", since = "1.0.0")] impl Borrow for String { #[inline] @@ -268,7 +308,10 @@ impl str { pub fn replace(&self, from: P, to: &str) -> String { // Fast path for replacing a single ASCII character with another. if let Some(from_byte) = match from.as_utf8_pattern() { - Some(Utf8Pattern::StringPattern([from_byte])) => Some(*from_byte), + Some(Utf8Pattern::StringPattern(s)) => match s.as_bytes() { + [from_byte] => Some(*from_byte), + _ => None, + }, Some(Utf8Pattern::CharPattern(c)) => c.as_ascii().map(|ascii_char| ascii_char.to_u8()), _ => None, } { @@ -335,24 +378,30 @@ impl str { /// Returns the lowercase equivalent of this string slice, as a new [`String`]. /// - /// 'Lowercase' is defined according to the terms of the Unicode Derived Core Property - /// `Lowercase`. + /// 'Lowercase' is defined according to the terms of + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G34432) + /// of the Unicode standard. /// /// Since some characters can expand into multiple characters when changing /// the case, this function returns a [`String`] instead of modifying the /// parameter in-place. /// + /// Unlike [`char::to_lowercase()`], this method fully handles the context-dependent + /// casing of Greek sigma. However, like that method, it does not handle locale-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See its documentation + /// for more information. + /// /// # Examples /// /// Basic usage: /// /// ``` - /// let s = "HELLO"; + /// let s = "HELLO WORLD"; /// - /// assert_eq!("hello", s.to_lowercase()); + /// assert_eq!("hello world", s.to_lowercase()); /// ``` /// - /// A tricky example, with sigma: + /// Tricky examples, with sigma: /// /// ``` /// let sigma = "Σ"; @@ -363,6 +412,10 @@ impl str { /// let odysseus = "ὈΔΥΣΣΕΎΣ"; /// /// assert_eq!("ὀδυσσεύς", odysseus.to_lowercase()); + /// + /// let odysseus_king_of_ithaca = "Ο ΟΔΥΣΣΈΑΣ ΒΑΣΙΛΙΆΣ ΤΗΣ ΙΘΆΚΗΣ"; + /// + /// assert_eq!("ο οδυσσέας βασιλιάς της ιθάκης", odysseus_king_of_ithaca.to_lowercase()); /// ``` /// /// Languages without case are not changed: @@ -378,7 +431,9 @@ impl str { without modifying the original"] #[stable(feature = "unicode_case_mapping", since = "1.2.0")] pub fn to_lowercase(&self) -> String { - let (mut s, rest) = convert_while_ascii(self, u8::to_ascii_lowercase); + // SAFETY: `to_ascii_lowercase` preserves ASCII bytes, so the converted + // prefix remains valid UTF-8. + let (mut s, rest) = unsafe { convert_while_ascii(self, u8::to_ascii_lowercase) }; let prefix_len = s.len(); @@ -407,40 +462,160 @@ impl str { } } return s; + } - fn map_uppercase_sigma(from: &str, i: usize) -> char { - // See https://www.unicode.org/versions/Unicode7.0.0/ch03.pdf#G33992 - // for the definition of `Final_Sigma`. - let is_word_final = case_ignorable_then_cased(from[..i].chars().rev()) - && !case_ignorable_then_cased(from[i + const { 'Σ'.len_utf8() }..].chars()); - if is_word_final { 'ς' } else { 'σ' } + /// Returns the titlecase equivalent of this string slice, + /// which is assumed to represent a single word, + /// as a new [`String`]. + /// + /// Essentially, this consists of uppercasing the first cased letter + /// (with [`char::to_titlecase()`]), and lowercasing everything that follows. + /// + /// 'Titlecase' is defined according to the terms of + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G34082) + /// of the Unicode standard. + /// + /// Since some characters can expand into multiple characters when changing + /// the case, this function returns a [`String`] instead of modifying the + /// parameter in-place. + /// + /// Unlike [`char::to_lowercase()`], this method fully handles the context-dependent + /// casing of Greek sigma. However, like that method, it does not handle locale-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See its documentation + /// for more information. + /// + /// This method does not perform any kind of word segmentation. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(titlecase)] + /// let s = "HELLO WORLD"; + /// + /// assert_eq!("Hello world", s.word_to_titlecase()); + /// ``` + /// + /// The first *cased* letter is uppercased: + /// + /// ``` + /// #![feature(titlecase)] + /// let the_night_before_christmas = "'twas"; + /// + /// assert_eq!("'Twas", the_night_before_christmas.word_to_titlecase()); + /// ``` + /// + /// Languages without case are not changed: + /// + /// ``` + /// #![feature(titlecase)] + /// let new_year = "农历新年"; + /// + /// assert_eq!(new_year, new_year.word_to_titlecase()); + /// ``` + /// + /// Georgian uppercase ("Mtavruli") letters are not used in titlecase: + /// + /// ``` + /// #![feature(titlecase)] + /// let georgian = "ერთობაშია"; + /// + /// assert_eq!(georgian, georgian.word_to_titlecase()); + /// ``` + /// + /// No word segmentation is performed, + /// so only the first cased letter in the whole string gets uppercased: + /// + /// ``` + /// #![feature(titlecase)] + /// let blazingly_fast = "ferris and I"; + /// + /// assert_eq!("Ferris and i", blazingly_fast.word_to_titlecase()); + /// ``` + /// + /// Tricky examples, with sigma: + /// + /// ``` + /// #![feature(titlecase)] + /// let odysseus = "ὈΔΥΣΣΕΎΣ"; + /// + /// assert_eq!("Ὀδυσσεύς", odysseus.word_to_titlecase()); + /// + /// let odysseus_king_of_ithaca = "Ο ΟΔΥΣΣΈΑΣ ΒΑΣΙΛΙΆΣ ΤΗΣ ΙΘΆΚΗΣ"; + /// + /// assert_eq!("Ο οδυσσέας βασιλιάς της ιθάκης", odysseus_king_of_ithaca.word_to_titlecase()); + /// ``` + #[cfg(not(no_global_oom_handling))] + #[rustc_allow_incoherent_impl] + #[must_use = "this returns the titlecase word as a new String, \ + without modifying the original"] + #[unstable(feature = "titlecase", issue = "153892")] + pub fn word_to_titlecase(&self) -> String { + // FIXME: add ASCII fast path + + let mut s = String::with_capacity(self.len()); + let mut chars = self.char_indices(); + + 'until_first_cased_char: for (_, c) in chars.by_ref() { + if c.is_cased() { + s.extend(c.to_titlecase()); + break 'until_first_cased_char; + } else { + s.push(c); + } } - fn case_ignorable_then_cased>(iter: I) -> bool { - match iter.skip_while(|&c| c.is_case_ignorable()).next() { - Some(c) => c.is_cased(), - None => false, + for (i, c) in chars { + if c == 'Σ' { + // Σ maps to σ, except at the end of a word where it maps to ς. + // This is the only conditional (contextual) but language-independent mapping + // in `SpecialCasing.txt`, + // so hard-code it rather than have a generic "condition" mechanism. + // See https://github.com/rust-lang/rust/issues/26035 + let sigma_lowercase = map_uppercase_sigma(self, i); + s.push(sigma_lowercase); + } else { + match conversions::to_lower(c) { + [a, '\0', _] => s.push(a), + [a, b, '\0'] => { + s.push(a); + s.push(b); + } + [a, b, c] => { + s.push(a); + s.push(b); + s.push(c); + } + } } } + + s } /// Returns the uppercase equivalent of this string slice, as a new [`String`]. /// - /// 'Uppercase' is defined according to the terms of the Unicode Derived Core Property - /// `Uppercase`. + /// 'Uppercase' is defined according to the terms of + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G34431) + /// of the Unicode standard. /// /// Since some characters can expand into multiple characters when changing /// the case, this function returns a [`String`] instead of modifying the /// parameter in-place. /// + /// Like [`char::to_uppercase()`] this method does not handle language-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See that method's documentation + /// for more information. + /// /// # Examples /// /// Basic usage: /// /// ``` - /// let s = "hello"; + /// let s = "hello world"; /// - /// assert_eq!("HELLO", s.to_uppercase()); + /// assert_eq!("HELLO WORLD", s.to_uppercase()); /// ``` /// /// Scripts without case are not changed: @@ -463,7 +638,9 @@ impl str { without modifying the original"] #[stable(feature = "unicode_case_mapping", since = "1.2.0")] pub fn to_uppercase(&self) -> String { - let (mut s, rest) = convert_while_ascii(self, u8::to_ascii_uppercase); + // SAFETY: `to_ascii_uppercase` preserves ASCII bytes, so the converted + // prefix remains valid UTF-8. + let (mut s, rest) = unsafe { convert_while_ascii(self, u8::to_ascii_uppercase) }; for c in rest.chars() { match conversions::to_upper(c) { @@ -626,11 +803,15 @@ pub unsafe fn from_boxed_utf8_unchecked(v: Box<[u8]>) -> Box { /// /// This function is only public so that it can be verified in a codegen test, /// see `issue-123712-str-to-lower-autovectorization.rs`. +/// +/// # Safety +/// +/// `convert` must return an ASCII byte for every ASCII input byte. #[unstable(feature = "str_internals", issue = "none")] #[doc(hidden)] #[inline] #[cfg(not(no_global_oom_handling))] -pub fn convert_while_ascii(s: &str, convert: fn(&u8) -> u8) -> (String, &str) { +pub unsafe fn convert_while_ascii(s: &str, convert: fn(&u8) -> u8) -> (String, &str) { // Process the input in chunks of 16 bytes to enable auto-vectorization. // Previously the chunk size depended on the size of `usize`, // but on 32-bit platforms with sse or neon is also the better choice. diff --git a/alloc/src/string.rs b/alloc/src/string.rs index 30e52f3e1be46..7c6befa95718c 100644 --- a/alloc/src/string.rs +++ b/alloc/src/string.rs @@ -410,7 +410,16 @@ pub struct FromUtf8Error { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[derive(Debug)] -pub struct FromUtf16Error(()); +pub struct FromUtf16Error { + kind: FromUtf16ErrorKind, +} + +#[cfg_attr(no_global_oom_handling, expect(dead_code))] +#[derive(Clone, PartialEq, Eq, Debug)] +enum FromUtf16ErrorKind { + LoneSurrogate, + OddBytes, +} impl String { /// Creates a new empty `String`. @@ -719,7 +728,7 @@ impl String { let mut ret = String::with_capacity(v.len()); for c in char::decode_utf16(v.iter().cloned()) { let Ok(c) = c else { - return Err(FromUtf16Error(())); + return Err(FromUtf16Error { kind: FromUtf16ErrorKind::LoneSurrogate }); }; ret.push(c); } @@ -782,13 +791,13 @@ impl String { #[unstable(feature = "str_from_utf16_endian", issue = "116258")] pub fn from_utf16le(v: &[u8]) -> Result { let (chunks, []) = v.as_chunks::<2>() else { - return Err(FromUtf16Error(())); + return Err(FromUtf16Error { kind: FromUtf16ErrorKind::OddBytes }); }; match (cfg!(target_endian = "little"), unsafe { v.align_to::() }) { (true, ([], v, [])) => Self::from_utf16(v), _ => char::decode_utf16(chunks.iter().copied().map(u16::from_le_bytes)) .collect::>() - .map_err(|_| FromUtf16Error(())), + .map_err(|_| FromUtf16Error { kind: FromUtf16ErrorKind::LoneSurrogate }), } } @@ -857,13 +866,13 @@ impl String { #[unstable(feature = "str_from_utf16_endian", issue = "116258")] pub fn from_utf16be(v: &[u8]) -> Result { let (chunks, []) = v.as_chunks::<2>() else { - return Err(FromUtf16Error(())); + return Err(FromUtf16Error { kind: FromUtf16ErrorKind::OddBytes }); }; match (cfg!(target_endian = "big"), unsafe { v.align_to::() }) { (true, ([], v, [])) => Self::from_utf16(v), _ => char::decode_utf16(chunks.iter().copied().map(u16::from_be_bytes)) .collect::>() - .map_err(|_| FromUtf16Error(())), + .map_err(|_| FromUtf16Error { kind: FromUtf16ErrorKind::LoneSurrogate }), } } @@ -1420,7 +1429,7 @@ impl String { // SAFETY: Just reserved capacity for at least the length needed to encode `ch`. unsafe { - core::char::encode_utf8_raw_unchecked(ch as u32, self.vec.as_mut_ptr().add(self.len())); + core::char::encode_utf8_raw_unchecked(ch as u32, self.vec.as_mut_ptr().add(len)); self.vec.set_len(len + ch_len); } } @@ -2335,7 +2344,11 @@ impl fmt::Display for FromUtf8Error { #[stable(feature = "rust1", since = "1.0.0")] impl fmt::Display for FromUtf16Error { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Display::fmt("invalid utf-16: lone surrogate found", f) + match self.kind { + FromUtf16ErrorKind::LoneSurrogate => "invalid utf-16: lone surrogate found", + FromUtf16ErrorKind::OddBytes => "invalid utf-16: odd number of bytes", + } + .fmt(f) } } @@ -2654,7 +2667,7 @@ impl<'b> Pattern for &'b String { #[inline] fn as_utf8_pattern(&self) -> Option> { - Some(Utf8Pattern::StringPattern(self.as_bytes())) + Some(Utf8Pattern::StringPattern(self.as_str())) } } @@ -2697,7 +2710,7 @@ impl_eq! { Cow<'_, str>, String } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for String { +const impl Default for String { /// Creates an empty `String`. #[inline] fn default() -> String { diff --git a/alloc/src/sync.rs b/alloc/src/sync.rs index b3e49af868b8c..4a9878d8e249d 100644 --- a/alloc/src/sync.rs +++ b/alloc/src/sync.rs @@ -12,7 +12,7 @@ use core::any::Any; use core::cell::CloneFromCell; #[cfg(not(no_global_oom_handling))] use core::clone::TrivialClone; -use core::clone::{CloneToUninit, UseCloned}; +use core::clone::{CloneToUninit, Share, UseCloned}; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; use core::intrinsics::abort; @@ -261,6 +261,11 @@ macro_rules! acquire { #[rustc_diagnostic_item = "Arc"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_insignificant_dtor] +#[diagnostic::on_move( + message = "the type `{Self}` does not implement `Copy`", + label = "this move could be avoided by cloning the original `{Self}`, which is inexpensive", + note = "consider using `Arc::clone`" +)] pub struct Arc< T: ?Sized, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global, @@ -1301,33 +1306,10 @@ impl Arc<[T]> { Arc::from_ptr(Arc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| Global.allocate_zeroed(layout), - |mem| { - ptr::slice_from_raw_parts_mut(mem as *mut T, len) - as *mut ArcInner<[mem::MaybeUninit]> - }, + |mem| mem.cast::().cast_slice(len) as *mut ArcInner<[mem::MaybeUninit]>, )) } } - - /// Converts the reference-counted slice into a reference-counted array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *const [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Arc::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Arc<[T], A> { @@ -1393,15 +1375,46 @@ impl Arc<[T], A> { Arc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| alloc.allocate_zeroed(layout), - |mem| { - ptr::slice_from_raw_parts_mut(mem.cast::(), len) - as *mut ArcInner<[mem::MaybeUninit]> - }, + |mem| mem.cast::().cast_slice(len) as *mut ArcInner<[mem::MaybeUninit]>, ), alloc, ) } } + + /// Converts the reference-counted slice into a reference-counted array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// # Errors + /// + /// Returns the original `Arc<[T]>` in the `Err` variant if `self.len()` does not equal `N`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// use std::sync::Arc; + /// + /// let arc_slice: Arc<[i32]> = Arc::new([1, 2, 3]); + /// + /// let arc_array: Arc<[i32; 3]> = arc_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Result, Self> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *const [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Arc::from_raw_in(ptr, alloc) }; + Ok(me) + } else { + Err(self) + } + } } impl Arc, A> { @@ -2253,7 +2266,7 @@ impl Arc<[T]> { Self::allocate_for_layout( Layout::array::(len).unwrap(), |layout| Global.allocate(layout), - |mem| ptr::slice_from_raw_parts_mut(mem.cast::(), len) as *mut ArcInner<[T]>, + |mem| mem.cast::().cast_slice(len) as *mut ArcInner<[T]>, ) } } @@ -2332,7 +2345,7 @@ impl Arc<[T], A> { Arc::allocate_for_layout( Layout::array::(len).unwrap(), |layout| alloc.allocate(layout), - |mem| ptr::slice_from_raw_parts_mut(mem.cast::(), len) as *mut ArcInner<[T]>, + |mem| mem.cast::().cast_slice(len) as *mut ArcInner<[T]>, ) } } @@ -2419,6 +2432,9 @@ impl Clone for Arc { #[unstable(feature = "ergonomic_clones", issue = "132290")] impl UseCloned for Arc {} +#[unstable(feature = "share_trait", issue = "156756")] +impl Share for Arc {} + #[stable(feature = "rust1", since = "1.0.0")] impl Deref for Arc { type Target = T; @@ -3227,7 +3243,13 @@ impl Weak { /// Attempts to upgrade the `Weak` pointer to an [`Arc`], delaying /// dropping of the inner value if successful. /// - /// Returns [`None`] if the inner value has since been dropped. + /// Returns [`None`] in the following cases: + /// + /// 1. The inner value has since been dropped or moved out. + /// + /// 2. This `Weak` does not point to an allocation. + /// + /// 3. The owning reference this `Weak` is associated with is either not fully-constructed or does not allow an upgrade. /// /// # Examples /// @@ -3526,12 +3548,12 @@ impl ArcEqIdent for Arc { impl ArcEqIdent for Arc { #[inline] fn eq(&self, other: &Arc) -> bool { - Arc::ptr_eq(self, other) || **self == **other + ptr::eq(self.ptr.as_ptr(), other.ptr.as_ptr()) || **self == **other } #[inline] fn ne(&self, other: &Arc) -> bool { - !Arc::ptr_eq(self, other) && **self != **other + !ptr::eq(self.ptr.as_ptr(), other.ptr.as_ptr()) && **self != **other } } diff --git a/alloc/src/vec/drain.rs b/alloc/src/vec/drain.rs index 9a6bfa823f2a5..d12dea20b33cb 100644 --- a/alloc/src/vec/drain.rs +++ b/alloc/src/vec/drain.rs @@ -232,7 +232,7 @@ impl Drop for Drain<'_, T, A> { // invalidate raw pointers to it which some unsafe code might rely on. let vec_ptr = vec.as_mut().as_mut_ptr(); let drop_offset = drop_ptr.offset_from_unsigned(vec_ptr); - let to_drop = ptr::slice_from_raw_parts_mut(vec_ptr.add(drop_offset), drop_len); + let to_drop = vec_ptr.add(drop_offset).cast_slice(drop_len); ptr::drop_in_place(to_drop); } } diff --git a/alloc/src/vec/extract_if.rs b/alloc/src/vec/extract_if.rs index 35eb7549738df..a4c4c19682195 100644 --- a/alloc/src/vec/extract_if.rs +++ b/alloc/src/vec/extract_if.rs @@ -130,20 +130,25 @@ where A: Allocator, { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let peek = if self.idx < self.end { - // This has to use pointer arithmetic as `self.vec[self.idx]` or - // `self.vec.get_unchecked(self.idx)` wouldn't work since we - // temporarily set the length of `self.vec` to zero. - // - // SAFETY: - // Since `self.idx` is smaller than `self.end` and `self.end` is - // smaller than `self.old_len`, `idx` is valid for indexing the - // buffer. Also, per the invariant of `self.idx`, this element - // has not been inspected/moved out yet. - Some(unsafe { &*self.vec.as_ptr().add(self.idx) }) - } else { - None - }; - f.debug_struct("ExtractIf").field("peek", &peek).finish_non_exhaustive() + // We have to use pointer arithmetics here, + // because the length of `self.vec` is temporarily set to 0. + let start = self.vec.as_ptr(); + + // SAFETY: we always keep first `self.idx - self.del` elements valid. + let retained = unsafe { slice::from_raw_parts(start, self.idx - self.del) }; + + // SAFETY: we have not yet touched elements starting at `self.idx`. + let valid_tail = + unsafe { slice::from_raw_parts(start.add(self.idx), self.old_len - self.idx) }; + + // SAFETY: `end - idx <= old_len - idx`, because `end <= old_len`. Also `idx <= end` by invariant. + let (remainder, skipped_tail) = + unsafe { valid_tail.split_at_unchecked(self.end - self.idx) }; + + f.debug_struct("ExtractIf") + .field("retained", &retained) + .field("remainder", &remainder) + .field("skipped_tail", &skipped_tail) + .finish_non_exhaustive() } } diff --git a/alloc/src/vec/in_place_drop.rs b/alloc/src/vec/in_place_drop.rs index c8cc758ac15c4..5c3d598cdef0c 100644 --- a/alloc/src/vec/in_place_drop.rs +++ b/alloc/src/vec/in_place_drop.rs @@ -1,5 +1,5 @@ use core::marker::PhantomData; -use core::ptr::{self, NonNull, drop_in_place}; +use core::ptr::NonNull; use crate::alloc::Global; use crate::raw_vec::RawVec; @@ -20,9 +20,7 @@ impl InPlaceDrop { impl Drop for InPlaceDrop { #[inline] fn drop(&mut self) { - unsafe { - ptr::drop_in_place(ptr::slice_from_raw_parts_mut(self.inner, self.len())); - } + unsafe { self.inner.cast_slice(self.len()).drop_in_place() } } } @@ -42,7 +40,7 @@ impl Drop for InPlaceDstDataSrcBufDrop { unsafe { let _drop_allocation = RawVec::::from_nonnull_in(self.ptr.cast::(), self.src_cap, Global); - drop_in_place(core::ptr::slice_from_raw_parts_mut::(self.ptr.as_ptr(), self.len)); + self.ptr.as_ptr().cast_slice(self.len).drop_in_place(); }; } } diff --git a/alloc/src/vec/into_iter.rs b/alloc/src/vec/into_iter.rs index 4f67a2c04fefc..97e4912596b94 100644 --- a/alloc/src/vec/into_iter.rs +++ b/alloc/src/vec/into_iter.rs @@ -115,7 +115,7 @@ impl IntoIter { } fn as_raw_mut_slice(&mut self) -> *mut [T] { - ptr::slice_from_raw_parts_mut(self.ptr.as_ptr(), self.len()) + self.ptr.as_ptr().cast_slice(self.len()) } /// Drops remaining elements and relinquishes the backing allocation. @@ -159,12 +159,51 @@ impl IntoIter { } /// Forgets to Drop the remaining elements while still allowing the backing allocation to be freed. + /// + /// This method does not consume `self`, and leaves deallocation to `impl Drop for IntoIter`. + /// If consuming `self` is possible, consider calling + /// [`Self::forget_remaining_elements_and_dealloc()`] instead. pub(crate) fn forget_remaining_elements(&mut self) { // For the ZST case, it is crucial that we mutate `end` here, not `ptr`. // `ptr` must stay aligned, while `end` may be unaligned. self.end = self.ptr.as_ptr(); } + /// Forgets to Drop the remaining elements and frees the backing allocation. + /// Consuming version of [`Self::forget_remaining_elements()`]. + /// + /// This can be used in place of `drop(self)` when `self` is known to be exhausted, + /// to avoid producing a needless `drop_in_place::<[T]>()`. + #[inline] + pub(crate) fn forget_remaining_elements_and_dealloc(self) { + let mut this = ManuallyDrop::new(self); + // SAFETY: `this` is in ManuallyDrop, so it will not be double-freed. + unsafe { + this.dealloc_only(); + } + } + + /// Frees the allocation, without checking or dropping anything else. + /// + /// The safe version of this method is [`Self::forget_remaining_elements_and_dealloc()`]. + /// This function exists only to share code between that method and the `impl Drop`. + /// + /// # Safety + /// + /// This function must only be called with an [`IntoIter`] that is not going to be dropped + /// or otherwise used in any way, either because it is being forgotten or because its `Drop` + /// is already executing; otherwise a double-free will occur, and possibly a read from freed + /// memory if there are any remaining elements. + #[inline] + unsafe fn dealloc_only(&mut self) { + unsafe { + // SAFETY: our caller promises not to touch `*self` again + let alloc = ManuallyDrop::take(&mut self.alloc); + // RawVec handles deallocation + let _ = RawVec::from_nonnull_in(self.buf, self.cap, alloc); + } + } + #[cfg(not(no_global_oom_handling))] #[inline] pub(crate) fn into_vecdeque(self) -> VecDeque { @@ -243,7 +282,7 @@ impl Iterator for IntoIter { #[inline] fn advance_by(&mut self, n: usize) -> Result<(), NonZero> { let step_size = self.len().min(n); - let to_drop = ptr::slice_from_raw_parts_mut(self.ptr.as_ptr(), step_size); + let to_drop = self.ptr.as_ptr().cast_slice(step_size); if T::IS_ZST { // See `next` for why we sub `end` here. self.end = self.end.wrapping_byte_sub(step_size); @@ -328,6 +367,12 @@ impl Iterator for IntoIter { accum = f(accum, tmp); } } + + // There are in fact no remaining elements to forget, but by doing this we can avoid + // potentially generating a needless loop to drop the elements that cannot exist at + // this point. + self.forget_remaining_elements_and_dealloc(); + accum } @@ -412,9 +457,9 @@ impl DoubleEndedIterator for IntoIter { } let to_drop = if T::IS_ZST { // ZST may cause unalignment - ptr::slice_from_raw_parts_mut(ptr::NonNull::::dangling().as_ptr(), step_size) + ptr::NonNull::::dangling().as_ptr().cast_slice(step_size) } else { - ptr::slice_from_raw_parts_mut(self.end as *mut T, step_size) + self.end.cast::().cast_mut().cast_slice(step_size) }; // SAFETY: same as for advance_by() unsafe { @@ -500,10 +545,7 @@ unsafe impl<#[may_dangle] T, A: Allocator> Drop for IntoIter { impl Drop for DropGuard<'_, T, A> { fn drop(&mut self) { unsafe { - // `IntoIter::alloc` is not used anymore after this and will be dropped by RawVec - let alloc = ManuallyDrop::take(&mut self.0.alloc); - // RawVec handles deallocation - let _ = RawVec::from_nonnull_in(self.0.buf, self.0.cap, alloc); + self.0.dealloc_only(); } } } diff --git a/alloc/src/vec/mod.rs b/alloc/src/vec/mod.rs index 942b2b9d2dadf..197b28d68fdf1 100644 --- a/alloc/src/vec/mod.rs +++ b/alloc/src/vec/mod.rs @@ -1062,8 +1062,7 @@ impl Vec { /// /// use std::alloc::System; /// - /// # #[allow(unused_mut)] - /// let mut vec: Vec = Vec::new_in(System); + /// let vec: Vec = Vec::new_in(System); /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] @@ -1741,6 +1740,34 @@ impl Vec { } } + /// Converts the Vec into a boxed array. This conversion will discard any spare capacity, + /// if there is any, see [`Vec::shrink_to_fit`]. + /// If you merely wish for a reference to an array, use [`as_array`](https://doc.rust-lang.org/stable/std/primitive.slice.html#method.as_array). + /// + /// # Errors + /// + /// Returns the original `Vec` in the `Err` variant if [`Vec::len`] does not equal `N`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// let vec: Vec = vec![1, 2, 3]; + /// let box_array: Box<[i32; 3]> = vec.clone().into_array().unwrap(); + /// let not_enough_elements: Result, Vec> = vec.into_array::<4>(); + /// assert_eq!(not_enough_elements, Err(vec![1, 2, 3])); + /// ``` + #[cfg(not(no_global_oom_handling))] + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[must_use] + pub fn into_array(self) -> Result, Self> { + if self.len() == N { + Ok(self.into_boxed_slice().into_array().ok().unwrap()) + } else { + Err(self) + } + } + /// Shortens the vector, keeping the first `len` elements and dropping /// the rest. /// @@ -1785,6 +1812,9 @@ impl Vec { /// [`drain`]: Vec::drain #[stable(feature = "rust1", since = "1.0.0")] pub fn truncate(&mut self, len: usize) { + // SAFETY: `BufWriter::flush_buf` assumes that this will not + // de-initialize any elements of the spare capacity. + // This is safe because: // // * the slice passed to `drop_in_place` is valid; the `len > self.len` @@ -1800,7 +1830,7 @@ impl Vec { return; } let remaining_len = self.len - len; - let s = ptr::slice_from_raw_parts_mut(self.as_mut_ptr().add(len), remaining_len); + let s = self.as_mut_ptr().add(len).cast_slice(remaining_len); self.len = len; ptr::drop_in_place(s); } @@ -1858,6 +1888,9 @@ impl Vec { #[rustc_diagnostic_item = "vec_as_mut_slice"] #[rustc_const_stable(feature = "const_vec_string_slice", since = "1.87.0")] pub const fn as_mut_slice(&mut self) -> &mut [T] { + // SAFETY: `BufWriter::flush_buf` assumes that this will not + // de-initialize any elements of the spare capacity. + // SAFETY: `slice::from_raw_parts_mut` requires pointee is a contiguous, aligned buffer of // size `len` containing properly-initialized `T`s. Data must not be accessed through any // other pointer for the returned lifetime. Further, `len * size_of::` <= @@ -2993,6 +3026,10 @@ impl Vec { #[inline] #[stable(feature = "rust1", since = "1.0.0")] pub fn clear(&mut self) { + // Though this is equivalent to `truncate(0)`, the manual version + // optimizes better, justifying the additional complexity + // (see #96002 and #154095 for context). + let elems: *mut [T] = self.as_mut_slice(); // SAFETY: @@ -3748,7 +3785,8 @@ impl ExtendFromWithinSpec for Vec { //////////////////////////////////////////////////////////////////////////////// #[stable(feature = "rust1", since = "1.0.0")] -impl ops::Deref for Vec { +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl ops::Deref for Vec { type Target = [T]; #[inline] @@ -3758,7 +3796,8 @@ impl ops::Deref for Vec { } #[stable(feature = "rust1", since = "1.0.0")] -impl ops::DerefMut for Vec { +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl ops::DerefMut for Vec { #[inline] fn deref_mut(&mut self) -> &mut [T] { self.as_mut_slice() @@ -3823,7 +3862,8 @@ impl Hash for Vec { } #[stable(feature = "rust1", since = "1.0.0")] -impl, A: Allocator> Index for Vec { +#[rustc_const_unstable(feature = "const_index", issue = "143775")] +const impl, A: Allocator> Index for Vec { type Output = I::Output; #[inline] @@ -3833,7 +3873,8 @@ impl, A: Allocator> Index for Vec { } #[stable(feature = "rust1", since = "1.0.0")] -impl, A: Allocator> IndexMut for Vec { +#[rustc_const_unstable(feature = "const_index", issue = "143775")] +const impl, A: Allocator> IndexMut for Vec { #[inline] fn index_mut(&mut self, index: I) -> &mut Self::Output { IndexMut::index_mut(&mut **self, index) @@ -4248,7 +4289,7 @@ unsafe impl<#[may_dangle] T, A: Allocator> Drop for Vec { // use drop for [T] // use a raw slice to refer to the elements of the vector as weakest necessary type; // could avoid questions of validity in certain cases - ptr::drop_in_place(ptr::slice_from_raw_parts_mut(self.as_mut_ptr(), self.len)) + self.as_mut_ptr().cast_slice(self.len).drop_in_place() } // RawVec handles deallocation } @@ -4256,7 +4297,7 @@ unsafe impl<#[may_dangle] T, A: Allocator> Drop for Vec { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Vec { +const impl Default for Vec { /// Creates an empty `Vec`. /// /// The vector will not allocate until elements are pushed onto it. diff --git a/alloc/src/vec/partial_eq.rs b/alloc/src/vec/partial_eq.rs index 5e620c4b2efe7..204e5678a69d6 100644 --- a/alloc/src/vec/partial_eq.rs +++ b/alloc/src/vec/partial_eq.rs @@ -4,11 +4,11 @@ use crate::alloc::Allocator; use crate::borrow::Cow; macro_rules! __impl_slice_eq1 { - ([$($vars:tt)*] $lhs:ty, $rhs:ty $(where $ty:ty: $bound:ident)?, #[$stability:meta]) => { - #[$stability] - impl PartialEq<$rhs> for $lhs + ($($const:ident, )? [$($vars:tt)*] $lhs:ty, $rhs:ty $(where $ty:ty: $bound:ident)?, $(#[$stability:meta])+ ) => { + $(#[$stability])+ + impl $($const)? PartialEq<$rhs> for $lhs where - T: PartialEq, + T: $([$const])? PartialEq, $($ty: $bound)? { #[inline] @@ -19,21 +19,21 @@ macro_rules! __impl_slice_eq1 { } } -__impl_slice_eq1! { [A1: Allocator, A2: Allocator] Vec, Vec, #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator] Vec, &[U], #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator] Vec, &mut [U], #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator] &[T], Vec, #[stable(feature = "partialeq_vec_for_ref_slice", since = "1.46.0")] } -__impl_slice_eq1! { [A: Allocator] &mut [T], Vec, #[stable(feature = "partialeq_vec_for_ref_slice", since = "1.46.0")] } -__impl_slice_eq1! { [A: Allocator] Vec, [U], #[stable(feature = "partialeq_vec_for_slice", since = "1.48.0")] } -__impl_slice_eq1! { [A: Allocator] [T], Vec, #[stable(feature = "partialeq_vec_for_slice", since = "1.48.0")] } +__impl_slice_eq1! { const, [A1: Allocator, A2: Allocator] Vec, Vec, #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator] Vec, &[U], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator] Vec, &mut [U], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator] &[T], Vec, #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "partialeq_vec_for_ref_slice", since = "1.46.0")] } +__impl_slice_eq1! { const, [A: Allocator] &mut [T], Vec, #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "partialeq_vec_for_ref_slice", since = "1.46.0")] } +__impl_slice_eq1! { const, [A: Allocator] Vec, [U], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "partialeq_vec_for_slice", since = "1.48.0")] } +__impl_slice_eq1! { const, [A: Allocator] [T], Vec, #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "partialeq_vec_for_slice", since = "1.48.0")] } #[cfg(not(no_global_oom_handling))] __impl_slice_eq1! { [A: Allocator] Cow<'_, [T]>, Vec where T: Clone, #[stable(feature = "rust1", since = "1.0.0")] } #[cfg(not(no_global_oom_handling))] __impl_slice_eq1! { [] Cow<'_, [T]>, &[U] where T: Clone, #[stable(feature = "rust1", since = "1.0.0")] } #[cfg(not(no_global_oom_handling))] __impl_slice_eq1! { [] Cow<'_, [T]>, &mut [U] where T: Clone, #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator, const N: usize] Vec, [U; N], #[stable(feature = "rust1", since = "1.0.0")] } -__impl_slice_eq1! { [A: Allocator, const N: usize] Vec, &[U; N], #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator, const N: usize] Vec, [U; N], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } +__impl_slice_eq1! { const, [A: Allocator, const N: usize] Vec, &[U; N], #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[stable(feature = "rust1", since = "1.0.0")] } // NOTE: some less important impls are omitted to reduce code bloat // FIXME(Centril): Reconsider this? diff --git a/alloc/src/vec/spec_extend.rs b/alloc/src/vec/spec_extend.rs index de6ef3d803263..b3fee7d094e20 100644 --- a/alloc/src/vec/spec_extend.rs +++ b/alloc/src/vec/spec_extend.rs @@ -29,11 +29,11 @@ where } impl SpecExtend> for Vec { - fn spec_extend(&mut self, mut iterator: IntoIter) { + fn spec_extend(&mut self, iterator: IntoIter) { unsafe { self.append_elements(iterator.as_slice() as _); } - iterator.forget_remaining_elements(); + iterator.forget_remaining_elements_and_dealloc(); } } diff --git a/alloctests/benches/lib.rs b/alloctests/benches/lib.rs index 4a25778d88c83..b7e09fc2e162b 100644 --- a/alloctests/benches/lib.rs +++ b/alloctests/benches/lib.rs @@ -1,5 +1,6 @@ // This is marked as `test = true` and hence picked up by `./x miri`, but that would be too slow. #![cfg(not(miri))] +#![allow(internal_features)] #![feature(iter_next_chunk)] #![feature(repr_simd)] #![feature(slice_partition_dedup)] diff --git a/alloctests/lib.rs b/alloctests/lib.rs index e09d8495fdeac..db643ccb7a4e6 100644 --- a/alloctests/lib.rs +++ b/alloctests/lib.rs @@ -23,6 +23,7 @@ #![feature(const_destruct)] #![feature(const_heap)] #![feature(const_option_ops)] +#![feature(const_result_trait_fn)] #![feature(const_try)] #![feature(copied_into_inner)] #![feature(core_intrinsics)] @@ -35,6 +36,7 @@ #![feature(iter_next_chunk)] #![feature(maybe_uninit_uninit_array_transpose)] #![feature(ptr_alignment_type)] +#![feature(ptr_cast_slice)] #![feature(ptr_internals)] #![feature(rev_into_inner)] #![feature(sized_type_properties)] @@ -54,6 +56,7 @@ // // Language features: // tidy-alphabetical-start +#![feature(const_closures)] #![feature(const_trait_impl)] #![feature(dropck_eyepatch)] #![feature(min_specialization)] diff --git a/alloctests/tests/arc.rs b/alloctests/tests/arc.rs index 00bdf527133f7..4b4d1787ace63 100644 --- a/alloctests/tests/arc.rs +++ b/alloctests/tests/arc.rs @@ -86,6 +86,34 @@ fn eq() { assert_eq!(*x.0.borrow(), 0); } +#[test] +fn eq_unsized() { + #[derive(Eq)] + struct TestEq(RefCell, T); + impl PartialEq for TestEq { + fn eq(&self, other: &TestEq) -> bool { + *self.0.borrow_mut() += 1; + *other.0.borrow_mut() += 1; + true + } + } + let x = Arc::>::new(TestEq(RefCell::new(0), [0, 1, 2])) as Arc>; + assert!(x == x); + assert!(!(x != x)); + assert_eq!(*x.0.borrow(), 0); +} + +#[test] +fn eq_unsized_slice() { + let a: Arc<[()]> = Arc::new([(); 3]); + let ptr: *const () = Arc::into_raw(a.clone()).cast(); + let b: Arc<[()]> = unsafe { Arc::from_raw(ptr.cast_slice(42)) }; + assert!(a == a); + assert!(!(a != a)); + assert!(a != b); + assert!(!(a == b)); +} + // The test code below is identical to that in `rc.rs`. // For better maintainability we therefore define this type alias. type Rc = Arc; diff --git a/alloctests/tests/boxed.rs b/alloctests/tests/boxed.rs index 83fd1ef7449a3..a0c3cb55edcc6 100644 --- a/alloctests/tests/boxed.rs +++ b/alloctests/tests/boxed.rs @@ -104,7 +104,7 @@ pub struct ConstAllocator; unsafe impl Allocator for ConstAllocator { fn allocate(&self, layout: Layout) -> Result, AllocError> { match layout.size() { - 0 => Ok(NonNull::slice_from_raw_parts(layout.dangling_ptr(), 0)), + 0 => Ok(layout.dangling_ptr().cast_slice(0)), _ => unsafe { let ptr = core::intrinsics::const_allocate(layout.size(), layout.align()); Ok(NonNull::new_unchecked(ptr as *mut [u8; 0] as *mut [u8])) diff --git a/alloctests/tests/lib.rs b/alloctests/tests/lib.rs index 699a5010282b0..1414835058b9a 100644 --- a/alloctests/tests/lib.rs +++ b/alloctests/tests/lib.rs @@ -41,6 +41,7 @@ #![feature(macro_metavar_expr_concat)] #![feature(vec_peek_mut)] #![feature(vec_try_remove)] +#![feature(ptr_cast_slice)] #![allow(internal_features)] #![deny(fuzzy_provenance_casts)] #![deny(unsafe_op_in_unsafe_fn)] diff --git a/alloctests/tests/rc.rs b/alloctests/tests/rc.rs index bb68eb4ac9e3d..0417206d713ef 100644 --- a/alloctests/tests/rc.rs +++ b/alloctests/tests/rc.rs @@ -87,6 +87,34 @@ fn eq() { assert_eq!(*x.0.borrow(), 0); } +#[test] +fn eq_unsized() { + #[derive(Eq)] + struct TestEq(RefCell, T); + impl PartialEq for TestEq { + fn eq(&self, other: &TestEq) -> bool { + *self.0.borrow_mut() += 1; + *other.0.borrow_mut() += 1; + true + } + } + let x = Rc::>::new(TestEq(RefCell::new(0), [0, 1, 2])) as Rc>; + assert!(x == x); + assert!(!(x != x)); + assert_eq!(*x.0.borrow(), 0); +} + +#[test] +fn eq_unsized_slice() { + let a: Rc<[()]> = Rc::new([(); 3]); + let ptr: *const () = Rc::into_raw(a.clone()).cast(); + let b: Rc<[()]> = unsafe { Rc::from_raw(ptr.cast_slice(42)) }; + assert!(a == a); + assert!(!(a != a)); + assert!(a != b); + assert!(!(a == b)); +} + const SHARED_ITER_MAX: u16 = 100; fn assert_trusted_len(_: &I) {} diff --git a/alloctests/tests/str.rs b/alloctests/tests/str.rs index c0bcdb8500af6..dca2c49249aff 100644 --- a/alloctests/tests/str.rs +++ b/alloctests/tests/str.rs @@ -164,7 +164,7 @@ fn test_join_for_different_lengths_with_long_separator() { } #[test] -fn test_join_issue_80335() { +fn test_join_inconsistent_borrow_shrink() { use core::borrow::Borrow; use core::cell::Cell; @@ -191,7 +191,26 @@ fn test_join_issue_80335() { } let arr: [WeirdBorrow; 3] = Default::default(); - test_join!("0-0-0", arr, "-"); + test_join!("123456-0-0", arr, "-"); +} + +#[test] +#[should_panic(expected = "mid > len")] +fn test_join_inconsistent_borrow_grow() { + use std::borrow::Borrow; + use std::cell::Cell; + + struct E(Cell); + + impl Borrow for E { + fn borrow(&self) -> &str { + let count = self.0.get(); + self.0.set(count + 1); + if count == 0 { "" } else { "longer string" } + } + } + + let _s = [E(Cell::new(0)), E(Cell::new(0))].join(""); } #[test] @@ -2329,6 +2348,7 @@ fn utf8_char_counts() { .flat_map(|n| n - spread..=n + spread) .collect::>(); if cfg!(not(miri)) { + // Miri is too slow reps.extend([1024, 1 << 16].iter().copied().flat_map(|n| n - spread..=n + spread)); } let counts = if cfg!(miri) { 0..1 } else { 0..8 }; diff --git a/alloctests/tests/sync.rs b/alloctests/tests/sync.rs index 6d3ab1b1d11e1..5742855768c70 100644 --- a/alloctests/tests/sync.rs +++ b/alloctests/tests/sync.rs @@ -469,8 +469,6 @@ fn test_weak_count_locked() { while !a2.load(SeqCst) { let n = Arc::weak_count(&a2); assert!(n < 2, "bad weak count: {}", n); - #[cfg(miri)] // Miri's scheduler does not guarantee liveness, and thus needs this hint. - std::hint::spin_loop(); } t.join().unwrap(); } diff --git a/alloctests/tests/vec.rs b/alloctests/tests/vec.rs index db7da0db47d74..54bdc4c19cfae 100644 --- a/alloctests/tests/vec.rs +++ b/alloctests/tests/vec.rs @@ -1651,13 +1651,17 @@ fn extract_if_unconsumed() { #[test] fn extract_if_debug() { - let mut vec = vec![1, 2]; - let mut drain = vec.extract_if(.., |&mut x| x % 2 != 0); - assert!(format!("{drain:?}").contains("Some(1)")); - drain.next(); - assert!(format!("{drain:?}").contains("Some(2)")); - drain.next(); - assert!(format!("{drain:?}").contains("None")); + let mut vec = vec![1, 2, 3, 4, 5, 6, 7, 8]; + let mut drain = vec.extract_if(1..5, |&mut x| x % 2 != 0); + assert_eq!( + format!("{drain:?}"), + "ExtractIf { retained: [1], remainder: [2, 3, 4, 5], skipped_tail: [6, 7, 8], .. }" + ); + drain.next().unwrap(); + assert_eq!( + format!("{drain:?}"), + "ExtractIf { retained: [1, 2], remainder: [4, 5], skipped_tail: [6, 7, 8], .. }" + ); } #[test] @@ -2565,7 +2569,7 @@ fn test_box_zero_allocator() { } else { unsafe { std::alloc::alloc(layout) } }; - Ok(NonNull::slice_from_raw_parts(NonNull::new(ptr).ok_or(AllocError)?, layout.size())) + Ok(NonNull::new(ptr).ok_or(AllocError)?.cast_slice(layout.size())) } unsafe fn deallocate(&self, ptr: NonNull, layout: Layout) { diff --git a/compiler-builtins/.editorconfig b/compiler-builtins/.editorconfig index f0735cedfbd6b..23a4d23f28200 100644 --- a/compiler-builtins/.editorconfig +++ b/compiler-builtins/.editorconfig @@ -1,5 +1,3 @@ -# EditorConfig helps developers define and maintain consistent -# coding styles between different editors and IDEs # editorconfig.org root = true @@ -12,5 +10,5 @@ insert_final_newline = true indent_style = space indent_size = 4 -[*.yml] +[*.{yaml,yml}] indent_size = 2 diff --git a/compiler-builtins/.github/renovate.json5 b/compiler-builtins/.github/renovate.json5 new file mode 100644 index 0000000000000..7d18fd573d6d8 --- /dev/null +++ b/compiler-builtins/.github/renovate.json5 @@ -0,0 +1,37 @@ +{ + $schema: "https://docs.renovatebot.com/renovate-schema.json", + extends: [ + "config:recommended", + ":maintainLockFilesMonthly", + "helpers:pinGitHubActionDigestsToSemver" + ], + packageRules: [ + { + matchCategories: [ + "rust" + ], + matchJsonata: [ + "isBreaking != true" + ], + // Disable non-breaking change updates because they + // are updated periodically with lockfile maintainance. + enabled: false, + }, + { + matchManagers: [ + "github-actions" + ], + // Every month + schedule: "* 0 1 * *", + groupName: "Github Actions", + } + ], + // Receive any update that fixes security vulnerabilities. + // We need this because we disabled "patch" updates for Rust. + // Note: You need to enable "Dependabot alerts" in "Code security" GitHub + // Settings to receive security updates. + // See https://docs.renovatebot.com/configuration-options/#vulnerabilityalerts + vulnerabilityAlerts: { + enabled: true, + }, +} diff --git a/compiler-builtins/.github/workflows/main.yaml b/compiler-builtins/.github/workflows/main.yaml index 261b1619f1c5f..2729b8fa5d5c3 100644 --- a/compiler-builtins/.github/workflows/main.yaml +++ b/compiler-builtins/.github/workflows/main.yaml @@ -1,4 +1,5 @@ name: CI +permissions: {} on: push: { branches: [main] } pull_request: @@ -10,6 +11,7 @@ concurrency: env: CARGO_TERM_COLOR: always + LIBM_BUILD_VERBOSE: true RUSTDOCFLAGS: -Dwarnings RUSTFLAGS: -Dwarnings RUST_BACKTRACE: full @@ -28,8 +30,9 @@ jobs: extensive_matrix: ${{ steps.script.outputs.extensive_matrix }} may_skip_libm_ci: ${{ steps.script.outputs.may_skip_libm_ci }} steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: + persist-credentials: false fetch-depth: 500 - name: Fetch pull request ref run: git fetch origin "$GITHUB_REF:$GITHUB_REF" @@ -42,6 +45,9 @@ jobs: test: name: Build and test timeout-minutes: 60 + # NOTE: self-hosted riscv64 runners are experimental and may be flaky. + # Do not block CI on failures from this platform for now. + continue-on-error: ${{ contains(matrix.os, 'self-hosted') }} strategy: fail-fast: false matrix: @@ -72,6 +78,9 @@ jobs: os: ubuntu-24.04 - target: powerpc64le-unknown-linux-gnu os: ubuntu-24.04-ppc64le + # FIXME(ci): re-enable these once more capacity is avialable + # - target: riscv64gc-unknown-linux-gnu + # os: ["self-hosted", "linux", "riscv64"] - target: riscv64gc-unknown-linux-gnu os: ubuntu-24.04 - target: s390x-unknown-linux-gnu @@ -104,53 +113,58 @@ jobs: needs: [calculate_vars] env: BUILD_ONLY: ${{ matrix.build_only }} + JOB_TARGET: ${{ matrix.target }} + JOB_CHANNEL: ${{ matrix.channel }} MAY_SKIP_LIBM_CI: ${{ needs.calculate_vars.outputs.may_skip_libm_ci }} + RUN_IN_DOCKER: ${{ matrix.os == 'ubuntu-24.04' }} steps: - - name: Print $HOME + - name: Print runner information shell: bash run: | set -x - echo "${HOME:-not found}" + uname -a + lscpu || (sysctl -a | grep cpu) || true + echo "home: ${HOME:-not found}" pwd - printenv - - name: Print runner information - run: uname -a # Native ppc and s390x runners don't have rustup by default - name: Install rustup if: matrix.os == 'ubuntu-24.04-ppc64le' || matrix.os == 'ubuntu-24.04-s390x' run: sudo apt-get update && sudo apt-get install -y rustup - - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } - name: Install Rust (rustup) shell: bash run: | channel="nightly" # Account for channels that have required components (MinGW) - [ -n "${{ matrix.channel }}" ] && channel="${{ matrix.channel }}" + [ -n "$JOB_CHANNEL" ] && channel="$JOB_CHANNEL" rustup update "$channel" --no-self-update rustup default "$channel" - rustup target add "${{ matrix.target }}" + rustup target add "$JOB_TARGET" - - uses: taiki-e/install-action@nextest + - uses: taiki-e/install-action@920ab1831fbf4fb3ef75c8ead83556c918bb7290 # v2.79.8 + with: + tool: nextest@0.9.131 - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@c19371144df3bb44fab255c43d04cbc2ab54d1c4 # v2.9.1 with: key: ${{ matrix.target }} - name: Cache Docker layers - uses: actions/cache@v4 - if: matrix.os == 'ubuntu-24.04' + uses: actions/cache@668228422ae6a00e4ad889ee87cd7109ec5666a7 # v5.0.4 + if: ${{ env.RUN_IN_DOCKER == 'true' }} with: path: /tmp/.buildx-cache key: ${{ matrix.target }}-buildx-${{ github.sha }} restore-keys: ${{ matrix.target }}-buildx- # Configure buildx to use Docker layer caching - - uses: docker/setup-buildx-action@v3 - if: matrix.os == 'ubuntu-24.04' + - uses: docker/setup-buildx-action@4d04d5d9486b7bd6fa91e7baf45bbb4f8b9deedd # v4 + if: ${{ env.RUN_IN_DOCKER == 'true' }} - name: Cache compiler-rt id: cache-compiler-rt - uses: actions/cache@v4 + uses: actions/cache@668228422ae6a00e4ad889ee87cd7109ec5666a7 # v5.0.4 with: path: compiler-rt key: ${{ runner.os }}-compiler-rt-${{ hashFiles('ci/download-compiler-rt.sh') }} @@ -166,19 +180,22 @@ jobs: shell: bash - name: Verify API list - if: matrix.os == 'ubuntu-24.04' - run: python3 etc/update-api-list.py --check + if: matrix.os == 'ubuntu-24.04' || contains(matrix.os, 'self-hosted') + run: | + # Must be run on the host (not in Docker) because git and fs access is required. + python3 etc/update-api-list.py --check + cargo test -p update-api-list # Non-linux tests just use our raw script - name: Run locally - if: matrix.os != 'ubuntu-24.04' + if: ${{ env.RUN_IN_DOCKER != 'true' }} shell: bash - run: ./ci/run.sh ${{ matrix.target }} + run: ./ci/run.sh "$JOB_TARGET" # Otherwise we use our docker containers to run builds - name: Run in Docker - if: matrix.os == 'ubuntu-24.04' - run: ./ci/run-docker.sh ${{ matrix.target }} + if: ${{ env.RUN_IN_DOCKER == 'true' }} + run: ./ci/run-docker.sh "$JOB_TARGET" - name: Print test logs if available if: always() @@ -189,7 +206,7 @@ jobs: # https://github.com/docker/build-push-action/issues/252 # https://github.com/moby/buildkit/issues/1896 - name: Move Docker cache - if: matrix.os == 'ubuntu-24.04' + if: ${{ env.RUN_IN_DOCKER == 'true' }} run: | rm -rf /tmp/.buildx-cache mv /tmp/.buildx-cache-new /tmp/.buildx-cache @@ -199,30 +216,43 @@ jobs: runs-on: ubuntu-24.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } # Unlike rustfmt, stable clippy does not work on code with nightly features. - name: Install nightly `clippy` run: | rustup update nightly --no-self-update rustup default nightly rustup component add clippy - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@c19371144df3bb44fab255c43d04cbc2ab54d1c4 # v2.9.1 - name: Download musl source run: ./ci/update-musl.sh - run: cargo clippy --workspace --all-targets + zizmor: + name: Zizmor (Static analysis for GitHub Actions) + runs-on: ubuntu-24.04 + permissions: + security-events: write + timeout-minutes: 10 + steps: + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } + - uses: zizmorcore/zizmor-action@71321a20a9ded102f6e9ce5718a2fcec2c4f70d8 # v0.5.2 + build-custom: name: Build custom target runs-on: ubuntu-24.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } - name: Install Rust run: | rustup update nightly --no-self-update rustup default nightly rustup component add rust-src - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@c19371144df3bb44fab255c43d04cbc2ab54d1c4 # v2.9.1 - run: | # Ensure we can build with custom target.json files (these can interact # poorly with build scripts) @@ -237,13 +267,14 @@ jobs: runs-on: ubuntu-24.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } - name: Install Rust run: | rustup update nightly --no-self-update rustup default nightly rustup component add rust-src - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@c19371144df3bb44fab255c43d04cbc2ab54d1c4 # v2.9.1 - run: | cargo build -p compiler_builtins -p libm \ --target etc/thumbv6-none-eabi.json \ @@ -252,23 +283,30 @@ jobs: benchmarks: name: Benchmarks - timeout-minutes: 20 + timeout-minutes: 30 strategy: fail-fast: false matrix: include: - - target: x86_64-unknown-linux-gnu - os: ubuntu-24.04 - target: aarch64-unknown-linux-gnu os: ubuntu-24.04-arm + - target: i686-unknown-linux-gnu + os: ubuntu-24.04 + - target: x86_64-unknown-linux-gnu + os: ubuntu-24.04 runs-on: ${{ matrix.os }} + env: + JOB_TARGET: ${{ matrix.target }} steps: - - uses: actions/checkout@master - - uses: taiki-e/install-action@cargo-binstall + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } + - uses: taiki-e/install-action@920ab1831fbf4fb3ef75c8ead83556c918bb7290 # v2.79.8 + with: + tool: cargo-binstall@1.17.7 - name: Set up dependencies - run: ./ci/install-bench-deps.sh - - uses: Swatinem/rust-cache@v2 + run: ./ci/install-bench-deps.sh "$JOB_TARGET" + - uses: Swatinem/rust-cache@c19371144df3bb44fab255c43d04cbc2ab54d1c4 # v2.9.1 with: key: ${{ matrix.target }} - name: Download musl source @@ -278,17 +316,14 @@ jobs: env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} PR_NUMBER: ${{ github.event.pull_request.number }} - run: ./ci/bench-icount.sh ${{ matrix.target }} + run: ./ci/bench-icount.sh "$JOB_TARGET" - name: Upload the benchmark baseline - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@bbbca2ddaa5d8feaa63e36b76fdaad77386f024f # v7.0.0 with: name: ${{ env.BASELINE_NAME }} path: ${{ env.BASELINE_NAME }}.tar.xz - - name: Run wall time benchmarks - run: ./ci/bench-walltime.sh - - name: Print test logs if available if: always() run: if [ -f "target/test-log.txt" ]; then cat target/test-log.txt; fi @@ -299,15 +334,14 @@ jobs: runs-on: ubuntu-24.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } - name: Install Rust (rustup) - # FIXME(ci): not working in the 2026-02-11 nightly - # https://rust-lang.zulipchat.com/#narrow/channel/269128-miri/topic/build-script-build.20contains.20outdated.20or.20invalid.20JSON/with/573426109 - run: rustup update nightly-2026-02-10 --no-self-update && rustup default nightly-2026-02-10 + run: rustup update nightly --no-self-update && rustup default nightly shell: bash - run: rustup component add miri - run: cargo miri setup - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@c19371144df3bb44fab255c43d04cbc2ab54d1c4 # v2.9.1 - run: ./ci/miri.sh msrv: @@ -317,13 +351,14 @@ jobs: env: RUSTFLAGS: # No need to check warnings on old MSRV, unset `-Dwarnings` steps: - - uses: actions/checkout@master + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } - name: Install Rust run: | msrv="$(perl -ne 'print if s/rust-version\s*=\s*"(.*)"/\1/g' libm/Cargo.toml)" echo "MSRV: $msrv" rustup update "$msrv" --no-self-update && rustup default "$msrv" - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@c19371144df3bb44fab255c43d04cbc2ab54d1c4 # v2.9.1 - run: | # FIXME(msrv): Remove the workspace Cargo.toml so 1.63 cargo doesn't see # `edition = "2024"` and get spooked. @@ -335,7 +370,8 @@ jobs: runs-on: ubuntu-24.04 timeout-minutes: 10 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } - name: Install nightly `rustfmt` run: rustup set profile minimal && rustup default nightly && rustup component add rustfmt - run: cargo fmt -- --check @@ -358,12 +394,13 @@ jobs: env: TO_TEST: ${{ matrix.to_test }} steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: { persist-credentials: false } - name: Install Rust run: | rustup update nightly --no-self-update rustup default nightly - - uses: Swatinem/rust-cache@v2 + - uses: Swatinem/rust-cache@c19371144df3bb44fab255c43d04cbc2ab54d1c4 # v2.9.1 - name: download musl source run: ./ci/update-musl.sh - name: Run extensive tests @@ -383,13 +420,16 @@ jobs: - msrv - rustfmt - test + - zizmor runs-on: ubuntu-24.04 timeout-minutes: 10 # GitHub branch protection is exceedingly silly and treats "jobs skipped because a dependency # failed" as success. So we have to do some contortions to ensure the job fails if any of its # dependencies fails. if: always() # make sure this is never "skipped" + env: + NEEDS: ${{ toJson(needs) }} steps: # Manually check the status of all dependencies. `if: failure()` does not work. - name: check if any dependency failed - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}' + run: jq --exit-status 'all(.result == "success")' <<< "$NEEDS" diff --git a/compiler-builtins/.github/workflows/publish.yaml b/compiler-builtins/.github/workflows/publish.yaml index d6f1dc398e8ec..aa742914a5344 100644 --- a/compiler-builtins/.github/workflows/publish.yaml +++ b/compiler-builtins/.github/workflows/publish.yaml @@ -11,15 +11,15 @@ jobs: release-plz: name: Release-plz runs-on: ubuntu-24.04 + environment: publish steps: - - name: Checkout repository - uses: actions/checkout@v4 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: + persist-credentials: false fetch-depth: 0 - name: Install Rust (rustup) run: rustup update nightly --no-self-update && rustup default nightly - name: Run release-plz - uses: MarcoIeni/release-plz-action@v0.5 + uses: release-plz/action@1528104d2ca23787631a1c1f022abb64b34c1e11 # v0.5 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - CARGO_REGISTRY_TOKEN: ${{ secrets.CARGO_REGISTRY_TOKEN }} diff --git a/compiler-builtins/.github/workflows/rustc-pull.yml b/compiler-builtins/.github/workflows/rustc-pull.yml index 8e88213332de4..ff8305d3729fd 100644 --- a/compiler-builtins/.github/workflows/rustc-pull.yml +++ b/compiler-builtins/.github/workflows/rustc-pull.yml @@ -5,7 +5,7 @@ on: workflow_dispatch: schedule: # Run at 04:00 UTC every Monday and Thursday - - cron: '0 4 * * 1,4' + - cron: "0 4 * * 1,4" env: JOSH_SYNC_VERBOSE: true @@ -13,15 +13,19 @@ env: jobs: pull: if: github.repository == 'rust-lang/compiler-builtins' - uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main + uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@8970a6eb3a6095db68e4d765b3b5fba5e9c42cf6 # main with: github-app-id: ${{ vars.APP_CLIENT_ID }} + pr-author: "workflows-compiler-builtins[bot]" # https://rust-lang.zulipchat.com/#narrow/channel/219381-t-libs/topic/compiler-builtins.20subtree.20sync.20automation/with/528482375 zulip-stream-id: 219381 - zulip-topic: 'compiler-builtins subtree sync automation' + zulip-topic: "compiler-builtins subtree sync automation" zulip-bot-email: "compiler-builtins-ci-bot@rust-lang.zulipchat.com" pr-base-branch: main branch-name: rustc-pull secrets: zulip-api-token: ${{ secrets.ZULIP_API_TOKEN }} github-app-secret: ${{ secrets.APP_PRIVATE_KEY }} + permissions: + contents: write + pull-requests: write diff --git a/compiler-builtins/Cargo.lock b/compiler-builtins/Cargo.lock index 7a3e9a38430b6..ed27483d44b4e 100644 --- a/compiler-builtins/Cargo.lock +++ b/compiler-builtins/Cargo.lock @@ -34,9 +34,9 @@ checksum = "4b46cbb362ab8752921c97e041f5e366ee6297bd428a31275b9fcf1e380f7299" [[package]] name = "anstream" -version = "0.6.21" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "43d5b281e737544384e969a5ccad3f1cdd24b48086a0fc1b2a5262a26b8f4f4a" +checksum = "824a212faf96e9acacdbd09febd34438f8f711fb84e09a8916013cd7815ca28d" dependencies = [ "anstyle", "anstyle-parse", @@ -49,15 +49,15 @@ dependencies = [ [[package]] name = "anstyle" -version = "1.0.13" +version = "1.0.14" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5192cca8006f1fd4f7237516f40fa183bb07f8fbdfedaa0036de5ea9b0b45e78" +checksum = "940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000" [[package]] name = "anstyle-parse" -version = "0.2.7" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4e7644824f0aa2c7b9384579234ef10eb7efb6a0deb83f9630a49594dd9c15c2" +checksum = "52ce7f38b242319f7cabaa6813055467063ecdc9d355bbb4ce0c68908cd8130e" dependencies = [ "utf8parse", ] @@ -68,7 +68,7 @@ version = "1.1.5" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc" dependencies = [ - "windows-sys 0.61.2", + "windows-sys", ] [[package]] @@ -79,20 +79,24 @@ checksum = "291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d" dependencies = [ "anstyle", "once_cell_polyfill", - "windows-sys 0.61.2", + "windows-sys", ] [[package]] name = "anyhow" -version = "1.0.101" +version = "1.0.102" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5f0e0fee31ef5ed1ba1316088939cea399010ed7731dba877ed44aeb407a75ea" +checksum = "7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c" + +[[package]] +name = "api-list-common" +version = "0.1.0" [[package]] name = "assert_cmd" -version = "2.1.2" +version = "2.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9c5bcfa8749ac45dd12cb11055aeeb6b27a3895560d60d71e3c23bf979e60514" +checksum = "39bae1d3fa576f7c6519514180a72559268dd7d1fe104070956cb687bc6673bd" dependencies = [ "anstyle", "bstr", @@ -116,19 +120,20 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "be5eb007b7cacc6c660343e96f650fedf4b5a77512399eb952ca6642cf8d13f7" [[package]] -name = "bincode" -version = "1.3.3" +name = "bincode-next" +version = "2.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b1f45e9417d87227c7a56d22e471c6206462cba514c7590c09aff4cf6d1ddcad" +checksum = "dbe9e7e6d14aeb39557f226bff158a30e367fac279d0e69b8b42fb41999f9a86" dependencies = [ "serde", + "unty-next", ] [[package]] name = "bitflags" -version = "2.11.0" +version = "2.11.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af" +checksum = "c4512299f36f043ab09a583e57bceb5a5aab7a73db1805848e8fef3c9e8c78b3" [[package]] name = "bstr" @@ -151,16 +156,13 @@ dependencies = [ "paste", "rand_xoshiro", "rustc_apfloat", - "test", - "utest-cortex-m-qemu", - "utest-macros", ] [[package]] name = "bumpalo" -version = "3.19.1" +version = "3.20.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5dd9dc738b7a8311c7ade152424974d8115f2cdad61e8dab8dac9f2362298510" +checksum = "5d20789868f4b01b2f2caec9f5c4e0213b41e3e5702a50157d699ae31ced2fcb" [[package]] name = "cast" @@ -170,9 +172,9 @@ checksum = "37b2a672a2cb129a2e41c10b1224bb368f9f37a2b16b612598138befd7b37eb5" [[package]] name = "cc" -version = "1.2.56" +version = "1.2.61" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "aebf35691d1bfb0ac386a69bac2fde4dd276fb618cf8bf4f5318fe285e821bb2" +checksum = "d16d90359e986641506914ba71350897565610e87ce0ad9e6f28569db3dd5c6d" dependencies = [ "find-msvc-tools", "shlex", @@ -224,9 +226,9 @@ dependencies = [ [[package]] name = "clap" -version = "4.5.58" +version = "4.6.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "63be97961acde393029492ce0be7a1af7e323e6bae9511ebfac33751be5e6806" +checksum = "1ddb117e43bbf7dacf0a4190fef4d345b9bad68dfc649cb349e7d17d28428e51" dependencies = [ "clap_builder", "clap_derive", @@ -234,9 +236,9 @@ dependencies = [ [[package]] name = "clap_builder" -version = "4.5.58" +version = "4.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7f13174bda5dfd69d7e947827e5af4b0f2f94a4a3ee92912fba07a66150f21e2" +checksum = "714a53001bf66416adb0e2ef5ac857140e7dc3a0c48fb28b2f10762fc4b5069f" dependencies = [ "anstream", "anstyle", @@ -246,9 +248,9 @@ dependencies = [ [[package]] name = "clap_derive" -version = "4.5.55" +version = "4.6.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a92793da1a46a5f2a02a6f4c46c6496b28c43638adea8306fcb0caa1634f24e5" +checksum = "f2ce8604710f6733aa641a2b3731eaa1e8b3d9973d5e3565da11800813f997a9" dependencies = [ "heck", "proc-macro2", @@ -258,15 +260,15 @@ dependencies = [ [[package]] name = "clap_lex" -version = "1.0.0" +version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3a822ea5bc7590f9d40f1ba12c0dc3c2760f3482c6984db1573ad11031420831" +checksum = "c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9" [[package]] name = "colorchoice" -version = "1.0.4" +version = "1.0.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b05b61dc5112cbb17e4b6cd61790d9845d13888356391624cbe7e41efeac1e75" +checksum = "1d07550c9036bf2ae0c684c4297d503f838287c83c53686d05370d0e139ae570" [[package]] name = "compiler_builtins" @@ -277,14 +279,13 @@ dependencies = [ [[package]] name = "console" -version = "0.16.2" +version = "0.16.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "03e45a4a8926227e4197636ba97a9fc9b00477e9f4bd711395687c5f0734bec4" +checksum = "d64e8af5551369d19cf50138de61f1c42074ab970f74e99be916646777f8fc87" dependencies = [ "encode_unicode", "libc", - "once_cell", - "windows-sys 0.61.2", + "windows-sys", ] [[package]] @@ -391,6 +392,12 @@ dependencies = [ "syn", ] +[[package]] +name = "diff" +version = "0.1.13" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "56254986775e3233ffa9c4d7d3faaf6d36a2c09d30b20687e9f88bc8bafc16c8" + [[package]] name = "difflib" version = "0.4.0" @@ -422,7 +429,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb" dependencies = [ "libc", - "windows-sys 0.61.2", + "windows-sys", ] [[package]] @@ -433,9 +440,9 @@ checksum = "5692dd7b5a1978a5aeb0ce83b7655c58ca8efdcb79d21036ea249da95afec2c6" [[package]] name = "fastrand" -version = "2.3.0" +version = "2.4.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "37909eebbb50d72f9059c3b6d82c0463f2ff062c9e95845c43a6c9c0355411be" +checksum = "9f1f227452a390804cdb637b74a86990f2a7d7ba4b7d5693aac9b4dd6defd8d6" [[package]] name = "find-msvc-tools" @@ -459,6 +466,30 @@ version = "0.1.5" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2" +[[package]] +name = "futures-core" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7e3450815272ef58cec6d564423f6e755e25379b217b0bc688e295ba24df6b1d" + +[[package]] +name = "futures-task" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "037711b3d59c33004d3856fbdc83b99d4ff37a24768fa1be9ce3538a1cde4393" + +[[package]] +name = "futures-util" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "389ca41296e6190b48053de0321d02a77f32f8a5d2461dd38762c0593805c6d6" +dependencies = [ + "futures-core", + "futures-task", + "pin-project-lite", + "slab", +] + [[package]] name = "getopts" version = "0.2.24" @@ -470,9 +501,9 @@ dependencies = [ [[package]] name = "getrandom" -version = "0.4.1" +version = "0.4.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "139ef39800118c7683f2fd3c98c1b23c09ae076556b435f8e9064ae108aaeeec" +checksum = "0de51e6874e94e7bf76d726fc5d13ba782deca734ff60d5bb2fb2607c7406555" dependencies = [ "cfg-if", "js-sys", @@ -484,23 +515,29 @@ dependencies = [ "wasm-bindgen", ] +[[package]] +name = "glob" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0cc23270f6e1808e30a928bdc84dea0b9b4136a8bc82338574f23baf47bbd280" + [[package]] name = "gmp-mpfr-sys" -version = "1.6.8" +version = "1.7.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "60f8970a75c006bb2f8ae79c6768a116dd215fa8346a87aed99bf9d82ca43394" +checksum = "7db155b537cb791b133341f99f68371d86ee7fa4c79aacfbc376d72d23c70531" dependencies = [ "libc", - "windows-sys 0.60.2", + "windows-sys", ] [[package]] name = "gungraun" -version = "0.17.2" +version = "0.19.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "61c1bbe46f51c63bc08a1fac0ee0c530a77c961613a86ecf828ab1b0ffc6687a" +checksum = "a710656785d3ed71a73a1007956874d6ebfdbc2f8660c492bb8d838c91e3f085" dependencies = [ - "bincode", + "bincode-next", "derive_more", "gungraun-macros", "gungraun-runner", @@ -508,9 +545,9 @@ dependencies = [ [[package]] name = "gungraun-macros" -version = "0.7.2" +version = "0.9.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "cdccd089c36fb2ee66ef0eb7b1baa3ce7e7878a8eae682d9c8c368869ff6eca1" +checksum = "4cc6269e89921872ec32af29af3a992618b9bd2ef47cbf3704af476066cb7182" dependencies = [ "derive_more", "proc-macro-error2", @@ -524,9 +561,9 @@ dependencies = [ [[package]] name = "gungraun-runner" -version = "0.17.2" +version = "0.19.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6da6487203fa53ae6b1c8fead642fe79a3199464b0dd1337635594d675a9ac05" +checksum = "12016920cc6ba0a8aefe276c8f19421a3bf7a125385e25697658b9dd66bde024" dependencies = [ "serde", ] @@ -553,9 +590,9 @@ dependencies = [ [[package]] name = "hashbrown" -version = "0.16.1" +version = "0.17.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100" +checksum = "4f467dd6dccf739c208452f8014c75c18bb8301b050ad1cfb27153803edb0f51" [[package]] name = "heck" @@ -571,12 +608,12 @@ checksum = "3d3067d79b975e8844ca9eb072e16b31c3c1c36928edf9c6789548c524d0d954" [[package]] name = "indexmap" -version = "2.13.0" +version = "2.14.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017" +checksum = "d466e9454f08e4a911e14806c24e16fba1b4c121d1ea474396f396069cf949d9" dependencies = [ "equivalent", - "hashbrown 0.16.1", + "hashbrown 0.17.0", "serde", "serde_core", ] @@ -610,16 +647,18 @@ dependencies = [ [[package]] name = "itoa" -version = "1.0.17" +version = "1.0.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "92ecc6618181def0457392ccd0ee51198e065e016d1d527a7ac1b6dc7c1f09d2" +checksum = "8f42a60cbdf9a97f5d2305f08a87dc4e09308d1276d28c869c684d7777685682" [[package]] name = "js-sys" -version = "0.3.85" +version = "0.3.97" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8c942ebf8e95485ca0d52d97da7c5a2c387d0e7f0ba4c35e93bfcaee045955b3" +checksum = "a1840c94c045fbcf8ba2812c95db44499f7c64910a912551aaaa541decebcacf" dependencies = [ + "cfg-if", + "futures-util", "once_cell", "wasm-bindgen", ] @@ -632,9 +671,9 @@ checksum = "09edd9e8b54e49e587e4f6295a7d29c3ea94d469cb40ab8ca70b288248a81db2" [[package]] name = "libc" -version = "0.2.182" +version = "0.2.186" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6800badb6cb2082ffd7b6a67e6125bb39f18782f793520caee8cb8846be06112" +checksum = "68ab91017fe16c622486840e4c83c9a37afeff978bd239b5293d61ece587de66" [[package]] name = "libm" @@ -653,6 +692,7 @@ checksum = "b6d2cec3eae94f9f509c767b45932f1ada8350c4bdb85af2fcab4a3c14807981" name = "libm-macros" version = "0.1.0" dependencies = [ + "api-list-common", "heck", "proc-macro2", "quote", @@ -664,6 +704,8 @@ name = "libm-test" version = "0.1.0" dependencies = [ "anyhow", + "api-list-common", + "compiler_builtins", "criterion", "getrandom", "gmp-mpfr-sys", @@ -682,9 +724,9 @@ dependencies = [ [[package]] name = "libtest-mimic" -version = "0.8.1" +version = "0.8.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5297962ef19edda4ce33aaa484386e0a5b3d7f2f4e037cbeee00503ef6b29d33" +checksum = "14e6ba06f0ade6e504aff834d7c34298e5155c6baca353cc6a4aaff2f9fd7f33" dependencies = [ "anstream", "anstyle", @@ -694,9 +736,9 @@ dependencies = [ [[package]] name = "linux-raw-sys" -version = "0.11.0" +version = "0.12.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "df1d3c3b53da64cf5760482273a98e575c651a67eec7f77df96b5b642de8f039" +checksum = "32a66949e030da00e8c7d4434b251670a91556f4144941d37452769c25d58a53" [[package]] name = "log" @@ -750,21 +792,21 @@ dependencies = [ [[package]] name = "object" -version = "0.38.1" +version = "0.39.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "271638cd5fa9cca89c4c304675ca658efc4e64a66c716b7cfe1afb4b9611dbbc" +checksum = "2e5a6c098c7a3b6547378093f5cc30bc54fd361ce711e05293a5cc589562739b" dependencies = [ "flate2", "memchr", "ruzstd", - "wasmparser 0.243.0", + "wasmparser 0.247.0", ] [[package]] name = "once_cell" -version = "1.21.3" +version = "1.21.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d" +checksum = "9f7c3e4beb33f85d45ae3e3a1792185706c8e16d043238c593331cc7cd313b50" [[package]] name = "once_cell_polyfill" @@ -798,6 +840,12 @@ version = "1.0.15" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a" +[[package]] +name = "pin-project-lite" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a89322df9ebe1c1578d689c92318e070967d1042b512afbe49518723f4e6d5cd" + [[package]] name = "plotters" version = "0.3.7" @@ -868,6 +916,16 @@ dependencies = [ "termtree", ] +[[package]] +name = "pretty_assertions" +version = "1.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3ae130e2f271fbc2ac3a40fb1d07180839cdbbe443c7a27e1e3c13c5cac0116d" +dependencies = [ + "diff", + "yansi", +] + [[package]] name = "prettyplease" version = "0.2.37" @@ -911,24 +969,24 @@ dependencies = [ [[package]] name = "quote" -version = "1.0.44" +version = "1.0.45" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "21b2ebcf727b7760c461f091f9f0f539b77b8e87f2fd88131e7f1b433b3cece4" +checksum = "41f2619966050689382d2b44f664f4bc593e129785a36d6ee376ddf37259b924" dependencies = [ "proc-macro2", ] [[package]] name = "r-efi" -version = "5.3.0" +version = "6.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f" +checksum = "f8dcc9c7d52a811697d2151c701e0d08956f92b0e24136cf4cf27b57a6a0d9bf" [[package]] name = "rand" -version = "0.10.0" +version = "0.10.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bc266eb313df6c5c09c1c7b1fbe2510961e5bcd3add930c1e31f7ed9da0feff8" +checksum = "d2e8e8bcc7961af1fdac401278c6a831614941f6164ee3bf4ce61b7edb162207" dependencies = [ "chacha20", "getrandom", @@ -947,9 +1005,9 @@ dependencies = [ [[package]] name = "rand_core" -version = "0.10.0" +version = "0.10.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0c8d0fd677905edcbeedbf2edb6494d676f0e98d54d5cf9bda0b061cb8fb8aba" +checksum = "63b8176103e19a2643978565ca18b50549f6101881c443590420e4dc998a3c69" [[package]] name = "rand_xoshiro" @@ -962,9 +1020,9 @@ dependencies = [ [[package]] name = "rayon" -version = "1.11.0" +version = "1.12.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "368f01d005bf8fd9b1206fb6fa653e6c4a81ceb1466406b81792d87c5677a58f" +checksum = "fb39b166781f92d482534ef4b4b1b2568f42613b53e5b6c160e24cfbfa30926d" dependencies = [ "either", "rayon-core", @@ -1005,15 +1063,15 @@ dependencies = [ [[package]] name = "regex-syntax" -version = "0.8.9" +version = "0.8.10" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a96887878f22d7bad8a3b6dc5b7440e0ada9a245242924394987b21cf2210a4c" +checksum = "dc897dd8d9e8bd1ed8cdad82b5966c3e0ecae09fb1907d58efaa013543185d0a" [[package]] name = "rug" -version = "1.28.1" +version = "1.30.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "de190ec858987c79cad4da30e19e546139b3339331282832af004d0ea7829639" +checksum = "07a8857882aec59d27254b02481c709327c13de6fad1da60bfc4f9783eaaa61e" dependencies = [ "az", "gmp-mpfr-sys", @@ -1042,15 +1100,15 @@ dependencies = [ [[package]] name = "rustix" -version = "1.1.3" +version = "1.1.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "146c9e247ccc180c1f61615433868c99f3de3ae256a30a43b49f67c2d9171f34" +checksum = "b6fe4565b9518b83ef4f91bb47ce29620ca828bd32cb7e408f0062e9930ba190" dependencies = [ "bitflags", "errno", "libc", "linux-raw-sys", - "windows-sys 0.61.2", + "windows-sys", ] [[package]] @@ -1077,17 +1135,11 @@ dependencies = [ "winapi-util", ] -[[package]] -name = "sc" -version = "0.2.7" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "010e18bd3bfd1d45a7e666b236c78720df0d9a7698ebaa9c1c559961eb60a38b" - [[package]] name = "semver" -version = "1.0.27" +version = "1.0.28" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d767eb0aabc880b29956c35734170f26ed551a859dbd361d140cdbeca61ab1e2" +checksum = "8a7852d02fc848982e0c167ef163aaff9cd91dc640ba85e263cb1ce46fae51cd" [[package]] name = "serde" @@ -1140,9 +1192,15 @@ checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64" [[package]] name = "simd-adler32" -version = "0.3.8" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "703d5c7ef118737c72f1af64ad2f6f8c5e1921f818cdcb97b8fe6fc69bf66214" + +[[package]] +name = "slab" +version = "0.4.12" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e320a6c5ad31d271ad523dcf3ad13e2767ad8b1cb8f047f75a8aeaf8da139da2" +checksum = "0c790de23124f9ab44544d7ac05d60440adc586479ce501c1d6d7da3cd8c9cf5" [[package]] name = "smallvec" @@ -1171,9 +1229,9 @@ dependencies = [ [[package]] name = "syn" -version = "2.0.116" +version = "2.0.117" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3df424c70518695237746f84cede799c9c58fcb37450d7b23716568cc8bc69cb" +checksum = "e665b8803e7b1d2a727f4023456bbbbe74da67099c585258af0ad9c5013b9b99" dependencies = [ "proc-macro2", "quote", @@ -1182,15 +1240,15 @@ dependencies = [ [[package]] name = "tempfile" -version = "3.25.0" +version = "3.27.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0136791f7c95b1f6dd99f9cc786b91bb81c3800b639b3478e561ddb7be95e5f1" +checksum = "32497e9a4c7b38532efcdebeef879707aa9f794296a4f0244f6f69e9bc8574bd" dependencies = [ "fastrand", "getrandom", "once_cell", "rustix", - "windows-sys 0.61.2", + "windows-sys", ] [[package]] @@ -1199,11 +1257,6 @@ version = "0.5.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "8f50febec83f5ee1df3015341d8bd429f2d1cc62bcba7ea2076759d315084683" -[[package]] -name = "test" -version = "0.1.0" -source = "git+https://github.com/japaric/utest#e32073e2b078e3bee46001c13ae4c1acf368d762" - [[package]] name = "tinytemplate" version = "1.2.1" @@ -1245,17 +1298,21 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "81e544489bf3d8ef66c953931f56617f423cd4b5494be343d9b9d3dda037b9a3" [[package]] -name = "utest-cortex-m-qemu" -version = "0.1.0" -source = "git+https://github.com/japaric/utest#e32073e2b078e3bee46001c13ae4c1acf368d762" -dependencies = [ - "sc", -] +name = "unty-next" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9fa66022bbd1ab992fad72bdedcfd07a0023b6f5ecc83d50121e39e3a3caed41" [[package]] -name = "utest-macros" +name = "update-api-list" version = "0.1.0" -source = "git+https://github.com/japaric/utest#e32073e2b078e3bee46001c13ae4c1acf368d762" +dependencies = [ + "api-list-common", + "getopts", + "glob", + "pretty_assertions", + "regex", +] [[package]] name = "utf8parse" @@ -1296,11 +1353,11 @@ dependencies = [ [[package]] name = "wasip2" -version = "1.0.2+wasi-0.2.9" +version = "1.0.3+wasi-0.2.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9517f9239f02c069db75e65f174b3da828fe5f5b945c4dd26bd25d89c03ebcf5" +checksum = "20064672db26d7cdc89c7798c48a0fdfac8213434a1186e5ef29fd560ae223d6" dependencies = [ - "wit-bindgen", + "wit-bindgen 0.57.1", ] [[package]] @@ -1309,14 +1366,14 @@ version = "0.4.0+wasi-0.3.0-rc-2026-01-06" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "5428f8bf88ea5ddc08faddef2ac4a67e390b88186c703ce6dbd955e1c145aca5" dependencies = [ - "wit-bindgen", + "wit-bindgen 0.51.0", ] [[package]] name = "wasm-bindgen" -version = "0.2.108" +version = "0.2.120" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "64024a30ec1e37399cf85a7ffefebdb72205ca1c972291c51512360d90bd8566" +checksum = "df52b6d9b87e0c74c9edfa1eb2d9bf85e5d63515474513aa50fa181b3c4f5db1" dependencies = [ "cfg-if", "once_cell", @@ -1327,9 +1384,9 @@ dependencies = [ [[package]] name = "wasm-bindgen-macro" -version = "0.2.108" +version = "0.2.120" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "008b239d9c740232e71bd39e8ef6429d27097518b6b30bdf9086833bd5b6d608" +checksum = "78b1041f495fb322e64aca85f5756b2172e35cd459376e67f2a6c9dffcedb103" dependencies = [ "quote", "wasm-bindgen-macro-support", @@ -1337,9 +1394,9 @@ dependencies = [ [[package]] name = "wasm-bindgen-macro-support" -version = "0.2.108" +version = "0.2.120" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5256bae2d58f54820e6490f9839c49780dff84c65aeab9e772f15d5f0e913a55" +checksum = "9dcd0ff20416988a18ac686d4d4d0f6aae9ebf08a389ff5d29012b05af2a1b41" dependencies = [ "bumpalo", "proc-macro2", @@ -1350,9 +1407,9 @@ dependencies = [ [[package]] name = "wasm-bindgen-shared" -version = "0.2.108" +version = "0.2.120" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1f01b580c9ac74c8d8f0c0e4afb04eeef2acf145458e52c03845ee9cd23e3d12" +checksum = "49757b3c82ebf16c57d69365a142940b384176c24df52a087fb748e2085359ea" dependencies = [ "unicode-ident", ] @@ -1381,30 +1438,30 @@ dependencies = [ [[package]] name = "wasmparser" -version = "0.243.0" +version = "0.244.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f6d8db401b0528ec316dfbe579e6ab4152d61739cfe076706d2009127970159d" +checksum = "47b807c72e1bac69382b3a6fb3dbe8ea4c0ed87ff5629b8685ae6b9a611028fe" dependencies = [ "bitflags", + "hashbrown 0.15.5", + "indexmap", + "semver", ] [[package]] name = "wasmparser" -version = "0.244.0" +version = "0.247.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "47b807c72e1bac69382b3a6fb3dbe8ea4c0ed87ff5629b8685ae6b9a611028fe" +checksum = "8e6fb4c2bee46c5ea4d40f8cdb5c131725cd976718ec56f1c8e82fbde5fa2a80" dependencies = [ "bitflags", - "hashbrown 0.15.5", - "indexmap", - "semver", ] [[package]] name = "web-sys" -version = "0.3.85" +version = "0.3.97" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "312e32e551d92129218ea9a2452120f4aabc03529ef03e4d0d82fb2780608598" +checksum = "2eadbac71025cd7b0834f20d1fe8472e8495821b4e9801eb0a60bd1f19827602" dependencies = [ "js-sys", "wasm-bindgen", @@ -1442,7 +1499,7 @@ version = "0.1.11" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "c2a7b1c03c876122aa43f3020e6c3c3ee5c05081c9a00739faf7503aeba10d22" dependencies = [ - "windows-sys 0.61.2", + "windows-sys", ] [[package]] @@ -1457,15 +1514,6 @@ version = "0.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5" -[[package]] -name = "windows-sys" -version = "0.60.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2f500e4d28234f72040990ec9d39e3a6b950f9f22d3dba18416c35882612bcb" -dependencies = [ - "windows-targets", -] - [[package]] name = "windows-sys" version = "0.61.2" @@ -1475,71 +1523,6 @@ dependencies = [ "windows-link", ] -[[package]] -name = "windows-targets" -version = "0.53.5" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4945f9f551b88e0d65f3db0bc25c33b8acea4d9e41163edf90dcd0b19f9069f3" -dependencies = [ - "windows-link", - "windows_aarch64_gnullvm", - "windows_aarch64_msvc", - "windows_i686_gnu", - "windows_i686_gnullvm", - "windows_i686_msvc", - "windows_x86_64_gnu", - "windows_x86_64_gnullvm", - "windows_x86_64_msvc", -] - -[[package]] -name = "windows_aarch64_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a9d8416fa8b42f5c947f8482c43e7d89e73a173cead56d044f6a56104a6d1b53" - -[[package]] -name = "windows_aarch64_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b9d782e804c2f632e395708e99a94275910eb9100b2114651e04744e9b125006" - -[[package]] -name = "windows_i686_gnu" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "960e6da069d81e09becb0ca57a65220ddff016ff2d6af6a223cf372a506593a3" - -[[package]] -name = "windows_i686_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fa7359d10048f68ab8b09fa71c3daccfb0e9b559aed648a8f95469c27057180c" - -[[package]] -name = "windows_i686_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1e7ac75179f18232fe9c285163565a57ef8d3c89254a30685b57d83a38d326c2" - -[[package]] -name = "windows_x86_64_gnu" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9c3842cdd74a865a8066ab39c8a7a473c0778a3f29370b5fd6b4b9aa7df4a499" - -[[package]] -name = "windows_x86_64_gnullvm" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0ffa179e2d07eee8ad8f57493436566c7cc30ac536a3379fdf008f47f6bb7ae1" - -[[package]] -name = "windows_x86_64_msvc" -version = "0.53.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d6bbff5f0aada427a1e5a6da5f1f98158182f26556f345ac9e04d36d0ebed650" - [[package]] name = "wit-bindgen" version = "0.51.0" @@ -1549,6 +1532,12 @@ dependencies = [ "wit-bindgen-rust-macro", ] +[[package]] +name = "wit-bindgen" +version = "0.57.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1ebf944e87a7c253233ad6766e082e3cd714b5d03812acc24c318f549614536e" + [[package]] name = "wit-bindgen-core" version = "0.51.0" @@ -1628,20 +1617,26 @@ dependencies = [ "wasmparser 0.244.0", ] +[[package]] +name = "yansi" +version = "1.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cfe53a6657fd280eaa890a3bc59152892ffa3e30101319d168b781ed6529b049" + [[package]] name = "zerocopy" -version = "0.8.39" +version = "0.8.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "db6d35d663eadb6c932438e763b262fe1a70987f9ae936e60158176d710cae4a" +checksum = "eed437bf9d6692032087e337407a86f04cd8d6a16a37199ed57949d415bd68e9" dependencies = [ "zerocopy-derive", ] [[package]] name = "zerocopy-derive" -version = "0.8.39" +version = "0.8.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517" +checksum = "70e3cd084b1788766f53af483dd21f93881ff30d7320490ec3ef7526d203bad4" dependencies = [ "proc-macro2", "quote", diff --git a/compiler-builtins/Cargo.toml b/compiler-builtins/Cargo.toml index 26a056f434967..ceff63ac930a2 100644 --- a/compiler-builtins/Cargo.toml +++ b/compiler-builtins/Cargo.toml @@ -3,10 +3,12 @@ resolver = "2" members = [ "builtins-shim", "builtins-test", + "crates/api-list-common", "crates/libm-macros", "crates/musl-math-sys", "crates/panic-handler", "crates/symbol-check", + "crates/update-api-list", "crates/util", "libm", "libm-test", @@ -15,14 +17,15 @@ members = [ default-members = [ "builtins-shim", "builtins-test", + "crates/api-list-common", "crates/libm-macros", "libm", "libm-test", ] exclude = [ - # `builtins-test-intrinsics` needs the feature `compiler-builtins` enabled - # and `mangled-names` disabled, which is the opposite of what is needed for + # `builtins-test-intrinsics` needs the features `compiler-builtins` and + # `unmangled-names` enabled, which is the opposite of what is needed for # other tests, so it makes sense to keep it out of the workspace. "builtins-test-intrinsics", # We test via the `builtins-shim` crate, so exclude the `compiler-builtins` @@ -33,6 +36,7 @@ exclude = [ [workspace.dependencies] anyhow = "1.0.101" +api-list-common = { path = "crates/api-list-common" } assert_cmd = "2.1.2" cc = "1.2.56" cfg-if = "1.0.4" @@ -40,8 +44,9 @@ compiler_builtins = { path = "builtins-shim", default-features = false } criterion = { version = "0.8.2", default-features = false, features = ["cargo_bench_support"] } getopts = "0.2.24" getrandom = "0.4.1" +glob = "0.3.3" gmp-mpfr-sys = { version = "1.6.8", default-features = false } -gungraun = "0.17.2" +gungraun = "0.19.0" heck = "0.5.0" indicatif = { version = "0.18.3", default-features = false } libm = { path = "libm", default-features = false } @@ -50,9 +55,10 @@ libm-test = { path = "libm-test", default-features = false } libtest-mimic = "0.8.1" musl-math-sys = { path = "crates/musl-math-sys" } no-panic = "0.1.36" -object = { version = "0.38.1", features = ["wasm"] } +object = { version = "0.39.0", features = ["wasm"] } panic-handler = { path = "crates/panic-handler" } paste = "1.0.15" +pretty_assertions = "1.4.1" proc-macro2 = "1.0.106" quote = "1.0.44" rand = "0.10.0" diff --git a/compiler-builtins/builtins-shim/Cargo.toml b/compiler-builtins/builtins-shim/Cargo.toml index 32b0308a7b3c9..c940723a1ba5f 100644 --- a/compiler-builtins/builtins-shim/Cargo.toml +++ b/compiler-builtins/builtins-shim/Cargo.toml @@ -39,27 +39,28 @@ test = false cc = { version = "1.2", optional = true } [features] -default = [] +default = ["arch"] + +# Enable architecture-specific features such as SIMD or assembly routines. If +# disabled, the generic version can be tested on any platform. +arch = [] # Enable compilation of C code in compiler-rt, filling in some more optimized # implementations and also filling in unimplemented intrinsics c = ["dep:cc"] -# For implementations where there is both a generic version and a platform- -# specific version, use the generic version. This is meant to enable testing -# the generic versions on all platforms. -no-asm = [] - # Flag this library as the unstable compiler-builtins lib. This must be enabled # when using as `std`'s dependency.' -compiler-builtins = [] +compiler-builtins = ["unmangled-names"] -# Generate memory-related intrinsics like memcpy +# Enable `no_mangle` symbols for memory-related intrinsics like memcpy. The +# mangled versions are always available. mem = [] -# Mangle all names so this can be linked in with other versions or other -# compiler-rt implementations. Also used for testing -mangled-names = [] +# Enable `no_mangle` symbols so this crate gets used as the runtime intrinsic +# implementation. Leave this disabled for testing to avoid conflicting with +# the system intrinsics. +unmangled-names = [] # This makes certain traits and function specializations public that # are not normally public but are required by the `builtins-test` diff --git a/compiler-builtins/builtins-test-intrinsics/Cargo.toml b/compiler-builtins/builtins-test-intrinsics/Cargo.toml index e73a1f7b17e5b..fed2ac39fb321 100644 --- a/compiler-builtins/builtins-test-intrinsics/Cargo.toml +++ b/compiler-builtins/builtins-test-intrinsics/Cargo.toml @@ -6,9 +6,15 @@ publish = false license = "MIT OR Apache-2.0" [dependencies] -compiler_builtins = { path = "../builtins-shim", features = ["compiler-builtins"] } +# FIXME: `aeabi_mem*` tests will require the "mem" feature to be enabled here. +compiler_builtins = { path = "../builtins-shim", features = ["compiler-builtins", "unmangled-names"] } panic-handler = { path = "../crates/panic-handler" } +[target.'cfg(all(target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux"))'.dev-dependencies] +test = { git = "https://github.com/japaric/utest" } +utest-cortex-m-qemu = { default-features = false, git = "https://github.com/japaric/utest" } +utest-macros = { git = "https://github.com/japaric/utest" } + [features] c = ["compiler_builtins/c"] diff --git a/compiler-builtins/builtins-test-intrinsics/build.rs b/compiler-builtins/builtins-test-intrinsics/build.rs index b82581262f7b0..c1ab650a6e82a 100644 --- a/compiler-builtins/builtins-test-intrinsics/build.rs +++ b/compiler-builtins/builtins-test-intrinsics/build.rs @@ -1,10 +1,10 @@ -mod builtins_configure { - include!("../compiler-builtins/configure.rs"); -} +#[path = "../libm/configure.rs"] +mod configure; -fn main() { - println!("cargo::rerun-if-changed=../configure.rs"); +use configure::{Config, Library}; - let target = builtins_configure::Target::from_env(); - builtins_configure::configure_aliases(&target); +fn main() { + println!("cargo::rerun-if-changed=../libm/configure.rs"); + let cfg = Config::from_env(Library::BuiltinsTestIntrinsics); + configure::emit(&cfg); } diff --git a/compiler-builtins/builtins-test-intrinsics/src/main.rs b/compiler-builtins/builtins-test-intrinsics/src/main.rs index a3df2c98376cb..e390590946f4c 100644 --- a/compiler-builtins/builtins-test-intrinsics/src/main.rs +++ b/compiler-builtins/builtins-test-intrinsics/src/main.rs @@ -1,7 +1,9 @@ -// By compiling this file we check that all the intrinsics we care about continue to be provided by -// the `compiler_builtins` crate regardless of the changes we make to it. If we, by mistake, stop -// compiling a C implementation and forget to implement that intrinsic in Rust, this file will fail -// to link due to the missing intrinsic (symbol). +//! Tests that require unmangled symbols from `compiler-builtins`. +//! +//! By compiling this file we check that all the intrinsics we care about continue to be provided by +//! the `compiler_builtins` crate regardless of the changes we make to it. If we, by mistake, stop +//! compiling a C implementation and forget to implement that intrinsic in Rust, this file will fail +//! to link due to the missing intrinsic (symbol). #![allow(internal_features, unused_features)] #![deny(dead_code)] diff --git a/compiler-builtins/builtins-test/tests/aeabi_memclr.rs b/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memclr.rs similarity index 98% rename from compiler-builtins/builtins-test/tests/aeabi_memclr.rs rename to compiler-builtins/builtins-test-intrinsics/tests/aeabi_memclr.rs index 0761feaffd9e2..df0e6a6d52997 100644 --- a/compiler-builtins/builtins-test/tests/aeabi_memclr.rs +++ b/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memclr.rs @@ -2,7 +2,6 @@ target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux", - feature = "mem" ))] #![feature(compiler_builtins_lib)] #![no_std] diff --git a/compiler-builtins/builtins-test/tests/aeabi_memcpy.rs b/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memcpy.rs similarity index 98% rename from compiler-builtins/builtins-test/tests/aeabi_memcpy.rs rename to compiler-builtins/builtins-test-intrinsics/tests/aeabi_memcpy.rs index e76e712a246f1..acd12eef64ba5 100644 --- a/compiler-builtins/builtins-test/tests/aeabi_memcpy.rs +++ b/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memcpy.rs @@ -2,7 +2,6 @@ target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux", - feature = "mem" ))] #![feature(compiler_builtins_lib)] #![no_std] diff --git a/compiler-builtins/builtins-test/tests/aeabi_memset.rs b/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memset.rs similarity index 99% rename from compiler-builtins/builtins-test/tests/aeabi_memset.rs rename to compiler-builtins/builtins-test-intrinsics/tests/aeabi_memset.rs index 8f9f80f969ccb..98d2c6852d14f 100644 --- a/compiler-builtins/builtins-test/tests/aeabi_memset.rs +++ b/compiler-builtins/builtins-test-intrinsics/tests/aeabi_memset.rs @@ -2,7 +2,6 @@ target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux", - feature = "mem" ))] #![feature(compiler_builtins_lib)] #![no_std] diff --git a/compiler-builtins/builtins-test/Cargo.toml b/compiler-builtins/builtins-test/Cargo.toml index b2313bb9d140e..f1a5be415675d 100644 --- a/compiler-builtins/builtins-test/Cargo.toml +++ b/compiler-builtins/builtins-test/Cargo.toml @@ -6,7 +6,7 @@ publish = false license = "MIT AND Apache-2.0 WITH LLVM-exception AND (MIT OR Apache-2.0)" [dependencies] -compiler_builtins = { workspace = true, features = ["unstable-public-internals"] } +compiler_builtins = { workspace = true, default-features = false, features = ["unstable-public-internals"] } # For fuzzing tests we want a deterministic seedable RNG. We also eliminate potential # problems with system RNGs on the variety of platforms this crate is tested on. @@ -23,25 +23,11 @@ gungraun = { workspace = true, optional = true } [dev-dependencies] paste.workspace = true -[target.'cfg(all(target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux"))'.dev-dependencies] -test = { git = "https://github.com/japaric/utest" } -utest-cortex-m-qemu = { default-features = false, git = "https://github.com/japaric/utest" } -utest-macros = { git = "https://github.com/japaric/utest" } - [features] -default = ["mangled-names"] +# Defaults should match the defaults in compiler-builtins since we have that +# dependency with `default-features=false`. +default = ["compiler_builtins/arch"] c = ["compiler_builtins/c"] -no-asm = ["compiler_builtins/no-asm"] -mem = ["compiler_builtins/mem"] -mangled-names = ["compiler_builtins/mangled-names"] -# Skip tests that rely on f128 symbols being available on the system -no-sys-f128 = ["no-sys-f128-int-convert", "no-sys-f16-f128-convert"] -# Some platforms have some f128 functions but everything except integer conversions -no-sys-f128-int-convert = [] -no-sys-f16-f128-convert = [] -no-sys-f16-f64-convert = [] -# Skip tests that rely on f16 symbols being available on the system -no-sys-f16 = ["no-sys-f16-f64-convert"] # Enable icount benchmarks (requires gungraun-runner and valgrind locally) icount = ["dep:gungraun"] @@ -51,11 +37,6 @@ icount = ["dep:gungraun"] benchmarking-reports = ["walltime", "criterion/plotters", "criterion/html_reports"] walltime = ["dep:criterion"] -# NOTE: benchmarks must be run with `--no-default-features` or with -# `-p builtins-test`, otherwise the default `compiler-builtins` feature -# of the `compiler_builtins` crate gets activated, resulting in linker -# errors. - [[bench]] name = "float_add" harness = false diff --git a/compiler-builtins/builtins-test/benches/float_add.rs b/compiler-builtins/builtins-test/benches/float_add.rs index 197f90b319da4..2c1d2d9f15520 100644 --- a/compiler-builtins/builtins-test/benches/float_add.rs +++ b/compiler-builtins/builtins-test/benches/float_add.rs @@ -74,7 +74,7 @@ float_bench! { crate_fn_ppc: add::__addkf3, sys_fn: __addtf3, sys_fn_ppc: __addkf3, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/compiler-builtins/builtins-test/benches/float_cmp.rs b/compiler-builtins/builtins-test/benches/float_cmp.rs index da29b5d313263..cb13ce18fe4c6 100644 --- a/compiler-builtins/builtins-test/benches/float_cmp.rs +++ b/compiler-builtins/builtins-test/benches/float_cmp.rs @@ -185,7 +185,7 @@ float_bench! { crate_fn_ppc: cmp::__gtkf2, sys_fn: __gttf2, sys_fn_ppc: __gtkf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), output_eq: gt_res_eq, asm: [] } @@ -198,7 +198,7 @@ float_bench! { crate_fn_ppc: cmp::__unordkf2, sys_fn: __unordtf2, sys_fn_ppc: __unordkf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/compiler-builtins/builtins-test/benches/float_conv.rs b/compiler-builtins/builtins-test/benches/float_conv.rs index 40c13d270ac8e..35255645b2464 100644 --- a/compiler-builtins/builtins-test/benches/float_conv.rs +++ b/compiler-builtins/builtins-test/benches/float_conv.rs @@ -84,7 +84,7 @@ float_bench! { crate_fn_ppc: conv::__floatunsikf, sys_fn: __floatunsitf, sys_fn_ppc: __floatunsikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -138,7 +138,7 @@ float_bench! { crate_fn_ppc: conv::__floatundikf, sys_fn: __floatunditf, sys_fn_ppc: __floatundikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -168,7 +168,7 @@ float_bench! { crate_fn_ppc: conv::__floatuntikf, sys_fn: __floatuntitf, sys_fn_ppc: __floatuntikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -249,7 +249,7 @@ float_bench! { crate_fn_ppc: conv::__floatsikf, sys_fn: __floatsitf, sys_fn_ppc: __floatsikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -328,7 +328,7 @@ float_bench! { crate_fn_ppc: conv::__floatdikf, sys_fn: __floatditf, sys_fn_ppc: __floatdikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -358,7 +358,7 @@ float_bench! { crate_fn_ppc: conv::__floattikf, sys_fn: __floattitf, sys_fn_ppc: __floattikf, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -473,7 +473,7 @@ float_bench! { crate_fn: conv::__fixunstfsi, crate_fn_ppc: conv::__fixunskfsi, sys_fn: __fixunstfsi, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -484,7 +484,7 @@ float_bench! { crate_fn: conv::__fixunstfdi, crate_fn_ppc: conv::__fixunskfdi, sys_fn: __fixunstfdi, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -495,7 +495,7 @@ float_bench! { crate_fn: conv::__fixunstfti, crate_fn_ppc: conv::__fixunskfti, sys_fn: __fixunstfti, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -610,7 +610,7 @@ float_bench! { crate_fn: conv::__fixtfsi, crate_fn_ppc: conv::__fixkfsi, sys_fn: __fixtfsi, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -621,7 +621,7 @@ float_bench! { crate_fn: conv::__fixtfdi, crate_fn_ppc: conv::__fixkfdi, sys_fn: __fixtfdi, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } @@ -632,7 +632,7 @@ float_bench! { crate_fn: conv::__fixtfti, crate_fn_ppc: conv::__fixkfti, sys_fn: __fixtfti, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [] } diff --git a/compiler-builtins/builtins-test/benches/float_div.rs b/compiler-builtins/builtins-test/benches/float_div.rs index d5b0ad0fd402b..dd2b2c1f940e2 100644 --- a/compiler-builtins/builtins-test/benches/float_div.rs +++ b/compiler-builtins/builtins-test/benches/float_div.rs @@ -74,7 +74,7 @@ float_bench! { crate_fn_ppc: div::__divkf3, sys_fn: __divtf3, sys_fn_ppc: __divkf3, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/compiler-builtins/builtins-test/benches/float_extend.rs b/compiler-builtins/builtins-test/benches/float_extend.rs index 939dc60f95f4a..7896d10c8d1aa 100644 --- a/compiler-builtins/builtins-test/benches/float_extend.rs +++ b/compiler-builtins/builtins-test/benches/float_extend.rs @@ -12,7 +12,7 @@ float_bench! { sig: (a: f16) -> f32, crate_fn: extend::__extendhfsf2, sys_fn: __extendhfsf2, - sys_available: not(feature = "no-sys-f16"), + sys_available: not(no_sys_f16), asm: [ #[cfg(target_arch = "aarch64")] { let ret: f32; @@ -34,7 +34,7 @@ float_bench! { sig: (a: f16) -> f64, crate_fn: extend::__extendhfdf2, sys_fn: __extendhfdf2, - sys_available: not(feature = "no-sys-f16-f64-convert"), + sys_available: not(no_sys_f16_f64_convert), asm: [ #[cfg(target_arch = "aarch64")] { let ret: f64; @@ -58,7 +58,7 @@ float_bench! { crate_fn_ppc: extend::__extendhfkf2, sys_fn: __extendhftf2, sys_fn_ppc: __extendhfkf2, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [], } @@ -91,7 +91,7 @@ float_bench! { crate_fn_ppc: extend::__extendsfkf2, sys_fn: __extendsftf2, sys_fn_ppc: __extendsfkf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [], } @@ -103,7 +103,7 @@ float_bench! { crate_fn_ppc: extend::__extenddfkf2, sys_fn: __extenddftf2, sys_fn_ppc: __extenddfkf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [], } diff --git a/compiler-builtins/builtins-test/benches/float_mul.rs b/compiler-builtins/builtins-test/benches/float_mul.rs index a7a2d34aa0489..54fc6daa9b2a6 100644 --- a/compiler-builtins/builtins-test/benches/float_mul.rs +++ b/compiler-builtins/builtins-test/benches/float_mul.rs @@ -74,7 +74,7 @@ float_bench! { crate_fn_ppc: mul::__mulkf3, sys_fn: __multf3, sys_fn_ppc: __mulkf3, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/compiler-builtins/builtins-test/benches/float_pow.rs b/compiler-builtins/builtins-test/benches/float_pow.rs index 64e37dd32416e..d749ae47ddafb 100644 --- a/compiler-builtins/builtins-test/benches/float_pow.rs +++ b/compiler-builtins/builtins-test/benches/float_pow.rs @@ -24,7 +24,7 @@ float_bench! { // FIXME(f16_f128): can be changed to only `f128_enabled` once `__multf3` and `__divtf3` are // distributed by nightly. -#[cfg(all(f128_enabled, not(feature = "no-sys-f128")))] +#[cfg(all(f128_enabled, not(no_sys_f128)))] float_bench! { name: powi_f128, sig: (a: f128, b: i32) -> f128, @@ -32,7 +32,7 @@ float_bench! { crate_fn_ppc: pow::__powikf2, sys_fn: __powitf2, sys_fn_ppc: __powikf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } @@ -42,7 +42,7 @@ pub fn float_pow() { powi_f32(&mut criterion); powi_f64(&mut criterion); - #[cfg(all(f128_enabled, not(feature = "no-sys-f128")))] + #[cfg(all(f128_enabled, not(no_sys_f128)))] powi_f128(&mut criterion); } diff --git a/compiler-builtins/builtins-test/benches/float_sub.rs b/compiler-builtins/builtins-test/benches/float_sub.rs index 8bae294cd56b1..a8b73d7c7719e 100644 --- a/compiler-builtins/builtins-test/benches/float_sub.rs +++ b/compiler-builtins/builtins-test/benches/float_sub.rs @@ -74,7 +74,7 @@ float_bench! { crate_fn_ppc: sub::__subkf3, sys_fn: __subtf3, sys_fn_ppc: __subkf3, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [] } diff --git a/compiler-builtins/builtins-test/benches/float_trunc.rs b/compiler-builtins/builtins-test/benches/float_trunc.rs index 9373f945bb2b8..fdf96fd3d34a4 100644 --- a/compiler-builtins/builtins-test/benches/float_trunc.rs +++ b/compiler-builtins/builtins-test/benches/float_trunc.rs @@ -11,7 +11,7 @@ float_bench! { sig: (a: f32) -> f16, crate_fn: trunc::__truncsfhf2, sys_fn: __truncsfhf2, - sys_available: not(feature = "no-sys-f16"), + sys_available: not(no_sys_f16), asm: [ #[cfg(target_arch = "aarch64")] { let ret: f16; @@ -33,7 +33,7 @@ float_bench! { sig: (a: f64) -> f16, crate_fn: trunc::__truncdfhf2, sys_fn: __truncdfhf2, - sys_available: not(feature = "no-sys-f16-f64-convert"), + sys_available: not(no_sys_f16_f64_convert), asm: [ #[cfg(target_arch = "aarch64")] { let ret: f16; @@ -90,7 +90,7 @@ float_bench! { crate_fn_ppc: trunc::__trunckfhf2, sys_fn: __trunctfhf2, sys_fn_ppc: __trunckfhf2, - sys_available: not(feature = "no-sys-f16-f128-convert"), + sys_available: not(no_sys_f16_f128_convert), asm: [], } @@ -102,7 +102,7 @@ float_bench! { crate_fn_ppc: trunc::__trunckfsf2, sys_fn: __trunctfsf2, sys_fn_ppc: __trunckfsf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [], } @@ -114,7 +114,7 @@ float_bench! { crate_fn_ppc: trunc::__trunckfdf2, sys_fn: __trunctfdf2, sys_fn_ppc: __trunckfdf2, - sys_available: not(feature = "no-sys-f128"), + sys_available: not(no_sys_f128), asm: [], } diff --git a/compiler-builtins/builtins-test/benches/mem_icount.rs b/compiler-builtins/builtins-test/benches/mem_icount.rs index 37595e8258436..7a3cad09b4044 100644 --- a/compiler-builtins/builtins-test/benches/mem_icount.rs +++ b/compiler-builtins/builtins-test/benches/mem_icount.rs @@ -118,7 +118,7 @@ mod mcpy { } } - library_benchmark_group!(name = memcpy; benchmarks = bench_cpy); + library_benchmark_group!(name = memcpy, benchmarks = [bench_cpy]); } mod mset { @@ -167,7 +167,7 @@ mod mset { } } - library_benchmark_group!(name = memset; benchmarks = bench_set); + library_benchmark_group!(name = memset, benchmarks = [bench_set]); } mod mcmp { @@ -235,7 +235,7 @@ mod mcmp { } } - library_benchmark_group!(name = memcmp; benchmarks = bench_cmp); + library_benchmark_group!(name = memcmp, benchmarks = [bench_cmp]); } mod mmove { @@ -489,7 +489,7 @@ mod mmove { } } - library_benchmark_group!(name = memmove; benchmarks = forward_move, backward_move); + library_benchmark_group!(name = memmove, benchmarks = [forward_move, backward_move]); } use mcmp::memcmp; @@ -497,4 +497,4 @@ use mcpy::memcpy; use mmove::memmove; use mset::memset; -main!(library_benchmark_groups = memcpy, memset, memcmp, memmove); +main!(library_benchmark_groups = [memcpy, memset, memcmp, memmove]); diff --git a/compiler-builtins/builtins-test/build.rs b/compiler-builtins/builtins-test/build.rs index 5b2dcd12ef86f..133186bc7f57d 100644 --- a/compiler-builtins/builtins-test/build.rs +++ b/compiler-builtins/builtins-test/build.rs @@ -1,12 +1,13 @@ +#[path = "../libm/configure.rs"] +mod configure; + use std::collections::HashSet; -mod builtins_configure { - include!("../compiler-builtins/configure.rs"); -} +use configure::{Config, Library, set_cfg}; /// Features to enable #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] -enum Feature { +enum SetCfg { NoSysF128, NoSysF128IntConvert, NoSysF16, @@ -14,7 +15,15 @@ enum Feature { NoSysF16F128Convert, } -impl Feature { +impl SetCfg { + const ALL: &[Self] = &[ + Self::NoSysF128, + Self::NoSysF128IntConvert, + Self::NoSysF16, + Self::NoSysF16F64Convert, + Self::NoSysF16F128Convert, + ]; + fn implies(self) -> &'static [Self] { match self { Self::NoSysF128 => [Self::NoSysF128IntConvert, Self::NoSysF16F128Convert].as_slice(), @@ -24,96 +33,89 @@ impl Feature { Self::NoSysF16F128Convert => [].as_slice(), } } + + fn name(self) -> &'static str { + match self { + Self::NoSysF128 => "no_sys_f128", + Self::NoSysF128IntConvert => "no_sys_f128_int_convert", + Self::NoSysF16F64Convert => "no_sys_f16_f64_convert", + Self::NoSysF16F128Convert => "no_sys_f16_f128_convert", + Self::NoSysF16 => "no_sys_f16", + } + } } fn main() { - println!("cargo::rerun-if-changed=../configure.rs"); + println!("cargo::rerun-if-changed=../libm/configure.rs"); - let target = builtins_configure::Target::from_env(); - let mut features = HashSet::new(); + let cfg = Config::from_env(Library::BuiltinsTest); + configure::emit(&cfg); + + let mut to_set = HashSet::new(); // These platforms do not have f128 symbols available in their system libraries, so // skip related tests. - if target.arch == "arm" - || target.vendor == "apple" - || target.env == "msvc" + if cfg.target_arch == "arm" + || cfg.target_vendor == "apple" + || cfg.target_env == "msvc" // GCC and LLVM disagree on the ABI of `f16` and `f128` with MinGW. See // . - || (target.os == "windows" && target.env == "gnu") + || (cfg.target_os == "windows" && cfg.target_env == "gnu") // FIXME(llvm): There is an ABI incompatibility between GCC and Clang on 32-bit x86. // See . - || target.arch == "x86" + || cfg.target_arch == "x86" // 32-bit PowerPC and 64-bit LE gets code generated that Qemu cannot handle. See // . - || target.arch == "powerpc" - || target.arch == "powerpc64le" + || cfg.target_arch == "powerpc" + || cfg.target_arch == "powerpc64le" // FIXME: We get different results from the builtin functions. See // . - || target.arch == "powerpc64" + || cfg.target_arch == "powerpc64" { - features.insert(Feature::NoSysF128); + to_set.insert(SetCfg::NoSysF128); } - if target.arch == "x86" { + if cfg.target_arch == "x86" { // 32-bit x86 does not have `__fixunstfti`/`__fixtfti` but does have everything else - features.insert(Feature::NoSysF128IntConvert); + to_set.insert(SetCfg::NoSysF128IntConvert); // FIXME: 32-bit x86 has a bug in `f128 -> f16` system libraries - features.insert(Feature::NoSysF16F128Convert); + to_set.insert(SetCfg::NoSysF16F128Convert); } // These platforms do not have f16 symbols available in their system libraries, so // skip related tests. Most of these are missing `f16 <-> f32` conversion routines. - if (target.arch == "aarch64" && target.os == "linux") - || target.arch.starts_with("arm") - || target.arch == "powerpc" - || target.arch == "powerpc64" - || target.arch == "powerpc64le" - || target.arch == "loongarch64" - || (target.arch == "x86" && !target.has_feature("sse")) - || target.os == "windows" + if (cfg.target_arch == "aarch64" && cfg.target_os == "linux") + || cfg.target_arch.starts_with("arm") + || cfg.target_arch == "powerpc" + || cfg.target_arch == "powerpc64" + || cfg.target_arch == "powerpc64le" + || cfg.target_arch == "loongarch64" + || (cfg.target_arch == "x86" && !cfg.has_target_feature("sse")) + || cfg.target_os == "windows" // Linking says "error: function signature mismatch: __extendhfsf2" and seems to // think the signature is either `(i32) -> f32` or `(f32) -> f32`. See // . - || target.arch == "wasm32" - || target.arch == "wasm64" + || cfg.target_arch == "wasm32" + || cfg.target_arch == "wasm64" { - features.insert(Feature::NoSysF16); + to_set.insert(SetCfg::NoSysF16); } // These platforms are missing either `__extendhfdf2` or `__truncdfhf2`. - if target.vendor == "apple" || target.os == "windows" { - features.insert(Feature::NoSysF16F64Convert); + if cfg.target_vendor == "apple" || cfg.target_os == "windows" { + to_set.insert(SetCfg::NoSysF16F64Convert); } // Add implied features. Collection is required for borrows. - features.extend( - features + to_set.extend( + to_set .iter() .flat_map(|x| x.implies()) .copied() .collect::>(), ); - for feature in features { - let (name, warning) = match feature { - Feature::NoSysF128 => ("no-sys-f128", "using apfloat fallback for f128"), - Feature::NoSysF128IntConvert => ( - "no-sys-f128-int-convert", - "using apfloat fallback for f128 <-> int conversions", - ), - Feature::NoSysF16F64Convert => ( - "no-sys-f16-f64-convert", - "using apfloat fallback for f16 <-> f64 conversions", - ), - Feature::NoSysF16F128Convert => ( - "no-sys-f16-f128-convert", - "using apfloat fallback for f16 <-> f128 conversions", - ), - Feature::NoSysF16 => ("no-sys-f16", "using apfloat fallback for f16"), - }; - println!("cargo:warning={warning}"); - println!("cargo:rustc-cfg=feature=\"{name}\""); + for cfg in SetCfg::ALL { + set_cfg(cfg.name(), to_set.contains(cfg)); } - - builtins_configure::configure_aliases(&target); } diff --git a/compiler-builtins/builtins-test/src/bench.rs b/compiler-builtins/builtins-test/src/bench.rs index 4bdcf482cd619..dd03579285cbc 100644 --- a/compiler-builtins/builtins-test/src/bench.rs +++ b/compiler-builtins/builtins-test/src/bench.rs @@ -1,7 +1,7 @@ use alloc::vec::Vec; use core::cell::RefCell; -use compiler_builtins::float::Float; +use compiler_builtins::support::Float; /// Fuzz with these many items to ensure equal functions pub const CHECK_ITER_ITEMS: u32 = 10_000; @@ -43,7 +43,7 @@ pub fn skip_sys_checks(test_name: &str) -> bool { return true; } - if cfg!(x86_no_sse) && X86_NO_SSE_SKIPPED.contains(&test_name) { + if cfg!(x86_no_sse2) && X86_NO_SSE_SKIPPED.contains(&test_name) { return true; } diff --git a/compiler-builtins/builtins-test/src/lib.rs b/compiler-builtins/builtins-test/src/lib.rs index b9ad649f88dd7..70478f5f6d745 100644 --- a/compiler-builtins/builtins-test/src/lib.rs +++ b/compiler-builtins/builtins-test/src/lib.rs @@ -19,8 +19,7 @@ pub mod bench; extern crate alloc; -use compiler_builtins::float::Float; -use compiler_builtins::int::{Int, MinInt}; +use compiler_builtins::support::{Float, Int, MinInt}; use rand_xoshiro::Xoshiro128StarStar; use rand_xoshiro::rand_core::{Rng, SeedableRng}; @@ -245,18 +244,18 @@ fn fuzz_float_step(rng: &mut Xoshiro128StarStar, f: &mut F) { let sign = (rng32 & 1) != 0; // exponent fuzzing. Only 4 bits for the selector needed. - let ones = (F::Int::ONE << F::EXP_BITS) - F::Int::ONE; + let ones = F::EXP_SAT; let r0 = (rng32 >> 1) % F::EXP_BITS; let r1 = (rng32 >> 5) % F::EXP_BITS; // custom rotate shift. Note that `F::Int` is unsigned, so we can shift right without smearing // the sign bit. let mask = if r1 == 0 { - ones.wrapping_shr(r0) + ones >> r0 } else { - let tmp = ones.wrapping_shr(r0); - (tmp.wrapping_shl(r1) | tmp.wrapping_shr(F::EXP_BITS - r1)) & ones + let tmp = ones >> r0; + ((tmp << r1) | (tmp >> (F::EXP_BITS - r1))) & ones }; - let mut exp = (f.to_bits() & F::EXP_MASK) >> F::SIG_BITS; + let mut exp = f.ex(); match (rng32 >> 9) % 4 { 0 => exp |= mask, 1 => exp &= mask, @@ -274,13 +273,13 @@ fn fuzz_float_step(rng: &mut Xoshiro128StarStar, f: &mut F) { macro_rules! float_edge_cases { ($F:ident, $case:ident, $inner:block) => { for exponent in [ - F::Int::ZERO, - F::Int::ONE, - F::Int::ONE << (F::EXP_BITS / 2), - (F::Int::ONE << (F::EXP_BITS - 1)) - F::Int::ONE, - F::Int::ONE << (F::EXP_BITS - 1), - (F::Int::ONE << (F::EXP_BITS - 1)) + F::Int::ONE, - (F::Int::ONE << F::EXP_BITS) - F::Int::ONE, + 0, + 1, + 1 << (F::EXP_BITS / 2), + (1 << (F::EXP_BITS - 1)) - 1, + 1 << (F::EXP_BITS - 1), + (1 << (F::EXP_BITS - 1)) + 1, + (1 << F::EXP_BITS) - 1, ] .iter() { diff --git a/compiler-builtins/builtins-test/tests/addsub.rs b/compiler-builtins/builtins-test/tests/addsub.rs index 410967967d2a3..859de3e425538 100644 --- a/compiler-builtins/builtins-test/tests/addsub.rs +++ b/compiler-builtins/builtins-test/tests/addsub.rs @@ -87,7 +87,8 @@ macro_rules! float_sum { #[test] fn $fn_add() { use core::ops::{Add, Sub}; - use compiler_builtins::float::{{add::$fn_add, sub::$fn_sub}, Float}; + use compiler_builtins::float::{add::$fn_add, sub::$fn_sub}; + use compiler_builtins::support::Float; fuzz_float_2(N, |x: $f, y: $f| { let add0 = apfloat_fallback!($f, $apfloat_ty, $sys_available, Add::add, x, y); @@ -112,7 +113,7 @@ macro_rules! float_sum { } } -#[cfg(not(x86_no_sse))] +#[cfg(not(x86_no_sse2))] mod float_addsub { use super::*; @@ -127,15 +128,15 @@ mod float_addsub { } #[cfg(f128_enabled)] - #[cfg(not(x86_no_sse))] + #[cfg(not(x86_no_sse2))] #[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))] float_sum! { - f128, __addtf3, __subtf3, Quad, not(feature = "no-sys-f128"); + f128, __addtf3, __subtf3, Quad, not(no_sys_f128); } #[cfg(f128_enabled)] #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] float_sum! { - f128, __addkf3, __subkf3, Quad, not(feature = "no-sys-f128"); + f128, __addkf3, __subkf3, Quad, not(no_sys_f128); } } diff --git a/compiler-builtins/builtins-test/tests/big.rs b/compiler-builtins/builtins-test/tests/big.rs deleted file mode 100644 index d1ae88bd16485..0000000000000 --- a/compiler-builtins/builtins-test/tests/big.rs +++ /dev/null @@ -1,134 +0,0 @@ -use compiler_builtins::int::{HInt, MinInt, i256, u256}; - -const LOHI_SPLIT: u128 = 0xaaaaaaaaaaaaaaaaffffffffffffffff; - -/// Print a `u256` as hex since we can't add format implementations -fn hexu(v: u256) -> String { - format!( - "0x{:016x}{:016x}{:016x}{:016x}", - v.0[3], v.0[2], v.0[1], v.0[0] - ) -} - -#[test] -fn widen_u128() { - assert_eq!(u128::MAX.widen(), u256([u64::MAX, u64::MAX, 0, 0])); - assert_eq!( - LOHI_SPLIT.widen(), - u256([u64::MAX, 0xaaaaaaaaaaaaaaaa, 0, 0]) - ); -} - -#[test] -fn widen_i128() { - assert_eq!((-1i128).widen(), u256::MAX.signed()); - assert_eq!( - (LOHI_SPLIT as i128).widen(), - i256([u64::MAX, 0xaaaaaaaaaaaaaaaa, u64::MAX, u64::MAX]) - ); - assert_eq!((-1i128).zero_widen().unsigned(), (u128::MAX).widen()); -} - -#[test] -fn widen_mul_u128() { - let tests = [ - (u128::MAX / 2, 2_u128, u256([u64::MAX - 1, u64::MAX, 0, 0])), - (u128::MAX, 2_u128, u256([u64::MAX - 1, u64::MAX, 1, 0])), - (u128::MAX, u128::MAX, u256([1, 0, u64::MAX - 1, u64::MAX])), - (u128::MIN, u128::MIN, u256::ZERO), - (1234, 0, u256::ZERO), - (0, 1234, u256::ZERO), - ]; - - let mut errors = Vec::new(); - for (i, (a, b, exp)) in tests.iter().copied().enumerate() { - let res = a.widen_mul(b); - let res_z = a.zero_widen_mul(b); - assert_eq!(res, res_z); - if res != exp { - errors.push((i, a, b, exp, res)); - } - } - - for (i, a, b, exp, res) in &errors { - eprintln!( - "FAILURE ({i}): {a:#034x} * {b:#034x} = {} got {}", - hexu(*exp), - hexu(*res) - ); - } - assert!(errors.is_empty()); -} - -#[test] -fn not_u128() { - assert_eq!(!u256::ZERO, u256::MAX); -} - -#[test] -fn shr_u128() { - let only_low = [ - 1, - u16::MAX.into(), - u32::MAX.into(), - u64::MAX.into(), - u128::MAX, - ]; - - let mut errors = Vec::new(); - - for a in only_low { - for perturb in 0..10 { - let a = a.saturating_add(perturb); - for shift in 0..128 { - let res = a.widen() >> shift; - let expected = (a >> shift).widen(); - if res != expected { - errors.push((a.widen(), shift, res, expected)); - } - } - } - } - - let check = [ - ( - u256::MAX, - 1, - u256([u64::MAX, u64::MAX, u64::MAX, u64::MAX >> 1]), - ), - ( - u256::MAX, - 5, - u256([u64::MAX, u64::MAX, u64::MAX, u64::MAX >> 5]), - ), - (u256::MAX, 63, u256([u64::MAX, u64::MAX, u64::MAX, 1])), - (u256::MAX, 64, u256([u64::MAX, u64::MAX, u64::MAX, 0])), - (u256::MAX, 65, u256([u64::MAX, u64::MAX, u64::MAX >> 1, 0])), - (u256::MAX, 127, u256([u64::MAX, u64::MAX, 1, 0])), - (u256::MAX, 128, u256([u64::MAX, u64::MAX, 0, 0])), - (u256::MAX, 129, u256([u64::MAX, u64::MAX >> 1, 0, 0])), - (u256::MAX, 191, u256([u64::MAX, 1, 0, 0])), - (u256::MAX, 192, u256([u64::MAX, 0, 0, 0])), - (u256::MAX, 193, u256([u64::MAX >> 1, 0, 0, 0])), - (u256::MAX, 191, u256([u64::MAX, 1, 0, 0])), - (u256::MAX, 254, u256([0b11, 0, 0, 0])), - (u256::MAX, 255, u256([1, 0, 0, 0])), - ]; - - for (input, shift, expected) in check { - let res = input >> shift; - if res != expected { - errors.push((input, shift, res, expected)); - } - } - - for (a, b, res, expected) in &errors { - eprintln!( - "FAILURE: {} >> {b} = {} got {}", - hexu(*a), - hexu(*expected), - hexu(*res), - ); - } - assert!(errors.is_empty()); -} diff --git a/compiler-builtins/builtins-test/tests/cmp.rs b/compiler-builtins/builtins-test/tests/cmp.rs index 4b01b6ca1c7d7..d9360027a9643 100644 --- a/compiler-builtins/builtins-test/tests/cmp.rs +++ b/compiler-builtins/builtins-test/tests/cmp.rs @@ -125,19 +125,19 @@ mod float_comparisons { fuzz_float_2(N, |x: f128, y: f128| { let x_is_nan = apfloat_fallback!( - f128, Quad, not(feature = "no-sys-f128"), + f128, Quad, not(no_sys_f128), |x: FloatTy| x.is_nan() => no_convert, x ); let y_is_nan = apfloat_fallback!( - f128, Quad, not(feature = "no-sys-f128"), + f128, Quad, not(no_sys_f128), |x: FloatTy| x.is_nan() => no_convert, y ); assert_eq!(__unordtf2(x, y) != 0, x_is_nan || y_is_nan); - cmp!(f128, x, y, Quad, not(feature = "no-sys-f128"), + cmp!(f128, x, y, Quad, not(no_sys_f128), 1, __lttf2; 1, __letf2; 1, __eqtf2; diff --git a/compiler-builtins/builtins-test/tests/conv.rs b/compiler-builtins/builtins-test/tests/conv.rs index 0fd15ad3ee662..e01eb259ac869 100644 --- a/compiler-builtins/builtins-test/tests/conv.rs +++ b/compiler-builtins/builtins-test/tests/conv.rs @@ -6,7 +6,7 @@ #![allow(unused_macros)] use builtins_test::*; -use compiler_builtins::float::Float; +use compiler_builtins::support::Float; use rustc_apfloat::{Float as _, FloatConvert as _}; mod i_to_f { @@ -18,7 +18,7 @@ mod i_to_f { #[test] fn $fn() { use compiler_builtins::float::conv::$fn; - use compiler_builtins::int::Int; + use compiler_builtins::support::Int; fuzz(N, |x: $i_ty| { let f0 = apfloat_fallback!( @@ -27,7 +27,7 @@ mod i_to_f { // When the builtin is not available, we need to use a different conversion // method (since apfloat doesn't support `as` casting). |x: $i_ty| { - use compiler_builtins::int::MinInt; + use compiler_builtins::support::MinInt; let apf = if <$i_ty>::SIGNED { FloatTy::from_i128(x.try_into().unwrap()).value @@ -117,7 +117,7 @@ mod i_to_f { #[cfg(f128_enabled)] #[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))] - i_to_f! { f128, Quad, not(feature = "no-sys-f128-int-convert"), + i_to_f! { f128, Quad, not(no_sys_f128_int_convert), u32, __floatunsitf; i32, __floatsitf; u64, __floatunditf; @@ -128,7 +128,7 @@ mod i_to_f { #[cfg(f128_enabled)] #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] - i_to_f! { f128, Quad, not(feature = "no-sys-f128-int-convert"), + i_to_f! { f128, Quad, not(no_sys_f128_int_convert), u32, __floatunsikf; i32, __floatsikf; u64, __floatundikf; @@ -155,7 +155,7 @@ mod f_to_i { // When the builtin is not available, we need to use a different conversion // method (since apfloat doesn't support `as` casting). |x: $f_ty| { - use compiler_builtins::int::MinInt; + use compiler_builtins::support::MinInt; let apf = FloatTy::from_bits(x.to_bits().into()); let bits: usize = <$i_ty>::BITS.try_into().unwrap(); @@ -236,7 +236,7 @@ mod f_to_i { x, f128, Quad, - not(feature = "no-sys-f128-int-convert"), + not(no_sys_f128_int_convert), u32, __fixunstfsi; u64, __fixunstfdi; u128, __fixunstfti; @@ -259,7 +259,8 @@ macro_rules! f_to_f { ) => {$( #[test] fn $fn() { - use compiler_builtins::float::{$mod::$fn, Float}; + use compiler_builtins::float::$mod::$fn; + use compiler_builtins::support::Float; use rustc_apfloat::ieee::{$from_ap_ty, $to_ap_ty}; fuzz_float(N, |x: $from_ty| { @@ -308,12 +309,12 @@ mod extend { )))] f_to_f! { extend, - f16 => f32, Half => Single, __extendhfsf2, not(feature = "no-sys-f16"); - f16 => f32, Half => Single, __gnu_h2f_ieee, not(feature = "no-sys-f16"); - f16 => f64, Half => Double, __extendhfdf2, not(feature = "no-sys-f16-f64-convert"); - f16 => f128, Half => Quad, __extendhftf2, not(feature = "no-sys-f16-f128-convert"); - f32 => f128, Single => Quad, __extendsftf2, not(feature = "no-sys-f128"); - f64 => f128, Double => Quad, __extenddftf2, not(feature = "no-sys-f128"); + f16 => f32, Half => Single, __extendhfsf2, not(no_sys_f16); + f16 => f32, Half => Single, __gnu_h2f_ieee, not(no_sys_f16); + f16 => f64, Half => Double, __extendhfdf2, not(no_sys_f16_f64_convert); + f16 => f128, Half => Quad, __extendhftf2, not(no_sys_f16_f128_convert); + f32 => f128, Single => Quad, __extendsftf2, not(no_sys_f128); + f64 => f128, Double => Quad, __extenddftf2, not(no_sys_f128); } #[cfg(f128_enabled)] @@ -321,8 +322,8 @@ mod extend { f_to_f! { extend, // FIXME(#655): `f16` tests disabled until we can bootstrap symbols - f32 => f128, Single => Quad, __extendsfkf2, not(feature = "no-sys-f128"); - f64 => f128, Double => Quad, __extenddfkf2, not(feature = "no-sys-f128"); + f32 => f128, Single => Quad, __extendsfkf2, not(no_sys_f128); + f64 => f128, Double => Quad, __extenddfkf2, not(no_sys_f128); } } @@ -342,12 +343,12 @@ mod trunc { )))] f_to_f! { trunc, - f32 => f16, Single => Half, __truncsfhf2, not(feature = "no-sys-f16"); - f32 => f16, Single => Half, __gnu_f2h_ieee, not(feature = "no-sys-f16"); - f64 => f16, Double => Half, __truncdfhf2, not(feature = "no-sys-f16-f64-convert"); - f128 => f16, Quad => Half, __trunctfhf2, not(feature = "no-sys-f16-f128-convert"); - f128 => f32, Quad => Single, __trunctfsf2, not(feature = "no-sys-f128"); - f128 => f64, Quad => Double, __trunctfdf2, not(feature = "no-sys-f128"); + f32 => f16, Single => Half, __truncsfhf2, not(no_sys_f16); + f32 => f16, Single => Half, __gnu_f2h_ieee, not(no_sys_f16); + f64 => f16, Double => Half, __truncdfhf2, not(no_sys_f16_f64_convert); + f128 => f16, Quad => Half, __trunctfhf2, not(no_sys_f16_f128_convert); + f128 => f32, Quad => Single, __trunctfsf2, not(no_sys_f128); + f128 => f64, Quad => Double, __trunctfdf2, not(no_sys_f128); } #[cfg(f128_enabled)] @@ -355,7 +356,7 @@ mod trunc { f_to_f! { trunc, // FIXME(#655): `f16` tests disabled until we can bootstrap symbols - f128 => f32, Quad => Single, __trunckfsf2, not(feature = "no-sys-f128"); - f128 => f64, Quad => Double, __trunckfdf2, not(feature = "no-sys-f128"); + f128 => f32, Quad => Single, __trunckfsf2, not(no_sys_f128); + f128 => f64, Quad => Double, __trunckfdf2, not(no_sys_f128); } } diff --git a/compiler-builtins/builtins-test/tests/div_rem.rs b/compiler-builtins/builtins-test/tests/div_rem.rs index 4ff86385a9630..5d04fe9c0a9b1 100644 --- a/compiler-builtins/builtins-test/tests/div_rem.rs +++ b/compiler-builtins/builtins-test/tests/div_rem.rs @@ -109,7 +109,8 @@ macro_rules! float { $( #[test] fn $fn() { - use compiler_builtins::float::{div::$fn, Float}; + use compiler_builtins::float::div::$fn; + use compiler_builtins::support::Float; use core::ops::Div; fuzz_float_2(N, |x: $f, y: $f| { @@ -138,7 +139,7 @@ macro_rules! float { }; } -#[cfg(not(x86_no_sse))] +#[cfg(not(x86_no_sse2))] mod float_div { use super::*; @@ -153,12 +154,12 @@ mod float_div { f128, __divtf3, Quad, // FIXME(llvm): there is a bug in LLVM rt. // See . - not(any(feature = "no-sys-f128", all(target_arch = "aarch64", target_os = "linux"))); + not(any(no_sys_f128, all(target_arch = "aarch64", target_os = "linux"))); } #[cfg(f128_enabled)] #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] float! { - f128, __divkf3, Quad, not(feature = "no-sys-f128"); + f128, __divkf3, Quad, not(no_sys_f128); } } diff --git a/compiler-builtins/builtins-test/tests/float_pow.rs b/compiler-builtins/builtins-test/tests/float_pow.rs index 3cea83a255c8c..c808b9efae65f 100644 --- a/compiler-builtins/builtins-test/tests/float_pow.rs +++ b/compiler-builtins/builtins-test/tests/float_pow.rs @@ -1,7 +1,7 @@ #![allow(unused_macros, unused_features)] #![cfg_attr(f128_enabled, feature(f128))] -#[cfg_attr(x86_no_sse, allow(unused))] +#[cfg_attr(x86_no_sse2, allow(unused))] use builtins_test::*; // This is approximate because of issues related to @@ -16,7 +16,8 @@ macro_rules! pow { #[cfg($sys_available)] fn $fn() { use compiler_builtins::float::pow::$fn; - use compiler_builtins::float::Float; + use compiler_builtins::support::Float; + fuzz_float_2(N, |x: $f, y: $f| { if !(Float::is_subnormal(x) || Float::is_subnormal(y) || x.is_nan()) { let n = y.to_bits() & !<$f as Float>::SIG_MASK; @@ -52,7 +53,7 @@ macro_rules! pow { }; } -#[cfg(not(x86_no_sse))] // FIXME(i586): failure for powidf2 +#[cfg(not(x86_no_sse2))] // FIXME(i586): failure for powidf2 pow! { f32, 1e-4, __powisf2, all(); f64, 1e-12, __powidf2, all(); @@ -61,11 +62,11 @@ pow! { #[cfg(f128_enabled)] #[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))] pow! { - f128, 1e-36, __powitf2, not(feature = "no-sys-f128"); + f128, 1e-36, __powitf2, not(no_sys_f128); } #[cfg(f128_enabled)] #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] pow! { - f128, 1e-36, __powikf2, not(feature = "no-sys-f128"); + f128, 1e-36, __powikf2, not(no_sys_f128); } diff --git a/compiler-builtins/builtins-test/tests/lse.rs b/compiler-builtins/builtins-test/tests/lse.rs index d408fe193bcff..20d4d19a328a1 100644 --- a/compiler-builtins/builtins-test/tests/lse.rs +++ b/compiler-builtins/builtins-test/tests/lse.rs @@ -1,12 +1,12 @@ #![allow(unused_features)] #![feature(decl_macro)] // so we can use pub(super) #![feature(macro_metavar_expr_concat)] -#![cfg(all(target_arch = "aarch64", feature = "mangled-names"))] +#![cfg(target_arch = "aarch64")] use std::sync::Mutex; use compiler_builtins::aarch64_outline_atomics::{get_have_lse_atomics, set_have_lse_atomics}; -use compiler_builtins::int::{Int, MinInt}; +use compiler_builtins::support::{Int, MinInt}; use compiler_builtins::{foreach_bytes, foreach_ordering}; #[track_caller] diff --git a/compiler-builtins/builtins-test/tests/mul.rs b/compiler-builtins/builtins-test/tests/mul.rs index 30516ebaf7866..b16d729be1dd5 100644 --- a/compiler-builtins/builtins-test/tests/mul.rs +++ b/compiler-builtins/builtins-test/tests/mul.rs @@ -96,7 +96,8 @@ macro_rules! float_mul { $( #[test] fn $fn() { - use compiler_builtins::float::{mul::$fn, Float}; + use compiler_builtins::float::mul::$fn; + use compiler_builtins::support::Float; use core::ops::Mul; fuzz_float_2(N, |x: $f, y: $f| { @@ -114,7 +115,7 @@ macro_rules! float_mul { }; } -#[cfg(not(x86_no_sse))] +#[cfg(not(x86_no_sse2))] mod float_mul { use super::*; @@ -132,7 +133,7 @@ mod float_mul { } #[cfg(f128_enabled)] -#[cfg(not(x86_no_sse))] +#[cfg(not(x86_no_sse2))] #[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))] mod float_mul_f128 { use super::*; @@ -141,7 +142,7 @@ mod float_mul_f128 { f128, __multf3, Quad, // FIXME(llvm): there is a bug in LLVM rt. // See . - not(any(feature = "no-sys-f128", all(target_arch = "aarch64", target_os = "linux"))); + not(any(no_sys_f128, all(target_arch = "aarch64", target_os = "linux"))); } } @@ -151,6 +152,6 @@ mod float_mul_f128_ppc { use super::*; float_mul! { - f128, __mulkf3, Quad, not(feature = "no-sys-f128"); + f128, __mulkf3, Quad, not(no_sys_f128); } } diff --git a/compiler-builtins/ci/bench-icount.sh b/compiler-builtins/ci/bench-icount.sh index 6d92b50a6dae7..cd36303ca316a 100755 --- a/compiler-builtins/ci/bench-icount.sh +++ b/compiler-builtins/ci/bench-icount.sh @@ -26,12 +26,20 @@ tag="$(echo "$target" | cut -d'-' -f1)" # after the first run with gungraun. [ -d "iai-home" ] && mv "iai-home" "$gungraun_home" +failed="0" + # Run benchmarks once function run_icount_benchmarks() { cargo_args=( + "--target" "$target" "--bench" "*icount*" "--no-default-features" - "--features" "unstable,unstable-float,icount" + "--features" "unstable unstable-float icount" + # Enable unmangled-names so our compiler-builtins gets used for + # intrinsics. This makes performance impacts of c-b changes show up + # in libm benchmarks and gives us a better idea of what will happen + # in std (e.g. speedups in __addtf3 will show up in fmaf128). + "--features" "compiler_builtins/unmangled-names" ) gungraun_args=( @@ -65,13 +73,18 @@ function run_icount_benchmarks() { # Disregard regressions after merge echo "Benchmarks completed with regressions; ignoring (not in a PR)" else - ./ci/ci-util.py handle-bench-regressions "$PR_NUMBER" + ./ci/ci-util.py handle-bench-regressions "$PR_NUMBER" || failed="1" fi } # Run once with softfloats, once with arch instructions enabled -run_icount_benchmarks --features force-soft-floats -- --save-baseline=softfloat -run_icount_benchmarks -- --save-baseline=hardfloat +run_icount_benchmarks -- --save-baseline=arch_disabled +run_icount_benchmarks --features arch -- --save-baseline=arch_enabled + +if [ "$failed" != "0" ]; then + echo "One or more benchmarks failed" + exit 1 +fi # Name and tar the new baseline name="baseline-icount-$tag-$(date -u +'%Y%m%d%H%M')-${GITHUB_SHA:0:12}" diff --git a/compiler-builtins/ci/bench-walltime.sh b/compiler-builtins/ci/bench-walltime.sh index 0393d02dfc452..5d564c97beb35 100755 --- a/compiler-builtins/ci/bench-walltime.sh +++ b/compiler-builtins/ci/bench-walltime.sh @@ -6,4 +6,4 @@ export LIBM_SEED=benchesbenchesbenchesbencheswoo! cargo bench --package libm-test \ --no-default-features \ - --features walltime,short-benchmarks,build-musl,libm/force-soft-floats + --features walltime,short-benchmarks,build-musl diff --git a/compiler-builtins/ci/ci-util.py b/compiler-builtins/ci/ci-util.py index 392f83c219e7a..f359c59797448 100755 --- a/compiler-builtins/ci/ci-util.py +++ b/compiler-builtins/ci/ci-util.py @@ -361,6 +361,10 @@ def base_name(name: str) -> tuple[str, str]: return (name.rstrip("f"), "f32") elif name.endswith("f16"): return (name.rstrip("f16"), "f16") + elif name.endswith("f32"): + return (name.rstrip("f32"), "f32") + elif name.endswith("f64"): + return (name.rstrip("f64"), "f64") elif name.endswith("f128"): return (name.rstrip("f128"), "f128") diff --git a/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile index 683bd07fd47ef..30a13fc5de910 100644 --- a/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile index 781abd1b6e888..41ff36a49e3bb 100644 --- a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile +++ b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile index 36ea4827dc52f..1fad72c470f03 100644 --- a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile +++ b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile b/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile index 8b76693b2799e..039ccd5745256 100644 --- a/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile +++ b/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile index 9125038acbde5..9319e73dd03f0 100644 --- a/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile index 9125038acbde5..9319e73dd03f0 100644 --- a/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile index a652235958777..442a13164880c 100644 --- a/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile index 0913f33c05ce4..9941a8c2736c0 100644 --- a/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile b/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile index d2f4e484b1aab..c20d0a77b81c3 100644 --- a/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile +++ b/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile b/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile index 873754b2793e9..584f7ffff45a5 100644 --- a/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile +++ b/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile index 5768b68d6c950..ead99bb9c1132 100644 --- a/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile index c625a4bcd5d7c..74071874ed7cf 100644 --- a/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile index 86a7a8cd46e4e..ba4fec7160b64 100644 --- a/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile index 722b10b0a7349..e90d4c8812042 100644 --- a/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile index 7a721ba05416e..96442121bcd9e 100644 --- a/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile @@ -1,11 +1,11 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev qemu-user ca-certificates \ gcc-riscv64-linux-gnu libc6-dev-riscv64-cross \ - qemu-system-riscv64 + qemu-system-riscv ENV TOOLCHAIN_PREFIX=riscv64-linux-gnu- ENV CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ diff --git a/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile index a1a6b3cf5cfd2..463cce94e5540 100644 --- a/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile index a1a6b3cf5cfd2..463cce94e5540 100644 --- a/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile b/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile index a1a6b3cf5cfd2..463cce94e5540 100644 --- a/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile index a1a6b3cf5cfd2..463cce94e5540 100644 --- a/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile b/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile index b646a72bb37cc..09f35c3b128d0 100644 --- a/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile +++ b/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile index 927515f90f329..103c395ee8496 100644 --- a/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.10 +ARG IMAGE=ubuntu:26.04 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/download-compiler-rt.sh b/compiler-builtins/ci/download-compiler-rt.sh index bf7f8c2489643..87b337d8255bb 100755 --- a/compiler-builtins/ci/download-compiler-rt.sh +++ b/compiler-builtins/ci/download-compiler-rt.sh @@ -6,5 +6,5 @@ set -eux rust_llvm_version=20.1-2025-02-13 -curl -L -o code.tar.gz "https://github.com/rust-lang/llvm-project/archive/rustc/${rust_llvm_version}.tar.gz" +curl -L --retry 3 -o code.tar.gz "https://github.com/rust-lang/llvm-project/archive/rustc/${rust_llvm_version}.tar.gz" tar xzf code.tar.gz --strip-components 1 llvm-project-rustc-${rust_llvm_version}/compiler-rt diff --git a/compiler-builtins/ci/install-bench-deps.sh b/compiler-builtins/ci/install-bench-deps.sh index 61f4723c0358d..7d73ed0d32f55 100755 --- a/compiler-builtins/ci/install-bench-deps.sh +++ b/compiler-builtins/ci/install-bench-deps.sh @@ -1,10 +1,22 @@ -#!/bin/sh +#!/bin/bash # Install needed dependencies for gungraun. +set -eux + +target="${1:-}" + +# Needed for gungraun +deps=(valgrind gdb libc6-dbg) + +[[ "$target" = *"i686"* ]] && deps+=(gcc-multilib) + sudo apt-get update -sudo apt-get install -y valgrind gdb libc6-dbg # Needed for gungraun +sudo apt-get install -y "${deps[@]}" + rustup update "$BENCHMARK_RUSTC" --no-self-update rustup default "$BENCHMARK_RUSTC" +[ -n "$target" ] && rustup target add "$target" + # Install the version of gungraun-runner that is specified in Cargo.toml gungraun_version="$(cargo metadata --format-version=1 --features icount | jq -r '.packages[] | select(.name == "gungraun").version')" diff --git a/compiler-builtins/ci/miri.sh b/compiler-builtins/ci/miri.sh index aae474d884638..2751bf0dc49e1 100755 --- a/compiler-builtins/ci/miri.sh +++ b/compiler-builtins/ci/miri.sh @@ -5,7 +5,7 @@ set -eux # compatible with Stacked Borrows. export MIRIFLAGS="-Zmiri-tree-borrows" -# One target that sets `mem-unaligned` and one that does not, +# One target that sets `mem_unaligned` and one that does not, # and a big-endian target. targets=( x86_64-unknown-linux-gnu @@ -13,10 +13,11 @@ targets=( s390x-unknown-linux-gnu ) for target in "${targets[@]}"; do - # Only run the `mem` tests to avoid this taking too long. + # Only run the `mem` tests to avoid this taking too long. Disable default + # features to turn off `arch` and avoid inline assembly. cargo miri test \ --manifest-path builtins-test/Cargo.toml \ - --features no-asm \ + --no-default-features \ --target "$target" \ -- mem done diff --git a/compiler-builtins/ci/run-docker.sh b/compiler-builtins/ci/run-docker.sh index e65ada271904f..a894677b59f90 100755 --- a/compiler-builtins/ci/run-docker.sh +++ b/compiler-builtins/ci/run-docker.sh @@ -78,6 +78,7 @@ run() { -e CI \ -e CARGO_TARGET_DIR=/builtins-target \ -e CARGO_TERM_COLOR \ + -e LIBM_BUILD_VERBOSE \ -e MAY_SKIP_LIBM_CI \ -e RUSTFLAGS \ -e RUST_BACKTRACE \ @@ -97,7 +98,7 @@ if [ "${1:-}" = "--help" ] || [ "$#" -gt 1 ]; then usage: ./ci/run-docker.sh [target] you can also set DOCKER_BASE_IMAGE to use something other than the default - ubuntu:25.10 (or rustlang/rust:nightly). + ubuntu:26.04 (or rustlang/rust:nightly). " exit fi diff --git a/compiler-builtins/ci/run-extensive.sh b/compiler-builtins/ci/run-extensive.sh index 4ba41a026fab6..9bdf8bcfbadcc 100755 --- a/compiler-builtins/ci/run-extensive.sh +++ b/compiler-builtins/ci/run-extensive.sh @@ -14,7 +14,15 @@ set -x test_cmd=( cargo test --package libm-test - --features "build-mpfr,libm/unstable,libm/force-soft-floats" + --no-default-features + # Don't enable `arch` for extensive tests. Usually anything in asm is + # only a single instruction or a small sequence, and we rely on the + # vendors to test that for us. + # + # libm/unstable enables libm/unstable-intrinsics, which means we usually + # get the single-instruction ops anyway when we aren't specifically + # testing for them. + --features "libm-test/build-mpfr libm-test/unstable-float libm/unstable" --profile release-checked ) diff --git a/compiler-builtins/ci/run.sh b/compiler-builtins/ci/run.sh index b9a21d555c9e5..93c551dc52ec7 100755 --- a/compiler-builtins/ci/run.sh +++ b/compiler-builtins/ci/run.sh @@ -20,19 +20,45 @@ if [ "${USING_CONTAINER_RUSTC:-}" = 1 ]; then rustup target add "$target" fi +# If nextest is available, use that +command -v cargo-nextest && nextest=1 || nextest=0 +if [ "$nextest" = "1" ]; then + test_runner=(cargo nextest run --max-fail=20) + profile_flag="--cargo-profile" + + # Workaround for https://github.com/nextest-rs/nextest/issues/2066 + if [ -n "${CARGO_TARGET_DIR:-}" ]; then + cfg_file="/tmp/nextest-config.toml" + echo "[store]" >> "$cfg_file" + echo "dir = \"$CARGO_TARGET_DIR/nextest\"" >> "$cfg_file" + test_runner+=(--config-file "$cfg_file") + fi + + # Not all configurations have tests to run on wasm + [[ "$target" = *"wasm"* ]] && test_runner+=(--no-tests=warn) +else + test_runner=(cargo test --no-fail-fast) + profile_flag="--profile" +fi + # Test our implementation if [ "${BUILD_ONLY:-}" = "1" ]; then echo "no tests to run for build-only targets" else - test_builtins=(cargo test --package builtins-test --no-fail-fast --target "$target") + test_builtins=( + "${test_runner[@]}" + --package builtins-test + --target "$target" + ) + "${test_builtins[@]}" "${test_builtins[@]}" --release "${test_builtins[@]}" --features c "${test_builtins[@]}" --features c --release - "${test_builtins[@]}" --features no-asm - "${test_builtins[@]}" --features no-asm --release "${test_builtins[@]}" --benches "${test_builtins[@]}" --benches --release + "${test_builtins[@]}" --no-default-features + "${test_builtins[@]}" --no-default-features --release # Validate that having a verbatim path for the target directory works # (trivial to regress using `/` in paths to build artifacts rather than @@ -53,12 +79,14 @@ symcheck+=(-- --build-and-check --target "$target") # Executable section checks are meaningless on no-std targets [[ "$target" == *"-none"* ]] && symcheck+=(--no-os) -"${symcheck[@]}" -- -p compiler_builtins -"${symcheck[@]}" -- -p compiler_builtins --release -"${symcheck[@]}" -- -p compiler_builtins --features c -"${symcheck[@]}" -- -p compiler_builtins --features c --release -"${symcheck[@]}" -- -p compiler_builtins --features no-asm -"${symcheck[@]}" -- -p compiler_builtins --features no-asm --release +# We only need to check the configurations std may use +symcheck_cb_args=(-- --package compiler_builtins --features compiler-builtins) +"${symcheck[@]}" "${symcheck_cb_args[@]}" +"${symcheck[@]}" "${symcheck_cb_args[@]}" --release +"${symcheck[@]}" "${symcheck_cb_args[@]}" --features c +"${symcheck[@]}" "${symcheck_cb_args[@]}" --features c --release +"${symcheck[@]}" "${symcheck_cb_args[@]}" --no-default-features +"${symcheck[@]}" "${symcheck_cb_args[@]}" --no-default-features --release run_intrinsics_test() { build_args=(--verbose --manifest-path builtins-test-intrinsics/Cargo.toml) @@ -100,13 +128,13 @@ mflags=() # We enumerate features manually. mflags+=(--no-default-features) -# Enable arch-specific routines when available. -mflags+=(--features arch) - # Always enable `unstable-float` since it expands available API but does not # change any implementations. mflags+=(--features unstable-float) +# This is a host program that may not run in containers. +mflags+=(--exclude update-api-list) + # We need to specifically skip tests for musl-math-sys on systems that can't # build musl since otherwise `--all` will activate it. case "$target" in @@ -157,28 +185,7 @@ if [ "${BUILD_ONLY:-}" = "1" ]; then else # symcheck tests need specific env setup, and is already tested above mflags+=(--workspace --exclude symbol-check --target "$target") - cmd=(cargo test "${mflags[@]}") - profile_flag="--profile" - - # If nextest is available, use that - command -v cargo-nextest && nextest=1 || nextest=0 - if [ "$nextest" = "1" ]; then - cmd=(cargo nextest run --max-fail=10) - - # Workaround for https://github.com/nextest-rs/nextest/issues/2066 - if [ -f /.dockerenv ]; then - cfg_file="/tmp/nextest-config.toml" - echo "[store]" >> "$cfg_file" - echo "dir = \"$CARGO_TARGET_DIR/nextest\"" >> "$cfg_file" - cmd+=(--config-file "$cfg_file") - fi - - # Not all configurations have tests to run on wasm - [[ "$target" = *"wasm"* ]] && cmd+=(--no-tests=warn) - - cmd+=("${mflags[@]}") - profile_flag="--cargo-profile" - fi + cmd=("${test_runner[@]}" "${mflags[@]}") # Test once without intrinsics "${cmd[@]}" @@ -191,15 +198,15 @@ else cmd+=(--exclude util --exclude libm-macros) # Test once with intrinsics enabled - "${cmd[@]}" --features unstable-intrinsics - "${cmd[@]}" --features unstable-intrinsics --benches + "${cmd[@]}" --features arch,unstable-intrinsics + "${cmd[@]}" --features arch,unstable-intrinsics --benches # Test the same in release mode, which also increases coverage. Also ensure # the soft float routines are checked. "${cmd[@]}" "$profile_flag" release-checked - "${cmd[@]}" "$profile_flag" release-checked --features force-soft-floats - "${cmd[@]}" "$profile_flag" release-checked --features unstable-intrinsics - "${cmd[@]}" "$profile_flag" release-checked --features unstable-intrinsics --benches + "${cmd[@]}" "$profile_flag" release-checked --features arch + "${cmd[@]}" "$profile_flag" release-checked --features arch,unstable-intrinsics + "${cmd[@]}" "$profile_flag" release-checked --features arch,unstable-intrinsics --benches # Ensure that the routines do not panic. # diff --git a/compiler-builtins/compiler-builtins/Cargo.toml b/compiler-builtins/compiler-builtins/Cargo.toml index d9acb8341d483..b2f1443f2eb09 100644 --- a/compiler-builtins/compiler-builtins/Cargo.toml +++ b/compiler-builtins/compiler-builtins/Cargo.toml @@ -34,27 +34,28 @@ core = { path = "../../core", optional = true } cc = { version = "1.2", optional = true } [features] -default = [] +default = ["arch"] + +# Enable architecture-specific features such as SIMD or assembly routines. If +# disabled, the generic version can be tested on any platform. +arch = [] # Enable compilation of C code in compiler-rt, filling in some more optimized # implementations and also filling in unimplemented intrinsics c = ["dep:cc"] -# For implementations where there is both a generic version and a platform- -# specific version, use the generic version. This is meant to enable testing -# the generic versions on all platforms. -no-asm = [] - # Flag this library as the unstable compiler-builtins lib. This must be enabled # when using as `std`'s dependency.' -compiler-builtins = ["dep:core"] +compiler-builtins = ["dep:core", "unmangled-names"] -# Generate memory-related intrinsics like memcpy +# Enable `no_mangle` symbols for memory-related intrinsics like memcpy. The +# mangled versions are always available. mem = [] -# Mangle all names so this can be linked in with other versions or other -# compiler-rt implementations. Also used for testing -mangled-names = [] +# Enable `no_mangle` symbols so this crate gets used as the runtime intrinsic +# implementation. Leave this disabled for testing to avoid conflicting with +# the system intrinsics. +unmangled-names = [] # This makes certain traits and function specializations public that # are not normally public but are required by the `builtins-test` diff --git a/compiler-builtins/compiler-builtins/build.rs b/compiler-builtins/compiler-builtins/build.rs index 6e1d230e3cd26..e86c784b5c631 100644 --- a/compiler-builtins/compiler-builtins/build.rs +++ b/compiler-builtins/compiler-builtins/build.rs @@ -1,120 +1,88 @@ +#[path = "../libm/configure.rs"] mod configure; use std::env; -use configure::{Target, configure_aliases}; +use configure::{Config, Library, set_cfg}; fn main() { - println!("cargo::rerun-if-changed=build.rs"); - println!("cargo::rerun-if-changed=configure.rs"); + let cfg = Config::from_env(Library::CompilerBuiltins); + let llvm_target = &cfg.target_triple_split; + + // Work around building as part of `builtins-shim`: if only `build.rs` is used, Cargo always + // considers the build dirty because `builtins-shim/build.rs` does not exist. If only + // `../c-b/build.rs` is used, the same may happen if not built in the workspace. + // Note: this may be `None` if CARGO_MANIFEST_DIR doesn't end in a directory name (e.g. ".") + if let Some(dir) = cfg.manifest_dir.file_name() + && dir == "builtins-shim" + { + println!("cargo::rerun-if-changed=../compiler-builtins/build.rs"); + } else { + println!("cargo::rerun-if-changed=build.rs"); + } - let target = Target::from_env(); - let cwd = env::current_dir().unwrap(); + println!("cargo::rerun-if-changed=../libm/configure.rs"); + configure::emit(&cfg); configure_check_cfg(); - configure_aliases(&target); - - configure_libm(&target); + let cwd = env::current_dir().unwrap(); println!("cargo:compiler-rt={}", cwd.join("compiler-rt").display()); - println!("cargo::rustc-check-cfg=cfg(kernel_user_helpers)"); - println!("cargo::rustc-check-cfg=cfg(feature, values(\"mem-unaligned\"))"); - - // Emscripten's runtime includes all the builtins - if target.os == "emscripten" { - return; - } - - // OpenBSD provides compiler_rt by default, use it instead of rebuilding it from source - if target.os == "openbsd" { - println!("cargo:rustc-link-search=native=/usr/lib"); - println!("cargo:rustc-link-lib=compiler_rt"); - return; - } - // Forcibly enable memory intrinsics on wasm & SGX as we don't have a libc to // provide them. - if (target.triple.contains("wasm") && !target.triple.contains("wasi")) - || (target.triple.contains("sgx") && target.triple.contains("fortanix")) - || target.triple.contains("-none") - || target.triple.contains("nvptx") - || target.triple.contains("uefi") - || target.triple.contains("xous") + if (cfg.target_triple.contains("wasm") && !cfg.target_triple.contains("wasi")) + || (cfg.target_triple.contains("sgx") && cfg.target_triple.contains("fortanix")) + || cfg.target_triple.contains("-none") + || cfg.target_triple.contains("nvptx") + || cfg.target_triple.contains("uefi") + || cfg.target_triple.contains("xous") { println!("cargo:rustc-cfg=feature=\"mem\""); } // These targets have hardware unaligned access support. - if target.arch.contains("x86_64") - || target.arch.contains("x86") - || target.arch.contains("aarch64") - || target.arch.contains("bpf") - { - println!("cargo:rustc-cfg=feature=\"mem-unaligned\""); - } - - // NOTE we are going to assume that llvm-target, what determines our codegen option, matches the - // target triple. This is usually correct for our built-in targets but can break in presence of - // custom targets, which can have arbitrary names. - let llvm_target = target.triple.split('-').collect::>(); - - // Build missing intrinsics from compiler-rt C source code. If we're - // mangling names though we assume that we're also in test mode so we don't - // build anything and we rely on the upstream implementation of compiler-rt - // functions - if !cfg!(feature = "mangled-names") && cfg!(feature = "c") { - // Don't use a C compiler for these targets: - // - // * nvptx - everything is bitcode, not compatible with mixed C/Rust - if !target.arch.contains("nvptx") { - #[cfg(feature = "c")] - c::compile(&llvm_target, &target); - } - } + let mem_unaligned = cfg.target_arch.contains("x86_64") + || cfg.target_arch.contains("x86") + || cfg.target_arch.contains("aarch64") + || cfg.target_arch.contains("bpf"); + set_cfg("mem_unaligned", mem_unaligned); // Only emit the ARM Linux atomic emulation on pre-ARMv6 architectures. This // includes the old androideabi. It is deprecated but it is available as a // rustc target (arm-linux-androideabi). - if llvm_target[0] == "armv4t" + let kernel_user_helpers = llvm_target[0] == "armv4t" || llvm_target[0] == "armv5te" - || target.triple == "arm-linux-androideabi" - { - println!("cargo:rustc-cfg=kernel_user_helpers") - } -} + || cfg.target_triple == "arm-linux-androideabi"; + set_cfg("kernel_user_helpers", kernel_user_helpers); -/// Run configuration for `libm` since it is included directly. -/// -/// Much of this is copied from `libm/configure.rs`. -fn configure_libm(target: &Target) { - println!("cargo:rustc-check-cfg=cfg(intrinsics_enabled)"); - println!("cargo:rustc-check-cfg=cfg(arch_enabled)"); - println!("cargo:rustc-check-cfg=cfg(optimizations_enabled)"); - println!("cargo:rustc-check-cfg=cfg(feature, values(\"unstable-public-internals\"))"); - - // Always use intrinsics - println!("cargo:rustc-cfg=intrinsics_enabled"); - - // The arch module may contain assembly. - if !cfg!(feature = "no-asm") { - println!("cargo:rustc-cfg=arch_enabled"); + let mut maybe_build_c = true; + + // Emscripten's runtime includes all the builtins + if cfg.target_os == "emscripten" { + maybe_build_c = false; } - println!("cargo:rustc-check-cfg=cfg(optimizations_enabled)"); - if !matches!(target.opt_level.as_str(), "0" | "1") { - println!("cargo:rustc-cfg=optimizations_enabled"); + // OpenBSD provides compiler_rt by default, use it instead of rebuilding it from source + if cfg.target_os == "openbsd" { + println!("cargo:rustc-link-search=native=/usr/lib"); + println!("cargo:rustc-link-lib=compiler_rt"); + maybe_build_c = false; } - println!( - "cargo:rustc-env=CFG_CARGO_FEATURES={:?}", - target.cargo_features - ); - println!("cargo:rustc-env=CFG_OPT_LEVEL={}", target.opt_level); - println!("cargo:rustc-env=CFG_TARGET_FEATURES={:?}", target.features); + // Everything is LLVM bitcode, not compatible with mixed C/Rust + if cfg.target_arch.contains("nvptx") { + maybe_build_c = false; + } - // Activate libm's unstable features to make full use of Nightly. - println!("cargo:rustc-cfg=feature=\"unstable-intrinsics\""); + // Build missing intrinsics from compiler-rt C source code. If we're + // mangling names though we assume that we're also in test mode so we don't + // build anything and we rely on the upstream implementation of compiler-rt + // functions + if cfg!(feature = "unmangled-names") && cfg!(feature = "c") && maybe_build_c { + #[cfg(feature = "c")] + c::compile(&cfg); + } } /// Emit directives for features we expect to support that aren't in `Cargo.toml`. @@ -176,10 +144,6 @@ fn configure_check_cfg() { // Rustc is unaware of sparc target features, but this does show up from // `rustc --print target-features --target sparc64-unknown-linux-gnu`. println!("cargo::rustc-check-cfg=cfg(target_feature, values(\"vis3\"))"); - - // FIXME: these come from libm and should be changed there - println!("cargo::rustc-check-cfg=cfg(feature, values(\"checked\"))"); - println!("cargo::rustc-check-cfg=cfg(assert_no_panic)"); } #[cfg(feature = "c")] @@ -190,7 +154,7 @@ mod c { use std::io::Write; use std::path::{Path, PathBuf}; - use super::Target; + use super::Config; struct Sources { // SYMBOL -> PATH TO SOURCE @@ -232,17 +196,18 @@ mod c { } /// Compile intrinsics from the compiler-rt C source code - pub fn compile(llvm_target: &[&str], target: &Target) { + pub fn compile(cfg: &Config) { + let llvm_target = &cfg.target_triple_split; let mut consider_float_intrinsics = true; - let cfg = &mut cc::Build::new(); + let build = &mut cc::Build::new(); // AArch64 GCCs exit with an error condition when they encounter any kind of floating point // code if the `nofp` and/or `nosimd` compiler flags have been set. // // Therefore, evaluate if those flags are present and set a boolean that causes any // compiler-rt intrinsics that contain floating point source to be excluded for this target. - if target.arch == "aarch64" { - let cflags_key = String::from("CFLAGS_") + &(target.triple.replace("-", "_")); + if cfg.target_arch == "aarch64" { + let cflags_key = String::from("CFLAGS_") + &(cfg.target_triple.replace("-", "_")); if let Ok(cflags_value) = env::var(cflags_key) { if cflags_value.contains("+nofp") || cflags_value.contains("+nosimd") { consider_float_intrinsics = false; @@ -256,22 +221,22 @@ mod c { // support `_Float16` on all targets (whereas Rust does). However, define the macro // anyway to prevent issues like rust#118813 and rust#123885 silently reoccuring if more // `f16` intrinsics get accidentally added here in the future. - cfg.define("COMPILER_RT_HAS_FLOAT16", None); + build.define("COMPILER_RT_HAS_FLOAT16", None); - cfg.warnings(false); + build.warnings(false); - if target.env == "msvc" { + if cfg.target_env == "msvc" { // Don't pull in extra libraries on MSVC - cfg.flag("/Zl"); + build.flag("/Zl"); // Emulate C99 and C++11's __func__ for MSVC prior to 2013 CTP - cfg.define("__func__", Some("__FUNCTION__")); + build.define("__func__", Some("__FUNCTION__")); } else { // Turn off various features of gcc and such, mostly copying // compiler-rt's build system already - cfg.flag("-fno-builtin"); - cfg.flag("-fvisibility=hidden"); - cfg.flag("-ffreestanding"); + build.flag("-fno-builtin"); + build.flag("-fvisibility=hidden"); + build.flag("-ffreestanding"); // Avoid the following warning appearing once **per file**: // clang: warning: optimization flag '-fomit-frame-pointer' is not supported for target 'armv7' [-Wignored-optimization-argument] // @@ -280,17 +245,17 @@ mod c { // `check_cxx_compiler_flag(-fomit-frame-pointer COMPILER_RT_HAS_FOMIT_FRAME_POINTER_FLAG)` // // in https://github.com/rust-lang/compiler-rt/blob/c8fbcb3/cmake/config-ix.cmake#L19. - cfg.flag_if_supported("-fomit-frame-pointer"); - cfg.define("VISIBILITY_HIDDEN", None); + build.flag_if_supported("-fomit-frame-pointer"); + build.define("VISIBILITY_HIDDEN", None); - if let "aarch64" | "arm64ec" = target.arch.as_str() { + if let "aarch64" | "arm64ec" = cfg.target_arch.as_str() { // FIXME(llvm20): Older GCCs on A64 fail to build with // -Werror=implicit-function-declaration due to a compiler-rt bug. // With a newer LLVM we should be able to enable the flag everywhere. // https://github.com/llvm/llvm-project/commit/8aa9d6206ce55bdaaf422839c351fbd63f033b89 } else { // Avoid implicitly creating references to undefined functions - cfg.flag("-Werror=implicit-function-declaration"); + build.flag("-Werror=implicit-function-declaration"); } } @@ -299,14 +264,14 @@ mod c { // at odds with compiling with `-ffreestanding`, as the header // may be incompatible or not present. Create a minimal stub // header to use instead. - if target.os == "uefi" { + if cfg.target_os == "uefi" { let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); let include_dir = out_dir.join("include"); if !include_dir.exists() { fs::create_dir(&include_dir).unwrap(); } fs::write(include_dir.join("stdlib.h"), "#include ").unwrap(); - cfg.flag(&format!("-I{}", include_dir.to_str().unwrap())); + build.flag(&format!("-I{}", include_dir.to_str().unwrap())); } let mut sources = Sources::new(); @@ -344,7 +309,7 @@ mod c { // On iOS and 32-bit OSX these are all just empty intrinsics, no need to // include them. - if target.vendor != "apple" || target.arch != "x86" { + if cfg.target_vendor != "apple" || cfg.target_arch != "x86" { sources.extend(&[ ("__absvti2", "absvti2.c"), ("__addvti3", "addvti3.c"), @@ -363,7 +328,7 @@ mod c { } } - if target.vendor == "apple" { + if cfg.target_vendor == "apple" { sources.extend(&[ ("atomic_flag_clear", "atomic_flag_clear.c"), ("atomic_flag_clear_explicit", "atomic_flag_clear_explicit.c"), @@ -377,8 +342,8 @@ mod c { ]); } - if target.env != "msvc" { - if target.arch == "x86" { + if cfg.target_env != "msvc" { + if cfg.target_arch == "x86" { sources.extend(&[ ("__ashldi3", "i386/ashldi3.S"), ("__ashrdi3", "i386/ashrdi3.S"), @@ -392,7 +357,7 @@ mod c { } } - if target.arch == "arm" && target.vendor != "apple" && target.env != "msvc" { + if cfg.target_arch == "arm" && cfg.target_vendor != "apple" && cfg.target_env != "msvc" { sources.extend(&[ ("__aeabi_div0", "arm/aeabi_div0.c"), ("__aeabi_drsub", "arm/aeabi_drsub.c"), @@ -412,7 +377,7 @@ mod c { ("__umodsi3", "arm/umodsi3.S"), ]); - if target.os == "freebsd" { + if cfg.target_os == "freebsd" { sources.extend(&[("__clear_cache", "clear_cache.c")]); } @@ -484,31 +449,36 @@ mod c { ]); } - if (target.arch == "aarch64" || target.arch == "arm64ec") && consider_float_intrinsics { + if (cfg.target_arch == "aarch64" || cfg.target_arch == "arm64ec") + && consider_float_intrinsics + { sources.extend(&[ ("__fe_getround", "fp_mode.c"), ("__fe_raise_inexact", "fp_mode.c"), ]); - if target.os != "windows" && target.os != "cygwin" { + if cfg.target_os != "windows" && cfg.target_os != "cygwin" { sources.extend(&[("__multc3", "multc3.c")]); } } - if target.arch == "mips" || target.arch == "riscv32" || target.arch == "riscv64" { + if cfg.target_arch == "mips" || cfg.target_arch == "riscv32" || cfg.target_arch == "riscv64" + { sources.extend(&[("__bswapsi2", "bswapsi2.c")]); } - if target.arch == "mips64" { + if cfg.target_arch == "mips64" { sources.extend(&[("__fe_getround", "fp_mode.c")]); } - if target.arch == "loongarch64" { + if cfg.target_arch == "loongarch64" { sources.extend(&[("__fe_getround", "fp_mode.c")]); } // Remove the assembly implementations that won't compile for the target - if llvm_target[0] == "thumbv6m" || llvm_target[0] == "thumbv8m.base" || target.os == "uefi" + if llvm_target[0] == "thumbv6m" + || llvm_target[0] == "thumbv8m.base" + || cfg.target_os == "uefi" { let mut to_remove = Vec::new(); for (k, v) in sources.map.iter() { @@ -524,19 +494,19 @@ mod c { } // Android and Cygwin uses emulated TLS so we need a runtime support function. - if target.os == "android" || target.os == "cygwin" { + if cfg.target_os == "android" || cfg.target_os == "cygwin" { sources.extend(&[("__emutls_get_address", "emutls.c")]); } // Work around a bug in the NDK headers (fixed in // https://r.android.com/2038949 which will be released in a future // NDK version) by providing a definition of LONG_BIT. - if target.os == "android" { - cfg.define("LONG_BIT", "(8 * sizeof(long))"); + if cfg.target_os == "android" { + build.define("LONG_BIT", "(8 * sizeof(long))"); } // OpenHarmony also uses emulated TLS. - if target.env == "ohos" { + if cfg.target_env == "ohos" { sources.extend(&[("__emutls_get_address", "emutls.c")]); } @@ -568,16 +538,16 @@ mod c { // Support deterministic builds by remapping the __FILE__ prefix if the // compiler supports it. This fixes the nondeterminism caused by the // use of that macro in lib/builtins/int_util.h in compiler-rt. - cfg.flag_if_supported(&format!("-ffile-prefix-map={}=.", root.display())); + build.flag_if_supported(&format!("-ffile-prefix-map={}=.", root.display())); // Include out-of-line atomics for aarch64, which are all generated by supplying different // sets of flags to the same source file. // Note: Out-of-line aarch64 atomics are not supported by the msvc toolchain (#430) and // on uefi. let src_dir = root.join("lib/builtins"); - if target.arch == "aarch64" && target.env != "msvc" && target.os != "uefi" { + if cfg.target_arch == "aarch64" && cfg.target_env != "msvc" && cfg.target_os != "uefi" { // See below for why we're building these as separate libraries. - build_aarch64_out_of_line_atomics_libraries(&src_dir, cfg, link_against_prebuilt_rt); + build_aarch64_out_of_line_atomics_libraries(&src_dir, build, link_against_prebuilt_rt); // Some run-time CPU feature detection is necessary, as well. let cpu_model_src = if src_dir.join("cpu_model.c").exists() { @@ -592,7 +562,7 @@ mod c { for (sym, src) in sources.map.iter() { let src = src_dir.join(src); if !link_against_prebuilt_rt && added_sources.insert(src.clone()) { - cfg.file(&src); + build.file(&src); println!("cargo:rerun-if-changed={}", src.display()); } println!("cargo:rustc-cfg={}=\"optimized-c\"", sym); @@ -616,7 +586,7 @@ mod c { ); } } else { - cfg.compile("libcompiler-rt.a"); + build.compile("libcompiler-rt.a"); } } diff --git a/compiler-builtins/compiler-builtins/configure.rs b/compiler-builtins/compiler-builtins/configure.rs deleted file mode 100644 index f16da6b58f812..0000000000000 --- a/compiler-builtins/compiler-builtins/configure.rs +++ /dev/null @@ -1,107 +0,0 @@ -// Configuration that is shared between `compiler_builtins` and `builtins_test`. - -use std::{env, str}; - -#[derive(Debug)] -#[allow(dead_code)] -pub struct Target { - pub triple: String, - pub triple_split: Vec, - pub opt_level: String, - pub cargo_features: Vec, - pub os: String, - pub arch: String, - pub vendor: String, - pub env: String, - pub pointer_width: u8, - pub little_endian: bool, - pub features: Vec, - pub reliable_f128: bool, - pub reliable_f16: bool, -} - -impl Target { - pub fn from_env() -> Self { - let triple = env::var("TARGET").unwrap(); - let triple_split = triple.split('-').map(ToOwned::to_owned).collect(); - let little_endian = match env::var("CARGO_CFG_TARGET_ENDIAN").unwrap().as_str() { - "little" => true, - "big" => false, - x => panic!("unknown endian {x}"), - }; - let cargo_features = env::vars() - .filter_map(|(name, _value)| name.strip_prefix("CARGO_FEATURE_").map(ToOwned::to_owned)) - .map(|s| s.to_lowercase().replace("_", "-")) - .collect(); - - Self { - triple, - triple_split, - os: env::var("CARGO_CFG_TARGET_OS").unwrap(), - opt_level: env::var("OPT_LEVEL").unwrap(), - cargo_features, - arch: env::var("CARGO_CFG_TARGET_ARCH").unwrap(), - vendor: env::var("CARGO_CFG_TARGET_VENDOR").unwrap(), - env: env::var("CARGO_CFG_TARGET_ENV").unwrap(), - pointer_width: env::var("CARGO_CFG_TARGET_POINTER_WIDTH") - .unwrap() - .parse() - .unwrap(), - little_endian, - features: env::var("CARGO_CFG_TARGET_FEATURE") - .unwrap_or_default() - .split(",") - .map(ToOwned::to_owned) - .collect(), - // Note that these are unstable options, so only show up with the nightly compiler or - // with `RUSTC_BOOTSTRAP=1` (which is required to use the types anyway). - reliable_f128: env::var_os("CARGO_CFG_TARGET_HAS_RELIABLE_F128").is_some(), - reliable_f16: env::var_os("CARGO_CFG_TARGET_HAS_RELIABLE_F16").is_some(), - } - } - - #[allow(dead_code)] - pub fn has_feature(&self, feature: &str) -> bool { - self.features.iter().any(|f| f == feature) - } -} - -pub fn configure_aliases(target: &Target) { - // To compile builtins-test-intrinsics for thumb targets, where there is no libc - println!("cargo::rustc-check-cfg=cfg(thumb)"); - if target.triple_split[0].starts_with("thumb") { - println!("cargo:rustc-cfg=thumb") - } - - // compiler-rt `cfg`s away some intrinsics for thumbv6m and thumbv8m.base because - // these targets do not have full Thumb-2 support but only original Thumb-1. - // We have to cfg our code accordingly. - println!("cargo::rustc-check-cfg=cfg(thumb_1)"); - if target.triple_split[0] == "thumbv6m" || target.triple_split[0] == "thumbv8m.base" { - println!("cargo:rustc-cfg=thumb_1") - } - - // Config shorthands - println!("cargo:rustc-check-cfg=cfg(x86_no_sse)"); - if target.arch == "x86" && !target.features.iter().any(|f| f == "sse") { - // Shorthand to detect i586 targets - println!("cargo:rustc-cfg=x86_no_sse"); - } - - /* Not all backends support `f16` and `f128` to the same level on all architectures, so we - * need to disable things if the compiler may crash. See configuration at: - * * https://github.com/rust-lang/rust/blob/c65dccabacdfd6c8a7f7439eba13422fdd89b91e/compiler/rustc_codegen_llvm/src/llvm_util.rs#L367-L432 - * * https://github.com/rust-lang/rustc_codegen_gcc/blob/4b5c44b14166083eef8d71f15f5ea1f53fc976a0/src/lib.rs#L496-L507 - * * https://github.com/rust-lang/rustc_codegen_cranelift/blob/c713ffab3c6e28ab4b4dd4e392330f786ea657ad/src/lib.rs#L196-L226 - */ - - println!("cargo::rustc-check-cfg=cfg(f16_enabled)"); - if target.reliable_f16 { - println!("cargo::rustc-cfg=f16_enabled"); - } - - println!("cargo::rustc-check-cfg=cfg(f128_enabled)"); - if target.reliable_f128 { - println!("cargo::rustc-cfg=f128_enabled"); - } -} diff --git a/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs b/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs index 100b67150772a..367768ecb60d6 100644 --- a/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs +++ b/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs @@ -35,14 +35,14 @@ intrinsics! { } /// Function to enable/disable LSE. To be used only for testing purposes. -#[cfg(feature = "mangled-names")] +#[cfg(feature = "unstable-public-internals")] pub unsafe fn set_have_lse_atomics(has_lse: bool) { let lse_flag = if has_lse { 1 } else { 0 }; HAVE_LSE_ATOMICS.store(lse_flag, Ordering::Relaxed); } /// Function to obtain whether LSE is enabled or not. To be used only for testing purposes. -#[cfg(feature = "mangled-names")] +#[cfg(feature = "unstable-public-internals")] pub fn get_have_lse_atomics() -> bool { HAVE_LSE_ATOMICS.load(Ordering::Relaxed) != 0 } diff --git a/compiler-builtins/compiler-builtins/src/float/add.rs b/compiler-builtins/compiler-builtins/src/float/add.rs index acdcd2ebe3133..69de07372f16e 100644 --- a/compiler-builtins/compiler-builtins/src/float/add.rs +++ b/compiler-builtins/compiler-builtins/src/float/add.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::{CastFrom, CastInto, Int, MinInt}; +use crate::support::{CastFrom, CastInto, Float, Int, MinInt}; /// Returns `a + b` fn add(a: F, b: F) -> F diff --git a/compiler-builtins/compiler-builtins/src/float/cmp.rs b/compiler-builtins/compiler-builtins/src/float/cmp.rs index 8ab39c2b5914d..a59365a2bdb8b 100644 --- a/compiler-builtins/compiler-builtins/src/float/cmp.rs +++ b/compiler-builtins/compiler-builtins/src/float/cmp.rs @@ -1,21 +1,28 @@ #![allow(unreachable_code)] -use crate::float::Float; -use crate::int::MinInt; -use crate::support::cfg_if; - -// Taken from LLVM config: -// https://github.com/llvm/llvm-project/blob/0cf3c437c18ed27d9663d87804a9a15ff6874af2/compiler-rt/lib/builtins/fp_compare_impl.inc#L11-L27 +use crate::support::{Float, MinInt, cfg_if}; + +// These definitions should be consistent with LLVM's definition from `getCmpLibcallReturnType`, +// compiler-rt's definitions [1], GCC's `CMPtype` [2], and `libgcc`. To find the definitions +// in GCC, there are a few things to grep for: +// +// * `default_libgcc_cmp_return_mode` for the default (word sized) +// * `TARGET_LIBGCC_CMP_RETURN_MODE` for the target hook to override the default +// * `# *define *CMPtype` as a last resort, for overrides that don't use the hook (AVR) +// +// [1]: https://github.com/llvm/llvm-project/blob/0cf3c437c18ed27d9663d87804a9a15ff6874af2/compiler-rt/lib/builtins/fp_compare_impl.inc#L11-L27 +// [2]: https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html#Comparison-functions-1 cfg_if! { - if #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { + if #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_family = "wasm"))] { // Aarch64 uses `int` rather than a pointer-sized value. + // `getCmpLibcallReturnType` for WASM is always set to i32. pub type CmpResult = i32; } else if #[cfg(target_arch = "avr")] { // AVR uses a single byte. pub type CmpResult = i8; } else { - // In compiler-rt, LLP64 ABIs use `long long` and everything else uses `long`. In effect, - // this means the return value is always pointer-sized. + // The default is word-sized. In LLVM's compiler-rt, this is done by using `long long` on + // LLP64 ABIs and `long` on everything else. pub type CmpResult = isize; } } @@ -28,8 +35,18 @@ enum Result { Unordered, } +/// Conversions to match GCC intrinsics [1]. +/// +/// * `unord`: nonzero if either NaN, 0 otherwise +/// * `eq`, `ne`: 0 if a == b and both YaN, nonzero otherwise +/// * `ge`, `gt`, `lt`, `le`: return an int result that provides the same comparison to 0 if both +/// YaN and the comparison matches. E.g. if a >= b, `ge` returns an `x >= 0`. +/// +/// The separate map functions are only needed to handle the unordered case. +/// +/// [1]: https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html#Comparison-functions-1 impl Result { - fn to_le_abi(self) -> CmpResult { + fn to_default_cmp_result(self) -> CmpResult { match self { Result::Less => -1, Result::Equal => 0, @@ -38,7 +55,7 @@ impl Result { } } - fn to_ge_abi(self) -> CmpResult { + fn to_gt_ge_cmp_result(self) -> CmpResult { match self { Result::Less => -1, Result::Equal => 0, @@ -118,11 +135,11 @@ fn unord(a: F, b: F) -> bool { #[cfg(f16_enabled)] intrinsics! { pub extern "C" fn __lehf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gehf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } pub extern "C" fn __unordhf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { @@ -130,29 +147,29 @@ intrinsics! { } pub extern "C" fn __eqhf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __lthf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __nehf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gthf2(a: f16, b: f16) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } } intrinsics! { pub extern "C" fn __lesf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gesf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } #[arm_aeabi_alias = __aeabi_fcmpun] @@ -161,27 +178,27 @@ intrinsics! { } pub extern "C" fn __eqsf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __ltsf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __nesf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gtsf2(a: f32, b: f32) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } pub extern "C" fn __ledf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gedf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } #[arm_aeabi_alias = __aeabi_dcmpun] @@ -190,19 +207,19 @@ intrinsics! { } pub extern "C" fn __eqdf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __ltdf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __nedf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } pub extern "C" fn __gtdf2(a: f64, b: f64) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } } @@ -210,12 +227,12 @@ intrinsics! { intrinsics! { #[ppc_alias = __lekf2] pub extern "C" fn __letf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } #[ppc_alias = __gekf2] pub extern "C" fn __getf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } #[ppc_alias = __unordkf2] @@ -225,22 +242,22 @@ intrinsics! { #[ppc_alias = __eqkf2] pub extern "C" fn __eqtf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } #[ppc_alias = __ltkf2] pub extern "C" fn __lttf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } #[ppc_alias = __nekf2] pub extern "C" fn __netf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_le_abi() + cmp(a, b).to_default_cmp_result() } #[ppc_alias = __gtkf2] pub extern "C" fn __gttf2(a: f128, b: f128) -> crate::float::cmp::CmpResult { - cmp(a, b).to_ge_abi() + cmp(a, b).to_gt_ge_cmp_result() } } diff --git a/compiler-builtins/compiler-builtins/src/float/conv.rs b/compiler-builtins/compiler-builtins/src/float/conv.rs index 75ea7ce02424a..7310cd4ec4f02 100644 --- a/compiler-builtins/compiler-builtins/src/float/conv.rs +++ b/compiler-builtins/compiler-builtins/src/float/conv.rs @@ -1,7 +1,6 @@ use core::ops::Neg; -use super::Float; -use crate::int::{CastFrom, CastInto, Int, MinInt}; +use crate::support::{CastFrom, CastInto, Float, Int, MinInt}; /// Conversions from integers to floats. /// diff --git a/compiler-builtins/compiler-builtins/src/float/div.rs b/compiler-builtins/compiler-builtins/src/float/div.rs index fc1fc085105a7..419d8ad5e7061 100644 --- a/compiler-builtins/compiler-builtins/src/float/div.rs +++ b/compiler-builtins/compiler-builtins/src/float/div.rs @@ -82,9 +82,7 @@ use core::mem::size_of; use core::ops; -use super::HalfRep; -use crate::float::Float; -use crate::int::{CastFrom, CastInto, DInt, HInt, Int, MinInt}; +use crate::support::{CastFrom, CastInto, DInt, Float, HInt, HalfRep, Int, MinInt}; fn div(a: F, b: F) -> F where diff --git a/compiler-builtins/compiler-builtins/src/float/extend.rs b/compiler-builtins/compiler-builtins/src/float/extend.rs index c4f1fe30e0ea8..58038ce57f834 100644 --- a/compiler-builtins/compiler-builtins/src/float/extend.rs +++ b/compiler-builtins/compiler-builtins/src/float/extend.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::{CastInto, Int, MinInt}; +use crate::support::{CastInto, Float, Int, MinInt}; /// Generic conversion from a narrower to a wider IEEE-754 floating-point type fn extend(a: F) -> R diff --git a/compiler-builtins/compiler-builtins/src/float/mod.rs b/compiler-builtins/compiler-builtins/src/float/mod.rs index 4a379d0d3575b..15318c4928804 100644 --- a/compiler-builtins/compiler-builtins/src/float/mod.rs +++ b/compiler-builtins/compiler-builtins/src/float/mod.rs @@ -6,10 +6,4 @@ pub mod extend; pub mod mul; pub mod pow; pub mod sub; -pub(crate) mod traits; pub mod trunc; - -#[cfg(not(feature = "unstable-public-internals"))] -pub(crate) use traits::{Float, HalfRep}; -#[cfg(feature = "unstable-public-internals")] -pub use traits::{Float, HalfRep}; diff --git a/compiler-builtins/compiler-builtins/src/float/mul.rs b/compiler-builtins/compiler-builtins/src/float/mul.rs index 49a2414eb5c69..ffba2dc41f8a0 100644 --- a/compiler-builtins/compiler-builtins/src/float/mul.rs +++ b/compiler-builtins/compiler-builtins/src/float/mul.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::{CastInto, DInt, HInt, Int, MinInt}; +use crate::support::{CastInto, DInt, Float, HInt, Int, MinInt}; fn mul(a: F, b: F) -> F where diff --git a/compiler-builtins/compiler-builtins/src/float/pow.rs b/compiler-builtins/compiler-builtins/src/float/pow.rs index 6997a9c213c59..2c92971d31397 100644 --- a/compiler-builtins/compiler-builtins/src/float/pow.rs +++ b/compiler-builtins/compiler-builtins/src/float/pow.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::Int; +use crate::support::{Float, Int}; /// Returns `a` raised to the power `b` fn pow(a: F, b: i32) -> F { diff --git a/compiler-builtins/compiler-builtins/src/float/sub.rs b/compiler-builtins/compiler-builtins/src/float/sub.rs index 48ef33b0b826f..11dd3b77d5d1c 100644 --- a/compiler-builtins/compiler-builtins/src/float/sub.rs +++ b/compiler-builtins/compiler-builtins/src/float/sub.rs @@ -1,4 +1,4 @@ -use crate::float::Float; +use crate::support::Float; intrinsics! { #[cfg(f16_enabled)] diff --git a/compiler-builtins/compiler-builtins/src/float/traits.rs b/compiler-builtins/compiler-builtins/src/float/traits.rs deleted file mode 100644 index a30d20900b1c4..0000000000000 --- a/compiler-builtins/compiler-builtins/src/float/traits.rs +++ /dev/null @@ -1,189 +0,0 @@ -use core::ops; - -use crate::int::{DInt, Int, MinInt}; - -/// Wrapper to extract the integer type half of the float's size -pub type HalfRep = <::Int as DInt>::H; - -/// Trait for some basic operations on floats -#[allow(dead_code)] -pub trait Float: - Copy - + core::fmt::Debug - + PartialEq - + PartialOrd - + ops::AddAssign - + ops::MulAssign - + ops::Add - + ops::Sub - + ops::Div - + ops::Rem -{ - /// A uint of the same width as the float - type Int: Int; - - /// A int of the same width as the float - type SignedInt: Int + MinInt; - - /// An int capable of containing the exponent bits plus a sign bit. This is signed. - type ExpInt: Int; - - const ZERO: Self; - const ONE: Self; - - /// The bitwidth of the float type. - const BITS: u32; - - /// The bitwidth of the significand. - const SIG_BITS: u32; - - /// The bitwidth of the exponent. - const EXP_BITS: u32 = Self::BITS - Self::SIG_BITS - 1; - - /// The saturated (maximum bitpattern) value of the exponent, i.e. the infinite - /// representation. - /// - /// This is in the rightmost position, use `EXP_MASK` for the shifted value. - const EXP_SAT: u32 = (1 << Self::EXP_BITS) - 1; - - /// The exponent bias value. - const EXP_BIAS: u32 = Self::EXP_SAT >> 1; - - /// A mask for the sign bit. - const SIGN_MASK: Self::Int; - - /// A mask for the significand. - const SIG_MASK: Self::Int; - - /// The implicit bit of the float format. - const IMPLICIT_BIT: Self::Int; - - /// A mask for the exponent. - const EXP_MASK: Self::Int; - - /// Returns `self` transmuted to `Self::Int` - fn to_bits(self) -> Self::Int; - - /// Returns `self` transmuted to `Self::SignedInt` - fn to_bits_signed(self) -> Self::SignedInt; - - /// Checks if two floats have the same bit representation. *Except* for NaNs! NaN can be - /// represented in multiple different ways. This method returns `true` if two NaNs are - /// compared. - fn eq_repr(self, rhs: Self) -> bool; - - /// Returns true if the sign is negative - fn is_sign_negative(self) -> bool; - - /// Returns the exponent, not adjusting for bias. - fn exp(self) -> Self::ExpInt; - - /// Returns the significand with no implicit bit (or the "fractional" part) - fn frac(self) -> Self::Int; - - /// Returns the significand with implicit bit - fn imp_frac(self) -> Self::Int; - - /// Returns a `Self::Int` transmuted back to `Self` - fn from_bits(a: Self::Int) -> Self; - - /// Constructs a `Self` from its parts. Inputs are treated as bits and shifted into position. - fn from_parts(negative: bool, exponent: Self::Int, significand: Self::Int) -> Self; - - fn abs(self) -> Self { - let abs_mask = !Self::SIGN_MASK; - Self::from_bits(self.to_bits() & abs_mask) - } - - /// Returns (normalized exponent, normalized significand) - fn normalize(significand: Self::Int) -> (i32, Self::Int); - - /// Returns if `self` is subnormal - fn is_subnormal(self) -> bool; -} - -macro_rules! float_impl { - ($ty:ident, $ity:ident, $sity:ident, $expty:ident, $bits:expr, $significand_bits:expr) => { - impl Float for $ty { - type Int = $ity; - type SignedInt = $sity; - type ExpInt = $expty; - - const ZERO: Self = 0.0; - const ONE: Self = 1.0; - - const BITS: u32 = $bits; - const SIG_BITS: u32 = $significand_bits; - - const SIGN_MASK: Self::Int = 1 << (Self::BITS - 1); - const SIG_MASK: Self::Int = (1 << Self::SIG_BITS) - 1; - const IMPLICIT_BIT: Self::Int = 1 << Self::SIG_BITS; - const EXP_MASK: Self::Int = !(Self::SIGN_MASK | Self::SIG_MASK); - - fn to_bits(self) -> Self::Int { - self.to_bits() - } - fn to_bits_signed(self) -> Self::SignedInt { - self.to_bits() as Self::SignedInt - } - fn eq_repr(self, rhs: Self) -> bool { - #[cfg(feature = "mangled-names")] - fn is_nan(x: $ty) -> bool { - // When using mangled-names, the "real" compiler-builtins might not have the - // necessary builtin (__unordtf2) to test whether `f128` is NaN. - // FIXME(f16_f128): Remove once the nightly toolchain has the __unordtf2 builtin - // x is NaN if all the bits of the exponent are set and the significand is non-0 - x.to_bits() & $ty::EXP_MASK == $ty::EXP_MASK && x.to_bits() & $ty::SIG_MASK != 0 - } - #[cfg(not(feature = "mangled-names"))] - fn is_nan(x: $ty) -> bool { - x.is_nan() - } - if is_nan(self) && is_nan(rhs) { - true - } else { - self.to_bits() == rhs.to_bits() - } - } - fn is_sign_negative(self) -> bool { - self.is_sign_negative() - } - fn exp(self) -> Self::ExpInt { - ((self.to_bits() & Self::EXP_MASK) >> Self::SIG_BITS) as Self::ExpInt - } - fn frac(self) -> Self::Int { - self.to_bits() & Self::SIG_MASK - } - fn imp_frac(self) -> Self::Int { - self.frac() | Self::IMPLICIT_BIT - } - fn from_bits(a: Self::Int) -> Self { - Self::from_bits(a) - } - fn from_parts(negative: bool, exponent: Self::Int, significand: Self::Int) -> Self { - Self::from_bits( - ((negative as Self::Int) << (Self::BITS - 1)) - | ((exponent << Self::SIG_BITS) & Self::EXP_MASK) - | (significand & Self::SIG_MASK), - ) - } - fn normalize(significand: Self::Int) -> (i32, Self::Int) { - let shift = significand.leading_zeros().wrapping_sub(Self::EXP_BITS); - ( - 1i32.wrapping_sub(shift as i32), - significand << shift as Self::Int, - ) - } - fn is_subnormal(self) -> bool { - (self.to_bits() & Self::EXP_MASK) == Self::Int::ZERO - } - } - }; -} - -#[cfg(f16_enabled)] -float_impl!(f16, u16, i16, i8, 16, 10); -float_impl!(f32, u32, i32, i16, 32, 23); -float_impl!(f64, u64, i64, i16, 64, 52); -#[cfg(f128_enabled)] -float_impl!(f128, u128, i128, i16, 128, 112); diff --git a/compiler-builtins/compiler-builtins/src/float/trunc.rs b/compiler-builtins/compiler-builtins/src/float/trunc.rs index 93db5d8bbdeb1..1a88b0649fda3 100644 --- a/compiler-builtins/compiler-builtins/src/float/trunc.rs +++ b/compiler-builtins/compiler-builtins/src/float/trunc.rs @@ -1,5 +1,4 @@ -use crate::float::Float; -use crate::int::{CastInto, Int, MinInt}; +use crate::support::{CastInto, Float, Int, MinInt}; fn trunc(a: F) -> R where diff --git a/compiler-builtins/compiler-builtins/src/hexagon.rs b/compiler-builtins/compiler-builtins/src/hexagon.rs index a5c7b4dfdda91..46062fc3700d8 100644 --- a/compiler-builtins/compiler-builtins/src/hexagon.rs +++ b/compiler-builtins/compiler-builtins/src/hexagon.rs @@ -1,7 +1,66 @@ use core::arch::global_asm; +// Hexagon L1 cache line size in bytes (Hexagon PRM sections 5.10.3-5.10.4). +const CACHE_LINE_SIZE: usize = 32; + +intrinsics! { + pub unsafe extern "C" fn __clear_cache(start: *mut u8, end: *mut u8) { + // Hexagon has separate instruction and data caches. + let mask = !(CACHE_LINE_SIZE - 1); + let start_line = start.addr() & mask; + let end_addr = end.addr(); + + // Clean and invalidate data cache to push new code to memory and + // invalidate stale lines in the L2 cache. + let mut addr = start_line; + while addr < end_addr { + unsafe { + core::arch::asm!( + "dccleaninva({addr})", + addr = in(reg) addr, + options(nostack, preserves_flags), + ); + } + addr += CACHE_LINE_SIZE; + } + + // Invalidate instruction cache so it re-fetches from memory. + addr = start_line; + while addr < end_addr { + unsafe { + core::arch::asm!( + "icinva({addr})", + addr = in(reg) addr, + options(nostack, preserves_flags), + ); + } + addr += CACHE_LINE_SIZE; + } + + // Instruction sync barrier ensures subsequent fetches see the new code. + unsafe { + core::arch::asm!("isync", options(nostack, preserves_flags)); + } + } +} + global_asm!(include_str!("hexagon/func_macro.s"), options(raw)); +global_asm!( + include_str!("hexagon/common_entry_exit_abi1.s"), + options(raw) +); + +global_asm!( + include_str!("hexagon/common_entry_exit_abi2.s"), + options(raw) +); + +global_asm!( + include_str!("hexagon/common_entry_exit_legacy.s"), + options(raw) +); + global_asm!(include_str!("hexagon/dfaddsub.s"), options(raw)); global_asm!(include_str!("hexagon/dfdiv.s"), options(raw)); diff --git a/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi1.s b/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi1.s new file mode 100644 index 0000000000000..61425abaad5ae --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi1.s @@ -0,0 +1,42 @@ + +FUNCTION_BEGIN __save_r24_through_r27 + memd(fp+#-16) = r27:26 +FALLTHROUGH_TAIL_CALL __save_r24_through_r27 __save_r24_through_r25 + { + memd(fp+#-8) = r25:24 + jumpr lr + } +FUNCTION_END __save_r24_through_r25 + + +FUNCTION_BEGIN __restore_r24_through_r27_and_deallocframe_before_tailcall + r27:26 = memd(fp+#-16) +FALLTHROUGH_TAIL_CALL __restore_r24_through_r27_and_deallocframe_before_tailcall __restore_r24_through_r25_and_deallocframe_before_tailcall + { + r25:24 = memd(fp+#-8) + deallocframe + jumpr lr + } +FUNCTION_END __restore_r24_through_r25_and_deallocframe_before_tailcall + + +FUNCTION_BEGIN __restore_r24_through_r27_and_deallocframe + { + lr = memw(fp+#4) + r27:26 = memd(fp+#-16) + } + { + r25:24 = memd(fp+#-8) + deallocframe + jumpr lr + } +FUNCTION_END __restore_r24_through_r27_and_deallocframe + + +FUNCTION_BEGIN __restore_r24_through_r25_and_deallocframe + { + r25:24 = memd(fp+#-8) + deallocframe + } + jumpr lr +FUNCTION_END __restore_r24_through_r25_and_deallocframe diff --git a/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi2.s b/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi2.s new file mode 100644 index 0000000000000..8734310fc3758 --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_abi2.s @@ -0,0 +1,237 @@ + + .macro ABI2_FUNCTION_BEGIN name + .p2align 2 + .section .text.\name,"ax",@progbits + .globl \name + .type \name, @function +\name: + .endm + + .macro ABI2_FUNCTION_END name + .size \name, . - \name + .endm + + +ABI2_FUNCTION_BEGIN __save_r16_through_r27 + { + memd(fp+#-48) = r27:26 + memd(fp+#-40) = r25:24 + } + { + memd(fp+#-32) = r23:22 + memd(fp+#-24) = r21:20 + } + { + memd(fp+#-16) = r19:18 + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r27 + +ABI2_FUNCTION_BEGIN __save_r16_through_r25 + { + memd(fp+#-40) = r25:24 + memd(fp+#-32) = r23:22 + } + { + memd(fp+#-24) = r21:20 + memd(fp+#-16) = r19:18 + } + { + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r25 + +ABI2_FUNCTION_BEGIN __save_r16_through_r23 + { + memd(fp+#-32) = r23:22 + memd(fp+#-24) = r21:20 + } + { + memd(fp+#-16) = r19:18 + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r23 + +ABI2_FUNCTION_BEGIN __save_r16_through_r21 + { + memd(fp+#-24) = r21:20 + memd(fp+#-16) = r19:18 + } + { + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r21 + +ABI2_FUNCTION_BEGIN __save_r16_through_r19 + { + memd(fp+#-16) = r19:18 + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r19 + +ABI2_FUNCTION_BEGIN __save_r16_through_r17 + { + memd(fp+#-8) = r17:16 + jumpr lr + } +ABI2_FUNCTION_END __save_r16_through_r17 + + +ABI2_FUNCTION_BEGIN __restore_r16_through_r27_and_deallocframe_before_tailcall + r27:26 = memd(fp+#-48) + { + r25:24 = memd(fp+#-40) + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r27_and_deallocframe_before_tailcall + +ABI2_FUNCTION_BEGIN __restore_r16_through_r25_and_deallocframe_before_tailcall + { + r25:24 = memd(fp+#-40) + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r25_and_deallocframe_before_tailcall + +ABI2_FUNCTION_BEGIN __restore_r16_through_r23_and_deallocframe_before_tailcall + { + r23:22 = memd(fp+#-32) + r21:20 = memd(fp+#-24) + } + r19:18 = memd(fp+#-16) + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r23_and_deallocframe_before_tailcall + + +ABI2_FUNCTION_BEGIN __restore_r16_through_r21_and_deallocframe_before_tailcall + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r21_and_deallocframe_before_tailcall + +ABI2_FUNCTION_BEGIN __restore_r16_through_r19_and_deallocframe_before_tailcall + r19:18 = memd(fp+#-16) + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r19_and_deallocframe_before_tailcall + +ABI2_FUNCTION_BEGIN __restore_r16_through_r17_and_deallocframe_before_tailcall + { + r17:16 = memd(fp+#-8) + deallocframe + jumpr lr + } +ABI2_FUNCTION_END __restore_r16_through_r17_and_deallocframe_before_tailcall + + +ABI2_FUNCTION_BEGIN __restore_r16_through_r27_and_deallocframe + r27:26 = memd(fp+#-48) + { + r25:24 = memd(fp+#-40) + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r27_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r25_and_deallocframe + { + r25:24 = memd(fp+#-40) + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r25_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r23_and_deallocframe + { + r23:22 = memd(fp+#-32) + } + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r23_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r21_and_deallocframe + { + r21:20 = memd(fp+#-24) + r19:18 = memd(fp+#-16) + } + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r21_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r19_and_deallocframe + { + r19:18 = memd(fp+#-16) + r17:16 = memd(fp+#-8) + } + { + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r19_and_deallocframe + +ABI2_FUNCTION_BEGIN __restore_r16_through_r17_and_deallocframe + { + r17:16 = memd(fp+#-8) + dealloc_return + } +ABI2_FUNCTION_END __restore_r16_through_r17_and_deallocframe + +ABI2_FUNCTION_BEGIN __deallocframe + dealloc_return +ABI2_FUNCTION_END __deallocframe diff --git a/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_legacy.s b/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_legacy.s new file mode 100644 index 0000000000000..4c539ea91f4af --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/hexagon/common_entry_exit_legacy.s @@ -0,0 +1,92 @@ + +FUNCTION_BEGIN __save_r27_through_r16 + memd(fp+#-48) = r17:16 +FALLTHROUGH_TAIL_CALL __save_r27_through_r16 __save_r27_through_r18 + memd(fp+#-40) = r19:18 +FALLTHROUGH_TAIL_CALL __save_r27_through_r18 __save_r27_through_r20 + memd(fp+#-32) = r21:20 +FALLTHROUGH_TAIL_CALL __save_r27_through_r20 __save_r27_through_r22 + memd(fp+#-24) = r23:22 +FALLTHROUGH_TAIL_CALL __save_r27_through_r22 __save_r27_through_r24 + memd(fp+#-16) = r25:24 + { + memd(fp+#-8) = r27:26 + jumpr lr + } +FUNCTION_END __save_r27_through_r24 + + +FUNCTION_BEGIN __restore_r27_through_r20_and_deallocframe_before_sibcall + { + r21:20 = memd(fp+#-32) + r23:22 = memd(fp+#-24) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r20_and_deallocframe_before_sibcall __restore_r27_through_r24_and_deallocframe_before_sibcall + { + r25:24 = memd(fp+#-16) + jump __restore_r27_through_r26_and_deallocframe_before_sibcall + } +FUNCTION_END __restore_r27_through_r24_and_deallocframe_before_sibcall + + +FUNCTION_BEGIN __restore_r27_through_r16_and_deallocframe_before_sibcall + r17:16 = memd(fp+#-48) +FALLTHROUGH_TAIL_CALL __restore_r27_through_r16_and_deallocframe_before_sibcall __restore_r27_through_r18_and_deallocframe_before_sibcall + { + r19:18 = memd(fp+#-40) + r21:20 = memd(fp+#-32) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r18_and_deallocframe_before_sibcall __restore_r27_through_r22_and_deallocframe_before_sibcall + { + r23:22 = memd(fp+#-24) + r25:24 = memd(fp+#-16) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r22_and_deallocframe_before_sibcall __restore_r27_through_r26_and_deallocframe_before_sibcall + { + r27:26 = memd(fp+#-8) + deallocframe + jumpr lr + } +FUNCTION_END __restore_r27_through_r26_and_deallocframe_before_sibcall + + +FUNCTION_BEGIN __restore_r27_through_r16_and_deallocframe + { + r17:16 = memd(fp+#-48) + r19:18 = memd(fp+#-40) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r16_and_deallocframe __restore_r27_through_r20_and_deallocframe + { + r21:20 = memd(fp+#-32) + r23:22 = memd(fp+#-24) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r20_and_deallocframe __restore_r27_through_r24_and_deallocframe + { + lr = memw(fp+#4) + r25:24 = memd(fp+#-16) + } + { + r27:26 = memd(fp+#-8) + deallocframe + jumpr lr + } +FUNCTION_END __restore_r27_through_r24_and_deallocframe + + +FUNCTION_BEGIN __restore_r27_through_r18_and_deallocframe + { + r19:18 = memd(fp+#-40) + r21:20 = memd(fp+#-32) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r18_and_deallocframe __restore_r27_through_r22_and_deallocframe + { + r23:22 = memd(fp+#-24) + r25:24 = memd(fp+#-16) + } +FALLTHROUGH_TAIL_CALL __restore_r27_through_r22_and_deallocframe __restore_r27_through_r26_and_deallocframe + { + r27:26 = memd(fp+#-8) + deallocframe + } + jumpr lr +FUNCTION_END __restore_r27_through_r26_and_deallocframe diff --git a/compiler-builtins/compiler-builtins/src/hexagon/func_macro.s b/compiler-builtins/compiler-builtins/src/hexagon/func_macro.s index 9a1e11aebcb50..f5514cb7f057b 100644 --- a/compiler-builtins/compiler-builtins/src/hexagon/func_macro.s +++ b/compiler-builtins/compiler-builtins/src/hexagon/func_macro.s @@ -10,3 +10,11 @@ .size \name, . - \name .endm + .macro FALLTHROUGH_TAIL_CALL name0 name1 + .size \name0, . - \name0 + .globl \name1 + .type \name1, @function + .falign +\name1: + .endm + diff --git a/compiler-builtins/compiler-builtins/src/hexagon/memcpy_likely_aligned.s b/compiler-builtins/compiler-builtins/src/hexagon/memcpy_likely_aligned.s index 7e9b62f6a791c..416675833192e 100644 --- a/compiler-builtins/compiler-builtins/src/hexagon/memcpy_likely_aligned.s +++ b/compiler-builtins/compiler-builtins/src/hexagon/memcpy_likely_aligned.s @@ -31,6 +31,35 @@ FUNCTION_BEGIN __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes } FUNCTION_END __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes +FUNCTION_BEGIN __hexagon_memcpy_dwloop + { + r5:4 = memd(r1) + r3 = #-3 + } + { + memd(r0++#8) = r5:4 + r5:4 = memd(r1+#8) + r3 += lsr(r2,#3) + } + { + memd(r0++#8) = r5:4 + r5:4 = memd(r1+#16) + r1 = add(r1,#24) + loop0(1f,r3) + } + .falign +1: + { + memd(r0++#8) = r5:4 + r5:4 = memd(r1++#8) + }:endloop0 + { + memd(r0) = r5:4 + r0 -= add(r2,#-8) + jumpr r31 + } +FUNCTION_END __hexagon_memcpy_dwloop + .Lmemcpy_call: jump memcpy@PLT diff --git a/compiler-builtins/compiler-builtins/src/int/addsub.rs b/compiler-builtins/compiler-builtins/src/int/addsub.rs index b2b21fc2c4401..ab5e8e1b5d873 100644 --- a/compiler-builtins/compiler-builtins/src/int/addsub.rs +++ b/compiler-builtins/compiler-builtins/src/int/addsub.rs @@ -1,4 +1,4 @@ -use crate::int::{DInt, Int, MinInt}; +use crate::support::{DInt, Int, MinInt}; trait UAddSub: DInt + Int { fn uadd(self, other: Self) -> Self { diff --git a/compiler-builtins/compiler-builtins/src/int/big.rs b/compiler-builtins/compiler-builtins/src/int/big.rs deleted file mode 100644 index 8e06009090c09..0000000000000 --- a/compiler-builtins/compiler-builtins/src/int/big.rs +++ /dev/null @@ -1,295 +0,0 @@ -//! Integers used for wide operations, larger than `u128`. - -#![allow(unused)] - -use core::{fmt, ops}; - -use crate::int::{DInt, HInt, Int, MinInt}; - -const WORD_LO_MASK: u64 = 0x00000000ffffffff; -const WORD_HI_MASK: u64 = 0xffffffff00000000; -const WORD_FULL_MASK: u64 = 0xffffffffffffffff; -const U128_LO_MASK: u128 = u64::MAX as u128; -const U128_HI_MASK: u128 = (u64::MAX as u128) << 64; - -/// A 256-bit unsigned integer represented as 4 64-bit limbs. -/// -/// Each limb is a native-endian number, but the array is little-limb-endian. -#[allow(non_camel_case_types)] -#[derive(Clone, Copy, Debug, PartialEq, PartialOrd)] -pub struct u256(pub [u64; 4]); - -impl u256 { - pub const MAX: Self = Self([u64::MAX, u64::MAX, u64::MAX, u64::MAX]); - - /// Reinterpret as a signed integer - pub fn signed(self) -> i256 { - i256(self.0) - } -} - -/// A 256-bit signed integer represented as 4 64-bit limbs. -/// -/// Each limb is a native-endian number, but the array is little-limb-endian. -#[allow(non_camel_case_types)] -#[derive(Clone, Copy, Debug, PartialEq, PartialOrd)] -pub struct i256(pub [u64; 4]); - -impl i256 { - /// Reinterpret as an unsigned integer - pub fn unsigned(self) -> u256 { - u256(self.0) - } -} - -impl MinInt for u256 { - type OtherSign = i256; - - type Unsigned = u256; - - const SIGNED: bool = false; - const BITS: u32 = 256; - const ZERO: Self = Self([0u64; 4]); - const ONE: Self = Self([1, 0, 0, 0]); - const MIN: Self = Self([0u64; 4]); - const MAX: Self = Self([u64::MAX; 4]); -} - -impl MinInt for i256 { - type OtherSign = u256; - - type Unsigned = u256; - - const SIGNED: bool = false; - const BITS: u32 = 256; - const ZERO: Self = Self([0u64; 4]); - const ONE: Self = Self([1, 0, 0, 0]); - const MIN: Self = Self([0, 0, 0, 1 << 63]); - const MAX: Self = Self([u64::MAX, u64::MAX, u64::MAX, u64::MAX >> 1]); -} - -macro_rules! impl_common { - ($ty:ty) => { - impl ops::BitOr for $ty { - type Output = Self; - - fn bitor(mut self, rhs: Self) -> Self::Output { - self.0[0] |= rhs.0[0]; - self.0[1] |= rhs.0[1]; - self.0[2] |= rhs.0[2]; - self.0[3] |= rhs.0[3]; - self - } - } - - impl ops::Not for $ty { - type Output = Self; - - fn not(self) -> Self::Output { - Self([!self.0[0], !self.0[1], !self.0[2], !self.0[3]]) - } - } - - impl ops::Shl for $ty { - type Output = Self; - - fn shl(self, rhs: u32) -> Self::Output { - unimplemented!("only used to meet trait bounds") - } - } - }; -} - -impl_common!(i256); -impl_common!(u256); - -impl ops::Shr for u256 { - type Output = Self; - - fn shr(self, rhs: u32) -> Self::Output { - assert!(rhs < Self::BITS, "attempted to shift right with overflow"); - - if rhs == 0 { - return self; - } - - let mut ret = self; - let byte_shift = rhs / 64; - let bit_shift = rhs % 64; - - for idx in 0..4 { - let base_idx = idx + byte_shift as usize; - - let Some(base) = ret.0.get(base_idx) else { - ret.0[idx] = 0; - continue; - }; - - let mut new_val = base >> bit_shift; - - if let Some(new) = ret.0.get(base_idx + 1) { - new_val |= new.overflowing_shl(64 - bit_shift).0; - } - - ret.0[idx] = new_val; - } - - ret - } -} - -macro_rules! word { - (1, $val:expr) => { - (($val >> (32 * 3)) & Self::from(WORD_LO_MASK)) as u64 - }; - (2, $val:expr) => { - (($val >> (32 * 2)) & Self::from(WORD_LO_MASK)) as u64 - }; - (3, $val:expr) => { - (($val >> (32 * 1)) & Self::from(WORD_LO_MASK)) as u64 - }; - (4, $val:expr) => { - (($val >> (32 * 0)) & Self::from(WORD_LO_MASK)) as u64 - }; -} - -impl HInt for u128 { - type D = u256; - - fn widen(self) -> Self::D { - let w0 = self & u128::from(u64::MAX); - let w1 = (self >> u64::BITS) & u128::from(u64::MAX); - u256([w0 as u64, w1 as u64, 0, 0]) - } - - fn zero_widen(self) -> Self::D { - self.widen() - } - - fn zero_widen_mul(self, rhs: Self) -> Self::D { - let product11: u64 = word!(1, self) * word!(1, rhs); - let product12: u64 = word!(1, self) * word!(2, rhs); - let product13: u64 = word!(1, self) * word!(3, rhs); - let product14: u64 = word!(1, self) * word!(4, rhs); - let product21: u64 = word!(2, self) * word!(1, rhs); - let product22: u64 = word!(2, self) * word!(2, rhs); - let product23: u64 = word!(2, self) * word!(3, rhs); - let product24: u64 = word!(2, self) * word!(4, rhs); - let product31: u64 = word!(3, self) * word!(1, rhs); - let product32: u64 = word!(3, self) * word!(2, rhs); - let product33: u64 = word!(3, self) * word!(3, rhs); - let product34: u64 = word!(3, self) * word!(4, rhs); - let product41: u64 = word!(4, self) * word!(1, rhs); - let product42: u64 = word!(4, self) * word!(2, rhs); - let product43: u64 = word!(4, self) * word!(3, rhs); - let product44: u64 = word!(4, self) * word!(4, rhs); - - let sum0: u128 = u128::from(product44); - let sum1: u128 = u128::from(product34) + u128::from(product43); - let sum2: u128 = u128::from(product24) + u128::from(product33) + u128::from(product42); - let sum3: u128 = u128::from(product14) - + u128::from(product23) - + u128::from(product32) - + u128::from(product41); - let sum4: u128 = u128::from(product13) + u128::from(product22) + u128::from(product31); - let sum5: u128 = u128::from(product12) + u128::from(product21); - let sum6: u128 = u128::from(product11); - - let r0: u128 = - (sum0 & u128::from(WORD_FULL_MASK)) + ((sum1 & u128::from(WORD_LO_MASK)) << 32); - let r1: u128 = (sum0 >> 64) - + ((sum1 >> 32) & u128::from(WORD_FULL_MASK)) - + (sum2 & u128::from(WORD_FULL_MASK)) - + ((sum3 << 32) & u128::from(WORD_HI_MASK)); - - let (lo, carry) = r0.overflowing_add(r1 << 64); - let hi = (r1 >> 64) - + (sum1 >> 96) - + (sum2 >> 64) - + (sum3 >> 32) - + sum4 - + (sum5 << 32) - + (sum6 << 64) - + u128::from(carry); - - u256([ - (lo & U128_LO_MASK) as u64, - ((lo >> 64) & U128_LO_MASK) as u64, - (hi & U128_LO_MASK) as u64, - ((hi >> 64) & U128_LO_MASK) as u64, - ]) - } - - fn widen_mul(self, rhs: Self) -> Self::D { - self.zero_widen_mul(rhs) - } - - fn widen_hi(self) -> Self::D { - self.widen() << ::BITS - } -} - -impl HInt for i128 { - type D = i256; - - fn widen(self) -> Self::D { - let mut ret = self.unsigned().zero_widen().signed(); - if self.is_negative() { - ret.0[2] = u64::MAX; - ret.0[3] = u64::MAX; - } - ret - } - - fn zero_widen(self) -> Self::D { - self.unsigned().zero_widen().signed() - } - - fn zero_widen_mul(self, rhs: Self) -> Self::D { - self.unsigned().zero_widen_mul(rhs.unsigned()).signed() - } - - fn widen_mul(self, rhs: Self) -> Self::D { - unimplemented!("signed i128 widening multiply is not used") - } - - fn widen_hi(self) -> Self::D { - self.widen() << ::BITS - } -} - -impl DInt for u256 { - type H = u128; - - fn lo(self) -> Self::H { - let mut tmp = [0u8; 16]; - tmp[..8].copy_from_slice(&self.0[0].to_le_bytes()); - tmp[8..].copy_from_slice(&self.0[1].to_le_bytes()); - u128::from_le_bytes(tmp) - } - - fn hi(self) -> Self::H { - let mut tmp = [0u8; 16]; - tmp[..8].copy_from_slice(&self.0[2].to_le_bytes()); - tmp[8..].copy_from_slice(&self.0[3].to_le_bytes()); - u128::from_le_bytes(tmp) - } -} - -impl DInt for i256 { - type H = i128; - - fn lo(self) -> Self::H { - let mut tmp = [0u8; 16]; - tmp[..8].copy_from_slice(&self.0[0].to_le_bytes()); - tmp[8..].copy_from_slice(&self.0[1].to_le_bytes()); - i128::from_le_bytes(tmp) - } - - fn hi(self) -> Self::H { - let mut tmp = [0u8; 16]; - tmp[..8].copy_from_slice(&self.0[2].to_le_bytes()); - tmp[8..].copy_from_slice(&self.0[3].to_le_bytes()); - i128::from_le_bytes(tmp) - } -} diff --git a/compiler-builtins/compiler-builtins/src/int/leading_zeros.rs b/compiler-builtins/compiler-builtins/src/int/leading_zeros.rs index aa5cb39935ad8..3b920ecff6b20 100644 --- a/compiler-builtins/compiler-builtins/src/int/leading_zeros.rs +++ b/compiler-builtins/compiler-builtins/src/int/leading_zeros.rs @@ -9,7 +9,7 @@ pub use implementation::{leading_zeros_default, leading_zeros_riscv}; pub(crate) use implementation::{leading_zeros_default, leading_zeros_riscv}; mod implementation { - use crate::int::{CastFrom, Int}; + use crate::support::{CastFrom, Int}; /// Returns the number of leading binary zeros in `x`. #[allow(dead_code)] diff --git a/compiler-builtins/compiler-builtins/src/int/mod.rs b/compiler-builtins/compiler-builtins/src/int/mod.rs index 518ccb23f8009..cd4011a933815 100644 --- a/compiler-builtins/compiler-builtins/src/int/mod.rs +++ b/compiler-builtins/compiler-builtins/src/int/mod.rs @@ -1,18 +1,10 @@ mod specialized_div_rem; pub mod addsub; -mod big; pub mod bswap; pub mod leading_zeros; pub mod mul; pub mod sdiv; pub mod shift; pub mod trailing_zeros; -mod traits; pub mod udiv; - -pub use big::{i256, u256}; -#[cfg(not(feature = "unstable-public-internals"))] -pub(crate) use traits::{CastFrom, CastInto, DInt, HInt, Int, MinInt}; -#[cfg(feature = "unstable-public-internals")] -pub use traits::{CastFrom, CastInto, DInt, HInt, Int, MinInt}; diff --git a/compiler-builtins/compiler-builtins/src/int/mul.rs b/compiler-builtins/compiler-builtins/src/int/mul.rs index 040c69342d148..9331ab60a4fc1 100644 --- a/compiler-builtins/compiler-builtins/src/int/mul.rs +++ b/compiler-builtins/compiler-builtins/src/int/mul.rs @@ -1,4 +1,4 @@ -use crate::int::{DInt, HInt, Int}; +use crate::support::{DInt, HInt, Int}; trait Mul: DInt + Int where @@ -98,11 +98,63 @@ impl_signed_mulo!(i64_overflowing_mul, i64, u64); impl_signed_mulo!(i128_overflowing_mul, i128, u128); intrinsics! { + // Ancient Egyptian/Ethiopian/Russian multiplication method + // see https://en.wikipedia.org/wiki/Ancient_Egyptian_multiplication + // + // This is a long-available stock algorithm; e.g. it is documented in + // Knuth's "The Art of Computer Programming" volume 2 (under the section + // "Evaluation of Powers") since at least the 2nd edition (1981). + // + // The main attraction of this method is that it implements (software) + // multiplication atop four simple operations: doubling, halving, checking + // if a value is even/odd, and addition. This is *not* considered to be the + // fastest multiplication method, but it may be amongst the simplest (and + // smallest with respect to code size). + // + // for reference, see also implementation from gcc + // https://raw.githubusercontent.com/gcc-mirror/gcc/master/libgcc/config/epiphany/mulsi3.c + // + // and from LLVM (in relatively readable RISC-V assembly): + // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/riscv/int_mul_impl.inc + #[cfg(any(target_arch = "riscv32", target_arch = "riscv64", target_arch = "m68k"))] + pub extern "C" fn __mulsi3(a: u32, b: u32) -> u32 { + let (mut a, mut b) = (a, b); + let mut r: u32 = 0; + + while a > 0 { + if a & 1 > 0 { + r = r.wrapping_add(b); + } + a >>= 1; + b <<= 1; + } + + r + } + #[maybe_use_optimized_c_shim] #[arm_aeabi_alias = __aeabi_lmul] - #[cfg(any(not(any(target_arch = "riscv32", target_arch = "riscv64")), target_feature = "m"))] pub extern "C" fn __muldi3(a: u64, b: u64) -> u64 { - a.mul(b) + #[cfg(all(any(target_arch = "riscv32", target_arch = "riscv64"), not(target_feature = "m")))] + { + let (mut a, mut b) = (a, b); + let mut r: u64 = 0; + + while a > 0 { + if a & 1 > 0 { + r = r.wrapping_add(b); + } + a >>= 1; + b <<= 1; + } + + r + } + + #[cfg(not(all(any(target_arch = "riscv32", target_arch = "riscv64"), not(target_feature = "m"))))] + { + a.mul(b) + } } pub extern "C" fn __multi3(a: i128, b: i128) -> i128 { @@ -139,4 +191,5 @@ intrinsics! { *oflow = o.into(); mul } + } diff --git a/compiler-builtins/compiler-builtins/src/int/shift.rs b/compiler-builtins/compiler-builtins/src/int/shift.rs index a85c1b33d6714..f5cac9ad4e367 100644 --- a/compiler-builtins/compiler-builtins/src/int/shift.rs +++ b/compiler-builtins/compiler-builtins/src/int/shift.rs @@ -1,4 +1,4 @@ -use crate::int::{DInt, HInt, Int, MinInt}; +use crate::support::{DInt, HInt, Int, MinInt}; trait Ashl: DInt { /// Returns `a << b`, requires `b < Self::BITS` diff --git a/compiler-builtins/compiler-builtins/src/int/specialized_div_rem/mod.rs b/compiler-builtins/compiler-builtins/src/int/specialized_div_rem/mod.rs index 5ffe1f59b4db6..902c191d65285 100644 --- a/compiler-builtins/compiler-builtins/src/int/specialized_div_rem/mod.rs +++ b/compiler-builtins/compiler-builtins/src/int/specialized_div_rem/mod.rs @@ -144,7 +144,7 @@ fn u64_by_u64_div_rem(duo: u64, div: u64) -> (u64, u64) { target_family = "wasm", not(any(target_pointer_width = "16", target_pointer_width = "32")), ), - not(all(not(feature = "no-asm"), target_arch = "x86_64")), + not(all(feature = "arch", target_arch = "x86_64")), not(any(target_arch = "sparc", target_arch = "sparc64")) ))] impl_trifecta!( @@ -165,7 +165,7 @@ impl_trifecta!( target_family = "wasm", not(any(target_pointer_width = "16", target_pointer_width = "32")), )), - not(all(not(feature = "no-asm"), target_arch = "x86_64")), + not(all(feature = "arch", target_arch = "x86_64")), not(any(target_arch = "sparc", target_arch = "sparc64")) ))] impl_delegate!( @@ -186,7 +186,7 @@ impl_delegate!( /// /// If the quotient does not fit in a `u64`, a floating point exception occurs. /// If `div == 0`, then a division by zero exception occurs. -#[cfg(all(not(feature = "no-asm"), target_arch = "x86_64"))] +#[cfg(all(feature = "arch", target_arch = "x86_64"))] #[inline] unsafe fn u128_by_u64_div_rem(duo: u128, div: u64) -> (u64, u64) { let duo_lo = duo as u64; @@ -208,7 +208,7 @@ unsafe fn u128_by_u64_div_rem(duo: u128, div: u64) -> (u64, u64) { } // use `asymmetric` instead of `trifecta` on x86_64 -#[cfg(all(not(feature = "no-asm"), target_arch = "x86_64"))] +#[cfg(all(feature = "arch", target_arch = "x86_64"))] impl_asymmetric!( u128_div_rem, zero_div_fn, @@ -237,7 +237,7 @@ fn u32_by_u32_div_rem(duo: u32, div: u32) -> (u32, u32) { // When not on x86 and the pointer width is not 64, use `delegate` since the division size is larger // than register size. #[cfg(all( - not(all(not(feature = "no-asm"), target_arch = "x86")), + not(all(feature = "arch", target_arch = "x86")), not(target_pointer_width = "64") ))] impl_delegate!( @@ -254,7 +254,7 @@ impl_delegate!( // When not on x86 and the pointer width is 64, use `binary_long`. #[cfg(all( - not(all(not(feature = "no-asm"), target_arch = "x86")), + not(all(feature = "arch", target_arch = "x86")), target_pointer_width = "64" ))] impl_binary_long!( @@ -272,7 +272,7 @@ impl_binary_long!( /// /// If the quotient does not fit in a `u32`, a floating point exception occurs. /// If `div == 0`, then a division by zero exception occurs. -#[cfg(all(not(feature = "no-asm"), target_arch = "x86"))] +#[cfg(all(feature = "arch", target_arch = "x86"))] #[inline] unsafe fn u64_by_u32_div_rem(duo: u64, div: u32) -> (u32, u32) { let duo_lo = duo as u32; @@ -294,7 +294,7 @@ unsafe fn u64_by_u32_div_rem(duo: u64, div: u32) -> (u32, u32) { } // use `asymmetric` instead of `delegate` on x86 -#[cfg(all(not(feature = "no-asm"), target_arch = "x86"))] +#[cfg(all(feature = "arch", target_arch = "x86"))] impl_asymmetric!( u64_div_rem, zero_div_fn, diff --git a/compiler-builtins/compiler-builtins/src/int/trailing_zeros.rs b/compiler-builtins/compiler-builtins/src/int/trailing_zeros.rs index 1b0ae5b73ad24..f42e9926dbb11 100644 --- a/compiler-builtins/compiler-builtins/src/int/trailing_zeros.rs +++ b/compiler-builtins/compiler-builtins/src/int/trailing_zeros.rs @@ -4,7 +4,7 @@ pub use implementation::trailing_zeros; pub(crate) use implementation::trailing_zeros; mod implementation { - use crate::int::{CastFrom, Int}; + use crate::support::{CastFrom, Int}; /// Returns number of trailing binary zeros in `x`. #[allow(dead_code)] diff --git a/compiler-builtins/compiler-builtins/src/int/traits.rs b/compiler-builtins/compiler-builtins/src/int/traits.rs deleted file mode 100644 index 25b9718ad53fb..0000000000000 --- a/compiler-builtins/compiler-builtins/src/int/traits.rs +++ /dev/null @@ -1,99 +0,0 @@ -pub use crate::support::{CastFrom, CastInto, Int, MinInt}; - -/// Trait for integers twice the bit width of another integer. This is implemented for all -/// primitives except for `u8`, because there is not a smaller primitive. -pub trait DInt: MinInt { - /// Integer that is half the bit width of the integer this trait is implemented for - type H: HInt; - - /// Returns the low half of `self` - fn lo(self) -> Self::H; - /// Returns the high half of `self` - fn hi(self) -> Self::H; - /// Returns the low and high halves of `self` as a tuple - fn lo_hi(self) -> (Self::H, Self::H) { - (self.lo(), self.hi()) - } - /// Constructs an integer using lower and higher half parts - fn from_lo_hi(lo: Self::H, hi: Self::H) -> Self { - lo.zero_widen() | hi.widen_hi() - } -} - -/// Trait for integers half the bit width of another integer. This is implemented for all -/// primitives except for `u128`, because it there is not a larger primitive. -pub trait HInt: Int { - /// Integer that is double the bit width of the integer this trait is implemented for - type D: DInt + MinInt; - - // NB: some of the below methods could have default implementations (e.g. `widen_hi`), but for - // unknown reasons this can cause infinite recursion when optimizations are disabled. See - // for context. - - /// Widens (using default extension) the integer to have double bit width - fn widen(self) -> Self::D; - /// Widens (zero extension only) the integer to have double bit width. This is needed to get - /// around problems with associated type bounds (such as `Int`) being unstable - fn zero_widen(self) -> Self::D; - /// Widens the integer to have double bit width and shifts the integer into the higher bits - fn widen_hi(self) -> Self::D; - /// Widening multiplication with zero widening. This cannot overflow. - fn zero_widen_mul(self, rhs: Self) -> Self::D; - /// Widening multiplication. This cannot overflow. - fn widen_mul(self, rhs: Self) -> Self::D; -} - -macro_rules! impl_d_int { - ($($X:ident $D:ident),*) => { - $( - impl DInt for $D { - type H = $X; - - fn lo(self) -> Self::H { - self as $X - } - fn hi(self) -> Self::H { - (self >> <$X as MinInt>::BITS) as $X - } - } - )* - }; -} - -macro_rules! impl_h_int { - ($($H:ident $uH:ident $X:ident),*) => { - $( - impl HInt for $H { - type D = $X; - - fn widen(self) -> Self::D { - self as $X - } - fn zero_widen(self) -> Self::D { - (self as $uH) as $X - } - fn zero_widen_mul(self, rhs: Self) -> Self::D { - self.zero_widen().wrapping_mul(rhs.zero_widen()) - } - fn widen_mul(self, rhs: Self) -> Self::D { - self.widen().wrapping_mul(rhs.widen()) - } - fn widen_hi(self) -> Self::D { - (self as $X) << ::BITS - } - } - )* - }; -} - -impl_d_int!(u8 u16, u16 u32, u32 u64, u64 u128, i8 i16, i16 i32, i32 i64, i64 i128); -impl_h_int!( - u8 u8 u16, - u16 u16 u32, - u32 u32 u64, - u64 u64 u128, - i8 u8 i16, - i16 u16 i32, - i32 u32 i64, - i64 u64 i128 -); diff --git a/compiler-builtins/compiler-builtins/src/lib.rs b/compiler-builtins/compiler-builtins/src/lib.rs index 07960222f20f0..9e847206caf19 100644 --- a/compiler-builtins/compiler-builtins/src/lib.rs +++ b/compiler-builtins/compiler-builtins/src/lib.rs @@ -48,6 +48,9 @@ pub mod mem; pub mod sync; // `libm` expects its `support` module to be available in the crate root. +#[cfg(feature = "unstable-public-internals")] +pub use math::libm_math::support; +#[cfg(not(feature = "unstable-public-internals"))] use math::libm_math::support; #[cfg(target_arch = "arm")] @@ -60,7 +63,10 @@ pub mod aarch64; // in the builtins-test tests. So this is a way of enabling the module during testing. #[cfg(all( target_arch = "aarch64", - any(target_feature = "outline-atomics", feature = "mangled-names") + any( + target_feature = "outline-atomics", + feature = "unstable-public-internals" + ) ))] pub mod aarch64_outline_atomics; @@ -70,9 +76,6 @@ pub mod avr; #[cfg(target_arch = "hexagon")] pub mod hexagon; -#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] -pub mod riscv; - #[cfg(target_arch = "x86")] pub mod x86; diff --git a/compiler-builtins/compiler-builtins/src/macros.rs b/compiler-builtins/compiler-builtins/src/macros.rs index 203cd0949ac52..c5e49f7780641 100644 --- a/compiler-builtins/compiler-builtins/src/macros.rs +++ b/compiler-builtins/compiler-builtins/src/macros.rs @@ -254,7 +254,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(all(target_vendor = "apple", any(target_arch = "x86", target_arch = "x86_64"), not(feature = "mangled-names")))] + #[cfg(all(target_vendor = "apple", any(target_arch = "x86", target_arch = "x86_64"), feature = "unmangled-names"))] mod $name { #[unsafe(no_mangle)] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] @@ -290,7 +290,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(all(target_vendor = "apple", any(target_arch = "x86", target_arch = "x86_64"), not(feature = "mangled-names")))] + #[cfg(all(target_vendor = "apple", any(target_arch = "x86", target_arch = "x86_64"), feature = "unmangled-names"))] mod $name { #[unsafe(no_mangle)] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] @@ -331,7 +331,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(all(target_arch = "arm", not(feature = "mangled-names")))] + #[cfg(all(target_arch = "arm", feature = "unmangled-names"))] mod $name { #[unsafe(no_mangle)] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] @@ -341,7 +341,7 @@ macro_rules! intrinsics { } } - #[cfg(all(target_arch = "arm", not(feature = "mangled-names")))] + #[cfg(all(target_arch = "arm", feature = "unmangled-names"))] mod $alias { #[unsafe(no_mangle)] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] @@ -392,7 +392,7 @@ macro_rules! intrinsics { intrinsics!($($rest)*); ); - // C mem* functions are only generated when the "mem" feature is enabled. + // C mem* functions are only exposed via `no_mangle` when the "mem" feature is enabled. ( #[mem_builtin] $(#[$($attr:tt)*])* @@ -407,7 +407,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(all(feature = "mem", not(feature = "mangled-names")))] + #[cfg(all(feature = "mem", feature = "unmangled-names"))] mod $name { $(#[$($attr)*])* #[unsafe(no_mangle)] @@ -435,7 +435,7 @@ macro_rules! intrinsics { pub mod $name { #[unsafe(naked)] $(#[$($attr)*])* - #[cfg_attr(not(feature = "mangled-names"), unsafe(no_mangle))] + #[cfg_attr(feature = "unmangled-names", unsafe(no_mangle))] #[cfg_attr(not(any(all(windows, target_env = "gnu"), target_os = "cygwin")), linkage = "weak")] pub unsafe extern $abi fn $name( $($argname: $ty),* ) $(-> $ret)? { $($body)* @@ -470,7 +470,7 @@ macro_rules! intrinsics { $($body)* } - #[cfg(not(feature = "mangled-names"))] + #[cfg(feature = "unmangled-names")] mod $name { $(#[$($attr)*])* #[unsafe(no_mangle)] diff --git a/compiler-builtins/compiler-builtins/src/math/mod.rs b/compiler-builtins/compiler-builtins/src/math/mod.rs index 61dfad213cbe3..3dfa3863bb770 100644 --- a/compiler-builtins/compiler-builtins/src/math/mod.rs +++ b/compiler-builtins/compiler-builtins/src/math/mod.rs @@ -144,8 +144,12 @@ pub mod partial_availability { libm_intrinsics! { fn acos(x: f64) -> f64; fn acosf(n: f32) -> f32; + fn acosh(x: f64) -> f64; + fn acoshf(x: f32) -> f32; fn asin(x: f64) -> f64; fn asinf(n: f32) -> f32; + fn asinh(x: f64) -> f64; + fn asinhf(x: f32) -> f32; fn atan(x: f64) -> f64; fn atan2(x: f64, y: f64) -> f64; fn atan2f(a: f32, b: f32) -> f32; diff --git a/compiler-builtins/compiler-builtins/src/mem/impls.rs b/compiler-builtins/compiler-builtins/src/mem/impls.rs index 9681f5d6dac6e..c7cfa6fb4618e 100644 --- a/compiler-builtins/compiler-builtins/src/mem/impls.rs +++ b/compiler-builtins/compiler-builtins/src/mem/impls.rs @@ -9,7 +9,7 @@ // ptr::add in these loops will wrap. And if compiler-builtins is compiled with cfg(ub_checks), // this will fail a UB check at runtime. // -// Since this scenario is UB, we are within our rights hit this check and halt execution... +// Since this scenario is UB, we are within our rights to hit this check and halt execution... // But we are also within our rights to try to make it work. // We use wrapping_add/wrapping_sub for pointer arithmetic in this module in an attempt to support // this use. Of course this is not a guarantee that such use will work, it just means that this @@ -35,7 +35,7 @@ const WORD_COPY_THRESHOLD: usize = if 2 * WORD_SIZE > 16 { 16 }; -#[cfg(feature = "mem-unaligned")] +#[cfg(mem_unaligned)] unsafe fn read_usize_unaligned(x: *const usize) -> usize { // Do not use `core::ptr::read_unaligned` here, since it calls `copy_nonoverlapping` which // is translated to memcpy in LLVM. @@ -46,7 +46,7 @@ unsafe fn read_usize_unaligned(x: *const usize) -> usize { /// Loads a `T`-sized chunk from `src` into `dst` at offset `offset`, if that does not exceed /// `load_sz`. The offset pointers must both be `T`-aligned. Returns the new offset, advanced by the /// chunk size if a load happened. -#[cfg(not(feature = "mem-unaligned"))] +#[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn load_chunk_aligned( src: *const usize, @@ -66,7 +66,7 @@ unsafe fn load_chunk_aligned( /// Load `load_sz` many bytes from `src`, which must be usize-aligned. Acts as if we did a `usize` /// read with the out-of-bounds part filled with 0s. /// `load_sz` be strictly less than `WORD_SIZE`. -#[cfg(not(feature = "mem-unaligned"))] +#[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn load_aligned_partial(src: *const usize, load_sz: usize) -> usize { debug_assert!(load_sz < WORD_SIZE); @@ -88,7 +88,7 @@ unsafe fn load_aligned_partial(src: *const usize, load_sz: usize) -> usize { /// `usize`-aligned. The bytes are returned as the *last* bytes of the return value, i.e., this acts /// as if we had done a `usize` read from `src`, with the out-of-bounds part filled with 0s. /// `load_sz` be strictly less than `WORD_SIZE`. -#[cfg(not(feature = "mem-unaligned"))] +#[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn load_aligned_end_partial(src: *const usize, load_sz: usize) -> usize { debug_assert!(load_sz < WORD_SIZE); @@ -136,7 +136,7 @@ pub unsafe fn copy_forward(mut dest: *mut u8, mut src: *const u8, mut n: usize) /// `n` is in units of bytes, but must be a multiple of the word size and must not be 0. /// `src` *must not* be `usize`-aligned. - #[cfg(not(feature = "mem-unaligned"))] + #[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn copy_forward_misaligned_words(dest: *mut u8, src: *const u8, n: usize) { debug_assert!(n > 0 && n % WORD_SIZE == 0); @@ -185,7 +185,7 @@ pub unsafe fn copy_forward(mut dest: *mut u8, mut src: *const u8, mut n: usize) /// `n` is in units of bytes, but must be a multiple of the word size and must not be 0. /// `src` *must not* be `usize`-aligned. - #[cfg(feature = "mem-unaligned")] + #[cfg(mem_unaligned)] #[inline(always)] unsafe fn copy_forward_misaligned_words(dest: *mut u8, src: *const u8, n: usize) { let mut dest_usize = dest as *mut usize; @@ -252,7 +252,7 @@ pub unsafe fn copy_backward(dest: *mut u8, src: *const u8, mut n: usize) { /// `n` is in units of bytes, but must be a multiple of the word size and must not be 0. /// `src` *must not* be `usize`-aligned. - #[cfg(not(feature = "mem-unaligned"))] + #[cfg(not(mem_unaligned))] #[inline(always)] unsafe fn copy_backward_misaligned_words(dest: *mut u8, src: *const u8, n: usize) { debug_assert!(n > 0 && n % WORD_SIZE == 0); @@ -301,7 +301,7 @@ pub unsafe fn copy_backward(dest: *mut u8, src: *const u8, mut n: usize) { /// `n` is in units of bytes, but must be a multiple of the word size and must not be 0. /// `src` *must not* be `usize`-aligned. - #[cfg(feature = "mem-unaligned")] + #[cfg(mem_unaligned)] #[inline(always)] unsafe fn copy_backward_misaligned_words(dest: *mut u8, src: *const u8, n: usize) { let mut dest_usize = dest as *mut usize; diff --git a/compiler-builtins/compiler-builtins/src/mem/mod.rs b/compiler-builtins/compiler-builtins/src/mem/mod.rs index a227f60a2949b..ac41cd33416f6 100644 --- a/compiler-builtins/compiler-builtins/src/mem/mod.rs +++ b/compiler-builtins/compiler-builtins/src/mem/mod.rs @@ -4,10 +4,7 @@ #![allow(unsafe_op_in_unsafe_fn)] // memcpy/memmove/memset have optimized implementations on some architectures -#[cfg_attr( - all(not(feature = "no-asm"), target_arch = "x86_64"), - path = "x86_64.rs" -)] +#[cfg_attr(all(feature = "arch", target_arch = "x86_64"), path = "x86_64.rs")] mod impls; intrinsics! { diff --git a/compiler-builtins/compiler-builtins/src/mem/x86_64.rs b/compiler-builtins/compiler-builtins/src/mem/x86_64.rs index bf36a286ac951..3b32f71cd138a 100644 --- a/compiler-builtins/compiler-builtins/src/mem/x86_64.rs +++ b/compiler-builtins/compiler-builtins/src/mem/x86_64.rs @@ -168,7 +168,7 @@ pub unsafe fn compare_bytes(a: *const u8, b: *const u8, n: usize) -> i32 { c16(a.cast(), b.cast(), n) } -// In order to process more than on byte simultaneously when executing strlen, +// In order to process more than one byte simultaneously when executing strlen, // two things must be considered: // * An n byte read with an n-byte aligned address will never cross // a page boundary and will always succeed. Any smaller alignment @@ -198,8 +198,8 @@ pub unsafe fn c_string_length(mut s: *const core::ffi::c_char) -> usize { s = s.add(1); } - // Shave of the least significand bits to align the address to a 16 - // byte boundary. The shaved of bits are used to correct the first iteration. + // Shave off the least significant bits to align the address to a 16 + // byte boundary. The shaved off bits are used to correct the first iteration. let align = s as usize & 15; let mut s = ((s as usize) - align) as *const __m128i; diff --git a/compiler-builtins/compiler-builtins/src/probestack.rs b/compiler-builtins/compiler-builtins/src/probestack.rs index 1cab64ea113c5..c4a2eeb0e0178 100644 --- a/compiler-builtins/compiler-builtins/src/probestack.rs +++ b/compiler-builtins/compiler-builtins/src/probestack.rs @@ -41,7 +41,7 @@ //! probes on any other architecture like ARM or PowerPC64. LLVM I'm sure would //! be more than welcome to accept such a change! -#![cfg(not(feature = "mangled-names"))] +#![cfg(feature = "unmangled-names")] // Windows and Cygwin already has builtins to do this. #![cfg(not(any(windows, target_os = "cygwin")))] // We only define stack probing for these architectures today. diff --git a/compiler-builtins/compiler-builtins/src/riscv.rs b/compiler-builtins/compiler-builtins/src/riscv.rs deleted file mode 100644 index bf31255334193..0000000000000 --- a/compiler-builtins/compiler-builtins/src/riscv.rs +++ /dev/null @@ -1,50 +0,0 @@ -intrinsics! { - // Ancient Egyptian/Ethiopian/Russian multiplication method - // see https://en.wikipedia.org/wiki/Ancient_Egyptian_multiplication - // - // This is a long-available stock algorithm; e.g. it is documented in - // Knuth's "The Art of Computer Programming" volume 2 (under the section - // "Evaluation of Powers") since at least the 2nd edition (1981). - // - // The main attraction of this method is that it implements (software) - // multiplication atop four simple operations: doubling, halving, checking - // if a value is even/odd, and addition. This is *not* considered to be the - // fastest multiplication method, but it may be amongst the simplest (and - // smallest with respect to code size). - // - // for reference, see also implementation from gcc - // https://raw.githubusercontent.com/gcc-mirror/gcc/master/libgcc/config/epiphany/mulsi3.c - // - // and from LLVM (in relatively readable RISC-V assembly): - // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/riscv/int_mul_impl.inc - pub extern "C" fn __mulsi3(a: u32, b: u32) -> u32 { - let (mut a, mut b) = (a, b); - let mut r: u32 = 0; - - while a > 0 { - if a & 1 > 0 { - r = r.wrapping_add(b); - } - a >>= 1; - b <<= 1; - } - - r - } - - #[cfg(not(target_feature = "m"))] - pub extern "C" fn __muldi3(a: u64, b: u64) -> u64 { - let (mut a, mut b) = (a, b); - let mut r: u64 = 0; - - while a > 0 { - if a & 1 > 0 { - r = r.wrapping_add(b); - } - a >>= 1; - b <<= 1; - } - - r - } -} diff --git a/compiler-builtins/crates/api-list-common/Cargo.toml b/compiler-builtins/crates/api-list-common/Cargo.toml new file mode 100644 index 0000000000000..bf9262eb828ff --- /dev/null +++ b/compiler-builtins/crates/api-list-common/Cargo.toml @@ -0,0 +1,6 @@ +[package] +name = "api-list-common" +version = "0.1.0" +edition = "2024" +publish = false +license = "MIT OR Apache-2.0" diff --git a/compiler-builtins/crates/api-list-common/src/lib.rs b/compiler-builtins/crates/api-list-common/src/lib.rs new file mode 100644 index 0000000000000..f6e5516a76fa6 --- /dev/null +++ b/compiler-builtins/crates/api-list-common/src/lib.rs @@ -0,0 +1,1567 @@ +//! A list of API we have available, shared among various test crates. + +use std::fmt; +use std::sync::LazyLock; + +/// Convenient structure for defining items, gets expanded into a flat structure. +struct NestedOp { + rust_sig: Signature, + c_sig: Option, + fn_list: &'static [&'static str], + scope: OpScope, +} + +/// Indicate where a function is defined and whether it is public or private. +#[derive(Clone, Copy, Debug)] +pub enum OpScope { + /// Part of `libm`'s public API. + LibmPublic, + /// Functions internal to `libm`, e.g. `rem_pio2`. + LibmPrivate, + /// Functions part of the public API for `compiler-builtins`. + BuiltinsPublic, +} + +impl OpScope { + /// Where we should look for functions of this scope. + pub const fn path_root(self) -> &'static str { + match self { + OpScope::LibmPublic => "libm", + OpScope::LibmPrivate => todo!(), + OpScope::BuiltinsPublic => "crate::builtins_wrapper", + } + } + + pub fn defined_in_compiler_builtins(self) -> bool { + match self { + OpScope::LibmPublic | OpScope::LibmPrivate => false, + OpScope::BuiltinsPublic => true, + } + } +} + +/// We need a flat list to work with most of the time, but define things as a more convenient +/// nested list. +const ALL_OPERATIONS_NESTED: &[NestedOp] = &[ + /******************************** + * compiler-builtins operations * + ********************************/ + NestedOp { + rust_sig: Signature { + args: &[Ty::F16, Ty::F16], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["addf16", "mulf16", "subf16"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32, Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["addf32", "divf32", "mulf32", "subf32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64, Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["addf64", "divf64", "mulf64", "subf64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128, Ty::F128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["addf128", "divf128", "mulf128", "subf128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32, Ty::I32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["powif32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64, Ty::I32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["powif64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128, Ty::I32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["powif128"], + scope: OpScope::BuiltinsPublic, + }, + /* Comparison */ + NestedOp { + rust_sig: Signature { + args: &[Ty::F16, Ty::F16], + returns: &[Ty::Bool], + }, + c_sig: None, + fn_list: &[ + "eqf16", "gef16", "gtf16", "lef16", "ltf16", "nef16", "unordf16", + ], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32, Ty::F32], + returns: &[Ty::Bool], + }, + c_sig: None, + fn_list: &[ + "eqf32", "gef32", "gtf32", "lef32", "ltf32", "nef32", "unordf32", + ], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64, Ty::F64], + returns: &[Ty::Bool], + }, + c_sig: None, + fn_list: &[ + "eqf64", "gef64", "gtf64", "lef64", "ltf64", "nef64", "unordf64", + ], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128, Ty::F128], + returns: &[Ty::Bool], + }, + c_sig: None, + fn_list: &[ + "eqf128", + "gef128", + "gtf128", + "lef128", + "ltf128", + "nef128", + "unordf128", + ], + scope: OpScope::BuiltinsPublic, + }, + /* conversion */ + NestedOp { + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["extend_f16_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["extend_f16_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["extend_f16_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["extend_f32_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["extend_f32_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["extend_f64_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["narrow_f32_f16"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["narrow_f64_f16"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["narrow_f128_f16"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["narrow_f64_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["narrow_f128_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["narrow_f128_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ftoi_f32_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["ftoi_f32_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &["ftoi_f32_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ftoi_f64_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["ftoi_f64_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &["ftoi_f64_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ftoi_f128_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["ftoi_f128_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &["ftoi_f128_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["ftoi_f32_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["ftoi_f32_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["ftoi_f32_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["ftoi_f64_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["ftoi_f64_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["ftoi_f64_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["ftoi_f128_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["ftoi_f128_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["ftoi_f128_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_i32_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_i64_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_i128_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_i32_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_i64_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_i128_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_i32_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_i64_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_i128_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_u32_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_u64_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["itof_u128_f32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_u32_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_u64_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["itof_u128_f64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_u32_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_u64_f128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["itof_u128_f128"], + scope: OpScope::BuiltinsPublic, + }, + /* int arithmetic */ + NestedOp { + rust_sig: Signature { + args: &[Ty::I32, Ty::I32], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["idiv_i32", "imod_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32, Ty::I32], + returns: &[Ty::I32, Ty::I32], + }, + c_sig: None, + fn_list: &["idivmod_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32, Ty::I32], + returns: &[Ty::I32, Ty::Bool], + }, + c_sig: None, + fn_list: &["imulo_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32, Ty::U32], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["idiv_u32", "imod_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32, Ty::U32], + returns: &[Ty::U32, Ty::U32], + }, + c_sig: None, + fn_list: &["idivmod_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64, Ty::I64], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["idiv_i64", "imod_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64, Ty::I64], + returns: &[Ty::I64, Ty::I64], + }, + c_sig: None, + fn_list: &["idivmod_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64, Ty::U64], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["idiv_u64", "imod_u64", "imul_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64, Ty::U64], + returns: &[Ty::U64, Ty::U64], + }, + c_sig: None, + fn_list: &["idivmod_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64, Ty::I64], + returns: &[Ty::I64, Ty::Bool], + }, + c_sig: None, + fn_list: &["imulo_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128, Ty::I128], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &[ + "iadd_i128", + "idiv_i128", + "imod_i128", + "imul_i128", + "isub_i128", + ], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128, Ty::I128], + returns: &[Ty::I128, Ty::I128], + }, + c_sig: None, + fn_list: &["idivmod_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128, Ty::I128], + returns: &[Ty::I128, Ty::Bool], + }, + c_sig: None, + fn_list: &["iaddo_i128", "imulo_i128", "isubo_i128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128, Ty::U128], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["iadd_u128", "idiv_u128", "imod_u128", "isub_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128, Ty::U128], + returns: &[Ty::U128, Ty::U128], + }, + c_sig: None, + fn_list: &["idivmod_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128, Ty::U128], + returns: &[Ty::U128, Ty::Bool], + }, + c_sig: None, + fn_list: &["iaddo_u128", "imulo_u128", "isubo_u128"], + scope: OpScope::BuiltinsPublic, + }, + /* int shifts */ + NestedOp { + rust_sig: Signature { + args: &[Ty::U32, Ty::U32], + returns: &[Ty::U32], + }, + c_sig: None, + fn_list: &["ashl_u32", "lshr_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64, Ty::U32], + returns: &[Ty::U64], + }, + c_sig: None, + fn_list: &["ashl_u64", "lshr_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128, Ty::U32], + returns: &[Ty::U128], + }, + c_sig: None, + fn_list: &["ashl_u128", "lshr_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I32, Ty::U32], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ashr_i32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I64, Ty::U32], + returns: &[Ty::I64], + }, + c_sig: None, + fn_list: &["ashr_i64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::I128, Ty::U32], + returns: &[Ty::I128], + }, + c_sig: None, + fn_list: &["ashr_i128"], + scope: OpScope::BuiltinsPublic, + }, + /* int bitwise ops */ + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["leading_zeros_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["leading_zeros_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["leading_zeros_u128"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U32], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["trailing_zeros_u32"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U64], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["trailing_zeros_u64"], + scope: OpScope::BuiltinsPublic, + }, + NestedOp { + rust_sig: Signature { + args: &[Ty::U128], + returns: &[Ty::USize], + }, + c_sig: None, + fn_list: &["trailing_zeros_u128"], + scope: OpScope::BuiltinsPublic, + }, + /******************* + * libm operations * + *******************/ + NestedOp { + // `fn(f16) -> f16` + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &[ + "ceilf16", + "fabsf16", + "floorf16", + "rintf16", + "roundevenf16", + "roundf16", + "sqrtf16", + "truncf16", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `fn(f32) -> f32` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &[ + "acosf", + "acoshf", + "asinf", + "asinhf", + "atanf", + "atanhf", + "cbrtf", + "ceilf", + "cosf", + "coshf", + "erfcf", + "erff", + "exp10f", + "exp2f", + "expf", + "expm1f", + "fabsf", + "floorf", + "j0f", + "j1f", + "lgammaf", + "log10f", + "log1pf", + "log2f", + "logf", + "rintf", + "roundevenf", + "roundf", + "sinf", + "sinhf", + "sqrtf", + "tanf", + "tanhf", + "tgammaf", + "truncf", + "y0f", + "y1f", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64) -> f64` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &[ + "acos", + "acosh", + "asin", + "asinh", + "atan", + "atanh", + "cbrt", + "ceil", + "cos", + "cosh", + "erf", + "erfc", + "exp", + "exp10", + "exp2", + "expm1", + "fabs", + "floor", + "j0", + "j1", + "lgamma", + "log", + "log10", + "log1p", + "log2", + "rint", + "round", + "roundeven", + "sin", + "sinh", + "sqrt", + "tan", + "tanh", + "tgamma", + "trunc", + "y0", + "y1", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `fn(f128) -> f128` + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &[ + "ceilf128", + "fabsf128", + "floorf128", + "rintf128", + "roundevenf128", + "roundf128", + "sqrtf128", + "truncf128", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16, f16) -> f16` + rust_sig: Signature { + args: &[Ty::F16, Ty::F16], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &[ + "copysignf16", + "fdimf16", + "fmaxf16", + "fmaximum_numf16", + "fmaximumf16", + "fminf16", + "fminimum_numf16", + "fminimumf16", + "fmodf16", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, f32) -> f32` + rust_sig: Signature { + args: &[Ty::F32, Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &[ + "atan2f", + "copysignf", + "fdimf", + "fmaxf", + "fmaximum_numf", + "fmaximumf", + "fminf", + "fminimum_numf", + "fminimumf", + "fmodf", + "hypotf", + "nextafterf", + "powf", + "remainderf", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, f64) -> f64` + rust_sig: Signature { + args: &[Ty::F64, Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &[ + "atan2", + "copysign", + "fdim", + "fmax", + "fmaximum", + "fmaximum_num", + "fmin", + "fminimum", + "fminimum_num", + "fmod", + "hypot", + "nextafter", + "pow", + "remainder", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128, f128) -> f128` + rust_sig: Signature { + args: &[Ty::F128, Ty::F128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &[ + "copysignf128", + "fdimf128", + "fmaxf128", + "fmaximum_numf128", + "fmaximumf128", + "fminf128", + "fminimum_numf128", + "fminimumf128", + "fmodf128", + ], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16, f16, f16) -> f16` + rust_sig: Signature { + args: &[Ty::F16, Ty::F16, Ty::F16], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["fmaf16"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, f32, f32) -> f32` + rust_sig: Signature { + args: &[Ty::F32, Ty::F32, Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["fmaf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, f64, f64) -> f64` + rust_sig: Signature { + args: &[Ty::F64, Ty::F64, Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["fma"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128, f128, f128) -> f128` + rust_sig: Signature { + args: &[Ty::F128, Ty::F128, Ty::F128], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["fmaf128"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16) -> i32` + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogbf16"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32) -> i32` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogbf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64) -> i32` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogb"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128) -> i32` + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogbf128"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(i32, f32) -> f32` + rust_sig: Signature { + args: &[Ty::I32, Ty::F32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["jnf", "ynf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(i32, f64) -> f64` + rust_sig: Signature { + args: &[Ty::I32, Ty::F64], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["jn", "yn"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16, i32) -> f16` + rust_sig: Signature { + args: &[Ty::F16, Ty::I32], + returns: &[Ty::F16], + }, + c_sig: None, + fn_list: &["ldexpf16", "scalbnf16"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, i32) -> f32` + rust_sig: Signature { + args: &[Ty::F32, Ty::I32], + returns: &[Ty::F32], + }, + c_sig: None, + fn_list: &["ldexpf", "scalbnf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, i64) -> f64` + rust_sig: Signature { + args: &[Ty::F64, Ty::I32], + returns: &[Ty::F64], + }, + c_sig: None, + fn_list: &["ldexp", "scalbn"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128, i32) -> f128` + rust_sig: Signature { + args: &[Ty::F128, Ty::I32], + returns: &[Ty::F128], + }, + c_sig: None, + fn_list: &["ldexpf128", "scalbnf128"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, &mut f32) -> f32` as `(f32) -> (f32, f32)` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F32, Ty::F32], + }, + c_sig: Some(Signature { + args: &[Ty::F32, Ty::MutF32], + returns: &[Ty::F32], + }), + fn_list: &["modff"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, &mut f64) -> f64` as `(f64) -> (f64, f64)` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F64, Ty::F64], + }, + c_sig: Some(Signature { + args: &[Ty::F64, Ty::MutF64], + returns: &[Ty::F64], + }), + fn_list: &["modf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f16, &mut c_int) -> f16` as `(f16) -> (f16, i32)` + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F16, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F16, Ty::MutCInt], + returns: &[Ty::F16], + }), + fn_list: &["frexpf16"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, &mut c_int) -> f32` as `(f32) -> (f32, i32)` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F32, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F32, Ty::MutCInt], + returns: &[Ty::F32], + }), + fn_list: &["frexpf", "lgammaf_r"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, &mut c_int) -> f64` as `(f64) -> (f64, i32)` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F64, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F64, Ty::MutCInt], + returns: &[Ty::F64], + }), + fn_list: &["frexp", "lgamma_r"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f128, &mut c_int) -> f128` as `(f128) -> (f128, i32)` + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F128, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F128, Ty::MutCInt], + returns: &[Ty::F128], + }), + fn_list: &["frexpf128"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, f32, &mut c_int) -> f32` as `(f32, f32) -> (f32, i32)` + rust_sig: Signature { + args: &[Ty::F32, Ty::F32], + returns: &[Ty::F32, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F32, Ty::F32, Ty::MutCInt], + returns: &[Ty::F32], + }), + fn_list: &["remquof"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, f64, &mut c_int) -> f64` as `(f64, f64) -> (f64, i32)` + rust_sig: Signature { + args: &[Ty::F64, Ty::F64], + returns: &[Ty::F64, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F64, Ty::F64, Ty::MutCInt], + returns: &[Ty::F64], + }), + fn_list: &["remquo"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f32, &mut f32, &mut f32)` as `(f32) -> (f32, f32)` + rust_sig: Signature { + args: &[Ty::F32], + returns: &[Ty::F32, Ty::F32], + }, + c_sig: Some(Signature { + args: &[Ty::F32, Ty::MutF32, Ty::MutF32], + returns: &[], + }), + fn_list: &["sincosf"], + scope: OpScope::LibmPublic, + }, + NestedOp { + // `(f64, &mut f64, &mut f64)` as `(f64) -> (f64, f64)` + rust_sig: Signature { + args: &[Ty::F64], + returns: &[Ty::F64, Ty::F64], + }, + c_sig: Some(Signature { + args: &[Ty::F64, Ty::MutF64, Ty::MutF64], + returns: &[], + }), + fn_list: &["sincos"], + scope: OpScope::LibmPublic, + }, +]; + +/// A type used in a function signature. +#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] +pub enum Ty { + F16, + F32, + F64, + F128, + I32, + I64, + I128, + U32, + U64, + U128, + USize, + Bool, + CInt, + MutF16, + MutF32, + MutF64, + MutF128, + MutI32, + MutCInt, +} + +impl Ty { + /// The number of bits needed to represent this type's possible values. That is, + /// `log2(variant_count)`. + pub fn effective_bits(self) -> u32 { + match self { + Ty::Bool => 1, + Ty::F16 | Ty::MutF16 => 16, + Ty::F32 | Ty::I32 | Ty::U32 | Ty::MutF32 | Ty::MutI32 => 32, + Ty::F64 | Ty::I64 | Ty::U64 | Ty::MutF64 => 64, + Ty::F128 | Ty::I128 | Ty::U128 | Ty::MutF128 => 128, + Ty::USize => usize::BITS, + // Assume we're not testing on a 16-bit system + Ty::CInt | Ty::MutCInt => 32, + } + } + + /// How to group functions that mostly have this kind of input. + fn group(self) -> Group { + match self { + Ty::F16 | Ty::MutF16 => Group::F16, + Ty::F32 | Ty::MutF32 => Group::F32, + Ty::F64 | Ty::MutF64 => Group::F64, + Ty::F128 | Ty::MutF128 => Group::F128, + Ty::I32 + | Ty::I64 + | Ty::I128 + | Ty::U32 + | Ty::U64 + | Ty::U128 + | Ty::USize + | Ty::Bool + | Ty::CInt + | Ty::MutI32 + | Ty::MutCInt => Group::Integer, + } + } + + fn is_float(self) -> bool { + match self { + Ty::F16 + | Ty::F32 + | Ty::F64 + | Ty::F128 + | Ty::MutF16 + | Ty::MutF32 + | Ty::MutF64 + | Ty::MutF128 => true, + Ty::I32 + | Ty::I64 + | Ty::I128 + | Ty::U32 + | Ty::U64 + | Ty::U128 + | Ty::USize + | Ty::Bool + | Ty::CInt + | Ty::MutI32 + | Ty::MutCInt => false, + } + } +} + +/// How a function should get grouped for things like extensive tests. +#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] +pub enum Group { + F16, + F32, + F64, + F128, + Integer, +} + +impl fmt::Display for Ty { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let s = match self { + Ty::F16 => "f16", + Ty::F32 => "f32", + Ty::F64 => "f64", + Ty::F128 => "f128", + Ty::I32 => "i32", + Ty::I64 => "i64", + Ty::I128 => "i128", + Ty::U32 => "u32", + Ty::U64 => "u64", + Ty::U128 => "u128", + Ty::USize => "usize", + Ty::Bool => "bool", + Ty::CInt => "::core::ffi::c_int", + Ty::MutF16 => "&mut f16", + Ty::MutF32 => "&mut f32", + Ty::MutF64 => "&mut f64", + Ty::MutF128 => "&mut f128", + Ty::MutI32 => "&mut i32", + Ty::MutCInt => "&mut ::core::ffi::c_int", + }; + f.write_str(s) + } +} + +/// Representation of e.g. `(f32, f32) -> f32` +#[derive(Debug, Clone)] +pub struct Signature { + pub args: &'static [Ty], + pub returns: &'static [Ty], +} + +/// Combined information about a function implementation. +#[derive(Debug, Clone)] +pub struct MathOpInfo { + pub name: &'static str, + /// How this function should be grouped when needed. Based on the first float argument. + pub group: Group, + /// Function signature for C implementations + pub c_sig: Signature, + /// Function signature for Rust implementations + pub rust_sig: Signature, + /// Indicate what crate this function is defined in and whether it is public or private. + pub scope: OpScope, + /// The path to this function, including crate but excluding the function itself. + pub path: String, +} + +/// A flat representation of `ALL_FUNCTIONS`. +pub static ALL_OPERATIONS: LazyLock> = LazyLock::new(|| { + let mut ret = Vec::new(); + + for op in ALL_OPERATIONS_NESTED { + let fn_names = op.fn_list; + for name in fn_names { + // Locate the first float argument or return value, fall back to whatever the first + // argument is if there are no floats. + let group_ty = op + .rust_sig + .args + .iter() + .chain(op.rust_sig.returns.iter()) + .find(|arg| arg.is_float()) + .unwrap_or(&op.rust_sig.args[0]); + let group = group_ty.group(); + + let api = MathOpInfo { + name, + group, + rust_sig: op.rust_sig.clone(), + c_sig: op.c_sig.clone().unwrap_or_else(|| op.rust_sig.clone()), + scope: op.scope, + path: format!("{}::{name}", op.scope.path_root()), + }; + ret.push(api); + } + } + + ret.sort_by_key(|item| item.name); + ret +}); + +#[cfg(test)] +mod tests { + use std::collections::HashSet; + + pub use super::*; + + #[test] + fn sorted_fn_list() { + for op in ALL_OPERATIONS_NESTED { + if !op.fn_list.is_sorted() { + let mut sorted = (*op.fn_list).to_owned(); + sorted.sort_unstable(); + panic!( + "names list is not sorted: {:?}\nExpected: {sorted:?}", + op.fn_list + ); + } + } + } + + #[test] + fn no_duplicates_in_list() { + let mut names = HashSet::new(); + let mut paths = HashSet::new(); + for item in &*ALL_OPERATIONS { + let new_name = names.insert(item.name); + assert!(new_name, "duplicate name `{item:?}`"); + let new_path = paths.insert(&item.path); + assert!(new_path, "duplicate path`{item:?}`"); + } + } +} diff --git a/compiler-builtins/crates/libm-macros/Cargo.toml b/compiler-builtins/crates/libm-macros/Cargo.toml index f99a92e21c709..920cc32104943 100644 --- a/compiler-builtins/crates/libm-macros/Cargo.toml +++ b/compiler-builtins/crates/libm-macros/Cargo.toml @@ -9,6 +9,7 @@ license = "MIT OR Apache-2.0" proc-macro = true [dependencies] +api-list-common.workspace = true heck.workspace = true proc-macro2.workspace = true quote.workspace = true diff --git a/compiler-builtins/crates/libm-macros/src/enums.rs b/compiler-builtins/crates/libm-macros/src/enums.rs index b4646f984d471..f15bdaa63821a 100644 --- a/compiler-builtins/crates/libm-macros/src/enums.rs +++ b/compiler-builtins/crates/libm-macros/src/enums.rs @@ -93,11 +93,6 @@ pub fn function_enum( #( #base_arms, )* } } - - /// Return information about this operation. - pub fn math_op(self) -> &'static crate::op::MathOpInfo { - crate::op::ALL_OPERATIONS.iter().find(|op| op.name == self.as_str()).unwrap() - } } }; diff --git a/compiler-builtins/crates/libm-macros/src/lib.rs b/compiler-builtins/crates/libm-macros/src/lib.rs index 7efa1488f570e..7bafd0ce8e1d4 100644 --- a/compiler-builtins/crates/libm-macros/src/lib.rs +++ b/compiler-builtins/crates/libm-macros/src/lib.rs @@ -1,18 +1,17 @@ mod enums; mod parse; -mod shared; +use api_list_common::{ALL_OPERATIONS, Group, MathOpInfo, Ty}; use parse::{Invocation, StructuredInput}; use proc_macro as pm; use proc_macro2::{self as pm2, Span}; use quote::{ToTokens, quote}; -pub(crate) use shared::{ALL_OPERATIONS, FloatTy, MathOpInfo, Ty}; use syn::spanned::Spanned; use syn::visit_mut::VisitMut; -use syn::{Ident, ItemEnum}; +use syn::{Ident, ItemEnum, PathArguments, PathSegment}; const KNOWN_TYPES: &[&str] = &[ - "FTy", "CFn", "CArgs", "CRet", "RustFn", "RustArgs", "RustRet", "public", + "CFn", "CArgs", "CRet", "RustFn", "RustArgs", "RustRet", "path", ]; /// Populate an enum with a variant representing function. Names are in upper camel case. @@ -66,8 +65,6 @@ pub fn base_name_enum(attributes: pm::TokenStream, tokens: pm::TokenStream) -> p /// ( /// // Name of that function /// fn_name: $fn_name:ident, -/// // The basic float type for this function (e.g. `f32`, `f64`) -/// FTy: $FTy:ty, /// // Function signature of the C version (e.g. `fn(f32, &mut f32) -> f32`) /// CFn: $CFn:ty, /// // A tuple representing the C version's arguments (e.g. `(f32, &mut f32)`) @@ -80,8 +77,8 @@ pub fn base_name_enum(attributes: pm::TokenStream, tokens: pm::TokenStream) -> p /// RustArgs: $RustArgs:ty, /// // The Rust version's return type (e.g. `(f32, f32)`) /// RustRet: $RustRet:ty, -/// // True if this is part of `libm`'s public API -/// public: $public:expr, +/// // Path to the function, e.g. `libm::fma` or `crate::builtins_wrapper::addf32`. +/// path: $path:path, /// // Attributes for the current function, if any /// attrs: [$($attr:meta),*], /// // Extra tokens passed directly (if any) @@ -143,11 +140,12 @@ pub fn for_each_function(tokens: pm::TokenStream) -> pm::TokenStream { fn validate(input: &mut StructuredInput) -> syn::Result> { // Replace magic mappers with a list of relevant functions. if let Some(map) = &mut input.fn_extra { - for (name, ty) in [ - ("ALL_F16", FloatTy::F16), - ("ALL_F32", FloatTy::F32), - ("ALL_F64", FloatTy::F64), - ("ALL_F128", FloatTy::F128), + for (name, group) in [ + ("ALL_F16", Group::F16), + ("ALL_F32", Group::F32), + ("ALL_F64", Group::F64), + ("ALL_F128", Group::F128), + ("ALL_INT", Group::Integer), ] { let Some(k) = map.keys().find(|key| *key == name) else { continue; @@ -156,7 +154,19 @@ fn validate(input: &mut StructuredInput) -> syn::Result let key = k.clone(); let val = map.remove(&key).unwrap(); - for op in ALL_OPERATIONS.iter().filter(|op| op.float_ty == ty) { + for op in ALL_OPERATIONS.iter().filter(|op| op.group == group) { + map.insert(Ident::new(op.name, key.span()), val.clone()); + } + } + + if let Some(k) = map.keys().find(|key| *key == "ALL_BUILTINS") { + let key = k.clone(); + let val = map.remove(&key).unwrap(); + + for op in ALL_OPERATIONS + .iter() + .filter(|op| op.scope.defined_in_compiler_builtins()) + { map.insert(Ident::new(op.name, key.span()), val.clone()); } } @@ -220,8 +230,23 @@ fn validate(input: &mut StructuredInput) -> syn::Result } // Omit f16 and f128 functions if requested - if input.skip_f16_f128 && (func.float_ty == FloatTy::F16 || func.float_ty == FloatTy::F128) - { + if input.skip_f16_f128 { + if matches!(func.group, Group::F16 | Group::F128) { + continue; + } + + if func + .rust_sig + .args + .iter() + .chain(func.rust_sig.returns.iter()) + .any(|ty| matches!(ty, Ty::F16 | Ty::F128)) + { + continue; + } + } + + if input.skip_builtins && func.scope.defined_in_compiler_builtins() { continue; } @@ -356,25 +381,33 @@ fn expand(input: StructuredInput, fn_list: &[&MathOpInfo]) -> syn::Result pm2::TokenStream::new(), }; - let base_fty = func.float_ty; - let c_args = &func.c_sig.args; - let c_ret = &func.c_sig.returns; - let rust_args = &func.rust_sig.args; - let rust_ret = &func.rust_sig.returns; - let public = func.public; + let path = syn::Path { + leading_colon: None, + segments: func + .path + .split("::") + .map(|pseg| PathSegment { + ident: Ident::new(pseg, Span::call_site()), + arguments: PathArguments::None, + }) + .collect(), + }; let mut ty_fields = Vec::new(); for ty in &input.emit_types { + let c_args = func.c_sig.args.iter().copied().map(ty_to_tokens); + let c_ret = func.c_sig.returns.iter().copied().map(ty_to_tokens); + let rust_args = func.rust_sig.args.iter().copied().map(ty_to_tokens); + let rust_ret = func.rust_sig.returns.iter().copied().map(ty_to_tokens); let field = match ty.to_string().as_str() { - "FTy" => quote! { FTy: #base_fty, }, "CFn" => quote! { CFn: fn( #(#c_args),* ,) -> ( #(#c_ret),* ), }, "CArgs" => quote! { CArgs: ( #(#c_args),* ,), }, "CRet" => quote! { CRet: ( #(#c_ret),* ), }, "RustFn" => quote! { RustFn: fn( #(#rust_args),* ,) -> ( #(#rust_ret),* ), }, "RustArgs" => quote! { RustArgs: ( #(#rust_args),* ,), }, "RustRet" => quote! { RustRet: ( #(#rust_ret),* ), }, - "public" => quote! { public: #public, }, - _ => unreachable!("checked in validation"), + "path" => quote! { path: #path, }, + _ => unreachable!("fields should be checked in validation"), }; ty_fields.push(field); } @@ -450,7 +483,7 @@ impl VisitMut for MacroReplace { /// Return the unsuffixed version of a function name; e.g. `abs` and `absf` both return `abs`, /// `lgamma_r` and `lgammaf_r` both return `lgamma_r`. fn base_name(name: &str) -> &str { - let known_mappings = &[ + let known_mappings = [ ("erff", "erf"), ("erf", "erf"), ("lgammaf_r", "lgamma_r"), @@ -458,45 +491,55 @@ fn base_name(name: &str) -> &str { ("modf", "modf"), ]; - match known_mappings.iter().find(|known| known.0 == name) { - Some(found) => found.1, - None => name - .strip_suffix("f") - .or_else(|| name.strip_suffix("f16")) - .or_else(|| name.strip_suffix("f128")) - .unwrap_or(name), + if let Some(found) = known_mappings.iter().find(|known| known.0 == name) { + return found.1; } -} -impl ToTokens for Ty { - fn to_tokens(&self, tokens: &mut pm2::TokenStream) { - let ts = match self { - Ty::F16 => quote! { f16 }, - Ty::F32 => quote! { f32 }, - Ty::F64 => quote! { f64 }, - Ty::F128 => quote! { f128 }, - Ty::I32 => quote! { i32 }, - Ty::CInt => quote! { ::core::ffi::c_int }, - Ty::MutF16 => quote! { &'a mut f16 }, - Ty::MutF32 => quote! { &'a mut f32 }, - Ty::MutF64 => quote! { &'a mut f64 }, - Ty::MutF128 => quote! { &'a mut f128 }, - Ty::MutI32 => quote! { &'a mut i32 }, - Ty::MutCInt => quote! { &'a mut core::ffi::c_int }, - }; + // Attempt to strip unambiguous suffixes first. This is repeated so e.g. + // `extend_f32_f64` turns into `extend`. + let strip = [ + "_f16", "_f32", "_f64", "_f128", "_i32", "_i64", "_i128", "_u32", "_u64", "_u128", "f16", + "f32", "f64", "f128", + ]; - tokens.extend(ts); + let mut any_found = false; + let mut ret = name; + + for sfx in strip { + if let Some(stripped) = ret.strip_suffix(sfx) { + ret = stripped; + any_found = true; + } + } + + // Only if no suffix was stripped, try stripping the C-style float suffix. + if !any_found && let Some(stripped) = ret.strip_suffix("f") { + ret = stripped; } + + ret } -impl ToTokens for FloatTy { - fn to_tokens(&self, tokens: &mut pm2::TokenStream) { - let ts = match self { - FloatTy::F16 => quote! { f16 }, - FloatTy::F32 => quote! { f32 }, - FloatTy::F64 => quote! { f64 }, - FloatTy::F128 => quote! { f128 }, - }; - tokens.extend(ts); +fn ty_to_tokens(ty: Ty) -> pm2::TokenStream { + match ty { + Ty::F16 => quote! { f16 }, + Ty::F32 => quote! { f32 }, + Ty::F64 => quote! { f64 }, + Ty::F128 => quote! { f128 }, + Ty::I32 => quote! { i32 }, + Ty::I64 => quote! { i64 }, + Ty::I128 => quote! { i128 }, + Ty::U32 => quote! { u32 }, + Ty::U64 => quote! { u64 }, + Ty::U128 => quote! { u128 }, + Ty::USize => quote! { usize }, + Ty::Bool => quote! { bool }, + Ty::CInt => quote! { ::core::ffi::c_int }, + Ty::MutF16 => quote! { &'a mut f16 }, + Ty::MutF32 => quote! { &'a mut f32 }, + Ty::MutF64 => quote! { &'a mut f64 }, + Ty::MutF128 => quote! { &'a mut f128 }, + Ty::MutI32 => quote! { &'a mut i32 }, + Ty::MutCInt => quote! { &'a mut core::ffi::c_int }, } } diff --git a/compiler-builtins/crates/libm-macros/src/parse.rs b/compiler-builtins/crates/libm-macros/src/parse.rs index 4876f3ef7263a..97067b876bda6 100644 --- a/compiler-builtins/crates/libm-macros/src/parse.rs +++ b/compiler-builtins/crates/libm-macros/src/parse.rs @@ -50,9 +50,13 @@ pub struct StructuredInput { pub emit_types: Vec, /// Skip these functions pub skip: Vec, - /// If true, omit f16 and f128 functions that aren't present in other libraries. + /// If true, omit f16 and f128 functions that may not be present in libraries we test + /// against (e.g. musl). pub skip_f16_f128: bool, - /// Invoke only for these functions + /// If true, omit functions that are defined in `compiler-builtins` and are not present + /// in libraries we test against (e.g. musl). + pub skip_builtins: bool, + /// Invoke only for the functions listed here. pub only: Option>, /// Attributes that get applied to specific functions pub attributes: Option>, @@ -73,6 +77,7 @@ impl StructuredInput { let emit_types_expr = expect_field(&mut map, "emit_types").ok(); let skip_expr = expect_field(&mut map, "skip").ok(); let skip_f16_f128 = expect_field(&mut map, "skip_f16_f128").ok(); + let skip_builtins = expect_field(&mut map, "skip_builtins").ok(); let only_expr = expect_field(&mut map, "only").ok(); let attr_expr = expect_field(&mut map, "attributes").ok(); let extra = expect_field(&mut map, "extra").ok(); @@ -101,6 +106,11 @@ impl StructuredInput { None => false, }; + let skip_builtins = match skip_builtins { + Some(expr) => expect_litbool(expr)?.value, + None => false, + }; + let only_span = only_expr.as_ref().map(|expr| expr.span()); let only = match only_expr { Some(expr) => Some(Parser::parse2(parse_ident_array, expr.into_token_stream())?), @@ -131,6 +141,7 @@ impl StructuredInput { emit_types, skip, skip_f16_f128, + skip_builtins, only, only_span, attributes, diff --git a/compiler-builtins/crates/libm-macros/src/shared.rs b/compiler-builtins/crates/libm-macros/src/shared.rs deleted file mode 100644 index ee1feed7c35eb..0000000000000 --- a/compiler-builtins/crates/libm-macros/src/shared.rs +++ /dev/null @@ -1,640 +0,0 @@ -/* List of all functions that is shared between `libm-macros` and `libm-test`. */ - -use std::fmt; -use std::sync::LazyLock; - -struct NestedOp { - float_ty: FloatTy, - rust_sig: Signature, - c_sig: Option, - fn_list: &'static [&'static str], - public: bool, -} - -/// We need a flat list to work with most of the time, but define things as a more convenient -/// nested list. -const ALL_OPERATIONS_NESTED: &[NestedOp] = &[ - NestedOp { - // `fn(f16) -> f16` - float_ty: FloatTy::F16, - rust_sig: Signature { - args: &[Ty::F16], - returns: &[Ty::F16], - }, - c_sig: None, - fn_list: &[ - "ceilf16", - "fabsf16", - "floorf16", - "rintf16", - "roundevenf16", - "roundf16", - "sqrtf16", - "truncf16", - ], - public: true, - }, - NestedOp { - // `fn(f32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &[ - "acosf", - "acoshf", - "asinf", - "asinhf", - "atanf", - "atanhf", - "cbrtf", - "ceilf", - "cosf", - "coshf", - "erfcf", - "erff", - "exp10f", - "exp2f", - "expf", - "expm1f", - "fabsf", - "floorf", - "j0f", - "j1f", - "lgammaf", - "log10f", - "log1pf", - "log2f", - "logf", - "rintf", - "roundevenf", - "roundf", - "sinf", - "sinhf", - "sqrtf", - "tanf", - "tanhf", - "tgammaf", - "truncf", - "y0f", - "y1f", - ], - public: true, - }, - NestedOp { - // `(f64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &[ - "acos", - "acosh", - "asin", - "asinh", - "atan", - "atanh", - "cbrt", - "ceil", - "cos", - "cosh", - "erf", - "erfc", - "exp", - "exp10", - "exp2", - "expm1", - "fabs", - "floor", - "j0", - "j1", - "lgamma", - "log", - "log10", - "log1p", - "log2", - "rint", - "round", - "roundeven", - "sin", - "sinh", - "sqrt", - "tan", - "tanh", - "tgamma", - "trunc", - "y0", - "y1", - ], - public: true, - }, - NestedOp { - // `fn(f128) -> f128` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128], - returns: &[Ty::F128], - }, - c_sig: None, - fn_list: &[ - "ceilf128", - "fabsf128", - "floorf128", - "rintf128", - "roundevenf128", - "roundf128", - "sqrtf128", - "truncf128", - ], - public: true, - }, - NestedOp { - // `(f16, f16) -> f16` - float_ty: FloatTy::F16, - rust_sig: Signature { - args: &[Ty::F16, Ty::F16], - returns: &[Ty::F16], - }, - c_sig: None, - fn_list: &[ - "copysignf16", - "fdimf16", - "fmaxf16", - "fmaximum_numf16", - "fmaximumf16", - "fminf16", - "fminimum_numf16", - "fminimumf16", - "fmodf16", - ], - public: true, - }, - NestedOp { - // `(f32, f32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32, Ty::F32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &[ - "atan2f", - "copysignf", - "fdimf", - "fmaxf", - "fmaximum_numf", - "fmaximumf", - "fminf", - "fminimum_numf", - "fminimumf", - "fmodf", - "hypotf", - "nextafterf", - "powf", - "remainderf", - ], - public: true, - }, - NestedOp { - // `(f64, f64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64, Ty::F64], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &[ - "atan2", - "copysign", - "fdim", - "fmax", - "fmaximum", - "fmaximum_num", - "fmin", - "fminimum", - "fminimum_num", - "fmod", - "hypot", - "nextafter", - "pow", - "remainder", - ], - public: true, - }, - NestedOp { - // `(f128, f128) -> f128` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128, Ty::F128], - returns: &[Ty::F128], - }, - c_sig: None, - fn_list: &[ - "copysignf128", - "fdimf128", - "fmaxf128", - "fmaximum_numf128", - "fmaximumf128", - "fminf128", - "fminimum_numf128", - "fminimumf128", - "fmodf128", - ], - public: true, - }, - NestedOp { - // `(f32, f32, f32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32, Ty::F32, Ty::F32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &["fmaf"], - public: true, - }, - NestedOp { - // `(f64, f64, f64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64, Ty::F64, Ty::F64], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &["fma"], - public: true, - }, - NestedOp { - // `(f128, f128, f128) -> f128` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128, Ty::F128, Ty::F128], - returns: &[Ty::F128], - }, - c_sig: None, - fn_list: &["fmaf128"], - public: true, - }, - NestedOp { - // `(f16) -> i32` - float_ty: FloatTy::F16, - rust_sig: Signature { - args: &[Ty::F16], - returns: &[Ty::I32], - }, - c_sig: None, - fn_list: &["ilogbf16"], - public: true, - }, - NestedOp { - // `(f32) -> i32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::I32], - }, - c_sig: None, - fn_list: &["ilogbf"], - public: true, - }, - NestedOp { - // `(f64) -> i32` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::I32], - }, - c_sig: None, - fn_list: &["ilogb"], - public: true, - }, - NestedOp { - // `(f128) -> i32` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128], - returns: &[Ty::I32], - }, - c_sig: None, - fn_list: &["ilogbf128"], - public: true, - }, - NestedOp { - // `(i32, f32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::I32, Ty::F32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &["jnf", "ynf"], - public: true, - }, - NestedOp { - // `(i32, f64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::I32, Ty::F64], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &["jn", "yn"], - public: true, - }, - NestedOp { - // `(f16, i32) -> f16` - float_ty: FloatTy::F16, - rust_sig: Signature { - args: &[Ty::F16, Ty::I32], - returns: &[Ty::F16], - }, - c_sig: None, - fn_list: &["ldexpf16", "scalbnf16"], - public: true, - }, - NestedOp { - // `(f32, i32) -> f32` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32, Ty::I32], - returns: &[Ty::F32], - }, - c_sig: None, - fn_list: &["ldexpf", "scalbnf"], - public: true, - }, - NestedOp { - // `(f64, i64) -> f64` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64, Ty::I32], - returns: &[Ty::F64], - }, - c_sig: None, - fn_list: &["ldexp", "scalbn"], - public: true, - }, - NestedOp { - // `(f128, i32) -> f128` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128, Ty::I32], - returns: &[Ty::F128], - }, - c_sig: None, - fn_list: &["ldexpf128", "scalbnf128"], - public: true, - }, - NestedOp { - // `(f32, &mut f32) -> f32` as `(f32) -> (f32, f32)` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::F32, Ty::F32], - }, - c_sig: Some(Signature { - args: &[Ty::F32, Ty::MutF32], - returns: &[Ty::F32], - }), - fn_list: &["modff"], - public: true, - }, - NestedOp { - // `(f64, &mut f64) -> f64` as `(f64) -> (f64, f64)` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::F64, Ty::F64], - }, - c_sig: Some(Signature { - args: &[Ty::F64, Ty::MutF64], - returns: &[Ty::F64], - }), - fn_list: &["modf"], - public: true, - }, - NestedOp { - // `(f16, &mut c_int) -> f16` as `(f16) -> (f16, i32)` - float_ty: FloatTy::F16, - rust_sig: Signature { - args: &[Ty::F16], - returns: &[Ty::F16, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F16, Ty::MutCInt], - returns: &[Ty::F16], - }), - fn_list: &["frexpf16"], - public: true, - }, - NestedOp { - // `(f32, &mut c_int) -> f32` as `(f32) -> (f32, i32)` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::F32, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F32, Ty::MutCInt], - returns: &[Ty::F32], - }), - fn_list: &["frexpf", "lgammaf_r"], - public: true, - }, - NestedOp { - // `(f64, &mut c_int) -> f64` as `(f64) -> (f64, i32)` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::F64, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F64, Ty::MutCInt], - returns: &[Ty::F64], - }), - fn_list: &["frexp", "lgamma_r"], - public: true, - }, - NestedOp { - // `(f128, &mut c_int) -> f128` as `(f128) -> (f128, i32)` - float_ty: FloatTy::F128, - rust_sig: Signature { - args: &[Ty::F128], - returns: &[Ty::F128, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F128, Ty::MutCInt], - returns: &[Ty::F128], - }), - fn_list: &["frexpf128"], - public: true, - }, - NestedOp { - // `(f32, f32, &mut c_int) -> f32` as `(f32, f32) -> (f32, i32)` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32, Ty::F32], - returns: &[Ty::F32, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F32, Ty::F32, Ty::MutCInt], - returns: &[Ty::F32], - }), - fn_list: &["remquof"], - public: true, - }, - NestedOp { - // `(f64, f64, &mut c_int) -> f64` as `(f64, f64) -> (f64, i32)` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64, Ty::F64], - returns: &[Ty::F64, Ty::I32], - }, - c_sig: Some(Signature { - args: &[Ty::F64, Ty::F64, Ty::MutCInt], - returns: &[Ty::F64], - }), - fn_list: &["remquo"], - public: true, - }, - NestedOp { - // `(f32, &mut f32, &mut f32)` as `(f32) -> (f32, f32)` - float_ty: FloatTy::F32, - rust_sig: Signature { - args: &[Ty::F32], - returns: &[Ty::F32, Ty::F32], - }, - c_sig: Some(Signature { - args: &[Ty::F32, Ty::MutF32, Ty::MutF32], - returns: &[], - }), - fn_list: &["sincosf"], - public: true, - }, - NestedOp { - // `(f64, &mut f64, &mut f64)` as `(f64) -> (f64, f64)` - float_ty: FloatTy::F64, - rust_sig: Signature { - args: &[Ty::F64], - returns: &[Ty::F64, Ty::F64], - }, - c_sig: Some(Signature { - args: &[Ty::F64, Ty::MutF64, Ty::MutF64], - returns: &[], - }), - fn_list: &["sincos"], - public: true, - }, -]; - -/// A type used in a function signature. -#[allow(dead_code)] -#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] -pub enum Ty { - F16, - F32, - F64, - F128, - I32, - CInt, - MutF16, - MutF32, - MutF64, - MutF128, - MutI32, - MutCInt, -} - -/// A subset of [`Ty`] representing only floats. -#[allow(dead_code)] -#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] -pub enum FloatTy { - F16, - F32, - F64, - F128, -} - -impl fmt::Display for Ty { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let s = match self { - Ty::F16 => "f16", - Ty::F32 => "f32", - Ty::F64 => "f64", - Ty::F128 => "f128", - Ty::I32 => "i32", - Ty::CInt => "::core::ffi::c_int", - Ty::MutF16 => "&mut f16", - Ty::MutF32 => "&mut f32", - Ty::MutF64 => "&mut f64", - Ty::MutF128 => "&mut f128", - Ty::MutI32 => "&mut i32", - Ty::MutCInt => "&mut ::core::ffi::c_int", - }; - f.write_str(s) - } -} - -impl fmt::Display for FloatTy { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let s = match self { - FloatTy::F16 => "f16", - FloatTy::F32 => "f32", - FloatTy::F64 => "f64", - FloatTy::F128 => "f128", - }; - f.write_str(s) - } -} - -/// Representation of e.g. `(f32, f32) -> f32` -#[derive(Debug, Clone)] -pub struct Signature { - pub args: &'static [Ty], - pub returns: &'static [Ty], -} - -/// Combined information about a function implementation. -#[derive(Debug, Clone)] -pub struct MathOpInfo { - pub name: &'static str, - pub float_ty: FloatTy, - /// Function signature for C implementations - pub c_sig: Signature, - /// Function signature for Rust implementations - pub rust_sig: Signature, - /// True if part of libm's public API - pub public: bool, -} - -/// A flat representation of `ALL_FUNCTIONS`. -pub static ALL_OPERATIONS: LazyLock> = LazyLock::new(|| { - let mut ret = Vec::new(); - - for op in ALL_OPERATIONS_NESTED { - let fn_names = op.fn_list; - for name in fn_names { - let api = MathOpInfo { - name, - float_ty: op.float_ty, - rust_sig: op.rust_sig.clone(), - c_sig: op.c_sig.clone().unwrap_or_else(|| op.rust_sig.clone()), - public: op.public, - }; - ret.push(api); - } - - if !fn_names.is_sorted() { - let mut sorted = (*fn_names).to_owned(); - sorted.sort_unstable(); - panic!("names list is not sorted: {fn_names:?}\nExpected: {sorted:?}"); - } - } - - ret.sort_by_key(|item| item.name); - ret -}); diff --git a/compiler-builtins/crates/libm-macros/tests/basic.rs b/compiler-builtins/crates/libm-macros/tests/basic.rs index 1876db8f5869d..668127c298e47 100644 --- a/compiler-builtins/crates/libm-macros/tests/basic.rs +++ b/compiler-builtins/crates/libm-macros/tests/basic.rs @@ -7,14 +7,13 @@ macro_rules! basic { ( fn_name: $fn_name:ident, - FTy: $FTy:ty, CFn: $CFn:ty, CArgs: $CArgs:ty, CRet: $CRet:ty, RustFn: $RustFn:ty, RustArgs: $RustArgs:ty, RustRet: $RustRet:ty, - public: $public:expr, + path: $path:path, attrs: [$($attr:meta),*], extra: [$($extra_tt:tt)*], fn_extra: $fn_extra:expr, @@ -22,12 +21,11 @@ macro_rules! basic { $(#[$attr])* #[allow(dead_code)] pub mod $fn_name { - type FTy= $FTy; type CFnTy<'a> = $CFn; type RustFnTy = $RustFn; type RustArgsTy = $RustArgs; type RustRetTy = $RustRet; - const PUBLIC: bool = $public; + const PATH: &str = stringify!($path); const A: &[&str] = &[$($extra_tt)*]; fn foo(a: f32) -> f32 { $fn_extra(a) @@ -147,6 +145,7 @@ fn test_fn_extra_expansion() { let mut vf32 = Vec::new(); let mut vf64 = Vec::new(); let mut vf128 = Vec::new(); + let mut vbuiltins = Vec::new(); // Test with no extra, no skip, and no attributes libm_macros::for_each_function! { @@ -156,6 +155,7 @@ fn test_fn_extra_expansion() { ALL_F32 => vf32, ALL_F64 => vf64, ALL_F128 => vf128, + ALL_BUILTINS => vbuiltins, } } @@ -171,8 +171,11 @@ fn test_fn_extra_expansion() { for name in vf32 { assert!(name.ends_with("f"), "{name}"); } - let _ = vf64; for name in vf128 { assert!(name.ends_with("f128"), "{name}"); } + + // Nothing to assert here + let _ = vf64; + let _ = vbuiltins; } diff --git a/compiler-builtins/crates/libm-macros/tests/enum.rs b/compiler-builtins/crates/libm-macros/tests/enum.rs index 93e209a0dcc90..f012e0a9ef0ad 100644 --- a/compiler-builtins/crates/libm-macros/tests/enum.rs +++ b/compiler-builtins/crates/libm-macros/tests/enum.rs @@ -23,16 +23,3 @@ fn basename() { assert_eq!(Identifier::Sin.base_name(), BaseName::Sin); assert_eq!(Identifier::Sinf.base_name(), BaseName::Sin); } - -#[test] -fn math_op() { - assert_eq!(Identifier::Sin.math_op().float_ty, FloatTy::F64); - assert_eq!(Identifier::Sinf.math_op().float_ty, FloatTy::F32); -} - -// Replicate the structure that we have in `libm-test` -mod op { - include!("../../libm-macros/src/shared.rs"); -} - -use op::FloatTy; diff --git a/compiler-builtins/crates/musl-math-sys/build.rs b/compiler-builtins/crates/musl-math-sys/build.rs index 3bab5f2eb112a..7f7080daa9943 100644 --- a/compiler-builtins/crates/musl-math-sys/build.rs +++ b/compiler-builtins/crates/musl-math-sys/build.rs @@ -52,7 +52,7 @@ fn main() { println!( "cargo::warning=Musl doesn't compile with the current \ target {}; skipping build", - &cfg.target_string + cfg.target_string ); return; } diff --git a/compiler-builtins/crates/symbol-check/src/main.rs b/compiler-builtins/crates/symbol-check/src/main.rs index 135019e5f729e..11486b6ff1138 100644 --- a/compiler-builtins/crates/symbol-check/src/main.rs +++ b/compiler-builtins/crates/symbol-check/src/main.rs @@ -13,8 +13,8 @@ use std::{env, fs}; use object::read::archive::ArchiveFile; use object::{ - Architecture, BinaryFormat, Endianness, File as ObjFile, Object, ObjectSection, ObjectSymbol, - Result as ObjResult, SectionFlags, Symbol, SymbolKind, SymbolScope, U32, elf, + Architecture, BinaryFormat, Endianness, File as ObjFile, FileFlags, Object, ObjectSection, + ObjectSymbol, Result as ObjResult, SectionFlags, Symbol, SymbolKind, SymbolScope, U32, elf, }; use regex::Regex; use serde_json::Value; @@ -526,12 +526,15 @@ fn check_elf_exe_stack(obj: &ObjFile) -> Result<(), ExeStack> { return Ok(()); } + let FileFlags::Elf { e_flags, .. } = obj.flags() else { + unreachable!("only elf files are being checked"); + }; + // If there is no `.note.GNU-stack` and no executable sections, behavior differs by platform. match obj.architecture() { // PPC64 doesn't set `.note.GNU-stack` since GNU nested functions don't need a trampoline, - // . From experimentation, it seems - // like this only applies to big endian. - Architecture::PowerPc64 if obj.endianness() == Endianness::Big => Ok(()), + // . This only applies to ELFv1. + Architecture::PowerPc64 if e_flags & elf::EF_PPC64_ABI != 2 => Ok(()), _ => Err(ExeStack::MissingGnuStackSec), } diff --git a/compiler-builtins/crates/symbol-check/tests/all.rs b/compiler-builtins/crates/symbol-check/tests/all.rs index cfc8641aca82a..d038fd0dc935f 100644 --- a/compiler-builtins/crates/symbol-check/tests/all.rs +++ b/compiler-builtins/crates/symbol-check/tests/all.rs @@ -111,8 +111,11 @@ mod exe_stack { let assert = t.symcheck_exe().arg(obj).arg("--no-visibility").assert(); - if t.is_ppc64be() || t.no_os() || t.binary_obj_format() != BinaryFormat::Elf { - // Ppc64be doesn't emit `.note.GNU-stack`, not relevant without an OS, and non-elf + if (t.is_ppc64be() && t.is_glibc()) + || t.no_os() + || t.binary_obj_format() != BinaryFormat::Elf + { + // Ppc64be ELFv1 doesn't emit `.note.GNU-stack`, not relevant without an OS, and non-elf // targets don't use `.note.GNU-stack`. assert.success(); return; @@ -143,8 +146,8 @@ mod exe_stack { let assert = t.symcheck_exe().arg(obj).arg("--no-visibility").assert(); - if t.is_ppc64be() || t.no_os() { - // Ppc64be doesn't emit `.note.GNU-stack`, not relevant without an OS. + if (t.is_ppc64be() && t.is_glibc()) || t.no_os() { + // Ppc64be ELFv1 doesn't emit `.note.GNU-stack`, not relevant without an OS. assert.success(); return; } @@ -316,6 +319,10 @@ impl TestTarget { self.triple.starts_with("powerpc64-") } + fn is_glibc(&self) -> bool { + self.triple.contains("-linux-gnu") + } + /// True if the target needs `--no-os` passed to symcheck. fn no_os(&self) -> bool { self.triple.contains("-none") diff --git a/compiler-builtins/crates/symbol-check/tests/input/missing_gnu_stack_section.S b/compiler-builtins/crates/symbol-check/tests/input/missing_gnu_stack_section.S index 09bb761c40ba7..99ac3ba51c47d 100644 --- a/compiler-builtins/crates/symbol-check/tests/input/missing_gnu_stack_section.S +++ b/compiler-builtins/crates/symbol-check/tests/input/missing_gnu_stack_section.S @@ -4,6 +4,12 @@ * executability is implied (usually yes on Linux). */ +/* Unless we set the ABI version, we have no way to differentiate between + big-endian ppc64 ELFv1 or ELFv2 since e_flags is otherwise unspecified */ +#if defined(__powerpc64__) && _CALL_ELF == 2 +.abiversion 2 +#endif + .global func #ifdef __wasm__ diff --git a/compiler-builtins/crates/update-api-list/Cargo.toml b/compiler-builtins/crates/update-api-list/Cargo.toml new file mode 100644 index 0000000000000..7a14a0e9770f5 --- /dev/null +++ b/compiler-builtins/crates/update-api-list/Cargo.toml @@ -0,0 +1,13 @@ +[package] +name = "update-api-list" +version = "0.1.0" +edition = "2024" +publish = false +license = "MIT OR Apache-2.0" + +[dependencies] +api-list-common.workspace = true +getopts.workspace = true +glob.workspace = true +pretty_assertions.workspace = true +regex.workspace = true diff --git a/compiler-builtins/crates/update-api-list/src/lib.rs b/compiler-builtins/crates/update-api-list/src/lib.rs new file mode 100644 index 0000000000000..a07ae3411ee37 --- /dev/null +++ b/compiler-builtins/crates/update-api-list/src/lib.rs @@ -0,0 +1,11 @@ +use std::path::{Path, PathBuf}; +use std::sync::LazyLock; + +pub static WORKSPACE_ROOT: LazyLock = LazyLock::new(|| { + Path::new(env!("CARGO_MANIFEST_DIR")) + .parent() + .unwrap() + .parent() + .unwrap() + .to_owned() +}); diff --git a/compiler-builtins/crates/update-api-list/tests/all.rs b/compiler-builtins/crates/update-api-list/tests/all.rs new file mode 100644 index 0000000000000..814c7cc3fa0ca --- /dev/null +++ b/compiler-builtins/crates/update-api-list/tests/all.rs @@ -0,0 +1,128 @@ +use std::fs; +use std::path::Path; +use std::process::Command; +use std::sync::LazyLock; + +use pretty_assertions::assert_str_eq; +use regex::Regex; +use update_api_list::WORKSPACE_ROOT; + +static PUBLIC_FUNCTIONS: LazyLock> = LazyLock::new(|| { + fs::read_to_string(WORKSPACE_ROOT.join("etc/function-list.txt")) + .unwrap() + .lines() + .map(|line| line.trim()) + .filter(|line| !(line.starts_with("#") || line.is_empty())) + .map(|line| line.to_owned()) + .collect() +}); + +/// In each file, check annotations indicating that blocks of code should be sorted or should +/// include an exhaustive list of all public API. +#[test] +fn tidy_lists() { + let out = Command::new("git") + .arg("ls-files") + .current_dir(&*WORKSPACE_ROOT) + .output() + .unwrap(); + assert!(out.status.success()); + + let file_list = str::from_utf8(&out.stdout).unwrap(); + + for path in file_list.lines() { + let relpath = Path::new(path); + let abspath = WORKSPACE_ROOT.join(relpath); + if abspath.is_dir() || relpath == file!() { + continue; + } + + let src = fs::read_to_string(&abspath).unwrap(); + let lines: Vec<_> = src.lines().collect(); + + validate_delimited_block( + relpath, + &lines, + "verify-sorted-start", + "verify-sorted-end", + ensure_sorted, + ); + + validate_delimited_block( + relpath, + &lines, + "verify-apilist-start", + "verify-apilist-end", + ensure_contains_api, + ); + } +} + +/// Identify blocks of code wrapped within `start` and `end`, collect their contents to a list of +/// strings, and call `validate` for each of those lists. +fn validate_delimited_block( + relpath: &Path, + lines: &[&str], + start: &str, + end: &str, + validate: impl Fn(&Path, usize, &[&str]), +) { + let mut block_lines = Vec::new(); + let mut block_start_line = None; + for (mut line_num, line) in lines.iter().enumerate() { + line_num += 1; + + if line.contains(start) { + block_start_line = Some(line_num); + continue; + } + + // End of a block, validate its contents + if line.contains(end) { + let Some(start_line) = block_start_line else { + panic!("`{end}` without `{start}` at {relpath:?}:{line_num}"); + }; + + validate(relpath, start_line, &block_lines); + block_lines.clear(); + block_start_line = None; + continue; + } + + if block_start_line.is_some() { + block_lines.push(*line); + } + } + + if let Some(start_line) = block_start_line { + panic!("`{start}` without `{end}` at {relpath:?}:{start_line}"); + } +} + +/// Given a list of strings, ensure that each public function we have is named somewhere. +fn ensure_contains_api(relpath: &Path, block_start_line: usize, lines: &[&str]) { + let mut not_found = Vec::new(); + + for func in &*PUBLIC_FUNCTIONS { + // The function name may be on its own or somewhere in a snake case string. + let re = Regex::new(&format!(r"(\b|_){func}(\b|_)")).unwrap(); + if !lines.iter().any(|line| re.is_match(line)) { + not_found.push(func); + } + } + + if not_found.is_empty() { + return; + } + + panic!("functions not found at {relpath:?}:{block_start_line}: {not_found:?}"); +} + +fn ensure_sorted(relpath: &Path, block_start_line: usize, lines: &[&str]) { + let mut sorted = lines.to_owned(); + sorted.sort_unstable(); + let a = lines.join("\n"); + let b = sorted.join("\n"); + + assert_str_eq!(a, b, "sorted block at {relpath:?}:{block_start_line}"); +} diff --git a/compiler-builtins/crates/util/build.rs b/compiler-builtins/crates/util/build.rs index a1be4127527ae..f7ed72addee10 100644 --- a/compiler-builtins/crates/util/build.rs +++ b/compiler-builtins/crates/util/build.rs @@ -1,10 +1,10 @@ -#![allow(unexpected_cfgs)] - #[path = "../../libm/configure.rs"] mod configure; +use configure::{Config, Library}; + fn main() { println!("cargo:rerun-if-changed=../../libm/configure.rs"); - let cfg = configure::Config::from_env(); - configure::emit_libm_config(&cfg); + let cfg = Config::from_env(Library::Util); + configure::emit(&cfg); } diff --git a/compiler-builtins/crates/util/src/main.rs b/compiler-builtins/crates/util/src/main.rs index 70aa613f18d06..ac2c126d8c0d1 100644 --- a/compiler-builtins/crates/util/src/main.rs +++ b/compiler-builtins/crates/util/src/main.rs @@ -9,10 +9,10 @@ use std::num::ParseIntError; use std::str::FromStr; use cfg_if::cfg_if; -use libm::support::{Float, Hexf, hf32, hf64}; +use libm::support::{Float, Hex, hf32, hf64}; #[cfg(feature = "build-mpfr")] use libm_test::mpfloat::MpOp; -use libm_test::{Hex, MathOp, TupleCall}; +use libm_test::{MathOp, TupleCall, builtins_wrapper}; #[cfg(feature = "build-mpfr")] use rug::az::{self, Az}; @@ -37,7 +37,14 @@ SUBCOMMAND: fn main() { let args = env::args().collect::>(); - let str_args = args.iter().map(|s| s.as_str()).collect::>(); + let str_args = args + .iter() + .map(|s| { + // Allow pasting from comma-separated arguments + let s = s.as_str(); + s.strip_suffix(",").unwrap_or(s) + }) + .collect::>(); match &str_args.as_slice()[1..] { ["eval" | "x", basis, op, inputs @ ..] => do_eval(basis, op, inputs), @@ -55,6 +62,7 @@ macro_rules! handle_call { CFn: $CFn:ty, RustFn: $RustFn:ty, RustArgs: $RustArgs:ty, + path: $path:path, attrs: [$($attr:meta),*], extra: ($basis:ident, $op:ident, $inputs:ident), fn_extra: $musl_fn:expr, @@ -64,7 +72,7 @@ macro_rules! handle_call { type Op = libm_test::op::$fn_name::Routine; let input = <$RustArgs>::parse($inputs); - let libm_fn: ::RustFn = libm::$fn_name; + let libm_fn: ::RustFn = $path; let output = match $basis { "libm" => input.call_intercept_panics(libm_fn), @@ -81,7 +89,7 @@ macro_rules! handle_call { } _ => panic!("unrecognized or disabled basis '{}'", $basis), }; - println!("{output:?} {:x}", Hexf(output)); + println!("{output:?} {:x}", Hex(output)); return; } }; @@ -91,7 +99,7 @@ macro_rules! handle_call { fn do_eval(basis: &str, op: &str, inputs: &[&str]) { libm_macros::for_each_function! { callback: handle_call, - emit_types: [CFn, RustFn, RustArgs], + emit_types: [CFn, RustFn, RustArgs, path], extra: (basis, op, inputs), fn_extra: match MACRO_FN_NAME { // Not provided by musl @@ -106,7 +114,8 @@ fn do_eval(basis: &str, op: &str, inputs: &[&str]) { | roundeven | roundevenf | ALL_F16 - | ALL_F128 => None, + | ALL_F128 + | ALL_BUILTINS => None, _ => Some(musl_math_sys::MACRO_FN_NAME) } } @@ -160,18 +169,17 @@ fn do_classify(inputs: &[&str]) { fn classify_print(x: F) where F: Float, - F::Int: Hex, { println!("{x:?}"); - println!(" hex: {}", Hexf(x)); - println!(" bits: {}", x.to_bits().hex()); + println!(" hex: {}", Hex(x)); + println!(" bits: {}", Hex(x.to_bits())); println!(" nan: {}", x.is_nan()); println!(" inf: {}", x.is_infinite()); println!(" normal: {}", !x.is_subnormal()); println!(" pos: {}", x.is_sign_positive()); - println!(" exp: {} {}", x.ex(), x.ex().hex()); + println!(" exp: {} {}", x.ex(), Hex(x.ex())); println!(" exp unbiased: {}", x.exp_unbiased()); - println!(" frac: {} {}", x.frac(), x.frac().hex()); + println!(" frac: {} {}", x.frac(), Hex(x.frac())); } /// Parse a tuple from a space-delimited string. @@ -308,6 +316,48 @@ impl_parse_tuple!(f64); #[cfg(f128_enabled)] impl_parse_tuple_via_rug!(f128); +macro_rules! impl_parse_tuple_int { + (@skip_u32 $ty:ty) => { + impl ParseTuple for ($ty,) { + fn parse(input: &[&str]) -> Self { + assert_eq!(input.len(), 1, "expected a single argument, got {input:?}"); + (parse(input, 0),) + } + } + + impl ParseTuple for ($ty, $ty) { + fn parse(input: &[&str]) -> Self { + assert_eq!(input.len(), 2, "expected two arguments, got {input:?}"); + (parse(input, 0), parse(input, 1)) + } + } + + impl FromStrRadix for $ty { + fn from_str_radix(s: &str, radix: u32) -> Result { + let s = strip_radix_prefix(s, radix); + <$ty>::from_str_radix(s, radix) + } + } + }; + ($ty:ty) => { + impl_parse_tuple_int!(@skip_u32 $ty); + + impl ParseTuple for ($ty, u32) { + fn parse(input: &[&str]) -> Self { + assert_eq!(input.len(), 2, "expected two arguments, got {input:?}"); + (parse(input, 0), parse(input, 1)) + } + } + }; +} + +impl_parse_tuple_int!(i32); +impl_parse_tuple_int!(i64); +impl_parse_tuple_int!(i128); +impl_parse_tuple_int!(@skip_u32 u32); +impl_parse_tuple_int!(u64); +impl_parse_tuple_int!(u128); + /// Try to parse the number, printing a nice message on failure. fn parse(input: &[&str], idx: usize) -> T { let s = input[idx]; @@ -354,13 +404,6 @@ trait FromStrRadix: Sized { fn from_str_radix(s: &str, radix: u32) -> Result; } -impl FromStrRadix for i32 { - fn from_str_radix(s: &str, radix: u32) -> Result { - let s = strip_radix_prefix(s, radix); - i32::from_str_radix(s, radix) - } -} - #[cfg(f16_enabled)] impl FromStrRadix for f16 { fn from_str_radix(s: &str, radix: u32) -> Result { diff --git a/compiler-builtins/etc/function-definitions.json b/compiler-builtins/etc/function-definitions.json index 6bd395a84b66f..f59bb7ceebb42 100644 --- a/compiler-builtins/etc/function-definitions.json +++ b/compiler-builtins/etc/function-definitions.json @@ -98,8 +98,8 @@ }, "ceil": { "sources": [ - "libm/src/math/arch/i586.rs", - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/i586/rounding.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/ceil.rs", "libm/src/math/generic/ceil.rs" ], @@ -107,7 +107,7 @@ }, "ceilf": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/ceil.rs", "libm/src/math/generic/ceil.rs" ], @@ -253,7 +253,7 @@ }, "fabs": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/fabs.rs", "libm/src/math/fabs.rs", "libm/src/math/generic/fabs.rs" ], @@ -261,7 +261,7 @@ }, "fabsf": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/fabs.rs", "libm/src/math/fabs.rs", "libm/src/math/generic/fabs.rs" ], @@ -311,8 +311,8 @@ }, "floor": { "sources": [ - "libm/src/math/arch/i586.rs", - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/i586/rounding.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/floor.rs", "libm/src/math/generic/floor.rs" ], @@ -320,7 +320,7 @@ }, "floorf": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/floor.rs", "libm/src/math/generic/floor.rs" ], @@ -342,26 +342,36 @@ }, "fma": { "sources": [ - "libm/src/math/arch/aarch64.rs", + "libm/src/math/arch/aarch64/fma.rs", "libm/src/math/arch/x86/fma.rs", - "libm/src/math/fma.rs" + "libm/src/math/fma.rs", + "libm/src/math/generic/fma.rs" ], "type": "f64" }, "fmaf": { "sources": [ - "libm/src/math/arch/aarch64.rs", + "libm/src/math/arch/aarch64/fma.rs", "libm/src/math/arch/x86/fma.rs", - "libm/src/math/fma.rs" + "libm/src/math/fma.rs", + "libm/src/math/generic/fma.rs" ], "type": "f32" }, "fmaf128": { "sources": [ - "libm/src/math/fma.rs" + "libm/src/math/fma.rs", + "libm/src/math/generic/fma.rs" ], "type": "f128" }, + "fmaf16": { + "sources": [ + "libm/src/math/fmaf16.rs", + "libm/src/math/generic/fma.rs" + ], + "type": "f16" + }, "fmax": { "sources": [ "libm/src/math/fmin_fmax.rs", @@ -820,29 +830,34 @@ }, "rint": { "sources": [ - "libm/src/math/arch/aarch64.rs", - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/aarch64/rounding.rs", + "libm/src/math/arch/i586/rounding.rs", + "libm/src/math/arch/wasm32/rounding.rs", + "libm/src/math/generic/rint.rs", "libm/src/math/rint.rs" ], "type": "f64" }, "rintf": { "sources": [ - "libm/src/math/arch/aarch64.rs", - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/aarch64/rounding.rs", + "libm/src/math/arch/wasm32/rounding.rs", + "libm/src/math/generic/rint.rs", "libm/src/math/rint.rs" ], "type": "f32" }, "rintf128": { "sources": [ + "libm/src/math/generic/rint.rs", "libm/src/math/rint.rs" ], "type": "f128" }, "rintf16": { "sources": [ - "libm/src/math/arch/aarch64.rs", + "libm/src/math/arch/aarch64/rounding.rs", + "libm/src/math/generic/rint.rs", "libm/src/math/rint.rs" ], "type": "f16" @@ -965,9 +980,9 @@ }, "sqrt": { "sources": [ - "libm/src/math/arch/aarch64.rs", - "libm/src/math/arch/wasm32.rs", - "libm/src/math/arch/x86.rs", + "libm/src/math/arch/aarch64/sqrt.rs", + "libm/src/math/arch/wasm32/sqrt.rs", + "libm/src/math/arch/x86/sqrt.rs", "libm/src/math/generic/sqrt.rs", "libm/src/math/sqrt.rs" ], @@ -975,9 +990,9 @@ }, "sqrtf": { "sources": [ - "libm/src/math/arch/aarch64.rs", - "libm/src/math/arch/wasm32.rs", - "libm/src/math/arch/x86.rs", + "libm/src/math/arch/aarch64/sqrt.rs", + "libm/src/math/arch/wasm32/sqrt.rs", + "libm/src/math/arch/x86/sqrt.rs", "libm/src/math/generic/sqrt.rs", "libm/src/math/sqrt.rs" ], @@ -992,7 +1007,7 @@ }, "sqrtf16": { "sources": [ - "libm/src/math/arch/aarch64.rs", + "libm/src/math/arch/aarch64/sqrt.rs", "libm/src/math/generic/sqrt.rs", "libm/src/math/sqrt.rs" ], @@ -1036,7 +1051,7 @@ }, "trunc": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/generic/trunc.rs", "libm/src/math/trunc.rs" ], @@ -1044,7 +1059,7 @@ }, "truncf": { "sources": [ - "libm/src/math/arch/wasm32.rs", + "libm/src/math/arch/wasm32/rounding.rs", "libm/src/math/generic/trunc.rs", "libm/src/math/trunc.rs" ], diff --git a/compiler-builtins/etc/function-list.txt b/compiler-builtins/etc/function-list.txt index f7a694d10f95a..14f75a2c5783b 100644 --- a/compiler-builtins/etc/function-list.txt +++ b/compiler-builtins/etc/function-list.txt @@ -54,6 +54,7 @@ floorf16 fma fmaf fmaf128 +fmaf16 fmax fmaxf fmaxf128 diff --git a/compiler-builtins/etc/update-api-list.py b/compiler-builtins/etc/update-api-list.py index 76c75cbf4dccb..2d8ad2903646d 100755 --- a/compiler-builtins/etc/update-api-list.py +++ b/compiler-builtins/etc/update-api-list.py @@ -6,6 +6,8 @@ needed, or that lists are sorted. """ +# FIXME: this needs to be updated to work with compiler-builtins sources + import difflib import json import re @@ -14,7 +16,7 @@ from dataclasses import dataclass from glob import glob from pathlib import Path -from typing import Any, Callable, TypeAlias +from typing import Any, TypeAlias SELF_PATH = Path(__file__) ETC_DIR = SELF_PATH.parent @@ -116,10 +118,20 @@ def _init_function_list(self, index: IndexTy) -> None: def _init_defs(self, index: IndexTy) -> None: defs = {name: set() for name in self.public_functions} - funcs = (i for i in index.values() if "function" in i["inner"]) - funcs = (f for f in funcs if f["name"] in self.public_functions) - for func in funcs: - defs[func["name"]].add(func["span"]["filename"]) + all_funcs = (i for i in index.values() if "function" in i["inner"]) + + for func_def in all_funcs: + func_def_name = func_def["name"] + for pub_func_name in self.public_functions: + needles = [ + pub_func_name, + f"{pub_func_name}_round", + f"{pub_func_name}_status", + ] + if not any(needle == func_def_name for needle in needles): + continue + + defs[pub_func_name].add(func_def["span"]["filename"]) # A lot of the `arch` module is often configured out so doesn't show up in docs. Use # string matching as a fallback. @@ -134,6 +146,8 @@ def _init_defs(self, index: IndexTy) -> None: for name, sources in defs.items(): base_sources = defs[base_name(name)[0]] + + # Also add any functions in `generic` that use this function's base name for src in (s for s in base_sources if "generic" in s): sources.add(src) @@ -187,36 +201,6 @@ def write_function_defs(self, check: bool) -> None: with open(out_file, "w") as f: f.write(output) - def tidy_lists(self) -> None: - """In each file, check annotations indicating blocks of code should be sorted or should - include all public API. - """ - - flist = sp.check_output(["git", "ls-files"], cwd=ROOT_DIR, text=True) - - for path in flist.splitlines(): - fpath = ROOT_DIR.joinpath(path) - if fpath.is_dir() or fpath == SELF_PATH: - continue - - lines = fpath.read_text().splitlines() - - validate_delimited_block( - fpath, - lines, - "verify-sorted-start", - "verify-sorted-end", - ensure_sorted, - ) - - validate_delimited_block( - fpath, - lines, - "verify-apilist-start", - "verify-apilist-end", - lambda p, n, lines: self.ensure_contains_api(p, n, lines), - ) - def ensure_contains_api(self, fpath: Path, line_num: int, lines: list[str]): """Given a list of strings, ensure that each public function we have is named somewhere. @@ -238,54 +222,6 @@ def ensure_contains_api(self, fpath: Path, line_num: int, lines: list[str]): exit(1) -def validate_delimited_block( - fpath: Path, - lines: list[str], - start: str, - end: str, - validate: Callable[[Path, int, list[str]], None], -) -> None: - """Identify blocks of code wrapped within `start` and `end`, collect their contents - to a list of strings, and call `validate` for each of those lists. - """ - relpath = fpath.relative_to(ROOT_DIR) - block_lines = [] - block_start_line: None | int = None - for line_num, line in enumerate(lines): - line_num += 1 - - if start in line: - block_start_line = line_num - continue - - if end in line: - if block_start_line is None: - eprint(f"`{end}` without `{start}` at {relpath}:{line_num}") - exit(1) - - validate(fpath, block_start_line, block_lines) - block_lines = [] - block_start_line = None - continue - - if block_start_line is not None: - block_lines.append(line) - - if block_start_line is not None: - eprint(f"`{start}` without `{end}` at {relpath}:{block_start_line}") - exit(1) - - -def ensure_sorted(fpath: Path, block_start_line: int, lines: list[str]) -> None: - """Ensure that a list of lines is sorted, otherwise print a diff and exit.""" - relpath = fpath.relative_to(ROOT_DIR) - diff_and_exit( - "\n".join(lines), - "\n".join(sorted(lines)), - f"sorted block at {relpath}:{block_start_line}", - ) - - def diff_and_exit(actual: str, expected: str, name: str): """If the two strings are different, print a diff between them and then exit with an error. @@ -322,11 +258,13 @@ def base_name(name: str) -> tuple[str, str]: if name.endswith("f"): return (name.rstrip("f"), "f32") - - if name.endswith("f16"): + elif name.endswith("f16"): return (name.rstrip("f16"), "f16") - - if name.endswith("f128"): + elif name.endswith("f32"): + return (name.rstrip("f32"), "f32") + elif name.endswith("f64"): + return (name.rstrip("f64"), "f64") + elif name.endswith("f128"): return (name.rstrip("f128"), "f128") return (name, "f64") @@ -340,8 +278,6 @@ def ensure_updated_list(check: bool) -> None: crate.write_function_list(check) crate.write_function_defs(check) - crate.tidy_lists() - def main(): """By default overwrite the file. If `--check` is passed, print a diff instead and diff --git a/compiler-builtins/libm-test/Cargo.toml b/compiler-builtins/libm-test/Cargo.toml index 8a8c2b0a2ce01..5014fb0008611 100644 --- a/compiler-builtins/libm-test/Cargo.toml +++ b/compiler-builtins/libm-test/Cargo.toml @@ -7,10 +7,12 @@ license = "MIT OR Apache-2.0" [dependencies] anyhow.workspace = true +api-list-common.workspace = true +compiler_builtins = { workspace = true, default-features = false, features = ["unstable-public-internals"] } # This is not directly used but is required so we can enable `gmp-mpfr-sys/force-cross`. gmp-mpfr-sys = { workspace = true, optional = true } indicatif.workspace = true -libm = { workspace = true, default-features = true, features = ["unstable-public-internals"] } +libm = { workspace = true, default-features = false, features = ["unstable-public-internals"] } libm-macros.workspace = true musl-math-sys = { workspace = true, optional = true } paste.workspace = true @@ -34,7 +36,9 @@ rand = { workspace = true, optional = true } libtest-mimic.workspace = true [features] -default = ["build-mpfr", "unstable-float"] +# Defaults should match the defaults in compiler-builtins since we have that +# dependency with `default-features=false`. +default = ["build-mpfr", "unstable-float", "compiler_builtins/arch"] # Propagated from libm because this affects which functions we test. unstable-float = ["libm/unstable-float", "rug?/nightly-float"] @@ -72,9 +76,3 @@ required-features = ["walltime"] # `z` so these tests get run last. name = "z_extensive" harness = false - -[lints.rust] -# Values from the chared config.rs used by `libm` but not the test crate -unexpected_cfgs = { level = "warn", check-cfg = [ - 'cfg(feature, values("arch", "force-soft-floats", "unstable-intrinsics"))', -] } diff --git a/compiler-builtins/libm-test/benches/icount.rs b/compiler-builtins/libm-test/benches/icount.rs index 617e9fb7ad21f..8e067f2da5e6d 100644 --- a/compiler-builtins/libm-test/benches/icount.rs +++ b/compiler-builtins/libm-test/benches/icount.rs @@ -5,7 +5,7 @@ use std::hint::black_box; use gungraun::{library_benchmark, library_benchmark_group, main}; -use libm::support::{HInt, Hexf, hf16, hf32, hf64, hf128, u256}; +use libm::support::{HInt, Hex, hf16, hf32, hf64, hf128, i256, u256}; use libm_test::generate::spaced; use libm_test::{CheckBasis, CheckCtx, GeneratorKind, MathOp, OpRustArgs, TupleCall, op}; @@ -41,11 +41,6 @@ macro_rules! icount_benches { input.call(f); } } - - library_benchmark_group!( - name = [< icount_bench_ $fn_name _group >]; - benchmarks = [< icount_bench_ $fn_name >] - ); } }; } @@ -54,6 +49,325 @@ libm_macros::for_each_function! { callback: icount_benches, } +library_benchmark_group!( + name = icount_bench_math_group, + benchmarks = [ + // verify-apilist-start + // verify-sorted-start + icount_bench_acos, + icount_bench_acosf, + icount_bench_acosh, + icount_bench_acoshf, + icount_bench_addf128, + icount_bench_addf16, + icount_bench_addf32, + icount_bench_addf64, + icount_bench_ashl_u128, + icount_bench_ashl_u32, + icount_bench_ashl_u64, + icount_bench_ashr_i128, + icount_bench_ashr_i32, + icount_bench_ashr_i64, + icount_bench_asin, + icount_bench_asinf, + icount_bench_asinh, + icount_bench_asinhf, + icount_bench_atan, + icount_bench_atan2, + icount_bench_atan2f, + icount_bench_atanf, + icount_bench_atanh, + icount_bench_atanhf, + icount_bench_cbrt, + icount_bench_cbrtf, + icount_bench_ceil, + icount_bench_ceilf, + icount_bench_ceilf128, + icount_bench_ceilf16, + icount_bench_copysign, + icount_bench_copysignf, + icount_bench_copysignf128, + icount_bench_copysignf16, + icount_bench_cos, + icount_bench_cosf, + icount_bench_cosh, + icount_bench_coshf, + icount_bench_divf128, + icount_bench_divf32, + icount_bench_divf64, + icount_bench_eqf128, + icount_bench_eqf16, + icount_bench_eqf32, + icount_bench_eqf64, + icount_bench_erf, + icount_bench_erfc, + icount_bench_erfcf, + icount_bench_erff, + icount_bench_exp, + icount_bench_exp10, + icount_bench_exp10f, + icount_bench_exp2, + icount_bench_exp2f, + icount_bench_expf, + icount_bench_expm1, + icount_bench_expm1f, + icount_bench_extend_f16_f128, + icount_bench_extend_f16_f32, + icount_bench_extend_f16_f64, + icount_bench_extend_f32_f128, + icount_bench_extend_f32_f64, + icount_bench_extend_f64_f128, + icount_bench_fabs, + icount_bench_fabsf, + icount_bench_fabsf128, + icount_bench_fabsf16, + icount_bench_fdim, + icount_bench_fdimf, + icount_bench_fdimf128, + icount_bench_fdimf16, + icount_bench_floor, + icount_bench_floorf, + icount_bench_floorf128, + icount_bench_floorf16, + icount_bench_fma, + icount_bench_fmaf, + icount_bench_fmaf128, + icount_bench_fmaf16, + icount_bench_fmax, + icount_bench_fmaxf, + icount_bench_fmaxf128, + icount_bench_fmaxf16, + icount_bench_fmaximum, + icount_bench_fmaximum_num, + icount_bench_fmaximum_numf, + icount_bench_fmaximum_numf128, + icount_bench_fmaximum_numf16, + icount_bench_fmaximumf, + icount_bench_fmaximumf128, + icount_bench_fmaximumf16, + icount_bench_fmin, + icount_bench_fminf, + icount_bench_fminf128, + icount_bench_fminf16, + icount_bench_fminimum, + icount_bench_fminimum_num, + icount_bench_fminimum_numf, + icount_bench_fminimum_numf128, + icount_bench_fminimum_numf16, + icount_bench_fminimumf, + icount_bench_fminimumf128, + icount_bench_fminimumf16, + icount_bench_fmod, + icount_bench_fmodf, + icount_bench_fmodf128, + icount_bench_fmodf16, + icount_bench_frexp, + icount_bench_frexpf, + icount_bench_frexpf128, + icount_bench_frexpf16, + icount_bench_ftoi_f128_i128, + icount_bench_ftoi_f128_i32, + icount_bench_ftoi_f128_i64, + icount_bench_ftoi_f128_u128, + icount_bench_ftoi_f128_u32, + icount_bench_ftoi_f128_u64, + icount_bench_ftoi_f32_i128, + icount_bench_ftoi_f32_i32, + icount_bench_ftoi_f32_i64, + icount_bench_ftoi_f32_u128, + icount_bench_ftoi_f32_u32, + icount_bench_ftoi_f32_u64, + icount_bench_ftoi_f64_i128, + icount_bench_ftoi_f64_i32, + icount_bench_ftoi_f64_i64, + icount_bench_ftoi_f64_u128, + icount_bench_ftoi_f64_u32, + icount_bench_ftoi_f64_u64, + icount_bench_gef128, + icount_bench_gef16, + icount_bench_gef32, + icount_bench_gef64, + icount_bench_gtf128, + icount_bench_gtf16, + icount_bench_gtf32, + icount_bench_gtf64, + icount_bench_hypot, + icount_bench_hypotf, + icount_bench_iadd_i128, + icount_bench_iadd_u128, + icount_bench_iaddo_i128, + icount_bench_iaddo_u128, + icount_bench_idiv_i128, + icount_bench_idiv_i32, + icount_bench_idiv_i64, + icount_bench_idiv_u128, + icount_bench_idiv_u32, + icount_bench_idiv_u64, + icount_bench_idivmod_i128, + icount_bench_idivmod_i32, + icount_bench_idivmod_i64, + icount_bench_idivmod_u128, + icount_bench_idivmod_u32, + icount_bench_idivmod_u64, + icount_bench_ilogb, + icount_bench_ilogbf, + icount_bench_ilogbf128, + icount_bench_ilogbf16, + icount_bench_imod_i128, + icount_bench_imod_i32, + icount_bench_imod_i64, + icount_bench_imod_u128, + icount_bench_imod_u32, + icount_bench_imod_u64, + icount_bench_imul_i128, + icount_bench_imul_u64, + icount_bench_imulo_i128, + icount_bench_imulo_i32, + icount_bench_imulo_i64, + icount_bench_imulo_u128, + icount_bench_isub_i128, + icount_bench_isub_u128, + icount_bench_isubo_i128, + icount_bench_isubo_u128, + icount_bench_itof_i128_f128, + icount_bench_itof_i128_f32, + icount_bench_itof_i128_f64, + icount_bench_itof_i32_f128, + icount_bench_itof_i32_f32, + icount_bench_itof_i32_f64, + icount_bench_itof_i64_f128, + icount_bench_itof_i64_f32, + icount_bench_itof_i64_f64, + icount_bench_itof_u128_f128, + icount_bench_itof_u128_f32, + icount_bench_itof_u128_f64, + icount_bench_itof_u32_f128, + icount_bench_itof_u32_f32, + icount_bench_itof_u32_f64, + icount_bench_itof_u64_f128, + icount_bench_itof_u64_f32, + icount_bench_itof_u64_f64, + icount_bench_j0, + icount_bench_j0f, + icount_bench_j1, + icount_bench_j1f, + icount_bench_jn, + icount_bench_jnf, + icount_bench_ldexp, + icount_bench_ldexpf, + icount_bench_ldexpf128, + icount_bench_ldexpf16, + icount_bench_leading_zeros_u128, + icount_bench_leading_zeros_u32, + icount_bench_leading_zeros_u64, + icount_bench_lef128, + icount_bench_lef16, + icount_bench_lef32, + icount_bench_lef64, + icount_bench_lgamma, + icount_bench_lgamma_r, + icount_bench_lgammaf, + icount_bench_lgammaf_r, + icount_bench_log, + icount_bench_log10, + icount_bench_log10f, + icount_bench_log1p, + icount_bench_log1pf, + icount_bench_log2, + icount_bench_log2f, + icount_bench_logf, + icount_bench_lshr_u128, + icount_bench_lshr_u32, + icount_bench_lshr_u64, + icount_bench_ltf128, + icount_bench_ltf16, + icount_bench_ltf32, + icount_bench_ltf64, + icount_bench_modf, + icount_bench_modff, + icount_bench_mulf128, + icount_bench_mulf16, + icount_bench_mulf32, + icount_bench_mulf64, + icount_bench_narrow_f128_f16, + icount_bench_narrow_f128_f32, + icount_bench_narrow_f128_f64, + icount_bench_narrow_f32_f16, + icount_bench_narrow_f64_f16, + icount_bench_narrow_f64_f32, + icount_bench_nef128, + icount_bench_nef16, + icount_bench_nef32, + icount_bench_nef64, + icount_bench_nextafter, + icount_bench_nextafterf, + icount_bench_pow, + icount_bench_powf, + icount_bench_powif128, + icount_bench_powif32, + icount_bench_powif64, + icount_bench_remainder, + icount_bench_remainderf, + icount_bench_remquo, + icount_bench_remquof, + icount_bench_rint, + icount_bench_rintf, + icount_bench_rintf128, + icount_bench_rintf16, + icount_bench_round, + icount_bench_roundeven, + icount_bench_roundevenf, + icount_bench_roundevenf128, + icount_bench_roundevenf16, + icount_bench_roundf, + icount_bench_roundf128, + icount_bench_roundf16, + icount_bench_scalbn, + icount_bench_scalbnf, + icount_bench_scalbnf128, + icount_bench_scalbnf16, + icount_bench_sin, + icount_bench_sincos, + icount_bench_sincosf, + icount_bench_sinf, + icount_bench_sinh, + icount_bench_sinhf, + icount_bench_sqrt, + icount_bench_sqrtf, + icount_bench_sqrtf128, + icount_bench_sqrtf16, + icount_bench_subf128, + icount_bench_subf16, + icount_bench_subf32, + icount_bench_subf64, + icount_bench_tan, + icount_bench_tanf, + icount_bench_tanh, + icount_bench_tanhf, + icount_bench_tgamma, + icount_bench_tgammaf, + icount_bench_trailing_zeros_u128, + icount_bench_trailing_zeros_u32, + icount_bench_trailing_zeros_u64, + icount_bench_trunc, + icount_bench_truncf, + icount_bench_truncf128, + icount_bench_truncf16, + icount_bench_unordf128, + icount_bench_unordf16, + icount_bench_unordf32, + icount_bench_unordf64, + icount_bench_y0, + icount_bench_y0f, + icount_bench_y1, + icount_bench_y1f, + icount_bench_yn, + icount_bench_ynf, + // verify-sorted-end + // verify-apilist-end + ] +); + fn setup_u128_mul() -> Vec<(u128, u128)> { let step = u128::MAX / 300; let mut x = 0u128; @@ -103,6 +417,13 @@ fn setup_u256_shift() -> Vec<(u256, u32)> { v } +fn setup_i256_shift() -> Vec<(i256, u32)> { + setup_u256_shift() + .into_iter() + .map(|(x, i)| (x.signed(), i)) + .collect() +} + #[library_benchmark] #[bench::linspace(setup_u128_mul())] fn icount_bench_u128_widen_mul(cases: Vec<(u128, u128)>) { @@ -154,15 +475,25 @@ fn icount_bench_u256_shr(cases: Vec<(u256, u32)>) { } } +#[library_benchmark] +#[bench::linspace(setup_i256_shift())] +fn icount_bench_i256_shr(cases: Vec<(i256, u32)>) { + for (x, y) in cases.iter().copied() { + black_box(black_box(x) >> black_box(y)); + } +} + library_benchmark_group!( - name = icount_bench_u128_group; - benchmarks = - icount_bench_u128_widen_mul, - icount_bench_u256_narrowing_div, - icount_bench_u256_add, - icount_bench_u256_sub, - icount_bench_u256_shl, - icount_bench_u256_shr + name = icount_bench_u128_group, + benchmarks = [ + icount_bench_u128_widen_mul, + icount_bench_u256_narrowing_div, + icount_bench_u256_add, + icount_bench_u256_sub, + icount_bench_u256_shl, + icount_bench_u256_shr, + icount_bench_i256_shr, + ] ); #[library_benchmark] @@ -194,226 +525,59 @@ fn icount_bench_hf128(s: &str) -> f128 { } library_benchmark_group!( - name = icount_bench_hf_parse_group; - benchmarks = - icount_bench_hf16, - icount_bench_hf32, - icount_bench_hf64, - icount_bench_hf128 + name = icount_bench_hf_parse_group, + benchmarks = [ + icount_bench_hf16, + icount_bench_hf32, + icount_bench_hf64, + icount_bench_hf128, + ] ); #[library_benchmark] #[bench::short(1.015625)] #[bench::max(f16::MAX)] fn icount_bench_print_hf16(x: f16) -> String { - black_box(Hexf(x).to_string()) + black_box(Hex(x).to_string()) } #[library_benchmark] #[bench::short(1.015625)] #[bench::max(f32::MAX)] fn icount_bench_print_hf32(x: f32) -> String { - black_box(Hexf(x).to_string()) + black_box(Hex(x).to_string()) } #[library_benchmark] #[bench::short(1.015625)] #[bench::max(f64::MAX)] fn icount_bench_print_hf64(x: f64) -> String { - black_box(Hexf(x).to_string()) + black_box(Hex(x).to_string()) } #[library_benchmark] #[bench::short(1.015625)] #[bench::max(f128::MAX)] fn icount_bench_print_hf128(x: f128) -> String { - black_box(Hexf(x).to_string()) + black_box(Hex(x).to_string()) } library_benchmark_group!( - name = icount_bench_hf_print_group; - benchmarks = - icount_bench_print_hf16, - icount_bench_print_hf32, - icount_bench_print_hf64, - icount_bench_print_hf128 + name = icount_bench_hf_print_group, + benchmarks = [ + icount_bench_print_hf16, + icount_bench_print_hf32, + icount_bench_print_hf64, + icount_bench_print_hf128, + ] ); main!( - library_benchmark_groups = - // Benchmarks not related to public libm math - icount_bench_u128_group, - icount_bench_hf_parse_group, - icount_bench_hf_print_group, - // verify-apilist-start - // verify-sorted-start - icount_bench_acos_group, - icount_bench_acosf_group, - icount_bench_acosh_group, - icount_bench_acoshf_group, - icount_bench_asin_group, - icount_bench_asinf_group, - icount_bench_asinh_group, - icount_bench_asinhf_group, - icount_bench_atan2_group, - icount_bench_atan2f_group, - icount_bench_atan_group, - icount_bench_atanf_group, - icount_bench_atanh_group, - icount_bench_atanhf_group, - icount_bench_cbrt_group, - icount_bench_cbrtf_group, - icount_bench_ceil_group, - icount_bench_ceilf128_group, - icount_bench_ceilf16_group, - icount_bench_ceilf_group, - icount_bench_copysign_group, - icount_bench_copysignf128_group, - icount_bench_copysignf16_group, - icount_bench_copysignf_group, - icount_bench_cos_group, - icount_bench_cosf_group, - icount_bench_cosh_group, - icount_bench_coshf_group, - icount_bench_erf_group, - icount_bench_erfc_group, - icount_bench_erfcf_group, - icount_bench_erff_group, - icount_bench_exp10_group, - icount_bench_exp10f_group, - icount_bench_exp2_group, - icount_bench_exp2f_group, - icount_bench_exp_group, - icount_bench_expf_group, - icount_bench_expm1_group, - icount_bench_expm1f_group, - icount_bench_fabs_group, - icount_bench_fabsf128_group, - icount_bench_fabsf16_group, - icount_bench_fabsf_group, - icount_bench_fdim_group, - icount_bench_fdimf128_group, - icount_bench_fdimf16_group, - icount_bench_fdimf_group, - icount_bench_floor_group, - icount_bench_floorf128_group, - icount_bench_floorf16_group, - icount_bench_floorf_group, - icount_bench_fma_group, - icount_bench_fmaf128_group, - icount_bench_fmaf_group, - icount_bench_fmax_group, - icount_bench_fmaxf128_group, - icount_bench_fmaxf16_group, - icount_bench_fmaxf_group, - icount_bench_fmaximum_group, - icount_bench_fmaximum_num_group, - icount_bench_fmaximum_numf128_group, - icount_bench_fmaximum_numf16_group, - icount_bench_fmaximum_numf_group, - icount_bench_fmaximumf128_group, - icount_bench_fmaximumf16_group, - icount_bench_fmaximumf_group, - icount_bench_fmin_group, - icount_bench_fminf128_group, - icount_bench_fminf16_group, - icount_bench_fminf_group, - icount_bench_fminimum_group, - icount_bench_fminimum_num_group, - icount_bench_fminimum_numf128_group, - icount_bench_fminimum_numf16_group, - icount_bench_fminimum_numf_group, - icount_bench_fminimumf128_group, - icount_bench_fminimumf16_group, - icount_bench_fminimumf_group, - icount_bench_fmod_group, - icount_bench_fmodf128_group, - icount_bench_fmodf16_group, - icount_bench_fmodf_group, - icount_bench_frexp_group, - icount_bench_frexpf128_group, - icount_bench_frexpf16_group, - icount_bench_frexpf_group, - icount_bench_hypot_group, - icount_bench_hypotf_group, - icount_bench_ilogb_group, - icount_bench_ilogbf128_group, - icount_bench_ilogbf16_group, - icount_bench_ilogbf_group, - icount_bench_j0_group, - icount_bench_j0f_group, - icount_bench_j1_group, - icount_bench_j1f_group, - icount_bench_jn_group, - icount_bench_jnf_group, - icount_bench_ldexp_group, - icount_bench_ldexpf128_group, - icount_bench_ldexpf16_group, - icount_bench_ldexpf_group, - icount_bench_lgamma_group, - icount_bench_lgamma_r_group, - icount_bench_lgammaf_group, - icount_bench_lgammaf_r_group, - icount_bench_log10_group, - icount_bench_log10f_group, - icount_bench_log1p_group, - icount_bench_log1pf_group, - icount_bench_log2_group, - icount_bench_log2f_group, - icount_bench_log_group, - icount_bench_logf_group, - icount_bench_modf_group, - icount_bench_modff_group, - icount_bench_nextafter_group, - icount_bench_nextafterf_group, - icount_bench_pow_group, - icount_bench_powf_group, - icount_bench_remainder_group, - icount_bench_remainderf_group, - icount_bench_remquo_group, - icount_bench_remquof_group, - icount_bench_rint_group, - icount_bench_rintf128_group, - icount_bench_rintf16_group, - icount_bench_rintf_group, - icount_bench_round_group, - icount_bench_roundeven_group, - icount_bench_roundevenf128_group, - icount_bench_roundevenf16_group, - icount_bench_roundevenf_group, - icount_bench_roundf128_group, - icount_bench_roundf16_group, - icount_bench_roundf_group, - icount_bench_scalbn_group, - icount_bench_scalbnf128_group, - icount_bench_scalbnf16_group, - icount_bench_scalbnf_group, - icount_bench_sin_group, - icount_bench_sincos_group, - icount_bench_sincosf_group, - icount_bench_sinf_group, - icount_bench_sinh_group, - icount_bench_sinhf_group, - icount_bench_sqrt_group, - icount_bench_sqrtf128_group, - icount_bench_sqrtf16_group, - icount_bench_sqrtf_group, - icount_bench_tan_group, - icount_bench_tanf_group, - icount_bench_tanh_group, - icount_bench_tanhf_group, - icount_bench_tgamma_group, - icount_bench_tgammaf_group, - icount_bench_trunc_group, - icount_bench_truncf128_group, - icount_bench_truncf16_group, - icount_bench_truncf_group, - icount_bench_y0_group, - icount_bench_y0f_group, - icount_bench_y1_group, - icount_bench_y1f_group, - icount_bench_yn_group, - icount_bench_ynf_group, - // verify-sorted-end - // verify-apilist-end + library_benchmark_groups = [ + // Benchmarks not related to public libm math + icount_bench_u128_group, + icount_bench_hf_parse_group, + icount_bench_hf_print_group, + icount_bench_math_group, + ] ); diff --git a/compiler-builtins/libm-test/benches/random.rs b/compiler-builtins/libm-test/benches/random.rs index 1b17f049ecac2..ae4c2f51bdec5 100644 --- a/compiler-builtins/libm-test/benches/random.rs +++ b/compiler-builtins/libm-test/benches/random.rs @@ -69,7 +69,7 @@ where use anyhow::Context; use libm_test::CheckOutput; - if cfg!(x86_no_sse) && musl_extra.skip_on_i586 { + if cfg!(x86_no_sse2) && musl_extra.skip_on_i586 { break; } @@ -137,7 +137,8 @@ libm_macros::for_each_function! { | roundeven | roundevenf | ALL_F16 - | ALL_F128 => (false, None), + | ALL_F128 + | ALL_BUILTINS => (false, None), // By default we never skip (false) and always have a musl function available _ => (false, Some(musl_math_sys::MACRO_FN_NAME)) diff --git a/compiler-builtins/libm-test/build.rs b/compiler-builtins/libm-test/build.rs index 510ba842f10ab..fa7db8ed63e3e 100644 --- a/compiler-builtins/libm-test/build.rs +++ b/compiler-builtins/libm-test/build.rs @@ -1,9 +1,10 @@ #[path = "../libm/configure.rs"] mod configure; -use configure::Config; + +use configure::{Config, Library}; fn main() { println!("cargo:rerun-if-changed=../libm/configure.rs"); - let cfg = Config::from_env(); - configure::emit_test_config(&cfg); + let cfg = Config::from_env(Library::LibmTest); + configure::emit(&cfg); } diff --git a/compiler-builtins/libm-test/examples/plot_domains.rs b/compiler-builtins/libm-test/examples/plot_domains.rs index 7331d454f2111..b2fd1979ad550 100644 --- a/compiler-builtins/libm-test/examples/plot_domains.rs +++ b/compiler-builtins/libm-test/examples/plot_domains.rs @@ -52,7 +52,7 @@ fn main() { /// Run multiple generators for a single operator. fn plot_one_operator(out_dir: &Path, config: &mut String) where - Op: MathOp, + Op: MathOp, Op::RustArgs: SpacedInput, { let mut ctx = CheckCtx::new(Op::IDENTIFIER, CheckBasis::Mpfr, GeneratorKind::Spaced); diff --git a/compiler-builtins/libm-test/src/builtins_wrapper.rs b/compiler-builtins/libm-test/src/builtins_wrapper.rs new file mode 100644 index 0000000000000..ce517148b9ca3 --- /dev/null +++ b/compiler-builtins/libm-test/src/builtins_wrapper.rs @@ -0,0 +1,310 @@ +//! Wrappers around compiler-builtins functions. +//! +//! Functions from compiler-builtins have a different naming scheme from libm and often a different +//! ABI (doesn't work with libm-test traits because that changes the type signature). Wrap these +//! to make them a bit more similar to the rest of the libm functions. + +macro_rules! cb_op { + // Fully generic version + ($mod:ident, $cb_name:ident, $new_name:ident, ($($arg:ident: $ArgTy:ty),*) -> $RetTy:ty) => { + pub fn $new_name($($arg: $ArgTy),*) -> $RetTy { + compiler_builtins::float::$mod::$cb_name($($arg),*) + } + }; + (@int $mod:ident, $cb_name:ident, $new_name:ident, ($($arg:ident: $ArgTy:ty),*) -> $RetTy:ty) => { + pub fn $new_name($($arg: $ArgTy),*) -> $RetTy { + compiler_builtins::int::$mod::$cb_name($($arg),*) + } + }; + + // Common signatures + (@binop $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + cb_op!($mod, $cb_name, $new_name, (a: $ty, b: $ty) -> $ty); + }; + + // Cmp signatures. See the documentation in cmp.rs regarding the result. + (@cmp_eq $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) == 0 + } + }; + (@cmp_ne $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) != 0 + } + }; + (@cmp_unord $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) != 0 + } + }; + (@cmp_lt $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) < 0 + } + }; + (@cmp_le $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) <= 0 + } + }; + (@cmp_gt $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) > 0 + } + }; + (@cmp_ge $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> bool { + compiler_builtins::float::$mod::$cb_name(a, b) >= 0 + } + }; + (@int_binop_oflow $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> ($ty, bool) { + let mut oflow = 0; + let res = compiler_builtins::int::$mod::$cb_name(a, b, &mut oflow); + (res, oflow != 0) + } + }; + + // Make division by 0 well-defined so testing is easier. + (@int_div $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> $ty { + if b == 0 { + return <$ty>::MIN; + } + compiler_builtins::int::$mod::$cb_name(a, b) + } + }; + (@int_divmod $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> ($ty, $ty) { + if b == 0 { + return (<$ty>::MIN, <$ty>::MIN); + } + let mut rem = 0; + let div = compiler_builtins::int::$mod::$cb_name(a, b, &mut rem); + (div, rem) + } + }; + (@int_udivmod $ty:ty, $mod:ident, $cb_name:ident, $new_name:ident) => { + pub fn $new_name(a: $ty, b: $ty) -> ($ty, $ty) { + if b == 0 { + return (<$ty>::MIN, <$ty>::MIN); + } + let mut rem = 0; + let div = compiler_builtins::int::$mod::$cb_name(a, b, Some(&mut rem)); + (div, rem) + } + }; +} + +#[cfg(f16_enabled)] +cb_op!(@binop f16, add, __addhf3, addf16); +cb_op!(@binop f32, add, __addsf3, addf32); +cb_op!(@binop f64, add, __adddf3, addf64); +#[cfg(f128_enabled)] +cb_op!(@binop f128, add, __addtf3, addf128); + +#[cfg(f16_enabled)] +cb_op!(@binop f16, sub, __subhf3, subf16); +cb_op!(@binop f32, sub, __subsf3, subf32); +cb_op!(@binop f64, sub, __subdf3, subf64); +#[cfg(f128_enabled)] +cb_op!(@binop f128, sub, __subtf3, subf128); + +#[cfg(f16_enabled)] +cb_op!(@binop f16, mul, __mulhf3, mulf16); +cb_op!(@binop f32, mul, __mulsf3, mulf32); +cb_op!(@binop f64, mul, __muldf3, mulf64); +#[cfg(f128_enabled)] +cb_op!(@binop f128, mul, __multf3, mulf128); + +cb_op!(@binop f32, div, __divsf3, divf32); +cb_op!(@binop f64, div, __divdf3, divf64); +#[cfg(f128_enabled)] +cb_op!(@binop f128, div, __divtf3, divf128); + +cb_op!(pow, __powisf2, powif32, (a: f32, b: i32) -> f32); +cb_op!(pow, __powidf2, powif64, (a: f64, b: i32) -> f64); +#[cfg(f128_enabled)] +cb_op!(pow, __powitf2, powif128, (a: f128, b: i32) -> f128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_eq f16, cmp, __eqhf2, eqf16); +cb_op!(@cmp_eq f32, cmp, __eqsf2, eqf32); +cb_op!(@cmp_eq f64, cmp, __eqdf2, eqf64); +#[cfg(f128_enabled)] +cb_op!(@cmp_eq f128, cmp, __eqtf2, eqf128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_gt f16, cmp, __gthf2, gtf16); +cb_op!(@cmp_gt f32, cmp, __gtsf2, gtf32); +cb_op!(@cmp_gt f64, cmp, __gtdf2, gtf64); +#[cfg(f128_enabled)] +cb_op!(@cmp_gt f128, cmp, __gttf2, gtf128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_ge f16, cmp, __gehf2, gef16); +cb_op!(@cmp_ge f32, cmp, __gesf2, gef32); +cb_op!(@cmp_ge f64, cmp, __gedf2, gef64); +#[cfg(f128_enabled)] +cb_op!(@cmp_ge f128, cmp, __getf2, gef128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_lt f16, cmp, __lthf2, ltf16); +cb_op!(@cmp_lt f32, cmp, __ltsf2, ltf32); +cb_op!(@cmp_lt f64, cmp, __ltdf2, ltf64); +#[cfg(f128_enabled)] +cb_op!(@cmp_lt f128, cmp, __lttf2, ltf128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_le f16, cmp, __lehf2, lef16); +cb_op!(@cmp_le f32, cmp, __lesf2, lef32); +cb_op!(@cmp_le f64, cmp, __ledf2, lef64); +#[cfg(f128_enabled)] +cb_op!(@cmp_le f128, cmp, __letf2, lef128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_ne f16, cmp, __nehf2, nef16); +cb_op!(@cmp_ne f32, cmp, __nesf2, nef32); +cb_op!(@cmp_ne f64, cmp, __nedf2, nef64); +#[cfg(f128_enabled)] +cb_op!(@cmp_ne f128, cmp, __netf2, nef128); + +#[cfg(f16_enabled)] +cb_op!(@cmp_unord f16, cmp, __unordhf2, unordf16); +cb_op!(@cmp_unord f32, cmp, __unordsf2, unordf32); +cb_op!(@cmp_unord f64, cmp, __unorddf2, unordf64); +#[cfg(f128_enabled)] +cb_op!(@cmp_unord f128, cmp, __unordtf2, unordf128); + +#[cfg(f16_enabled)] +cb_op!(extend, __extendhfsf2, extend_f16_f32, (a: f16) -> f32); +#[cfg(f16_enabled)] +cb_op!(extend, __extendhfdf2, extend_f16_f64, (a: f16) -> f64); +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +cb_op!(extend, __extendhftf2, extend_f16_f128, (a: f16) -> f128); +cb_op!(extend, __extendsfdf2, extend_f32_f64, (a: f32) -> f64); +#[cfg(f128_enabled)] +cb_op!(extend, __extendsftf2, extend_f32_f128, (a: f32) -> f128); +#[cfg(f128_enabled)] +cb_op!(extend, __extenddftf2, extend_f64_f128, (a: f64) -> f128); + +// Note that these are renamed from trunc to narrow to avoid collision with libm `trunc`. +#[cfg(f16_enabled)] +cb_op!(trunc, __truncsfhf2, narrow_f32_f16, (a: f32) -> f16); +#[cfg(f16_enabled)] +cb_op!(trunc, __truncdfhf2, narrow_f64_f16, (a: f64) -> f16); +cb_op!(trunc, __truncdfsf2, narrow_f64_f32, (a: f64) -> f32); +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +cb_op!(trunc, __trunctfhf2, narrow_f128_f16, (a: f128) -> f16); +#[cfg(f128_enabled)] +cb_op!(trunc, __trunctfsf2, narrow_f128_f32, (a: f128) -> f32); +#[cfg(f128_enabled)] +cb_op!(trunc, __trunctfdf2, narrow_f128_f64, (a: f128) -> f64); + +cb_op!(conv, __fixsfsi, ftoi_f32_i32, (a: f32) -> i32); +cb_op!(conv, __fixsfdi, ftoi_f32_i64, (a: f32) -> i64); +cb_op!(conv, __fixsfti, ftoi_f32_i128, (a: f32) -> i128); +cb_op!(conv, __fixdfsi, ftoi_f64_i32, (a: f64) -> i32); +cb_op!(conv, __fixdfdi, ftoi_f64_i64, (a: f64) -> i64); +cb_op!(conv, __fixdfti, ftoi_f64_i128, (a: f64) -> i128); +#[cfg(f128_enabled)] +cb_op!(conv, __fixtfsi, ftoi_f128_i32, (a: f128) -> i32); +#[cfg(f128_enabled)] +cb_op!(conv, __fixtfdi, ftoi_f128_i64, (a: f128) -> i64); +#[cfg(f128_enabled)] +cb_op!(conv, __fixtfti, ftoi_f128_i128, (a: f128) -> i128); +cb_op!(conv, __fixunssfsi, ftoi_f32_u32, (a: f32) -> u32); +cb_op!(conv, __fixunssfdi, ftoi_f32_u64, (a: f32) -> u64); +cb_op!(conv, __fixunssfti, ftoi_f32_u128, (a: f32) -> u128); +cb_op!(conv, __fixunsdfsi, ftoi_f64_u32, (a: f64) -> u32); +cb_op!(conv, __fixunsdfdi, ftoi_f64_u64, (a: f64) -> u64); +cb_op!(conv, __fixunsdfti, ftoi_f64_u128, (a: f64) -> u128); +#[cfg(f128_enabled)] +cb_op!(conv, __fixunstfsi, ftoi_f128_u32, (a: f128) -> u32); +#[cfg(f128_enabled)] +cb_op!(conv, __fixunstfdi, ftoi_f128_u64, (a: f128) -> u64); +#[cfg(f128_enabled)] +cb_op!(conv, __fixunstfti, ftoi_f128_u128, (a: f128) -> u128); + +cb_op!(conv, __floatsisf, itof_i32_f32, (a: i32) -> f32); +cb_op!(conv, __floatdisf, itof_i64_f32, (a: i64) -> f32); +cb_op!(conv, __floattisf, itof_i128_f32, (a: i128) -> f32); +cb_op!(conv, __floatsidf, itof_i32_f64, (a: i32) -> f64); +cb_op!(conv, __floatdidf, itof_i64_f64, (a: i64) -> f64); +cb_op!(conv, __floattidf, itof_i128_f64, (a: i128) -> f64); +#[cfg(f128_enabled)] +cb_op!(conv, __floatsitf, itof_i32_f128, (a: i32) -> f128); +#[cfg(f128_enabled)] +cb_op!(conv, __floatditf, itof_i64_f128, (a: i64) -> f128); +#[cfg(f128_enabled)] +cb_op!(conv, __floattitf, itof_i128_f128, (a: i128) -> f128); +cb_op!(conv, __floatunsisf, itof_u32_f32, (a: u32) -> f32); +cb_op!(conv, __floatundisf, itof_u64_f32, (a: u64) -> f32); +cb_op!(conv, __floatuntisf, itof_u128_f32, (a: u128) -> f32); +cb_op!(conv, __floatunsidf, itof_u32_f64, (a: u32) -> f64); +cb_op!(conv, __floatundidf, itof_u64_f64, (a: u64) -> f64); +cb_op!(conv, __floatuntidf, itof_u128_f64, (a: u128) -> f64); +#[cfg(f128_enabled)] +cb_op!(conv, __floatunsitf, itof_u32_f128, (a: u32) -> f128); +#[cfg(f128_enabled)] +cb_op!(conv, __floatunditf, itof_u64_f128, (a: u64) -> f128); +#[cfg(f128_enabled)] +cb_op!(conv, __floatuntitf, itof_u128_f128, (a: u128) -> f128); + +/* int ops */ + +cb_op!(@int addsub, __rust_i128_add, iadd_i128, (a: i128, b: i128) -> i128); +cb_op!(@int addsub, __rust_i128_sub, isub_i128, (a: i128, b: i128) -> i128); +cb_op!(@int addsub, __rust_u128_add, iadd_u128, (a: u128, b: u128) -> u128); +cb_op!(@int addsub, __rust_u128_sub, isub_u128, (a: u128, b: u128) -> u128); +cb_op!(@int_binop_oflow i128, addsub, __rust_i128_addo, iaddo_i128); +cb_op!(@int_binop_oflow i128, addsub, __rust_i128_subo, isubo_i128); +cb_op!(@int_binop_oflow u128, addsub, __rust_u128_addo, iaddo_u128); +cb_op!(@int_binop_oflow u128, addsub, __rust_u128_subo, isubo_u128); + +cb_op!(@int mul, __muldi3, imul_u64, (a: u64, b: u64) -> u64); +cb_op!(@int mul, __multi3, imul_i128, (a: i128, b: i128) -> i128); +cb_op!(@int_binop_oflow i32, mul, __mulosi4, imulo_i32); +cb_op!(@int_binop_oflow i64, mul, __mulodi4, imulo_i64); +cb_op!(@int_binop_oflow i128, mul, __muloti4, imulo_i128); +cb_op!(@int_binop_oflow u128, mul, __rust_u128_mulo, imulo_u128); + +cb_op!(@int_div i32, sdiv, __divsi3, idiv_i32); +cb_op!(@int_div i64, sdiv, __divdi3, idiv_i64); +cb_op!(@int_div i128, sdiv, __divti3, idiv_i128); +cb_op!(@int_div i32, sdiv, __modsi3, imod_i32); +cb_op!(@int_div i64, sdiv, __moddi3, imod_i64); +cb_op!(@int_div i128, sdiv, __modti3, imod_i128); +cb_op!(@int_divmod i32, sdiv, __divmodsi4, idivmod_i32); +cb_op!(@int_divmod i64, sdiv, __divmoddi4, idivmod_i64); +cb_op!(@int_divmod i128, sdiv, __divmodti4, idivmod_i128); + +cb_op!(@int_div u32, udiv, __udivsi3, idiv_u32); +cb_op!(@int_div u64, udiv, __udivdi3, idiv_u64); +cb_op!(@int_div u128, udiv, __udivti3, idiv_u128); +cb_op!(@int_div u32, udiv, __umodsi3, imod_u32); +cb_op!(@int_div u64, udiv, __umoddi3, imod_u64); +cb_op!(@int_div u128, udiv, __umodti3, imod_u128); +cb_op!(@int_udivmod u32, udiv, __udivmodsi4, idivmod_u32); +cb_op!(@int_udivmod u64, udiv, __udivmoddi4, idivmod_u64); +cb_op!(@int_udivmod u128, udiv, __udivmodti4, idivmod_u128); + +cb_op!(@int shift, __ashlsi3, ashl_u32, (a: u32, b: u32) -> u32); +cb_op!(@int shift, __ashldi3, ashl_u64, (a: u64, b: u32) -> u64); +cb_op!(@int shift, __ashlti3, ashl_u128, (a: u128, b: u32) -> u128); +cb_op!(@int shift, __ashrsi3, ashr_i32, (a: i32, b: u32) -> i32); +cb_op!(@int shift, __ashrdi3, ashr_i64, (a: i64, b: u32) -> i64); +cb_op!(@int shift, __ashrti3, ashr_i128, (a: i128, b: u32) -> i128); +cb_op!(@int shift, __lshrsi3, lshr_u32, (a: u32, b: u32) -> u32); +cb_op!(@int shift, __lshrdi3, lshr_u64, (a: u64, b: u32) -> u64); +cb_op!(@int shift, __lshrti3, lshr_u128, (a: u128, b: u32) -> u128); + +cb_op!(@int leading_zeros, __clzsi2, leading_zeros_u32, (a: u32) -> usize); +cb_op!(@int leading_zeros, __clzdi2, leading_zeros_u64, (a: u64) -> usize); +cb_op!(@int leading_zeros, __clzti2, leading_zeros_u128, (a: u128) -> usize); +cb_op!(@int trailing_zeros, __ctzsi2, trailing_zeros_u32, (a: u32) -> usize); +cb_op!(@int trailing_zeros, __ctzdi2, trailing_zeros_u64, (a: u64) -> usize); +cb_op!(@int trailing_zeros, __ctzti2, trailing_zeros_u128, (a: u128) -> usize); diff --git a/compiler-builtins/libm-test/src/domain.rs b/compiler-builtins/libm-test/src/domain.rs index eb009bfa093f4..0ae105f4a02d2 100644 --- a/compiler-builtins/libm-test/src/domain.rs +++ b/compiler-builtins/libm-test/src/domain.rs @@ -224,6 +224,47 @@ pub fn get_domain( argnum: usize, ) -> EitherPrim, Domain> { let x = match id.base_name() { + // Basic arithmetic + BaseName::Add => &EitherPrim::UNBOUNDED2[..], + BaseName::Sub => &EitherPrim::UNBOUNDED2[..], + BaseName::Mul => &EitherPrim::UNBOUNDED2[..], + BaseName::Div => &EitherPrim::UNBOUNDED2[..], + BaseName::Powi => &EitherPrim::UNBOUNDED2[..], + + // Comparison + BaseName::Eq => &EitherPrim::UNBOUNDED2[..], + BaseName::Ne => &EitherPrim::UNBOUNDED2[..], + BaseName::Gt => &EitherPrim::UNBOUNDED2[..], + BaseName::Ge => &EitherPrim::UNBOUNDED2[..], + BaseName::Lt => &EitherPrim::UNBOUNDED2[..], + BaseName::Le => &EitherPrim::UNBOUNDED2[..], + BaseName::Unord => &EitherPrim::UNBOUNDED2[..], + + // Conversions + BaseName::Extend => &EitherPrim::UNBOUNDED1[..], + BaseName::Narrow => &EitherPrim::UNBOUNDED1[..], + BaseName::Ftoi => &EitherPrim::UNBOUNDED1[..], + BaseName::Itof => &EitherPrim::UNBOUNDED1[..], + + // Integer ops + BaseName::Iadd => &EitherPrim::UNBOUNDED2[..], + BaseName::Iaddo => &EitherPrim::UNBOUNDED2[..], + BaseName::Isub => &EitherPrim::UNBOUNDED2[..], + BaseName::Isubo => &EitherPrim::UNBOUNDED2[..], + BaseName::Imul => &EitherPrim::UNBOUNDED2[..], + BaseName::Imulo => &EitherPrim::UNBOUNDED2[..], + BaseName::Idiv => &EitherPrim::UNBOUNDED2[..], + BaseName::Imod => &EitherPrim::UNBOUNDED2[..], + BaseName::Idivmod => &EitherPrim::UNBOUNDED2[..], + // Shifts technically aren't unbounded, but its range is restricted elsewhere in + // our test generators. + BaseName::Ashl => &EitherPrim::UNBOUNDED2[..], + BaseName::Ashr => &EitherPrim::UNBOUNDED2[..], + BaseName::Lshr => &EitherPrim::UNBOUNDED2[..], + BaseName::LeadingZeros => &EitherPrim::UNBOUNDED1[..], + BaseName::TrailingZeros => &EitherPrim::UNBOUNDED1[..], + + // Math functions BaseName::Acos => &EitherPrim::INVERSE_TRIG_PERIODIC[..], BaseName::Acosh => &EitherPrim::ACOSH[..], BaseName::Asin => &EitherPrim::INVERSE_TRIG_PERIODIC[..], diff --git a/compiler-builtins/libm-test/src/f8_impl.rs b/compiler-builtins/libm-test/src/f8_impl.rs index 9f19f518e2a34..fb95e279eedd6 100644 --- a/compiler-builtins/libm-test/src/f8_impl.rs +++ b/compiler-builtins/libm-test/src/f8_impl.rs @@ -36,6 +36,7 @@ impl Float for f8 { const NEG_SNAN: Self = Self(0b1_1111_001); const MIN_POSITIVE_NORMAL: Self = Self(1 << Self::SIG_BITS); + const MIN_POSITIVE_SUBNORMAL: Self = Self(1); // FIXME: incorrect values const EPSILON: Self = Self::ZERO; const PI: Self = Self::ZERO; @@ -58,6 +59,14 @@ impl Float for f8 { self.0 as i8 } + fn eq_repr(self, rhs: Self) -> bool { + if self.is_nan() && rhs.is_nan() { + true + } else { + self.to_bits() == rhs.to_bits() + } + } + fn is_nan(self) -> bool { self.0 & Self::EXP_MASK == Self::EXP_MASK && self.0 & Self::SIG_MASK != 0 } diff --git a/compiler-builtins/libm-test/src/generate.rs b/compiler-builtins/libm-test/src/generate.rs index da080d23fa79c..7118752f4f0bb 100644 --- a/compiler-builtins/libm-test/src/generate.rs +++ b/compiler-builtins/libm-test/src/generate.rs @@ -48,3 +48,28 @@ impl Iterator for KnownSize { } impl ExactSizeIterator for KnownSize {} + +/// Yield `(a0, b0), ..., (a0, bn), ..., (an, bn)` for iterators `[a0, ..., an]` and +/// `[b0, ..., bn]`. +fn product2(i0: I0, i1: I1) -> impl Iterator +where + I0: Iterator, + I1: Iterator + Clone, +{ + i0.flat_map(move |first| i1.clone().map(move |second| (first, second))) +} + +/// Yield `(a0, b0, c0), ..., (a0, b0, cn), ..., (a0, bn, cn), ..., (an, bn, cn)` for iterators +/// `[a0, ..., an]`, `[b0, ..., bn]` and `[c0, ..., cn]`. +fn product3( + i0: I0, + i1: I1, + i2: I2, +) -> impl Iterator +where + I0: Iterator, + I1: Iterator + Clone, + I2: Iterator + Clone, +{ + product2(product2(i0, i1), i2).map(|((first, second), third)| (first, second, third)) +} diff --git a/compiler-builtins/libm-test/src/generate/case_list.rs b/compiler-builtins/libm-test/src/generate/case_list.rs index 66d7f6a282f6b..2275787307d95 100644 --- a/compiler-builtins/libm-test/src/generate/case_list.rs +++ b/compiler-builtins/libm-test/src/generate/case_list.rs @@ -6,9 +6,11 @@ //! //! This is useful for adding regression tests or expected failures. -use libm::hf64; +#[cfg(f16_enabled)] +use libm::hf16; #[cfg(f128_enabled)] use libm::hf128; +use libm::{hf32, hf64}; use crate::{CheckBasis, CheckCtx, GeneratorKind, MathOp, op}; @@ -18,834 +20,1625 @@ pub struct TestCase { } impl TestCase { - #[expect(dead_code)] - fn append_inputs(v: &mut Vec, l: &[Op::RustArgs]) { - v.extend(l.iter().copied().map(|input| Self { - input, - output: None, - })); - } - - fn append_pairs(v: &mut Vec, l: &[(Op::RustArgs, Option)]) + /// Turn into a different operation with the same types. + fn cast(self) -> TestCase where - Op::RustRet: Copy, + Op2::RustArgs: From, + Op2::RustRet: From, { - v.extend( - l.iter() - .copied() - .map(|(input, output)| Self { input, output }), - ); + TestCase { + input: self.input.into(), + output: self.output.map(Into::into), + } } } +macro_rules! cases { + ( + $( + $(#[$($meta:tt)*])* + ($($tt:tt)*) + ),* $(,)? + ) => {{ + Vec::from_iter([ + $( + $(#[$($meta)*])* + cases!(@single $($tt)*), + )* + ]) + }}; + + // Variant without a result, which will check against MPFR. + (@single ($($arg:expr),* $(,)?), None $(,)?) => { + TestCase{ + input: ($($arg,)*), + output: None, + } + }; + + // Variant for when the result is specified. + (@single ($($arg:expr),* $(,)?), $res:expr $(,)?) => { + TestCase{ + input: ($($arg,)*), + output: Some($res), + } + }; +} + +/******************************** + * compiler-builtins test cases * + ********************************/ + +#[cfg(f16_enabled)] +fn addf16_cases() -> Vec> { + cases![] +} + +fn addf32_cases() -> Vec> { + cases![] +} + +fn addf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn addf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn subf16_cases() -> Vec> { + cases![] +} + +fn subf32_cases() -> Vec> { + cases![] +} + +fn subf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn subf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn mulf16_cases() -> Vec> { + cases![] +} + +fn mulf32_cases() -> Vec> { + cases![] +} + +fn mulf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn mulf128_cases() -> Vec> { + cases![] +} + +fn divf32_cases() -> Vec> { + cases![] +} + +fn divf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn divf128_cases() -> Vec> { + cases![] +} + +fn powif32_cases() -> Vec> { + cases![] +} + +fn powif64_cases() -> Vec> { + cases![ + // High error + ((0.9999497584118668, -5858518), 6.823250355352412e127), + ] +} + +#[cfg(f128_enabled)] +fn powif128_cases() -> Vec> { + cases![] +} + +/* comparison */ + +#[cfg(f16_enabled)] +fn eqf16_cases() -> Vec> { + cases![] +} + +fn eqf32_cases() -> Vec> { + cases![] +} + +fn eqf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn eqf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn gtf16_cases() -> Vec> { + cases![] +} + +fn gtf32_cases() -> Vec> { + cases![] +} + +fn gtf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn gtf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn gef16_cases() -> Vec> { + cases![] +} + +fn gef32_cases() -> Vec> { + cases![] +} + +fn gef64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn gef128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn ltf16_cases() -> Vec> { + cases![] +} + +fn ltf32_cases() -> Vec> { + cases![] +} + +fn ltf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ltf128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn lef16_cases() -> Vec> { + cases![] +} + +fn lef32_cases() -> Vec> { + cases![] +} + +fn lef64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn lef128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn nef16_cases() -> Vec> { + cases![] +} + +fn nef32_cases() -> Vec> { + cases![] +} + +fn nef64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn nef128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn unordf16_cases() -> Vec> { + cases![] +} + +fn unordf32_cases() -> Vec> { + cases![] +} + +fn unordf64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn unordf128_cases() -> Vec> { + cases![] +} + +/* conversion */ + +#[cfg(f16_enabled)] +fn extend_f16_f32_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn extend_f16_f64_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +fn extend_f16_f128_cases() -> Vec> { + cases![] +} + +fn extend_f32_f64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn extend_f32_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn extend_f64_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn narrow_f32_f16_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +fn narrow_f64_f16_cases() -> Vec> { + cases![] +} + +fn narrow_f64_f32_cases() -> Vec> { + cases![] +} + +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +fn narrow_f128_f16_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn narrow_f128_f32_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn narrow_f128_f64_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_i32_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_i64_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_i128_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_i32_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_i64_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_i128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_i32_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_i64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_i128_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_u32_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_u64_cases() -> Vec> { + cases![] +} + +fn ftoi_f32_u128_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_u32_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_u64_cases() -> Vec> { + cases![] +} + +fn ftoi_f64_u128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_u32_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_u64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn ftoi_f128_u128_cases() -> Vec> { + cases![] +} + +fn itof_i32_f32_cases() -> Vec> { + cases![] +} + +fn itof_i64_f32_cases() -> Vec> { + cases![] +} + +fn itof_i128_f32_cases() -> Vec> { + cases![] +} + +fn itof_i32_f64_cases() -> Vec> { + cases![] +} + +fn itof_i64_f64_cases() -> Vec> { + cases![] +} + +fn itof_i128_f64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_i32_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_i64_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_i128_f128_cases() -> Vec> { + cases![] +} + +fn itof_u32_f32_cases() -> Vec> { + cases![] +} + +fn itof_u64_f32_cases() -> Vec> { + cases![] +} + +fn itof_u128_f32_cases() -> Vec> { + cases![] +} + +fn itof_u32_f64_cases() -> Vec> { + cases![] +} + +fn itof_u64_f64_cases() -> Vec> { + cases![] +} + +fn itof_u128_f64_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_u32_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_u64_f128_cases() -> Vec> { + cases![] +} + +#[cfg(f128_enabled)] +fn itof_u128_f128_cases() -> Vec> { + cases![] +} + +/* int arithmetic */ + +fn iadd_i128_cases() -> Vec> { + cases![] +} + +fn iadd_u128_cases() -> Vec> { + cases![] +} + +fn iaddo_i128_cases() -> Vec> { + cases![] +} + +fn iaddo_u128_cases() -> Vec> { + cases![] +} + +fn isub_i128_cases() -> Vec> { + cases![] +} + +fn isub_u128_cases() -> Vec> { + cases![] +} + +fn isubo_i128_cases() -> Vec> { + cases![] +} + +fn isubo_u128_cases() -> Vec> { + cases![] +} + +fn idiv_i128_cases() -> Vec> { + cases![] +} + +fn idiv_i32_cases() -> Vec> { + cases![] +} + +fn idiv_i64_cases() -> Vec> { + cases![] +} + +fn idiv_u128_cases() -> Vec> { + cases![] +} + +fn idiv_u32_cases() -> Vec> { + cases![] +} + +fn idiv_u64_cases() -> Vec> { + cases![] +} + +fn idivmod_i128_cases() -> Vec> { + cases![] +} + +fn idivmod_i32_cases() -> Vec> { + cases![] +} + +fn idivmod_i64_cases() -> Vec> { + cases![] +} + +fn idivmod_u128_cases() -> Vec> { + cases![] +} + +fn idivmod_u32_cases() -> Vec> { + cases![] +} + +fn idivmod_u64_cases() -> Vec> { + cases![] +} + +fn imod_i128_cases() -> Vec> { + cases![] +} + +fn imod_i32_cases() -> Vec> { + cases![] +} + +fn imod_i64_cases() -> Vec> { + cases![] +} + +fn imod_u128_cases() -> Vec> { + cases![] +} + +fn imod_u32_cases() -> Vec> { + cases![] +} + +fn imod_u64_cases() -> Vec> { + cases![] +} + +fn imul_i128_cases() -> Vec> { + cases![] +} + +fn imul_u64_cases() -> Vec> { + cases![] +} + +fn imulo_i128_cases() -> Vec> { + cases![] +} + +fn imulo_i32_cases() -> Vec> { + cases![] +} + +fn imulo_i64_cases() -> Vec> { + cases![] +} + +fn imulo_u128_cases() -> Vec> { + cases![] +} + +/* int shifts */ + +fn ashl_u32_cases() -> Vec> { + cases![] +} + +fn ashl_u64_cases() -> Vec> { + cases![] +} + +fn ashl_u128_cases() -> Vec> { + cases![] +} + +fn ashr_i32_cases() -> Vec> { + cases![] +} + +fn ashr_i64_cases() -> Vec> { + cases![] +} + +fn ashr_i128_cases() -> Vec> { + cases![] +} + +fn lshr_u32_cases() -> Vec> { + cases![] +} + +fn lshr_u64_cases() -> Vec> { + cases![] +} + +fn lshr_u128_cases() -> Vec> { + cases![] +} + +/* int bitwise ops */ + +fn leading_zeros_u32_cases() -> Vec> { + cases![] +} + +fn leading_zeros_u64_cases() -> Vec> { + cases![] +} + +fn leading_zeros_u128_cases() -> Vec> { + cases![] +} + +fn trailing_zeros_u32_cases() -> Vec> { + cases![] +} + +fn trailing_zeros_u64_cases() -> Vec> { + cases![] +} + +fn trailing_zeros_u128_cases() -> Vec> { + cases![] +} + +/******************* + * libm test cases * + *******************/ + fn acos_cases() -> Vec> { - vec![] + cases![] } fn acosf_cases() -> Vec> { - vec![] + cases![] } fn acosh_cases() -> Vec> { - vec![] + cases![] } fn acoshf_cases() -> Vec> { - vec![] + cases![] } fn asin_cases() -> Vec> { - vec![] + cases![] } fn asinf_cases() -> Vec> { - vec![] + cases![] } -fn asinh_cases() -> Vec> { - vec![] +fn asinhf_cases() -> Vec> { + cases![ + // Failure on i586 + ((-0.37330312), -0.3651353), + ((-0.421092), -0.40954682), + ] } -fn asinhf_cases() -> Vec> { - vec![] +fn asinh_cases() -> Vec> { + cases![] } fn atan_cases() -> Vec> { - vec![] + cases![] } fn atan2_cases() -> Vec> { - vec![] + cases![] } fn atan2f_cases() -> Vec> { - vec![] + cases![] } fn atanf_cases() -> Vec> { - vec![] + cases![] } fn atanh_cases() -> Vec> { - vec![] + cases![] } fn atanhf_cases() -> Vec> { - vec![] + cases![] } fn cbrt_cases() -> Vec> { - vec![] + cases![] } fn cbrtf_cases() -> Vec> { - vec![] + cases![] } fn ceil_cases() -> Vec> { - vec![] + cases![] } fn ceilf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn ceilf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn ceilf16_cases() -> Vec> { - vec![] + cases![] } fn copysign_cases() -> Vec> { - vec![] + cases![] } fn copysignf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn copysignf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn copysignf16_cases() -> Vec> { - vec![] + cases![] } fn cos_cases() -> Vec> { - vec![] + cases![] } fn cosf_cases() -> Vec> { - vec![] + cases![] } fn cosh_cases() -> Vec> { - vec![] + cases![] } fn coshf_cases() -> Vec> { - vec![] + cases![] } fn erf_cases() -> Vec> { - vec![] + cases![] } fn erfc_cases() -> Vec> { - vec![] + cases![] } fn erfcf_cases() -> Vec> { - vec![] + cases![] } fn erff_cases() -> Vec> { - vec![] + cases![] } fn exp_cases() -> Vec> { - vec![] + cases![] } fn exp10_cases() -> Vec> { - vec![] + cases![] } fn exp10f_cases() -> Vec> { - vec![] + cases![] } fn exp2_cases() -> Vec> { - vec![] + cases![] } fn exp2f_cases() -> Vec> { - vec![] + cases![] } fn expf_cases() -> Vec> { - vec![] + cases![ + ((hf32!("-0x1.2d245ap-8")), hf32!("0x1.fda718p-1")), + ((hf32!("0x1.db1b7ap-7")), hf32!("0x1.03bd22p+0")), + ((hf32!("-0x1.dc15fcp+5")), hf32!("0x1.1ae6e6p-86")), + ] } fn expm1_cases() -> Vec> { - vec![] + cases![] } fn expm1f_cases() -> Vec> { - vec![] + cases![] } fn fabs_cases() -> Vec> { - vec![] + cases![] } fn fabsf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fabsf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fabsf16_cases() -> Vec> { - vec![] + cases![] } fn fdim_cases() -> Vec> { - vec![] + cases![ + // Failures on i586 + ( + ( + hf64!("0x1.10d2f8a8dffd1p+355"), + hf64!("-0x1.5203b17e54a8cp+373") + ), + hf64!("0x1.5203f5b312d2fp+373") + ), + ( + ( + hf64!("0x1.9ffdf64f0d2f8p+294"), + hf64!("-0x1.71addd21280b5p+344") + ), + hf64!("0x1.71addd21280bbp+344") + ), + ( + ( + hf64!("0x1.f3600eb4ad0e0p-953"), + hf64!("-0x1.0c29b2b40023dp-976") + ), + hf64!("0x1.f36010cd00737p-953") + ), + ] } fn fdimf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fdimf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fdimf16_cases() -> Vec> { - vec![] + cases![] } fn floor_cases() -> Vec> { - vec![] + cases![] } fn floorf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn floorf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn floorf16_cases() -> Vec> { - vec![] + cases![] } -fn fma_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Previous failure with incorrect sign - ((5e-324, -5e-324, 0.0), Some(-0.0)), - ], - ); - v +#[cfg(f16_enabled)] +fn fmaf16_cases() -> Vec> { + cases![ + // Subnormal result + ((hf16!("0x1p-11"), hf16!("0x1p-11"), 0.0), None,), + ((hf16!("0x1p-24"), hf16!("0x1p-24"), 0.0), None,), + // Failed during extensive tests + ( + ( + hf16!("-0x1.c4p-12"), + hf16!("0x1.22p-14"), + hf16!("-0x1.f4p-15"), + ), + hf16!("-0x1.f48p-15") + ), + // Examples from https://github.com/llvm/llvm-project/issues/128450 + ( + ( + hf16!("0x1.400p+8"), + hf16!("0x1.008p+7"), + hf16!("0x1.000p-24"), + ), + hf16!("0x1.40cp+15") + ), + ( + (hf16!("0x1.eb8p-12"), hf16!("0x1.9p-11"), hf16!("-0x1p-11"),), + None + ), + // Previous failures during testing + ((-569.0, -4.89, 65470.0), None), + ((-998.0, 0.02596, -998.0), None), + ((6e-8, 6e-8, -6.104e-5), None), + ((6e-8, 65300.0, 9.5e-7), None), + ((-569.0, -4.89, -0.0417), None), + ((6444.0, 0.003443, 0.003443), None), + ((6e-8, 6e-8, 6e-8), None), + ((6e-8, -1.0, 6e-8), None), + ((1.001, 65500.0, 6e-8), None), + ((1.001, 65500.0, 65500.0), None), + ((1.002, 65470.0, 0.0), None), + ((1.002, 65470.0, 65500.0), None), + ((0.0002216, -8.464e-5, 4.4e-5), None), + ((-56700.0, -2.082, -61120.0), None), + ((-475.3, -475.3, 60450.0), None), + ((-61120.0, -3.969, 20320.0), None), + ((6e-8, -6e-8, 0.0), None), + ] } fn fmaf_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Known rounding error for some implementations (notably MinGW) + cases![ + // Known rounding error for some implementations (notably MinGW) + ((-1.9369631e13f32, 2.1513551e-7, -1.7354427e-24), -4167095.8), + // Failure on i586 + ( ( - (-1.9369631e13f32, 2.1513551e-7, -1.7354427e-24), - Some(-4167095.8), + hf32!("-0x1.c92494p+109"), + hf32!("-0x0.000018p-126"), + hf32!("-0x1.6db6f0p-91"), ), - ], - ); - v + hf32!("0x1.56db6ep-36") + ), + ] +} + +fn fma_cases() -> Vec> { + cases![ + // Previous failure with incorrect sign + ((5e-324, -5e-324, 0.0), -0.0), + // Failure on i586 + ( + (0.999999999999999, 1.0000000000000013, 0.0), + 1.0000000000000002 + ), + // Failure on musl i686/i586 + ( + ( + hf64!("0x0.0000000100001p-1022"), + hf64!("0x1.ffffffffffffbp+1023"), + hf64!("0x0p+0") + ), + hf64!("0x1.00000fffffffdp-30") + ) + ] } #[cfg(f128_enabled)] fn fmaf128_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ + cases![ + ( + // Tricky rounding case that previously failed in extensive tests ( - // Tricky rounding case that previously failed in extensive tests - ( - hf128!("-0x1.1966cc01966cc01966cc01966f06p-25"), - hf128!("-0x1.669933fe69933fe69933fe6997c9p-16358"), - hf128!("-0x0.000000000000000000000000048ap-16382"), - ), - Some(hf128!("0x0.c5171470a3ff5e0f68d751491b18p-16382")), + hf128!("-0x1.1966cc01966cc01966cc01966f06p-25"), + hf128!("-0x1.669933fe69933fe69933fe6997c9p-16358"), + hf128!("-0x0.000000000000000000000000048ap-16382"), ), + hf128!("0x0.c5171470a3ff5e0f68d751491b18p-16382") + ), + ( + // Subnormal edge case that caused a failure ( - // Subnormal edge case that caused a failure - ( - hf128!("0x0.7ffffffffffffffffffffffffff7p-16382"), - hf128!("0x1.ffffffffffffffffffffffffffffp-1"), - hf128!("0x0.8000000000000000000000000009p-16382"), - ), - Some(hf128!("0x1.0000000000000000000000000000p-16382")), + hf128!("0x0.7ffffffffffffffffffffffffff7p-16382"), + hf128!("0x1.ffffffffffffffffffffffffffffp-1"), + hf128!("0x0.8000000000000000000000000009p-16382"), ), - ], - ); - v + hf128!("0x1.0000000000000000000000000000p-16382") + ), + ] } #[cfg(f16_enabled)] fn fmaxf16_cases() -> Vec> { - vec![] + cases![] } fn fmaxf_cases() -> Vec> { - vec![] + cases![] } fn fmax_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fmaxf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fmaximumf16_cases() -> Vec> { - vec![] + cases![] } fn fmaximumf_cases() -> Vec> { - vec![] + cases![] } fn fmaximum_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fmaximumf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fmaximum_numf16_cases() -> Vec> { - vec![] + cases![] } fn fmaximum_numf_cases() -> Vec> { - vec![] + cases![] } fn fmaximum_num_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fmaximum_numf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fminf16_cases() -> Vec> { - vec![] + cases![] } fn fminf_cases() -> Vec> { - vec![] + cases![] } fn fmin_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fminf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fminimumf16_cases() -> Vec> { - vec![] + cases![] } fn fminimumf_cases() -> Vec> { - vec![] + cases![] } fn fminimum_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fminimumf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fminimum_numf16_cases() -> Vec> { - vec![] + cases![] } fn fminimum_numf_cases() -> Vec> { - vec![] + cases![] } fn fminimum_num_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn fminimum_numf128_cases() -> Vec> { - vec![] + cases![] } fn fmod_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Previous failure with incorrect loop iteration - // - ((2.1, 3.123e-320), Some(2.0696e-320)), - ((2.1, 2.253547e-318), Some(1.772535e-318)), - ], - ); - v + cases![ + // Previous failure with incorrect loop iteration + // + ((2.1, 3.123e-320), 2.0696e-320), + ((2.1, 2.253547e-318), 1.772535e-318), + ] } fn fmodf_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Previous failure with incorrect loop iteration - // - ((2.1, 8.858e-42), Some(8.085e-42)), - ((2.1, 6.39164e-40), Some(6.1636e-40)), - ((5.5, 6.39164e-40), Some(4.77036e-40)), - ((-151.189, 6.39164e-40), Some(-5.64734e-40)), - ], - ); - v + cases![ + // Previous failure with incorrect loop iteration + // + ((2.1, 8.858e-42), 8.085e-42), + ((2.1, 6.39164e-40), 6.1636e-40), + ((5.5, 6.39164e-40), 4.77036e-40), + ((-151.189, 6.39164e-40), -5.64734e-40), + ] } #[cfg(f128_enabled)] fn fmodf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn fmodf16_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn frexpf16_cases() -> Vec> { - vec![] + cases![] } fn frexpf_cases() -> Vec> { - vec![] + cases![] } fn frexp_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn frexpf128_cases() -> Vec> { - vec![] + cases![] } -fn hypot_cases() -> Vec> { - vec![] +fn hypotf_cases() -> Vec> { + cases![] } -fn hypotf_cases() -> Vec> { - vec![] +fn hypot_cases() -> Vec> { + cases![ + // Cases that can overflow exponent if wrapping arithmetic is not used + ( + ( + hf64!("-0x1.800f800f80100p+1023"), + hf64!("0x1.8354835473720p+996"), + ), + None + ), + ( + (hf64!("0x1.201b201b201c0p+0"), hf64!("0x1.b028b028b02a0p-1")), + None + ), + ( + ( + hf64!("-0x1.e538e538e564p+980"), + hf64!("-0x1.c4dfc4dfc508p+983"), + ), + None + ), + ( + ( + hf64!("-0x1.2f22e4f77aa58p+983"), + hf64!("-0x1.44c9f5524c8ccp+980"), + ), + None + ), + ] } #[cfg(f16_enabled)] fn ilogbf16_cases() -> Vec> { - vec![] + cases![] } fn ilogbf_cases() -> Vec> { - vec![] + cases![] } fn ilogb_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn ilogbf128_cases() -> Vec> { - vec![] + cases![] } fn j0_cases() -> Vec> { - vec![] + cases![] } fn j0f_cases() -> Vec> { - vec![] + cases![] } fn j1_cases() -> Vec> { - vec![] + cases![] } fn j1f_cases() -> Vec> { - vec![] + cases![] } -fn jn_cases() -> Vec> { - vec![] +fn jnf_cases() -> Vec> { + cases![] } -fn jnf_cases() -> Vec> { - vec![] +fn jn_cases() -> Vec> { + cases![ + // Inputs that produce high errors + ((190, 1005.366268038242), 7.328620335959289e-10), + ((238, -311.0349), 7.270196433535006e-8), + ] } fn ldexp_cases() -> Vec> { - vec![] + cases![] } fn ldexpf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn ldexpf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn ldexpf16_cases() -> Vec> { - vec![] + cases![] } fn lgamma_cases() -> Vec> { - vec![] + cases![] } -fn lgamma_r_cases() -> Vec> { - vec![] +fn lgammaf_cases() -> Vec> { + cases![ + // High error + ((-4.933393,), -1.9580022), + ] } -fn lgammaf_cases() -> Vec> { - vec![] +fn lgamma_r_cases() -> Vec> { + cases![] } fn lgammaf_r_cases() -> Vec> { - vec![] + cases![] } fn log_cases() -> Vec> { - vec![] + cases![] } fn log10_cases() -> Vec> { - vec![] + cases![] } fn log10f_cases() -> Vec> { - vec![] + cases![] } -fn log1p_cases() -> Vec> { - vec![] +fn log1pf_cases() -> Vec> { + cases![ + // Musl failures on i586 + ((hf32!("-0x1.8292f6p-2")), hf32!("-0x1.e56918p-2")), + ((hf32!("0x1.12d15ep-1")), hf32!("0x1.b7fbf8p-2")), + ((hf32!("-0x1.904ebep-2")), hf32!("-0x1.fbb6cap-2")), + ] } -fn log1pf_cases() -> Vec> { - vec![] +fn log1p_cases() -> Vec> { + cases![ + // Musl failure on i586 + ( + (hf64!("-0x1.9094dbf7f2e85p-2"),), + hf64!("-0x1.fc29f046c88a1p-2") + ), + ] } fn log2_cases() -> Vec> { - vec![] + cases![] } fn log2f_cases() -> Vec> { - vec![] + cases![] } fn logf_cases() -> Vec> { - vec![] + cases![] } fn modf_cases() -> Vec> { - vec![] + cases![] } fn modff_cases() -> Vec> { - vec![] + cases![] } fn nextafter_cases() -> Vec> { - vec![] + cases![] } fn nextafterf_cases() -> Vec> { - vec![] + cases![] } fn pow_cases() -> Vec> { - vec![] + cases![] } fn powf_cases() -> Vec> { - vec![] + cases![] } fn remainder_cases() -> Vec> { - vec![] + cases![] } fn remainderf_cases() -> Vec> { - vec![] + cases![] } fn remquo_cases() -> Vec> { - vec![] + cases![] } fn remquof_cases() -> Vec> { - vec![] + cases![] } -fn rint_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Known failure on i586 - #[cfg(not(x86_no_sse))] - ( - (hf64!("-0x1.e3f13ff995ffcp+38"),), - Some(hf64!("-0x1.e3f13ff994000p+38")), - ), - #[cfg(x86_no_sse)] - ( - (hf64!("-0x1.e3f13ff995ffcp+38"),), - Some(hf64!("-0x1.e3f13ff998000p+38")), - ), - ], - ); - v +#[cfg(f16_enabled)] +fn rintf16_cases() -> Vec> { + // Out rint doesn't respect rounding modes so it is the same as roundeven + roundevenf16_cases() + .into_iter() + .map(TestCase::cast) + .collect() } fn rintf_cases() -> Vec> { - vec![] + // Out rint doesn't respect rounding modes so it is the same as roundeven + roundevenf_cases().into_iter().map(TestCase::cast).collect() } -#[cfg(f128_enabled)] -fn rintf128_cases() -> Vec> { - vec![] +fn rint_cases() -> Vec> { + // Out rint doesn't respect rounding modes so it is the same as roundeven + roundeven_cases().into_iter().map(TestCase::cast).collect() } -#[cfg(f16_enabled)] -fn rintf16_cases() -> Vec> { - vec![] +#[cfg(f128_enabled)] +fn rintf128_cases() -> Vec> { + // Out rint doesn't respect rounding modes so it is the same as roundeven + roundevenf128_cases() + .into_iter() + .map(TestCase::cast) + .collect() } #[cfg(f16_enabled)] fn roundf16_cases() -> Vec> { - vec![] + cases![] } fn round_cases() -> Vec> { - vec![] + cases![ + // Failure on i586 + ( + (hf64!("0x1.9efc6a203d4a9p+52"),), + hf64!("0x1.9efc6a203d4a9p+52") + ) + ] } fn roundf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn roundf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn roundevenf16_cases() -> Vec> { - vec![] + cases![] } -fn roundeven_cases() -> Vec> { - let mut v = vec![]; - TestCase::append_pairs( - &mut v, - &[ - // Known failure on i586 - #[cfg(not(x86_no_sse))] - ( - (hf64!("-0x1.e3f13ff995ffcp+38"),), - Some(hf64!("-0x1.e3f13ff994000p+38")), - ), - #[cfg(x86_no_sse)] - ( - (hf64!("-0x1.e3f13ff995ffcp+38"),), - Some(hf64!("-0x1.e3f13ff998000p+38")), - ), - ], - ); - v +fn roundevenf_cases() -> Vec> { + cases![] } -fn roundevenf_cases() -> Vec> { - vec![] +fn roundeven_cases() -> Vec> { + cases![ + // Failure on i586 + ((-519629176421.49976,), -519629176421.0), + // Failures with a previous algorithm + ((-849751480.5001163,), -849751481.0), + ((-12493089.499809155,), -12493089.0), + ((-1308.5000830345912,), -1309.0), + ] } #[cfg(f128_enabled)] fn roundevenf128_cases() -> Vec> { - vec![] + cases![] } fn scalbn_cases() -> Vec> { - vec![] + cases![] } fn scalbnf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn scalbnf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn scalbnf16_cases() -> Vec> { - vec![] + cases![] } fn sin_cases() -> Vec> { - vec![] + cases![] } fn sincos_cases() -> Vec> { - vec![] + cases![] } fn sincosf_cases() -> Vec> { - vec![] + cases![] } fn sinf_cases() -> Vec> { - vec![] + cases![] } fn sinh_cases() -> Vec> { - vec![] + cases![] } fn sinhf_cases() -> Vec> { - vec![] + cases![] } fn sqrt_cases() -> Vec> { - vec![] + cases![] } fn sqrtf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn sqrtf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn sqrtf16_cases() -> Vec> { - vec![] + cases![] } -fn tan_cases() -> Vec> { - vec![] +fn tanf_cases() -> Vec> { + cases![] } -fn tanf_cases() -> Vec> { - vec![] +fn tan_cases() -> Vec> { + cases![ + // Musl failures on i586 + ( + (hf64!("0x1.fffffffffffafp+1023"),), + hf64!("0x1.c573c6dd8c00ap+0") + ), + ( + (hf64!("0x1.fffffffffffafp+1023"),), + hf64!("0x1.c573c6dd8c00ap+0") + ), + ( + (hf64!("-0x1.0b10f6eaf2ca0p+883"),), + hf64!("0x1.cefbd167e2402p+0") + ), + ] } fn tanh_cases() -> Vec> { - vec![] + cases![( + (hf64!("0x1.fbfdb8b31b9b4p-3"),), + hf64!("0x1.f1d2bcb4e1b45p-3") + )] } fn tanhf_cases() -> Vec> { - vec![] + cases![ + // Inaccuracy in musl + ((0.24503659,), 0.24024734), + ((0.19125812,), 0.18895969), + ] } fn tgamma_cases() -> Vec> { - vec![] + cases![] } fn tgammaf_cases() -> Vec> { - vec![] + cases![] } fn trunc_cases() -> Vec> { - vec![] + cases![] } fn truncf_cases() -> Vec> { - vec![] + cases![] } #[cfg(f128_enabled)] fn truncf128_cases() -> Vec> { - vec![] + cases![] } #[cfg(f16_enabled)] fn truncf16_cases() -> Vec> { - vec![] + cases![] } fn y0_cases() -> Vec> { - vec![] + cases![] } fn y0f_cases() -> Vec> { - vec![] + cases![] } fn y1_cases() -> Vec> { - vec![] + cases![] } fn y1f_cases() -> Vec> { - vec![] + cases![] } -fn yn_cases() -> Vec> { - vec![] +fn ynf_cases() -> Vec> { + cases![] } -fn ynf_cases() -> Vec> { - vec![] +fn yn_cases() -> Vec> { + cases![ + // Inputs that should be finite but tend to round to infinity + ((228, 120.75621), -3.3293829e38), + ((148, 61.379253), -3.2585946e38), + ((184, 87.26689), -3.2943882e38), + ] } pub trait CaseListInput: MathOp + Sized { diff --git a/compiler-builtins/libm-test/src/generate/edge_cases.rs b/compiler-builtins/libm-test/src/generate/edge_cases.rs index 4e4a782a16988..9ada6d5c95b2d 100644 --- a/compiler-builtins/libm-test/src/generate/edge_cases.rs +++ b/compiler-builtins/libm-test/src/generate/edge_cases.rs @@ -3,10 +3,9 @@ use libm::support::{CastInto, Float, Int, MinInt}; use crate::domain::get_domain; -use crate::generate::KnownSize; -use crate::op::OpITy; +use crate::generate::{KnownSize, product2, product3}; use crate::run_cfg::{check_near_count, check_point_count}; -use crate::{BaseName, CheckCtx, FloatExt, FloatTy, MathOp, test_log}; +use crate::{Arg0, Arg1, Arg2, BaseName, CheckCtx, FloatExt, MathOp, Ty, test_log}; /// Generate a sequence of edge cases, e.g. numbers near zeroes and infiniteis. pub trait EdgeCaseInput { @@ -14,15 +13,12 @@ pub trait EdgeCaseInput { } /// Create a list of values around interesting points (infinities, zeroes, NaNs). -fn float_edge_cases( +fn float_edge_cases( ctx: &CheckCtx, argnum: usize, -) -> (impl Iterator + Clone, u64) -where - Op: MathOp, -{ +) -> (impl Iterator + Clone, u64) { let mut ret = Vec::new(); - let one = OpITy::::ONE; + let one = F::Int::ONE; let values = &mut ret; let domain = get_domain::<_, i8>(ctx.fn_ident, argnum).unwrap_float(); let domain_start = domain.range_start(); @@ -32,17 +28,17 @@ where let near_points = check_near_count(ctx); // Check near some notable constants - count_up(Op::FTy::ONE, near_points, values); - count_up(Op::FTy::ZERO, near_points, values); - count_up(Op::FTy::NEG_ONE, near_points, values); - count_down(Op::FTy::ONE, near_points, values); - count_down(Op::FTy::ZERO, near_points, values); - count_down(Op::FTy::NEG_ONE, near_points, values); - values.push(Op::FTy::NEG_ZERO); + count_up(F::ONE, near_points, values); + count_up(F::ZERO, near_points, values); + count_up(F::NEG_ONE, near_points, values); + count_down(F::ONE, near_points, values); + count_down(F::ZERO, near_points, values); + count_down(F::NEG_ONE, near_points, values); + values.push(F::NEG_ZERO); // Check values near the extremes - count_up(Op::FTy::NEG_INFINITY, near_points, values); - count_down(Op::FTy::INFINITY, near_points, values); + count_up(F::NEG_INFINITY, near_points, values); + count_down(F::INFINITY, near_points, values); count_down(domain_end, near_points, values); count_up(domain_start, near_points, values); count_down(domain_start, near_points, values); @@ -50,20 +46,20 @@ where count_down(domain_end, near_points, values); // Check some special values that aren't included in the above ranges - values.push(Op::FTy::NAN); - values.push(Op::FTy::NEG_NAN); - values.extend(Op::FTy::consts().iter()); + values.push(F::NAN); + values.push(F::NEG_NAN); + values.extend(F::consts().iter()); // Check around the maximum subnormal value - let sub_max = Op::FTy::from_bits(Op::FTy::SIG_MASK); + let sub_max = F::from_bits(F::SIG_MASK); count_up(sub_max, near_points, values); count_down(sub_max, near_points, values); count_up(-sub_max, near_points, values); count_down(-sub_max, near_points, values); // Check a few values around the subnormal range - for shift in (0..Op::FTy::SIG_BITS).step_by(Op::FTy::SIG_BITS as usize / 5) { - let v = Op::FTy::from_bits(one << shift); + for shift in (0..F::SIG_BITS).step_by(F::SIG_BITS as usize / 5) { + let v = F::from_bits(one << shift); count_up(v, 2, values); count_down(v, 2, values); count_up(-v, 2, values); @@ -142,21 +138,22 @@ where if matches!(ctx.base_name, BaseName::Scalbn | BaseName::Ldexp) { assert_eq!(argnum, 1, "scalbn integer argument should be arg1"); - let (emax, emin, emin_sn) = match ctx.fn_ident.math_op().float_ty { - FloatTy::F16 => { + let (emax, emin, emin_sn) = match ctx.fn_ident.math_op().rust_sig.args[0] { + Ty::F16 => { #[cfg(not(f16_enabled))] unreachable!(); #[cfg(f16_enabled)] (f16::EXP_MAX, f16::EXP_MIN, f16::EXP_MIN_SUBNORM) } - FloatTy::F32 => (f32::EXP_MAX, f32::EXP_MIN, f32::EXP_MIN_SUBNORM), - FloatTy::F64 => (f64::EXP_MAX, f64::EXP_MIN, f64::EXP_MIN_SUBNORM), - FloatTy::F128 => { + Ty::F32 => (f32::EXP_MAX, f32::EXP_MIN, f32::EXP_MIN_SUBNORM), + Ty::F64 => (f64::EXP_MAX, f64::EXP_MIN, f64::EXP_MIN_SUBNORM), + Ty::F128 => { #[cfg(not(f128_enabled))] unreachable!(); #[cfg(f128_enabled)] (f128::EXP_MAX, f128::EXP_MIN, f128::EXP_MIN_SUBNORM) } + ty => unreachable!("expected a float first argument, got {ty}"), }; // `scalbn`/`ldexp` have their trickiest behavior around exponent limits @@ -172,6 +169,22 @@ where int_count_around((emin_sn - emax).cast(), near_points, &mut values); } + if matches!( + ctx.base_name, + BaseName::Ashl | BaseName::Ashr | BaseName::Lshr + ) { + // Don't test shift values that are allowed to invoke UB. + let max = match ctx.fn_ident.math_op().rust_sig.args[0] { + Ty::U32 | Ty::I32 => 31, + Ty::U64 | Ty::I64 => 63, + Ty::U128 | Ty::I128 => 127, + ty => panic!("unexpected type {ty}"), + }; + let max: I = max.cast(); + int_count_around(max, near_points, &mut values); + values.retain(|v| *v <= max); + } + values.sort(); values.dedup(); let count = values.len().try_into().unwrap(); @@ -213,10 +226,10 @@ macro_rules! impl_edge_case_input { ($fty:ty) => { impl EdgeCaseInput for ($fty,) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let (iter0, steps0) = float_edge_cases::(ctx, 0); + let (iter0, steps0) = float_edge_cases::>(ctx, 0); let iter0 = iter0.map(|v| (v,)); (iter0, steps0) } @@ -224,37 +237,28 @@ macro_rules! impl_edge_case_input { impl EdgeCaseInput for ($fty, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let (iter0, steps0) = float_edge_cases::(ctx, 0); - let (iter1, steps1) = float_edge_cases::(ctx, 1); - let iter = - iter0.flat_map(move |first| iter1.clone().map(move |second| (first, second))); - let count = steps0.checked_mul(steps1).unwrap(); + let (iter0, steps0) = float_edge_cases::>(ctx, 0); + let (iter1, steps1) = float_edge_cases::>(ctx, 1); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); (iter, count) } } impl EdgeCaseInput for ($fty, $fty, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let (iter0, steps0) = float_edge_cases::(ctx, 0); - let (iter1, steps1) = float_edge_cases::(ctx, 1); - let (iter2, steps2) = float_edge_cases::(ctx, 2); - - let iter = iter0 - .flat_map(move |first| iter1.clone().map(move |second| (first, second))) - .flat_map(move |(first, second)| { - iter2.clone().map(move |third| (first, second, third)) - }); - let count = steps0 - .checked_mul(steps1) - .unwrap() - .checked_mul(steps2) - .unwrap(); + let (iter0, steps0) = float_edge_cases::>(ctx, 0); + let (iter1, steps1) = float_edge_cases::>(ctx, 1); + let (iter2, steps2) = float_edge_cases::>(ctx, 2); + + let iter = product3(iter0, iter1, iter2); + let count = steps0.strict_mul(steps1).strict_mul(steps2); (iter, count) } @@ -262,15 +266,14 @@ macro_rules! impl_edge_case_input { impl EdgeCaseInput for (i32, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let (iter0, steps0) = int_edge_cases(ctx, 0); - let (iter1, steps1) = float_edge_cases::(ctx, 1); + let (iter1, steps1) = float_edge_cases::>(ctx, 1); - let iter = - iter0.flat_map(move |first| iter1.clone().map(move |second| (first, second))); - let count = steps0.checked_mul(steps1).unwrap(); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); (iter, count) } @@ -278,15 +281,14 @@ macro_rules! impl_edge_case_input { impl EdgeCaseInput for ($fty, i32) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let (iter0, steps0) = float_edge_cases::(ctx, 0); + let (iter0, steps0) = float_edge_cases::>(ctx, 0); let (iter1, steps1) = int_edge_cases(ctx, 1); - let iter = - iter0.flat_map(move |first| iter1.clone().map(move |second| (first, second))); - let count = steps0.checked_mul(steps1).unwrap(); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); (iter, count) } @@ -301,6 +303,57 @@ impl_edge_case_input!(f64); #[cfg(f128_enabled)] impl_edge_case_input!(f128); +macro_rules! impl_edge_case_input_int { + (@skip_u32 $ity:ty) => { + impl EdgeCaseInput for ($ity,) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let (iter0, steps0) = int_edge_cases(ctx, 0); + let iter0 = iter0.map(|v| (v,)); + (iter0, steps0) + } + } + + impl EdgeCaseInput for ($ity, $ity) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let (iter0, steps0) = int_edge_cases(ctx, 0); + let (iter1, steps1) = int_edge_cases(ctx, 1); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + (iter, count) + } + } + }; + ($ity:ty) => { + impl_edge_case_input_int!(@skip_u32 $ity); + + impl EdgeCaseInput for ($ity, u32) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let (iter0, steps0) = int_edge_cases(ctx, 0); + let (iter1, steps1) = int_edge_cases(ctx, 1); + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + (iter, count) + } + } + }; +} + +impl_edge_case_input_int!(i32); +impl_edge_case_input_int!(i64); +impl_edge_case_input_int!(i128); +impl_edge_case_input_int!(@skip_u32 u32); +impl_edge_case_input_int!(u64); +impl_edge_case_input_int!(u128); + pub fn get_test_cases( ctx: &CheckCtx, ) -> (impl Iterator + Send + use<'_, Op>, u64) diff --git a/compiler-builtins/libm-test/src/generate/random.rs b/compiler-builtins/libm-test/src/generate/random.rs index 09a3766c66780..32bd2f24ee044 100644 --- a/compiler-builtins/libm-test/src/generate/random.rs +++ b/compiler-builtins/libm-test/src/generate/random.rs @@ -2,14 +2,16 @@ use std::env; use std::ops::RangeInclusive; use std::sync::LazyLock; -use libm::support::Float; +use libm::support::{Float, Int}; +use rand::distr::uniform::SampleUniform; use rand::distr::{Alphanumeric, StandardUniform}; use rand::prelude::Distribution; use rand::{RngExt, SeedableRng}; use rand_chacha::ChaCha8Rng; -use super::KnownSize; use crate::CheckCtx; +use crate::generate::{KnownSize, product2, product3}; +use crate::num::full_range; use crate::run_cfg::{int_range, iteration_count}; pub(crate) const SEED_ENV: &str = "LIBM_SEED"; @@ -31,7 +33,7 @@ pub trait RandomInput: Sized { } /// Generate a sequence of deterministically random floats. -fn random_floats(count: u64) -> impl Iterator +fn random_floats(count: u64) -> impl Iterator + Clone where StandardUniform: Distribution, { @@ -43,9 +45,12 @@ where } /// Generate a sequence of deterministically random `i32`s within a specified range. -fn random_ints(count: u64, range: RangeInclusive) -> impl Iterator { +fn random_ints(count: u64, range: RangeInclusive) -> impl Iterator + Clone +where + I: Int + SampleUniform, +{ let mut rng = ChaCha8Rng::from_seed(*SEED); - (0..count).map(move |_| rng.random_range::(range.clone())) + (0..count).map(move |_| rng.random_range::(range.clone())) } macro_rules! impl_random_input { @@ -62,9 +67,11 @@ macro_rules! impl_random_input { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let count0 = iteration_count(ctx, 0); let count1 = iteration_count(ctx, 1); - let iter = random_floats(count0) - .flat_map(move |f1: $fty| random_floats(count1).map(move |f2: $fty| (f1, f2))); - (iter, count0 * count1) + let iter0 = random_floats(count0); + let iter1 = random_floats(count1); + let iter = product2(iter0, iter1); + let count = count0.strict_mul(count1); + (iter, count) } } @@ -73,12 +80,12 @@ macro_rules! impl_random_input { let count0 = iteration_count(ctx, 0); let count1 = iteration_count(ctx, 1); let count2 = iteration_count(ctx, 2); - let iter = random_floats(count0).flat_map(move |f1: $fty| { - random_floats(count1).flat_map(move |f2: $fty| { - random_floats(count2).map(move |f3: $fty| (f1, f2, f3)) - }) - }); - (iter, count0 * count1 * count2) + let iter0 = random_floats(count0); + let iter1 = random_floats(count1); + let iter2 = random_floats(count2); + let iter = product3(iter0, iter1, iter2); + let count = count0.strict_mul(count1).strict_mul(count2); + (iter, count) } } @@ -86,10 +93,12 @@ macro_rules! impl_random_input { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let count0 = iteration_count(ctx, 0); let count1 = iteration_count(ctx, 1); - let range0 = int_range(ctx, 0); - let iter = random_ints(count0, range0) - .flat_map(move |f1: i32| random_floats(count1).map(move |f2: $fty| (f1, f2))); - (iter, count0 * count1) + let range0 = int_range::(ctx, 0).unwrap_or(full_range()); + let iter0 = random_ints(count0, range0); + let iter1 = random_floats(count1); + let iter = product2(iter0, iter1); + let count = count0.strict_mul(count1); + (iter, count) } } @@ -97,11 +106,12 @@ macro_rules! impl_random_input { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let count0 = iteration_count(ctx, 0); let count1 = iteration_count(ctx, 1); - let range1 = int_range(ctx, 1); - let iter = random_floats(count0).flat_map(move |f1: $fty| { - random_ints(count1, range1.clone()).map(move |f2: i32| (f1, f2)) - }); - (iter, count0 * count1) + let range1 = int_range::(ctx, 1).unwrap_or(full_range()); + let iter0 = random_floats(count0); + let iter1 = random_ints(count1, range1.clone()); + let iter = product2(iter0, iter1); + let count = count0.strict_mul(count1); + (iter, count) } } }; @@ -114,6 +124,55 @@ impl_random_input!(f64); #[cfg(f128_enabled)] impl_random_input!(f128); +macro_rules! impl_random_input_int { + (@skip_u32 $ity:ty) => { + impl RandomInput for ($ity,) { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let count = iteration_count(ctx, 0); + let range = int_range::<$ity>(ctx, 0).unwrap_or(full_range()); + let iter = random_ints(count, range).map(|f: $ity| (f,)); + (iter, count) + } + } + + impl RandomInput for ($ity, $ity) { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let count0 = iteration_count(ctx, 0); + let count1 = iteration_count(ctx, 1); + let range0 = int_range::<$ity>(ctx, 0).unwrap_or(full_range()); + let range1 = int_range::<$ity>(ctx, 1).unwrap_or(full_range()); + let iter0 = random_ints(count0, range0); + let iter1 = random_ints(count1, range1.clone()); + let iter = product2(iter0, iter1); + (iter, count0 * count1) + } + } + }; + ($ity:ty) => { + impl_random_input_int!(@skip_u32 $ity); + + impl RandomInput for ($ity, u32) { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let count0 = iteration_count(ctx, 0); + let count1 = iteration_count(ctx, 1); + let range0 = int_range::<$ity>(ctx, 0).unwrap_or(full_range()); + let range1 = int_range::(ctx, 1).unwrap_or(full_range()); + let iter0 = random_ints(count0, range0); + let iter1 = random_ints(count1, range1.clone()); + let iter = product2(iter0, iter1); + (iter, count0 * count1) + } + } + }; +} + +impl_random_input_int!(i32); +impl_random_input_int!(i64); +impl_random_input_int!(i128); +impl_random_input_int!(@skip_u32 u32); +impl_random_input_int!(u64); +impl_random_input_int!(u128); + /// Create a test case iterator. pub fn get_test_cases( ctx: &CheckCtx, diff --git a/compiler-builtins/libm-test/src/generate/spaced.rs b/compiler-builtins/libm-test/src/generate/spaced.rs index 8e6b376ebd1e9..192106cc61827 100644 --- a/compiler-builtins/libm-test/src/generate/spaced.rs +++ b/compiler-builtins/libm-test/src/generate/spaced.rs @@ -1,12 +1,13 @@ use std::fmt; use std::ops::RangeInclusive; -use libm::support::{Float, MinInt}; +use libm::support::{Float, Int, MinInt}; use crate::domain::get_domain; -use crate::op::OpITy; +use crate::generate::{product2, product3}; +use crate::num::full_range; use crate::run_cfg::{int_range, iteration_count}; -use crate::{CheckCtx, MathOp, linear_ints, logspace}; +use crate::{Arg0, Arg1, Arg2, CheckCtx, MathOp, linear_ints, logspace}; /// Generate a sequence of inputs that eiher cover the domain in completeness (for smaller float /// types and single argument functions) or provide evenly spaced inputs across the domain with @@ -17,23 +18,23 @@ pub trait SpacedInput { /// Construct an iterator from `logspace` and also calculate the total number of steps expected /// for that iterator. -fn logspace_steps( +fn logspace_steps( ctx: &CheckCtx, argnum: usize, max_steps: u64, -) -> (impl Iterator + Clone, u64) +) -> (impl Iterator + Clone, u64) where - Op: MathOp, - OpITy: TryFrom, - u64: TryFrom, Error: fmt::Debug>, - RangeInclusive>: Iterator, + F: Float, + F::Int: TryFrom, + u64: TryFrom, + RangeInclusive: Iterator, { // i8 is a dummy type here, it can be any integer. - let domain = get_domain::(ctx.fn_ident, argnum).unwrap_float(); + let domain = get_domain::(ctx.fn_ident, argnum).unwrap_float(); let start = domain.range_start(); let end = domain.range_end(); - let max_steps = OpITy::::try_from(max_steps).unwrap_or(OpITy::::MAX); + let max_steps = F::Int::try_from(max_steps).unwrap_or(F::Int::MAX); let (iter, steps) = logspace(start, end, max_steps); // `steps` will be <= the original `max_steps`, which is a `u64`. @@ -66,174 +67,194 @@ impl, B: Iterator> Iterator for EitherIter() -> Option +fn total_value_count() -> Option where u64: TryFrom, { - u64::try_from(F::Int::MAX) + total_value_count_int::() +} + +fn total_value_count_int() -> Option +where + u64: TryFrom, +{ + u64::try_from(I::MAX.abs_diff(I::MIN)) .ok() .and_then(|max| max.checked_add(1)) } /// Returns an iterator of every possible value of type `F`. -fn all_values() -> impl Iterator +fn exhaustive_float() -> (impl Iterator + Clone, u64) where + u64: TryFrom, RangeInclusive: Iterator, { - (F::Int::MIN..=F::Int::MAX).map(|bits| F::from_bits(bits)) + let count = total_value_count::().expect("tried exhaustive with > u64::MAX items"); + let iter = (F::Int::MIN..=F::Int::MAX).map(|bits| F::from_bits(bits)); + (iter, count) } macro_rules! impl_spaced_input { ($fty:ty) => { impl SpacedInput for ($fty,) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let max_steps0 = iteration_count(ctx, 0); - // `f16` and `f32` can have exhaustive tests. - match value_count::() { - Some(steps0) if steps0 <= max_steps0 => { - let iter0 = all_values(); - let iter0 = iter0.map(|v| (v,)); - (EitherIter::A(iter0), steps0) - } - _ => { - let (iter0, steps0) = logspace_steps::(ctx, 0, max_steps0); - let iter0 = iter0.map(|v| (v,)); - (EitherIter::B(iter0), steps0) - } + + // Unary tests: `f16` and `f32` may be exhaustive. + if let Some(exhaustive_steps0) = total_value_count::>() + && exhaustive_steps0 <= max_steps0 + { + let (iter0, steps0) = exhaustive_float(); + let iter0 = iter0.map(|v| (v,)); + + return (EitherIter::A(iter0), steps0); } + + // Non-exhaustive, sweep a subset of inputs. + let (iter0, steps0) = logspace_steps::>(ctx, 0, max_steps0); + let iter0 = iter0.map(|v| (v,)); + (EitherIter::B(iter0), steps0) } } impl SpacedInput for ($fty, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let max_steps0 = iteration_count(ctx, 0); let max_steps1 = iteration_count(ctx, 1); - // `f16` can have exhaustive tests. - match value_count::() { - Some(count) if count <= max_steps0 && count <= max_steps1 => { - let iter = all_values() - .flat_map(|first| all_values().map(move |second| (first, second))); - (EitherIter::A(iter), count.checked_mul(count).unwrap()) - } - _ => { - let (iter0, steps0) = logspace_steps::(ctx, 0, max_steps0); - let (iter1, steps1) = logspace_steps::(ctx, 1, max_steps1); - let iter = iter0.flat_map(move |first| { - iter1.clone().map(move |second| (first, second)) - }); - let count = steps0.checked_mul(steps1).unwrap(); - (EitherIter::B(iter), count) - } + + // Binary test: `f16` may be exhaustive. + if let Some(exhaustive_steps0) = total_value_count::>() + && exhaustive_steps0 <= max_steps0 + && let Some(exhaustive_steps1) = total_value_count::>() + && exhaustive_steps1 <= max_steps1 + { + let (iter0, steps0) = exhaustive_float(); + let (iter1, steps1) = exhaustive_float(); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); } + + // Non-exhaustive, sweep a subset of inputs. + let (iter0, steps0) = logspace_steps::>(ctx, 0, max_steps0); + let (iter1, steps1) = logspace_steps::>(ctx, 1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + (EitherIter::B(iter), count) } } impl SpacedInput for ($fty, $fty, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let max_steps0 = iteration_count(ctx, 0); let max_steps1 = iteration_count(ctx, 1); let max_steps2 = iteration_count(ctx, 2); - // `f16` can be exhaustive tested if `LIBM_EXTENSIVE_TESTS` is incresed. - match value_count::() { - Some(count) - if count <= max_steps0 && count <= max_steps1 && count <= max_steps2 => - { - let iter = all_values().flat_map(|first| { - all_values().flat_map(move |second| { - all_values().map(move |third| (first, second, third)) - }) - }); - (EitherIter::A(iter), count.checked_pow(3).unwrap()) - } - _ => { - let (iter0, steps0) = logspace_steps::(ctx, 0, max_steps0); - let (iter1, steps1) = logspace_steps::(ctx, 1, max_steps1); - let (iter2, steps2) = logspace_steps::(ctx, 2, max_steps2); - - let iter = iter0 - .flat_map(move |first| iter1.clone().map(move |second| (first, second))) - .flat_map(move |(first, second)| { - iter2.clone().map(move |third| (first, second, third)) - }); - let count = steps0 - .checked_mul(steps1) - .unwrap() - .checked_mul(steps2) - .unwrap(); - - (EitherIter::B(iter), count) - } + + // Ternary test: `f16` may be exhaustive tested if `LIBM_EXTENSIVE_TESTS` + // is incresed. + if let Some(exhaustive_steps0) = total_value_count::>() + && exhaustive_steps0 <= max_steps0 + && let Some(exhaustive_steps1) = total_value_count::>() + && exhaustive_steps1 <= max_steps1 + && let Some(exhaustive_steps2) = total_value_count::>() + && exhaustive_steps2 <= max_steps2 + { + let (iter0, steps0) = exhaustive_float(); + let (iter1, steps1) = exhaustive_float(); + let (iter2, steps2) = exhaustive_float(); + + let iter = product3(iter0, iter1, iter2); + let count = steps0.strict_mul(steps1).strict_mul(steps2); + + return (EitherIter::A(iter), count); } + + // Non-exhaustive, sweep a subset of inputs. + let (iter0, steps0) = logspace_steps::>(ctx, 0, max_steps0); + let (iter1, steps1) = logspace_steps::>(ctx, 1, max_steps1); + let (iter2, steps2) = logspace_steps::>(ctx, 2, max_steps2); + + let iter = product3(iter0, iter1, iter2); + let count = steps0.strict_mul(steps1).strict_mul(steps2); + + (EitherIter::B(iter), count) } } impl SpacedInput for (i32, $fty) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { - let range0 = int_range(ctx, 0); + let range0 = int_range(ctx, 0).unwrap_or(full_range()); let max_steps0 = iteration_count(ctx, 0); let max_steps1 = iteration_count(ctx, 1); - match value_count::() { - Some(count1) if count1 <= max_steps1 => { - let (iter0, steps0) = linear_ints(range0, max_steps0); - let iter = iter0 - .flat_map(move |first| all_values().map(move |second| (first, second))); - (EitherIter::A(iter), steps0.checked_mul(count1).unwrap()) - } - _ => { - let (iter0, steps0) = linear_ints(range0, max_steps0); - let (iter1, steps1) = logspace_steps::(ctx, 1, max_steps1); - - let iter = iter0.flat_map(move |first| { - iter1.clone().map(move |second| (first, second)) - }); - let count = steps0.checked_mul(steps1).unwrap(); - - (EitherIter::B(iter), count) - } + + if let Some(exhaustive_steps0) = total_value_count_int::>() + && exhaustive_steps0 <= max_steps0 + && let Some(exhaustive_steps1) = total_value_count::>() + && exhaustive_steps1 <= max_steps1 + { + let (iter0, steps0) = linear_ints(range0, max_steps0); + let (iter1, steps1) = exhaustive_float(); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); } + + let (iter0, steps0) = linear_ints(range0, max_steps0); + let (iter1, steps1) = logspace_steps::>(ctx, 1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + (EitherIter::B(iter), count) } } impl SpacedInput for ($fty, i32) where - Op: MathOp, + Op: MathOp, { fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { let max_steps0 = iteration_count(ctx, 0); - let range1 = int_range(ctx, 1); + let range1 = int_range(ctx, 1).unwrap_or(full_range()); let max_steps1 = iteration_count(ctx, 1); - match value_count::() { - Some(count0) if count0 <= max_steps0 => { - let (iter1, steps1) = linear_ints(range1, max_steps1); - let iter = all_values().flat_map(move |first| { - iter1.clone().map(move |second| (first, second)) - }); - (EitherIter::A(iter), count0.checked_mul(steps1).unwrap()) - } - _ => { - let (iter0, steps0) = logspace_steps::(ctx, 0, max_steps0); - let (iter1, steps1) = linear_ints(range1, max_steps1); - - let iter = iter0.flat_map(move |first| { - iter1.clone().map(move |second| (first, second)) - }); - let count = steps0.checked_mul(steps1).unwrap(); - - (EitherIter::B(iter), count) - } + + if let Some(exhaustive_steps0) = total_value_count::>() + && exhaustive_steps0 <= max_steps0 + { + let (iter0, steps0) = exhaustive_float(); + let (iter1, steps1) = linear_ints(range1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); } + + let (iter0, steps0) = logspace_steps::>(ctx, 0, max_steps0); + let (iter1, steps1) = linear_ints(range1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + (EitherIter::B(iter), count) } } }; @@ -246,6 +267,102 @@ impl_spaced_input!(f64); #[cfg(f128_enabled)] impl_spaced_input!(f128); +macro_rules! impl_spaced_input_int { + (@skip_u32 $ity:ty) => { + impl SpacedInput for ($ity,) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let range = int_range(ctx, 0).unwrap_or(full_range()); + let max_steps0 = iteration_count(ctx, 0); + + if let Some(steps0) = total_value_count_int::>() + && steps0 <= max_steps0 + { + let iter0 = range.map(|v| (v,)); + return (EitherIter::A(iter0), steps0); + } + + let (iter0, steps0) = linear_ints::>(range, max_steps0); + let iter0 = iter0.map(|v| (v,)); + (EitherIter::B(iter0), steps0) + } + } + + impl SpacedInput for ($ity, $ity) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let range0 = int_range(ctx, 0).unwrap_or(full_range()); + let range1 = int_range(ctx, 1).unwrap_or(full_range()); + let max_steps0 = iteration_count(ctx, 0); + let max_steps1 = iteration_count(ctx, 0); + + if let Some(steps0) = total_value_count_int::>() + && steps0 <= max_steps0 + && let Some(steps1) = total_value_count_int::>() + && steps1 <= max_steps1 + { + let iter = product2(range0, range1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); + } + + let (iter0, steps0) = linear_ints::>(range0, max_steps0); + let (iter1, steps1) = linear_ints::>(range1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + + (EitherIter::B(iter), count) + } + } + }; + ($ity:ty) => { + impl_spaced_input_int!(@skip_u32 $ity); + + impl SpacedInput for ($ity, u32) + where + Op: MathOp, + { + fn get_cases(ctx: &CheckCtx) -> (impl Iterator, u64) { + let range0 = int_range(ctx, 0).unwrap_or(full_range()); + let range1 = int_range(ctx, 1).unwrap_or(full_range()); + let max_steps0 = iteration_count(ctx, 0); + let max_steps1 = iteration_count(ctx, 0); + + if let Some(steps0) = total_value_count_int::>() + && steps0 <= max_steps0 + && let Some(steps1) = total_value_count_int::>() + && steps1 <= max_steps1 + { + let iter = product2(range0, range1); + let count = steps0.strict_mul(steps1); + + return (EitherIter::A(iter), count); + } + + let (iter0, steps0) = linear_ints::>(range0, max_steps0); + let (iter1, steps1) = linear_ints::>(range1, max_steps1); + + let iter = product2(iter0, iter1); + let count = steps0.strict_mul(steps1); + (EitherIter::B(iter), count) + } + } + }; +} + +impl_spaced_input_int!(i32); +impl_spaced_input_int!(i64); +impl_spaced_input_int!(i128); +impl_spaced_input_int!(@skip_u32 u32); +impl_spaced_input_int!(u64); +impl_spaced_input_int!(u128); + /// Create a test case iterator for extensive inputs. Also returns the total test case count. pub fn get_test_cases( ctx: &CheckCtx, diff --git a/compiler-builtins/libm-test/src/lib.rs b/compiler-builtins/libm-test/src/lib.rs index 60d96ae9bceee..f2ee03252139e 100644 --- a/compiler-builtins/libm-test/src/lib.rs +++ b/compiler-builtins/libm-test/src/lib.rs @@ -3,6 +3,7 @@ #![allow(clippy::unusual_byte_groupings)] // sometimes we group by sign_exp_sig #![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable +pub mod builtins_wrapper; pub mod domain; mod f8_impl; pub mod generate; @@ -25,8 +26,8 @@ pub use f8_impl::{f8, hf8}; pub use libm::support::{Float, Int, IntTy, MinInt}; pub use num::{FloatExt, linear_ints, logspace}; pub use op::{ - BaseName, FloatTy, Identifier, MathOp, OpCFn, OpCRet, OpFTy, OpRustArgs, OpRustFn, OpRustRet, - Ty, + Arg0, Arg1, Arg2, BaseName, Group, Identifier, MathOp, OpCFn, OpCRet, OpRustArgs, OpRustFn, + OpRustRet, Ret0, Ret1, Ty, }; pub use precision::{MaybeOverride, SpecialCase, default_ulp}; use run_cfg::extensive_max_iterations; @@ -34,7 +35,7 @@ pub use run_cfg::{ CheckBasis, CheckCtx, EXTENSIVE_ENV, GeneratorKind, bigint_fuzz_iteration_count, skip_extensive_test, }; -pub use test_traits::{CheckOutput, Hex, TupleCall}; +pub use test_traits::{CheckOutput, Tuple, TupleCall}; /// Result type for tests is usually from `anyhow`. Most times there is no success value to /// propagate. diff --git a/compiler-builtins/libm-test/src/mpfloat.rs b/compiler-builtins/libm-test/src/mpfloat.rs index 91130f892b8ab..69c6590d3763b 100644 --- a/compiler-builtins/libm-test/src/mpfloat.rs +++ b/compiler-builtins/libm-test/src/mpfloat.rs @@ -6,12 +6,14 @@ use std::cmp::Ordering; use rug::Assign; -pub use rug::Float as MpFloat; -use rug::az::{self, Az}; +use rug::az::{self, Az, CheckedCast, OverflowingCast, WrappingAs}; use rug::float::Round::Nearest; -use rug::ops::{PowAssignRound, RemAssignRound}; +use rug::ops::{ + AddAssignRound, DivAssignRound, MulAssignRound, PowAssignRound, RemAssignRound, SubAssignRound, +}; +pub use rug::{Float as MpFloat, Integer as MpInt}; -use crate::{Float, MathOp}; +use crate::{Arg0, Arg1, Arg2, Float, MathOp, Ret0, Ret1}; /// Create a multiple-precision float with the correct number of bits for a concrete float type. fn new_mpfloat() -> MpFloat { @@ -19,7 +21,7 @@ fn new_mpfloat() -> MpFloat { } /// Set subnormal emulation and convert to a concrete float type. -fn prep_retval(mp: &mut MpFloat, ord: Ordering) -> F +fn prep_retval(mp: &mut MpFloat, ord: Ordering) -> F where for<'a> &'a MpFloat: az::Cast, { @@ -59,7 +61,7 @@ macro_rules! impl_mp_op { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -83,7 +85,7 @@ macro_rules! impl_mp_op { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -109,9 +111,9 @@ macro_rules! impl_mp_op { fn new_mp() -> Self::MpTy { ( - new_mpfloat::(), - new_mpfloat::(), - new_mpfloat::(), + new_mpfloat::>(), + new_mpfloat::>(), + new_mpfloat::>(), ) } @@ -133,6 +135,16 @@ libm_macros::for_each_function! { skip: [ // Most of these need a manual implementation // verify-sorted-start + addf128, + addf16, + addf32, + addf64, + ashl_u128, + ashl_u32, + ashl_u64, + ashr_i128, + ashr_i32, + ashr_i64, ceil, ceilf, ceilf128, @@ -141,6 +153,19 @@ libm_macros::for_each_function! { copysignf, copysignf128, copysignf16, + divf128, + divf32, + divf64, + eqf128, + eqf16, + eqf32, + eqf64, + extend_f16_f128, + extend_f16_f32, + extend_f16_f64, + extend_f32_f128, + extend_f32_f64, + extend_f64_f128, fabs, fabsf, fabsf128, @@ -164,26 +189,133 @@ libm_macros::for_each_function! { frexpf, frexpf128, frexpf16, + ftoi_f128_i128, + ftoi_f128_i32, + ftoi_f128_i64, + ftoi_f128_u128, + ftoi_f128_u32, + ftoi_f128_u64, + ftoi_f32_i128, + ftoi_f32_i32, + ftoi_f32_i64, + ftoi_f32_u128, + ftoi_f32_u32, + ftoi_f32_u64, + ftoi_f64_i128, + ftoi_f64_i32, + ftoi_f64_i64, + ftoi_f64_u128, + ftoi_f64_u32, + ftoi_f64_u64, + gef128, + gef16, + gef32, + gef64, + gtf128, + gtf16, + gtf32, + gtf64, + iadd_i128, + iadd_u128, + iaddo_i128, + iaddo_u128, + idiv_i128, + idiv_i32, + idiv_i64, + idiv_u128, + idiv_u32, + idiv_u64, + idivmod_i128, + idivmod_i32, + idivmod_i64, + idivmod_u128, + idivmod_u32, + idivmod_u64, ilogb, ilogbf, ilogbf128, ilogbf16, + imod_i128, + imod_i32, + imod_i64, + imod_u128, + imod_u32, + imod_u64, + imul_i128, + imul_u64, + imulo_i128, + imulo_i32, + imulo_i64, + imulo_u128, + isub_i128, + isub_u128, + isubo_i128, + isubo_u128, + itof_i128_f128, + itof_i128_f32, + itof_i128_f64, + itof_i32_f128, + itof_i32_f32, + itof_i32_f64, + itof_i64_f128, + itof_i64_f32, + itof_i64_f64, + itof_u128_f128, + itof_u128_f32, + itof_u128_f64, + itof_u32_f128, + itof_u32_f32, + itof_u32_f64, + itof_u64_f128, + itof_u64_f32, + itof_u64_f64, jn, jnf, ldexp, ldexpf, ldexpf128, ldexpf16, + leading_zeros_u128, + leading_zeros_u32, + leading_zeros_u64, + lef128, + lef16, + lef32, + lef64, lgamma, lgamma_r, lgammaf, lgammaf_r, + lshr_u128, + lshr_u32, + lshr_u64, + ltf128, + ltf16, + ltf32, + ltf64, modf, modff, + mulf128, + mulf16, + mulf32, + mulf64, + narrow_f128_f16, + narrow_f128_f32, + narrow_f128_f64, + narrow_f32_f16, + narrow_f64_f16, + narrow_f64_f32, + nef128, + nef16, + nef32, + nef64, nextafter, nextafterf, pow, powf,remquo, + powif128, + powif32, + powif64, remquof, rint, rintf, @@ -202,10 +334,21 @@ libm_macros::for_each_function! { scalbnf128, scalbnf16, sincos,sincosf, + subf128, + subf16, + subf32, + subf64, + trailing_zeros_u128, + trailing_zeros_u32, + trailing_zeros_u64, trunc, truncf, truncf128, truncf16,yn, + unordf128, + unordf16, + unordf32, + unordf64, ynf, // verify-sorted-end ], @@ -214,7 +357,7 @@ libm_macros::for_each_function! { expm1 | expm1f => exp_m1, fabs | fabsf => abs, fdim | fdimf | fdimf16 | fdimf128 => positive_diff, - fma | fmaf | fmaf128 => mul_add, + fmaf16 | fma | fmaf | fmaf128 => mul_add, fmax | fmaxf | fmaxf16 | fmaxf128 | fmaximum_num | fmaximum_numf | fmaximum_numf16 | fmaximum_numf128 => max, fmin | fminf | fminf16 | fminf128 | @@ -240,7 +383,7 @@ macro_rules! impl_no_round { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -299,7 +442,7 @@ macro_rules! impl_op_for_ty { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -307,8 +450,8 @@ macro_rules! impl_op_for_ty { this.1.assign(&this.0); let (ord0, ord1) = this.0.trunc_fract_round(&mut this.1, Nearest); ( - prep_retval::(&mut this.1, ord0), - prep_retval::(&mut this.0, ord1), + prep_retval::>(&mut this.1, ord0), + prep_retval::>(&mut this.0, ord1), ) } } @@ -317,7 +460,7 @@ macro_rules! impl_op_for_ty { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -332,14 +475,14 @@ macro_rules! impl_op_for_ty { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { let (n, x) = input; this.assign(x); let ord = this.jn_round(n, Nearest); - prep_retval::(this, ord) + prep_retval::(this, ord) } } @@ -347,7 +490,7 @@ macro_rules! impl_op_for_ty { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -355,8 +498,8 @@ macro_rules! impl_op_for_ty { this.1.assign(0.0); let (sord, cord) = this.0.sin_cos_round(&mut this.1, Nearest); ( - prep_retval::(&mut this.0, sord), - prep_retval::(&mut this.1, cord) + prep_retval::>(&mut this.0, sord), + prep_retval::>(&mut this.1, cord) ) } } @@ -366,8 +509,8 @@ macro_rules! impl_op_for_ty { fn new_mp() -> Self::MpTy { ( - new_mpfloat::(), - new_mpfloat::(), + new_mpfloat::>(), + new_mpfloat::>(), ) } @@ -375,7 +518,7 @@ macro_rules! impl_op_for_ty { this.0.assign(input.0); this.1.assign(input.1); let (ord, q) = this.0.remainder_quo31_round(&this.1, Nearest); - (prep_retval::(&mut this.0, ord), q) + (prep_retval::>(&mut this.0, ord), q) } } @@ -383,14 +526,14 @@ macro_rules! impl_op_for_ty { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { let (n, x) = input; this.assign(x); let ord = this.yn_round(n, Nearest); - prep_retval::(this, ord) + prep_retval::(this, ord) } } } @@ -401,11 +544,154 @@ macro_rules! impl_op_for_ty { macro_rules! impl_op_for_ty_all { ($fty:ty, $suffix:literal) => { paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + let ord = this.0.add_assign_round(&this.1, Nearest); + prep_retval::(&mut this.0, ord) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + let ord = this.0.sub_assign_round(&this.1, Nearest); + prep_retval::(&mut this.0, ord) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + let ord = this.0.mul_assign_round(&this.1, Nearest); + prep_retval::(&mut this.0, ord) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 == this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 > this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 >= this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 < this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 <= this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0 != this.1 + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + this.0.is_nan() || this.1.is_nan() + } + } + impl MpOp for crate::op::[]::Routine { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -420,7 +706,7 @@ macro_rules! impl_op_for_ty_all { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -436,7 +722,7 @@ macro_rules! impl_op_for_ty_all { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -456,7 +742,7 @@ macro_rules! impl_op_for_ty_all { type MpTy = (MpFloat, MpFloat); fn new_mp() -> Self::MpTy { - (new_mpfloat::(), new_mpfloat::()) + (new_mpfloat::>(), new_mpfloat::>()) } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -476,13 +762,13 @@ macro_rules! impl_op_for_ty_all { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { this.assign(input.0); let exp = this.frexp_mut(); - (prep_retval::(this, Ordering::Equal), exp) + (prep_retval::>(this, Ordering::Equal), exp) } } @@ -490,7 +776,7 @@ macro_rules! impl_op_for_ty_all { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -527,13 +813,122 @@ macro_rules! impl_op_for_ty_all { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { this.assign(input.0); *this <<= input.1; - prep_retval::(this, Ordering::Equal) + prep_retval::(this, Ordering::Equal) + } + } + } + }; +} + +macro_rules! impl_op_for_ty_no_f16 { + ($fty:ty, $suffix:literal) => { + paste::paste! { + impl MpOp for crate::op::[
]::Routine { + type MpTy = (MpFloat, MpFloat); + + fn new_mp() -> Self::MpTy { + (new_mpfloat::>(), new_mpfloat::>()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.0.assign(input.0); + this.1.assign(input.1); + let ord = this.0.div_assign_round(&this.1, Nearest); + prep_retval::(&mut this.0, ord) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + let ord = this.pow_assign_round(input.1, Nearest); + prep_retval::(this, ord) + } + } + } + }; +} + +macro_rules! impl_extend_trunc { + ($narrow:ty, $wide:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + prep_retval::(this, Ordering::Equal) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + prep_retval::(this, Ordering::Equal) + } + } + } + }; +} + +macro_rules! impl_ftoi_itof { + ($fty:ty, $ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::>() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + this.trunc_mut(); + this.subnormalize_ieee_round(Ordering::Equal, Nearest); + (&*this).checked_cast().unwrap_or_else(|| { + if this.is_nan() { + 0 + } else if this.is_sign_negative() { + Self::RustRet::MIN + } else { + Self::RustRet::MAX + } + }) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + prep_retval::(this, Ordering::Equal) } } } @@ -543,6 +938,11 @@ macro_rules! impl_op_for_ty_all { impl_op_for_ty!(f32, "f"); impl_op_for_ty!(f64, ""); +impl_op_for_ty_no_f16!(f32, "f"); +impl_op_for_ty_no_f16!(f64, ""); +#[cfg(f128_enabled)] +impl_op_for_ty_no_f16!(f128, "f128"); + #[cfg(f16_enabled)] impl_op_for_ty_all!(f16, "f16"); impl_op_for_ty_all!(f32, "f"); @@ -550,18 +950,56 @@ impl_op_for_ty_all!(f64, ""); #[cfg(f128_enabled)] impl_op_for_ty_all!(f128, "f128"); +#[cfg(f16_enabled)] +impl_extend_trunc!(f16, f32); +#[cfg(f16_enabled)] +impl_extend_trunc!(f16, f64); +#[cfg(f16_enabled)] +#[cfg(f128_enabled)] +impl_extend_trunc!(f16, f128); +impl_extend_trunc!(f32, f64); +#[cfg(f128_enabled)] +impl_extend_trunc!(f32, f128); +#[cfg(f128_enabled)] +impl_extend_trunc!(f64, f128); + +impl_ftoi_itof!(f32, i32); +impl_ftoi_itof!(f32, i64); +impl_ftoi_itof!(f32, i128); +impl_ftoi_itof!(f32, u32); +impl_ftoi_itof!(f32, u64); +impl_ftoi_itof!(f32, u128); +impl_ftoi_itof!(f64, i32); +impl_ftoi_itof!(f64, i64); +impl_ftoi_itof!(f64, i128); +impl_ftoi_itof!(f64, u32); +impl_ftoi_itof!(f64, u64); +impl_ftoi_itof!(f64, u128); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, i32); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, i64); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, i128); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, u32); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, u64); +#[cfg(f128_enabled)] +impl_ftoi_itof!(f128, u128); + // `lgamma_r` is not a simple suffix so we can't use the above macro. impl MpOp for crate::op::lgamma_r::Routine { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { this.assign(input.0); let (sign, ord) = this.ln_abs_gamma_round(Nearest); - let ret = prep_retval::(this, ord); + let ret = prep_retval::>(this, ord); (ret, sign as i32) } } @@ -570,13 +1008,13 @@ impl MpOp for crate::op::lgammaf_r::Routine { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { this.assign(input.0); let (sign, ord) = this.ln_abs_gamma_round(Nearest); - let ret = prep_retval::(this, ord); + let ret = prep_retval::>(this, ord); (ret, sign as i32) } } @@ -585,7 +1023,7 @@ impl MpOp for crate::op::lgamma::Routine { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -597,7 +1035,7 @@ impl MpOp for crate::op::lgammaf::Routine { type MpTy = MpFloat; fn new_mp() -> Self::MpTy { - new_mpfloat::() + new_mpfloat::>() } fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { @@ -630,3 +1068,286 @@ impl MpOp for crate::op::nextafterf::Routine { unimplemented!("nextafter does not yet have a MPFR operation"); } } + +macro_rules! impl_int_ops { + ($ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + if input.1 == 0 { + // Make divide by 0 well-defined to match our wrappers. + return <$ity>::MIN; + } + this.assign(input.0); + *this /= input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + if input.1 == 0 { + // Make divide by 0 well-defined to match our wrappers. + return <$ity>::MIN; + } + this.assign(input.0); + *this %= input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = (MpInt, MpInt); + + fn new_mp() -> Self::MpTy { + (MpInt::new(), MpInt::new()) + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + if input.1 == 0 { + // Make divide by 0 well-defined to match our wrappers. + return (<$ity>::MIN, <$ity>::MIN); + } + this.0.assign(input.0); + this.1.assign(input.1); + this.0.div_rem_mut(&mut this.1); + ( + (&this.0).wrapping_as::>(), + (&this.1).wrapping_as::>(), + ) + } + } + } + }; +} + +impl_int_ops!(i32); +impl_int_ops!(i64); +impl_int_ops!(i128); +impl_int_ops!(u32); +impl_int_ops!(u64); +impl_int_ops!(u128); + +macro_rules! impl_unsigned_int_ops { + ($ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + assert!(input.1 < Arg0::::BITS, "got UB shift {}", input.1); + this.assign(input.0); + *this <<= input.1; + (&*this).wrapping_as::>() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + assert!(input.1 < Arg0::::BITS, "got UB shift {}", input.1); + this.assign(input.0); + *this >>= input.1; + (&*this).wrapping_as::>() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + (Arg0::::BITS - this.significant_bits()).try_into().unwrap() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + this.find_one(0).unwrap_or(Arg0::::BITS).try_into().unwrap() + } + } + } + }; +} + +impl_unsigned_int_ops!(u32); +impl_unsigned_int_ops!(u64); +impl_unsigned_int_ops!(u128); + +macro_rules! impl_signed_int_ops { + ($ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + assert!(input.1 < Arg0::::BITS, "got UB shift {}", input.1); + this.assign(input.0); + *this >>= input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this *= input.1; + (&*this).overflowing_cast() + } + } + } + }; +} + +impl_signed_int_ops!(i32); +impl_signed_int_ops!(i64); +impl_signed_int_ops!(i128); + +macro_rules! impl_u128_i128_int_ops { + ($ity:ty) => { + paste::paste! { + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this += input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this -= input.1; + (&*this).wrapping_as::() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this += input.1; + (&*this).overflowing_cast() + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this -= input.1; + (&*this).overflowing_cast() + } + } + } + }; +} + +impl_u128_i128_int_ops!(i128); +impl_u128_i128_int_ops!(u128); + +impl MpOp for crate::op::imul_u64::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this *= input.1; + (&*this).wrapping_as() + } +} + +impl MpOp for crate::op::imul_i128::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this *= input.1; + (&*this).wrapping_as() + } +} + +impl MpOp for crate::op::imulo_u128::Routine { + type MpTy = MpInt; + + fn new_mp() -> Self::MpTy { + MpInt::new() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + *this *= input.1; + (&*this).overflowing_cast() + } +} diff --git a/compiler-builtins/libm-test/src/num.rs b/compiler-builtins/libm-test/src/num.rs index 3237c85039d57..efa87d6351597 100644 --- a/compiler-builtins/libm-test/src/num.rs +++ b/compiler-builtins/libm-test/src/num.rs @@ -1,6 +1,7 @@ //! Helpful numeric operations. use std::cmp::min; +use std::fmt; use std::ops::RangeInclusive; use libm::support::Float; @@ -257,15 +258,20 @@ where } /// Returns an iterator of up to `steps` integers evenly distributed. -pub fn linear_ints( - range: RangeInclusive, +pub fn linear_ints( + range: RangeInclusive, steps: u64, -) -> (impl Iterator + Clone, u64) { - let steps = steps.checked_sub(1).unwrap(); - let between = u64::from(range.start().abs_diff(*range.end())); - let spacing = i32::try_from((between / steps).max(1)).unwrap(); - let steps = steps.min(between); - let mut x: i32 = *range.start(); +) -> (impl Iterator + Clone, u64) +where + I: Int + TryFrom, + u128: TryFrom, +{ + let spaces: u128 = steps.checked_sub(1).unwrap().into(); + let between = u128::try_from(range.start().abs_diff(*range.end())).expect("out of u128 range"); + let spacing = I::try_from((between / spaces).max(1)).unwrap(); + let steps = spaces.min(between); + let steps = u64::try_from(steps).expect("> u64::MAX steps"); + let mut x: I = *range.start(); ( (0..=steps).map(move |_| { let res = x; @@ -278,6 +284,11 @@ pub fn linear_ints( ) } +/// `..` as a `RangeInclusive`. +pub fn full_range() -> RangeInclusive { + I::MIN..=I::MAX +} + #[cfg(test)] mod tests { use std::cmp::max; diff --git a/compiler-builtins/libm-test/src/op.rs b/compiler-builtins/libm-test/src/op.rs index afd445ff9c5ae..809d518755262 100644 --- a/compiler-builtins/libm-test/src/op.rs +++ b/compiler-builtins/libm-test/src/op.rs @@ -16,19 +16,25 @@ use std::fmt; use std::panic::{RefUnwindSafe, UnwindSafe}; -pub use shared::{ALL_OPERATIONS, FloatTy, MathOpInfo, Ty}; +pub use api_list_common::{ALL_OPERATIONS, Group, MathOpInfo, Ty}; -use crate::{CheckOutput, Float, TupleCall}; - -mod shared { - include!("../../crates/libm-macros/src/shared.rs"); -} +use crate::{CheckOutput, Tuple, TupleCall}; /// An enum representing each possible symbol name (`sin`, `sinf`, `sinl`, etc). #[libm_macros::function_enum(BaseName)] #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)] pub enum Identifier {} +impl Identifier { + /// Return information about this operation. + pub fn math_op(self) -> &'static MathOpInfo { + ALL_OPERATIONS + .iter() + .find(|op| op.name == self.as_str()) + .unwrap() + } +} + impl fmt::Display for Identifier { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.write_str(self.as_str()) @@ -49,9 +55,6 @@ impl fmt::Display for BaseName { /// Attributes ascribed to a `libm` routine including signature, type information, /// and naming. pub trait MathOp { - /// The float type used for this operation. - type FTy: Float; - /// The function type representing the signature in a C library. type CFn: Copy; @@ -72,6 +75,7 @@ pub trait MathOp { /// The required `TupleCall` bounds ensure this type can be passed either to the C function or /// to the Rust function. type RustArgs: Copy + + Tuple + TupleCall + TupleCall + RefUnwindSafe; @@ -90,38 +94,44 @@ pub trait MathOp { /// The function in `libm` which can be called. const ROUTINE: Self::RustFn; - - /// Whether or not the function is part of libm public API. - const PUBLIC: bool; } -/// Access the associated `FTy` type from an op (helper to avoid ambiguous associated types). -pub type OpFTy = ::FTy; -/// Access the associated `FTy::Int` type from an op (helper to avoid ambiguous associated types). -pub type OpITy = <::FTy as Float>::Int; -/// Access the associated `CFn` type from an op (helper to avoid ambiguous associated types). +/* Most of these are workarounds for */ + +/// Access the associated `CFn` type from an op. pub type OpCFn = ::CFn; -/// Access the associated `CRet` type from an op (helper to avoid ambiguous associated types). +/// Access the associated `CRet` type from an op. pub type OpCRet = ::CRet; -/// Access the associated `RustFn` type from an op (helper to avoid ambiguous associated types). +/// Access the associated `RustFn` type from an op. pub type OpRustFn = ::RustFn; -/// Access the associated `RustArgs` type from an op (helper to avoid ambiguous associated types). +/// Access the associated `RustArgs` type from an op. pub type OpRustArgs = ::RustArgs; -/// Access the associated `RustRet` type from an op (helper to avoid ambiguous associated types). +/// Access the associated `RustRet` type from an op. pub type OpRustRet = ::RustRet; +/// Get the type of the first Rust argument. +pub type Arg0 = as Tuple>::T0; +/// Get the type of the second Rust argument. +pub type Arg1 = as Tuple>::T1; +/// Get the type of the third Rust argument. +pub type Arg2 = as Tuple>::T2; + +/// If the Rust return type is a tuple, get the first type. +pub type Ret0 = as Tuple>::T0; +/// If the Rust return type is a tuple, get the second type. +pub type Ret1 = as Tuple>::T1; + macro_rules! create_op_modules { // Matcher for unary functions ( fn_name: $fn_name:ident, - FTy: $FTy:ty, CFn: $CFn:ty, CArgs: $CArgs:ty, CRet: $CRet:ty, RustFn: $RustFn:ty, RustArgs: $RustArgs:ty, RustRet: $RustRet:ty, - public: $public:expr, + path: $path:path, attrs: [$($attr:meta),*], ) => { paste::paste! { @@ -131,7 +141,6 @@ macro_rules! create_op_modules { pub struct Routine; impl MathOp for Routine { - type FTy = $FTy; type CFn = for<'a> $CFn; type CArgs<'a> = $CArgs where Self: 'a; type CRet = $CRet; @@ -140,8 +149,7 @@ macro_rules! create_op_modules { type RustRet = $RustRet; const IDENTIFIER: Identifier = Identifier::[< $fn_name:camel >]; - const ROUTINE: Self::RustFn = libm::$fn_name; - const PUBLIC: bool = $public; + const ROUTINE: Self::RustFn = $path; } } diff --git a/compiler-builtins/libm-test/src/precision.rs b/compiler-builtins/libm-test/src/precision.rs index e994244142749..967274caa9644 100644 --- a/compiler-builtins/libm-test/src/precision.rs +++ b/compiler-builtins/libm-test/src/precision.rs @@ -13,9 +13,38 @@ pub struct SpecialCase; /// ULP allowed to differ from the results returned by a test basis. #[allow(clippy::single_match)] -pub fn default_ulp(ctx: &CheckCtx) -> u32 { +pub fn default_ulp(ctx: &CheckCtx) -> Option { // ULP compared to the infinite (MPFR) result. let mut ulp = match ctx.base_name { + // Basic arithmetic needs to always be precise. + Bn::Add | Bn::Sub | Bn::Mul | Bn::Div => 0, + // FIXME(correctness): we need a better powi implementation (though this is no worse + // than C). + Bn::Powi if ctx.fn_ident == Id::Powif64 => 500_000, + Bn::Powi => 1000, + + // Operations that only return non-float results + Bn::Eq | Bn::Ne | Bn::Gt | Bn::Ge | Bn::Lt | Bn::Le | Bn::Unord | Bn::Ilogb => return None, + + // Integer ops + Bn::Ashl + | Bn::Ashr + | Bn::Lshr + | Bn::LeadingZeros + | Bn::TrailingZeros + | Bn::Iadd + | Bn::Iaddo + | Bn::Isub + | Bn::Isubo + | Bn::Imul + | Bn::Imulo + | Bn::Idiv + | Bn::Imod + | Bn::Idivmod => return None, + + // Convrsion operations must be precise. + Bn::Extend | Bn::Narrow | Bn::Ftoi | Bn::Itof => 0, + // Operations that require exact results. This list should correlate with what we // have documented at . Bn::Ceil @@ -32,7 +61,6 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { | Bn::FminimumNum | Bn::Fmod | Bn::Frexp - | Bn::Ilogb | Bn::Ldexp | Bn::Modf | Bn::Nextafter @@ -47,6 +75,7 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { // Operations that aren't required to be exact, but our implementations are. Bn::Cbrt => 0, + Bn::Hypot if ctx.fn_ident == Id::Hypot => 0, // Bessel functions have large inaccuracies. Bn::J0 | Bn::J1 | Bn::Y0 | Bn::Y1 | Bn::Jn | Bn::Yn => 8_000_000, @@ -84,8 +113,10 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Bn::Tgamma => 20, }; - // These have a separate implementation on i586 - if cfg!(x86_no_sse) { + let mut orig_ulp = ulp; + + // These have a separate implementation on i586 which is more accurate. + if cfg!(x86_no_sse2) { match ctx.fn_ident { Id::Exp => ulp = 1, Id::Exp2 => ulp = 1, @@ -95,43 +126,17 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Id::Exp10f => ulp = 0, _ => (), } - } - - // There are some cases where musl's approximation is less accurate than ours. For these - // cases, increase the ULP. - if ctx.basis == Musl { - match ctx.base_name { - Bn::Cosh => ulp = 2, - Bn::Exp10 if usize::BITS < 64 => ulp = 4, - Bn::Tanh => ulp = 4, - _ => (), - } - match ctx.fn_ident { - Id::Cbrt => ulp = 2, - // FIXME(#401): musl has an incorrect result here. - Id::Fdim => ulp = 2, - Id::Exp2f => ulp = 1, - Id::Expf => ulp = 1, - Id::Sincosf => ulp = 500, - Id::Tgamma => ulp = 20, - _ => (), - } - } + assert!(ulp <= orig_ulp, "pattern can be deleted {ctx:?}"); + orig_ulp = ulp; - if cfg!(target_arch = "x86") { + // Due to rust-lang/rust#114479 (unsound floating point behavior on x86 without SSE), the + // following operations have worse precision. match ctx.fn_ident { - // Input `fma(0.999999999999999, 1.0000000000000013, 0.0) = 1.0000000000000002` is - // incorrect on i586 and i686. + // FIXME: these need to be correctly rounded but are not, likely due to LLVM bugs + // around precision without SSE float ops. It may be worth looking into an assembly + // implementation. Id::Fma => ulp = 1, - _ => (), - } - } - - // In some cases, our implementation is less accurate than musl on i586. - if cfg!(x86_no_sse) { - match ctx.fn_ident { - // FIXME(#401): these need to be correctly rounded but are not. Id::Fmaf => ulp = 1, Id::Fdim => ulp = 1, Id::Round => ulp = 1, @@ -139,13 +144,44 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Id::Asinh => ulp = 3, Id::Asinhf => ulp = 3, Id::Cbrt => ulp = 1, - Id::Log1p | Id::Log1pf => ulp = 2, + Id::Hypot => ulp = 1, + Id::Log1p => ulp = 2, + Id::Log1pf => ulp = 2, Id::Tan => ulp = 2, _ => (), } + + assert!(ulp >= orig_ulp, "pattern can be deleted {ctx:?}"); + orig_ulp = ulp; + } + + // There are some cases where musl's approximation is less accurate than ours, either due to + // the implementation itself or because of x87 inaccuracy problems. For these cases, increase + // the allowed ULP. + if ctx.basis == Musl { + match ctx.fn_ident { + // Musl probably runs into issues with the x87 ABI here which we don't have. + Id::Fma if cfg!(target_arch = "x86") => ulp = 1, + Id::Fdim => ulp = 2, + + Id::Asinhf => ulp = 3, + Id::Cbrt => ulp = 2, + Id::Cosh => ulp = 2, + Id::Coshf => ulp = 2, + Id::Exp10 if cfg!(x86_no_sse2) => ulp = 4, + Id::Exp10f if cfg!(x86_no_sse2) => ulp = 4, + Id::Exp2f => ulp = 1, + Id::Expf => ulp = 1, + Id::Hypot => ulp = 1, + Id::Tanh => ulp = 4, + Id::Tanhf => ulp = 4, + _ => (), + } + + assert!(ulp >= orig_ulp, "pattern can be deleted {ctx:?}"); } - ulp + Some(ulp) } /// Result of checking for possible overrides. @@ -261,15 +297,6 @@ impl MaybeOverride<(f32,)> for SpecialCase { impl MaybeOverride<(f64,)> for SpecialCase { fn check_float(input: (f64,), actual: F, expected: F, ctx: &CheckCtx) -> CheckAction { - if cfg!(x86_no_sse) - && (ctx.base_name == BaseName::Rint || ctx.base_name == BaseName::Roundeven) - && (expected - actual).abs() <= F::ONE - && (expected - actual).abs() > F::ZERO - { - // Our rounding mode is incorrect. - return XFAIL("i586 rint rounding mode"); - } - if ctx.base_name == BaseName::J0 && input.0 < -1e300 { // Errors get huge close to -inf return XFAIL_NOCHECK; @@ -499,18 +526,19 @@ fn int_float_common( } // Our bessel functions blow up with large N values - if ctx.basis == Musl && (ctx.base_name == BaseName::Jn || ctx.base_name == BaseName::Yn) { - if cfg!(x86_no_sse) { + if ctx.base_name == BaseName::Jn || ctx.base_name == BaseName::Yn { + if cfg!(x86_no_sse2) { // Precision is especially bad on i586, not worth checking. return XFAIL_NOCHECK; } - if input.0 > 4000 { + if input.0 > 140 { return XFAIL_NOCHECK; - } else if input.0 > 100 { - return CheckAction::AssertWithUlp(2_000_000); + } else if input.0 > 80 { + return CheckAction::AssertWithUlp(10_000_000); } } + DEFAULT } @@ -521,7 +549,29 @@ impl MaybeOverride<(f64, i32)> for SpecialCase {} #[cfg(f128_enabled)] impl MaybeOverride<(f128, i32)> for SpecialCase {} +#[cfg(f16_enabled)] +impl MaybeOverride<(f16, f16, f16)> for SpecialCase {} impl MaybeOverride<(f32, f32, f32)> for SpecialCase {} impl MaybeOverride<(f64, f64, f64)> for SpecialCase {} #[cfg(f128_enabled)] impl MaybeOverride<(f128, f128, f128)> for SpecialCase {} + +impl MaybeOverride<(i32,)> for SpecialCase {} +impl MaybeOverride<(i64,)> for SpecialCase {} +impl MaybeOverride<(i128,)> for SpecialCase {} +impl MaybeOverride<(u32,)> for SpecialCase {} +impl MaybeOverride<(u64,)> for SpecialCase {} +impl MaybeOverride<(u128,)> for SpecialCase {} + +impl MaybeOverride<(i32, i32)> for SpecialCase {} +impl MaybeOverride<(i64, i64)> for SpecialCase {} +impl MaybeOverride<(i128, i128)> for SpecialCase {} +impl MaybeOverride<(u32, u32)> for SpecialCase {} +impl MaybeOverride<(u64, u64)> for SpecialCase {} +impl MaybeOverride<(u128, u128)> for SpecialCase {} + +impl MaybeOverride<(i32, u32)> for SpecialCase {} +impl MaybeOverride<(i64, u32)> for SpecialCase {} +impl MaybeOverride<(i128, u32)> for SpecialCase {} +impl MaybeOverride<(u64, u32)> for SpecialCase {} +impl MaybeOverride<(u128, u32)> for SpecialCase {} diff --git a/compiler-builtins/libm-test/src/run_cfg.rs b/compiler-builtins/libm-test/src/run_cfg.rs index 90f81195c8560..2b42d581b4c9f 100644 --- a/compiler-builtins/libm-test/src/run_cfg.rs +++ b/compiler-builtins/libm-test/src/run_cfg.rs @@ -2,10 +2,10 @@ use std::ops::RangeInclusive; use std::sync::LazyLock; -use std::{env, str}; +use std::{env, fmt, str}; use crate::generate::random::{SEED, SEED_ENV}; -use crate::{BaseName, FloatTy, Identifier, test_log}; +use crate::{BaseName, Group, Identifier, Ty, test_log}; /// The environment variable indicating which extensive tests should be run. pub const EXTENSIVE_ENV: &str = "LIBM_EXTENSIVE_TESTS"; @@ -69,7 +69,7 @@ pub fn extensive_max_iterations() -> u64 { #[derive(Clone, Debug, PartialEq, Eq)] pub struct CheckCtx { /// Allowed ULP deviation - pub ulp: u32, + pub ulp: Option, pub fn_ident: Identifier, pub base_name: BaseName, /// Function name. @@ -88,7 +88,7 @@ impl CheckCtx { /// Create a new check context, using the default ULP for the function. pub fn new(fn_ident: Identifier, basis: CheckBasis, gen_kind: GeneratorKind) -> Self { let mut ret = Self { - ulp: 0, + ulp: None, fn_ident, fn_name: fn_ident.as_str(), base_name: fn_ident.base_name(), @@ -152,10 +152,10 @@ static EXTENSIVE: LazyLock> = LazyLock::new(|| { let list = var.split(",").filter(|s| !s.is_empty()).collect::>(); let mut ret = Vec::new(); - let append_ty_ops = |ret: &mut Vec<_>, fty: FloatTy| { + let append_ty_ops = |ret: &mut Vec<_>, group: Group| { let iter = Identifier::ALL .iter() - .filter(move |id| id.math_op().float_ty == fty) + .filter(move |id| id.math_op().group == group) .copied(); ret.extend(iter); }; @@ -163,10 +163,11 @@ static EXTENSIVE: LazyLock> = LazyLock::new(|| { for item in list { match item { "all" => ret = Identifier::ALL.to_owned(), - "all_f16" => append_ty_ops(&mut ret, FloatTy::F16), - "all_f32" => append_ty_ops(&mut ret, FloatTy::F32), - "all_f64" => append_ty_ops(&mut ret, FloatTy::F64), - "all_f128" => append_ty_ops(&mut ret, FloatTy::F128), + "all_f16" => append_ty_ops(&mut ret, Group::F16), + "all_f32" => append_ty_ops(&mut ret, Group::F32), + "all_f64" => append_ty_ops(&mut ret, Group::F64), + "all_f128" => append_ty_ops(&mut ret, Group::F128), + "all_int" => append_ty_ops(&mut ret, Group::Integer), s => { let id = Identifier::from_str(s) .unwrap_or_else(|| panic!("unrecognized test name `{s}`")); @@ -178,13 +179,18 @@ static EXTENSIVE: LazyLock> = LazyLock::new(|| { ret }); +/// Most ops are somewhere on the order or 10^7 iterations per second when running exhaustive +/// tests. Assuming about four hours to run, this is log2 of the max number of inputs that coul +/// be tested. +const MAX_REASONABLE_EXHAUSTIVE_BITS: u32 = 36; + /// Information about the function to be tested. #[derive(Debug)] struct TestEnv { /// Tests should be reduced because the platform is slow. E.g. 32-bit or emulated. slow_platform: bool, - /// The float cannot be tested exhaustively, `f64` or `f128`. - large_float_ty: bool, + /// How many bits of input there are for this function. + total_input_bits: u32, /// Env indicates that an extensive test should be run. should_run_extensive: bool, /// Multiprecision tests will be run. @@ -199,10 +205,11 @@ impl TestEnv { let op = id.math_op(); let will_run_mp = cfg!(feature = "build-mpfr"); - let large_float_ty = match op.float_ty { - FloatTy::F16 | FloatTy::F32 => false, - FloatTy::F64 | FloatTy::F128 => true, - }; + + let mut total_input_bits = 0; + for ty in op.rust_sig.args { + total_input_bits += ty.effective_bits(); + } let will_run_extensive = EXTENSIVE.contains(&id); @@ -210,7 +217,7 @@ impl TestEnv { Self { slow_platform: slow_platform(), - large_float_ty, + total_input_bits, should_run_extensive: will_run_extensive, mp_tests_enabled: will_run_mp, input_count, @@ -260,8 +267,9 @@ pub fn iteration_count(ctx: &CheckCtx, argnum: usize) -> u64 { } }; - // Larger float types get more iterations. - if t_env.large_float_ty { + // This signature has too many possible inputs to test exhaustively, so increase input count + // on all other kinds of tests to get better coverage. + if t_env.total_input_bits > MAX_REASONABLE_EXHAUSTIVE_BITS { if ctx.extensive { // Extensive already has a pretty high test count. total_iterations *= 2; @@ -339,12 +347,39 @@ pub fn iteration_count(ctx: &CheckCtx, argnum: usize) -> u64 { ntests } -/// Some tests require that an integer be kept within reasonable limits; generate that here. -pub fn int_range(ctx: &CheckCtx, argnum: usize) -> RangeInclusive { +/// Some tests require that an integer be kept within reasonable limits; if that is needed, retun +/// a limited range. +pub fn int_range(ctx: &CheckCtx, argnum: usize) -> Option> +where + I: TryFrom, +{ let t_env = TestEnv::from_env(ctx); + let argcount = ctx.fn_ident.math_op().rust_sig.args.len(); + assert!( + argnum < argcount, + "requested argnum {argnum} of only {argcount} args" + ); + + // Shift operations can have UB if the shift value exceeds their range + if matches!( + ctx.base_name, + BaseName::Ashl | BaseName::Ashr | BaseName::Lshr + ) && argnum == 1 + { + let max = match ctx.fn_ident.math_op().rust_sig.args[0] { + Ty::U32 | Ty::I32 => 31, + Ty::U64 | Ty::I64 => 63, + Ty::U128 | Ty::I128 => 127, + ty => panic!("unexpected type {ty}"), + }; + + return Some(map_range(0..=max)); + } + + // Use the whole range for most functions. if !matches!(ctx.base_name, BaseName::Jn | BaseName::Yn) { - return i32::MIN..=i32::MAX; + return None; } assert_eq!( @@ -362,12 +397,21 @@ pub fn int_range(ctx: &CheckCtx, argnum: usize) -> RangeInclusive { let extensive_range = (-0xfff)..=0xfffff; - match ctx.gen_kind { + let ret = match ctx.gen_kind { _ if ctx.extensive => extensive_range, GeneratorKind::Spaced | GeneratorKind::Random => non_extensive_range, GeneratorKind::EdgeCases => extensive_range, GeneratorKind::List => unimplemented!("shoudn't need range for {:?}", ctx.gen_kind), - } + }; + + Some(map_range(ret)) +} + +fn map_range(r: RangeInclusive) -> RangeInclusive +where + I: TryFrom, +{ + I::try_from(*r.start()).unwrap()..=I::try_from(*r.end()).unwrap() } /// For domain tests, limit how many asymptotes or specified check points we test. diff --git a/compiler-builtins/libm-test/src/test_traits.rs b/compiler-builtins/libm-test/src/test_traits.rs index f8621a3734a4c..a1b48224bfd47 100644 --- a/compiler-builtins/libm-test/src/test_traits.rs +++ b/compiler-builtins/libm-test/src/test_traits.rs @@ -1,7 +1,8 @@ //! Traits related to testing. //! -//! There are two main traits in this module: +//! There are three main traits in this module: //! +//! - `Tuple`: Implemented on tuples to help extract types. //! - `TupleCall`: implemented on tuples to allow calling them as function arguments. //! - `CheckOutput`: implemented on anything that is an output type for validation against an //! expected value. @@ -10,7 +11,7 @@ use std::panic::{RefUnwindSafe, UnwindSafe}; use std::{fmt, panic}; use anyhow::{Context, anyhow, bail, ensure}; -use libm::support::Hexf; +use libm::support::{DisplayHex, Hex}; use crate::precision::CheckAction; use crate::{ @@ -23,6 +24,7 @@ use crate::{ /// tuple for multiple signatures). pub trait TupleCall: fmt::Debug { type Output; + fn call(self, f: Func) -> Self::Output; /// Intercept panics and print the input to stderr before continuing. @@ -42,6 +44,16 @@ pub trait TupleCall: fmt::Debug { } } +/// Helper to allow extracting types from a tuple. +pub trait Tuple { + type T0; + type T1; + type T2; +} + +/// If a tuple contains fewer types than provided in `Tuple`, they use this struct. +pub enum Unused {} + /// A trait to implement on any output type so we can verify it in a generic way. pub trait CheckOutput: Sized { /// Validate `self` (actual) and `expected` are the same. @@ -50,15 +62,24 @@ pub trait CheckOutput: Sized { fn validate(self, expected: Self, input: Input, ctx: &CheckCtx) -> TestResult; } -/// A helper trait to print something as hex with the correct number of nibbles, e.g. a `u32` -/// will always print with `0x` followed by 8 digits. -/// -/// This is only used for printing errors so allocating is okay. -pub trait Hex: Copy { - /// Hex integer syntax. - fn hex(self) -> String; - /// Hex float syntax. - fn hexf(self) -> String; +/* implement Tuple */ + +impl Tuple for (T0,) { + type T0 = T0; + type T1 = Unused; + type T2 = Unused; +} + +impl Tuple for (T0, T1) { + type T0 = T0; + type T1 = T1; + type T2 = Unused; +} + +impl Tuple for (T0, T1, T2) { + type T0 = T0; + type T1 = T1; + type T2 = T2; } /* implement `TupleCall` */ @@ -142,47 +163,25 @@ where } } -/* implement `Hex` */ - -impl Hex for (T1,) -where - T1: Hex, -{ - fn hex(self) -> String { - format!("({},)", self.0.hex()) - } - - fn hexf(self) -> String { - format!("({},)", self.0.hexf()) - } -} - -impl Hex for (T1, T2) -where - T1: Hex, - T2: Hex, -{ - fn hex(self) -> String { - format!("({}, {})", self.0.hex(), self.1.hex()) - } - - fn hexf(self) -> String { - format!("({}, {})", self.0.hexf(), self.1.hexf()) - } -} +/* trait implementations for bool */ -impl Hex for (T1, T2, T3) +impl CheckOutput for bool where - T1: Hex, - T2: Hex, - T3: Hex, + Input: Copy + DisplayHex + fmt::Debug, + SpecialCase: MaybeOverride, { - fn hex(self) -> String { - format!("({}, {}, {})", self.0.hex(), self.1.hex(), self.2.hex()) - } + fn validate<'a>(self, expected: Self, input: Input, _ctx: &CheckCtx) -> TestResult { + anyhow::ensure!( + self == expected, + "\ + \n input: {input:?} {ibits}\ + \n expected: {expected}\ + \n actual: {self}\ + ", + ibits = Hex(input), + ); - fn hexf(self) -> String { - format!("({}, {}, {})", self.0.hexf(), self.1.hexf(), self.2.hexf()) + Ok(()) } } @@ -191,19 +190,9 @@ where macro_rules! impl_int { ($($ty:ty),*) => { $( - impl Hex for $ty { - fn hex(self) -> String { - format!("{self:#0width$x}", width = ((Self::BITS / 4) + 2) as usize) - } - - fn hexf(self) -> String { - String::new() - } - } - impl $crate::CheckOutput for $ty where - Input: Hex + fmt::Debug, + Input: Copy + DisplayHex + fmt::Debug, SpecialCase: MaybeOverride, { fn validate<'a>( @@ -221,8 +210,8 @@ macro_rules! impl_int { fn validate_int(actual: I, expected: I, input: Input, ctx: &CheckCtx) -> TestResult where - I: Int + Hex, - Input: Hex + fmt::Debug, + I: Int, + Input: Copy + DisplayHex + fmt::Debug, SpecialCase: MaybeOverride, { let (result, xfail_msg) = match SpecialCase::check_int(input, actual, expected, ctx) { @@ -243,47 +232,29 @@ where None => String::new(), }; - anyhow::ensure!( - result, - "\ - \n input: {input:?} {ibits}\ - \n expected: {expected:<22?} {expbits}\ - \n actual: {actual:<22?} {actbits}\ - \n {msg}\ - ", - actbits = actual.hex(), - expbits = expected.hex(), - ibits = input.hex(), - msg = make_xfail_msg() - ); + if !result { + bail!(make_error_message( + input, + expected, + actual, + "", + &make_xfail_msg() + )); + } Ok(()) } -impl_int!(u16, i16, u32, i32, u64, i64, u128, i128); +impl_int!(u16, i16, u32, i32, u64, i64, u128, i128, usize); /* trait implementations for floats */ macro_rules! impl_float { ($($ty:ty),*) => { $( - impl Hex for $ty { - fn hex(self) -> String { - format!( - "{:#0width$x}", - self.to_bits(), - width = ((Self::BITS / 4) + 2) as usize - ) - } - - fn hexf(self) -> String { - format!("{}", Hexf(self)) - } - } - impl $crate::CheckOutput for $ty where - Input: Hex + fmt::Debug, + Input: Copy + DisplayHex + fmt::Debug, SpecialCase: MaybeOverride, { fn validate<'a>( @@ -301,8 +272,8 @@ macro_rules! impl_float { fn validate_float(actual: F, expected: F, input: Input, ctx: &CheckCtx) -> TestResult where - F: Float + Hex, - Input: Hex + fmt::Debug, + F: Float, + Input: Copy + DisplayHex + fmt::Debug, u32: TryFrom, SpecialCase: MaybeOverride, { @@ -310,11 +281,11 @@ where // Create a wrapper function so we only need to `.with_context` once. let mut inner = || -> TestResult { - let mut allowed_ulp = ctx.ulp; + let mut allowed_ulp = ctx + .ulp + .expect("functions returning floats should have a default ulp set"); match SpecialCase::check_float(input, actual, expected, ctx) { - // Forbid overrides if the items came from an explicit list - _ if ctx.gen_kind == GeneratorKind::List => (), CheckAction::AssertSuccess => (), CheckAction::AssertFailure(msg) => assert_failure_msg = Some(msg), CheckAction::Custom(res) => return res, @@ -385,23 +356,7 @@ where } } - res.with_context(|| { - format!( - "\ - \n input: {input:?}\ - \n as hex: {ihex}\ - \n as bits: {ibits}\ - \n expected: {expected:<22?} {exphex} {expbits}\ - \n actual: {actual:<22?} {acthex} {actbits}\ - ", - ihex = input.hexf(), - ibits = input.hex(), - exphex = expected.hexf(), - expbits = expected.hex(), - actbits = actual.hex(), - acthex = actual.hexf(), - ) - }) + res.with_context(|| make_error_message(input, expected, actual, "", "")) } impl_float!(f32, f64); @@ -420,30 +375,27 @@ macro_rules! impl_tuples { $( impl CheckOutput for ($a, $b) where - Input: Hex + fmt::Debug, + Input: Copy + DisplayHex + fmt::Debug, SpecialCase: MaybeOverride, - { + { fn validate<'a>( self, expected: Self, input: Input, ctx: &CheckCtx, ) -> TestResult { - self.0.validate(expected.0, input, ctx) + self.0 + .validate(expected.0, input, ctx) .and_then(|()| self.1.validate(expected.1, input, ctx)) - .with_context(|| format!( - "full context:\ - \n input: {input:?} {ibits}\ - \n as hex: {ihex}\ - \n as bits: {ibits}\ - \n expected: {expected:?} {expbits}\ - \n actual: {self:?} {actbits}\ - ", - ihex = input.hexf(), - ibits = input.hex(), - expbits = expected.hex(), - actbits = self.hex(), - )) + .with_context(|| { + make_error_message( + input, + expected, + self, + "full context:", + "", + ) + }) } } )* @@ -451,6 +403,22 @@ macro_rules! impl_tuples { } impl_tuples!( + (i32, i32); + (i64, i64); + (i128, i128); + + (u32, u32); + (u64, u64); + (u128, u128); + + (i32, bool); + (i64, bool); + (i128, bool); + + (u32, bool); + (u64, bool); + (u128, bool); + (f32, i32); (f64, i32); (f32, f32); @@ -468,3 +436,33 @@ impl_tuples!( (f128, i32); (f128, f128); ); + +fn make_error_message( + input: I, + expected: E, + actual: A, + pre_msg: &str, + post_msg: &str, +) -> String +where + I: Copy + fmt::Debug + DisplayHex, + E: Copy + fmt::Debug + DisplayHex, + A: Copy + fmt::Debug + DisplayHex, +{ + let pre_pad = if pre_msg.is_empty() { "" } else { "\n " }; + let post_pad = if post_msg.is_empty() { "" } else { "\n " }; + format!( + "\ + {pre_pad}{pre_msg}\ + \n input: {input:?}\ + \n as hex: {ihex}\ + \n as bits: {ihex:-}\ + \n expected: {expected:<16?} {exphex} {exphex:-}\ + \n actual: {actual:<16?} {acthex} {acthex:-}\ + {post_pad}{post_msg}\ + ", + ihex = Hex(input), + exphex = Hex(expected), + acthex = Hex(actual), + ) +} diff --git a/compiler-builtins/libm-test/tests/check_coverage.rs b/compiler-builtins/libm-test/tests/check_coverage.rs index 3b445a3de9da1..384fef19daf8c 100644 --- a/compiler-builtins/libm-test/tests/check_coverage.rs +++ b/compiler-builtins/libm-test/tests/check_coverage.rs @@ -39,7 +39,14 @@ fn test_for_each_function_all_included() { `ALL_OPERATIONS` (in `libm-macros`)." ); } - assert_eq!(all_functions, tested); + + // FIXME: This needs to be updated to interact with compiler-builtins + // assert_eq!( + // all_functions, + // tested, + // "difference: {:?}", + // tested.difference(&all_functions) + // ); } #[test] diff --git a/compiler-builtins/libm-test/tests/compare_built_musl.rs b/compiler-builtins/libm-test/tests/compare_built_musl.rs index 86f3b8b711ea7..5e9ead0473c2e 100644 --- a/compiler-builtins/libm-test/tests/compare_built_musl.rs +++ b/compiler-builtins/libm-test/tests/compare_built_musl.rs @@ -78,6 +78,7 @@ libm_macros::for_each_function! { attributes: [], // Not provided by musl skip_f16_f128: true, + skip_builtins: true, skip: [ // TODO integer inputs jn, diff --git a/compiler-builtins/libm-test/tests/u256.rs b/compiler-builtins/libm-test/tests/u256.rs index e697945f47971..a17e16f8f429b 100644 --- a/compiler-builtins/libm-test/tests/u256.rs +++ b/compiler-builtins/libm-test/tests/u256.rs @@ -2,14 +2,15 @@ //! routines, so this only does a few million fuzz iterations against GMP. #![cfg(feature = "build-mpfr")] +#![allow(unstable_name_collisions)] // for the integer_widen_truncate feature use std::sync::LazyLock; -use libm::support::{HInt, u256}; +use libm::support::{HInt, i256, u256}; type BigInt = rug::Integer; -use libm_test::bigint_fuzz_iteration_count; use libm_test::generate::random::SEED; +use libm_test::{MinInt, bigint_fuzz_iteration_count}; use rand::{RngExt, SeedableRng}; use rand_chacha::ChaCha8Rng; use rug::Assign; @@ -19,56 +20,162 @@ use rug::ops::NotAssign; static BIGINT_U256_MAX: LazyLock = LazyLock::new(|| BigInt::from_digits(&[u128::MAX, u128::MAX], Order::Lsf)); -/// Copied from the test module. -fn hexu(v: u256) -> String { - format!("0x{:032x}{:032x}", v.hi, v.lo) -} - fn random_u256(rng: &mut ChaCha8Rng) -> u256 { let lo: u128 = rng.random(); let hi: u128 = rng.random(); u256 { lo, hi } } -fn assign_bigint(bx: &mut BigInt, x: u256) { - bx.assign_digits(&[x.lo, x.hi], Order::Lsf); +fn random_i256(rng: &mut ChaCha8Rng) -> i256 { + random_u256(rng).signed() +} + +fn assign_bigint_u256(bx: &mut BigInt, x: u256) { + bx.assign(x.hi); + *bx <<= 128; + *bx += x.lo; } -fn from_bigint(bx: &mut BigInt) -> u256 { +fn assign_bigint_i256(bx: &mut BigInt, x: i256) { + bx.assign(x.hi); + *bx <<= 128; + *bx += x.lo; +} + +/// Note that this destroys the result in `bx`. +fn from_bigint_u256(bx: &mut BigInt) -> u256 { // Truncate so the result fits into `[u128; 2]`. This makes all ops overflowing. *bx &= &*BIGINT_U256_MAX; let mut bres = [0u128, 0]; bx.write_digits(&mut bres, Order::Lsf); - bx.assign(0); + bx.assign(0); // prevent accidental reuse u256 { lo: bres[0], hi: bres[1], } } -fn check_one( - x: impl FnOnce() -> String, - y: impl FnOnce() -> Option, - actual: u256, - expected: &mut BigInt, -) { - let expected = from_bigint(expected); +/// Note that this destroys the result in `bx`. +fn from_bigint_i256(bx: &mut BigInt) -> i256 { + // Truncate so the result fits into `[u128; 2]`. This makes all ops overflowing. + *bx &= &*BIGINT_U256_MAX; + let lo = bx.to_u128_wrapping(); + *bx >>= 128; + let hi = bx.to_i128_wrapping(); + bx.assign(0); // prevent accidental reuse + i256 { hi, lo } +} + +#[track_caller] +fn assert_same_u256(msg: impl Fn() -> String, actual: u256, expected_big: &mut BigInt) { + let expected = from_bigint_u256(expected_big); + if actual != expected { + let mut act_big = BigInt::new(); + assign_bigint_u256(&mut act_big, actual); + panic!( + "Test failure: {}\n\ + actual: {act_big}\n\ + expected: {expected_big}\n\ + actual: {actual:#x}\n\ + expected: {expected:#x}\ + ", + msg() + ) + } +} + +#[track_caller] +fn assert_same_i256(msg: impl Fn() -> String, actual: i256, expected_big: &mut BigInt) { + let expected = from_bigint_i256(expected_big); if actual != expected { - let xmsg = x(); - let ymsg = y().map(|y| format!("y: {y}\n")).unwrap_or_default(); + let mut act_big = BigInt::new(); + assign_bigint_i256(&mut act_big, actual); panic!( - "Results do not match\n\ - input: {xmsg}\n\ - {ymsg}\ - actual: {}\n\ - expected: {}\ + "Test failure: {}\n\ + actual: {act_big}\n\ + expected: {expected_big}\n\ + actual: {actual:#x}\n\ + expected: {expected:#x}\ ", - hexu(actual), - hexu(expected), + msg() ) } } +/// Verify the test setup. +#[test] +fn mp_u256_roundtrip() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_u256(&mut rng); + assign_bigint_u256(&mut bx, x); + assert_eq!(from_bigint_u256(&mut bx), x); + } + + // Check wraparound + assign_bigint_u256(&mut bx, u256::MAX); + bx += 1; + assert_eq!(from_bigint_u256(&mut bx), u256::MIN); + assign_bigint_u256(&mut bx, u256::MIN); + bx -= 1; + assert_eq!(from_bigint_u256(&mut bx), u256::MAX); +} + +/// Verify the test setup. +#[test] +fn mp_i256_roundtrip() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assert_eq!(from_bigint_i256(&mut bx), x); + } + + // Check wraparound + assign_bigint_i256(&mut bx, i256::MAX); + bx += 1; + assert_eq!(from_bigint_i256(&mut bx), i256::MIN); + assign_bigint_i256(&mut bx, i256::MIN); + bx -= 1; + assert_eq!(from_bigint_i256(&mut bx), i256::MAX); +} + +#[test] +fn mp_u256_ord() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_u256(&mut rng); + let y = random_u256(&mut rng); + assign_bigint_u256(&mut bx, x); + assign_bigint_u256(&mut by, y); + + assert_eq!(x.cmp(&y), bx.cmp(&by), "cmp({x:#x}, {y:#x})"); + } +} + +#[test] +fn mp_i256_ord() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let y = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assign_bigint_i256(&mut by, y); + + assert_eq!(x.cmp(&y), bx.cmp(&by), "cmp({x:#x}, {y:#x})"); + } +} + #[test] fn mp_u256_bitor() { let mut rng = ChaCha8Rng::from_seed(*SEED); @@ -78,11 +185,28 @@ fn mp_u256_bitor() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let y = random_u256(&mut rng); - assign_bigint(&mut bx, x); - assign_bigint(&mut by, y); + assign_bigint_u256(&mut bx, x); + assign_bigint_u256(&mut by, y); + let actual = x | y; + bx |= &by; + assert_same_u256(|| format!("{x:#x} ^ {y:#x}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_bitor() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let y = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assign_bigint_i256(&mut by, y); let actual = x | y; bx |= &by; - check_one(|| hexu(x), || Some(hexu(y)), actual, &mut bx); + assert_same_i256(|| format!("{x:#x} ^ {y:#x}"), actual, &mut bx); } } @@ -93,10 +217,24 @@ fn mp_u256_not() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); - assign_bigint(&mut bx, x); + assign_bigint_u256(&mut bx, x); + let actual = !x; + bx.not_assign(); + assert_same_u256(|| format!("!{x:#x}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_not() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); let actual = !x; bx.not_assign(); - check_one(|| hexu(x), || None, actual, &mut bx); + assert_same_i256(|| format!("!{x:#x}"), actual, &mut bx); } } @@ -109,8 +247,9 @@ fn mp_u256_add() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let y = random_u256(&mut rng); - assign_bigint(&mut bx, x); - assign_bigint(&mut by, y); + assign_bigint_u256(&mut bx, x); + assign_bigint_u256(&mut by, y); + // Emulate wrapping semantics with panicking ops let actual = if u256::MAX - x >= y { x + y } else { @@ -119,7 +258,35 @@ fn mp_u256_add() { y - (u256::MAX - x) - 1_u128.widen() }; bx += &by; - check_one(|| hexu(x), || Some(hexu(y)), actual, &mut bx); + assert_same_u256(|| format!("{x:#x} + {y:#x}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_add() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let y = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assign_bigint_i256(&mut by, y); + + // Emulate wrapping semantics with panicking ops + let actual = if x > i256::ZERO && y > i256::MAX - x { + // Overflow condition + (x + i256::MIN) + (y + i256::MIN) + } else if x < i256::ZERO && y < i256::MIN - x { + // Underflow condition + (x - i256::MIN) + (y - i256::MIN) + } else { + // Otherwise there is no overflow + x + y + }; + bx += &by; + assert_same_i256(|| format!("{x:#x} + {y:#x}"), actual, &mut bx); } } @@ -132,15 +299,41 @@ fn mp_u256_sub() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let y = random_u256(&mut rng); - assign_bigint(&mut bx, x); - assign_bigint(&mut by, y); + assign_bigint_u256(&mut bx, x); + assign_bigint_u256(&mut by, y); // since the operators (may) panic on overflow, // we should test something that doesn't let actual = if x >= y { x - y } else { y - x }; bx -= &by; bx.abs_mut(); - check_one(|| hexu(x), || Some(hexu(y)), actual, &mut bx); + assert_same_u256(|| format!("{x:#x} - {y:#x}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_sub() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + let mut by = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let y = random_i256(&mut rng); + assign_bigint_i256(&mut bx, x); + assign_bigint_i256(&mut by, y); + dbg!(&bx, &by); + + // Emulate wrapping semantics with panicking ops + let actual = if y > i256::ZERO && x < i256::MIN + y { + (x - i256::MIN) - (y + i256::MIN) + } else if y < i256::ZERO && x > i256::MAX + y { + (x + i256::MIN) - (y - i256::MIN) + } else { + x - y + }; + bx -= &by; + assert_same_i256(|| format!("{x:#x} - {y:#x}"), actual, &mut bx); } } @@ -152,10 +345,25 @@ fn mp_u256_shl() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let shift: u32 = rng.random_range(0..256); - assign_bigint(&mut bx, x); + assign_bigint_u256(&mut bx, x); + let actual = x << shift; + bx <<= shift; + assert_same_u256(|| format!("{x:#x} << {shift}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_shl() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let shift: u32 = rng.random_range(0..256); + assign_bigint_i256(&mut bx, x); let actual = x << shift; bx <<= shift; - check_one(|| hexu(x), || Some(shift.to_string()), actual, &mut bx); + assert_same_i256(|| format!("{x:#x} << {shift}"), actual, &mut bx); } } @@ -167,15 +375,30 @@ fn mp_u256_shr() { for _ in 0..bigint_fuzz_iteration_count() { let x = random_u256(&mut rng); let shift: u32 = rng.random_range(0..256); - assign_bigint(&mut bx, x); + assign_bigint_u256(&mut bx, x); + let actual = x >> shift; + bx >>= shift; + assert_same_u256(|| format!("{x:#x} >> {shift}"), actual, &mut bx); + } +} + +#[test] +fn mp_i256_shr() { + let mut rng = ChaCha8Rng::from_seed(*SEED); + let mut bx = BigInt::new(); + + for _ in 0..bigint_fuzz_iteration_count() { + let x = random_i256(&mut rng); + let shift: u32 = rng.random_range(0..256); + assign_bigint_i256(&mut bx, x); let actual = x >> shift; bx >>= shift; - check_one(|| hexu(x), || Some(shift.to_string()), actual, &mut bx); + assert_same_i256(|| format!("{x:#x} >> {shift}"), actual, &mut bx); } } #[test] -fn mp_u256_widen_mul() { +fn mp_u256_u128_widen_mul() { let mut rng = ChaCha8Rng::from_seed(*SEED); let mut bx = BigInt::new(); let mut by = BigInt::new(); @@ -187,9 +410,8 @@ fn mp_u256_widen_mul() { by.assign(y); let actual = x.widen_mul(y); bx *= &by; - check_one( - || format!("{x:#034x}"), - || Some(format!("{y:#034x}")), + assert_same_u256( + || format!("{x:#034x}.widen_mul({y:#034x})"), actual, &mut bx, ); diff --git a/compiler-builtins/libm/Cargo.toml b/compiler-builtins/libm/Cargo.toml index 28e594dca1f91..8d7fe9515e4d1 100644 --- a/compiler-builtins/libm/Cargo.toml +++ b/compiler-builtins/libm/Cargo.toml @@ -38,16 +38,17 @@ unstable-public-internals = [] # Enable the nightly-only `f16` and `f128`. unstable-float = [] -# Used to prevent using any intrinsics or arch-specific code. -# -# HACK: this is a negative feature which is generally a bad idea in Cargo, but -# we need it to be able to forbid other features when this crate is used in -# Rust dependencies. Setting this overrides all features that may enable -# hard float operations. +# DEPRECATED: This feature is kept around for compatibility reasons but +# does not do anything. +# FIXME(1.0): remove this feature. force-soft-floats = [] [lints.rust] unexpected_cfgs = { level = "warn", check-cfg = [ - # compiler-builtins sets this feature, but we use it in `libm` + # compiler-builtins sets these features, but we use them in `libm` 'cfg(feature, values("compiler-builtins"))', + 'cfg(feature, values("unmangled-names"))', ] } + +[package.metadata.docs.rs] +features = ["unstable-float"] diff --git a/compiler-builtins/libm/build.rs b/compiler-builtins/libm/build.rs index 07d08ed4364db..584e6a25da270 100644 --- a/compiler-builtins/libm/build.rs +++ b/compiler-builtins/libm/build.rs @@ -1,18 +1,11 @@ -use std::env; - mod configure; -fn main() { - let cfg = configure::Config::from_env(); +use configure::{Config, Library}; +fn main() { println!("cargo:rerun-if-changed=build.rs"); println!("cargo:rerun-if-changed=configure.rs"); - println!("cargo:rustc-check-cfg=cfg(assert_no_panic)"); - - // If set, enable `no-panic`. Requires LTO (`release-opt` profile). - if env::var("ENSURE_NO_PANIC").is_ok() { - println!("cargo:rustc-cfg=assert_no_panic"); - } - configure::emit_libm_config(&cfg); + let cfg = Config::from_env(Library::Libm); + configure::emit(&cfg); } diff --git a/compiler-builtins/libm/configure.rs b/compiler-builtins/libm/configure.rs index ee65a3a8d6243..ec4e46c391042 100644 --- a/compiler-builtins/libm/configure.rs +++ b/compiler-builtins/libm/configure.rs @@ -1,16 +1,23 @@ -// Configuration shared with both libm and libm-test +//! Common configuration shared by multiple crates in the workspace. -use std::env; +use std::env::{self, VarError}; use std::path::PathBuf; +use std::sync::atomic::AtomicBool; +use std::sync::atomic::Ordering::Relaxed; + +/// Read from env, print more debug output via `cargo:warning` if set. +static VERBOSE_BUILD: AtomicBool = AtomicBool::new(false); #[derive(Debug)] #[allow(dead_code)] pub struct Config { + pub library: Library, pub manifest_dir: PathBuf, pub out_dir: PathBuf, pub opt_level: String, pub cargo_features: Vec, pub target_triple: String, + pub target_triple_split: Vec, pub target_arch: String, pub target_env: String, pub target_families: Vec, @@ -23,8 +30,14 @@ pub struct Config { } impl Config { - pub fn from_env() -> Self { + pub fn from_env(library: Library) -> Self { + println!("cargo:rerun-if-env-changed=LIBM_BUILD_VERBOSE"); + if env_flag("LIBM_BUILD_VERBOSE") { + VERBOSE_BUILD.store(true, Relaxed); + } + let target_triple = env::var("TARGET").unwrap(); + let target_triple_split = target_triple.split('-').map(ToOwned::to_owned).collect(); let target_families = env::var("CARGO_CFG_TARGET_FAMILY") .map(|feats| feats.split(',').map(ToOwned::to_owned).collect()) .unwrap_or_default(); @@ -35,9 +48,16 @@ impl Config { .filter_map(|(name, _value)| name.strip_prefix("CARGO_FEATURE_").map(ToOwned::to_owned)) .map(|s| s.to_lowercase().replace("_", "-")) .collect(); + if VERBOSE_BUILD.load(Relaxed) { + for feature in &cargo_features { + println!("cargo:warning=feature `{feature}` enabled"); + } + } Self { + library, target_triple, + target_triple_split, manifest_dir: PathBuf::from(env::var("CARGO_MANIFEST_DIR").unwrap()), out_dir: PathBuf::from(env::var("OUT_DIR").unwrap()), opt_level: env::var("OPT_LEVEL").unwrap(), @@ -55,70 +75,98 @@ impl Config { reliable_f16: env::var_os("CARGO_CFG_TARGET_HAS_RELIABLE_F16").is_some(), } } -} -/// Libm gets most config options made available. -#[allow(dead_code)] -pub fn emit_libm_config(cfg: &Config) { - emit_intrinsics_cfg(); - emit_arch_cfg(); - emit_optimization_cfg(cfg); - emit_cfg_shorthands(cfg); - emit_cfg_env(cfg); - emit_f16_f128_cfg(cfg); + #[allow(dead_code)] + pub fn has_target_feature(&self, feature: &str) -> bool { + self.target_features.iter().any(|f| f == feature) + } } -/// Tests don't need most feature-related config. +/// The library that is setting this configuration #[allow(dead_code)] -pub fn emit_test_config(cfg: &Config) { - emit_optimization_cfg(cfg); - emit_cfg_shorthands(cfg); - emit_cfg_env(cfg); - emit_f16_f128_cfg(cfg); +#[derive(Debug)] +pub enum Library { + BuiltinsTest, + BuiltinsTestIntrinsics, + CompilerBuiltins, + Libm, + LibmTest, + Util, } -/// Simplify the feature logic for enabling intrinsics so code only needs to use -/// `cfg(intrinsics_enabled)`. -fn emit_intrinsics_cfg() { - println!("cargo:rustc-check-cfg=cfg(intrinsics_enabled)"); +#[allow(unexpected_cfgs)] // Not all crates use all these features +pub fn emit(cfg: &Config) { + let split = &cfg.target_triple_split; - // Disabled by default; `unstable-intrinsics` enables again; `force-soft-floats` overrides - // to disable. - if cfg!(feature = "unstable-intrinsics") && !cfg!(feature = "force-soft-floats") { - println!("cargo:rustc-cfg=intrinsics_enabled"); - } -} + let unstable_float = cfg!(feature = "unstable-float"); -/// Simplify the feature logic for enabling arch-specific features so code only needs to use -/// `cfg(arch_enabled)`. -fn emit_arch_cfg() { - println!("cargo:rustc-check-cfg=cfg(arch_enabled)"); + // Intrinsics may include `core::arch` use, so also gate it under `arch`. + let intrinsics_enabled = cfg!(feature = "unstable-intrinsics") && cfg!(feature = "arch"); - // Enabled by default via the "arch" feature, `force-soft-floats` overrides to disable. - if cfg!(feature = "arch") && !cfg!(feature = "force-soft-floats") { - println!("cargo:rustc-cfg=arch_enabled"); - } -} + // Some tests are extremely slow. Emit a config option based on optimization level. + let opt = !matches!(cfg.opt_level.as_str(), "0" | "1"); -/// Some tests are extremely slow. Emit a config option based on optimization level. -fn emit_optimization_cfg(cfg: &Config) { - println!("cargo:rustc-check-cfg=cfg(optimizations_enabled)"); + // To compile builtins-test-intrinsics for thumb targets, where there is no libc + let thumb = split[0].starts_with("thumb"); - if !matches!(cfg.opt_level.as_str(), "0" | "1") { - println!("cargo:rustc-cfg=optimizations_enabled"); - } -} + // compiler-rt `cfg`s away some intrinsics for thumbv6m and thumbv8m.base because + // these targets do not have full Thumb-2 support but only original Thumb-1. + // We have to cfg our code accordingly. + let thumb_1 = split[0] == "thumbv6m" || split[0] == "thumbv8m.base"; + + // Shorthand to detect i586 targets + let x86_no_sse2 = cfg.target_arch == "x86" && !cfg.target_features.iter().any(|f| f == "sse2"); -/// Provide an alias for common longer config combinations. -fn emit_cfg_shorthands(cfg: &Config) { - println!("cargo:rustc-check-cfg=cfg(x86_no_sse)"); - if cfg.target_arch == "x86" && !cfg.target_features.iter().any(|f| f == "sse") { - // Shorthand to detect i586 targets - println!("cargo:rustc-cfg=x86_no_sse"); + // If set, enable `no-panic` for `libm`. Requires LTO (`release-opt` profile). + let assert_no_panic = env_flag("ENSURE_NO_PANIC"); + + // Arch shorthand config is used in most crates. + set_cfg("thumb", thumb); + set_cfg("thumb_1", thumb_1); + set_cfg("x86_no_sse2", x86_no_sse2); + + match cfg.library { + Library::CompilerBuiltins => { + // libm config. Intrinsics are always enabled when a part of c-b. + set_cfg("assert_no_panic", assert_no_panic); + set_cfg("intrinsics_enabled", true); + set_cfg("optimizations_enabled", opt); + + // Not all backends support `f16` and `f128` to the same level on all architectures, + // so we need to disable things if the compiler may crash. See configuration at: + // * https://github.com/rust-lang/rust/blob/c65dccabacdfd6c8a7f7439eba13422fdd89b91e/compiler/rustc_codegen_llvm/src/llvm_util.rs#L367-L432 + // * https://github.com/rust-lang/rustc_codegen_gcc/blob/4b5c44b14166083eef8d71f15f5ea1f53fc976a0/src/lib.rs#L496-L507 + // * https://github.com/rust-lang/rustc_codegen_cranelift/blob/c713ffab3c6e28ab4b4dd4e392330f786ea657ad/src/lib.rs#L196-L226 + set_cfg("f16_enabled", cfg.reliable_f16); + set_cfg("f128_enabled", cfg.reliable_f128); + } + Library::BuiltinsTest => { + set_cfg("f16_enabled", cfg.reliable_f16); + set_cfg("f128_enabled", cfg.reliable_f128); + } + Library::BuiltinsTestIntrinsics => { + set_cfg("f16_enabled", cfg.reliable_f16); + set_cfg("f128_enabled", cfg.reliable_f128); + } + Library::Libm | Library::Util => { + set_cfg("assert_no_panic", assert_no_panic); + set_cfg("intrinsics_enabled", intrinsics_enabled); + set_cfg("optimizations_enabled", opt); + + set_cfg("f16_enabled", unstable_float && cfg.reliable_f16); + set_cfg("f128_enabled", unstable_float && cfg.reliable_f128); + } + Library::LibmTest => { + set_cfg("optimizations_enabled", opt); + emit_cfg_env(cfg); + + set_cfg("f16_enabled", unstable_float && cfg.reliable_f16); + set_cfg("f128_enabled", unstable_float && cfg.reliable_f128); + } } } -/// Reemit config that we make use of for test logging. +/// Re-emit config that we make use of for test logging. fn emit_cfg_env(cfg: &Config) { println!( "cargo:rustc-env=CFG_CARGO_FEATURES={:?}", @@ -131,25 +179,24 @@ fn emit_cfg_env(cfg: &Config) { ); } -/// Configure whether or not `f16` and `f128` support should be enabled. -fn emit_f16_f128_cfg(cfg: &Config) { - println!("cargo:rustc-check-cfg=cfg(f16_enabled)"); - println!("cargo:rustc-check-cfg=cfg(f128_enabled)"); - - // `unstable-float` enables these features. - if !cfg!(feature = "unstable-float") { +/// Emit a check-cfg directive and enable the cfg if `set` is `true`. +pub fn set_cfg(name: &str, set: bool) { + println!("cargo:rustc-check-cfg=cfg({name})"); + if !set { return; } - - /* See the compiler-builtins configure file for info about the meaning of these options */ - - println!("cargo:rustc-check-cfg=cfg(f16_enabled)"); - if cfg.reliable_f16 { - println!("cargo:rustc-cfg=f16_enabled"); + if VERBOSE_BUILD.load(Relaxed) { + println!("cargo:warning=setting config `{name}`"); } + println!("cargo:rustc-cfg={name}"); +} - println!("cargo:rustc-check-cfg=cfg(f128_enabled)"); - if cfg.reliable_f128 { - println!("cargo:rustc-cfg=f128_enabled"); +/// Return true if the env is set to a value other than `0`. +pub fn env_flag(key: &str) -> bool { + match env::var(key) { + Ok(x) if x == "0" => false, + Err(VarError::NotPresent) => false, + Err(VarError::NotUnicode(_)) => panic!("non-unicode var for `{key}`"), + Ok(_) => true, } } diff --git a/compiler-builtins/libm/src/libm_helper.rs b/compiler-builtins/libm/src/libm_helper.rs index 1e6e0beb3e3e0..f2c4daed561ec 100644 --- a/compiler-builtins/libm/src/libm_helper.rs +++ b/compiler-builtins/libm/src/libm_helper.rs @@ -195,6 +195,7 @@ libm_helper! { (fn fabs(x: f16) -> (f16); => fabsf16); (fn fdim(x: f16, y: f16) -> (f16); => fdimf16); (fn floor(x: f16) -> (f16); => floorf16); + (fn fma(x: f16, y: f16, z: f16) -> (f16); => fmaf16); (fn fmax(x: f16, y: f16) -> (f16); => fmaxf16); (fn fmaximum_num(x: f16, y: f16) -> (f16); => fmaximum_numf16); (fn fmaximumf16(x: f16, y: f16) -> (f16); => fmaximumf16); diff --git a/compiler-builtins/libm/src/math/approx/cbrtf64.rs b/compiler-builtins/libm/src/math/approx/cbrtf64.rs new file mode 100644 index 0000000000000..7b371feb96b6d --- /dev/null +++ b/compiler-builtins/libm/src/math/approx/cbrtf64.rs @@ -0,0 +1,113 @@ +/* origin: FreeBSD /usr/src/lib/msun/src/s_cbrt.c */ +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + * + * Optimized by Bruce D. Evans. + */ +/* cbrt(x) + * Return cube root of x + */ + +use core::f64; + +const B1: u32 = 715094163; /* B1 = (1023-1023/3-0.03306235651)*2**20 */ +const B2: u32 = 696219795; /* B2 = (1023-1023/3-54/3-0.03306235651)*2**20 */ + +/* |1/cbrt(x) - p(x)| < 2**-23.5 (~[-7.93e-8, 7.929e-8]). */ +const P0: f64 = 1.87595182427177009643; /* 0x3ffe03e6, 0x0f61e692 */ +const P1: f64 = -1.88497979543377169875; /* 0xbffe28e0, 0x92f02420 */ +const P2: f64 = 1.621429720105354466140; /* 0x3ff9f160, 0x4a49d6c2 */ +const P3: f64 = -0.758397934778766047437; /* 0xbfe844cb, 0xbee751d9 */ +const P4: f64 = 0.145996192886612446982; /* 0x3fc2b000, 0xd4e4edd7 */ + +/// Cube root (f64) +/// +/// Computes the cube root of the argument. +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn cbrtf64(x: f64) -> f64 { + let x1p54 = f64::from_bits(0x4350000000000000); // 0x1p54 === 2 ^ 54 + + let mut ui: u64 = x.to_bits(); + let mut r: f64; + let s: f64; + let mut t: f64; + let w: f64; + let mut hx: u32 = (ui >> 32) as u32 & 0x7fffffff; + + if hx >= 0x7ff00000 { + /* cbrt(NaN,INF) is itself */ + return x + x; + } + + /* + * Rough cbrt to 5 bits: + * cbrt(2**e*(1+m) ~= 2**(e/3)*(1+(e%3+m)/3) + * where e is integral and >= 0, m is real and in [0, 1), and "/" and + * "%" are integer division and modulus with rounding towards minus + * infinity. The RHS is always >= the LHS and has a maximum relative + * error of about 1 in 16. Adding a bias of -0.03306235651 to the + * (e%3+m)/3 term reduces the error to about 1 in 32. With the IEEE + * floating point representation, for finite positive normal values, + * ordinary integer divison of the value in bits magically gives + * almost exactly the RHS of the above provided we first subtract the + * exponent bias (1023 for doubles) and later add it back. We do the + * subtraction virtually to keep e >= 0 so that ordinary integer + * division rounds towards minus infinity; this is also efficient. + */ + if hx < 0x00100000 { + /* zero or subnormal? */ + ui = (x * x1p54).to_bits(); + hx = (ui >> 32) as u32 & 0x7fffffff; + if hx == 0 { + return x; /* cbrt(0) is itself */ + } + hx = hx / 3 + B2; + } else { + hx = hx / 3 + B1; + } + ui &= 1 << 63; + ui |= (hx as u64) << 32; + t = f64::from_bits(ui); + + /* + * New cbrt to 23 bits: + * cbrt(x) = t*cbrt(x/t**3) ~= t*P(t**3/x) + * where P(r) is a polynomial of degree 4 that approximates 1/cbrt(r) + * to within 2**-23.5 when |r - 1| < 1/10. The rough approximation + * has produced t such than |t/cbrt(x) - 1| ~< 1/32, and cubing this + * gives us bounds for r = t**3/x. + * + * Try to optimize for parallel evaluation as in __tanf.c. + */ + r = (t * t) * (t / x); + t = t * ((P0 + r * (P1 + r * P2)) + ((r * r) * r) * (P3 + r * P4)); + + /* + * Round t away from zero to 23 bits (sloppily except for ensuring that + * the result is larger in magnitude than cbrt(x) but not much more than + * 2 23-bit ulps larger). With rounding towards zero, the error bound + * would be ~5/6 instead of ~4/6. With a maximum error of 2 23-bit ulps + * in the rounded t, the infinite-precision error in the Newton + * approximation barely affects third digit in the final error + * 0.667; the error in the rounded t can be up to about 3 23-bit ulps + * before the final error is larger than 0.667 ulps. + */ + ui = t.to_bits(); + ui = (ui + 0x80000000) & 0xffffffffc0000000; + t = f64::from_bits(ui); + + /* one step Newton iteration to 53 bits with error < 0.667 ulps */ + s = t * t; /* t*t is exact */ + r = x / s; /* error <= 0.5 ulps; |r| < |t| */ + w = t + t; /* t+t is exact */ + r = (r - t) / (w + r); /* r-t is exact; w+r ~= 3*t */ + t = t + t * r; /* error <= 0.5 + 0.5/3 + epsilon */ + t +} diff --git a/compiler-builtins/libm/src/math/approx/hypot.rs b/compiler-builtins/libm/src/math/approx/hypot.rs new file mode 100644 index 0000000000000..c0b2a19370cd7 --- /dev/null +++ b/compiler-builtins/libm/src/math/approx/hypot.rs @@ -0,0 +1,72 @@ +use super::sqrt; + +const SPLIT: f64 = 134217728. + 1.; // 0x1p27 + 1 === (2 ^ 27) + 1 + +fn sq(x: f64) -> (f64, f64) { + let xh: f64; + let xl: f64; + let xc: f64; + + xc = x * SPLIT; + xh = x - xc + xc; + xl = x - xh; + let hi = x * x; + let lo = xh * xh - hi + 2. * xh * xl + xl * xl; + (hi, lo) +} + +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn hypot(mut x: f64, mut y: f64) -> f64 { + let x1p700 = f64::from_bits(0x6bb0000000000000); // 0x1p700 === 2 ^ 700 + let x1p_700 = f64::from_bits(0x1430000000000000); // 0x1p-700 === 2 ^ -700 + + let mut uxi = x.to_bits(); + let mut uyi = y.to_bits(); + let uti; + let ex: i64; + let ey: i64; + let mut z: f64; + + /* arrange |x| >= |y| */ + uxi &= -1i64 as u64 >> 1; + uyi &= -1i64 as u64 >> 1; + if uxi < uyi { + uti = uxi; + uxi = uyi; + uyi = uti; + } + + /* special cases */ + ex = (uxi >> 52) as i64; + ey = (uyi >> 52) as i64; + x = f64::from_bits(uxi); + y = f64::from_bits(uyi); + /* note: hypot(inf,nan) == inf */ + if ey == 0x7ff { + return y; + } + if ex == 0x7ff || uyi == 0 { + return x; + } + /* note: hypot(x,y) ~= x + y*y/x/2 with inexact for small y/x */ + /* 64 difference is enough for ld80 double_t */ + if ex - ey > 64 { + return x + y; + } + + /* precise sqrt argument in nearest rounding mode without overflow */ + /* xh*xh must not overflow and xl*xl must not underflow in sq */ + z = 1.; + if ex > 0x3ff + 510 { + z = x1p700; + x *= x1p_700; + y *= x1p_700; + } else if ey < 0x3ff - 450 { + z = x1p_700; + x *= x1p700; + y *= x1p700; + } + let (hx, lx) = sq(x); + let (hy, ly) = sq(y); + z * sqrt(ly + lx + hy + hx) +} diff --git a/compiler-builtins/libm/src/math/approx/mod.rs b/compiler-builtins/libm/src/math/approx/mod.rs new file mode 100644 index 0000000000000..da0d0bf39efc4 --- /dev/null +++ b/compiler-builtins/libm/src/math/approx/mod.rs @@ -0,0 +1,8 @@ +//! Approximate implementations. +//! +//! These functions may be smaller or faster than those in the main `math` module, but will +//! not be as accurate. + +mod cbrtf64; + +pub use cbrtf64::cbrtf64; diff --git a/compiler-builtins/libm/src/math/arch/aarch64.rs b/compiler-builtins/libm/src/math/arch/aarch64.rs deleted file mode 100644 index 8896804b50403..0000000000000 --- a/compiler-builtins/libm/src/math/arch/aarch64.rs +++ /dev/null @@ -1,121 +0,0 @@ -//! Architecture-specific support for aarch64 with neon. - -use core::arch::asm; - -pub fn fma(mut x: f64, y: f64, z: f64) -> f64 { - // SAFETY: `fmadd` is available with neon and has no side effects. - unsafe { - asm!( - "fmadd {x:d}, {x:d}, {y:d}, {z:d}", - x = inout(vreg) x, - y = in(vreg) y, - z = in(vreg) z, - options(nomem, nostack, pure) - ); - } - x -} - -pub fn fmaf(mut x: f32, y: f32, z: f32) -> f32 { - // SAFETY: `fmadd` is available with neon and has no side effects. - unsafe { - asm!( - "fmadd {x:s}, {x:s}, {y:s}, {z:s}", - x = inout(vreg) x, - y = in(vreg) y, - z = in(vreg) z, - options(nomem, nostack, pure) - ); - } - x -} - -// NB: `frintx` is technically the correct instruction for C's `rint`. However, in Rust (and LLVM -// by default), `rint` is identical to `roundeven` (no fpenv interaction) so we use the -// side-effect-free `frintn`. -// -// In general, C code that calls Rust's libm should assume that fpenv is ignored. - -pub fn rint(mut x: f64) -> f64 { - // SAFETY: `frintn` is available with neon and has no side effects. - // - // `frintn` is always round-to-nearest which does not match the C specification, but Rust does - // not support rounding modes. - unsafe { - asm!( - "frintn {x:d}, {x:d}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -pub fn rintf(mut x: f32) -> f32 { - // SAFETY: `frintn` is available with neon and has no side effects. - // - // `frintn` is always round-to-nearest which does not match the C specification, but Rust does - // not support rounding modes. - unsafe { - asm!( - "frintn {x:s}, {x:s}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -#[cfg(all(f16_enabled, target_feature = "fp16"))] -pub fn rintf16(mut x: f16) -> f16 { - // SAFETY: `frintn` is available for `f16` with `fp16` (implies `neon`) and has no side effects. - // - // `frintn` is always round-to-nearest which does not match the C specification, but Rust does - // not support rounding modes. - unsafe { - asm!( - "frintn {x:h}, {x:h}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -pub fn sqrt(mut x: f64) -> f64 { - // SAFETY: `fsqrt` is available with neon and has no side effects. - unsafe { - asm!( - "fsqrt {x:d}, {x:d}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -pub fn sqrtf(mut x: f32) -> f32 { - // SAFETY: `fsqrt` is available with neon and has no side effects. - unsafe { - asm!( - "fsqrt {x:s}, {x:s}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} - -#[cfg(all(f16_enabled, target_feature = "fp16"))] -pub fn sqrtf16(mut x: f16) -> f16 { - // SAFETY: `fsqrt` is available for `f16` with `fp16` (implies `neon`) and has no - // side effects. - unsafe { - asm!( - "fsqrt {x:h}, {x:h}", - x = inout(vreg) x, - options(nomem, nostack, pure) - ); - } - x -} diff --git a/compiler-builtins/libm/src/math/arch/aarch64/fma.rs b/compiler-builtins/libm/src/math/arch/aarch64/fma.rs new file mode 100644 index 0000000000000..9fd574fad37d2 --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/aarch64/fma.rs @@ -0,0 +1,29 @@ +use core::arch::asm; + +pub fn fmaf(mut x: f32, y: f32, z: f32) -> f32 { + // SAFETY: `fmadd` is available with neon and has no side effects. + unsafe { + asm!( + "fmadd {x:s}, {x:s}, {y:s}, {z:s}", + x = inout(vreg) x, + y = in(vreg) y, + z = in(vreg) z, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn fma(mut x: f64, y: f64, z: f64) -> f64 { + // SAFETY: `fmadd` is available with neon and has no side effects. + unsafe { + asm!( + "fmadd {x:d}, {x:d}, {y:d}, {z:d}", + x = inout(vreg) x, + y = in(vreg) y, + z = in(vreg) z, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/compiler-builtins/libm/src/math/arch/aarch64/mod.rs b/compiler-builtins/libm/src/math/arch/aarch64/mod.rs new file mode 100644 index 0000000000000..0192a3d442aec --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/aarch64/mod.rs @@ -0,0 +1,13 @@ +//! Architecture-specific support for aarch64 with neon. + +mod fma; +mod rounding; +mod sqrt; + +pub use fma::{fma, fmaf}; +#[cfg(all(f16_enabled, target_feature = "fp16"))] +pub use rounding::rintf16; +pub use rounding::{rint, rintf}; +#[cfg(all(f16_enabled, target_feature = "fp16"))] +pub use sqrt::sqrtf16; +pub use sqrt::{sqrt, sqrtf}; diff --git a/compiler-builtins/libm/src/math/arch/aarch64/rounding.rs b/compiler-builtins/libm/src/math/arch/aarch64/rounding.rs new file mode 100644 index 0000000000000..255e8e85b2f0b --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/aarch64/rounding.rs @@ -0,0 +1,53 @@ +//! NB: `frintx` is technically the correct instruction for C's `rint`. However, in Rust (and LLVM +//! by default), `rint` is identical to `roundeven` (no fpenv interaction) so we use the +//! side-effect-free `frintn`. +//! +//! In general, C code that calls Rust's libm should assume that fpenv is ignored. + +use core::arch::asm; + +#[cfg(all(f16_enabled, target_feature = "fp16"))] +pub fn rintf16(mut x: f16) -> f16 { + // SAFETY: `frintn` is available for `f16` with `fp16` (implies `neon`) and has no side effects. + // + // `frintn` is always round-to-nearest which does not match the C specification, but Rust does + // not support rounding modes. + unsafe { + asm!( + "frintn {x:h}, {x:h}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn rintf(mut x: f32) -> f32 { + // SAFETY: `frintn` is available with neon and has no side effects. + // + // `frintn` is always round-to-nearest which does not match the C specification, but Rust does + // not support rounding modes. + unsafe { + asm!( + "frintn {x:s}, {x:s}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn rint(mut x: f64) -> f64 { + // SAFETY: `frintn` is available with neon and has no side effects. + // + // `frintn` is always round-to-nearest which does not match the C specification, but Rust does + // not support rounding modes. + unsafe { + asm!( + "frintn {x:d}, {x:d}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/compiler-builtins/libm/src/math/arch/aarch64/sqrt.rs b/compiler-builtins/libm/src/math/arch/aarch64/sqrt.rs new file mode 100644 index 0000000000000..e3743dfd558aa --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/aarch64/sqrt.rs @@ -0,0 +1,39 @@ +use core::arch::asm; + +#[cfg(all(f16_enabled, target_feature = "fp16"))] +pub fn sqrtf16(mut x: f16) -> f16 { + // SAFETY: `fsqrt` is available for `f16` with `fp16` (implies `neon`) and has no + // side effects. + unsafe { + asm!( + "fsqrt {x:h}, {x:h}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn sqrtf(mut x: f32) -> f32 { + // SAFETY: `fsqrt` is available with neon and has no side effects. + unsafe { + asm!( + "fsqrt {x:s}, {x:s}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} + +pub fn sqrt(mut x: f64) -> f64 { + // SAFETY: `fsqrt` is available with neon and has no side effects. + unsafe { + asm!( + "fsqrt {x:d}, {x:d}", + x = inout(vreg) x, + options(nomem, nostack, pure) + ); + } + x +} diff --git a/compiler-builtins/libm/src/math/arch/i586.rs b/compiler-builtins/libm/src/math/arch/i586/exp_all.rs similarity index 53% rename from compiler-builtins/libm/src/math/arch/i586.rs rename to compiler-builtins/libm/src/math/arch/i586/exp_all.rs index d9bb93fbf5852..020b5c057daaf 100644 --- a/compiler-builtins/libm/src/math/arch/i586.rs +++ b/compiler-builtins/libm/src/math/arch/i586/exp_all.rs @@ -1,65 +1,3 @@ -//! Architecture-specific support for x86-32 without SSE2 -//! -//! We use an alternative implementation on x86, because the -//! main implementation fails with the x87 FPU used by -//! debian i386, probably due to excess precision issues. -//! -//! See https://github.com/rust-lang/compiler-builtins/pull/976 for discussion on why these -//! functions are implemented in this way. - -pub fn ceil(mut x: f64) -> f64 { - unsafe { - core::arch::asm!( - "fld qword ptr [{x}]", - // Save the FPU control word, using `x` as scratch space. - "fstcw [{x}]", - // Set rounding control to 0b10 (+∞). - "mov word ptr [{x} + 2], 0x0b7f", - "fldcw [{x} + 2]", - // Round. - "frndint", - // Restore FPU control word. - "fldcw [{x}]", - // Save rounded value to memory. - "fstp qword ptr [{x}]", - x = in(reg) &mut x, - // All the x87 FPU stack is used, all registers must be clobbered - out("st(0)") _, out("st(1)") _, - out("st(2)") _, out("st(3)") _, - out("st(4)") _, out("st(5)") _, - out("st(6)") _, out("st(7)") _, - options(nostack), - ); - } - x -} - -pub fn floor(mut x: f64) -> f64 { - unsafe { - core::arch::asm!( - "fld qword ptr [{x}]", - // Save the FPU control word, using `x` as scratch space. - "fstcw [{x}]", - // Set rounding control to 0b01 (-∞). - "mov word ptr [{x} + 2], 0x077f", - "fldcw [{x} + 2]", - // Round. - "frndint", - // Restore FPU control word. - "fldcw [{x}]", - // Save rounded value to memory. - "fstp qword ptr [{x}]", - x = in(reg) &mut x, - // All the x87 FPU stack is used, all registers must be clobbered - out("st(0)") _, out("st(1)") _, - out("st(2)") _, out("st(3)") _, - out("st(4)") _, out("st(5)") _, - out("st(6)") _, out("st(7)") _, - options(nostack), - ); - } - x -} /// Implements the exponential functions with `x87` assembly. /// /// This relies on the instruction `f2xm1`, which computes `2^x - 1` (for diff --git a/compiler-builtins/libm/src/math/arch/i586/mod.rs b/compiler-builtins/libm/src/math/arch/i586/mod.rs new file mode 100644 index 0000000000000..f80be49fc4b3f --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/i586/mod.rs @@ -0,0 +1,14 @@ +//! Architecture-specific support for x86-32 without SSE2 +//! +//! We use an alternative implementation on x86, because the +//! main implementation fails with the x87 FPU used by +//! debian i386, probably due to excess precision issues. +//! +//! See https://github.com/rust-lang/compiler-builtins/pull/976 for discussion on why these +//! functions are implemented in this way. + +mod exp_all; +mod rounding; + +pub use exp_all::{x87_exp, x87_exp2, x87_exp2f, x87_exp10, x87_exp10f, x87_expf}; +pub use rounding::{ceil, floor, rint}; diff --git a/compiler-builtins/libm/src/math/arch/i586/rounding.rs b/compiler-builtins/libm/src/math/arch/i586/rounding.rs new file mode 100644 index 0000000000000..45bf0adafd304 --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/i586/rounding.rs @@ -0,0 +1,103 @@ +pub fn ceil(mut x: f64) -> f64 { + unsafe { + core::arch::asm!( + "fld qword ptr [{x}]", + // Save the FPU control word, using `x` as scratch space. + "fstcw [{x}]", + // Set rounding control to 0b10 (+∞). + "mov word ptr [{x} + 2], 0x0b7f", + "fldcw [{x} + 2]", + // Round. + "frndint", + // Restore FPU control word. + "fldcw [{x}]", + // Save rounded value to memory. + "fstp qword ptr [{x}]", + x = in(reg) &mut x, + // All the x87 FPU stack is used, all registers must be clobbered + out("st(0)") _, out("st(1)") _, + out("st(2)") _, out("st(3)") _, + out("st(4)") _, out("st(5)") _, + out("st(6)") _, out("st(7)") _, + options(nostack), + ); + } + x +} + +pub fn floor(mut x: f64) -> f64 { + unsafe { + core::arch::asm!( + "fld qword ptr [{x}]", + // Save the FPU control word, using `x` as scratch space. + "fstcw [{x}]", + // Set rounding control to 0b01 (-∞). + "mov word ptr [{x} + 2], 0x077f", + "fldcw [{x} + 2]", + // Round. + "frndint", + // Restore FPU control word. + "fldcw [{x}]", + // Save rounded value to memory. + "fstp qword ptr [{x}]", + x = in(reg) &mut x, + // All the x87 FPU stack is used, all registers must be clobbered + out("st(0)") _, out("st(1)") _, + out("st(2)") _, out("st(3)") _, + out("st(4)") _, out("st(5)") _, + out("st(6)") _, out("st(7)") _, + options(nostack), + ); + } + x +} + +/// Note that this respects rounding mode. Because it is UB to have a non-default rounding +/// mode in Rust, this acts as roundeven. +pub fn rint(mut x: f64) -> f64 { + unsafe { + core::arch::asm!( + "fld qword ptr [{x}]", + "frndint", + "fstp qword ptr [{x}]", + x = in(reg) &mut x, + // All the x87 FPU stack is used, all registers must be clobbered + out("st(0)") _, out("st(1)") _, + out("st(2)") _, out("st(3)") _, + out("st(4)") _, out("st(5)") _, + out("st(6)") _, out("st(7)") _, + options(nostack), + ); + } + x +} + +/* FIXME(msrv): after 1.82, the below can be used to compute control words using `asm_const`: + +#[derive(Clone, Copy, Debug, PartialEq)] +enum Precision { + Single, + Double, + Extended, +} + +/// See: Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: +/// Basic Architecture, section 8.1.5 x87 FPU Control Word. +const fn make_fpcw(round: Round, prec: Precision) -> u16 { + let exceptions = 0b111111; // Disable all 6 exceptions + let misc = 0b1000000; // reserved field usually set by default + let pc = match prec { + Precision::Single => 0b00, + Precision::Double => 0b10, + Precision::Extended => 0b11, + }; + let rc = match round { + Round::Nearest => 0b00, + Round::Negative => 0b01, + Round::Positive => 0b10, + Round::Zero => 0b11, + }; + (rc << 10) | (pc << 8) | misc | exceptions +} + +*/ diff --git a/compiler-builtins/libm/src/math/arch/mod.rs b/compiler-builtins/libm/src/math/arch/mod.rs index ba859c679d0db..1bed464cfa7d6 100644 --- a/compiler-builtins/libm/src/math/arch/mod.rs +++ b/compiler-builtins/libm/src/math/arch/mod.rs @@ -7,7 +7,7 @@ // Most implementations should be defined here, to ensure they are not made available when // soft floats are required. -#[cfg(arch_enabled)] +#[cfg(feature = "arch")] cfg_if! { if #[cfg(all(target_arch = "wasm32", intrinsics_enabled))] { mod wasm32; @@ -41,15 +41,20 @@ cfg_if! { } // There are certain architecture-specific implementations that are needed for correctness -// even with `force-soft-float`. These are configured here. +// even with `arch` disabled. These are configured here. cfg_if! { - if #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] { + if #[cfg(x86_no_sse2)] { mod i586; - pub use i586::{ceil, floor}; - } -} -cfg_if! { - if #[cfg(x86_no_sse)] { - pub use i586::{x87_exp10f, x87_exp10, x87_expf, x87_exp, x87_exp2f, x87_exp2}; + pub use i586::{ + ceil, + floor, + rint, + x87_exp, + x87_exp10, + x87_exp10f, + x87_exp2, + x87_exp2f, + x87_expf, + }; } } diff --git a/compiler-builtins/libm/src/math/arch/wasm32/fabs.rs b/compiler-builtins/libm/src/math/arch/wasm32/fabs.rs new file mode 100644 index 0000000000000..1f5ff3f28131b --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/wasm32/fabs.rs @@ -0,0 +1,7 @@ +pub fn fabsf(x: f32) -> f32 { + x.abs() +} + +pub fn fabs(x: f64) -> f64 { + x.abs() +} diff --git a/compiler-builtins/libm/src/math/arch/wasm32/mod.rs b/compiler-builtins/libm/src/math/arch/wasm32/mod.rs new file mode 100644 index 0000000000000..b262e0108155e --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/wasm32/mod.rs @@ -0,0 +1,10 @@ +//! Wasm has builtins for simple float operations. Use the unstable `core::arch` intrinsics which +//! are significantly faster than soft float operations. + +mod fabs; +mod rounding; +mod sqrt; + +pub use fabs::{fabs, fabsf}; +pub use rounding::{ceil, ceilf, floor, floorf, rint, rintf, trunc, truncf}; +pub use sqrt::{sqrt, sqrtf}; diff --git a/compiler-builtins/libm/src/math/arch/wasm32.rs b/compiler-builtins/libm/src/math/arch/wasm32/rounding.rs similarity index 76% rename from compiler-builtins/libm/src/math/arch/wasm32.rs rename to compiler-builtins/libm/src/math/arch/wasm32/rounding.rs index de80c8a581726..1c8914e4561c1 100644 --- a/compiler-builtins/libm/src/math/arch/wasm32.rs +++ b/compiler-builtins/libm/src/math/arch/wasm32/rounding.rs @@ -1,50 +1,34 @@ //! Wasm has builtins for simple float operations. Use the unstable `core::arch` intrinsics which //! are significantly faster than soft float operations. -pub fn ceil(x: f64) -> f64 { - core::arch::wasm32::f64_ceil(x) -} - pub fn ceilf(x: f32) -> f32 { core::arch::wasm32::f32_ceil(x) } -pub fn fabs(x: f64) -> f64 { - x.abs() -} - -pub fn fabsf(x: f32) -> f32 { - x.abs() -} - -pub fn floor(x: f64) -> f64 { - core::arch::wasm32::f64_floor(x) +pub fn ceil(x: f64) -> f64 { + core::arch::wasm32::f64_ceil(x) } pub fn floorf(x: f32) -> f32 { core::arch::wasm32::f32_floor(x) } -pub fn rint(x: f64) -> f64 { - core::arch::wasm32::f64_nearest(x) +pub fn floor(x: f64) -> f64 { + core::arch::wasm32::f64_floor(x) } pub fn rintf(x: f32) -> f32 { core::arch::wasm32::f32_nearest(x) } -pub fn sqrt(x: f64) -> f64 { - core::arch::wasm32::f64_sqrt(x) +pub fn rint(x: f64) -> f64 { + core::arch::wasm32::f64_nearest(x) } -pub fn sqrtf(x: f32) -> f32 { - core::arch::wasm32::f32_sqrt(x) +pub fn truncf(x: f32) -> f32 { + core::arch::wasm32::f32_trunc(x) } pub fn trunc(x: f64) -> f64 { core::arch::wasm32::f64_trunc(x) } - -pub fn truncf(x: f32) -> f32 { - core::arch::wasm32::f32_trunc(x) -} diff --git a/compiler-builtins/libm/src/math/arch/wasm32/sqrt.rs b/compiler-builtins/libm/src/math/arch/wasm32/sqrt.rs new file mode 100644 index 0000000000000..1d73e4ddcfe96 --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/wasm32/sqrt.rs @@ -0,0 +1,7 @@ +pub fn sqrtf(x: f32) -> f32 { + core::arch::wasm32::f32_sqrt(x) +} + +pub fn sqrt(x: f64) -> f64 { + core::arch::wasm32::f64_sqrt(x) +} diff --git a/compiler-builtins/libm/src/math/arch/x86/detect.rs b/compiler-builtins/libm/src/math/arch/x86/detect.rs index ca785470b806d..983818b5b5e47 100644 --- a/compiler-builtins/libm/src/math/arch/x86/detect.rs +++ b/compiler-builtins/libm/src/math/arch/x86/detect.rs @@ -1,5 +1,5 @@ -// Using runtime feature detection requires atomics. Currently there are no x86 targets -// that support sse but not `AtomicPtr`. +//! Using runtime feature detection requires atomics. Currently there are no x86 targets +//! that support sse but not `AtomicPtr`. #[cfg(target_arch = "x86")] use core::arch::x86::{__cpuid, __cpuid_count, _xgetbv, CpuidResult}; diff --git a/compiler-builtins/libm/src/math/arch/x86/mod.rs b/compiler-builtins/libm/src/math/arch/x86/mod.rs new file mode 100644 index 0000000000000..279bf35b9c9e0 --- /dev/null +++ b/compiler-builtins/libm/src/math/arch/x86/mod.rs @@ -0,0 +1,8 @@ +//! Architecture-specific support for x86-32 with SSE2 (i686) and x86-64. + +mod detect; +mod fma; +mod sqrt; + +pub use fma::{fma, fmaf}; +pub use sqrt::{sqrt, sqrtf}; diff --git a/compiler-builtins/libm/src/math/arch/x86.rs b/compiler-builtins/libm/src/math/arch/x86/sqrt.rs similarity index 85% rename from compiler-builtins/libm/src/math/arch/x86.rs rename to compiler-builtins/libm/src/math/arch/x86/sqrt.rs index 454aa285074d6..d172e1239f1a9 100644 --- a/compiler-builtins/libm/src/math/arch/x86.rs +++ b/compiler-builtins/libm/src/math/arch/x86/sqrt.rs @@ -1,10 +1,3 @@ -//! Architecture-specific support for x86-32 and x86-64 with SSE2 - -mod detect; -mod fma; - -pub use fma::{fma, fmaf}; - pub fn sqrtf(mut x: f32) -> f32 { // SAFETY: `sqrtss` is part of `sse2`, which this module is gated behind. It has no memory // access or side effects. diff --git a/compiler-builtins/libm/src/math/atan2.rs b/compiler-builtins/libm/src/math/atan2.rs index 51456e409b8cc..19be7584bbf07 100644 --- a/compiler-builtins/libm/src/math/atan2.rs +++ b/compiler-builtins/libm/src/math/atan2.rs @@ -119,7 +119,7 @@ mod tests { use super::*; #[test] - #[cfg_attr(x86_no_sse, ignore = "FIXME(i586): possible incorrect rounding")] + #[cfg_attr(x86_no_sse2, ignore = "FIXME(i586): possible incorrect rounding")] fn sanity_check() { assert_eq!(atan2(0.0, 1.0), 0.0); assert_eq!(atan2(0.0, -1.0), PI); diff --git a/compiler-builtins/libm/src/math/cbrt.rs b/compiler-builtins/libm/src/math/cbrt.rs index e905e15f13fbe..b6d24c807eb00 100644 --- a/compiler-builtins/libm/src/math/cbrt.rs +++ b/compiler-builtins/libm/src/math/cbrt.rs @@ -208,7 +208,7 @@ mod tests { #[test] fn spot_checks() { - if !cfg!(x86_no_sse) { + if !cfg!(x86_no_sse2) { // Exposes a rounding mode problem. Ignored on i586 because of inaccurate FMA. assert_biteq!( cbrt(f64::from_bits(0xf7f792b28f600000)), diff --git a/compiler-builtins/libm/src/math/ceil.rs b/compiler-builtins/libm/src/math/ceil.rs index 2cac49f29ba97..c8fb17e7ddca1 100644 --- a/compiler-builtins/libm/src/math/ceil.rs +++ b/compiler-builtins/libm/src/math/ceil.rs @@ -1,10 +1,12 @@ +use super::generic; + /// Ceil (f16) /// /// Finds the nearest integer greater than or equal to `x`. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn ceilf16(x: f16) -> f16 { - super::generic::ceil(x) + generic::ceil_status(x).val } /// Ceil (f32) @@ -18,7 +20,7 @@ pub fn ceilf(x: f32) -> f32 { args: x, } - super::generic::ceil(x) + generic::ceil_status(x).val } /// Ceil (f64) @@ -29,11 +31,11 @@ pub fn ceil(x: f64) -> f64 { select_implementation! { name: ceil, use_arch: all(target_arch = "wasm32", intrinsics_enabled), - use_arch_required: all(target_arch = "x86", not(target_feature = "sse2")), + use_arch_required: x86_no_sse2, args: x, } - super::generic::ceil(x) + generic::ceil_status(x).val } /// Ceil (f128) @@ -42,5 +44,105 @@ pub fn ceil(x: f64) -> f64 { #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn ceilf128(x: f128) -> f128 { - super::generic::ceil(x) + generic::ceil_status(x).val +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::support::{Float, FpResult, Hex, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 1.0, Status::INEXACT), + (-0.1, -0.0, Status::INEXACT), + (0.5, 1.0, Status::INEXACT), + (-0.5, -0.0, Status::INEXACT), + (0.9, 1.0, Status::INEXACT), + (-0.9, -0.0, Status::INEXACT), + (1.1, 2.0, Status::INEXACT), + (-1.1, -1.0, Status::INEXACT), + (1.5, 2.0, Status::INEXACT), + (-1.5, -1.0, Status::INEXACT), + (1.9, 2.0, Status::INEXACT), + (-1.9, -1.0, Status::INEXACT), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { + let FpResult { val, status } = generic::ceil_status(x); + assert_biteq!(val, exp_res, "generic::ceil_status({x:?}) ({})", Hex(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hex(x), + Hex(exp_res) + ); + let val = f(x); + assert_biteq!(val, exp_res, "ceil({x:?}) ({})", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(ceilf16, &cases!(f16)); + check::( + ceilf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ], + ); + } + + #[test] + fn check_f32() { + check::(ceilf, &cases!(f32)); + check::( + ceilf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ], + ); + } + + #[test] + fn check_f64() { + check::(ceil, &cases!(f64)); + check::( + ceil, + &[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ], + ); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(ceilf128, &cases!(f128)); + check::( + ceilf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ], + ); + } } diff --git a/compiler-builtins/libm/src/math/exp.rs b/compiler-builtins/libm/src/math/exp.rs index cb939ad5d8bf2..05203985bf313 100644 --- a/compiler-builtins/libm/src/math/exp.rs +++ b/compiler-builtins/libm/src/math/exp.rs @@ -85,7 +85,7 @@ const P5: f64 = 4.13813679705723846039e-08; /* 0x3E663769, 0x72BEA4D0 */ pub fn exp(mut x: f64) -> f64 { select_implementation! { name: x87_exp, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/compiler-builtins/libm/src/math/exp10.rs b/compiler-builtins/libm/src/math/exp10.rs index e0af1945b922a..452b29a2c3d14 100644 --- a/compiler-builtins/libm/src/math/exp10.rs +++ b/compiler-builtins/libm/src/math/exp10.rs @@ -11,7 +11,7 @@ const P10: &[f64] = &[ pub fn exp10(x: f64) -> f64 { select_implementation! { name: x87_exp10, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/compiler-builtins/libm/src/math/exp10f.rs b/compiler-builtins/libm/src/math/exp10f.rs index f0a311c2d1915..4b9e949fbbe97 100644 --- a/compiler-builtins/libm/src/math/exp10f.rs +++ b/compiler-builtins/libm/src/math/exp10f.rs @@ -11,7 +11,7 @@ const P10: &[f32] = &[ pub fn exp10f(x: f32) -> f32 { select_implementation! { name: x87_exp10f, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/compiler-builtins/libm/src/math/exp2.rs b/compiler-builtins/libm/src/math/exp2.rs index d4c9e96652000..cc2aa434c4e9d 100644 --- a/compiler-builtins/libm/src/math/exp2.rs +++ b/compiler-builtins/libm/src/math/exp2.rs @@ -326,7 +326,7 @@ static TBL: [u64; TBLSIZE * 2] = [ pub fn exp2(mut x: f64) -> f64 { select_implementation! { name: x87_exp2, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/compiler-builtins/libm/src/math/exp2f.rs b/compiler-builtins/libm/src/math/exp2f.rs index ceff6822c5969..44872d74b0ca8 100644 --- a/compiler-builtins/libm/src/math/exp2f.rs +++ b/compiler-builtins/libm/src/math/exp2f.rs @@ -77,7 +77,7 @@ static EXP2FT: [u64; TBLSIZE] = [ pub fn exp2f(mut x: f32) -> f32 { select_implementation! { name: x87_exp2f, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/compiler-builtins/libm/src/math/expf.rs b/compiler-builtins/libm/src/math/expf.rs index 5541ab79a9c14..d1185ff2c4621 100644 --- a/compiler-builtins/libm/src/math/expf.rs +++ b/compiler-builtins/libm/src/math/expf.rs @@ -34,7 +34,7 @@ const P2: f32 = -2.7667332906e-3; /* -0xb55215.0p-32 */ pub fn expf(mut x: f32) -> f32 { select_implementation! { name: x87_expf, - use_arch_required: x86_no_sse, + use_arch_required: x86_no_sse2, args: x, } diff --git a/compiler-builtins/libm/src/math/floor.rs b/compiler-builtins/libm/src/math/floor.rs index 7241c427f6463..2b1e31c0564b0 100644 --- a/compiler-builtins/libm/src/math/floor.rs +++ b/compiler-builtins/libm/src/math/floor.rs @@ -1,10 +1,12 @@ +use super::generic; + /// Floor (f16) /// /// Finds the nearest integer less than or equal to `x`. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn floorf16(x: f16) -> f16 { - return super::generic::floor(x); + return generic::floor_status(x).val; } /// Floor (f64) @@ -15,11 +17,11 @@ pub fn floor(x: f64) -> f64 { select_implementation! { name: floor, use_arch: all(target_arch = "wasm32", intrinsics_enabled), - use_arch_required: all(target_arch = "x86", not(target_feature = "sse2")), + use_arch_required: x86_no_sse2, args: x, } - return super::generic::floor(x); + return generic::floor_status(x).val; } /// Floor (f32) @@ -33,7 +35,7 @@ pub fn floorf(x: f32) -> f32 { args: x, } - return super::generic::floor(x); + return generic::floor_status(x).val; } /// Floor (f128) @@ -42,5 +44,105 @@ pub fn floorf(x: f32) -> f32 { #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn floorf128(x: f128) -> f128 { - return super::generic::floor(x); + return generic::floor_status(x).val; +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::support::{Float, FpResult, Hex, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 0.0, Status::INEXACT), + (-0.1, -1.0, Status::INEXACT), + (0.5, 0.0, Status::INEXACT), + (-0.5, -1.0, Status::INEXACT), + (0.9, 0.0, Status::INEXACT), + (-0.9, -1.0, Status::INEXACT), + (1.1, 1.0, Status::INEXACT), + (-1.1, -2.0, Status::INEXACT), + (1.5, 1.0, Status::INEXACT), + (-1.5, -2.0, Status::INEXACT), + (1.9, 1.0, Status::INEXACT), + (-1.9, -2.0, Status::INEXACT), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { + let FpResult { val, status } = generic::floor_status(x); + assert_biteq!(val, exp_res, "generic::floor_status({x:?}) ({})", Hex(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hex(x), + Hex(exp_res) + ); + let val = f(x); + assert_biteq!(val, exp_res, "floor({x:?}) ({})", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(floorf16, &cases!(f16)); + check::( + floorf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ], + ); + } + + #[test] + fn check_f32() { + check::(floorf, &cases!(f32)); + check::( + floorf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ], + ); + } + + #[test] + fn check_f64() { + check::(floor, &cases!(f64)); + check::( + floor, + &[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ], + ); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(floorf128, &cases!(f128)); + check::( + floorf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ], + ); + } } diff --git a/compiler-builtins/libm/src/math/fma.rs b/compiler-builtins/libm/src/math/fma.rs index 70e6de768fab0..513921d530faf 100644 --- a/compiler-builtins/libm/src/math/fma.rs +++ b/compiler-builtins/libm/src/math/fma.rs @@ -4,13 +4,7 @@ use super::generic; use crate::support::Round; -// Placeholder so we can have `fmaf16` in the `Float` trait. -#[allow(unused)] -#[cfg(f16_enabled)] -#[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub(crate) fn fmaf16(_x: f16, _y: f16, _z: f16) -> f16 { - unimplemented!() -} +/* See `fmaf16.rs` for that implementation */ /// Floating multiply add (f32) /// @@ -58,42 +52,83 @@ pub fn fmaf128(x: f128, y: f128, z: f128) -> f128 { #[cfg(test)] mod tests { use super::*; - use crate::support::{CastFrom, CastInto, Float, FpResult, HInt, MinInt, Round, Status}; - - /// Test the generic `fma_round` algorithm for a given float. - fn spec_test(f: impl Fn(F, F, F) -> F) - where - F: Float, - F: CastFrom, - F: CastFrom, - F::Int: HInt, - u32: CastInto, - { - let x = F::from_bits(F::Int::ONE); - let y = F::from_bits(F::Int::ONE); - let z = F::ZERO; - - // 754-2020 says "When the exact result of (a × b) + c is non-zero yet the result of - // fusedMultiplyAdd is zero because of rounding, the zero result takes the sign of the - // exact result" - assert_biteq!(f(x, y, z), F::ZERO); - assert_biteq!(f(x, -y, z), F::NEG_ZERO); - assert_biteq!(f(-x, y, z), F::NEG_ZERO); - assert_biteq!(f(-x, -y, z), F::ZERO); + use crate::support::{Float, FpResult, Hex, Round, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // Simple + (0.0, 0.0, 0.0, 0.0), + (1.0, 1.0, 0.0, 1.0), + (1.0, 0.0, 1.0, 1.0), + // Sign checks + (1.0, 1.0, 1.0, 2.0), + (1.0, 1.0, -1.0, 0.0), + (1.0, -1.0, 1.0, 0.0), + (1.0, -1.0, -1.0, -2.0), + (-1.0, 1.0, 1.0, 0.0), + (-1.0, 1.0, -1.0, -2.0), + (-1.0, -1.0, 1.0, 2.0), + (-1.0, -1.0, -1.0, 0.0), + + // Roundtrip + (<$f>::MAX, 1.0, 0.0, <$f>::MAX), + (<$f>::MAX, <$f>::MAX, 1.0, <$f>::INFINITY), + (<$f>::MAX, 1.0, -<$f>::MAX, 0.0), + (-<$f>::MAX, 1.0, <$f>::MAX, 0.0), + (<$f>::MIN_POSITIVE_NORMAL, 1.0, -<$f>::MIN_POSITIVE_NORMAL, 0.0), + (-<$f>::MIN_POSITIVE_NORMAL, 1.0, <$f>::MIN_POSITIVE_NORMAL, 0.0), + (<$f>::MIN_POSITIVE_SUBNORMAL, 1.0, -<$f>::MIN_POSITIVE_SUBNORMAL, 0.0), + (-<$f>::MIN_POSITIVE_SUBNORMAL, 1.0, <$f>::MIN_POSITIVE_SUBNORMAL, 0.0), + (<$f>::MAX, 1.0, -<$f>::MAX, 0.0), + + // 754-2020 says "When the exact result of (a × b) + c is non-zero yet the result of + // fusedMultiplyAdd is zero because of rounding, the zero result takes the sign of the + // exact result" + (<$f>::MIN_POSITIVE_SUBNORMAL, <$f>::MIN_POSITIVE_SUBNORMAL, 0.0, 0.0), + (<$f>::MIN_POSITIVE_SUBNORMAL, -<$f>::MIN_POSITIVE_SUBNORMAL, 0.0, -0.0), + (-<$f>::MIN_POSITIVE_SUBNORMAL, <$f>::MIN_POSITIVE_SUBNORMAL, 0.0, -0.0), + (-<$f>::MIN_POSITIVE_SUBNORMAL, -<$f>::MIN_POSITIVE_SUBNORMAL, 0.0, 0.0), + ] + }; + } + + #[track_caller] + fn check(f: fn(F, F, F) -> F, cases: &[(F, F, F, F)]) { + for &(x, y, z, exp_res) in cases { + let val = f(x, y, z); + assert_biteq!( + val, + exp_res, + "fma({x:?}, {y:?}, {z:?}) ({} {} {})", + Hex(x), + Hex(y), + Hex(z) + ); + } } #[test] - fn spec_test_f32() { - spec_test::(fmaf); + #[cfg(f16_enabled)] + fn check_f16() { + check::(super::super::fmaf16, &cases!(f16)); + } + + #[test] + fn check_f32() { + check::(fmaf, &cases!(f32)); // Also do a small check that the non-widening version works for f32 (this should ideally // get tested some more). - spec_test::(|x, y, z| generic::fma_round(x, y, z, Round::Nearest).val); + check::( + |x, y, z| generic::fma_round(x, y, z, Round::Nearest).val, + &cases!(f32), + ); } #[test] - fn spec_test_f64() { - spec_test::(fma); + fn check_f64() { + check::(fma, &cases!(f64)); let expect_underflow = [ ( @@ -121,8 +156,8 @@ mod tests { #[test] #[cfg(f128_enabled)] - fn spec_test_f128() { - spec_test::(fmaf128); + fn check_f128() { + check::(fmaf128, &cases!(f128)); } #[test] @@ -148,7 +183,7 @@ mod tests { let result = fma(-0.992, -0.992, -0.992); //force rounding to storage format on x87 to prevent superious errors. - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let result = force_eval!(result); assert_eq!(result, -0.007936000000000007,); } diff --git a/compiler-builtins/libm/src/math/fmaf16.rs b/compiler-builtins/libm/src/math/fmaf16.rs new file mode 100644 index 0000000000000..8d1c5bccf8527 --- /dev/null +++ b/compiler-builtins/libm/src/math/fmaf16.rs @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: MIT OR Apache-2.0 + * origin: original implementation, 2026 (TG) */ + +use crate::support::{CastFrom, Float, Int, unbounded_shr_u64}; + +/// We use a a U21.43 fixed-point representation when needed. +const FIXED_FRAC_BITS: u32 = 43; + +/// Floating multiply add (f16) +/// +/// Computes `(x*y)+z`, rounded as one ternary operation (i.e. calculated with infinite precision). +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn fmaf16(x: f16, y: f16, z: f16) -> f16 { + let ix = x.to_bits() & !f16::SIGN_MASK; + let iy = y.to_bits() & !f16::SIGN_MASK; + let iz = z.to_bits() & !f16::SIGN_MASK; + + let xneg = x.is_sign_negative(); + let yneg = y.is_sign_negative(); + let zneg = z.is_sign_negative(); + + let mneg = xneg ^ yneg; + + if ix == 0 || ix >= f16::EXP_MASK || iy == 0 || iy >= f16::EXP_MASK { + // Value will overflow, defer to non-fused operations. + return x * y + z; + } + + if iz == 0 { + // Empty add component means we only need to multiply. + return x * y; + } + + if iz >= f16::EXP_MASK { + // `z` is NaN or infinity, which sets the result. + return z; + } + + let mut xexp = x.ex(); + let mut yexp = y.ex(); + let mut zexp = z.ex(); + + let mut xsig = ix & f16::SIG_MASK; + let mut ysig = iy & f16::SIG_MASK; + let mut zsig = iz & f16::SIG_MASK; + + // If not subnormal, set the implicit bit + if xexp != 0 { + xsig |= f16::IMPLICIT_BIT; + } + if yexp != 0 { + ysig |= f16::IMPLICIT_BIT; + } + if zexp != 0 { + zsig |= f16::IMPLICIT_BIT; + } + + // A biased exponent of 1 (min normal) and 0 (subnormal) have the same real exponent, so + // adjust for this. Bias is now 14 rather than 15. + xexp = xexp.saturating_sub(1); + yexp = yexp.saturating_sub(1); + zexp = zexp.saturating_sub(1); + let adjbias = f16::EXP_BIAS - 1; + + // Exponent after multiplication. Bias doubles to 28. + let mexp = xexp + yexp; + let mbias = adjbias * 2; + + // Exit now if we know the result will overflow. We need to keep one beyond the infinite + // exponent in case the addition rounds down to a finite number. + // + // Note that `EXP_MAX` (i.e. max finite) represents infinity here because our values are + // acting with a bias of 14. + let inf_exp = mbias + f16::EXP_MAX.unsigned(); + if mexp > inf_exp + 1 { + if mneg { + return f16::NEG_INFINITY; + } else { + return f16::INFINITY; + } + } + + // Multiplication moves the explicit 1 from the 11th bit to the 22nd bit. + let m = u32::from(xsig) * u32::from(ysig); + let mut m64 = u64::from(m); + + // The entire dynamic range of an `f16` fits into a `u64`. Shift based on the exponent to + // create a U21.43 fixed-point value. At the maximum exponent, there are five zeros before + // the explicit leading 1 (intentional so this truncates to the final repr). + if let Some(mshift) = mexp.checked_sub(5) { + debug_assert_eq!( + unbounded_shr_u64(m64, 64 - mshift), + 0, + "data shifted out {m} {mshift}" + ); + m64 <<= mshift; + } else { + // The lower few bits here would be on the order of 2^-43, which is too small to show up + // in a result significand. Just squash them to a sticky bit. + let sticky = m64 & 0b11111 != 0; + m64 >>= 5 - mexp; + m64 |= u64::from(sticky); + } + + // Shift z to U21.43 as well. + let zshift = zexp + FIXED_FRAC_BITS - f16::SIG_BITS - adjbias; + let z64 = u64::from(zsig) << zshift; + + let sub = mneg ^ zneg; + + let rneg; + let r64 = if sub { + if m64 > z64 { + rneg = mneg; + m64.wrapping_sub(z64) + } else if m64 == z64 { + rneg = false; + m64.wrapping_sub(z64) + } else { + rneg = zneg; + z64.wrapping_sub(m64) + } + } else { + rneg = mneg; + m64 + z64 + }; + + let sign = if rneg { -1.0 } else { 1.0 }; + f16_from_u21_43(r64).copysign(sign) +} + +/// Turn a U21.43 value into an f16 with positive sign. +fn f16_from_u21_43(mut r64: u64) -> f16 { + let extra_bits = 64 - 16; + let max_finite_lz = 64 - f16::SIG_BITS - extra_bits - 1; // 5 + + // Check for overflow to infinity after addition, return before checking lz. + if r64 & (u64::MAX << (64 - max_finite_lz)) != 0 { + return f16::INFINITY; + } + + // Shift the fixed point to floating point. There are 5 leading zeros before the largest + // finite value's explicit one. + // + // We want `rexp` as one less than the actual value to be stored because it gets added to + // a value with the leading one set. This value and the shift are clamped so subnormals + // don't become normalized. + let exp_max_biased_m1 = f16::EXP_MAX.unsigned() + f16::EXP_BIAS - 1; // 29 + let lz = r64.leading_zeros(); + let rexp = (exp_max_biased_m1 + max_finite_lz).saturating_sub(lz); + let shift = exp_max_biased_m1 - rexp; + r64 <<= shift; + + // Round up if the round bit (one past significand end) is set and any trailing bit is set, + // or if the preceding bit is set. + let round_bit = 1u64 << (extra_bits - 1); + let up_mask = ((1u64 << (extra_bits + 1)) - 1) & !round_bit; + let round_up = r64 & round_bit != 0 && r64 & up_mask != 0; + let round_up = u16::from(round_up); + + // Truncate then round. Automatically accounts for subnormals with the unset explicit decimal + // bit, since `rexp` is one less than the actual biased value. + let mut r = (r64 >> extra_bits) as u16; + r += u16::cast_from(rexp) << f16::SIG_BITS; + r += round_up; + + f16::from_bits(r) +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn test_from_fixed() { + // Move 1.xx... floating point to 1.xx... fixed point + let shift_to_one = |x: u16| u64::from(x) << (FIXED_FRAC_BITS - f16::SIG_BITS); + let top_sig = f16::IMPLICIT_BIT; + let max_sig = f16::IMPLICIT_BIT | f16::SIG_MASK; + + // Basic values + let one = shift_to_one(top_sig); + let max = shift_to_one(max_sig) << 15; + let inf = shift_to_one(max_sig + 1) << 15; + let min_norm = one >> 14; + let max_sub = shift_to_one(f16::SIG_MASK) >> 14; + let min_sub = shift_to_one(1) >> 14; + + assert_biteq!(f16_from_u21_43(0), 0.0f16); + assert_biteq!(f16_from_u21_43(one), 1.0f16); + assert_biteq!(f16_from_u21_43(max), f16::MAX); + assert_biteq!(f16_from_u21_43(inf), f16::INFINITY); + assert_biteq!(f16_from_u21_43(min_norm), f16::MIN_POSITIVE_NORMAL); + assert_biteq!(f16_from_u21_43(max_sub), f16::from_bits(f16::SIG_MASK)); + assert_biteq!(f16_from_u21_43(min_sub), f16::MIN_POSITIVE_SUBNORMAL); + + // Masks centered around 1 to add a rounding + let mask_r = shift_to_one(0b1) >> 1; // round bit + let mask_rg = shift_to_one(0b11) >> 2; // round + guard + let mask_rgs = shift_to_one(0b111) >> 3; // round + guard + sticky + let mask_rs = shift_to_one(0b101) >> 3; // round + sticky + let mask_rs2 = shift_to_one(0b1000_0001) >> 8; // round + part of sticky + + let signed_shift = |val: u64, shift: i32| { + if shift >= 0 { + val << shift + } else { + val >> -shift + } + }; + + let check_round = |fixed: u64, shift: i32, lsb_set: bool, down: f16, up: f16| { + // Masks that will cause rounding down + let mdown = if lsb_set { &[0][..] } else { &[0, mask_r][..] }; + // Masks that will cause rounding up + let mup = if lsb_set { + &[mask_r, mask_rg, mask_rgs, mask_rs, mask_rs2][..] + } else { + &[mask_rg, mask_rgs, mask_rs, mask_rs2][..] + }; + + for (i, mask) in mdown.iter().enumerate() { + let bits = fixed | signed_shift(*mask, shift); + assert_biteq!(f16_from_u21_43(bits), down, "{bits:#066b} {i}"); + } + + for (i, mask) in mup.iter().enumerate() { + let bits = fixed | signed_shift(*mask, shift); + assert_biteq!(f16_from_u21_43(bits), up, "{bits:#066b} {i}"); + } + }; + + check_round(one, 0, false, 1.0, 1.0f16.next_up()); + check_round(max, 15, true, f16::MAX, f16::INFINITY); + check_round( + min_norm, + -14, + false, + f16::MIN_POSITIVE_NORMAL, + f16::MIN_POSITIVE_NORMAL.next_up(), + ); + check_round( + max_sub, + -14, + true, + f16::MIN_POSITIVE_NORMAL.next_down(), + f16::MIN_POSITIVE_NORMAL, + ); + check_round( + min_sub, + -14, + true, + f16::MIN_POSITIVE_SUBNORMAL, + f16::MIN_POSITIVE_SUBNORMAL.next_up(), + ); + check_round(0, -14, false, 0.0, f16::MIN_POSITIVE_SUBNORMAL); + } +} diff --git a/compiler-builtins/libm/src/math/fmin_fmax.rs b/compiler-builtins/libm/src/math/fmin_fmax.rs index ead9e6599f1be..64ad79928f7a0 100644 --- a/compiler-builtins/libm/src/math/fmin_fmax.rs +++ b/compiler-builtins/libm/src/math/fmin_fmax.rs @@ -77,8 +77,7 @@ pub fn fmaxf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; - use crate::support::hex_float::Hexi; - use crate::support::{Float, Hexf}; + use crate::support::{Float, Hex}; fn fmin_spec_test(f: impl Fn(F, F) -> F) { // Note that (YaN, sNaN) and (sNaN, YaN) results differ from 754-2008. This is intentional, @@ -171,7 +170,7 @@ mod tests { for (x, y, res) in cases { let val = f(x, y); - assert_biteq!(val, res, "fmin({}, {})", Hexf(x), Hexf(y)); + assert_biteq!(val, res, "fmin({}, {})", Hex(x), Hex(y)); } // Ordering between zeros does not matter @@ -314,10 +313,10 @@ mod tests { val, res, "fmax({}, {}) ({}, {})", - Hexf(x), - Hexf(y), - Hexi(x.to_bits()), - Hexi(y.to_bits()), + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), ); } diff --git a/compiler-builtins/libm/src/math/fminimum_fmaximum.rs b/compiler-builtins/libm/src/math/fminimum_fmaximum.rs index ffc724e3a8d74..59d9af317674f 100644 --- a/compiler-builtins/libm/src/math/fminimum_fmaximum.rs +++ b/compiler-builtins/libm/src/math/fminimum_fmaximum.rs @@ -69,8 +69,7 @@ pub fn fmaximumf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; - use crate::support::hex_float::Hexi; - use crate::support::{Float, Hexf}; + use crate::support::{Float, Hex}; fn fminimum_spec_test(f: impl Fn(F, F) -> F) { let cases = [ @@ -132,10 +131,10 @@ mod tests { val, res, "fminimum({}, {}) ({}, {})", - Hexf(x), - Hexf(y), - Hexi(x.to_bits()), - Hexi(y.to_bits()), + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), ); } @@ -264,10 +263,10 @@ mod tests { val, res, "fmaximum({}, {}) ({}, {})", - Hexf(x), - Hexf(y), - Hexi(x.to_bits()), - Hexi(y.to_bits()), + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), ); } diff --git a/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs b/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs index 3157f8a3fee8c..51b20b736d2ca 100644 --- a/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs +++ b/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs @@ -69,8 +69,7 @@ pub fn fmaximum_numf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; - use crate::support::hex_float::Hexi; - use crate::support::{Float, Hexf}; + use crate::support::{Float, Hex}; fn fminimum_num_spec_test(f: impl Fn(F, F) -> F) { let cases = [ @@ -167,10 +166,10 @@ mod tests { actual, expected, "fminimum_num({}, {}) ({}, {})", - Hexf(x), - Hexf(y), - Hexi(x.to_bits()), - Hexi(y.to_bits()), + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), ); } @@ -312,10 +311,10 @@ mod tests { actual, expected, "fmaximum_num({}, {}) ({}, {})", - Hexf(x), - Hexf(y), - Hexi(x.to_bits()), - Hexi(y.to_bits()), + Hex(x), + Hex(y), + Hex(x.to_bits()), + Hex(y.to_bits()), ); } diff --git a/compiler-builtins/libm/src/math/generic/ceil.rs b/compiler-builtins/libm/src/math/generic/ceil.rs index 5584f6503ef58..944cb4d4c7259 100644 --- a/compiler-builtins/libm/src/math/generic/ceil.rs +++ b/compiler-builtins/libm/src/math/generic/ceil.rs @@ -9,11 +9,6 @@ use crate::support::{Float, FpResult, Int, IntTy, MinInt, Status}; -#[inline] -pub fn ceil(x: F) -> F { - ceil_status(x).val -} - #[inline] pub fn ceil_status(x: F) -> FpResult { let zero = IntTy::::ZERO; @@ -66,89 +61,3 @@ pub fn ceil_status(x: F) -> FpResult { FpResult::new(res, status) } - -#[cfg(test)] -mod tests { - use super::*; - use crate::support::Hexf; - - macro_rules! cases { - ($f:ty) => { - [ - // roundtrip - (0.0, 0.0, Status::OK), - (-0.0, -0.0, Status::OK), - (1.0, 1.0, Status::OK), - (-1.0, -1.0, Status::OK), - (<$f>::INFINITY, <$f>::INFINITY, Status::OK), - (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), - // with rounding - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.5, 1.0, Status::INEXACT), - (-0.5, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.5, 2.0, Status::INEXACT), - (-1.5, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ] - }; - } - - #[track_caller] - fn check(cases: &[(F, F, Status)]) { - for &(x, exp_res, exp_stat) in cases { - let FpResult { val, status } = ceil_status(x); - assert_biteq!(val, exp_res, "{x:?} {}", Hexf(x)); - assert_eq!( - status, - exp_stat, - "{x:?} {} -> {exp_res:?} {}", - Hexf(x), - Hexf(exp_res) - ); - } - } - - #[test] - #[cfg(f16_enabled)] - fn check_f16() { - check::(&cases!(f16)); - check::(&[ - (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), - (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), - ]); - } - - #[test] - fn check_f32() { - check::(&cases!(f32)); - check::(&[ - (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), - (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), - ]); - } - - #[test] - fn check_f64() { - check::(&cases!(f64)); - check::(&[ - (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), - (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), - ]); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - check::(&cases!(f128)); - check::(&[ - (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), - (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), - ]); - } -} diff --git a/compiler-builtins/libm/src/math/generic/floor.rs b/compiler-builtins/libm/src/math/generic/floor.rs index 7045229c0c75a..a99d192831e3c 100644 --- a/compiler-builtins/libm/src/math/generic/floor.rs +++ b/compiler-builtins/libm/src/math/generic/floor.rs @@ -9,11 +9,6 @@ use crate::support::{Float, FpResult, Int, IntTy, MinInt, Status}; -#[inline] -pub fn floor(x: F) -> F { - floor_status(x).val -} - #[inline] pub fn floor_status(x: F) -> FpResult { let zero = IntTy::::ZERO; @@ -58,89 +53,3 @@ pub fn floor_status(x: F) -> FpResult { FpResult::new(res, Status::INEXACT) } - -#[cfg(test)] -mod tests { - use super::*; - use crate::support::Hexf; - - macro_rules! cases { - ($f:ty) => { - [ - // roundtrip - (0.0, 0.0, Status::OK), - (-0.0, -0.0, Status::OK), - (1.0, 1.0, Status::OK), - (-1.0, -1.0, Status::OK), - (<$f>::INFINITY, <$f>::INFINITY, Status::OK), - (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), - // with rounding - (0.1, 0.0, Status::INEXACT), - (-0.1, -1.0, Status::INEXACT), - (0.5, 0.0, Status::INEXACT), - (-0.5, -1.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -1.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -2.0, Status::INEXACT), - (1.5, 1.0, Status::INEXACT), - (-1.5, -2.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -2.0, Status::INEXACT), - ] - }; - } - - #[track_caller] - fn check(cases: &[(F, F, Status)]) { - for &(x, exp_res, exp_stat) in cases { - let FpResult { val, status } = floor_status(x); - assert_biteq!(val, exp_res, "{x:?} {}", Hexf(x)); - assert_eq!( - status, - exp_stat, - "{x:?} {} -> {exp_res:?} {}", - Hexf(x), - Hexf(exp_res) - ); - } - } - - #[test] - #[cfg(f16_enabled)] - fn check_f16() { - check::(&cases!(f16)); - check::(&[ - (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), - (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), - ]); - } - - #[test] - fn check_f32() { - check::(&cases!(f32)); - check::(&[ - (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), - (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), - ]); - } - - #[test] - fn check_f64() { - check::(&cases!(f64)); - check::(&[ - (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), - (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), - ]); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - check::(&cases!(f128)); - check::(&[ - (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), - (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), - ]); - } -} diff --git a/compiler-builtins/libm/src/math/generic/mod.rs b/compiler-builtins/libm/src/math/generic/mod.rs index 114fcddf516e5..7a26295e39077 100644 --- a/compiler-builtins/libm/src/math/generic/mod.rs +++ b/compiler-builtins/libm/src/math/generic/mod.rs @@ -1,5 +1,11 @@ -// Note: generic functions are marked `#[inline]` because, even though generic functions are -// typically inlined, this does not seem to always be the case. +//! Generic implementations that are shared by multiple types. +//! +//! Implementation and usage notes: +//! +//! * Generic functions are marked `#[inline]` because, even though generic functions are +//! typically inlined, we seem to occasionally run into exceptions. +//! * Tests usually live wherever the functions are consumed (e.g. `src/ceil`) so they can be +//! reused to test arch-specific implementations. mod ceil; mod copysign; @@ -23,11 +29,11 @@ mod scalbn; mod sqrt; mod trunc; -pub use ceil::ceil; +pub use ceil::ceil_status; pub use copysign::copysign; pub use fabs::fabs; pub use fdim::fdim; -pub use floor::floor; +pub use floor::floor_status; pub use fma::fma_round; pub use fma_wide::fma_wide_round; pub use fmax::fmax; @@ -39,8 +45,10 @@ pub use fminimum_num::fminimum_num; pub use fmod::fmod; pub use frexp::frexp; pub use ilogb::ilogb; -pub use rint::rint_round; +pub use rint::rint_status; pub use round::round; pub use scalbn::scalbn; -pub use sqrt::sqrt; -pub use trunc::trunc; +#[cfg(test)] +pub use sqrt::SqrtHelper; +pub use sqrt::sqrt_round; +pub use trunc::trunc_status; diff --git a/compiler-builtins/libm/src/math/generic/rint.rs b/compiler-builtins/libm/src/math/generic/rint.rs index c5bc27d3de6bc..aa3d94e9a30d8 100644 --- a/compiler-builtins/libm/src/math/generic/rint.rs +++ b/compiler-builtins/libm/src/math/generic/rint.rs @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: MIT */ /* origin: musl src/math/rint.c */ -use crate::support::{Float, FpResult, Round}; +use crate::support::{Float, FpResult, Status}; /// IEEE 754-2019 `roundToIntegralExact`, which respects rounding mode and raises inexact if /// applicable. #[inline] -pub fn rint_round(x: F, _round: Round) -> FpResult { +pub fn rint_status(x: F) -> FpResult { let toint = F::ONE / F::EPSILON; let e = x.ex(); let positive = x.is_sign_positive(); @@ -14,7 +14,7 @@ pub fn rint_round(x: F, _round: Round) -> FpResult { // On i386 `force_eval!` must be used to force rounding via storage to memory. Otherwise, // the excess precission from x87 would cause an incorrect final result. let force = |x| { - if cfg!(x86_no_sse) && (F::BITS == 32 || F::BITS == 64) { + if cfg!(x86_no_sse2) && (F::BITS == 32 || F::BITS == 64) { force_eval!(x) } else { x @@ -41,90 +41,10 @@ pub fn rint_round(x: F, _round: Round) -> FpResult { } }; - FpResult::ok(res) -} - -#[cfg(test)] -mod tests { - use super::*; - use crate::support::{Hexf, Status}; - - fn spec_test(cases: &[(F, F, Status)]) { - let roundtrip = [ - F::ZERO, - F::ONE, - F::NEG_ONE, - F::NEG_ZERO, - F::INFINITY, - F::NEG_INFINITY, - ]; - - for x in roundtrip { - let FpResult { val, status } = rint_round(x, Round::Nearest); - assert_biteq!(val, x, "rint_round({})", Hexf(x)); - assert_eq!(status, Status::OK, "{}", Hexf(x)); - } - - for &(x, res, res_stat) in cases { - let FpResult { val, status } = rint_round(x, Round::Nearest); - assert_biteq!(val, res, "rint_round({})", Hexf(x)); - assert_eq!(status, res_stat, "{}", Hexf(x)); - } - } - - #[test] - #[cfg(f16_enabled)] - fn spec_tests_f16() { - let cases = []; - spec_test::(&cases); - } - - #[test] - fn spec_tests_f32() { - let cases = [ - (0.1, 0.0, Status::OK), - (-0.1, -0.0, Status::OK), - (0.5, 0.0, Status::OK), - (-0.5, -0.0, Status::OK), - (0.9, 1.0, Status::OK), - (-0.9, -1.0, Status::OK), - (1.1, 1.0, Status::OK), - (-1.1, -1.0, Status::OK), - (1.5, 2.0, Status::OK), - (-1.5, -2.0, Status::OK), - (1.9, 2.0, Status::OK), - (-1.9, -2.0, Status::OK), - (2.8, 3.0, Status::OK), - (-2.8, -3.0, Status::OK), - ]; - spec_test::(&cases); - } - - #[test] - fn spec_tests_f64() { - let cases = [ - (0.1, 0.0, Status::OK), - (-0.1, -0.0, Status::OK), - (0.5, 0.0, Status::OK), - (-0.5, -0.0, Status::OK), - (0.9, 1.0, Status::OK), - (-0.9, -1.0, Status::OK), - (1.1, 1.0, Status::OK), - (-1.1, -1.0, Status::OK), - (1.5, 2.0, Status::OK), - (-1.5, -2.0, Status::OK), - (1.9, 2.0, Status::OK), - (-1.9, -2.0, Status::OK), - (2.8, 3.0, Status::OK), - (-2.8, -3.0, Status::OK), - ]; - spec_test::(&cases); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - let cases = []; - spec_test::(&cases); - } + let status = if res == x { + Status::OK + } else { + Status::INEXACT + }; + FpResult::new(res, status) } diff --git a/compiler-builtins/libm/src/math/generic/round.rs b/compiler-builtins/libm/src/math/generic/round.rs index 16739f01d8775..9cab1e22c2c6c 100644 --- a/compiler-builtins/libm/src/math/generic/round.rs +++ b/compiler-builtins/libm/src/math/generic/round.rs @@ -1,4 +1,4 @@ -use super::{copysign, trunc}; +use super::{copysign, trunc_status}; use crate::support::{Float, MinInt}; #[inline] @@ -6,78 +6,5 @@ pub fn round(x: F) -> F { let f0p5 = F::from_parts(false, F::EXP_BIAS - 1, F::Int::ZERO); // 0.5 let f0p25 = F::from_parts(false, F::EXP_BIAS - 2, F::Int::ZERO); // 0.25 - trunc(x + copysign(f0p5 - f0p25 * F::EPSILON, x)) -} - -#[cfg(test)] -mod tests { - use super::*; - - #[test] - #[cfg(f16_enabled)] - fn zeroes_f16() { - assert_biteq!(round(0.0_f16), 0.0_f16); - assert_biteq!(round(-0.0_f16), -0.0_f16); - } - - #[test] - #[cfg(f16_enabled)] - fn sanity_check_f16() { - assert_eq!(round(-1.0_f16), -1.0); - assert_eq!(round(2.8_f16), 3.0); - assert_eq!(round(-0.5_f16), -1.0); - assert_eq!(round(0.5_f16), 1.0); - assert_eq!(round(-1.5_f16), -2.0); - assert_eq!(round(1.5_f16), 2.0); - } - - #[test] - fn zeroes_f32() { - assert_biteq!(round(0.0_f32), 0.0_f32); - assert_biteq!(round(-0.0_f32), -0.0_f32); - } - - #[test] - fn sanity_check_f32() { - assert_eq!(round(-1.0_f32), -1.0); - assert_eq!(round(2.8_f32), 3.0); - assert_eq!(round(-0.5_f32), -1.0); - assert_eq!(round(0.5_f32), 1.0); - assert_eq!(round(-1.5_f32), -2.0); - assert_eq!(round(1.5_f32), 2.0); - } - - #[test] - fn zeroes_f64() { - assert_biteq!(round(0.0_f64), 0.0_f64); - assert_biteq!(round(-0.0_f64), -0.0_f64); - } - - #[test] - fn sanity_check_f64() { - assert_eq!(round(-1.0_f64), -1.0); - assert_eq!(round(2.8_f64), 3.0); - assert_eq!(round(-0.5_f64), -1.0); - assert_eq!(round(0.5_f64), 1.0); - assert_eq!(round(-1.5_f64), -2.0); - assert_eq!(round(1.5_f64), 2.0); - } - - #[test] - #[cfg(f128_enabled)] - fn zeroes_f128() { - assert_biteq!(round(0.0_f128), 0.0_f128); - assert_biteq!(round(-0.0_f128), -0.0_f128); - } - - #[test] - #[cfg(f128_enabled)] - fn sanity_check_f128() { - assert_eq!(round(-1.0_f128), -1.0); - assert_eq!(round(2.8_f128), 3.0); - assert_eq!(round(-0.5_f128), -1.0); - assert_eq!(round(0.5_f128), 1.0); - assert_eq!(round(-1.5_f128), -2.0); - assert_eq!(round(1.5_f128), 2.0); - } + trunc_status(x + copysign(f0p5 - f0p25 * F::EPSILON, x)).val } diff --git a/compiler-builtins/libm/src/math/generic/sqrt.rs b/compiler-builtins/libm/src/math/generic/sqrt.rs index e97a43d349569..013f6c097487f 100644 --- a/compiler-builtins/libm/src/math/generic/sqrt.rs +++ b/compiler-builtins/libm/src/math/generic/sqrt.rs @@ -45,20 +45,6 @@ use crate::support::{ CastFrom, CastInto, DInt, Float, FpResult, HInt, Int, IntTy, MinInt, Round, Status, cold_path, }; -#[inline] -pub fn sqrt(x: F) -> F -where - F: Float + SqrtHelper, - F::Int: HInt, - F::Int: From, - F::Int: From, - F::Int: CastInto, - F::Int: CastInto, - u32: CastInto, -{ - sqrt_round(x, Round::Nearest).val -} - #[inline] pub fn sqrt_round(x: F, _round: Round) -> FpResult where @@ -164,17 +150,17 @@ where let s1_u2: F::ISet1 = ((m_u2) >> (F::BITS - F::ISet1::BITS)).cast(); // Perform iterations, if any, at quarter width (used for `f128`). - let (r1_u0, _s1_u2) = goldschmidt::(r1_u0, s1_u2, F::SET1_ROUNDS, false); + let (r1_u0, _s1_u2) = goldschmidt::(r1_u0, s1_u2, F::SET1_ROUNDS, false); // Widen values and perform iterations at half width (used for `f64` and `f128`). let r2_u0: F::ISet2 = F::ISet2::from(r1_u0) << (F::ISet2::BITS - F::ISet1::BITS); let s2_u2: F::ISet2 = ((m_u2) >> (F::BITS - F::ISet2::BITS)).cast(); - let (r2_u0, _s2_u2) = goldschmidt::(r2_u0, s2_u2, F::SET2_ROUNDS, false); + let (r2_u0, _s2_u2) = goldschmidt::(r2_u0, s2_u2, F::SET2_ROUNDS, false); // Perform final iterations at full width (used for all float types). let r_u0: F::Int = F::Int::from(r2_u0) << (F::BITS - F::ISet2::BITS); let s_u2: F::Int = m_u2; - let (_r_u0, s_u2) = goldschmidt::(r_u0, s_u2, F::FINAL_ROUNDS, true); + let (_r_u0, s_u2) = goldschmidt::(r_u0, s_u2, F::FINAL_ROUNDS, true); // Shift back to mantissa position. let mut m = s_u2 >> (F::EXP_BITS - 2); @@ -250,9 +236,8 @@ fn wmulh(a: I, b: I) -> I { /// Note that performance relies on the optimizer being able to unroll these loops (reasonably /// trivial, `count` is a constant when called). #[inline] -fn goldschmidt(mut r_u0: I, mut s_u2: I, count: u32, final_set: bool) -> (I, I) +fn goldschmidt(mut r_u0: I, mut s_u2: I, count: u32, final_set: bool) -> (I, I) where - F: SqrtHelper, I: HInt + From, { let three_u2 = I::from(0b11u8) << (I::BITS - 2); @@ -365,175 +350,3 @@ static RSQRT_TAB: [u16; 128] = [ 0xc116, 0xc03c, 0xbf65, 0xbe90, 0xbdbe, 0xbcef, 0xbc23, 0xbb59, 0xba91, 0xb9cc, 0xb90a, 0xb84a, 0xb78c, 0xb6d0, 0xb617, 0xb560, ]; - -#[cfg(test)] -mod tests { - use super::*; - - /// Test behavior specified in IEEE 754 `squareRoot`. - fn spec_test() - where - F: Float + SqrtHelper, - F::Int: HInt, - F::Int: From, - F::Int: From, - F::Int: CastInto, - F::Int: CastInto, - u32: CastInto, - { - // Values that should return a NaN and raise invalid - let nan = [F::NEG_INFINITY, F::NEG_ONE, F::NAN, F::MIN]; - - // Values that return unaltered - let roundtrip = [F::ZERO, F::NEG_ZERO, F::INFINITY]; - - for x in nan { - let FpResult { val, status } = sqrt_round(x, Round::Nearest); - assert!(val.is_nan()); - assert!(status == Status::INVALID); - } - - for x in roundtrip { - let FpResult { val, status } = sqrt_round(x, Round::Nearest); - assert_biteq!(val, x); - assert!(status == Status::OK); - } - } - - #[test] - #[cfg(f16_enabled)] - fn sanity_check_f16() { - assert_biteq!(sqrt(100.0f16), 10.0); - assert_biteq!(sqrt(4.0f16), 2.0); - } - - #[test] - #[cfg(f16_enabled)] - fn spec_tests_f16() { - spec_test::(); - } - - #[test] - #[cfg(f16_enabled)] - #[allow(clippy::approx_constant)] - fn conformance_tests_f16() { - let cases = [ - (f16::PI, 0x3f17_u16), - (10000.0_f16, 0x5640_u16), - (f16::from_bits(0x0000000f), 0x13bf_u16), - (f16::INFINITY, f16::INFINITY.to_bits()), - ]; - - for (input, output) in cases { - assert_biteq!( - sqrt(input), - f16::from_bits(output), - "input: {input:?} ({:#018x})", - input.to_bits() - ); - } - } - - #[test] - fn sanity_check_f32() { - assert_biteq!(sqrt(100.0f32), 10.0); - assert_biteq!(sqrt(4.0f32), 2.0); - } - - #[test] - fn spec_tests_f32() { - spec_test::(); - } - - #[test] - #[allow(clippy::approx_constant)] - fn conformance_tests_f32() { - let cases = [ - (f32::PI, 0x3fe2dfc5_u32), - (10000.0f32, 0x42c80000_u32), - (f32::from_bits(0x0000000f), 0x1b2f456f_u32), - (f32::INFINITY, f32::INFINITY.to_bits()), - ]; - - for (input, output) in cases { - assert_biteq!( - sqrt(input), - f32::from_bits(output), - "input: {input:?} ({:#018x})", - input.to_bits() - ); - } - } - - #[test] - fn sanity_check_f64() { - assert_biteq!(sqrt(100.0f64), 10.0); - assert_biteq!(sqrt(4.0f64), 2.0); - } - - #[test] - fn spec_tests_f64() { - spec_test::(); - } - - #[test] - #[allow(clippy::approx_constant)] - fn conformance_tests_f64() { - let cases = [ - (f64::PI, 0x3ffc5bf891b4ef6a_u64), - (10000.0, 0x4059000000000000_u64), - (f64::from_bits(0x0000000f), 0x1e7efbdeb14f4eda_u64), - (f64::INFINITY, f64::INFINITY.to_bits()), - ]; - - for (input, output) in cases { - assert_biteq!( - sqrt(input), - f64::from_bits(output), - "input: {input:?} ({:#018x})", - input.to_bits() - ); - } - } - - #[test] - #[cfg(f128_enabled)] - fn sanity_check_f128() { - assert_biteq!(sqrt(100.0f128), 10.0); - assert_biteq!(sqrt(4.0f128), 2.0); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - spec_test::(); - } - - #[test] - #[cfg(f128_enabled)] - #[allow(clippy::approx_constant)] - fn conformance_tests_f128() { - let cases = [ - (f128::PI, 0x3fffc5bf891b4ef6aa79c3b0520d5db9_u128), - // 10_000.0, see `f16` for reasoning. - ( - f128::from_bits(0x400c3880000000000000000000000000), - 0x40059000000000000000000000000000_u128, - ), - ( - f128::from_bits(0x0000000f), - 0x1fc9efbdeb14f4ed9b17ae807907e1e9_u128, - ), - (f128::INFINITY, f128::INFINITY.to_bits()), - ]; - - for (input, output) in cases { - assert_biteq!( - sqrt(input), - f128::from_bits(output), - "input: {input:?} ({:#018x})", - input.to_bits() - ); - } - } -} diff --git a/compiler-builtins/libm/src/math/generic/trunc.rs b/compiler-builtins/libm/src/math/generic/trunc.rs index 7f18eb42e884a..0b252fab94ae1 100644 --- a/compiler-builtins/libm/src/math/generic/trunc.rs +++ b/compiler-builtins/libm/src/math/generic/trunc.rs @@ -3,11 +3,6 @@ use crate::support::{Float, FpResult, Int, IntTy, MinInt, Status}; -#[inline] -pub fn trunc(x: F) -> F { - trunc_status(x).val -} - #[inline] pub fn trunc_status(x: F) -> FpResult { let xi: F::Int = x.to_bits(); @@ -39,89 +34,3 @@ pub fn trunc_status(x: F) -> FpResult { // Now zero the bits we need to truncate and return. FpResult::new(F::from_bits(xi ^ cleared), status) } - -#[cfg(test)] -mod tests { - use super::*; - use crate::support::Hexf; - - macro_rules! cases { - ($f:ty) => { - [ - // roundtrip - (0.0, 0.0, Status::OK), - (-0.0, -0.0, Status::OK), - (1.0, 1.0, Status::OK), - (-1.0, -1.0, Status::OK), - (<$f>::INFINITY, <$f>::INFINITY, Status::OK), - (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), - // with rounding - (0.1, 0.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.5, 0.0, Status::INEXACT), - (-0.5, -0.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.5, 1.0, Status::INEXACT), - (-1.5, -1.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ] - }; - } - - #[track_caller] - fn check(cases: &[(F, F, Status)]) { - for &(x, exp_res, exp_stat) in cases { - let FpResult { val, status } = trunc_status(x); - assert_biteq!(val, exp_res, "{x:?} {}", Hexf(x)); - assert_eq!( - status, - exp_stat, - "{x:?} {} -> {exp_res:?} {}", - Hexf(x), - Hexf(exp_res) - ); - } - } - - #[test] - #[cfg(f16_enabled)] - fn check_f16() { - check::(&cases!(f16)); - check::(&[ - (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), - (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), - ]); - } - - #[test] - fn check_f32() { - check::(&cases!(f32)); - check::(&[ - (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), - (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), - ]); - } - - #[test] - fn check_f64() { - check::(&cases!(f64)); - check::(&[ - (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), - (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), - ]); - } - - #[test] - #[cfg(f128_enabled)] - fn spec_tests_f128() { - check::(&cases!(f128)); - check::(&[ - (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), - (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), - ]); - } -} diff --git a/compiler-builtins/libm/src/math/hypot.rs b/compiler-builtins/libm/src/math/hypot.rs index c0b2a19370cd7..e8bd44ca975d5 100644 --- a/compiler-builtins/libm/src/math/hypot.rs +++ b/compiler-builtins/libm/src/math/hypot.rs @@ -1,72 +1,301 @@ +/* SPDX-License-Identifier: MIT */ +/* origin: core-math/src/binary64/hypot/hypot.c + * Copyright (c) 2022 Alexei Sibidanov. + * Ported to Rust in 2025, TG + * Approximate CORE-MATH commit: 8ea8ea35c518 + */ + +//! Euclidian distance via the pythagorean theorem (`√(x2 + y2)`). +//! +//! Per IEEE 754-2019: +//! +//! - Domain: `[−∞, +∞] × [−∞, +∞]` +//! - `hypot(±0, ±0)` is +0 +//! - `hypot(±∞, qNaN)` is +∞ +//! - `hypot(qNaN, ±∞)` is +∞. +//! - May raise overflow or underflow + use super::sqrt; +#[allow(unused_imports)] // msrv compat +use super::support::Float; +use super::support::cold_path; + +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn hypot(x: f64, y: f64) -> f64 { + return cr_hypot(x, y); +} + +fn cr_hypot(mut x: f64, mut y: f64) -> f64 { + let flag = get_flags(); + + let xi = x.to_bits(); + let yi = y.to_bits(); + + let emsk: u64 = 0x7ffu64 << 52; + let mut ex: u64 = xi & emsk; + let mut ey: u64 = yi & emsk; + /* emsk corresponds to the upper bits of NaN and Inf (apart the sign bit) */ + x = x.abs(); + y = y.abs(); + if ex == emsk || ey == emsk { + cold_path(); + + /* Either x or y is NaN or Inf */ + let wx: u64 = xi << 1; + let wy: u64 = yi << 1; + let wm: u64 = emsk << 1; + + let one_inf = (wx == wm) ^ (wy == wm); + let one_nan = x.is_nan() ^ y.is_nan(); + + // let nqnn: i32 = (((wx >> 52) == 0xfff) ^ ((wy >> 52) == 0xfff)) as i32; + // /* ninf is 1 when only one of x and y is +/-Inf + // nqnn is 1 when only one of x and y is qNaN + // IEEE 754 says that hypot(+/-Inf,qNaN)=hypot(qNaN,+/-Inf)=+Inf. */ + if one_inf && one_nan { + return f64::INFINITY; + } + return x + y; /* inf, sNaN */ + } + + let u: f64 = x.max(y); + let v: f64 = x.min(y); + let mut xd: u64 = u.to_bits(); + let mut yd: u64 = v.to_bits(); + ey = yd; -const SPLIT: f64 = 134217728. + 1.; // 0x1p27 + 1 === (2 ^ 27) + 1 + if ey >> 52 == 0 { + cold_path(); -fn sq(x: f64) -> (f64, f64) { - let xh: f64; - let xl: f64; - let xc: f64; + if yd == 0 { + return f64::from_bits(xd); + } - xc = x * SPLIT; - xh = x - xc + xc; - xl = x - xh; - let hi = x * x; - let lo = xh * xh - hi + 2. * xh * xl + xl * xl; - (hi, lo) + ex = xd; + + if ex >> 52 == 0 { + cold_path(); + + if ex == 0 { + return 0.0; + } + + return as_hypot_denorm(ex, ey); + } + + let nz: u32 = ey.leading_zeros(); + ey <<= nz - 11; + ey &= u64::MAX >> 12; + ey = ey.wrapping_sub(((nz as i64 - 12i64) << 52) as u64); + let t = ey; // why did they do this? + yd = t; + } + + let de: u64 = xd.wrapping_sub(yd); + if de > (27_u64 << 52) { + cold_path(); + return hf64!("0x1p-27").fma(v, u); + } + + let off: i64 = (0x3ff_i64 << 52) - (xd & emsk) as i64; + xd = xd.wrapping_add(off as u64); + yd = yd.wrapping_add(off as u64); + x = f64::from_bits(xd); + y = f64::from_bits(yd); + let x2: f64 = x * x; + let dx2: f64 = x.fma(x, -x2); + let y2: f64 = y * y; + let dy2: f64 = y.fma(y, -y2); + let r2: f64 = x2 + y2; + let ir2: f64 = 0.5 / r2; + let dr2: f64 = ((x2 - r2) + y2) + (dx2 + dy2); + let mut th: f64 = sqrt(r2); + let rsqrt: f64 = th * ir2; + let dz: f64 = dr2 - th.fma(th, -r2); + let mut tl: f64 = rsqrt * dz; + th = fasttwosum(th, tl, &mut tl); + let mut thd: u64 = th.to_bits(); + let tld = tl.abs().to_bits(); + ex = thd; + ey = tld; + ex &= 0x7ff_u64 << 52; + let aidr: u64 = ey.wrapping_add(0x3fe_u64 << 52).wrapping_sub(ex); + let mid: u64 = (aidr.wrapping_sub(0x3c90000000000000).wrapping_add(16)) >> 5; + if mid == 0 || !(0x39b0000000000000_u64..=0x3c9fffffffffff80_u64).contains(&aidr) { + cold_path(); + thd = as_hypot_hard(x, y, flag).to_bits(); + } + thd = thd.wrapping_sub(off as u64); + if thd >= (0x7ff_u64 << 52) { + cold_path(); + return as_hypot_overflow(); + } + + f64::from_bits(thd) } -#[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub fn hypot(mut x: f64, mut y: f64) -> f64 { - let x1p700 = f64::from_bits(0x6bb0000000000000); // 0x1p700 === 2 ^ 700 - let x1p_700 = f64::from_bits(0x1430000000000000); // 0x1p-700 === 2 ^ -700 - - let mut uxi = x.to_bits(); - let mut uyi = y.to_bits(); - let uti; - let ex: i64; - let ey: i64; - let mut z: f64; - - /* arrange |x| >= |y| */ - uxi &= -1i64 as u64 >> 1; - uyi &= -1i64 as u64 >> 1; - if uxi < uyi { - uti = uxi; - uxi = uyi; - uyi = uti; +fn fasttwosum(x: f64, y: f64, e: &mut f64) -> f64 { + let s: f64 = x + y; + let z: f64 = s - x; + *e = y - z; + s +} + +fn as_hypot_overflow() -> f64 { + let z: f64 = hf64!("0x1.fffffffffffffp1023"); + let f = z + z; + if f > z { + // errno = ERANGE + } + f +} + +/// Here the square root is refined by Newton iterations: x^2+y^2 is exact +/// and fits in a 128-bit integer, so the approximation is squared (which +/// also fits in a 128-bit integer), compared and adjusted if necessary using +/// the exact value of x^2+y^2. +fn as_hypot_hard(x: f64, y: f64, flag: FExcept) -> f64 { + let op: f64 = 1.0 + hf64!("0x1p-54"); + let om: f64 = 1.0 - hf64!("0x1p-54"); + let mut xi: u64 = x.to_bits(); + let yi: u64 = y.to_bits(); + let mut bm: u64 = (xi & (u64::MAX >> 12)) | 1u64 << 52; + let mut lm: u64 = (yi & (u64::MAX >> 12)) | 1u64 << 52; + let be: i32 = (xi >> 52) as i32; + let le: i32 = (yi >> 52) as i32; + let ri: u64 = sqrt(x * x + y * y).to_bits(); + let bs: i32 = 2; + let mut rm: u64 = ri & (u64::MAX >> 12); + let mut re: i32 = (ri >> 52) as i32 - 0x3ff; + rm |= 1u64 << 52; + + for _ in 0..3 { + if rm == 1u64 << 52 { + rm = u64::MAX >> 11; + re -= 1; + } else { + cold_path(); + rm -= 1; + } + } + + bm <<= bs; + let mut m2: u64 = bm.wrapping_mul(bm); + let de: i32 = be - le; + let mut ls: i32 = bs - de; + + if ls >= 0 { + lm <<= ls; + m2 = m2.wrapping_add(lm.wrapping_mul(lm)); + } else { + cold_path(); + let lm2: u128 = (lm as u128) * (lm as u128); + ls *= 2; + m2 = m2.wrapping_add((lm2 >> -ls) as u64); + m2 |= ((lm2 << (128 + ls)) != 0) as u64; + } + + let k: i32 = bs + re; + let mut d: i64; + + loop { + rm += 1 + (rm >= (1u64 << 53)) as u64; + let tm: u64 = rm << k; + let rm2: u64 = tm.wrapping_mul(tm); + d = m2 as i64 - rm2 as i64; + + if d <= 0 { + break; + } } - /* special cases */ - ex = (uxi >> 52) as i64; - ey = (uyi >> 52) as i64; - x = f64::from_bits(uxi); - y = f64::from_bits(uyi); - /* note: hypot(inf,nan) == inf */ - if ey == 0x7ff { - return y; + if d == 0 { + set_flags(flag); + } else if op == om { + let tm: u64 = (rm << k) - (1 << (k - (rm <= (1u64 << 53)) as i32)); + d = m2 as i64 - (tm.wrapping_mul(tm)) as i64; + + if d == 0 { + cold_path(); + rm -= rm & 1; + } else { + rm = rm.wrapping_add((d >> 63) as u64); + } + } else { + cold_path(); + rm -= ((op == 1.0) as u64) << (rm > (1u64 << 53)) as u32; } - if ex == 0x7ff || uyi == 0 { - return x; + + if rm >= (1u64 << 53) { + rm >>= 1; + re += 1; } - /* note: hypot(x,y) ~= x + y*y/x/2 with inexact for small y/x */ - /* 64 difference is enough for ld80 double_t */ - if ex - ey > 64 { - return x + y; + + let e: u64 = (be - 1 + re) as u64; + xi = (e << 52) + rm; + + f64::from_bits(xi) +} + +fn as_hypot_denorm(mut a: u64, mut b: u64) -> f64 { + let op: f64 = 1.0 + hf64!("0x1p-54"); + let om: f64 = 1.0 - hf64!("0x1p-54"); + let af: f64 = a as i64 as f64; + let bf: f64 = b as i64 as f64; + a <<= 1; + b <<= 1; + // Is this casting right? + let mut rm: u64 = sqrt(af * af + bf * bf) as u64; + let tm: u64 = rm << 1; + let mut d: i64 = (a.wrapping_mul(a) as i64) + .wrapping_sub(tm.wrapping_mul(tm) as i64) + .wrapping_add(b.wrapping_mul(b) as i64); + let sd: i64 = d >> 63; + let um: i64 = ((rm as i64) ^ sd) - sd; + let mut drm: i64 = sd + 1; + let mut dd: i64 = (um << 3) + 4; + let mut p_d: i64; + rm -= drm as u64; + drm += sd; + loop { + p_d = d; + rm = rm.wrapping_add(drm as u64); + d = d.wrapping_sub(dd); + dd = dd.wrapping_add(8); + if (d ^ p_d) <= 0 { + cold_path(); + break; + } } + p_d = (sd & d) + (!sd & p_d); + if p_d != 0 { + if op == om { + let sum: i64 = p_d + .wrapping_sub(4u64.wrapping_mul(rm) as i64) + .wrapping_sub(1); - /* precise sqrt argument in nearest rounding mode without overflow */ - /* xh*xh must not overflow and xl*xl must not underflow in sq */ - z = 1.; - if ex > 0x3ff + 510 { - z = x1p700; - x *= x1p_700; - y *= x1p_700; - } else if ey < 0x3ff - 450 { - z = x1p_700; - x *= x1p700; - y *= x1p700; + if sum != 0 { + rm = rm.wrapping_add((sum >> 63).wrapping_add(1) as u64); + } else { + cold_path(); + rm += rm & 1; + } + } else { + cold_path(); + rm += (op > 1.0) as u64; + } + } else { + cold_path(); } - let (hx, lx) = sq(x); - let (hy, ly) = sq(y); - z * sqrt(ly + lx + hy + hx) + + let xi: u64 = rm; + f64::from_bits(xi) +} + +type FExcept = u32; + +fn set_flags(_flag: FExcept) {} + +fn get_flags() -> FExcept { + 0 } diff --git a/compiler-builtins/libm/src/math/j1f.rs b/compiler-builtins/libm/src/math/j1f.rs index cd829c1aa1213..d545a8635b127 100644 --- a/compiler-builtins/libm/src/math/j1f.rs +++ b/compiler-builtins/libm/src/math/j1f.rs @@ -374,8 +374,7 @@ mod tests { fn test_y1f_2002() { //allow slightly different result on x87 let res = y1f(2.0000002_f32); - if cfg!(all(target_arch = "x86", not(target_feature = "sse2"))) && (res == -0.10703231_f32) - { + if cfg!(x86_no_sse2) && (res == -0.10703231_f32) { return; } assert_eq!(res, -0.10703229_f32); diff --git a/compiler-builtins/libm/src/math/mod.rs b/compiler-builtins/libm/src/math/mod.rs index 4bee4478164a0..809d5e5d18092 100644 --- a/compiler-builtins/libm/src/math/mod.rs +++ b/compiler-builtins/libm/src/math/mod.rs @@ -75,6 +75,8 @@ cfg_if! { } } +pub mod approx; + // Private modules mod arch; mod expo2; @@ -294,12 +296,15 @@ pub use self::trunc::{trunc, truncf}; cfg_if! { if #[cfg(f16_enabled)] { + mod fmaf16; + // verify-sorted-start pub use self::ceil::ceilf16; pub use self::copysign::copysignf16; pub use self::fabs::fabsf16; pub use self::fdim::fdimf16; pub use self::floor::floorf16; + pub use self::fmaf16::fmaf16; pub use self::fmin_fmax::{fmaxf16, fminf16}; pub use self::fminimum_fmaximum::{fmaximumf16, fminimumf16}; pub use self::fminimum_fmaximum_num::{fmaximum_numf16, fminimum_numf16}; @@ -314,9 +319,6 @@ cfg_if! { pub use self::sqrt::sqrtf16; pub use self::trunc::truncf16; // verify-sorted-end - - #[allow(unused_imports)] - pub(crate) use self::fma::fmaf16; } } diff --git a/compiler-builtins/libm/src/math/pow.rs b/compiler-builtins/libm/src/math/pow.rs index 914d68cfce1a2..87eaab3c7c727 100644 --- a/compiler-builtins/libm/src/math/pow.rs +++ b/compiler-builtins/libm/src/math/pow.rs @@ -472,9 +472,9 @@ mod tests { let exp = expected(*val); let res = computed(*val); - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let exp = force_eval!(exp); - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let res = force_eval!(res); assert!( if exp.is_nan() { diff --git a/compiler-builtins/libm/src/math/rem_pio2.rs b/compiler-builtins/libm/src/math/rem_pio2.rs index 61b1030275a22..d2be3957358ae 100644 --- a/compiler-builtins/libm/src/math/rem_pio2.rs +++ b/compiler-builtins/libm/src/math/rem_pio2.rs @@ -53,7 +53,7 @@ pub(crate) fn rem_pio2(x: f64) -> (i32, f64, f64) { let tmp = x * INV_PIO2 + TO_INT; // force rounding of tmp to it's storage format on x87 to avoid // excess precision issues. - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let tmp = force_eval!(tmp); let f_n = tmp - TO_INT; let n = f_n as i32; @@ -195,7 +195,7 @@ mod tests { #[test] // FIXME(correctness): inaccurate results on i586 - #[cfg_attr(x86_no_sse, ignore)] + #[cfg_attr(x86_no_sse2, ignore)] fn test_near_pi() { let arg = 3.141592025756836; let arg = force_eval!(arg); diff --git a/compiler-builtins/libm/src/math/rem_pio2_large.rs b/compiler-builtins/libm/src/math/rem_pio2_large.rs index 841a51b84c278..8212c1a0a9f42 100644 --- a/compiler-builtins/libm/src/math/rem_pio2_large.rs +++ b/compiler-builtins/libm/src/math/rem_pio2_large.rs @@ -228,7 +228,7 @@ pub(crate) fn rem_pio2_large(x: &[f64], y: &mut [f64], e0: i32, prec: usize) -> // FIXME(rust-lang/rust#144518): Inline assembly would cause `no_panic` to fail // on the callers of this function. As a workaround, avoid inlining `floor` here // when implemented with assembly. - #[cfg_attr(x86_no_sse, inline(never))] + #[cfg_attr(x86_no_sse2, inline(never))] extern "C" fn floor(x: f64) -> f64 { super::floor(x) } diff --git a/compiler-builtins/libm/src/math/rem_pio2f.rs b/compiler-builtins/libm/src/math/rem_pio2f.rs index 481f7ee830bbb..bbf8042752137 100644 --- a/compiler-builtins/libm/src/math/rem_pio2f.rs +++ b/compiler-builtins/libm/src/math/rem_pio2f.rs @@ -44,7 +44,7 @@ pub(crate) fn rem_pio2f(x: f32) -> (i32, f64) { let tmp = x64 * INV_PIO2 + TOINT; // force rounding of tmp to it's storage format on x87 to avoid // excess precision issues. - #[cfg(all(target_arch = "x86", not(target_feature = "sse2")))] + #[cfg(x86_no_sse2)] let tmp = force_eval!(tmp); let f_n = tmp - TOINT; return (f_n as i32, x64 - f_n * PIO2_1 - f_n * PIO2_1T); diff --git a/compiler-builtins/libm/src/math/rint.rs b/compiler-builtins/libm/src/math/rint.rs index 011a7ae3d60ad..75c46acc0e856 100644 --- a/compiler-builtins/libm/src/math/rint.rs +++ b/compiler-builtins/libm/src/math/rint.rs @@ -1,4 +1,4 @@ -use super::support::Round; +use super::generic; /// Round `x` to the nearest integer, breaking ties toward even. #[cfg(f16_enabled)] @@ -10,7 +10,7 @@ pub fn rintf16(x: f16) -> f16 { args: x, } - super::generic::rint_round(x, Round::Nearest).val + generic::rint_status(x).val } /// Round `x` to the nearest integer, breaking ties toward even. @@ -25,7 +25,7 @@ pub fn rintf(x: f32) -> f32 { args: x, } - super::generic::rint_round(x, Round::Nearest).val + generic::rint_status(x).val } /// Round `x` to the nearest integer, breaking ties toward even. @@ -37,15 +37,120 @@ pub fn rint(x: f64) -> f64 { all(target_arch = "aarch64", target_feature = "neon"), all(target_arch = "wasm32", intrinsics_enabled), ), + use_arch_required: x86_no_sse2, args: x, } - super::generic::rint_round(x, Round::Nearest).val + generic::rint_status(x).val } /// Round `x` to the nearest integer, breaking ties toward even. #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn rintf128(x: f128) -> f128 { - super::generic::rint_round(x, Round::Nearest).val + generic::rint_status(x).val +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::support::{Float, FpResult, Hex, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 0.0, Status::INEXACT), + (-0.1, -0.0, Status::INEXACT), + (0.5, 0.0, Status::INEXACT), + (-0.5, -0.0, Status::INEXACT), + (0.9, 1.0, Status::INEXACT), + (-0.9, -1.0, Status::INEXACT), + (1.1, 1.0, Status::INEXACT), + (-1.1, -1.0, Status::INEXACT), + (1.5, 2.0, Status::INEXACT), + (-1.5, -2.0, Status::INEXACT), + (1.9, 2.0, Status::INEXACT), + (-1.9, -2.0, Status::INEXACT), + (2.5, 2.0, Status::INEXACT), + (-2.5, -2.0, Status::INEXACT), + (3.5, 4.0, Status::INEXACT), + (-3.5, -4.0, Status::INEXACT), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { + let FpResult { val, status } = generic::rint_status(x); + assert_biteq!(val, exp_res, "generic::rint_status({x:?}) ({})", Hex(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hex(x), + Hex(exp_res) + ); + let val = f(x); + assert_biteq!(val, exp_res, "rint({x:?}) ({})", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(rintf16, &cases!(f16)); + check::( + rintf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ], + ); + } + + #[test] + fn check_f32() { + check::(rintf, &cases!(f32)); + check::( + rintf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ], + ); + } + + #[test] + fn check_f64() { + check::(rint, &cases!(f64)); + check::( + rint, + &[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ], + ); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(rintf128, &cases!(f128)); + check::( + rintf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ], + ); + } } diff --git a/compiler-builtins/libm/src/math/round.rs b/compiler-builtins/libm/src/math/round.rs index 256197e6ccbee..091cd801ad6b4 100644 --- a/compiler-builtins/libm/src/math/round.rs +++ b/compiler-builtins/libm/src/math/round.rs @@ -1,25 +1,120 @@ +use super::generic; + /// Round `x` to the nearest integer, breaking ties away from zero. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundf16(x: f16) -> f16 { - super::generic::round(x) + generic::round(x) } /// Round `x` to the nearest integer, breaking ties away from zero. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundf(x: f32) -> f32 { - super::generic::round(x) + generic::round(x) } /// Round `x` to the nearest integer, breaking ties away from zero. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn round(x: f64) -> f64 { - super::generic::round(x) + generic::round(x) } /// Round `x` to the nearest integer, breaking ties away from zero. #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundf128(x: f128) -> f128 { - super::generic::round(x) + generic::round(x) +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::support::{Float, Hex}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0), + (-0.0, -0.0), + (1.0, 1.0), + (-1.0, -1.0), + (<$f>::INFINITY, <$f>::INFINITY), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY), + // with rounding + (0.1, 0.0), + (-0.1, -0.0), + (0.5, 1.0), + (-0.5, -1.0), + (0.9, 1.0), + (-0.9, -1.0), + (1.1, 1.0), + (-1.1, -1.0), + (1.5, 2.0), + (-1.5, -2.0), + (1.9, 2.0), + (-1.9, -2.0), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F)]) { + for &(x, exp_res) in cases { + let val = generic::round(x); + assert_biteq!(val, exp_res, "generic::round_status({x:?}) {}", Hex(x)); + let val = f(x); + assert_biteq!(val, exp_res, "round({x:?}) {}", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(roundf16, &cases!(f16)); + check::( + roundf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10")), + (hf16!("-0x1p10"), hf16!("-0x1p10")), + ], + ); + } + + #[test] + fn check_f32() { + check::(roundf, &cases!(f32)); + check::( + roundf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23")), + (hf32!("-0x1p23"), hf32!("-0x1p23")), + ], + ); + } + + #[test] + fn check_f64() { + check::(round, &cases!(f64)); + check::( + round, + &[ + (hf64!("0x1p52"), hf64!("0x1p52")), + (hf64!("-0x1p52"), hf64!("-0x1p52")), + ], + ); + } + + #[test] + #[cfg(f128_enabled)] + fn check_f128() { + check::(roundf128, &cases!(f128)); + check::( + roundf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112")), + (hf128!("-0x1p112"), hf128!("-0x1p112")), + ], + ); + } } diff --git a/compiler-builtins/libm/src/math/roundeven.rs b/compiler-builtins/libm/src/math/roundeven.rs index f0d67d41076ec..4cedd0c16b82d 100644 --- a/compiler-builtins/libm/src/math/roundeven.rs +++ b/compiler-builtins/libm/src/math/roundeven.rs @@ -1,25 +1,28 @@ -use super::support::{Float, Round}; +//! Note that we can use `rint` for these implementations since Rust expects the rounding +//! mode is always ties-to-even. `roundeven` also does not raise `FE_INEXACT`. +//! +//! Tested in the `rint` module. /// Round `x` to the nearest integer, breaking ties toward even. This is IEEE 754 /// `roundToIntegralTiesToEven`. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundevenf16(x: f16) -> f16 { - roundeven_impl(x) + super::rintf16(x) } /// Round `x` to the nearest integer, breaking ties toward even. This is IEEE 754 /// `roundToIntegralTiesToEven`. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundevenf(x: f32) -> f32 { - roundeven_impl(x) + super::rintf(x) } /// Round `x` to the nearest integer, breaking ties toward even. This is IEEE 754 /// `roundToIntegralTiesToEven`. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundeven(x: f64) -> f64 { - roundeven_impl(x) + super::rint(x) } /// Round `x` to the nearest integer, breaking ties toward even. This is IEEE 754 @@ -27,10 +30,5 @@ pub fn roundeven(x: f64) -> f64 { #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn roundevenf128(x: f128) -> f128 { - roundeven_impl(x) -} - -#[inline] -pub fn roundeven_impl(x: F) -> F { - super::generic::rint_round(x, Round::Nearest).val + super::rintf128(x) } diff --git a/compiler-builtins/libm/src/math/sin.rs b/compiler-builtins/libm/src/math/sin.rs index 5378a7bc3874a..2f54074c25ef0 100644 --- a/compiler-builtins/libm/src/math/sin.rs +++ b/compiler-builtins/libm/src/math/sin.rs @@ -86,7 +86,7 @@ mod tests { use super::*; #[test] - #[cfg_attr(x86_no_sse, ignore = "FIXME(i586): possible incorrect rounding")] + #[cfg_attr(x86_no_sse2, ignore = "FIXME(i586): possible incorrect rounding")] fn test_near_pi() { let x = f64::from_bits(0x400921fb000FD5DD); // 3.141592026217707 let sx = f64::from_bits(0x3ea50d15ced1a4a2); // 6.273720864039205e-7 diff --git a/compiler-builtins/libm/src/math/sqrt.rs b/compiler-builtins/libm/src/math/sqrt.rs index 7ba1bc9b32b23..10edf397a0a0a 100644 --- a/compiler-builtins/libm/src/math/sqrt.rs +++ b/compiler-builtins/libm/src/math/sqrt.rs @@ -1,3 +1,6 @@ +use super::generic; +use crate::support::Round; + /// The square root of `x` (f16). #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] @@ -8,7 +11,7 @@ pub fn sqrtf16(x: f16) -> f16 { args: x, } - return super::generic::sqrt(x); + return generic::sqrt_round(x, Round::Nearest).val; } /// The square root of `x` (f32). @@ -24,7 +27,7 @@ pub fn sqrtf(x: f32) -> f32 { args: x, } - super::generic::sqrt(x) + generic::sqrt_round(x, Round::Nearest).val } /// The square root of `x` (f64). @@ -40,12 +43,187 @@ pub fn sqrt(x: f64) -> f64 { args: x, } - super::generic::sqrt(x) + generic::sqrt_round(x, Round::Nearest).val } /// The square root of `x` (f128). #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn sqrtf128(x: f128) -> f128 { - return super::generic::sqrt(x); + return generic::sqrt_round(x, Round::Nearest).val; +} + +#[cfg(test)] +mod tests { + use generic::SqrtHelper; + + use super::*; + use crate::support::{CastInto, Float, FpResult, HInt, Status}; + + /// Test behavior specified in IEEE 754 `squareRoot`. + fn spec_test() + where + F: Float + SqrtHelper, + F::Int: HInt, + F::Int: From, + F::Int: From, + F::Int: CastInto, + F::Int: CastInto, + u32: CastInto, + { + // Values that should return a NaN and raise invalid + let nan = [F::NEG_INFINITY, F::NEG_ONE, F::NAN, F::MIN]; + + // Values that return unaltered + let roundtrip = [F::ZERO, F::NEG_ZERO, F::INFINITY]; + + for x in nan { + let FpResult { val, status } = generic::sqrt_round(x, Round::Nearest); + assert!(val.is_nan()); + assert!(status == Status::INVALID); + } + + for x in roundtrip { + let FpResult { val, status } = generic::sqrt_round(x, Round::Nearest); + assert_biteq!(val, x); + assert!(status == Status::OK); + } + } + + #[test] + #[cfg(f16_enabled)] + fn sanity_check_f16() { + assert_biteq!(sqrtf16(100.0f16), 10.0); + assert_biteq!(sqrtf16(4.0f16), 2.0); + } + + #[test] + #[cfg(f16_enabled)] + fn spec_tests_f16() { + spec_test::(); + } + + #[test] + #[cfg(f16_enabled)] + #[allow(clippy::approx_constant)] + fn conformance_tests_f16() { + let cases = [ + (f16::PI, 0x3f17_u16), + (10000.0_f16, 0x5640_u16), + (f16::from_bits(0x0000000f), 0x13bf_u16), + (f16::INFINITY, f16::INFINITY.to_bits()), + ]; + + for (input, output) in cases { + assert_biteq!( + sqrtf16(input), + f16::from_bits(output), + "input: {input:?} ({:#018x})", + input.to_bits() + ); + } + } + + #[test] + fn sanity_check_f32() { + assert_biteq!(sqrtf(100.0f32), 10.0); + assert_biteq!(sqrtf(4.0f32), 2.0); + } + + #[test] + fn spec_tests_f32() { + spec_test::(); + } + + #[test] + #[allow(clippy::approx_constant)] + fn conformance_tests_f32() { + let cases = [ + (f32::PI, 0x3fe2dfc5_u32), + (10000.0f32, 0x42c80000_u32), + (f32::from_bits(0x0000000f), 0x1b2f456f_u32), + (f32::INFINITY, f32::INFINITY.to_bits()), + ]; + + for (input, output) in cases { + assert_biteq!( + sqrtf(input), + f32::from_bits(output), + "input: {input:?} ({:#018x})", + input.to_bits() + ); + } + } + + #[test] + fn sanity_check_f64() { + assert_biteq!(sqrt(100.0f64), 10.0); + assert_biteq!(sqrt(4.0f64), 2.0); + } + + #[test] + fn spec_tests_f64() { + spec_test::(); + } + + #[test] + #[allow(clippy::approx_constant)] + fn conformance_tests_f64() { + let cases = [ + (f64::PI, 0x3ffc5bf891b4ef6a_u64), + (10000.0, 0x4059000000000000_u64), + (f64::from_bits(0x0000000f), 0x1e7efbdeb14f4eda_u64), + (f64::INFINITY, f64::INFINITY.to_bits()), + ]; + + for (input, output) in cases { + assert_biteq!( + sqrt(input), + f64::from_bits(output), + "input: {input:?} ({:#018x})", + input.to_bits() + ); + } + } + + #[test] + #[cfg(f128_enabled)] + fn sanity_check_f128() { + assert_biteq!(sqrtf128(100.0f128), 10.0); + assert_biteq!(sqrtf128(4.0f128), 2.0); + } + + #[test] + #[cfg(f128_enabled)] + fn spec_tests_f128() { + spec_test::(); + } + + #[test] + #[cfg(f128_enabled)] + #[allow(clippy::approx_constant)] + fn conformance_tests_f128() { + let cases = [ + (f128::PI, 0x3fffc5bf891b4ef6aa79c3b0520d5db9_u128), + // 10_000.0, see `f16` for reasoning. + ( + f128::from_bits(0x400c3880000000000000000000000000), + 0x40059000000000000000000000000000_u128, + ), + ( + f128::from_bits(0x0000000f), + 0x1fc9efbdeb14f4ed9b17ae807907e1e9_u128, + ), + (f128::INFINITY, f128::INFINITY.to_bits()), + ]; + + for (input, output) in cases { + assert_biteq!( + sqrtf128(input), + f128::from_bits(output), + "input: {input:?} ({:#018x})", + input.to_bits() + ); + } + } } diff --git a/compiler-builtins/libm/src/math/support/big.rs b/compiler-builtins/libm/src/math/support/big.rs index b7f1285424956..c316d93f524ab 100644 --- a/compiler-builtins/libm/src/math/support/big.rs +++ b/compiler-builtins/libm/src/math/support/big.rs @@ -3,7 +3,7 @@ #[cfg(test)] mod tests; -use core::ops; +use core::{fmt, ops}; use super::{DInt, HInt, Int, MinInt}; @@ -11,18 +11,18 @@ const U128_LO_MASK: u128 = u64::MAX as u128; /// A 256-bit unsigned integer represented as two 128-bit native-endian limbs. #[allow(non_camel_case_types)] -#[derive(Clone, Copy, Debug, PartialEq, PartialOrd, Eq, Ord)] +#[derive(Clone, Copy, PartialEq, PartialOrd, Eq, Ord)] pub struct u256 { pub hi: u128, pub lo: u128, } impl u256 { - #[cfg(any(test, feature = "unstable-public-internals"))] pub const MAX: Self = Self { lo: u128::MAX, hi: u128::MAX, }; + pub const MIN: Self = Self { lo: 0, hi: 0 }; /// Reinterpret as a signed integer pub fn signed(self) -> i256 { @@ -35,15 +35,23 @@ impl u256 { /// A 256-bit signed integer represented as two 128-bit native-endian limbs. #[allow(non_camel_case_types)] -#[derive(Clone, Copy, Debug, PartialEq, PartialOrd, Eq, Ord)] +#[derive(Clone, Copy, PartialEq, PartialOrd, Eq, Ord)] pub struct i256 { pub hi: i128, pub lo: u128, } impl i256 { + pub const MAX: Self = Self { + lo: u128::MAX, + hi: i128::MAX, + }; + pub const MIN: Self = Self { + lo: u128::MIN, + hi: i128::MIN, + }; + /// Reinterpret as an unsigned integer - #[cfg(any(test, feature = "unstable-public-internals"))] pub fn unsigned(self) -> u256 { u256 { lo: self.lo, @@ -61,11 +69,8 @@ impl MinInt for u256 { const BITS: u32 = 256; const ZERO: Self = Self { lo: 0, hi: 0 }; const ONE: Self = Self { lo: 1, hi: 0 }; - const MIN: Self = Self { lo: 0, hi: 0 }; - const MAX: Self = Self { - lo: u128::MAX, - hi: u128::MAX, - }; + const MIN: Self = Self::MIN; + const MAX: Self = Self::MAX; } impl MinInt for i256 { @@ -77,14 +82,8 @@ impl MinInt for i256 { const BITS: u32 = 256; const ZERO: Self = Self { lo: 0, hi: 0 }; const ONE: Self = Self { lo: 1, hi: 0 }; - const MIN: Self = Self { - lo: u128::MIN, - hi: i128::MIN, - }; - const MAX: Self = Self { - lo: u128::MAX, - hi: i128::MAX, - }; + const MIN: Self = Self::MIN; + const MAX: Self = Self::MAX; } macro_rules! impl_common { @@ -280,3 +279,35 @@ impl DInt for i256 { self.hi } } + +impl fmt::Debug for u256 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::LowerHex::fmt(self, f) + } +} + +impl fmt::Debug for i256 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::LowerHex::fmt(&self.unsigned(), f) + } +} + +impl fmt::LowerHex for u256 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + cfg_if! { + if #[cfg(feature = "compiler-builtins")] { + let _ = f; + unimplemented!() + } else { + let pfx= if f.alternate() { "0x"} else {""}; + write!(f, "{pfx}{:032x}{:032x}", self.hi, self.lo) + } + } + } +} + +impl fmt::LowerHex for i256 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::LowerHex::fmt(&self.unsigned(), f) + } +} diff --git a/compiler-builtins/libm/src/math/support/big/tests.rs b/compiler-builtins/libm/src/math/support/big/tests.rs index 2eafed50a2757..0ac8f9721a4dd 100644 --- a/compiler-builtins/libm/src/math/support/big/tests.rs +++ b/compiler-builtins/libm/src/math/support/big/tests.rs @@ -1,17 +1,11 @@ extern crate std; -use std::string::String; -use std::{eprintln, format}; +use std::eprintln; -use super::{HInt, MinInt, i256, u256}; +use super::{DInt, HInt, MinInt, i256, u256}; use crate::support::{Int as _, NarrowingDiv}; const LOHI_SPLIT: u128 = 0xaaaaaaaaaaaaaaaaffffffffffffffff; -/// Print a `u256` as hex since we can't add format implementations -fn hexu(v: u256) -> String { - format!("0x{:032x}{:032x}", v.hi, v.lo) -} - #[test] fn widen_u128() { assert_eq!( @@ -81,11 +75,9 @@ fn widen_mul_u128() { eprintln!( "\ FAILURE ({i}): {a:#034x} * {b:#034x}\n\ - expected: {}\n\ - got: {}\ + expected: {expected:#x}\n\ + actual: {actual:#x}\ ", - hexu(expected), - hexu(actual) ); }; @@ -106,6 +98,169 @@ fn not_u256() { assert_eq!(!u256::ZERO, u256::MAX); } +#[test] +fn shl_u256() { + let only_high = [ + 1, + u16::MAX.into(), + u32::MAX.into(), + u64::MAX.into(), + u128::MAX, + ]; + let mut has_errors = false; + + let mut add_error = |a, b, expected, actual| { + has_errors = true; + eprintln!( + "\ + FAILURE: {a:#x} << {b}\n\ + expected: {expected:#x}\n\ + actual: {actual:#x}\ + ", + ); + }; + + for a in only_high { + for perturb in 0..10 { + let a = a.saturating_add(perturb); + for shift in 0..128 { + let res = u256::from_lo_hi(0, a) << shift; + let expected = u256::from_lo_hi(0, a << shift); + if res != expected { + add_error(a.widen(), shift, expected, res); + } + } + } + } + + let check = [ + ( + u256::MAX, + 1, + u256 { + lo: u128::MAX << 1, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 5, + u256 { + lo: u128::MAX << 5, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 63, + u256 { + lo: u128::MAX << 63, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 64, + u256 { + lo: (u64::MAX as u128) << 64, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 65, + u256 { + lo: (u64::MAX as u128) << 65, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 127, + u256 { + lo: 1 << 127, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 128, + u256 { + lo: 0, + hi: u128::MAX, + }, + ), + ( + u256::MAX, + 129, + u256 { + lo: 0, + hi: u128::MAX << 1, + }, + ), + ( + u256::MAX, + 191, + u256 { + lo: 0, + hi: u128::MAX << 63, + }, + ), + ( + u256::MAX, + 192, + u256 { + lo: 0, + hi: u128::MAX << 64, + }, + ), + ( + u256::MAX, + 193, + u256 { + lo: 0, + hi: u128::MAX << 65, + }, + ), + ( + u256::MAX, + 254, + u256 { + lo: 0, + hi: 0b11 << 126, + }, + ), + ( + u256::MAX, + 255, + u256 { + lo: 0, + hi: 1 << 127, + }, + ), + ( + u256 { + hi: 0, + lo: LOHI_SPLIT, + }, + 64, + u256 { + lo: 0xffffffffffffffff0000000000000000, + hi: 0xaaaaaaaaaaaaaaaa, + }, + ), + ]; + + for (input, shift, expected) in check { + let res = input << shift; + if res != expected { + add_error(input, shift, expected, res); + } + } + + assert!(!has_errors); +} + #[test] fn shr_u256() { let only_low = [ @@ -121,13 +276,10 @@ fn shr_u256() { has_errors = true; eprintln!( "\ - FAILURE: {} >> {b}\n\ - expected: {}\n\ - actual: {}\ + FAILURE: {a:#x} >> {b}\n\ + expected: {expected:#x}\n\ + actual: {actual:#x}\ ", - hexu(a), - hexu(expected), - hexu(actual), ); }; @@ -269,10 +421,10 @@ fn shr_u256_overflow() { #[test] #[cfg(not(debug_assertions))] fn shr_u256_overflow() { - // No panic without debug assertions - assert_eq!(u256::MAX >> 256, u256::ZERO); - assert_eq!(u256::MAX >> 257, u256::ZERO); - assert_eq!(u256::MAX >> u32::MAX, u256::ZERO); + // Without debug assertions, the shift amount is wrapped + assert_eq!(u256::MAX >> 256, u256::MAX); + assert_eq!(u256::MAX >> 257, u256::MAX >> 1); + assert_eq!(u256::MAX >> u32::MAX, u256::ONE); } #[test] diff --git a/compiler-builtins/libm/src/math/support/float_traits.rs b/compiler-builtins/libm/src/math/support/float_traits.rs index 944546601c9ca..7bc9734a20994 100644 --- a/compiler-builtins/libm/src/math/support/float_traits.rs +++ b/compiler-builtins/libm/src/math/support/float_traits.rs @@ -1,6 +1,11 @@ use core::{fmt, mem, ops}; use super::int_traits::{CastFrom, Int, MinInt}; +use crate::support::{DInt, DisplayHex}; + +/// Wrapper to extract the integer type half of the float's size +#[allow(unused)] // only used in c-b +pub type HalfRep = <::Int as DInt>::H; /// Whether MIPS sNaN/qNaNs should be used. /// @@ -14,6 +19,7 @@ const MIPS_NAN: bool = cfg!(target_arch = "mips") || cfg!(target_arch = "mips64" pub trait Float: Copy + fmt::Debug + + DisplayHex + PartialEq + PartialOrd + ops::AddAssign @@ -56,14 +62,15 @@ pub trait Float: const FRAC_PI_2: Self; const MIN_POSITIVE_NORMAL: Self; + const MIN_POSITIVE_SUBNORMAL: Self; - /// The bitwidth of the float type + /// The bitwidth of the float type. const BITS: u32; - /// The bitwidth of the significand + /// The bitwidth of the significand (does not include the implicit bit). const SIG_BITS: u32; - /// The bitwidth of the exponent + /// The bitwidth of the exponent. const EXP_BITS: u32 = Self::BITS - Self::SIG_BITS - 1; /// The saturated (maximum bitpattern) value of the exponent, i.e. the infinite @@ -72,7 +79,7 @@ pub trait Float: /// This shifted fully right, use `EXP_MASK` for the shifted value. const EXP_SAT: u32 = (1 << Self::EXP_BITS) - 1; - /// The exponent bias value + /// The exponent bias value. const EXP_BIAS: u32 = Self::EXP_SAT >> 1; /// Maximum unbiased exponent value. @@ -120,13 +127,7 @@ pub trait Float: /// This method returns `true` if two NaNs are compared. Use [`biteq`](Self::biteq) instead /// if `NaN` should not be treated separately. #[allow(dead_code)] - fn eq_repr(self, rhs: Self) -> bool { - if self.is_nan() && rhs.is_nan() { - true - } else { - self.biteq(rhs) - } - } + fn eq_repr(self, rhs: Self) -> bool; /// Returns true if the value is NaN. fn is_nan(self) -> bool; @@ -283,6 +284,9 @@ macro_rules! float_impl { // Exponent is a 1 in the LSB const MIN_POSITIVE_NORMAL: Self = $from_bits(1 << Self::SIG_BITS); + // Single 1 in the LSB + const MIN_POSITIVE_SUBNORMAL: Self = $from_bits(1); + const PI: Self = core::$ty::consts::PI; const NEG_PI: Self = -Self::PI; const FRAC_PI_2: Self = core::$ty::consts::FRAC_PI_2; @@ -299,6 +303,27 @@ macro_rules! float_impl { fn to_bits(self) -> Self::Int { self.to_bits() } + + fn eq_repr(self, rhs: Self) -> bool { + #[cfg(not(feature = "unmangled-names"))] + fn is_nan(x: $ty) -> bool { + // When not using unmangled-names, the "real" compiler-builtins might not have + // the necessary builtin (__unordtf2) to test whether `f128` is NaN. + // FIXME(f128): Remove once the nightly toolchain has the __unordtf2 builtin + // x is NaN if all the bits of the exponent are set and the significand is non-0 + x.to_bits() & $ty::EXP_MASK == $ty::EXP_MASK && x.to_bits() & $ty::SIG_MASK != 0 + } + #[cfg(feature = "unmangled-names")] + fn is_nan(x: $ty) -> bool { + x.is_nan() + } + if is_nan(self) && is_nan(rhs) { + true + } else { + self.to_bits() == rhs.to_bits() + } + } + fn is_nan(self) -> bool { self.is_nan() } @@ -548,7 +573,7 @@ mod tests { } assert!(f32::NAN.is_qnan()); // FIXME(rust-lang/rust#115567): x87 use in `is_snan` quiets the sNaN - if !cfg!(x86_no_sse) { + if !cfg!(x86_no_sse2) { assert!(f32::SNAN.is_snan()); } @@ -593,7 +618,7 @@ mod tests { } assert!(f64::NAN.is_qnan()); // FIXME(rust-lang/rust#115567): x87 use in `is_snan` quiets the sNaN - if !cfg!(x86_no_sse) { + if !cfg!(x86_no_sse2) { assert!(f64::SNAN.is_snan()); } diff --git a/compiler-builtins/libm/src/math/support/hex_float.rs b/compiler-builtins/libm/src/math/support/hex_float.rs index 5be0d3159de3b..e1100a4a119f0 100644 --- a/compiler-builtins/libm/src/math/support/hex_float.rs +++ b/compiler-builtins/libm/src/math/support/hex_float.rs @@ -1,5 +1,7 @@ //! Utilities for working with hex float formats. +pub use hex_fmt::{DisplayHex, Hex}; + use super::{Round, Status, f32_from_bits, f64_from_bits}; /// Construct a 16-bit float from hex float representation (C-style) @@ -324,27 +326,32 @@ const fn hex_digit(c: u8) -> Option { } } -#[cfg(any(test, feature = "unstable-public-internals"))] mod hex_fmt { use core::fmt; - use crate::support::{Float, Int}; - - /// Format a floating point number as its IEEE hex (`%a`) representation. - pub struct Hexf(pub F); + use crate::support::{Float, div_ceil_u32}; // Adapted from https://github.com/ericseppanen/hexfloat2/blob/a5c27932f0ff/src/format.rs - #[cfg(not(feature = "compiler-builtins"))] pub(super) fn fmt_any_hex(x: &F, f: &mut fmt::Formatter<'_>) -> fmt::Result { if x.is_sign_negative() { write!(f, "-")?; + } else { + write!(f, "+")?; + } + + if x.is_nan() { + if x.is_snan() { + write!(f, "sNaN")?; + } else if x.is_nan() { + write!(f, "qNaN")?; + } + let payload = x.frac() & !F::SIG_TOP_BIT; + let width = div_ceil_u32(F::SIG_BITS, 4) as usize + 2; + write!(f, "({payload:#0width$x})")?; + return Ok(()); } - if x.is_snan() { - return write!(f, "sNaN"); - } else if x.is_nan() { - return write!(f, "qNaN"); - } else if x.is_infinite() { + if x.is_infinite() { return write!(f, "inf"); } else if *x == F::ZERO { return write!(f, "0x0p+0"); @@ -370,150 +377,136 @@ mod hex_fmt { write!(f, "0x{leading}{sig:0mwidth$x}p{exponent:+}") } - #[cfg(feature = "compiler-builtins")] - pub(super) fn fmt_any_hex(_x: &F, _f: &mut fmt::Formatter<'_>) -> fmt::Result { - unimplemented!() + /// Types that can be formatted as hex via `Hex`. For ints we always print with a fixed + /// number of leading zeros. For floats we use the IEEE hex (`%a`) representation. The `-` + /// format modifier is used to print the integer hex representation rather than hex float. + pub trait DisplayHex { + #[allow(unused)] // Only used for tests and public test internals + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result; } - impl fmt::LowerHex for Hexf { + /// A wrapper implementing formatting traits via `DisplayHex`. + #[allow(unused)] // Only used for tests and public test internals + pub struct Hex(pub T); + + impl fmt::Debug for Hex { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - fmt_any_hex(&self.0, f) - } - } + self.0.fmt(f) } } - impl fmt::LowerHex for Hexf<(F, F)> { + impl fmt::Display for Hex { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - write!(f, "({:x}, {:x})", Hexf(self.0.0), Hexf(self.0.1)) - } - } + self.0.fmt(f) } } - impl fmt::LowerHex for Hexf<(F, i32)> { + impl fmt::LowerHex for Hex { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - write!(f, "({:x}, {:x})", Hexf(self.0.0), Hexf(self.0.1)) - } - } + self.0.fmt(f) } } - impl fmt::LowerHex for Hexf { + impl DisplayHex for F { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - write!(f, "{:#010x}", self.0) - } + if f.sign_minus() { + self.to_bits().fmt(f) + } else { + fmt_any_hex(self, f) } } } - impl fmt::Debug for Hexf - where - Hexf: fmt::LowerHex, - { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - fmt::LowerHex::fmt(self, f) + macro_rules! impl_int { + ($ity:ty) => { + impl DisplayHex for $ity { + #[inline] + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!( + f, + "{self:#0width$x}", + width = ((<$ity>::BITS / 4) + 2) as usize, + ) } } - } + }; } - impl fmt::Display for Hexf - where - Hexf: fmt::LowerHex, - { + impl_int!(i8); + impl_int!(i16); + impl_int!(i32); + impl_int!(i64); + impl_int!(i128); + impl_int!(isize); + impl_int!(u8); + impl_int!(u16); + impl_int!(u32); + impl_int!(u64); + impl_int!(u128); + impl_int!(usize); + + // Not really a meaningful impl, but makes some generics easier. + impl DisplayHex for bool { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { cfg_if! { if #[cfg(feature = "compiler-builtins")] { let _ = f; unimplemented!() } else { - fmt::LowerHex::fmt(self, f) + write!(f, "{self}") } } } } - pub struct Hexi(pub F); - - impl fmt::LowerHex for Hexi { + impl DisplayHex for (T1,) + where + T1: Copy + DisplayHex, + { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - write!(f, "{:#0width$x}", self.0, width = ((I::BITS / 4) + 2) as usize) - } - } + write!(f, "(")?; + self.0.fmt(f)?; + write!(f, ",)") } } - impl fmt::Debug for Hexi + impl DisplayHex for (T1, T2) where - Hexi: fmt::LowerHex, + T1: Copy + DisplayHex, + T2: Copy + DisplayHex, { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - fmt::LowerHex::fmt(self, f) - } - } + write!(f, "(")?; + self.0.fmt(f)?; + write!(f, ", ")?; + self.1.fmt(f)?; + write!(f, ")") } } - impl fmt::Display for Hexi + impl DisplayHex for (T1, T2, T3) where - Hexi: fmt::LowerHex, + T1: Copy + DisplayHex, + T2: Copy + DisplayHex, + T3: Copy + DisplayHex, { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - cfg_if! { - if #[cfg(feature = "compiler-builtins")] { - let _ = f; - unimplemented!() - } else { - fmt::LowerHex::fmt(self, f) - } - } + write!(f, "(")?; + self.0.fmt(f)?; + write!(f, ", ")?; + self.1.fmt(f)?; + write!(f, ", ")?; + self.2.fmt(f)?; + write!(f, ")") } } } -#[cfg(any(test, feature = "unstable-public-internals"))] -pub use hex_fmt::*; - #[cfg(test)] mod parse_tests { extern crate std; - use std::string::String; + + use std::string::{String, ToString}; use std::{format, println}; use super::*; @@ -563,13 +556,17 @@ mod parse_tests { Ok(()) } + /// Strip the qNaN/sNaN and payload since we don't parse that. #[cfg_attr(not(f16_enabled), expect(unused))] - pub fn canonicalize_snan_str(s: String) -> String { + pub fn canonicalize_snan_str(mut s: String) -> String { if s.contains("sNaN") || s.contains("qNaN") { - s.replace("sNaN", "NaN").replace("qNaN", "NaN") - } else { - s + s = s.replace("sNaN", "NaN").replace("qNaN", "NaN"); + if let Some((nan, payload)) = s.split_once("(") { + assert!(payload.ends_with(")")); + s = nan.to_string(); + } } + s } #[test] @@ -578,7 +575,7 @@ mod parse_tests { let n = 1_i32 << 14; for i in -n..n { let u = i.rotate_right(11) as u32; - let s = format!("{}", Hexf(f32::from_bits(u))); + let s = format!("{}", Hex(f32::from_bits(u))); let s = canonicalize_snan_str(s); match rounding_properties(&s) { Ok(()) => (), @@ -653,7 +650,7 @@ mod parse_tests { #[cfg(f128_enabled)] fn rounding() { let pi = std::f128::consts::PI; - let s = format!("{}", Hexf(pi)); + let s = format!("{}", Hex(pi)); for k in 0..=111 { let (bits, status) = parse_any(&s, 128 - k, 112 - k, Round::Nearest).unwrap(); @@ -914,62 +911,59 @@ mod tests_panicking { extern crate std; use super::*; - // HACK(msrv): 1.63 rejects unknown width float literals at an AST level, so use a macro to - // hide them from the AST. + #[test] #[cfg(f16_enabled)] - macro_rules! f16_tests { - () => { - #[test] - fn test_f16_almost_extra_precision() { - // Exact maximum precision allowed - hf16("0x1.ffcp+0"); - } - - #[test] - #[should_panic(expected = "the value is too precise")] - fn test_f16_extra_precision() { - // One bit more than the above. - hf16("0x1.ffdp+0"); - } + fn test_f16_almost_extra_precision() { + // Exact maximum precision allowed + hf16("0x1.ffcp+0"); + } - #[test] - #[should_panic(expected = "the value is too huge")] - fn test_f16_overflow() { - // One bit more than the above. - hf16("0x1p+16"); - } + #[test] + #[cfg(f16_enabled)] + #[should_panic(expected = "the value is too precise")] + fn test_f16_extra_precision() { + // One bit more than the above. + hf16("0x1.ffdp+0"); + } - #[test] - fn test_f16_tiniest() { - let x = hf16("0x1.p-24"); - let y = hf16("0x0.001p-12"); - let z = hf16("0x0.8p-23"); - assert_eq!(x, y); - assert_eq!(x, z); - } + #[test] + #[cfg(f16_enabled)] + #[should_panic(expected = "the value is too huge")] + fn test_f16_overflow() { + // One bit more than the above. + hf16("0x1p+16"); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f16_too_tiny() { - hf16("0x1.p-25"); - } + #[test] + #[cfg(f16_enabled)] + fn test_f16_tiniest() { + let x = hf16("0x1.p-24"); + let y = hf16("0x0.001p-12"); + let z = hf16("0x0.8p-23"); + assert_eq!(x, y); + assert_eq!(x, z); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f16_also_too_tiny() { - hf16("0x0.8p-24"); - } + #[test] + #[cfg(f16_enabled)] + #[should_panic(expected = "the value is too tiny")] + fn test_f16_too_tiny() { + hf16("0x1.p-25"); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f16_again_too_tiny() { - hf16("0x0.001p-13"); - } - }; + #[test] + #[cfg(f16_enabled)] + #[should_panic(expected = "the value is too tiny")] + fn test_f16_also_too_tiny() { + hf16("0x0.8p-24"); } + #[test] #[cfg(f16_enabled)] - f16_tests!(); + #[should_panic(expected = "the value is too tiny")] + fn test_f16_again_too_tiny() { + hf16("0x0.001p-13"); + } #[test] fn test_f32_almost_extra_precision() { @@ -1038,68 +1032,66 @@ mod tests_panicking { hf64("0x1.abcdabcdabcdf8p+0"); } - // HACK(msrv): 1.63 rejects unknown width float literals at an AST level, so use a macro to - // hide them from the AST. + #[test] #[cfg(f128_enabled)] - macro_rules! f128_tests { - () => { - #[test] - fn test_f128_almost_extra_precision() { - // Exact maximum precision allowed - hf128("0x1.ffffffffffffffffffffffffffffp+16383"); - } - - #[test] - #[should_panic(expected = "the value is too precise")] - fn test_f128_extra_precision() { - // Just below the maximum finite. - hf128("0x1.fffffffffffffffffffffffffffe8p+16383"); - } - #[test] - #[should_panic(expected = "the value is too huge")] - fn test_f128_extra_precision_overflow() { - // One bit more than the above. Should overflow. - hf128("0x1.ffffffffffffffffffffffffffff8p+16383"); - } + fn test_f128_almost_extra_precision() { + // Exact maximum precision allowed + hf128("0x1.ffffffffffffffffffffffffffffp+16383"); + } - #[test] - #[should_panic(expected = "the value is too huge")] - fn test_f128_overflow() { - // One bit more than the above. - hf128("0x1p+16384"); - } + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too precise")] + fn test_f128_extra_precision() { + // Just below the maximum finite. + hf128("0x1.fffffffffffffffffffffffffffe8p+16383"); + } + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too huge")] + fn test_f128_extra_precision_overflow() { + // One bit more than the above. Should overflow. + hf128("0x1.ffffffffffffffffffffffffffff8p+16383"); + } - #[test] - fn test_f128_tiniest() { - let x = hf128("0x1.p-16494"); - let y = hf128("0x0.0000000000000001p-16430"); - let z = hf128("0x0.8p-16493"); - assert_eq!(x, y); - assert_eq!(x, z); - } + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too huge")] + fn test_f128_overflow() { + // One bit more than the above. + hf128("0x1p+16384"); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f128_too_tiny() { - hf128("0x1.p-16495"); - } + #[test] + #[cfg(f128_enabled)] + fn test_f128_tiniest() { + let x = hf128("0x1.p-16494"); + let y = hf128("0x0.0000000000000001p-16430"); + let z = hf128("0x0.8p-16493"); + assert_eq!(x, y); + assert_eq!(x, z); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f128_again_too_tiny() { - hf128("0x0.0000000000000001p-16431"); - } + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too tiny")] + fn test_f128_too_tiny() { + hf128("0x1.p-16495"); + } - #[test] - #[should_panic(expected = "the value is too tiny")] - fn test_f128_also_too_tiny() { - hf128("0x0.8p-16494"); - } - }; + #[test] + #[cfg(f128_enabled)] + #[should_panic(expected = "the value is too tiny")] + fn test_f128_again_too_tiny() { + hf128("0x0.0000000000000001p-16431"); } + #[test] #[cfg(f128_enabled)] - f128_tests!(); + #[should_panic(expected = "the value is too tiny")] + fn test_f128_also_too_tiny() { + hf128("0x0.8p-16494"); + } } #[cfg(test)] @@ -1119,7 +1111,7 @@ mod print_tests { use super::parse_tests::canonicalize_snan_str; let f = f16::from_bits(x); - let s = format!("{}", Hexf(f)); + let s = format!("{}", Hex(f)); let s = canonicalize_snan_str(s); let from_s = hf16(&s); @@ -1148,10 +1140,10 @@ mod print_tests { // - `f16 -> f32 -> str -> f16 -> f32` for x in 0..=u16::MAX { let f16 = f16::from_bits(x); - let s16 = format!("{}", Hexf(f16)); + let s16 = format!("{}", Hex(f16)); let s16 = canonicalize_snan_str(s16); let f32 = f16 as f32; - let s32 = format!("{}", Hexf(f32)); + let s32 = format!("{}", Hex(f32)); let s32 = canonicalize_snan_str(s32); let a = hf32(&s16); @@ -1181,66 +1173,94 @@ mod print_tests { } #[test] fn spot_checks() { - assert_eq!(Hexf(f32::MAX).to_string(), "0x1.fffffep+127"); - assert_eq!(Hexf(f64::MAX).to_string(), "0x1.fffffffffffffp+1023"); + assert_eq!(Hex(f32::MAX).to_string(), "+0x1.fffffep+127"); + assert_eq!(Hex(f64::MAX).to_string(), "+0x1.fffffffffffffp+1023"); - assert_eq!(Hexf(f32::MIN).to_string(), "-0x1.fffffep+127"); - assert_eq!(Hexf(f64::MIN).to_string(), "-0x1.fffffffffffffp+1023"); + assert_eq!(Hex(f32::MIN).to_string(), "-0x1.fffffep+127"); + assert_eq!(Hex(f64::MIN).to_string(), "-0x1.fffffffffffffp+1023"); - assert_eq!(Hexf(f32::ZERO).to_string(), "0x0p+0"); - assert_eq!(Hexf(f64::ZERO).to_string(), "0x0p+0"); + assert_eq!(Hex(f32::ZERO).to_string(), "+0x0p+0"); + assert_eq!(Hex(f64::ZERO).to_string(), "+0x0p+0"); - assert_eq!(Hexf(f32::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f64::NEG_ZERO).to_string(), "-0x0p+0"); + assert_eq!(Hex(f32::NEG_ZERO).to_string(), "-0x0p+0"); + assert_eq!(Hex(f64::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f32::NAN).to_string(), "qNaN"); - assert_eq!(Hexf(f64::NAN).to_string(), "qNaN"); - assert_eq!(Hexf(f32::NEG_NAN).to_string(), "-qNaN"); - assert_eq!(Hexf(f64::NEG_NAN).to_string(), "-qNaN"); - if !cfg!(x86_no_sse) { + assert_eq!(Hex(f32::NAN).to_string(), "+qNaN(0x000000)"); + assert_eq!(Hex(f64::NAN).to_string(), "+qNaN(0x0000000000000)"); + assert_eq!(Hex(f32::NEG_NAN).to_string(), "-qNaN(0x000000)"); + assert_eq!(Hex(f64::NEG_NAN).to_string(), "-qNaN(0x0000000000000)"); + if !cfg!(x86_no_sse2) { // FIXME(rust-lang/rust#115567): calls quiet the sNaN - assert_eq!(Hexf(f32::SNAN).to_string(), "sNaN"); - assert_eq!(Hexf(f64::SNAN).to_string(), "sNaN"); - assert_eq!(Hexf(f32::NEG_SNAN).to_string(), "-sNaN"); - assert_eq!(Hexf(f64::NEG_SNAN).to_string(), "-sNaN"); + assert_eq!(Hex(f32::SNAN).to_string(), "+sNaN(0x200000)"); + assert_eq!(Hex(f64::SNAN).to_string(), "+sNaN(0x4000000000000)"); + assert_eq!(Hex(f32::NEG_SNAN).to_string(), "-sNaN(0x200000)"); + assert_eq!(Hex(f64::NEG_SNAN).to_string(), "-sNaN(0x4000000000000)"); + assert_eq!(Hex(f32::from_bits(u32::MAX)).to_string(), "-qNaN(0x3fffff)"); + assert_eq!( + Hex(f64::from_bits(u64::MAX)).to_string(), + "-qNaN(0x7ffffffffffff)" + ); } - assert_eq!(Hexf(f32::INFINITY).to_string(), "inf"); - assert_eq!(Hexf(f64::INFINITY).to_string(), "inf"); + assert_eq!(Hex(f32::INFINITY).to_string(), "+inf"); + assert_eq!(Hex(f64::INFINITY).to_string(), "+inf"); - assert_eq!(Hexf(f32::NEG_INFINITY).to_string(), "-inf"); - assert_eq!(Hexf(f64::NEG_INFINITY).to_string(), "-inf"); + assert_eq!(Hex(f32::NEG_INFINITY).to_string(), "-inf"); + assert_eq!(Hex(f64::NEG_INFINITY).to_string(), "-inf"); #[cfg(f16_enabled)] { - assert_eq!(Hexf(f16::MAX).to_string(), "0x1.ffcp+15"); - assert_eq!(Hexf(f16::MIN).to_string(), "-0x1.ffcp+15"); - assert_eq!(Hexf(f16::ZERO).to_string(), "0x0p+0"); - assert_eq!(Hexf(f16::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f16::NAN).to_string(), "qNaN"); - assert_eq!(Hexf(f16::SNAN).to_string(), "sNaN"); - assert_eq!(Hexf(f16::NEG_NAN).to_string(), "-qNaN"); - assert_eq!(Hexf(f16::INFINITY).to_string(), "inf"); - assert_eq!(Hexf(f16::NEG_INFINITY).to_string(), "-inf"); + assert_eq!(Hex(f16::MAX).to_string(), "+0x1.ffcp+15"); + assert_eq!(Hex(f16::MIN).to_string(), "-0x1.ffcp+15"); + assert_eq!(Hex(f16::ZERO).to_string(), "+0x0p+0"); + assert_eq!(Hex(f16::NEG_ZERO).to_string(), "-0x0p+0"); + + assert_eq!(Hex(f16::NAN).to_string(), "+qNaN(0x000)"); + assert_eq!(Hex(f16::SNAN).to_string(), "+sNaN(0x100)"); + assert_eq!(Hex(f16::NEG_NAN).to_string(), "-qNaN(0x000)"); + assert_eq!(Hex(f16::NEG_SNAN).to_string(), "-sNaN(0x100)"); + assert_eq!(Hex(f16::from_bits(u16::MAX)).to_string(), "-qNaN(0x1ff)"); + + assert_eq!(Hex(f16::INFINITY).to_string(), "+inf"); + assert_eq!(Hex(f16::NEG_INFINITY).to_string(), "-inf"); } #[cfg(f128_enabled)] { assert_eq!( - Hexf(f128::MAX).to_string(), - "0x1.ffffffffffffffffffffffffffffp+16383" + Hex(f128::MAX).to_string(), + "+0x1.ffffffffffffffffffffffffffffp+16383" ); assert_eq!( - Hexf(f128::MIN).to_string(), + Hex(f128::MIN).to_string(), "-0x1.ffffffffffffffffffffffffffffp+16383" ); - assert_eq!(Hexf(f128::ZERO).to_string(), "0x0p+0"); - assert_eq!(Hexf(f128::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f128::NAN).to_string(), "qNaN"); - assert_eq!(Hexf(f128::SNAN).to_string(), "sNaN"); - assert_eq!(Hexf(f128::NEG_NAN).to_string(), "-qNaN"); - assert_eq!(Hexf(f128::INFINITY).to_string(), "inf"); - assert_eq!(Hexf(f128::NEG_INFINITY).to_string(), "-inf"); + assert_eq!(Hex(f128::ZERO).to_string(), "+0x0p+0"); + assert_eq!(Hex(f128::NEG_ZERO).to_string(), "-0x0p+0"); + + assert_eq!( + Hex(f128::NAN).to_string(), + "+qNaN(0x0000000000000000000000000000)" + ); + assert_eq!( + Hex(f128::SNAN).to_string(), + "+sNaN(0x4000000000000000000000000000)" + ); + assert_eq!( + Hex(f128::NEG_NAN).to_string(), + "-qNaN(0x0000000000000000000000000000)" + ); + assert_eq!( + Hex(f128::NEG_SNAN).to_string(), + "-sNaN(0x4000000000000000000000000000)" + ); + assert_eq!( + Hex(f128::from_bits(u128::MAX)).to_string(), + "-qNaN(0x7fffffffffffffffffffffffffff)" + ); + + assert_eq!(Hex(f128::INFINITY).to_string(), "+inf"); + assert_eq!(Hex(f128::NEG_INFINITY).to_string(), "-inf"); } } } diff --git a/compiler-builtins/libm/src/math/support/int_traits.rs b/compiler-builtins/libm/src/math/support/int_traits.rs index 55b609affd2e6..f113f9d62d143 100644 --- a/compiler-builtins/libm/src/math/support/int_traits.rs +++ b/compiler-builtins/libm/src/math/support/int_traits.rs @@ -3,6 +3,8 @@ use core::{cmp, fmt, ops}; mod narrowing_div; pub use narrowing_div::NarrowingDiv; +use crate::support::DisplayHex; + /// Minimal integer implementations needed on all integer types, including wide integers. #[allow(dead_code)] // Some constants are only used with tests pub trait MinInt: @@ -40,6 +42,7 @@ pub trait Int: + fmt::Display + fmt::Binary + fmt::LowerHex + + DisplayHex + ops::AddAssign + ops::SubAssign + ops::MulAssign diff --git a/compiler-builtins/libm/src/math/support/macros.rs b/compiler-builtins/libm/src/math/support/macros.rs index 550d2e92eb7c5..f1bfa21eec7f7 100644 --- a/compiler-builtins/libm/src/math/support/macros.rs +++ b/compiler-builtins/libm/src/math/support/macros.rs @@ -1,42 +1,67 @@ /// `libm` cannot have dependencies, so this is vendored directly from the `cfg-if` crate /// (with some comments stripped for compactness). macro_rules! cfg_if { - // match if/else chains with a final `else` - ($( - if #[cfg($meta:meta)] { $($tokens:tt)* } - ) else * else { - $($tokens2:tt)* - }) => { - cfg_if! { @__items () ; $( ( ($meta) ($($tokens)*) ), )* ( () ($($tokens2)*) ), } - }; - - // match if/else chains lacking a final `else` ( - if #[cfg($i_met:meta)] { $($i_tokens:tt)* } - $( else if #[cfg($e_met:meta)] { $($e_tokens:tt)* } )* + if #[cfg( $($i_meta:tt)+ )] { $( $i_tokens:tt )* } + $( + else if #[cfg( $($ei_meta:tt)+ )] { $( $ei_tokens:tt )* } + )* + $( + else { $( $e_tokens:tt )* } + )? ) => { cfg_if! { - @__items - () ; - ( ($i_met) ($($i_tokens)*) ), - $( ( ($e_met) ($($e_tokens)*) ), )* - ( () () ), + @__items () ; + (( $($i_meta)+ ) ( $( $i_tokens )* )), + $( + (( $($ei_meta)+ ) ( $( $ei_tokens )* )), + )* + $( + (() ( $( $e_tokens )* )), + )? } }; // Internal and recursive macro to emit all the items // - // Collects all the negated cfgs in a list at the beginning and after the - // semicolon is all the remaining items - (@__items ($($not:meta,)*) ; ) => {}; - (@__items ($($not:meta,)*) ; ( ($($m:meta),*) ($($tokens:tt)*) ), $($rest:tt)*) => { - #[cfg(all($($m,)* not(any($($not),*))))] cfg_if! { @__identity $($tokens)* } - cfg_if! { @__items ($($not,)* $($m,)*) ; $($rest)* } + // Collects all the previous cfgs in a list at the beginning, so they can be + // negated. After the semicolon are all the remaining items. + (@__items ( $( ($($_:tt)*) , )* ) ; ) => {}; + ( + @__items ( $( ($($no:tt)+) , )* ) ; + (( $( $($yes:tt)+ )? ) ( $( $tokens:tt )* )), + $( $rest:tt , )* + ) => { + // Emit all items within one block, applying an appropriate #[cfg]. The + // #[cfg] will require all `$yes` matchers specified and must also negate + // all previous matchers. + #[cfg(all( + $( $($yes)+ , )? + not(any( $( $($no)+ ),* )) + ))] + // Subtle: You might think we could put `$( $tokens )*` here. But if + // that contains multiple items then the `#[cfg(all(..))]` above would + // only apply to the first one. By wrapping `$( $tokens )*` in this + // macro call, we temporarily group the items into a single thing (the + // macro call) that will be included/excluded by the `#[cfg(all(..))]` + // as appropriate. If the `#[cfg(all(..))]` succeeds, the macro call + // will be included, and then evaluated, producing `$( $tokens )*`. See + // also the "issue #90" test below. + cfg_if! { @__temp_group $( $tokens )* } + + // Recurse to emit all other items in `$rest`, and when we do so add all + // our `$yes` matchers to the list of `$no` matchers as future emissions + // will have to negate everything we just matched as well. + cfg_if! { + @__items ( $( ($($no)+) , )* $( ($($yes)+) , )? ) ; + $( $rest , )* + } }; - // Internal macro to make __apply work out right for different match types, - // because of how macros matching/expand stuff. - (@__identity $($tokens:tt)*) => { $($tokens)* }; + // See the "Subtle" comment above. + (@__temp_group $( $tokens:tt )* ) => { + $( $tokens )* + }; } /// Choose between using an arch-specific implementation and the function body. Returns directly @@ -46,7 +71,7 @@ macro_rules! cfg_if { /// These live in the `math::arch::some_target_arch` module. /// /// Specify a `use_arch_required` meta field if something architecture-specific must be used -/// regardless of feature configuration (`force-soft-floats`). +/// regardless of feature configuration (`arch`). /// /// The passed meta options do not need to account for the `arch` target feature. macro_rules! select_implementation { @@ -71,8 +96,8 @@ macro_rules! select_implementation { } } - // By default, never use arch-specific implementations if we have force-soft-floats - #[cfg(arch_enabled)] + // By default, never use arch-specific implementations if `arch` is disabled. + #[cfg(feature = "arch")] select_implementation! { @cfg $($use_arch)?; // Wrap in `if true` to avoid unused warnings @@ -146,9 +171,9 @@ macro_rules! assert_biteq { "{}\nl: {l:?} ({lb:#0width$x} {lh})\nr: {r:?} ({rb:#0width$x} {rh})", format_args!($($tt)*), lb = l.to_bits(), - lh = $crate::support::Hexf(l), + lh = $crate::support::Hex(l), rb = r.to_bits(), - rh = $crate::support::Hexf(r), + rh = $crate::support::Hex(r), width = ((bits / 4) + 2) as usize, ); diff --git a/compiler-builtins/libm/src/math/support/mod.rs b/compiler-builtins/libm/src/math/support/mod.rs index 9dc872cdc1506..61999a1f94059 100644 --- a/compiler-builtins/libm/src/math/support/mod.rs +++ b/compiler-builtins/libm/src/math/support/mod.rs @@ -17,10 +17,8 @@ pub use big::{i256, u256}; pub(crate) use cfg_if; pub use env::{FpResult, Round, Status}; #[allow(unused_imports)] -pub use float_traits::{DFloat, Float, HFloat, IntTy}; +pub use float_traits::{DFloat, Float, HFloat, HalfRep, IntTy}; pub(crate) use float_traits::{f32_from_bits, f64_from_bits}; -#[cfg(any(test, feature = "unstable-public-internals"))] -pub use hex_float::Hexf; #[cfg(f16_enabled)] #[allow(unused_imports)] pub use hex_float::hf16; @@ -28,7 +26,7 @@ pub use hex_float::hf16; #[allow(unused_imports)] pub use hex_float::hf128; #[allow(unused_imports)] -pub use hex_float::{hf32, hf64}; +pub use hex_float::{DisplayHex, Hex, hf32, hf64}; pub use int_traits::{CastFrom, CastInto, DInt, HInt, Int, MinInt, NarrowingDiv}; pub use modular::linear_mul_reduction; @@ -70,3 +68,16 @@ pub unsafe fn unchecked_div_isize(x: isize, y: isize) -> isize { } } } + +// FIXME(msrv): `div_ceil` is stable in 1.73. +pub fn div_ceil_u32(a: u32, b: u32) -> u32 { + let d = a / b; + let r = a % b; + if r > 0 { d + 1 } else { d } +} + +// FIXME(msrv): unbounded shifts are stable in 1.87 +#[allow(unused)] +pub fn unbounded_shr_u64(x: u64, shift: u32) -> u64 { + x.checked_shr(shift).unwrap_or(0) +} diff --git a/compiler-builtins/libm/src/math/trunc.rs b/compiler-builtins/libm/src/math/trunc.rs index 20d52a111a120..9eb902ea578f8 100644 --- a/compiler-builtins/libm/src/math/trunc.rs +++ b/compiler-builtins/libm/src/math/trunc.rs @@ -1,10 +1,12 @@ +use super::generic; + /// Rounds the number toward 0 to the closest integral value (f16). /// /// This effectively removes the decimal part of the number, leaving the integral part. #[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn truncf16(x: f16) -> f16 { - super::generic::trunc(x) + generic::trunc_status(x).val } /// Rounds the number toward 0 to the closest integral value (f32). @@ -18,7 +20,7 @@ pub fn truncf(x: f32) -> f32 { args: x, } - super::generic::trunc(x) + generic::trunc_status(x).val } /// Rounds the number toward 0 to the closest integral value (f64). @@ -32,7 +34,7 @@ pub fn trunc(x: f64) -> f64 { args: x, } - super::generic::trunc(x) + generic::trunc_status(x).val } /// Rounds the number toward 0 to the closest integral value (f128). @@ -41,13 +43,105 @@ pub fn trunc(x: f64) -> f64 { #[cfg(f128_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn truncf128(x: f128) -> f128 { - super::generic::trunc(x) + generic::trunc_status(x).val } #[cfg(test)] mod tests { + use super::*; + use crate::support::{Float, FpResult, Hex, Status}; + + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 0.0, Status::INEXACT), + (-0.1, -0.0, Status::INEXACT), + (0.5, 0.0, Status::INEXACT), + (-0.5, -0.0, Status::INEXACT), + (0.9, 0.0, Status::INEXACT), + (-0.9, -0.0, Status::INEXACT), + (1.1, 1.0, Status::INEXACT), + (-1.1, -1.0, Status::INEXACT), + (1.5, 1.0, Status::INEXACT), + (-1.5, -1.0, Status::INEXACT), + (1.9, 1.0, Status::INEXACT), + (-1.9, -1.0, Status::INEXACT), + ] + }; + } + + #[track_caller] + fn check(f: fn(F) -> F, cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { + let FpResult { val, status } = generic::trunc_status(x); + assert_biteq!(val, exp_res, "generic::trunc_status({x:?}) ({})", Hex(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hex(x), + Hex(exp_res) + ); + let val = f(x); + assert_biteq!(val, exp_res, "trunc({x:?}) ({})", Hex(x)); + } + } + + #[test] + #[cfg(f16_enabled)] + fn check_f16() { + check::(truncf16, &cases!(f16)); + check::( + truncf16, + &[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ], + ); + } + + #[test] + fn check_f32() { + check::(truncf, &cases!(f32)); + check::( + truncf, + &[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ], + ); + } + + #[test] + fn check_f64() { + check::(trunc, &cases!(f64)); + check::( + trunc, + &[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ], + ); + } + #[test] - fn sanity_check() { - assert_eq!(super::truncf(1.1), 1.0); + #[cfg(f128_enabled)] + fn check_f128() { + check::(truncf128, &cases!(f128)); + check::( + truncf128, + &[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ], + ); } } diff --git a/compiler-builtins/rust-version b/compiler-builtins/rust-version index aa3876b14a221..e3a2981071adc 100644 --- a/compiler-builtins/rust-version +++ b/compiler-builtins/rust-version @@ -1 +1 @@ -db3e99bbab28c6ca778b13222becdea54533d908 +68ffae46b581747074413e4242ab0c6ecc4db4a9 diff --git a/core/src/alloc/mod.rs b/core/src/alloc/mod.rs index 18310cf98918d..102fb19efc8ea 100644 --- a/core/src/alloc/mod.rs +++ b/core/src/alloc/mod.rs @@ -377,7 +377,7 @@ pub const unsafe trait Allocator { #[unstable(feature = "allocator_api", issue = "32838")] #[rustc_const_unstable(feature = "const_heap", issue = "79597")] -unsafe impl const Allocator for &A +const unsafe impl Allocator for &A where A: [const] Allocator + ?Sized, { diff --git a/core/src/any.rs b/core/src/any.rs index 71a529400511c..862f01ecbedb1 100644 --- a/core/src/any.rs +++ b/core/src/any.rs @@ -666,7 +666,7 @@ impl dyn Any + Send + Sync { /// /// The following is an example program that tries to use `TypeId::of` to /// implement a generic type `Unique` that guarantees unique instances for each `Unique`, -/// that is, and for each type `T` there can be at most one value of type `Unique` at any time. +/// that is, for each type `T` there can be at most one value of type `Unique` at any time. /// /// ``` /// mod unique { @@ -739,33 +739,10 @@ unsafe impl Sync for TypeId {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for TypeId { +const impl PartialEq for TypeId { #[inline] fn eq(&self, other: &Self) -> bool { - #[cfg(miri)] - return crate::intrinsics::type_id_eq(*self, *other); - #[cfg(not(miri))] - { - let this = self; - crate::intrinsics::const_eval_select!( - @capture { this: &TypeId, other: &TypeId } -> bool: - if const { - crate::intrinsics::type_id_eq(*this, *other) - } else { - // Ideally we would just invoke `type_id_eq` unconditionally here, - // but since we do not MIR inline intrinsics, because backends - // may want to override them (and miri does!), MIR opts do not - // clean up this call sufficiently for LLVM to turn repeated calls - // of `TypeId` comparisons against one specific `TypeId` into - // a lookup table. - // SAFETY: We know that at runtime none of the bits have provenance and all bits - // are initialized. So we can just convert the whole thing to a `u128` and compare that. - unsafe { - crate::mem::transmute::<_, u128>(*this) == crate::mem::transmute::<_, u128>(*other) - } - } - ) - } + crate::intrinsics::type_id_eq(*self, *other) } } @@ -839,7 +816,7 @@ impl TypeId { self, trait_represented_by_type_id: TypeId, ) -> Option> { - if self.info().size.is_none() { + if self.size().is_none() { return None; } @@ -852,7 +829,7 @@ impl TypeId { } } - fn as_u128(self) -> u128 { + pub(crate) fn as_u128(self) -> u128 { let mut bytes = [0; 16]; // This is a provenance-stripping memcpy. @@ -1007,18 +984,23 @@ pub const fn type_name_of_val(_val: &T) -> &'static str { #[must_use] #[unstable(feature = "try_as_dyn", issue = "144361")] pub const fn try_as_dyn< - T: Any + 'static, + T: Any + ?Sized + 'static, U: ptr::Pointee> + ?Sized + 'static, >( t: &T, ) -> Option<&U> { + // For unsized `T`, `trait_info_of` always returns `None` (vtable lookup is + // only supported for sized types). The function therefore unconditionally + // returns `None` in that case. let vtable: Option> = const { TypeId::of::().trait_info_of::().as_ref().map(TraitImpl::get_vtable) }; match vtable { Some(dyn_metadata) => { - let pointer = ptr::from_raw_parts(t, dyn_metadata); + let pointer = ptr::from_raw_parts(t as *const T as *const (), dyn_metadata); // SAFETY: `t` is a reference to a type, so we know it is valid. // `dyn_metadata` is a vtable for T, implementing the trait of `U`. + // `T` is sized here because `trait_info_of` only returns `Some` for sized types, + // so the thin data pointer fully describes the value. Some(unsafe { &*pointer }) } None => None, @@ -1061,18 +1043,23 @@ pub const fn try_as_dyn< #[must_use] #[unstable(feature = "try_as_dyn", issue = "144361")] pub const fn try_as_dyn_mut< - T: Any + 'static, + T: Any + ?Sized + 'static, U: ptr::Pointee> + ?Sized + 'static, >( t: &mut T, ) -> Option<&mut U> { + // For unsized `T`, `trait_info_of` always returns `None` (vtable lookup is + // only supported for sized types). The function therefore unconditionally + // returns `None` in that case. let vtable: Option> = const { TypeId::of::().trait_info_of::().as_ref().map(TraitImpl::get_vtable) }; match vtable { Some(dyn_metadata) => { - let pointer = ptr::from_raw_parts_mut(t, dyn_metadata); + let pointer = ptr::from_raw_parts_mut(t as *mut T as *mut (), dyn_metadata); // SAFETY: `t` is a reference to a type, so we know it is valid. // `dyn_metadata` is a vtable for T, implementing the trait of `U`. + // `T` is sized here because `trait_info_of` only returns `Some` for sized types, + // so the thin data pointer fully describes the value. Some(unsafe { &mut *pointer }) } None => None, diff --git a/core/src/arch.rs b/core/src/arch.rs index e5078a45c6d9c..737a643ef8659 100644 --- a/core/src/arch.rs +++ b/core/src/arch.rs @@ -76,3 +76,33 @@ pub macro global_asm("assembly template", $(operands,)* $(options($(option),*))? pub fn breakpoint() { core::intrinsics::breakpoint(); } + +/// The `core::arch::return_address!()` macro returns a pointer with an address that corresponds to the caller of the function that invoked the `return_address!()` macro. +/// The pointer has no provenance, as if created by `core::ptr::without_provenance`. It cannot be used to read memory (other than ZSTs). +/// +/// The value returned by the macro depends highly on the architecture and compiler (including any options set). +/// In particular, it is allowed to be wrong (particularly if inlining is involved), or even contain a nonsense value. +/// The result of this macro must not be relied upon for soundness or correctness, only for debugging purposes. +/// +/// As a best effort, if a useful value cannot be determined (for example, due to limitations on the current codegen), +/// this macro tries to return a null pointer instead of nonsense (this cannot be relied upon for correctness, however). +/// +/// Formally, this function returns a pointer with a non-deterministic address and no provenance. +/// +/// This is equivalent to the gcc `__builtin_return_address(0)` intrinsic (other forms of the intrinsic are not supported). +/// Because the operation can be always performed by the compiler without crashing or causing undefined behaviour, invoking the macro is a safe operation. +/// +/// ## Example +/// ``` +/// #![feature(return_address)] +/// +/// # fn run_test() { +/// let addr = core::arch::return_address!(); +/// println!("Caller is {addr:p}"); +/// # } +/// # #[cfg(not(miri))] // FIXME: Figure out how to make miri work before stabilizing this macro +/// # run_test() +/// ``` +#[unstable(feature = "return_address", issue = "154966")] +#[allow_internal_unstable(core_intrinsics)] +pub macro return_address() {{ core::intrinsics::return_address() }} diff --git a/core/src/array/drain.rs b/core/src/array/drain.rs index 17792dca583d2..96a5a3178c11e 100644 --- a/core/src/array/drain.rs +++ b/core/src/array/drain.rs @@ -1,22 +1,23 @@ use crate::marker::{Destruct, PhantomData}; -use crate::mem::{ManuallyDrop, SizedTypeProperties, conjure_zst}; -use crate::ptr::{NonNull, drop_in_place, from_raw_parts_mut, null_mut}; +use crate::mem::{ManuallyDrop, SizedTypeProperties, conjure_zst, transmute}; +use crate::ptr::{NonNull, drop_in_place, from_raw_parts_mut, without_provenance_mut}; -impl<'l, 'f, T, U, const N: usize, F: FnMut(T) -> U> Drain<'l, 'f, T, N, F> { +impl<'l, 'f, T, U, F: FnMut(T) -> U> Drain<'l, 'f, T, F> { /// This function returns a function that lets you index the given array in const. /// As implemented it can optimize better than iterators, and can be constified. /// It acts like a sort of guard (owns the array) and iterator combined, which can be implemented - /// as it is a struct that implements const fn; - /// in that regard it is somewhat similar to an array::Iter implementing `UncheckedIterator`. + /// as it is a struct that implements const fn. /// The only method you're really allowed to call is `next()`, /// anything else is more or less UB, hence this function being unsafe. /// Moved elements will not be dropped. /// This will also not actually store the array. /// /// SAFETY: must only be called `N` times. Thou shalt not drop the array either. - // FIXME(const-hack): this is a hack for `let guard = Guard(array); |i| f(guard[i])`. #[rustc_const_unstable(feature = "array_try_map", issue = "79711")] - pub(super) const unsafe fn new(array: &'l mut ManuallyDrop<[T; N]>, f: &'f mut F) -> Self { + pub(super) const unsafe fn new( + array: &'l mut ManuallyDrop<[T; N]>, + f: &'f mut F, + ) -> Self { // dont drop the array, transfers "ownership" to Self let ptr: NonNull = NonNull::from_mut(array).cast(); // SAFETY: @@ -24,16 +25,17 @@ impl<'l, 'f, T, U, const N: usize, F: FnMut(T) -> U> Drain<'l, 'f, T, N, F> { // at the end of `slice`. `end` will never be dereferenced, only checked // for direct pointer equality with `ptr` to check if the drainer is done. unsafe { - let end = if T::IS_ZST { null_mut() } else { ptr.as_ptr().add(N) }; - Self { ptr, end, f, l: PhantomData } + let end_or_len = + if T::IS_ZST { without_provenance_mut(N) } else { ptr.as_ptr().add(N) }; + Self { ptr, end_or_len, f, l: PhantomData } } } } /// See [`Drain::new`]; this is our fake iterator. #[unstable(feature = "array_try_map", issue = "79711")] -pub(super) struct Drain<'l, 'f, T, const N: usize, F> { - // FIXME(const-hack): This is essentially a slice::IterMut<'static>, replace when possible. +pub(super) struct Drain<'l, 'f, T, F> { + // FIXME(const-hack): This is a slice::IterMut<'l>, replace when possible. /// The pointer to the next element to return, or the past-the-end location /// if the drainer is empty. /// @@ -41,16 +43,16 @@ pub(super) struct Drain<'l, 'f, T, const N: usize, F> { /// As we "own" this array, we dont need to store any lifetime. ptr: NonNull, /// For non-ZSTs, the non-null pointer to the past-the-end element. - /// For ZSTs, this is null. - end: *mut T, + /// For ZSTs, this is the number of unprocessed items. + end_or_len: *mut T, f: &'f mut F, - l: PhantomData<&'l mut [T; N]>, + l: PhantomData<&'l mut [T]>, } #[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] -impl const FnOnce<(usize,)> for &mut Drain<'_, '_, T, N, F> +const impl FnOnce<(usize,)> for &mut Drain<'_, '_, T, F> where F: [const] FnMut(T) -> U, { @@ -63,7 +65,7 @@ where } #[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] -impl const FnMut<(usize,)> for &mut Drain<'_, '_, T, N, F> +const impl FnMut<(usize,)> for &mut Drain<'_, '_, T, F> where F: [const] FnMut(T) -> U, { @@ -73,6 +75,16 @@ where (_ /* ignore argument */,): (usize,), ) -> Self::Output { if T::IS_ZST { + #[expect(ptr_to_integer_transmute_in_consts)] + // SAFETY: + // This is equivalent to `self.end_or_len.addr`, but that's not + // available in `const`. `self.end_or_len` doesn't have provenance, + // so transmuting is fine. + let len = unsafe { transmute::<*mut T, usize>(self.end_or_len) }; + // SAFETY: + // The caller guarantees that this is never called more than N times + // (see `Drain::new`), hence this cannot underflow. + self.end_or_len = without_provenance_mut(unsafe { len.unchecked_sub(1) }); // its UB to call this more than N times, so returning more ZSTs is valid. // SAFETY: its a ZST? we conjur. (self.f)(unsafe { conjure_zst::() }) @@ -88,20 +100,32 @@ where } #[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] -impl const Drop for Drain<'_, '_, T, N, F> { +const impl Drop for Drain<'_, '_, T, F> { fn drop(&mut self) { - if !T::IS_ZST { + let slice = if T::IS_ZST { + from_raw_parts_mut::<[T]>( + self.ptr.as_ptr(), + #[expect(ptr_to_integer_transmute_in_consts)] + // SAFETY: + // This is equivalent to `self.end_or_len.addr`, but that's not + // available in `const`. `self.end_or_len` doesn't have provenance, + // so transmuting is fine. + unsafe { + transmute::<*mut T, usize>(self.end_or_len) + }, + ) + } else { // SAFETY: we cant read more than N elements - let slice = unsafe { + unsafe { from_raw_parts_mut::<[T]>( self.ptr.as_ptr(), // SAFETY: `start <= end` - self.end.offset_from_unsigned(self.ptr.as_ptr()), + self.end_or_len.offset_from_unsigned(self.ptr.as_ptr()), ) - }; + } + }; - // SAFETY: By the type invariant, we're allowed to drop all these. (we own it, after all) - unsafe { drop_in_place(slice) } - } + // SAFETY: By the type invariant, we're allowed to drop all these. (we own it, after all) + unsafe { drop_in_place(slice) } } } diff --git a/core/src/array/equality.rs b/core/src/array/equality.rs index ec79a657e58e2..d4692ca478388 100644 --- a/core/src/array/equality.rs +++ b/core/src/array/equality.rs @@ -2,7 +2,7 @@ use crate::cmp::BytewiseEq; #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U; N]> for [T; N] +const impl PartialEq<[U; N]> for [T; N] where T: [const] PartialEq, { @@ -18,7 +18,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U]> for [T; N] +const impl PartialEq<[U]> for [T; N] where T: [const] PartialEq, { @@ -40,7 +40,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U; N]> for [T] +const impl PartialEq<[U; N]> for [T] where T: [const] PartialEq, { @@ -62,7 +62,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<&[U]> for [T; N] +const impl PartialEq<&[U]> for [T; N] where T: [const] PartialEq, { @@ -78,7 +78,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U; N]> for &[T] +const impl PartialEq<[U; N]> for &[T] where T: [const] PartialEq, { @@ -94,7 +94,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<&mut [U]> for [T; N] +const impl PartialEq<&mut [U]> for [T; N] where T: [const] PartialEq, { @@ -110,7 +110,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U; N]> for &mut [T] +const impl PartialEq<[U; N]> for &mut [T] where T: [const] PartialEq, { @@ -130,7 +130,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for [T; N] {} +const impl Eq for [T; N] {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] const trait SpecArrayEq: Sized { @@ -139,7 +139,7 @@ const trait SpecArrayEq: Sized { } #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl, Other, const N: usize> const SpecArrayEq for T { +const impl, Other, const N: usize> SpecArrayEq for T { default fn spec_eq(a: &[Self; N], b: &[Other; N]) -> bool { a[..] == b[..] } @@ -149,7 +149,7 @@ impl, Other, const N: usize> const SpecArrayEq, U, const N: usize> const SpecArrayEq for T { +const impl, U, const N: usize> SpecArrayEq for T { fn spec_eq(a: &[T; N], b: &[U; N]) -> bool { // SAFETY: Arrays are compared element-wise, and don't add any padding // between elements, so when the elements are `BytewiseEq`, we can diff --git a/core/src/array/iter.rs b/core/src/array/iter.rs index cd2a9e00b5a6e..7aed4a1324060 100644 --- a/core/src/array/iter.rs +++ b/core/src/array/iter.rs @@ -23,11 +23,13 @@ pub struct IntoIter { impl IntoIter { #[inline] - fn unsize(&self) -> &InnerUnsized { + #[rustc_const_unstable(feature = "const_iter", issue = "92476")] + const fn unsize(&self) -> &InnerUnsized { self.inner.deref() } #[inline] - fn unsize_mut(&mut self) -> &mut InnerUnsized { + #[rustc_const_unstable(feature = "const_iter", issue = "92476")] + const fn unsize_mut(&mut self) -> &mut InnerUnsized { self.inner.deref_mut() } } @@ -219,7 +221,8 @@ impl IntoIter { /// Returns a mutable slice of all elements that have not been yielded yet. #[stable(feature = "array_value_iter", since = "1.51.0")] #[inline] - pub fn as_mut_slice(&mut self) -> &mut [T] { + #[rustc_const_unstable(feature = "const_iter", issue = "92476")] + pub const fn as_mut_slice(&mut self) -> &mut [T] { self.unsize_mut().as_mut_slice() } } diff --git a/core/src/array/iter/iter_inner.rs b/core/src/array/iter/iter_inner.rs index 3c2343591f8cf..d93cbf32c0162 100644 --- a/core/src/array/iter/iter_inner.rs +++ b/core/src/array/iter/iter_inner.rs @@ -1,9 +1,10 @@ //! Defines the `IntoIter` owned iterator for arrays. +use crate::clone::TrivialClone; use crate::mem::MaybeUninit; use crate::num::NonZero; use crate::ops::{IndexRange, NeverShortCircuit, Try}; -use crate::{fmt, iter}; +use crate::{fmt, iter, ptr}; #[allow(private_bounds)] trait PartialDrop { @@ -99,9 +100,26 @@ impl PolymorphicIter<[MaybeUninit; N]> { impl Clone for PolymorphicIter<[MaybeUninit; N]> { #[inline] fn clone(&self) -> Self { + SpecPolymorphicIterClone::::spec_clone(self) + } +} + +trait SpecPolymorphicIterClone { + fn spec_clone( + this: &PolymorphicIter<[MaybeUninit; N]>, + ) -> PolymorphicIter<[MaybeUninit; N]> + where + Self: Sized; +} + +impl SpecPolymorphicIterClone for T { + #[inline] + default fn spec_clone( + this: &PolymorphicIter<[MaybeUninit; N]>, + ) -> PolymorphicIter<[MaybeUninit; N]> { // Note, we don't really need to match the exact same alive range, so // we can just clone into offset 0 regardless of where `self` is. - let mut new = Self::empty(); + let mut new = PolymorphicIter::<[MaybeUninit; N]>::empty(); fn clone_into_new( source: &PolymorphicIter<[MaybeUninit]>, @@ -118,7 +136,33 @@ impl Clone for PolymorphicIter<[MaybeUninit; N]> { } } - clone_into_new(self, &mut new); + clone_into_new(this, &mut new); + new + } +} + +impl SpecPolymorphicIterClone for T { + #[inline] + fn spec_clone( + this: &PolymorphicIter<[MaybeUninit; N]>, + ) -> PolymorphicIter<[MaybeUninit; N]> { + // Note, we don't really need to match the exact same alive range, so + // we can just clone into offset 0 regardless of where `self` is. + let mut new = PolymorphicIter::<[MaybeUninit; N]>::empty(); + + let len = this.alive.len(); + + // SAFETY: These two allocations can not overlap since `new` is allocated + // on the stack of this function. + unsafe { + ptr::copy_nonoverlapping( + this.data.as_ptr().add(this.alive.start()), + new.data.as_mut_ptr(), + len, + ); + new.alive = IndexRange::zero_to(len); + } + new } } @@ -134,7 +178,8 @@ impl PolymorphicIter<[MaybeUninit]> { } #[inline] - pub(super) fn as_mut_slice(&mut self) -> &mut [T] { + #[rustc_const_unstable(feature = "const_iter", issue = "92476")] + pub(super) const fn as_mut_slice(&mut self) -> &mut [T] { // SAFETY: We know that all elements within `alive` are properly initialized. unsafe { let slice = self.data.get_unchecked_mut(self.alive.clone()); diff --git a/core/src/array/mod.rs b/core/src/array/mod.rs index b116841578902..5784dbed03634 100644 --- a/core/src/array/mod.rs +++ b/core/src/array/mod.rs @@ -11,7 +11,7 @@ use crate::convert::Infallible; use crate::error::Error; use crate::hash::{self, Hash}; use crate::intrinsics::transmute_unchecked; -use crate::iter::{UncheckedIterator, repeat_n}; +use crate::iter::{TrustedLen, repeat_n}; use crate::marker::Destruct; use crate::mem::{self, ManuallyDrop, MaybeUninit}; use crate::ops::{ @@ -52,7 +52,10 @@ pub use iter::IntoIter; #[must_use = "cloning is often expensive and is not expected to have side effects"] #[stable(feature = "array_repeat", since = "1.91.0")] pub fn repeat(val: T) -> [T; N] { - from_trusted_iterator(repeat_n(val, N)) + let mut iter = repeat_n(val, N); + // SAFETY: Unless a panic occurs, from_fn will call the closure N times, + // and repeat_n's next() will return Some for N times. + from_fn(move |_| unsafe { iter.next().unwrap_unchecked() }) } /// Creates an array where each element is produced by calling `f` with @@ -90,10 +93,8 @@ pub fn repeat(val: T) -> [T; N] { /// You can also capture things, for example to create an array full of clones /// where you can't just use `[item; N]` because it's not `Copy`: /// ``` -/// # // TBH `array::repeat` would be better for this, but it's not stable yet. -/// let my_string = String::from("Hello"); -/// let clones: [String; 42] = std::array::from_fn(|_| my_string.clone()); -/// assert!(clones.iter().all(|x| *x == my_string)); +/// let my_string: [String; 2] = std::array::from_fn(|i| format!("Hello {i}")); +/// assert_eq!(my_string, ["Hello 0", "Hello 1"]); /// ``` /// /// The array is generated in ascending index order, starting from the front @@ -194,7 +195,7 @@ impl Error for TryFromSliceError {} #[stable(feature = "try_from_slice_error", since = "1.36.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for TryFromSliceError { +const impl From for TryFromSliceError { fn from(x: Infallible) -> TryFromSliceError { match x {} } @@ -202,7 +203,7 @@ impl const From for TryFromSliceError { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef<[T]> for [T; N] { +const impl AsRef<[T]> for [T; N] { #[inline] fn as_ref(&self) -> &[T] { &self[..] @@ -211,7 +212,7 @@ impl const AsRef<[T]> for [T; N] { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut<[T]> for [T; N] { +const impl AsMut<[T]> for [T; N] { #[inline] fn as_mut(&mut self) -> &mut [T] { &mut self[..] @@ -220,7 +221,7 @@ impl const AsMut<[T]> for [T; N] { #[stable(feature = "array_borrow", since = "1.4.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow<[T]> for [T; N] { +const impl Borrow<[T]> for [T; N] { fn borrow(&self) -> &[T] { self } @@ -228,7 +229,7 @@ impl const Borrow<[T]> for [T; N] { #[stable(feature = "array_borrow", since = "1.4.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const BorrowMut<[T]> for [T; N] { +const impl BorrowMut<[T]> for [T; N] { fn borrow_mut(&mut self) -> &mut [T] { self } @@ -248,7 +249,7 @@ impl const BorrowMut<[T]> for [T; N] { /// ``` #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom<&[T]> for [T; N] +const impl TryFrom<&[T]> for [T; N] where T: Copy, { @@ -274,7 +275,7 @@ where /// ``` #[stable(feature = "try_from_mut_slice_to_array", since = "1.59.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom<&mut [T]> for [T; N] +const impl TryFrom<&mut [T]> for [T; N] where T: Copy, { @@ -300,7 +301,7 @@ where /// ``` #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a, T, const N: usize> const TryFrom<&'a [T]> for &'a [T; N] { +const impl<'a, T, const N: usize> TryFrom<&'a [T]> for &'a [T; N] { type Error = TryFromSliceError; #[inline] @@ -323,7 +324,7 @@ impl<'a, T, const N: usize> const TryFrom<&'a [T]> for &'a [T; N] { /// ``` #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a, T, const N: usize> const TryFrom<&'a mut [T]> for &'a mut [T; N] { +const impl<'a, T, const N: usize> TryFrom<&'a mut [T]> for &'a mut [T; N] { type Error = TryFromSliceError; #[inline] @@ -379,7 +380,7 @@ impl<'a, T, const N: usize> IntoIterator for &'a mut [T; N] { #[stable(feature = "index_trait_on_arrays", since = "1.50.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const Index for [T; N] +const impl Index for [T; N] where [T]: [const] Index, { @@ -393,7 +394,7 @@ where #[stable(feature = "index_trait_on_arrays", since = "1.50.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const IndexMut for [T; N] +const impl IndexMut for [T; N] where [T]: [const] IndexMut, { @@ -406,7 +407,7 @@ where /// Implements comparison of arrays [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for [T; N] { +const impl PartialOrd for [T; N] { #[inline] fn partial_cmp(&self, other: &[T; N]) -> Option { PartialOrd::partial_cmp(&&self[..], &&other[..]) @@ -432,7 +433,7 @@ impl const PartialOrd for [T; N] { /// Implements comparison of arrays [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for [T; N] { +const impl Ord for [T; N] { #[inline] fn cmp(&self, other: &[T; N]) -> Ordering { Ord::cmp(&&self[..], &&other[..]) @@ -466,7 +467,15 @@ trait SpecArrayClone: Clone { impl SpecArrayClone for T { #[inline] default fn clone(array: &[T; N]) -> [T; N] { - from_trusted_iterator(array.iter().cloned()) + let mut ptr: *const T = array.as_ptr(); + // SAFETY: Unless a panic occurs, from_fn will call the closure N times, + // so our pointer arithmetic will be in bounds for the N-element array. + // This works even for ZSTs, since in that case, add() is a no-op. + from_fn(move |_| unsafe { + let old = ptr; + ptr = ptr.add(1); + (&*old).clone() + }) } } @@ -879,39 +888,6 @@ impl [T; N] { } } -/// Populate an array from the first `N` elements of `iter` -/// -/// # Panics -/// -/// If the iterator doesn't actually have enough items. -/// -/// By depending on `TrustedLen`, however, we can do that check up-front (where -/// it easily optimizes away) so it doesn't impact the loop that fills the array. -#[inline] -fn from_trusted_iterator(iter: impl UncheckedIterator) -> [T; N] { - try_from_trusted_iterator(iter.map(NeverShortCircuit)).0 -} - -#[inline] -fn try_from_trusted_iterator( - iter: impl UncheckedIterator, -) -> ChangeOutputType -where - R: Try, - R::Residual: Residual<[T; N]>, -{ - assert!(iter.size_hint().0 >= N); - fn next(mut iter: impl UncheckedIterator) -> impl FnMut(usize) -> T { - move |_| { - // SAFETY: We know that `from_fn` will call this at most N times, - // and we checked to ensure that we have at least that many items. - unsafe { iter.next_unchecked() } - } - } - - try_from_fn(next(iter)) -} - /// Version of [`try_from_fn`] using a passed-in slice in order to avoid /// needing to monomorphize for every array length. /// @@ -982,7 +958,7 @@ impl Guard<'_, T> { } #[rustc_const_unstable(feature = "array_try_from_fn", issue = "89379")] -impl const Drop for Guard<'_, T> { +const impl Drop for Guard<'_, T> { #[inline] fn drop(&mut self) { debug_assert!(self.initialized <= self.array_mut.len()); @@ -1005,33 +981,82 @@ impl const Drop for Guard<'_, T> { /// dropped. /// /// Used for [`Iterator::next_chunk`]. +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] #[inline] -pub(crate) fn iter_next_chunk( - iter: &mut impl Iterator, +pub(crate) const fn iter_next_chunk( + iter: &mut impl [const] Iterator, ) -> Result<[T; N], IntoIter> { - let mut array = [const { MaybeUninit::uninit() }; N]; - let r = iter_next_chunk_erased(&mut array, iter); - match r { - Ok(()) => { - // SAFETY: All elements of `array` were populated. - Ok(unsafe { MaybeUninit::array_assume_init(array) }) + iter.spec_next_chunk() +} + +pub(crate) const trait SpecNextChunk: Iterator { + fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter>; +} +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl, T, const N: usize> SpecNextChunk for I { + #[inline] + default fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter> { + let mut array = [const { MaybeUninit::uninit() }; N]; + let r = iter_next_chunk_erased(&mut array, self); + match r { + Ok(()) => { + // SAFETY: All elements of `array` were populated. + Ok(unsafe { MaybeUninit::array_assume_init(array) }) + } + Err(initialized) => { + // SAFETY: Only the first `initialized` elements were populated + Err(unsafe { IntoIter::new_unchecked(array, 0..initialized) }) + } } - Err(initialized) => { - // SAFETY: Only the first `initialized` elements were populated - Err(unsafe { IntoIter::new_unchecked(array, 0..initialized) }) + } +} +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl + TrustedLen, T, const N: usize> SpecNextChunk + for I +{ + fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter> { + let len = (*self).size_hint().0; + let mut array = [const { MaybeUninit::uninit() }; N]; + if len < N { + // SAFETY: `TrustedLen`, an unsafe trait, requires that i can get len items out of it. + unsafe { write(&mut array, self, len) }; + // SAFETY: Only the first `len` elements were populated + Err(unsafe { IntoIter::new_unchecked(array, 0..len) }) + } else { + // SAFETY: `TrustedLen`, an unsafe trait, requires that i can get N items out of it. + unsafe { write(&mut array, self, N) }; + // SAFETY: All N items were populated + Ok(unsafe { MaybeUninit::array_assume_init(array) }) } } } +// SAFETY: `from` must have len items, and len items must be < N. +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const unsafe fn write( + to: &mut [MaybeUninit; N], + from: &mut impl [const] Iterator, + len: usize, +) { + let mut guard = Guard { array_mut: to, initialized: 0 }; + while guard.initialized < len { + // SAFETY: caller has guaranteed, from has len items. + let item = unsafe { from.next().unwrap_unchecked() }; + // SAFETY: guard.initialized < len < N + unsafe { guard.push_unchecked(item) }; + } + crate::mem::forget(guard); +} /// Version of [`iter_next_chunk`] using a passed-in slice in order to avoid /// needing to monomorphize for every array length. /// /// Unfortunately this loop has two exit conditions, the buffer filling up /// or the iterator running out of items, making it tend to optimize poorly. +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] #[inline] -fn iter_next_chunk_erased( +const fn iter_next_chunk_erased( buffer: &mut [MaybeUninit], - iter: &mut impl Iterator, + iter: &mut impl [const] Iterator, ) -> Result<(), usize> { // if `Iterator::next` panics, this guard will drop already initialized items let mut guard = Guard { array_mut: buffer, initialized: 0 }; diff --git a/core/src/ascii/ascii_char.rs b/core/src/ascii/ascii_char.rs index ec3e551056fee..a957005972a20 100644 --- a/core/src/ascii/ascii_char.rs +++ b/core/src/ascii/ascii_char.rs @@ -949,7 +949,8 @@ impl AsciiChar { self.to_u8().is_ascii_hexdigit() } - /// Checks if the value is a punctuation character: + /// Checks if the value is a punctuation or symbol character + /// (i.e. not alphanumeric, whitespace, or control): /// /// - 0x21 ..= 0x2F `! " # $ % & ' ( ) * + , - . /`, or /// - 0x3A ..= 0x40 `: ; < = > ? @`, or @@ -989,7 +990,8 @@ impl AsciiChar { self.to_u8().is_ascii_punctuation() } - /// Checks if the value is a graphic character: + /// Checks if the value is a graphic character + /// (i.e. not whitespace or control): /// 0x21 '!' ..= 0x7E '~'. /// /// # Examples diff --git a/core/src/autodiff.md b/core/src/autodiff.md new file mode 100644 index 0000000000000..847ed8b3ef324 --- /dev/null +++ b/core/src/autodiff.md @@ -0,0 +1,157 @@ +This module provides support for automatic differentiation. For precise information on +differences between the `autodiff_forward` and `autodiff_reverse` macros and how to +use them, see their respective documentation. + +## General usage + +Autodiff macros can be applied to almost all function definitions, see below for examples. +They can be applied to functions accepting structs, arrays, slices, vectors, tuples, and more. + +It is possible to apply multiple autodiff macros to the same function. As an example, this can +be helpful to compute the partial derivatives with respect to `x` and `y` independently: +```rust,ignore (optional component) +#[autodiff_forward(dsquare1, Dual, Const, Dual)] +#[autodiff_forward(dsquare2, Const, Dual, Dual)] +#[autodiff_forward(dsquare3, Active, Active, Active)] +fn square(x: f64, y: f64) -> f64 { + x * x + 2.0 * y +} +``` + +We also support autodiff on functions with generic parameters: +```rust,ignore (optional component) +#[autodiff_forward(generic_derivative, Duplicated, Active)] +fn generic_f + Copy>(x: &T) -> T { + x * x +} +``` + +or applying autodiff to nested functions: +```rust,ignore (optional component) +fn outer(x: f64) -> f64 { + #[autodiff_forward(inner_derivative, Dual, Const)] + fn inner(y: f64) -> f64 { + y * y + } + inner_derivative(x, 1.0) +} + +fn main() { + assert_eq!(outer(3.14), 6.28); +} +``` +The generated function will be available in the same scope as the function differentiated, and +have the same private/pub usability. + +## Traits and impls +Autodiff macros can be used in multiple ways in combination with traits: +```rust,ignore (optional component) +struct Foo { + a: f64, +} + +trait MyTrait { + #[autodiff_reverse(df, Const, Active, Active)] + fn f(&self, x: f64) -> f64; +} + +impl MyTrait for Foo { + fn f(&self, x: f64) -> f64 { + x.sin() + } +} + +fn main() { + let foo = Foo { a: 3.0f64 }; + assert_eq!(foo.f(2.0), 2.0_f64.sin()); + assert_eq!(foo.df(2.0, 1.0).1, 2.0_f64.cos()); +} +``` +In this case `df` will be the default implementation provided by the library who provided the +trait. A user implementing `MyTrait` could then decide to use the default implementation of +`df`, or overwrite it with a custom implementation as a form of "custom derivatives". + +On the other hand, a function generated by either autodiff macro can also be used to implement a +trait: +```rust,ignore (optional component) +struct Foo { + a: f64, +} + +trait MyTrait { + fn f(&self, x: f64) -> f64; + fn df(&self, x: f64, seed: f64) -> (f64, f64); +} + +impl MyTrait for Foo { + #[autodiff_reverse(df, Const, Active, Active)] + fn f(&self, x: f64) -> f64 { + self.a * 0.25 * (x * x - 1.0 - 2.0 * x.ln()) + } +} +``` + +Simple `impl` blocks without traits are also supported. Differentiating with respect to the +implemented struct will then require the use of a "shadow struct" to hold the derivatives of the +struct fields: + +```rust,ignore (optional component) +struct OptProblem { + a: f64, + b: f64, +} + +impl OptProblem { + #[autodiff_reverse(d_objective, Duplicated, Duplicated, Duplicated)] + fn objective(&self, x: &[f64], out: &mut f64) { + *out = self.a + x[0].sqrt() * self.b + } +} +fn main() { + let p = OptProblem { a: 1., b: 2. }; + let mut p_shadow = OptProblem { a: 0., b: 0. }; + let mut dx = [0.0]; + let mut out = 0.0; + let mut dout = 1.0; + + p.d_objective(&mut p_shadow, &x, &mut dx, &mut out, &mut dout); +} +``` + +## Higher-order derivatives +Finally, it is possible to generate higher-order derivatives (e.g. Hessian) by applying an +autodiff macro to a function that is already generated by an autodiff macro, via a thin wrapper. +The following example uses Forward mode over Reverse mode + +```rust,ignore (optional component) +#[autodiff_reverse(df, Duplicated, Duplicated)] +fn f(x: &[f64;2], y: &mut f64) { + *y = x[0] * x[0] + x[1] * x[0] +} + +#[autodiff_forward(h, Dual, Dual, Dual, Dual)] +fn wrapper(x: &[f64;2], dx: &mut [f64;2], y: &mut f64, dy: &mut f64) { + df(x, dx, y, dy); +} + +fn main() { + let mut y = 0.0; + let x = [2.0, 2.0]; + + let mut dy = 0.0; + let mut dx = [1.0, 0.0]; + + let mut bx = [0.0, 0.0]; + let mut by = 1.0; + let mut dbx = [0.0, 0.0]; + let mut dby = 0.0; + h(&x, &mut dx, &mut bx, &mut dbx, &mut y, &mut dy, &mut by, &mut dby); + assert_eq!(&dbx, [2.0, 1.0]); +} +``` + +## Current limitations: + +- Differentiating a function which accepts a `dyn Trait` is currently not supported. +- Builds without `lto="fat"` are not yet supported. +- Builds in debug mode are currently more likely to fail compilation. diff --git a/core/src/bool.rs b/core/src/bool.rs index 9b9d2f02550bd..751b8d0f1b762 100644 --- a/core/src/bool.rs +++ b/core/src/bool.rs @@ -78,15 +78,11 @@ impl bool { /// # Examples /// /// ``` - /// #![feature(bool_to_result)] - /// /// assert_eq!(false.ok_or(0), Err(0)); /// assert_eq!(true.ok_or(0), Ok(())); /// ``` /// /// ``` - /// #![feature(bool_to_result)] - /// /// let mut a = 0; /// let mut function_with_side_effects = || { a += 1; }; /// @@ -97,7 +93,7 @@ impl bool { /// // evaluated eagerly. /// assert_eq!(a, 2); /// ``` - #[unstable(feature = "bool_to_result", issue = "142748")] + #[stable(feature = "bool_to_result", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_bool", issue = "151531")] #[inline] pub const fn ok_or(self, err: E) -> Result<(), E> { @@ -110,15 +106,11 @@ impl bool { /// # Examples /// /// ``` - /// #![feature(bool_to_result)] - /// /// assert_eq!(false.ok_or_else(|| 0), Err(0)); /// assert_eq!(true.ok_or_else(|| 0), Ok(())); /// ``` /// /// ``` - /// #![feature(bool_to_result)] - /// /// let mut a = 0; /// /// assert!(true.ok_or_else(|| { a += 1; }).is_ok()); @@ -128,7 +120,7 @@ impl bool { /// // `ok_or_else`. /// assert_eq!(a, 1); /// ``` - #[unstable(feature = "bool_to_result", issue = "142748")] + #[stable(feature = "bool_to_result", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_bool", issue = "151531")] #[inline] pub const fn ok_or_else E + [const] Destruct>( diff --git a/core/src/borrow.rs b/core/src/borrow.rs index eb4562bda4ce3..fe844e32c7e0f 100644 --- a/core/src/borrow.rs +++ b/core/src/borrow.rs @@ -209,7 +209,7 @@ pub const trait BorrowMut: [const] Borrow { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow for T { +const impl Borrow for T { #[rustc_diagnostic_item = "noop_method_borrow"] fn borrow(&self) -> &T { self @@ -218,7 +218,7 @@ impl const Borrow for T { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const BorrowMut for T { +const impl BorrowMut for T { fn borrow_mut(&mut self) -> &mut T { self } @@ -226,7 +226,7 @@ impl const BorrowMut for T { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow for &T { +const impl Borrow for &T { fn borrow(&self) -> &T { self } @@ -234,7 +234,7 @@ impl const Borrow for &T { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow for &mut T { +const impl Borrow for &mut T { fn borrow(&self) -> &T { self } @@ -242,7 +242,7 @@ impl const Borrow for &mut T { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const BorrowMut for &mut T { +const impl BorrowMut for &mut T { fn borrow_mut(&mut self) -> &mut T { self } diff --git a/core/src/bstr/mod.rs b/core/src/bstr/mod.rs index 9d623d3af8b5d..26a7f9c93b8c7 100644 --- a/core/src/bstr/mod.rs +++ b/core/src/bstr/mod.rs @@ -131,7 +131,7 @@ impl ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for ByteStr { +const impl Deref for ByteStr { type Target = [u8]; #[inline] @@ -142,7 +142,7 @@ impl const Deref for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for ByteStr { +const impl DerefMut for ByteStr { #[inline] fn deref_mut(&mut self) -> &mut [u8] { &mut self.0 @@ -258,7 +258,7 @@ impl fmt::Display for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef<[u8]> for ByteStr { +const impl AsRef<[u8]> for ByteStr { #[inline] fn as_ref(&self) -> &[u8] { &self.0 @@ -267,7 +267,7 @@ impl const AsRef<[u8]> for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for ByteStr { +const impl AsRef for ByteStr { #[inline] fn as_ref(&self) -> &ByteStr { self @@ -278,7 +278,7 @@ impl const AsRef for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for str { +const impl AsRef for str { #[inline] fn as_ref(&self) -> &ByteStr { ByteStr::new(self) @@ -287,7 +287,7 @@ impl const AsRef for str { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut<[u8]> for ByteStr { +const impl AsMut<[u8]> for ByteStr { #[inline] fn as_mut(&mut self) -> &mut [u8] { &mut self.0 @@ -302,7 +302,7 @@ impl const AsMut<[u8]> for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Borrow<[u8]> for ByteStr { +const impl Borrow<[u8]> for ByteStr { #[inline] fn borrow(&self) -> &[u8] { &self.0 @@ -313,7 +313,7 @@ impl const Borrow<[u8]> for ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const BorrowMut<[u8]> for ByteStr { +const impl BorrowMut<[u8]> for ByteStr { #[inline] fn borrow_mut(&mut self) -> &mut [u8] { &mut self.0 @@ -382,7 +382,7 @@ impl<'a> Default for &'a mut ByteStr { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a> const TryFrom<&'a ByteStr> for &'a str { +const impl<'a> TryFrom<&'a ByteStr> for &'a str { type Error = crate::str::Utf8Error; #[inline] @@ -393,7 +393,7 @@ impl<'a> const TryFrom<&'a ByteStr> for &'a str { #[unstable(feature = "bstr", issue = "134915")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a> const TryFrom<&'a mut ByteStr> for &'a mut str { +const impl<'a> TryFrom<&'a mut ByteStr> for &'a mut str { type Error = crate::str::Utf8Error; #[inline] diff --git a/core/src/cell.rs b/core/src/cell.rs index d67693f9d0fc3..1c79cf6bfcb36 100644 --- a/core/src/cell.rs +++ b/core/src/cell.rs @@ -334,7 +334,7 @@ impl Clone for Cell { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Cell { +const impl Default for Cell { /// Creates a `Cell`, with the `Default` value for T. #[inline] fn default() -> Cell { @@ -391,7 +391,7 @@ impl Ord for Cell { #[stable(feature = "cell_from", since = "1.12.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Cell { +const impl From for Cell { /// Creates a new `Cell` containing the given value. fn from(t: T) -> Cell { Cell::new(t) @@ -1461,7 +1461,7 @@ impl Clone for RefCell { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for RefCell { +const impl Default for RefCell { /// Creates a `RefCell`, with the `Default` value for T. #[inline] fn default() -> RefCell { @@ -1539,7 +1539,7 @@ impl Ord for RefCell { #[stable(feature = "cell_from", since = "1.12.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for RefCell { +const impl From for RefCell { /// Creates a new `RefCell` containing the given value. fn from(t: T) -> RefCell { RefCell::new(t) @@ -1579,7 +1579,7 @@ impl<'b> BorrowRef<'b> { } #[rustc_const_unstable(feature = "const_ref_cell", issue = "137844")] -impl const Drop for BorrowRef<'_> { +const impl Drop for BorrowRef<'_> { #[inline] fn drop(&mut self) { let borrow = self.borrow.get(); @@ -1589,7 +1589,7 @@ impl const Drop for BorrowRef<'_> { } #[rustc_const_unstable(feature = "const_ref_cell", issue = "137844")] -impl const Clone for BorrowRef<'_> { +const impl Clone for BorrowRef<'_> { #[inline] fn clone(&self) -> Self { // Since this Ref exists, we know the borrow flag @@ -1621,7 +1621,7 @@ pub struct Ref<'b, T: ?Sized + 'b> { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for Ref<'_, T> { +const impl Deref for Ref<'_, T> { type Target = T; #[inline] @@ -2047,7 +2047,7 @@ struct BorrowRefMut<'b> { } #[rustc_const_unstable(feature = "const_ref_cell", issue = "137844")] -impl const Drop for BorrowRefMut<'_> { +const impl Drop for BorrowRefMut<'_> { #[inline] fn drop(&mut self) { let borrow = self.borrow.get(); @@ -2105,7 +2105,7 @@ pub struct RefMut<'b, T: ?Sized + 'b> { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for RefMut<'_, T> { +const impl Deref for RefMut<'_, T> { type Target = T; #[inline] @@ -2117,7 +2117,7 @@ impl const Deref for RefMut<'_, T> { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for RefMut<'_, T> { +const impl DerefMut for RefMut<'_, T> { #[inline] fn deref_mut(&mut self) -> &mut T { // SAFETY: the value is accessible as long as we hold our borrow. @@ -2567,7 +2567,7 @@ impl UnsafeCell { #[stable(feature = "unsafe_cell_default", since = "1.10.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for UnsafeCell { +const impl Default for UnsafeCell { /// Creates an `UnsafeCell`, with the `Default` value for T. fn default() -> UnsafeCell { UnsafeCell::new(Default::default()) @@ -2576,7 +2576,7 @@ impl const Default for UnsafeCell { #[stable(feature = "cell_from", since = "1.12.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for UnsafeCell { +const impl From for UnsafeCell { /// Creates a new `UnsafeCell` containing the given value. fn from(t: T) -> UnsafeCell { UnsafeCell::new(t) @@ -2674,7 +2674,7 @@ impl SyncUnsafeCell { #[unstable(feature = "sync_unsafe_cell", issue = "95439")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for SyncUnsafeCell { +const impl Default for SyncUnsafeCell { /// Creates an `SyncUnsafeCell`, with the `Default` value for T. fn default() -> SyncUnsafeCell { SyncUnsafeCell::new(Default::default()) @@ -2683,7 +2683,7 @@ impl const Default for SyncUnsafeCell { #[unstable(feature = "sync_unsafe_cell", issue = "95439")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for SyncUnsafeCell { +const impl From for SyncUnsafeCell { /// Creates a new `SyncUnsafeCell` containing the given value. fn from(t: T) -> SyncUnsafeCell { SyncUnsafeCell::new(t) diff --git a/core/src/cell/lazy.rs b/core/src/cell/lazy.rs index ae559e599f481..ba32fff2284fd 100644 --- a/core/src/cell/lazy.rs +++ b/core/src/cell/lazy.rs @@ -346,7 +346,8 @@ impl T> DerefMut for LazyCell { } #[stable(feature = "lazy_cell", since = "1.80.0")] -impl Default for LazyCell { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for LazyCell { /// Creates a new lazy value using `Default` as the initializing function. #[inline] fn default() -> LazyCell { @@ -366,7 +367,7 @@ impl fmt::Debug for LazyCell { } } -#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] impl From for LazyCell { /// Constructs a `LazyCell` that starts already initialized /// with the provided value. diff --git a/core/src/cell/once.rs b/core/src/cell/once.rs index af4469fad2cc6..799e19cce67e6 100644 --- a/core/src/cell/once.rs +++ b/core/src/cell/once.rs @@ -354,7 +354,7 @@ impl OnceCell { #[stable(feature = "once_cell", since = "1.70.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for OnceCell { +const impl Default for OnceCell { #[inline] fn default() -> Self { Self::new() @@ -397,7 +397,7 @@ impl Eq for OnceCell {} #[stable(feature = "once_cell", since = "1.70.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for OnceCell { +const impl From for OnceCell { /// Creates a new `OnceCell` which already contains the given `value`. #[inline] fn from(value: T) -> Self { diff --git a/core/src/char/convert.rs b/core/src/char/convert.rs index 90c09d43f14f5..a60fc68c22990 100644 --- a/core/src/char/convert.rs +++ b/core/src/char/convert.rs @@ -37,7 +37,7 @@ pub(super) const unsafe fn from_u32_unchecked(i: u32) -> char { #[stable(feature = "char_convert", since = "1.13.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u32 { +const impl From for u32 { /// Converts a [`char`] into a [`u32`]. /// /// # Examples @@ -56,7 +56,7 @@ impl const From for u32 { #[stable(feature = "more_char_conversions", since = "1.51.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u64 { +const impl From for u64 { /// Converts a [`char`] into a [`u64`]. /// /// # Examples @@ -77,7 +77,7 @@ impl const From for u64 { #[stable(feature = "more_char_conversions", since = "1.51.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u128 { +const impl From for u128 { /// Converts a [`char`] into a [`u128`]. /// /// # Examples @@ -102,7 +102,7 @@ impl const From for u128 { /// See [`impl From for char`](char#impl-From-for-char) for details on the encoding. #[stable(feature = "u8_from_char", since = "1.59.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for u8 { +const impl TryFrom for u8 { type Error = TryFromCharError; /// Tries to convert a [`char`] into a [`u8`]. @@ -132,7 +132,7 @@ impl const TryFrom for u8 { /// This corresponds to the UCS-2 encoding, as specified in ISO/IEC 10646:2003. #[stable(feature = "u16_from_char", since = "1.74.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for u16 { +const impl TryFrom for u16 { type Error = TryFromCharError; /// Tries to convert a [`char`] into a [`u16`]. @@ -164,7 +164,7 @@ impl const TryFrom for u16 { /// UTF-32 code point to the extent representable by pointer addresses. #[stable(feature = "usize_try_from_char", since = "1.94.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for usize { +const impl TryFrom for usize { type Error = TryFromCharError; /// Tries to convert a [`char`] into a [`usize`]. @@ -214,7 +214,7 @@ impl const TryFrom for usize { /// C0 and C1 control codes. #[stable(feature = "char_convert", since = "1.13.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for char { +const impl From for char { /// Converts a [`u8`] into a [`char`]. /// /// # Examples @@ -300,7 +300,7 @@ const fn char_try_from_u32(i: u32) -> Result { #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for char { +const impl TryFrom for char { type Error = CharTryFromError; #[inline] diff --git a/core/src/char/methods.rs b/core/src/char/methods.rs index 46d48afbf5a14..d8b7fe44e453a 100644 --- a/core/src/char/methods.rs +++ b/core/src/char/methods.rs @@ -810,7 +810,7 @@ impl char { match self { 'a'..='z' | 'A'..='Z' => true, '\0'..='\u{A9}' => false, - _ => unicode::Cased(self), + _ => unicode::Lowercase(self) || unicode::Uppercase(self) || unicode::Lt(self), } } @@ -840,10 +840,10 @@ impl char { 'a'..='z' => Some(CharCase::Lower), 'A'..='Z' => Some(CharCase::Upper), '\0'..='\u{A9}' => None, - _ if !unicode::Cased(self) => None, _ if unicode::Lowercase(self) => Some(CharCase::Lower), _ if unicode::Uppercase(self) => Some(CharCase::Upper), - _ => Some(CharCase::Title), + _ if unicode::Lt(self) => Some(CharCase::Title), + _ => None, } } @@ -919,7 +919,7 @@ impl char { pub fn is_titlecase(self) -> bool { match self { '\0'..='\u{01C4}' => false, - _ => self.is_cased() && !self.is_lowercase() && !self.is_uppercase(), + _ => unicode::Lt(self), } } @@ -1050,8 +1050,9 @@ impl char { /// ``` #[must_use] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_stable(feature = "const_is_control", since = "1.97.0")] #[inline] - pub fn is_control(self) -> bool { + pub const fn is_control(self) -> bool { // According to // https://www.unicode.org/policies/stability_policy.html#Property_Value, // the set of codepoints in `Cc` will never change. @@ -1074,18 +1075,20 @@ impl char { self > '\u{02FF}' && unicode::Grapheme_Extend(self) } - /// Returns `true` if this `char` has the `Case_Ignorable` property. + /// Returns `true` if this `char` has the `Case_Ignorable` property. This narrow-use property + /// is used to implement context-dependent casing for the Greek letter sigma (uppercase Σ), + /// which has two lowercase forms. /// - /// `Case_Ignorable` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and - /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]. + /// `Case_Ignorable` is [described][D136] in Chapter 3 (Conformance) of the Unicode Core Specification, + /// and specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]; + /// see those resources for more information. /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ + /// [D136]: https://www.unicode.org/versions/latest/core-spec/chapter-3/#G63116 /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt #[must_use] #[inline] - #[doc(hidden)] - #[unstable(feature = "char_internals", reason = "exposed only for libstd", issue = "none")] + #[unstable(feature = "case_ignorable", issue = "154848")] pub fn is_case_ignorable(self) -> bool { if self.is_ascii() { matches!(self, '\'' | '.' | ':' | '^' | '`') @@ -1149,13 +1152,14 @@ impl char { /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields - /// the `char`(s) given by [`SpecialCasing.txt`]. + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. /// /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt /// /// This operation performs an unconditional mapping without tailoring. That is, the conversion - /// is independent of context and language. + /// is independent of context and language. See [below](#notes-on-context-and-locale) + /// for more information. /// /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. @@ -1197,6 +1201,48 @@ impl char { /// // convert into themselves. /// assert_eq!('山'.to_lowercase().to_string(), "山"); /// ``` + /// # Notes on context and locale + /// + /// As stated earlier, this method does not take into account language or context. + /// Below is a non-exhaustive list of situations where this can be relevant. + /// If you need to handle locale-depedendent casing in your code, consider using + /// an external crate, like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. + /// + /// ## Greek sigma + /// + /// In Greek, the letter simga (uppercase Σ) has two lowercase forms: + /// ς which is used only at the end of a word, and σ which is used everywhere else. + /// `to_lowercase()` always uses the second form: + /// + /// ``` + /// assert_eq!('Σ'.to_lowercase().to_string(), "σ"); + /// ``` + /// + /// ## Turkish and Azeri I/ı/İ/i + /// + /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: + /// + /// * 'Dotless': I / ı, sometimes written ï + /// * 'Dotted': İ / i + /// + /// Note that the uppercase undotted 'I' is the same as the Latin. Therefore: + /// + /// ``` + /// let lower_i = 'I'.to_lowercase().to_string(); + /// ``` + /// + /// The value of `lower_i` here relies on the language of the text: if we're + /// in `en-US`, it should be `"i"`, but if we're in `tr-TR` or `az-AZ`, it should + /// be `"ı"`. `to_lowercase()` does not take this into account, and so: + /// + /// ``` + /// let lower_i = 'I'.to_lowercase().to_string(); + /// + /// assert_eq!(lower_i, "i"); + /// ``` + /// + /// holds across languages. #[must_use = "this returns the lowercased character as a new iterator, \ without modifying the original"] #[stable(feature = "rust1", since = "1.0.0")] @@ -1209,8 +1255,10 @@ impl char { /// `char`s. /// /// This is usually, but not always, equivalent to the uppercase mapping - /// returned by [`Self::to_uppercase`]. Prefer this method when seeking to capitalize - /// Only The First Letter of a word, but use [`Self::to_uppercase`] for ALL CAPS. + /// returned by [`to_uppercase()`]. Prefer this method when seeking to capitalize + /// Only The First Letter of a word, but use [`to_uppercase()`] for ALL CAPS. + /// See [below](#difference-from-uppercase) for a thorough explanation + /// of the difference between the two methods. /// /// If this `char` does not have a titlecase mapping, the iterator yields the same `char`. /// @@ -1220,13 +1268,14 @@ impl char { /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields - /// the `char`(s) given by [`SpecialCasing.txt`]. + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. /// /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt /// /// This operation performs an unconditional mapping without tailoring. That is, the conversion - /// is independent of context and language. + /// is independent of context and language. See [below](#note-on-locale) + /// for more information. /// /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. @@ -1263,8 +1312,9 @@ impl char { /// ``` /// #![feature(titlecase)] /// assert_eq!('c'.to_titlecase().to_string(), "C"); + /// assert_eq!('ა'.to_titlecase().to_string(), "ა"); /// assert_eq!('dž'.to_titlecase().to_string(), "Dž"); - /// assert_eq!('ῼ'.to_titlecase().to_string(), "ῼ"); + /// assert_eq!('ᾨ'.to_titlecase().to_string(), "ᾨ"); /// /// // Sometimes the result is more than one character: /// assert_eq!('ß'.to_titlecase().to_string(), "Ss"); @@ -1274,8 +1324,78 @@ impl char { /// assert_eq!('山'.to_titlecase().to_string(), "山"); /// ``` /// + /// # Difference from uppercase + /// + /// Currently, there are three classes of characters where [`to_uppercase()`] + /// and `to_titlecase()` give different results: + /// + /// ## Georgian script + /// + /// Each letter in the modern Georgian alphabet can be written in one of two forms: + /// the typical lowercase-like "mkhedruli" form, and a variant uppercase-like "mtavruli" + /// form. However, unlike uppercase in most cased scripts, mtavruli is not typically used + /// to start sentences, denote proper nouns, or for any other purpose + /// in running text. It is instead confined to titles and headings, which are written entirely + /// in mtavruli. For this reason, [`to_uppercase()`] applied to a Georgian letter + /// will return the mtavruli form, but `to_titlecase()` will return the mkhedruli form. + /// + /// ``` + /// #![feature(titlecase)] + /// let ani = 'ა'; // First letter of the Georgian alphabet, in mkhedruli form + /// + /// // Titlecasing mkhedruli maps it to itself... + /// assert_eq!(ani.to_titlecase().to_string(), ani.to_string()); + /// + /// // but uppercasing it maps it to mtavruli + /// assert_eq!(ani.to_uppercase().to_string(), "Ა"); + /// ``` + /// + /// ## Compatibility digraphs for Latin-alphabet Serbo-Croatian + /// + /// The standard Latin alphabet for the Serbo-Croatian language + /// (Bosnian, Croatian, Montenegrin, and Serbian) contains + /// three digraphs: Dž, Lj, and Nj. These are usually represented as + /// two characters. However, for compatibility with older character sets, + /// Unicode includes single-character versions of these digraphs. + /// Each has a uppercase, titlecase, and lowercase version: + /// + /// - `'DŽ'`, `'Dž'`, `'dž'` + /// - `'LJ'`, `'Lj'`, `'lj'` + /// - `'NJ'`, `'Nj'`, `'nj'` + /// + /// Unicode additionally encodes a casing triad for the Dz digraph + /// without the caron: `'DZ'`, `'Dz'`, `'dz'`. + /// + /// ## Iota-subscritped Greek vowels + /// + /// In ancient Greek, the long vowels alpha (α), eta (η), and omega (ω) + /// were sometimes followed by an iota (ι), forming a diphthong. Over time, + /// the diphthong pronunciation was slowly lost, with the iota becoming mute. + /// Eventually, the ι disappeared from the spelling as well. + /// However, there remains a need to represent ancient texts faithfully. + /// + /// Modern editions of ancient Greek texts commonly use a reduced-sized + /// ι symbol to denote mute iotas, while distinguishing them from ιs + /// which continued to affect pronunciation. The exact standard differs + /// between different publications. Some render the mute ι below its associated + /// vowel (subscript), while others place it to the right of said vowel (adscript). + /// The interaction of mute ι symbols with casing also varies. + /// + /// The Unicode Standard, for its default casing rules, chose to make lowercase + /// Greek vowels with iota subscipt (e.g. `'ᾠ'`) titlecase to the uppercase vowel + /// with iota subscript (`'ᾨ'`) but uppercase to the uppercase vowel followed by + /// full-size uppercase iota (`"ὨΙ"`). This is just one convention among many + /// in common use, but it is the one Unicode settled on, + /// so it is what this method does also. + /// /// # Note on locale /// + /// As stated above, this method is locale-insensitive. + /// If you need locale support, consider using an external crate, + /// like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. A description of a common + /// locale-dependent casing issue follows: + /// /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: /// /// * 'Dotless': I / ı, sometimes written ï @@ -1300,6 +1420,8 @@ impl char { /// ``` /// /// holds across languages. + /// + /// [`to_uppercase()`]: Self::to_uppercase() #[must_use = "this returns the titlecased character as a new iterator, \ without modifying the original"] #[unstable(feature = "titlecase", issue = "153892")] @@ -1311,8 +1433,9 @@ impl char { /// Returns an iterator that yields the uppercase mapping of this `char` as one or more /// `char`s. /// - /// Prefer this method when converting a word into ALL CAPS, but consider [`Self::to_titlecase`] - /// instead if you seek to capitalize Only The First Letter. + /// Prefer this method when converting a word into ALL CAPS, but consider [`to_titlecase()`] + /// instead if you seek to capitalize Only The First Letter. See that method's documentation + /// for more information on the difference between the two. /// /// If this `char` does not have an uppercase mapping, the iterator yields the same `char`. /// @@ -1322,13 +1445,14 @@ impl char { /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields - /// the `char`(s) given by [`SpecialCasing.txt`]. + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. /// /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt /// /// This operation performs an unconditional mapping without tailoring. That is, the conversion - /// is independent of context and language. + /// is independent of context and language. See [below](#note-on-locale) + /// for more information. /// /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. @@ -1336,6 +1460,7 @@ impl char { /// [Unicode Standard]: https://www.unicode.org/versions/latest/ /// /// # Examples + /// /// `'ſt'` (U+FB05) is a single Unicode code point (a ligature) that maps to "ST" in uppercase. /// /// As an iterator: @@ -1363,11 +1488,12 @@ impl char { /// /// ``` /// assert_eq!('c'.to_uppercase().to_string(), "C"); + /// assert_eq!('ა'.to_uppercase().to_string(), "Ა"); /// assert_eq!('dž'.to_uppercase().to_string(), "DŽ"); /// /// // Sometimes the result is more than one character: /// assert_eq!('ſt'.to_uppercase().to_string(), "ST"); - /// assert_eq!('ῼ'.to_uppercase().to_string(), "ΩΙ"); + /// assert_eq!('ᾨ'.to_uppercase().to_string(), "ὨΙ"); /// /// // Characters that do not have both uppercase and lowercase /// // convert into themselves. @@ -1376,6 +1502,12 @@ impl char { /// /// # Note on locale /// + /// As stated above, this method is locale-insensitive. + /// If you need locale support, consider using an external crate, + /// like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. A description of a common + /// locale-dependent casing issue follows: + /// /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: /// /// * 'Dotless': I / ı, sometimes written ï @@ -1398,6 +1530,8 @@ impl char { /// ``` /// /// holds across languages. + /// + /// [`to_titlecase()`]: Self::to_titlecase() #[must_use = "this returns the uppercased character as a new iterator, \ without modifying the original"] #[stable(feature = "rust1", since = "1.0.0")] @@ -1851,7 +1985,8 @@ impl char { matches!(*self, '0'..='9') | matches!(*self, 'A'..='F') | matches!(*self, 'a'..='f') } - /// Checks if the value is an ASCII punctuation character: + /// Checks if the value is an ASCII punctuation or symbol character + /// (i.e. not alphanumeric, whitespace, or control): /// /// - U+0021 ..= U+002F `! " # $ % & ' ( ) * + , - . /`, or /// - U+003A ..= U+0040 `: ; < = > ? @`, or @@ -1892,7 +2027,8 @@ impl char { | matches!(*self, '{'..='~') } - /// Checks if the value is an ASCII graphic character: + /// Checks if the value is an ASCII graphic character + /// (i.e. not whitespace or control): /// U+0021 '!' ..= U+007E '~'. /// /// # Examples @@ -1930,6 +2066,9 @@ impl char { /// U+0020 SPACE, U+0009 HORIZONTAL TAB, U+000A LINE FEED, /// U+000C FORM FEED, or U+000D CARRIAGE RETURN. /// + /// **Warning:** Because the list above excludes U+000B VERTICAL TAB, + /// `c.is_ascii_whitespace()` is **not** equivalent to `c.is_ascii() && c.is_whitespace()`. + /// /// Rust uses the WhatWG Infra Standard's [definition of ASCII /// whitespace][infra-aw]. There are several other definitions in /// wide use. For instance, [the POSIX locale][pct] includes diff --git a/core/src/char/mod.rs b/core/src/char/mod.rs index 3231c4193064c..2416406576204 100644 --- a/core/src/char/mod.rs +++ b/core/src/char/mod.rs @@ -93,31 +93,31 @@ const MAX_THREE_B: u32 = 0x10000; /// The highest valid code point a `char` can have, `'\u{10FFFF}'`. Use [`char::MAX`] instead. #[stable(feature = "rust1", since = "1.0.0")] +#[deprecated(since = "TBD", note = "replaced by the `MAX` associated constant on `char`")] pub const MAX: char = char::MAX; -/// The maximum number of bytes required to [encode](char::encode_utf8) a `char` to -/// UTF-8 encoding. -#[unstable(feature = "char_max_len", issue = "121714")] -pub const MAX_LEN_UTF8: usize = char::MAX_LEN_UTF8; - -/// The maximum number of two-byte units required to [encode](char::encode_utf16) a `char` -/// to UTF-16 encoding. -#[unstable(feature = "char_max_len", issue = "121714")] -pub const MAX_LEN_UTF16: usize = char::MAX_LEN_UTF16; - /// `U+FFFD REPLACEMENT CHARACTER` (�) is used in Unicode to represent a /// decoding error. Use [`char::REPLACEMENT_CHARACTER`] instead. #[stable(feature = "decode_utf16", since = "1.9.0")] +#[deprecated( + since = "TBD", + note = "replaced by the `REPLACEMENT_CHARACTER` associated constant on `char`" +)] pub const REPLACEMENT_CHARACTER: char = char::REPLACEMENT_CHARACTER; /// The version of [Unicode](https://www.unicode.org/) that the Unicode parts of /// `char` and `str` methods are based on. Use [`char::UNICODE_VERSION`] instead. #[stable(feature = "unicode_version", since = "1.45.0")] +#[deprecated( + since = "TBD", + note = "replaced by the `UNICODE_VERSION` associated constant on `char`" +)] pub const UNICODE_VERSION: (u8, u8, u8) = char::UNICODE_VERSION; /// Creates an iterator over the UTF-16 encoded code points in `iter`, returning /// unpaired surrogates as `Err`s. Use [`char::decode_utf16`] instead. #[stable(feature = "decode_utf16", since = "1.9.0")] +#[deprecated(since = "TBD", note = "replaced by the `decode_utf16` method on `char`")] #[inline] pub fn decode_utf16>(iter: I) -> DecodeUtf16 { self::decode::decode_utf16(iter) @@ -126,6 +126,7 @@ pub fn decode_utf16>(iter: I) -> DecodeUtf16 Option { @@ -136,6 +137,7 @@ pub const fn from_u32(i: u32) -> Option { /// instead. #[stable(feature = "char_from_unchecked", since = "1.5.0")] #[rustc_const_stable(feature = "const_char_from_u32_unchecked", since = "1.81.0")] +#[deprecated(since = "TBD", note = "replaced by the `from_u32_unchecked` method on `char`")] #[must_use] #[inline] pub const unsafe fn from_u32_unchecked(i: u32) -> char { @@ -146,6 +148,7 @@ pub const unsafe fn from_u32_unchecked(i: u32) -> char { /// Converts a digit in the given radix to a `char`. Use [`char::from_digit`] instead. #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_char_convert", since = "1.67.0")] +#[deprecated(since = "TBD", note = "replaced by the `from_digit` method on `char`")] #[must_use] #[inline] pub const fn from_digit(num: u32, radix: u32) -> Option { diff --git a/core/src/clone.rs b/core/src/clone.rs index 85b09ee06f1fd..93e774226349c 100644 --- a/core/src/clone.rs +++ b/core/src/clone.rs @@ -290,6 +290,90 @@ pub macro Clone($item:item) { /* compiler built-in */ } +/// A trait for types whose [`Clone`] operation creates another alias to the same +/// logical resource or shared state. +/// +/// `Share` marks types where cloning creates another handle, reference, or alias +/// to the same logical resource or shared state, rather than an independent owned +/// value. The distinction is semantic, not cost-based: implementing `Share` does +/// not merely mean that cloning is cheap, constant-time, allocation-free, or +/// convenient. +/// +/// Calling [`share`](Share::share) is equivalent to calling [`clone`](Clone::clone) +/// for implementors, but communicates that the resulting value aliases the same +/// underlying resource. +/// +/// Shared references, `Rc`, `Arc`, `Sender`, and `SyncSender` are +/// examples of types that can be shared this way. Types such as `Vec`, +/// `String`, and `Box` are not `Share` even though they implement `Clone`, +/// because cloning them creates another owned value rather than another handle +/// to the same logical resource. +/// +/// # Examples +/// +/// ``` +/// #![feature(share_trait)] +/// +/// use std::cell::Cell; +/// use std::clone::Share; +/// use std::rc::Rc; +/// use std::sync::{ +/// Arc, +/// atomic::{AtomicUsize, Ordering}, +/// }; +/// +/// let value = 1; +/// let reference = &value; +/// assert!(std::ptr::eq(reference, reference.share())); +/// +/// let rc = Rc::new(Cell::new(2)); +/// let shared_rc = rc.share(); +/// assert!(Rc::ptr_eq(&rc, &shared_rc)); +/// shared_rc.set(3); +/// assert_eq!(rc.get(), 3); +/// +/// let arc = Arc::new(AtomicUsize::new(4)); +/// let shared_arc = arc.share(); +/// assert!(Arc::ptr_eq(&arc, &shared_arc)); +/// shared_arc.store(5, Ordering::Relaxed); +/// assert_eq!(arc.load(Ordering::Relaxed), 5); +/// ``` +/// +/// ``` +/// #![feature(share_trait)] +/// +/// use std::clone::Share; +/// use std::sync::mpsc::{channel, sync_channel}; +/// +/// let (sender, receiver) = channel(); +/// let shared_sender = sender.share(); +/// sender.send(1).unwrap(); +/// shared_sender.send(2).unwrap(); +/// +/// let mut received = [receiver.recv().unwrap(), receiver.recv().unwrap()]; +/// received.sort(); +/// assert_eq!(received, [1, 2]); +/// +/// let (sync_sender, sync_receiver) = sync_channel(2); +/// let shared_sync_sender = sync_sender.share(); +/// sync_sender.send(3).unwrap(); +/// shared_sync_sender.send(4).unwrap(); +/// +/// let mut received = [sync_receiver.recv().unwrap(), sync_receiver.recv().unwrap()]; +/// received.sort(); +/// assert_eq!(received, [3, 4]); +/// ``` +#[unstable(feature = "share_trait", issue = "156756")] +pub trait Share: Clone { + /// Creates another alias to the same underlying resource or shared state. + /// + /// This is equivalent to calling [`Clone::clone`]. + #[unstable(feature = "share_trait", issue = "156756")] + fn share(&self) -> Self { + Clone::clone(self) + } +} + /// Trait for objects whose [`Clone`] impl is lightweight (e.g. reference-counted) /// /// Cloning an object implementing this trait should in general: @@ -601,7 +685,7 @@ unsafe impl CloneToUninit for crate::bstr::ByteStr { /// are implemented in `traits::SelectionContext::copy_clone_conditions()` /// in `rustc_trait_selection`. mod impls { - use super::TrivialClone; + use super::{Share, TrivialClone}; use crate::marker::PointeeSized; macro_rules! impl_clone { @@ -633,7 +717,7 @@ mod impls { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for ! { + const impl Clone for ! { #[inline] fn clone(&self) -> Self { *self @@ -643,11 +727,11 @@ mod impls { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for ! {} + const unsafe impl TrivialClone for ! {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for *const T { + const impl Clone for *const T { #[inline(always)] fn clone(&self) -> Self { *self @@ -657,11 +741,11 @@ mod impls { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for *const T {} + const unsafe impl TrivialClone for *const T {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for *mut T { + const impl Clone for *mut T { #[inline(always)] fn clone(&self) -> Self { *self @@ -671,23 +755,26 @@ mod impls { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for *mut T {} + const unsafe impl TrivialClone for *mut T {} /// Shared references can be cloned, but mutable references *cannot*! #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - impl const Clone for &T { + const impl Clone for &T { #[inline(always)] #[rustc_diagnostic_item = "noop_method_clone"] fn clone(&self) -> Self { - self + *self } } #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] - unsafe impl const TrivialClone for &T {} + const unsafe impl TrivialClone for &T {} + + #[unstable(feature = "share_trait", issue = "156756")] + impl Share for &T {} /// Shared references can be cloned, but mutable references *cannot*! #[stable(feature = "rust1", since = "1.0.0")] diff --git a/core/src/cmp.rs b/core/src/cmp.rs index 49d7487c2803b..b699c7a02e477 100644 --- a/core/src/cmp.rs +++ b/core/src/cmp.rs @@ -241,10 +241,9 @@ use crate::ops::ControlFlow; #[stable(feature = "rust1", since = "1.0.0")] #[doc(alias = "==")] #[doc(alias = "!=")] -#[rustc_on_unimplemented( +#[diagnostic::on_unimplemented( message = "can't compare `{Self}` with `{Rhs}`", - label = "no implementation for `{Self} == {Rhs}`", - append_const_msg + label = "no implementation for `{Self} == {Rhs}`" )] #[rustc_diagnostic_item = "PartialEq"] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] @@ -281,8 +280,9 @@ pub macro PartialEq($item:item) { /// The primary difference to [`PartialEq`] is the additional requirement for reflexivity. A type /// that implements [`PartialEq`] guarantees that for all `a`, `b` and `c`: /// -/// - symmetric: `a == b` implies `b == a` and `a != b` implies `!(a == b)` +/// - symmetric: `a == b` implies `b == a` /// - transitive: `a == b` and `b == c` implies `a == c` +/// - consistent: `a != b` if and only if `!(a == b)` /// /// `Eq`, which builds on top of [`PartialEq`] also implies: /// @@ -685,7 +685,7 @@ pub struct Reverse(#[stable(feature = "reverse_cmp_key", since = "1.19.0")] p #[stable(feature = "reverse_cmp_key", since = "1.19.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for Reverse { +const impl PartialOrd for Reverse { #[inline] fn partial_cmp(&self, other: &Reverse) -> Option { other.0.partial_cmp(&self.0) @@ -711,7 +711,7 @@ impl const PartialOrd for Reverse { #[stable(feature = "reverse_cmp_key", since = "1.19.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for Reverse { +const impl Ord for Reverse { #[inline] fn cmp(&self, other: &Reverse) -> Ordering { other.0.cmp(&self.0) @@ -1356,10 +1356,9 @@ pub macro Ord($item:item) { #[doc(alias = "<")] #[doc(alias = "<=")] #[doc(alias = ">=")] -#[rustc_on_unimplemented( +#[diagnostic::on_unimplemented( message = "can't compare `{Self}` with `{Rhs}`", - label = "no implementation for `{Self} < {Rhs}` and `{Self} > {Rhs}`", - append_const_msg + label = "no implementation for `{Self} < {Rhs}` and `{Self} > {Rhs}`" )] #[rustc_diagnostic_item = "PartialOrd"] #[allow(multiple_supertrait_upcastable)] // FIXME(sized_hierarchy): remove this @@ -1885,7 +1884,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq for () { + const impl PartialEq for () { #[inline] fn eq(&self, _other: &()) -> bool { true @@ -1971,7 +1970,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd for () { + const impl PartialOrd for () { #[inline] fn partial_cmp(&self, _: &()) -> Option { Some(Equal) @@ -1980,7 +1979,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd for bool { + const impl PartialOrd for bool { #[inline] fn partial_cmp(&self, other: &bool) -> Option { Some(self.cmp(other)) @@ -2037,7 +2036,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for () { + const impl Ord for () { #[inline] fn cmp(&self, _other: &()) -> Ordering { Equal @@ -2046,7 +2045,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for bool { + const impl Ord for bool { #[inline] fn cmp(&self, other: &bool) -> Ordering { // Casting to i8's and converting the difference to an Ordering generates @@ -2082,7 +2081,7 @@ mod impls { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq for ! { + const impl PartialEq for ! { #[inline] fn eq(&self, _: &!) -> bool { *self @@ -2091,11 +2090,11 @@ mod impls { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Eq for ! {} + const impl Eq for ! {} #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd for ! { + const impl PartialOrd for ! { #[inline] fn partial_cmp(&self, _: &!) -> Option { *self @@ -2104,7 +2103,7 @@ mod impls { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for ! { + const impl Ord for ! { #[inline] fn cmp(&self, _: &!) -> Ordering { *self @@ -2115,7 +2114,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq<&B> for &A + const impl PartialEq<&B> for &A where A: [const] PartialEq, { @@ -2130,7 +2129,7 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd<&B> for &A + const impl PartialOrd<&B> for &A where A: [const] PartialOrd, { @@ -2173,7 +2172,7 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for &A + const impl Ord for &A where A: [const] Ord, { @@ -2184,13 +2183,13 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Eq for &A where A: [const] Eq {} + const impl Eq for &A where A: [const] Eq {} // &mut pointers #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq<&mut B> for &mut A + const impl PartialEq<&mut B> for &mut A where A: [const] PartialEq, { @@ -2205,7 +2204,7 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialOrd<&mut B> for &mut A + const impl PartialOrd<&mut B> for &mut A where A: [const] PartialOrd, { @@ -2248,7 +2247,7 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Ord for &mut A + const impl Ord for &mut A where A: [const] Ord, { @@ -2259,11 +2258,11 @@ mod impls { } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const Eq for &mut A where A: [const] Eq {} + const impl Eq for &mut A where A: [const] Eq {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq<&mut B> for &A + const impl PartialEq<&mut B> for &A where A: [const] PartialEq, { @@ -2279,7 +2278,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - impl const PartialEq<&B> for &mut A + const impl PartialEq<&B> for &mut A where A: [const] PartialEq, { diff --git a/core/src/convert/mod.rs b/core/src/convert/mod.rs index ef4ab15f93c0b..34cf9c5d0a5b2 100644 --- a/core/src/convert/mod.rs +++ b/core/src/convert/mod.rs @@ -5,22 +5,21 @@ //! //! - Implement the [`AsRef`] trait for cheap reference-to-reference conversions //! - Implement the [`AsMut`] trait for cheap mutable-to-mutable conversions -//! - Implement the [`From`] trait for consuming value-to-value conversions -//! - Implement the [`Into`] trait for consuming value-to-value conversions to types -//! outside the current crate -//! - The [`TryFrom`] and [`TryInto`] traits behave like [`From`] and [`Into`], -//! but should be implemented when the conversion can fail. +//! - Implement the [`From`] trait for consuming value-to-value conversions that cannot fail. This +//! automatically provides an implementation of [`Into`] +//! - Implement the [`TryFrom`] trait for consuming value-to-value conversions that can fail. This +//! automatically provides an implementation of [`TryInto`] //! -//! The traits in this module are often used as trait bounds for generic functions such that to +//! The traits in this module are often used as trait bounds for generic functions such that //! arguments of multiple types are supported. See the documentation of each trait for examples. //! //! As a library author, you should always prefer implementing [`From`][`From`] or //! [`TryFrom`][`TryFrom`] rather than [`Into`][`Into`] or [`TryInto`][`TryInto`], //! as [`From`] and [`TryFrom`] provide greater flexibility and offer //! equivalent [`Into`] or [`TryInto`] implementations for free, thanks to a -//! blanket implementation in the standard library. When targeting a version prior to Rust 1.41, it -//! may be necessary to implement [`Into`] or [`TryInto`] directly when converting to a type -//! outside the current crate. +//! blanket implementation in the standard library. In versions of Rust prior to Rust 1.41, +//! it was sometimes necessary to implement [`Into`] or [`TryInto`] directly when converting to a +//! type outside the current crate. //! //! # Generic Implementations //! @@ -577,6 +576,7 @@ pub const trait Into: Sized { /// [`from`]: From::from /// [book]: ../../book/ch09-00-error-handling.html #[rustc_diagnostic_item = "From"] +#[lang = "From"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_on_unimplemented(on( all(Self = "&str", T = "alloc::string::String"), @@ -709,7 +709,7 @@ pub const trait TryFrom: Sized { // As lifts over & #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for &T +const impl AsRef for &T where T: [const] AsRef, { @@ -722,7 +722,7 @@ where // As lifts over &mut #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for &mut T +const impl AsRef for &mut T where T: [const] AsRef, { @@ -743,7 +743,7 @@ where // AsMut lifts over &mut #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut for &mut T +const impl AsMut for &mut T where T: [const] AsMut, { @@ -764,7 +764,7 @@ where // From implies Into #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Into for T +const impl Into for T where U: [const] From, { @@ -782,7 +782,7 @@ where // From (and thus Into) is reflexive #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for T { +const impl From for T { /// Returns the argument unchanged. #[inline(always)] fn from(t: T) -> T { @@ -799,7 +799,7 @@ impl const From for T { #[rustc_reservation_impl = "permitting this impl would forbid us from adding \ `impl From for T` later; see rust-lang/rust#64715 for details"] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for T { +const impl From for T { fn from(t: !) -> T { t } @@ -808,7 +808,7 @@ impl const From for T { // TryFrom implies TryInto #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryInto for T +const impl TryInto for T where U: [const] TryFrom, { @@ -824,7 +824,7 @@ where // with an uninhabited error type. #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for T +const impl TryFrom for T where U: [const] Into, { @@ -842,7 +842,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef<[T]> for [T] { +const impl AsRef<[T]> for [T] { #[inline(always)] fn as_ref(&self) -> &[T] { self @@ -851,7 +851,7 @@ impl const AsRef<[T]> for [T] { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut<[T]> for [T] { +const impl AsMut<[T]> for [T] { #[inline(always)] fn as_mut(&mut self) -> &mut [T] { self @@ -860,7 +860,7 @@ impl const AsMut<[T]> for [T] { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for str { +const impl AsRef for str { #[inline(always)] fn as_ref(&self) -> &str { self @@ -869,7 +869,7 @@ impl const AsRef for str { #[stable(feature = "as_mut_str_for_str", since = "1.51.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsMut for str { +const impl AsMut for str { #[inline(always)] fn as_mut(&mut self) -> &mut str { self @@ -931,7 +931,7 @@ pub enum Infallible {} #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -impl const Clone for Infallible { +const impl Clone for Infallible { fn clone(&self) -> Infallible { match *self {} } @@ -956,7 +956,7 @@ impl Error for Infallible {} #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for Infallible { +const impl PartialEq for Infallible { fn eq(&self, _: &Infallible) -> bool { match *self {} } @@ -964,11 +964,11 @@ impl const PartialEq for Infallible { #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for Infallible {} +const impl Eq for Infallible {} #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for Infallible { +const impl PartialOrd for Infallible { fn partial_cmp(&self, _other: &Self) -> Option { match *self {} } @@ -976,7 +976,7 @@ impl const PartialOrd for Infallible { #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for Infallible { +const impl Ord for Infallible { fn cmp(&self, _other: &Self) -> crate::cmp::Ordering { match *self {} } @@ -984,7 +984,7 @@ impl const Ord for Infallible { #[stable(feature = "convert_infallible", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Infallible { +const impl From for Infallible { #[inline] fn from(x: !) -> Self { x diff --git a/core/src/convert/num.rs b/core/src/convert/num.rs index b80980219b1e2..2e968e8ccc324 100644 --- a/core/src/convert/num.rs +++ b/core/src/convert/num.rs @@ -1,4 +1,4 @@ -use crate::num::TryFromIntError; +use crate::num::{IntErrorKind, TryFromIntError}; mod private { /// This trait being unreachable from outside the crate @@ -172,8 +172,14 @@ impl_from!(u32 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0 impl_from!(u64 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); // float -> float -// FIXME(f16,f128): adding additional `From<{float}>` impls to `f32` breaks inference. See -// + +// FIXME(f16): adding the additional `From<{float}>` impl to `f32` would break inference in cases +// like `f32::from(1.0)`. The type checker has a custom workaround to keep that and similar code +// compiling even with the second `From<16> for f32` instance. We keep this instance unstable for +// now so that we can later remove the workaround. +// +// See also . +impl_from!(f16 => f32, #[unstable(feature = "f32_from_f16", issue = "154005")], #[unstable_feature_bound(f32_from_f16)]); impl_from!(f16 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(f16 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(f32 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); @@ -272,7 +278,7 @@ macro_rules! impl_try_from_lower_bounded { if u >= 0 { Ok(u as Self) } else { - Err(TryFromIntError(())) + Err(TryFromIntError(IntErrorKind::NegOverflow)) } } } @@ -293,7 +299,7 @@ macro_rules! impl_try_from_upper_bounded { #[inline] fn try_from(u: $source) -> Result { if u > (Self::MAX as $source) { - Err(TryFromIntError(())) + Err(TryFromIntError(IntErrorKind::PosOverflow)) } else { Ok(u as Self) } @@ -317,8 +323,10 @@ macro_rules! impl_try_from_both_bounded { fn try_from(u: $source) -> Result { let min = Self::MIN as $source; let max = Self::MAX as $source; - if u < min || u > max { - Err(TryFromIntError(())) + if u < min { + Err(TryFromIntError(IntErrorKind::NegOverflow)) + } else if u > max { + Err(TryFromIntError(IntErrorKind::PosOverflow)) } else { Ok(u as Self) } @@ -329,8 +337,8 @@ macro_rules! impl_try_from_both_bounded { /// Implement `TryFrom` for `bool` macro_rules! impl_try_from_integer_for_bool { - ($($int:ty)+) => {$( - #[stable(feature = "try_from", since = "1.34.0")] + ($signedness:ident $($int:ty)+) => {$( + #[stable(feature = "bool_try_from_int", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const TryFrom<$int> for bool { type Error = TryFromIntError; @@ -349,10 +357,23 @@ macro_rules! impl_try_from_integer_for_bool { /// ``` #[inline] fn try_from(i: $int) -> Result { - match i { - 0 => Ok(false), - 1 => Ok(true), - _ => Err(TryFromIntError(())), + sign_dependent_expr!{ + $signedness ? + if signed { + match i { + 0 => Ok(false), + 1 => Ok(true), + ..0 => Err(TryFromIntError(IntErrorKind::NegOverflow)), + 2.. => Err(TryFromIntError(IntErrorKind::PosOverflow)), + } + } + if unsigned { + match i { + 0 => Ok(false), + 1 => Ok(true), + 2.. => Err(TryFromIntError(IntErrorKind::PosOverflow)), + } + } } } } @@ -366,8 +387,8 @@ macro_rules! rev { } // integer -> bool -impl_try_from_integer_for_bool!(u128 u64 u32 u16 u8); -impl_try_from_integer_for_bool!(i128 i64 i32 i16 i8); +impl_try_from_integer_for_bool!(unsigned u128 u64 u32 u16 u8); +impl_try_from_integer_for_bool!(signed i128 i64 i32 i16 i8); // unsigned integer -> unsigned integer impl_try_from_upper_bounded!(u16 => u8); @@ -405,7 +426,7 @@ impl_try_from_lower_bounded!(isize => usize); #[cfg(target_pointer_width = "16")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8); impl_try_from_unbounded!(usize => u16, u32, u64, u128); @@ -427,7 +448,7 @@ mod ptr_try_from_impls { #[cfg(target_pointer_width = "32")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8, u16); impl_try_from_unbounded!(usize => u32, u64, u128); @@ -452,7 +473,7 @@ mod ptr_try_from_impls { #[cfg(target_pointer_width = "64")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8, u16, u32); impl_try_from_unbounded!(usize => u64, u128); @@ -482,7 +503,7 @@ macro_rules! impl_nonzero_int_from_nonzero_int { ($Small:ty => $Large:ty) => { #[stable(feature = "nz_int_conv", since = "1.41.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const From> for NonZero<$Large> { + const impl From> for NonZero<$Large> { // Rustdocs on the impl block show a "[+] show undocumented items" toggle. // Rustdocs on functions do not. #[doc = concat!("Converts [NonZero]\\<[", stringify!($Small), "]> ")] @@ -541,7 +562,7 @@ macro_rules! impl_nonzero_int_try_from_int { ($Int:ty) => { #[stable(feature = "nzint_try_from_int_conv", since = "1.46.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const TryFrom<$Int> for NonZero<$Int> { + const impl TryFrom<$Int> for NonZero<$Int> { type Error = TryFromIntError; // Rustdocs on the impl block show a "[+] show undocumented items" toggle. @@ -550,7 +571,7 @@ macro_rules! impl_nonzero_int_try_from_int { #[doc = concat!("to [NonZero]\\<[", stringify!($Int), "]>.")] #[inline] fn try_from(value: $Int) -> Result { - Self::new(value).ok_or(TryFromIntError(())) + Self::new(value).ok_or(TryFromIntError(IntErrorKind::Zero)) } } }; diff --git a/core/src/default.rs b/core/src/default.rs index 1cc4fb6e8fdd3..359ef29bb7331 100644 --- a/core/src/default.rs +++ b/core/src/default.rs @@ -151,7 +151,7 @@ macro_rules! default_impl { ($t:ty, $v:expr, $doc:tt) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] - impl const Default for $t { + const impl Default for $t { #[inline(always)] #[doc = $doc] fn default() -> $t { diff --git a/core/src/error.rs b/core/src/error.rs index 011d6ac4a1c78..0f01c09c8d91c 100644 --- a/core/src/error.rs +++ b/core/src/error.rs @@ -494,7 +494,7 @@ where /// `Request` supports generic, type-driven access to data. Its use is currently restricted to the /// standard library in cases where trait authors wish to allow trait implementors to share generic /// information across trait boundaries. The motivating and prototypical use case is -/// `core::error::Error` which would otherwise require a method per concrete type (eg. +/// `core::error::Error` which would otherwise require a method per concrete type (e.g. /// `std::backtrace::Backtrace` instance that implementors want to expose to users). /// /// # Data flow @@ -502,29 +502,29 @@ where /// To describe the intended data flow for Request objects, let's consider two conceptual users /// separated by API boundaries: /// -/// * Consumer - the consumer requests objects using a Request instance; eg a crate that offers +/// * Consumer - the consumer requests objects using a Request instance; e.g. a crate that offers /// fancy `Error`/`Result` reporting to users wants to request a Backtrace from a given `dyn Error`. /// -/// * Producer - the producer provides objects when requested via Request; eg. a library with an +/// * Producer - the producer provides objects when requested via Request; e.g. a library with an /// an `Error` implementation that automatically captures backtraces at the time instances are /// created. /// -/// The consumer only needs to know where to submit their request and are expected to handle the +/// The consumer only needs to know where to submit their request and is expected to handle the /// request not being fulfilled by the use of `Option` in the responses offered by the producer. /// /// * A Producer initializes the value of one of its fields of a specific type. (or is otherwise -/// prepared to generate a value requested). eg, `backtrace::Backtrace` or -/// `std::backtrace::Backtrace` +/// prepared to generate a value requested). e.g., `backtrace::Backtrace` or +/// `std::backtrace::Backtrace`. /// * A Consumer requests an object of a specific type (say `std::backtrace::Backtrace`). In the /// case of a `dyn Error` trait object (the Producer), there are functions called `request_ref` and /// `request_value` to simplify obtaining an `Option` for a given type. /// * The Producer, when requested, populates the given Request object which is given as a mutable /// reference. /// * The Consumer extracts a value or reference to the requested type from the `Request` object -/// wrapped in an `Option`; in the case of `dyn Error` the aforementioned `request_ref` and ` -/// request_value` methods mean that `dyn Error` users don't have to deal with the `Request` type at +/// wrapped in an `Option`; in the case of `dyn Error` the aforementioned `request_ref` and +/// `request_value` methods mean that `dyn Error` users don't have to deal with the `Request` type at /// all (but `Error` implementors do). The `None` case of the `Option` suggests only that the -/// Producer cannot currently offer an instance of the requested type, not it can't or never will. +/// Producer cannot currently offer an instance of the requested type, not that it can't or never will. /// /// # Examples /// diff --git a/core/src/ffi/c_double.md b/core/src/ffi/c_double.md index d49e29b6e6e7f..8586dec909d92 100644 --- a/core/src/ffi/c_double.md +++ b/core/src/ffi/c_double.md @@ -1,6 +1,6 @@ Equivalent to C's `double` type. -This type will almost always be [`f64`], which is guaranteed to be an [IEEE 754 double-precision float] in Rust. That said, the standard technically only guarantees that it be a floating-point number with at least the precision of a [`float`], and it may be `f32` or something entirely different from the IEEE-754 standard. +This type will almost always be [`f64`], which is guaranteed to be an [IEEE 754 double-precision float] in Rust. That said, the standard technically only guarantees that it be a floating-point number with at least the precision of a [`float`]; some 16-bit systems use [`f32`], for example. Esoteric systems could use something entirely different from the IEEE-754 standard. [IEEE 754 double-precision float]: https://en.wikipedia.org/wiki/IEEE_754 [`float`]: c_float diff --git a/core/src/ffi/c_short.md b/core/src/ffi/c_short.md index 3d1e53d1325f3..29415129b50a7 100644 --- a/core/src/ffi/c_short.md +++ b/core/src/ffi/c_short.md @@ -1,5 +1,3 @@ Equivalent to C's `signed short` (`short`) type. This type will almost always be [`i16`], but may differ on some esoteric systems. The C standard technically only requires that this type be a signed integer with at least 16 bits; some systems may define it as `i32`, for example. - -[`char`]: c_char diff --git a/core/src/ffi/c_str.rs b/core/src/ffi/c_str.rs index 62b3d75d7a779..d3318b0863e6e 100644 --- a/core/src/ffi/c_str.rs +++ b/core/src/ffi/c_str.rs @@ -155,7 +155,7 @@ impl Error for FromBytesWithNulError {} /// within the slice. /// /// This error is created by the [`CStr::from_bytes_until_nul`] method. -#[derive(Clone, PartialEq, Eq, Debug)] +#[derive(Clone, Copy, PartialEq, Eq, Debug)] #[stable(feature = "cstr_from_bytes_until_nul", since = "1.69.0")] pub struct FromBytesUntilNulError(()); @@ -176,7 +176,8 @@ impl fmt::Debug for CStr { } #[stable(feature = "cstr_default", since = "1.10.0")] -impl Default for &CStr { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for &CStr { #[inline] fn default() -> Self { c"" @@ -716,7 +717,7 @@ impl ops::Index> for CStr { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl ops::Index> for CStr { type Output = CStr; @@ -728,7 +729,7 @@ impl ops::Index> for CStr { #[stable(feature = "cstring_asref", since = "1.7.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for CStr { +const impl AsRef for CStr { #[inline] fn as_ref(&self) -> &CStr { self diff --git a/core/src/ffi/mod.rs b/core/src/ffi/mod.rs index f1b928da7ef3c..3f1aa54050a31 100644 --- a/core/src/ffi/mod.rs +++ b/core/src/ffi/mod.rs @@ -23,6 +23,7 @@ use crate::fmt; #[stable(feature = "c_str_module", since = "1.88.0")] pub mod c_str; +mod va_list; #[unstable( feature = "c_variadic", issue = "44930", @@ -30,13 +31,6 @@ pub mod c_str; )] pub use self::va_list::{VaArgSafe, VaList}; -#[unstable( - feature = "c_variadic", - issue = "44930", - reason = "the `c_variadic` feature has not been properly tested on all supported platforms" -)] -pub mod va_list; - mod primitives; #[stable(feature = "core_ffi_c", since = "1.64.0")] pub use self::primitives::{ diff --git a/core/src/ffi/primitives.rs b/core/src/ffi/primitives.rs index fa23cf33af431..11dad9a65470c 100644 --- a/core/src/ffi/primitives.rs +++ b/core/src/ffi/primitives.rs @@ -15,24 +15,27 @@ macro_rules! type_alias { } } -type_alias! { "c_char.md", c_char = c_char_definition::c_char; #[doc(cfg(all()))] } +// `#[doc(cfg(true))]` is used to prevent rustdoc from displaying a "Available on ..." box. +// The implementation of these constants is target-specific, but every target does define them. + +type_alias! { "c_char.md", c_char = c_char_definition::c_char; #[doc(cfg(true))] } type_alias! { "c_schar.md", c_schar = i8; } type_alias! { "c_uchar.md", c_uchar = u8; } type_alias! { "c_short.md", c_short = i16; } type_alias! { "c_ushort.md", c_ushort = u16; } -type_alias! { "c_int.md", c_int = c_int_definition::c_int; #[doc(cfg(all()))] } -type_alias! { "c_uint.md", c_uint = c_int_definition::c_uint; #[doc(cfg(all()))] } +type_alias! { "c_int.md", c_int = c_int_definition::c_int; #[doc(cfg(true))] } +type_alias! { "c_uint.md", c_uint = c_int_definition::c_uint; #[doc(cfg(true))] } -type_alias! { "c_long.md", c_long = c_long_definition::c_long; #[doc(cfg(all()))] } -type_alias! { "c_ulong.md", c_ulong = c_long_definition::c_ulong; #[doc(cfg(all()))] } +type_alias! { "c_long.md", c_long = c_long_definition::c_long; #[doc(cfg(true))] } +type_alias! { "c_ulong.md", c_ulong = c_long_definition::c_ulong; #[doc(cfg(true))] } type_alias! { "c_longlong.md", c_longlong = i64; } type_alias! { "c_ulonglong.md", c_ulonglong = u64; } type_alias! { "c_float.md", c_float = f32; } -type_alias! { "c_double.md", c_double = f64; } +type_alias! { "c_double.md", c_double= c_double_definition::c_double; #[doc(cfg(true))] } mod c_char_definition { crate::cfg_select! { @@ -183,3 +186,18 @@ mod c_int_definition { } } } + +mod c_double_definition { + crate::cfg_select! { + target_arch = "avr" => { + // avr: + // Per https://gcc.gnu.org/wiki/avr-gcc#Type_Layout. The table says `4,8` because + // in C the width of `double` can be changed with the `-mdouble=32/64` setting. But + // 32-bits is the default for the rust avr target. + pub(super) type c_double = f32; + } + _ => { + pub(super) type c_double = f64; + } + } +} diff --git a/core/src/ffi/va_list.rs b/core/src/ffi/va_list.rs index f0f58a0f83430..d5b83a23abe80 100644 --- a/core/src/ffi/va_list.rs +++ b/core/src/ffi/va_list.rs @@ -2,6 +2,12 @@ //! //! Better known as "varargs". +#![unstable( + feature = "c_variadic", + issue = "44930", + reason = "the `c_variadic` feature has not been properly tested on all supported platforms" +)] + #[cfg(not(target_arch = "xtensa"))] use crate::ffi::c_void; use crate::fmt; @@ -204,7 +210,7 @@ crate::cfg_select! { /// unsafe fn vmy_func(count: u32, mut ap: VaList<'_>) -> i32 { /// let mut sum = 0; /// for _ in 0..count { -/// sum += unsafe { ap.arg::() }; +/// sum += unsafe { ap.next_arg::() }; /// } /// sum /// } @@ -213,14 +219,15 @@ crate::cfg_select! { /// assert_eq!(unsafe { my_func(3, 42i32, -7i32, 20i32) }, 55); /// ``` /// -/// The [`VaList::arg`] method can be used to read an argument from the list. This method -/// automatically advances the `VaList` to the next argument. The C equivalent is `va_arg`. +/// The [`VaList::next_arg`] method reads the next argument from the variable argument list, +/// and is equivalent to C `va_arg`. /// /// Cloning a `VaList` performs the equivalent of C `va_copy`, producing an independent cursor /// that arguments can be read from without affecting the original. Dropping a `VaList` performs /// the equivalent of C `va_end`. /// -/// This can be used across an FFI boundary, and fully matches the platform's `va_list`. +/// A `VaList` can be used across an FFI boundary, and fully matches the platform's `va_list` in +/// terms of layout and ABI. #[repr(transparent)] #[lang = "va_list"] pub struct VaList<'a> { @@ -243,7 +250,10 @@ impl VaList<'_> { } #[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] -impl<'f> const Clone for VaList<'f> { +const impl<'f> Clone for VaList<'f> { + /// Clone the [`VaList`], producing a second independent cursor into the variable argument list. + /// + /// Corresponds to `va_copy` in C. #[inline] // Avoid codegen when not used to help backends that don't support VaList. fn clone(&self) -> Self { // We only implement Clone and not Copy because some future target might not be able to @@ -255,9 +265,15 @@ impl<'f> const Clone for VaList<'f> { } #[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] -impl<'f> const Drop for VaList<'f> { +const impl<'f> Drop for VaList<'f> { + /// Drop the [`VaList`]. + /// + /// Corresponds to `va_end` in C. #[inline] // Avoid codegen when not used to help backends that don't support VaList. fn drop(&mut self) { + // Call the rust `va_end` intrinsic, which is a no-op and does not map to LLVM `va_end`. + // The rust intrinsic exists as a hook for Miri to check for UB. + // // SAFETY: this variable argument list is being dropped, so won't be read from again. unsafe { va_end(self) } } @@ -266,70 +282,148 @@ impl<'f> const Drop for VaList<'f> { mod sealed { pub trait Sealed {} + impl Sealed for i16 {} impl Sealed for i32 {} impl Sealed for i64 {} impl Sealed for isize {} + impl Sealed for u16 {} impl Sealed for u32 {} impl Sealed for u64 {} impl Sealed for usize {} + impl Sealed for f32 {} impl Sealed for f64 {} impl Sealed for *mut T {} impl Sealed for *const T {} } -/// Types that are valid to read using [`VaList::arg`]. +/// Types that are valid to read using [`VaList::next_arg`]. /// -/// # Safety +/// This trait is implemented for primitive types that have a variable argument application-binary +/// interface (ABI) on the current platform. It is always implemented for: /// -/// The standard library implements this trait for primitive types that are -/// expected to have a variable argument application-binary interface (ABI) on all -/// platforms. +/// - [`c_int`], [`c_long`] and [`c_longlong`] +/// - [`c_uint`], [`c_ulong`] and [`c_ulonglong`] +/// - [`c_double`] +/// - `*const T` and `*mut T` /// -/// When C passes variable arguments, integers smaller than [`c_int`] and floats smaller -/// than [`c_double`] are implicitly promoted to [`c_int`] and [`c_double`] respectively. -/// Implementing this trait for types that are subject to this promotion rule is invalid. +/// Implementations for e.g. `i32` or `usize` shouldn't be relied upon directly, +/// because they may not be available on all platforms. +/// +/// # Safety +/// +/// When C passes variable arguments, signed integers smaller than [`c_int`] are promoted +/// to [`c_int`], unsigned integers smaller than [`c_uint`] are promoted to [`c_uint`], +/// and [`c_float`] is promoted to [`c_double`]. Implementing this trait for types that are +/// subject to this promotion rule is invalid. /// /// [`c_int`]: core::ffi::c_int +/// [`c_long`]: core::ffi::c_long +/// [`c_longlong`]: core::ffi::c_longlong +/// +/// [`c_uint`]: core::ffi::c_uint +/// [`c_ulong`]: core::ffi::c_ulong +/// [`c_ulonglong`]: core::ffi::c_ulonglong +/// +/// [`c_float`]: core::ffi::c_float /// [`c_double`]: core::ffi::c_double // We may unseal this trait in the future, but currently our `va_arg` implementations don't support // types with an alignment larger than 8, or with a non-scalar layout. Inline assembly can be used // to accept unsupported types in the meantime. -pub unsafe trait VaArgSafe: sealed::Sealed {} +#[lang = "va_arg_safe"] +pub unsafe trait VaArgSafe: Copy + sealed::Sealed {} + +crate::cfg_select! { + any(target_arch = "avr", target_arch = "msp430") => { + // c_int/c_uint are i16/u16 on these targets. + // + // - i8 is implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. + // - u8 is implicitly promoted to c_uint in C, and cannot implement `VaArgSafe`. + unsafe impl VaArgSafe for i16 {} + unsafe impl VaArgSafe for u16 {} + } + _ => { + // c_int/c_uint are i32/u32 on this target. + // + // - i8 and i16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. + // - u8 and u16 are implicitly promoted to c_uint in C, and cannot implement `VaArgSafe`. + } +} + +crate::cfg_select! { + target_arch = "avr" => { + // c_double is f32 on this target. + unsafe impl VaArgSafe for f32 {} + } + _ => { + // c_double is f64 on this target. + // + // - f32 is implicitly promoted to c_double in C, and cannot implement `VaArgSafe`. + } +} -// i8 and i16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. unsafe impl VaArgSafe for i32 {} unsafe impl VaArgSafe for i64 {} unsafe impl VaArgSafe for isize {} -// u8 and u16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. unsafe impl VaArgSafe for u32 {} unsafe impl VaArgSafe for u64 {} unsafe impl VaArgSafe for usize {} -// f32 is implicitly promoted to c_double in C, and cannot implement `VaArgSafe`. unsafe impl VaArgSafe for f64 {} unsafe impl VaArgSafe for *mut T {} unsafe impl VaArgSafe for *const T {} +// Check that relevant `core::ffi` types implement `VaArgSafe`. +const _: () = { + const fn va_arg_safe_check() {} + + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); + + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); + + va_arg_safe_check::(); + + va_arg_safe_check::<*const crate::ffi::c_void>(); + va_arg_safe_check::<*mut crate::ffi::c_void>(); + + va_arg_safe_check::<*const crate::ffi::c_char>(); + va_arg_safe_check::<*mut crate::ffi::c_char>(); +}; + impl<'f> VaList<'f> { - /// Read an argument from the variable argument list, and advance to the next argument. + /// Read the next argument from the variable argument list. /// /// Only types that implement [`VaArgSafe`] can be read from a variable argument list. /// /// # Safety /// - /// This function is only sound to call when there is another argument to read, and that - /// argument is a properly initialized value of the type `T`. + /// This function is safe to call only if all of the following conditions are satisfied: + /// + /// - There is another c-variadic argument to read. + /// - The actual type of the argument `U` is compatible with `T` (as defined below). + /// - If `U` and `T` are both integer types, then the value passed by the caller must be + /// representable in both types. + /// + /// Types `T` and `U` are compatible when: + /// + /// - `T` and `U` are the same type. + /// - `T` and `U` are integer types of the same size. + /// - `T` and `U` are both pointers, and their target types are compatible. + /// - `T` is a pointer to [`c_void`] and `U` is a pointer to [`i8`] or [`u8`], or vice versa. /// - /// Calling this function with an incompatible type, an invalid value, or when there - /// are no more variable arguments, is unsound. + /// [`c_void`]: core::ffi::c_void #[inline] // Avoid codegen when not used to help backends that don't support VaList. #[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] - pub const unsafe fn arg(&mut self) -> T { + #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces + pub const unsafe fn next_arg(&mut self) -> T { // SAFETY: the caller must uphold the safety contract for `va_arg`. unsafe { va_arg(self) } } diff --git a/core/src/field.rs b/core/src/field.rs index e8ef309b9c84f..90d16e5f2af5f 100644 --- a/core/src/field.rs +++ b/core/src/field.rs @@ -1,26 +1,64 @@ //! Field Reflection +use crate::fmt; +use crate::hash::{Hash, Hasher}; use crate::marker::PhantomData; /// Field Representing Type #[unstable(feature = "field_representing_type_raw", issue = "none")] #[lang = "field_representing_type"] -#[expect(missing_debug_implementations)] #[fundamental] pub struct FieldRepresentingType { - _phantom: PhantomData, + // We want this type to be invariant over `T`, because otherwise `field_of!(Struct<'short>, + // field)` is a subtype of `field_of!(Struct<'long>, field)`. This subtype relationship does not + // have an immediately obvious meaning and we want to prevent people from relying on it. + _phantom: PhantomData T>, } -// SAFETY: `FieldRepresentingType` doesn't contain any `T` -unsafe impl Send - for FieldRepresentingType -{ -} - -// SAFETY: `FieldRepresentingType` doesn't contain any `T` -unsafe impl Sync +impl fmt::Debug for FieldRepresentingType { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + enum Member { + Name(&'static str), + Index(u32), + } + impl fmt::Display for Member { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Name(name) => fmt::Display::fmt(name, f), + Self::Index(idx) => fmt::Display::fmt(idx, f), + } + } + } + let (variant, field) = const { + use crate::mem::type_info::{Type, TypeKind}; + match Type::of::().kind { + TypeKind::Struct(struct_) => { + (None, Member::Name(struct_.fields[FIELD as usize].name)) + } + TypeKind::Tuple(_) => (None, Member::Index(FIELD)), + TypeKind::Enum(enum_) => { + let variant = &enum_.variants[VARIANT as usize]; + (Some(variant.name), Member::Name(variant.fields[FIELD as usize].name)) + } + TypeKind::Union(union) => (None, Member::Name(union.fields[FIELD as usize].name)), + _ => unreachable!(), + } + }; + let type_name = const { crate::any::type_name::() }; + match variant { + Some(variant) => write!(f, "field_of!({type_name}, {variant}.{field})"), + None => write!(f, "field_of!({type_name}, {field})"), + } + // NOTE: if there are changes in the reflection work and the above no + // longer compiles, then the following debug impl could also work in + // the meantime: + // ```rust + // let type_name = const { type_name::() }; + // write!(f, "field_of!({type_name}, {VARIANT}.{FIELD})") + // ``` + } } impl Copy @@ -36,12 +74,60 @@ impl Clone } } +impl Default + for FieldRepresentingType +{ + fn default() -> Self { + Self { _phantom: PhantomData::default() } + } +} + +impl Hash + for FieldRepresentingType +{ + fn hash(&self, state: &mut H) { + self._phantom.hash(state); + } +} + +impl PartialEq + for FieldRepresentingType +{ + fn eq(&self, other: &Self) -> bool { + self._phantom == other._phantom + } +} + +impl Eq + for FieldRepresentingType +{ +} + +impl PartialOrd + for FieldRepresentingType +{ + fn partial_cmp(&self, other: &Self) -> Option { + self._phantom.partial_cmp(&other._phantom) + } +} + +impl Ord + for FieldRepresentingType +{ + fn cmp(&self, other: &Self) -> crate::cmp::Ordering { + self._phantom.cmp(&other._phantom) + } +} + /// Expands to the field representing type of the given field. /// /// The container type may be a tuple, `struct`, `union` or `enum`. In the case of an enum, the /// variant must also be specified. Only a single field is supported. #[unstable(feature = "field_projections", issue = "145383")] #[allow_internal_unstable(field_representing_type_raw, builtin_syntax)] +#[diagnostic::on_unmatch_args( + note = "this macro expects a container type and a field path, like `field_of!(Type, field)` or `field_of!(Enum, Variant.field)`" +)] // NOTE: when stabilizing this macro, we can never add new trait impls for `FieldRepresentingType`, // since it is `#[fundamental]` and thus could break users of this macro, since the compiler expands // it to `FieldRepresentingType<...>`. Thus stabilizing this requires careful thought about the diff --git a/core/src/fmt/float.rs b/core/src/fmt/float.rs index 87ce27b0d86de..bb70e59f960ed 100644 --- a/core/src/fmt/float.rs +++ b/core/src/fmt/float.rs @@ -171,8 +171,7 @@ where }; if let Some(precision) = fmt.options.get_precision() { - // 1 integral digit + `precision` fractional digits = `precision + 1` total digits - float_to_exponential_common_exact(fmt, num, sign, precision + 1, upper) + float_to_exponential_common_exact(fmt, num, sign, precision, upper) } else { float_to_exponential_common_shortest(fmt, num, sign, upper) } diff --git a/core/src/fmt/mod.rs b/core/src/fmt/mod.rs index ecd1e34078e29..9e5f693246f33 100644 --- a/core/src/fmt/mod.rs +++ b/core/src/fmt/mod.rs @@ -2007,7 +2007,13 @@ impl<'a> Formatter<'a> { // SAFETY: Per the precondition. unsafe { self.write_formatted_parts(&formatted) } } else { - let post_padding = self.padding(width - len as u16, Alignment::Right)?; + // Padding widths are capped at `u16`, so reaching this branch means + // the formatted output is also shorter than `u16::MAX`. + let len = match u16::try_from(len) { + Ok(len) => len, + Err(_) => unreachable!(), + }; + let post_padding = self.padding(width - len, Alignment::Right)?; // SAFETY: Per the precondition. unsafe { self.write_formatted_parts(&formatted)?; diff --git a/core/src/fmt/num.rs b/core/src/fmt/num.rs index e9302a6127f5c..309aee53f93c7 100644 --- a/core/src/fmt/num.rs +++ b/core/src/fmt/num.rs @@ -299,8 +299,8 @@ macro_rules! impl_Display { } impl $Unsigned { - /// Allows users to write an integer (in signed decimal format) into a variable `buf` of - /// type [`NumBuffer`] that is passed by the caller by mutable reference. + /// Allows users to write an integer (in unsigned decimal format) into a variable `buf` + /// of type [`NumBuffer`] that is passed by the caller by mutable reference. /// /// # Examples /// @@ -738,7 +738,7 @@ impl u128 { offset } - /// Allows users to write an integer (in signed decimal format) into a variable `buf` of + /// Allows users to write an integer (in unsigned decimal format) into a variable `buf` of /// type [`NumBuffer`] that is passed by the caller by mutable reference. /// /// # Examples @@ -868,7 +868,7 @@ fn div_rem_1e16(n: u128) -> (u128, u64) { const M_HIGH: u128 = 76624777043294442917917351357515459181; const SH_POST: u8 = 51; - let quot = n.widening_mul(M_HIGH).1 >> SH_POST; + let quot = n.carrying_mul(M_HIGH, 0).1 >> SH_POST; let rem = n - quot * D; (quot, rem as u64) } diff --git a/core/src/fmt/num_buffer.rs b/core/src/fmt/num_buffer.rs index 474a8d20ef6c5..cc3680b8a42be 100644 --- a/core/src/fmt/num_buffer.rs +++ b/core/src/fmt/num_buffer.rs @@ -34,8 +34,23 @@ impl_NumBufferTrait! { /// A buffer wrapper of which the internal size is based on the maximum /// number of digits the associated integer can have. +/// +/// # Examples +/// +/// ``` +/// #![feature(int_format_into)] +/// use core::fmt::NumBuffer; +/// +/// let mut buf = NumBuffer::new(); +/// let n1 = 1972u32; +/// assert_eq!(n1.format_into(&mut buf), "1972"); +/// +/// // Formatting a negative integer includes the sign. +/// let mut buf = NumBuffer::new(); +/// let n2 = -1972i32; +/// assert_eq!(n2.format_into(&mut buf), "-1972"); +/// ``` #[unstable(feature = "int_format_into", issue = "138215")] -#[derive(Debug)] pub struct NumBuffer { // FIXME: Once const generics feature is working, use `T::BUF_SIZE` instead of 40. pub(crate) buf: [MaybeUninit; 40], @@ -43,6 +58,13 @@ pub struct NumBuffer { phantom: core::marker::PhantomData, } +#[unstable(feature = "int_format_into", issue = "138215")] +impl core::fmt::Debug for NumBuffer { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + f.debug_struct("NumBuffer").finish() + } +} + #[unstable(feature = "int_format_into", issue = "138215")] impl NumBuffer { /// Initializes internal buffer. diff --git a/core/src/future/async_drop.rs b/core/src/future/async_drop.rs index 106493fd3e815..2f067531f18a4 100644 --- a/core/src/future/async_drop.rs +++ b/core/src/future/async_drop.rs @@ -52,7 +52,7 @@ pub trait AsyncDrop { /// [ptr::drop_in_place]: crate::ptr::drop_in_place() #[unstable(feature = "async_drop", issue = "126482")] #[lang = "async_drop_in_place"] -pub async unsafe fn async_drop_in_place(_to_drop: *mut T) { +pub async unsafe fn async_drop_in_place(_to_drop: &mut T) { // Code here does not matter - this is replaced by the // real implementation by the compiler. } diff --git a/core/src/hash/mod.rs b/core/src/hash/mod.rs index eea6118571204..c7c8d57e1010d 100644 --- a/core/src/hash/mod.rs +++ b/core/src/hash/mod.rs @@ -784,7 +784,7 @@ impl Clone for BuildHasherDefault { #[stable(since = "1.7.0", feature = "build_hasher")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for BuildHasherDefault { +const impl Default for BuildHasherDefault { fn default() -> BuildHasherDefault { Self::new() } diff --git a/core/src/hash/sip.rs b/core/src/hash/sip.rs index eed1044bd2a92..bc74bd0e085ff 100644 --- a/core/src/hash/sip.rs +++ b/core/src/hash/sip.rs @@ -340,7 +340,7 @@ impl Clone for Hasher { } #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Hasher { +const impl Default for Hasher { /// Creates a `Hasher` with the two initial keys set to 0. #[inline] fn default() -> Hasher { diff --git a/core/src/hint.rs b/core/src/hint.rs index a8e01e6e78b4b..90326e649058b 100644 --- a/core/src/hint.rs +++ b/core/src/hint.rs @@ -778,6 +778,9 @@ pub const fn unlikely(b: bool) -> bool { #[stable(feature = "cold_path", since = "1.95.0")] #[rustc_const_stable(feature = "cold_path", since = "1.95.0")] #[inline(always)] +// Even if for some reason the cold_path intrinsic is not visible to codegen, the coldness will +// ensure that branches this is in are still known to be cold. +#[cold] pub const fn cold_path() { crate::intrinsics::cold_path() } diff --git a/core/src/intrinsics/fallback.rs b/core/src/intrinsics/fallback.rs index aa9033ee3d260..bc415ec977684 100644 --- a/core/src/intrinsics/fallback.rs +++ b/core/src/intrinsics/fallback.rs @@ -80,7 +80,7 @@ const fn wide_mul_u128(a: u128, b: u128) -> (u128, u128) { } #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] -impl const CarryingMulAdd for u128 { +const impl CarryingMulAdd for u128 { type Unsigned = u128; #[inline] fn carrying_mul_add(self, b: u128, c: u128, d: u128) -> (u128, u128) { @@ -94,7 +94,7 @@ impl const CarryingMulAdd for u128 { } #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] -impl const CarryingMulAdd for i128 { +const impl CarryingMulAdd for i128 { type Unsigned = u128; #[inline] fn carrying_mul_add(self, b: i128, c: i128, d: i128) -> (u128, i128) { diff --git a/core/src/intrinsics/gpu.rs b/core/src/intrinsics/gpu.rs index 9e7624841d0c6..8ea894b3955d4 100644 --- a/core/src/intrinsics/gpu.rs +++ b/core/src/intrinsics/gpu.rs @@ -5,6 +5,51 @@ #![unstable(feature = "gpu_intrinsics", issue = "none")] +/// Returns the pointer to workgroup memory allocated at launch-time on GPUs. +/// +/// Workgroup memory is a memory region that is shared between all threads in +/// the same workgroup. It is faster to access than other memory but pointers do not +/// work outside the workgroup where they were obtained. +/// Workgroup memory can be allocated statically or after compilation, when +/// launching a gpu-kernel. `gpu_launch_sized_workgroup_mem` returns the pointer to +/// the memory that is allocated at launch-time. +/// The size of this memory can differ between launches of a gpu-kernel, depending on +/// what is specified at launch-time. +/// However, the alignment is fixed by the kernel itself, at compile-time. +/// +/// The returned pointer is the start of the workgroup memory region that is +/// allocated at launch-time. +/// All calls to `gpu_launch_sized_workgroup_mem` in a workgroup, independent of the +/// generic type, return the same address, so alias the same memory. +/// The returned pointer is aligned by at least the alignment of `T`. +/// +/// If `gpu_launch_sized_workgroup_mem` is invoked multiple times with different +/// types that have different alignment, then you may only rely on the resulting +/// pointer having the alignment of `T` after a call to `gpu_launch_sized_workgroup_mem::` +/// has occurred in the current program execution. +/// +/// # Safety +/// +/// The pointer is safe to dereference from the start (the returned pointer) up to the +/// size of workgroup memory that was specified when launching the current gpu-kernel. +/// This allocated size is not related in any way to `T`. +/// +/// The user must take care of synchronizing access to workgroup memory between +/// threads in a workgroup. The usual data race requirements apply. +/// +/// # Other APIs +/// +/// CUDA and HIP call this dynamic shared memory, shared between threads in a block. +/// OpenCL and SYCL call this local memory, shared between threads in a work-group. +/// GLSL calls this shared memory, shared between invocations in a work group. +/// DirectX calls this groupshared memory, shared between threads in a thread-group. +#[must_use = "returns a pointer that does nothing unless used"] +#[rustc_intrinsic] +#[rustc_nounwind] +#[unstable(feature = "gpu_launch_sized_workgroup_mem", issue = "135513")] +#[cfg(any(doc, target_arch = "amdgpu", target_arch = "nvptx64"))] +pub fn gpu_launch_sized_workgroup_mem() -> *mut T; + /// Returns a pointer to the HSA kernel dispatch packet. /// /// A `gpu-kernel` on amdgpu is always launched through a kernel dispatch packet. @@ -18,6 +63,6 @@ /// [hsa.h]: https://github.com/ROCm/rocm-systems/blob/rocm-7.1.0/projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h#L2959 #[rustc_nounwind] #[rustc_intrinsic] -#[cfg(target_arch = "amdgpu")] +#[cfg(any(doc, target_arch = "amdgpu"))] #[must_use = "returns a pointer that does nothing unless used"] pub fn amdgpu_dispatch_ptr() -> *const (); diff --git a/core/src/intrinsics/mir.rs b/core/src/intrinsics/mir.rs index 7659e0042b379..183db46c6405e 100644 --- a/core/src/intrinsics/mir.rs +++ b/core/src/intrinsics/mir.rs @@ -229,7 +229,7 @@ //! //! #### Statements //! - Assign statements work via normal Rust assignment. -//! - [`Retag`], [`StorageLive`], [`StorageDead`] statements have an associated function. +//! - [`StorageLive`], [`StorageDead`] statements have an associated function. //! //! #### Rvalues //! @@ -407,7 +407,6 @@ define!( "mir_ptr_metadata", fn PtrMetadata(place: *const P) ->

(&mut self, predicate: P) -> Option where Self: Sized, diff --git a/core/src/iter/traits/iterator.rs b/core/src/iter/traits/iterator.rs index 943e869d74380..c5182cb3d0720 100644 --- a/core/src/iter/traits/iterator.rs +++ b/core/src/iter/traits/iterator.rs @@ -7,6 +7,7 @@ use super::super::{ use super::TrustedLen; use crate::array; use crate::cmp::{self, Ordering}; +use crate::marker::Destruct; use crate::num::NonZero; use crate::ops::{ChangeOutputType, ControlFlow, FromResidual, Residual, Try}; @@ -108,7 +109,6 @@ pub const trait Iterator { /// ``` #[inline] #[unstable(feature = "iter_next_chunk", issue = "98326")] - #[rustc_non_const_trait_method] fn next_chunk( &mut self, ) -> Result<[Self::Item; N], array::IntoIter> @@ -221,15 +221,15 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn count(self) -> usize where - Self: Sized, + Self: Sized + [const] Destruct, + Self::Item: [const] Destruct, { self.fold( 0, #[rustc_inherit_overflow_checks] - |count, _| count + 1, + const |accum, _elem| accum + 1, ) } @@ -254,13 +254,17 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn last(self) -> Option where - Self: Sized, + Self: Sized + [const] Destruct, + Self::Item: [const] Destruct, { #[inline] - fn some(_: Option, x: T) -> Option { + #[rustc_const_unstable(feature = "const_destruct", issue = "133214")] + const fn some(_: Option, x: T) -> Option + where + T: [const] Destruct, + { Some(x) } @@ -503,11 +507,10 @@ pub const trait Iterator { /// [`OsStr`]: ../../std/ffi/struct.OsStr.html #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn chain(self, other: U) -> Chain where Self: Sized, - U: IntoIterator, + U: [const] IntoIterator, { Chain::new(self, other.into_iter()) } @@ -687,7 +690,6 @@ pub const trait Iterator { /// [`intersperse_with`]: Iterator::intersperse_with #[inline] #[unstable(feature = "iter_intersperse", issue = "79524")] - #[rustc_non_const_trait_method] fn intersperse(self, separator: Self::Item) -> Intersperse where Self: Sized, @@ -767,7 +769,6 @@ pub const trait Iterator { /// [`intersperse_with`]: Iterator::intersperse_with #[inline] #[unstable(feature = "iter_intersperse", issue = "79524")] - #[rustc_non_const_trait_method] fn intersperse_with(self, separator: G) -> IntersperseWith where Self: Sized, @@ -827,7 +828,6 @@ pub const trait Iterator { #[rustc_diagnostic_item = "IteratorMap"] #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn map(self, f: F) -> Map where Self: Sized, @@ -949,7 +949,6 @@ pub const trait Iterator { #[inline] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "iter_filter"] - #[rustc_non_const_trait_method] fn filter

(self, predicate: P) -> Filter where Self: Sized, @@ -995,7 +994,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn filter_map(self, f: F) -> FilterMap where Self: Sized, @@ -1043,7 +1041,6 @@ pub const trait Iterator { #[inline] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "enumerate_method"] - #[rustc_non_const_trait_method] fn enumerate(self) -> Enumerate where Self: Sized, @@ -1115,7 +1112,6 @@ pub const trait Iterator { /// [`next`]: Iterator::next #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn peekable(self) -> Peekable where Self: Sized, @@ -1181,7 +1177,6 @@ pub const trait Iterator { #[inline] #[doc(alias = "drop_while")] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn skip_while

(self, predicate: P) -> SkipWhile where Self: Sized, @@ -1260,7 +1255,6 @@ pub const trait Iterator { /// the iteration should stop, but wasn't placed back into the iterator. #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn take_while

(self, predicate: P) -> TakeWhile where Self: Sized, @@ -1349,7 +1343,6 @@ pub const trait Iterator { /// [`fuse`]: Iterator::fuse #[inline] #[stable(feature = "iter_map_while", since = "1.57.0")] - #[rustc_non_const_trait_method] fn map_while(self, predicate: P) -> MapWhile where Self: Sized, @@ -1379,7 +1372,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn skip(self, n: usize) -> Skip where Self: Sized, @@ -1452,7 +1444,6 @@ pub const trait Iterator { #[doc(alias = "limit")] #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn take(self, n: usize) -> Take where Self: Sized, @@ -1500,7 +1491,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn scan(self, initial_state: St, f: F) -> Scan where Self: Sized, @@ -1624,7 +1614,6 @@ pub const trait Iterator { /// [`flat_map()`]: Iterator::flat_map #[inline] #[stable(feature = "iterator_flatten", since = "1.29.0")] - #[rustc_non_const_trait_method] fn flatten(self) -> Flatten where Self: Sized, @@ -1779,7 +1768,6 @@ pub const trait Iterator { /// ``` #[inline] #[unstable(feature = "iter_map_windows", issue = "87155")] - #[rustc_non_const_trait_method] fn map_windows(self, f: F) -> MapWindows where Self: Sized, @@ -1842,7 +1830,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn fuse(self) -> Fuse where Self: Sized, @@ -1927,7 +1914,6 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn inspect(self, f: F) -> Inspect where Self: Sized, @@ -2497,12 +2483,11 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "iterator_try_fold", since = "1.27.0")] - #[rustc_non_const_trait_method] fn try_fold(&mut self, init: B, mut f: F) -> R where Self: Sized, - F: FnMut(B, Self::Item) -> R, - R: Try, + F: [const] FnMut(B, Self::Item) -> R + [const] Destruct, + R: [const] Try, { let mut accum = init; while let Some(x) = self.next() { @@ -2676,11 +2661,10 @@ pub const trait Iterator { #[doc(alias = "inject", alias = "foldl")] #[inline] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn fold(mut self, init: B, mut f: F) -> B where - Self: Sized, - F: FnMut(B, Self::Item) -> B, + Self: Sized + [const] Destruct, + F: [const] FnMut(B, Self::Item) -> B + [const] Destruct, { let mut accum = init; while let Some(x) = self.next() { @@ -2714,11 +2698,10 @@ pub const trait Iterator { /// ``` #[inline] #[stable(feature = "iterator_fold_self", since = "1.51.0")] - #[rustc_non_const_trait_method] fn reduce(mut self, f: F) -> Option where - Self: Sized, - F: FnMut(Self::Item, Self::Item) -> Self::Item, + Self: Sized + [const] Destruct, + F: [const] FnMut(Self::Item, Self::Item) -> Self::Item + [const] Destruct, { let first = self.next()?; Some(self.fold(first, f)) @@ -2786,14 +2769,13 @@ pub const trait Iterator { /// ``` #[inline] #[unstable(feature = "iterator_try_reduce", issue = "87053")] - #[rustc_non_const_trait_method] fn try_reduce( &mut self, - f: impl FnMut(Self::Item, Self::Item) -> R, + f: impl [const] FnMut(Self::Item, Self::Item) -> R + [const] Destruct, ) -> ChangeOutputType> where Self: Sized, - R: Try>>, + R: [const] Try>>, { let first = match self.next() { Some(i) => i, @@ -3458,7 +3440,6 @@ pub const trait Iterator { #[inline] #[doc(alias = "reverse")] #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_non_const_trait_method] fn rev(self) -> Rev where Self: Sized + DoubleEndedIterator, @@ -3527,7 +3508,6 @@ pub const trait Iterator { /// ``` #[stable(feature = "iter_copied", since = "1.36.0")] #[rustc_diagnostic_item = "iter_copied"] - #[rustc_non_const_trait_method] fn copied<'a, T>(self) -> Copied where T: Copy + 'a, @@ -3576,7 +3556,6 @@ pub const trait Iterator { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "iter_cloned"] - #[rustc_non_const_trait_method] fn cloned<'a, T>(self) -> Cloned where T: Clone + 'a, @@ -3608,10 +3587,9 @@ pub const trait Iterator { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[inline] - #[rustc_non_const_trait_method] fn cycle(self) -> Cycle where - Self: Sized + Clone, + Self: Sized + [const] Clone, { Cycle::new(self) } @@ -3652,7 +3630,6 @@ pub const trait Iterator { /// ``` #[track_caller] #[unstable(feature = "iter_array_chunks", issue = "100450")] - #[rustc_non_const_trait_method] fn array_chunks(self) -> ArrayChunks where Self: Sized, @@ -3689,16 +3666,15 @@ pub const trait Iterator { /// assert_eq!(sum, -0.0_f32); /// ``` #[stable(feature = "iter_arith", since = "1.11.0")] - #[rustc_non_const_trait_method] fn sum(self) -> S where Self: Sized, - S: Sum, + S: [const] Sum, { Sum::sum(self) } - /// Iterates over the entire iterator, multiplying all the elements + /// Iterates over the entire iterator, multiplying all the elements. /// /// An empty iterator returns the one value of the type. /// @@ -3722,11 +3698,10 @@ pub const trait Iterator { /// assert_eq!(factorial(5), 120); /// ``` #[stable(feature = "iter_arith", since = "1.11.0")] - #[rustc_non_const_trait_method] fn product

(self) -> P where Self: Sized, - P: Product, + P: [const] Product, { Product::product(self) } diff --git a/core/src/iter/traits/marker.rs b/core/src/iter/traits/marker.rs index 2e756a6dd67c4..542d283fe95ab 100644 --- a/core/src/iter/traits/marker.rs +++ b/core/src/iter/traits/marker.rs @@ -63,9 +63,11 @@ impl FusedIterator for &mut I {} /// of this trait must inspect [`Iterator::size_hint()`]’s upper bound. #[unstable(feature = "trusted_len", issue = "37572")] #[rustc_unsafe_specialization_marker] -pub unsafe trait TrustedLen: Iterator {} +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +pub const unsafe trait TrustedLen: [const] Iterator {} #[unstable(feature = "trusted_len", issue = "37572")] +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] unsafe impl TrustedLen for &mut I {} /// An iterator that when yielding an item will have taken at least one element diff --git a/core/src/iter/traits/mod.rs b/core/src/iter/traits/mod.rs index b330e9ffe21ac..7639704d5799c 100644 --- a/core/src/iter/traits/mod.rs +++ b/core/src/iter/traits/mod.rs @@ -4,7 +4,6 @@ mod double_ended; mod exact_size; mod iterator; mod marker; -mod unchecked_iterator; #[unstable(issue = "none", feature = "inplace_iteration")] pub use self::marker::InPlaceIterable; @@ -12,7 +11,6 @@ pub use self::marker::InPlaceIterable; pub use self::marker::TrustedFused; #[unstable(feature = "trusted_step", issue = "85731")] pub use self::marker::TrustedStep; -pub(crate) use self::unchecked_iterator::UncheckedIterator; #[stable(feature = "rust1", since = "1.0.0")] pub use self::{ accum::{Product, Sum}, diff --git a/core/src/iter/traits/unchecked_iterator.rs b/core/src/iter/traits/unchecked_iterator.rs deleted file mode 100644 index ae4bfcad4e68f..0000000000000 --- a/core/src/iter/traits/unchecked_iterator.rs +++ /dev/null @@ -1,36 +0,0 @@ -use crate::iter::TrustedLen; - -/// [`TrustedLen`] cannot have methods, so this allows augmenting it. -/// -/// It currently requires `TrustedLen` because it's unclear whether it's -/// reasonably possible to depend on the `size_hint` of anything else. -pub(crate) trait UncheckedIterator: TrustedLen { - /// Gets the next item from a non-empty iterator. - /// - /// Because there's always a value to return, that means it can return - /// the `Item` type directly, without wrapping it in an `Option`. - /// - /// # Safety - /// - /// This can only be called if `size_hint().0 != 0`, guaranteeing that - /// there's at least one item available. - /// - /// Otherwise (aka when `size_hint().1 == Some(0)`), this is UB. - /// - /// # Note to Implementers - /// - /// This has a default implementation using [`Option::unwrap_unchecked`]. - /// That's probably sufficient if your `next` *always* returns `Some`, - /// such as for infinite iterators. In more complicated situations, however, - /// sometimes there can still be `insertvalue`/`assume`/`extractvalue` - /// instructions remaining in the IR from the `Option` handling, at which - /// point you might want to implement this manually instead. - #[unstable(feature = "trusted_len_next_unchecked", issue = "37572")] - #[inline] - unsafe fn next_unchecked(&mut self) -> Self::Item { - let opt = self.next(); - // SAFETY: The caller promised that we're not empty, and - // `Self: TrustedLen` so we can actually trust the `size_hint`. - unsafe { opt.unwrap_unchecked() } - } -} diff --git a/core/src/lib.rs b/core/src/lib.rs index 35f93d8fb33b2..b16996acb1c44 100644 --- a/core/src/lib.rs +++ b/core/src/lib.rs @@ -61,11 +61,11 @@ target_has_atomic = "32", target_has_atomic = "64", target_has_atomic = "ptr", - target_has_atomic_equal_alignment = "8", - target_has_atomic_equal_alignment = "16", - target_has_atomic_equal_alignment = "32", - target_has_atomic_equal_alignment = "64", - target_has_atomic_equal_alignment = "ptr", + target_has_atomic_primitive_alignment = "8", + target_has_atomic_primitive_alignment = "16", + target_has_atomic_primitive_alignment = "32", + target_has_atomic_primitive_alignment = "64", + target_has_atomic_primitive_alignment = "ptr", target_has_atomic_load_store = "8", target_has_atomic_load_store = "16", target_has_atomic_load_store = "32", @@ -110,6 +110,7 @@ #![feature(offset_of_enum)] #![feature(panic_internals)] #![feature(pattern_type_macro)] +#![feature(sealed)] #![feature(ub_checks)] // tidy-alphabetical-end // @@ -122,14 +123,15 @@ #![feature(auto_traits)] #![feature(cfg_sanitize)] #![feature(cfg_target_has_atomic)] -#![feature(cfg_target_has_atomic_equal_alignment)] #![feature(cfg_ub_checks)] +#![feature(const_closures)] #![feature(const_precise_live_drops)] #![feature(const_trait_impl)] #![feature(decl_macro)] #![feature(deprecated_suggestion)] #![feature(derive_const)] #![feature(diagnostic_on_const)] +#![feature(diagnostic_on_unmatch_args)] #![feature(doc_cfg)] #![feature(doc_notable_trait)] #![feature(extern_types)] @@ -155,6 +157,7 @@ #![feature(no_core)] #![feature(optimize_attribute)] #![feature(pattern_types)] +#![feature(pin_macro_internals)] #![feature(prelude_import)] #![feature(repr_simd)] #![feature(rustc_attrs)] @@ -163,7 +166,6 @@ #![feature(staged_api)] #![feature(stmt_expr_attributes)] #![feature(strict_provenance_lints)] -#![feature(target_feature_inline_always)] #![feature(trait_alias)] #![feature(transparent_unions)] #![feature(try_blocks)] @@ -206,7 +208,7 @@ use prelude::rust_2024::*; #[macro_use] mod macros; -#[stable(feature = "assert_matches", since = "1.95.0")] +#[stable(feature = "assert_matches", since = "1.96.0")] pub use crate::macros::{assert_matches, debug_assert_matches}; #[unstable(feature = "derive_from", issue = "144889")] @@ -216,17 +218,31 @@ pub mod from { pub use crate::macros::builtin::From; } +mod sealed { + /// This trait being unreachable from outside the crate + /// prevents outside implementations of our extension traits. + /// This allows adding more trait methods in the future. + #[unstable(feature = "sealed", issue = "none")] + pub trait Sealed {} +} + // We don't export this through #[macro_export] for now, to avoid breakage. #[unstable(feature = "autodiff", issue = "124509")] -/// Unstable module containing the unstable `autodiff` macro. +#[doc = include_str!("../../core/src/autodiff.md")] pub mod autodiff { #[unstable(feature = "autodiff", issue = "124509")] pub use crate::macros::builtin::{autodiff_forward, autodiff_reverse}; } +#[unstable(feature = "gpu_offload", issue = "131513")] +#[doc = include_str!("../../core/src/offload.md")] +pub mod offload; + #[unstable(feature = "contracts", issue = "128044")] pub mod contracts; +#[unstable(feature = "derive_macro_global_path", issue = "154645")] +pub use crate::macros::builtin::derive; #[stable(feature = "cfg_select", since = "1.95.0")] pub use crate::macros::cfg_select; @@ -294,7 +310,7 @@ pub mod bstr; pub mod cell; pub mod char; pub mod ffi; -#[unstable(feature = "core_io_borrowed_buf", issue = "117693")] +#[unstable(feature = "core_io", issue = "154046")] pub mod io; pub mod iter; pub mod net; @@ -305,6 +321,8 @@ pub mod panicking; #[unstable(feature = "pattern_type_macro", issue = "123646")] pub mod pat; pub mod pin; +#[unstable(feature = "abort_immediate", issue = "154601")] +pub mod process; #[unstable(feature = "random", issue = "130703")] pub mod random; #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] diff --git a/core/src/macros/mod.rs b/core/src/macros/mod.rs index 7f35e94d3df30..c21191dbc19be 100644 --- a/core/src/macros/mod.rs +++ b/core/src/macros/mod.rs @@ -164,11 +164,11 @@ macro_rules! assert_ne { /// assert_matches!(a, Some(x) if x > 100); /// // assert_matches!(a, Some(x) if x < 100); // panics /// ``` -#[stable(feature = "assert_matches", since = "1.95.0")] +#[stable(feature = "assert_matches", since = "1.96.0")] #[allow_internal_unstable(panic_internals)] #[rustc_macro_transparency = "semiopaque"] pub macro assert_matches { - ($left:expr, $(|)? $( $pattern:pat_param )|+ $( if $guard: expr )? $(,)?) => { + ($left:expr, $(|)? $( $pattern:pat_param )|+ $( if $guard: expr )? $(,)?) => {{ match $left { $( $pattern )|+ $( if $guard )? => {} ref left_val => { @@ -179,8 +179,8 @@ pub macro assert_matches { ); } } - }, - ($left:expr, $(|)? $( $pattern:pat_param )|+ $( if $guard: expr )?, $($arg:tt)+) => { + }}, + ($left:expr, $(|)? $( $pattern:pat_param )|+ $( if $guard: expr )?, $($arg:tt)+) => {{ match $left { $( $pattern )|+ $( if $guard )? => {} ref left_val => { @@ -191,7 +191,7 @@ pub macro assert_matches { ); } } - }, + }}, } /// Selects code at compile-time based on `cfg` predicates. @@ -229,6 +229,7 @@ pub macro assert_matches { /// }; /// ``` #[stable(feature = "cfg_select", since = "1.95.0")] +#[doc(alias = "cfg_if", alias = "cfg-if")] #[rustc_diagnostic_item = "cfg_select"] #[rustc_builtin_macro] pub macro cfg_select($($tt:tt)*) { @@ -391,7 +392,7 @@ macro_rules! debug_assert_ne { /// debug_assert_matches!(a, Some(x) if x > 100); /// // debug_assert_matches!(a, Some(x) if x < 100); // panics /// ``` -#[stable(feature = "assert_matches", since = "1.95.0")] +#[stable(feature = "assert_matches", since = "1.96.0")] #[allow_internal_unstable(assert_matches)] #[rustc_macro_transparency = "semiopaque"] pub macro debug_assert_matches($($arg:tt)*) { @@ -1627,6 +1628,48 @@ pub(crate) mod builtin { /* compiler built-in */ } + /// The `offload_kernel` macro is applied to a function to generate two separate + /// definitions: a host-side wrapper for dispatch and a device-side kernel. + /// + /// The macro does not perform the offload itself. It generates the necessary + /// code required by the compiler's offloading infrastructure. + /// + /// ### Usage example: + /// + /// ```rust,ignore (offload requires a -Z flag) + /// #[offload_kernel] + /// fn foo(a: &[f32], b: &[f32], c: *mut f32) { + /// *c = a[0] + b[0]; + /// } + /// ``` + /// + /// This expands to the host-side function: + /// + /// ```rust,ignore (offload requires a -Z flag) + /// #[unsafe(no_mangle)] + /// #[inline(never)] + /// fn foo(_: &[f32], _: &[f32], _: *mut f32) { + /// ::core::panicking::panic("not implemented") + /// } + /// ``` + /// + /// And the device-side kernel: + /// + /// ```rust,ignore (offload requires a -Z flag) + /// #[rustc_offload_kernel] + /// #[unsafe(no_mangle)] + /// unsafe extern "gpu-kernel" fn foo(a: &[f32], b: &[f32], c: *mut f32) { + /// *c = a[0] + b[0]; + /// } + /// ``` + #[unstable(feature = "gpu_offload", issue = "131513")] + #[allow_internal_unstable(rustc_attrs)] + #[allow_internal_unstable(core_intrinsics)] + #[rustc_builtin_macro] + pub macro offload_kernel($item:item) { + /* compiler built-in */ + } + /// Asserts that a boolean expression is `true` at runtime. /// /// This will invoke the [`panic!`] macro if the provided expression cannot be @@ -1720,7 +1763,7 @@ pub(crate) mod builtin { /// /// See [the reference] for more info. /// - /// [the reference]: ../../../reference/attributes/derive.html + /// [the reference]: ../reference/attributes/derive.html #[stable(feature = "rust1", since = "1.0.0")] #[rustc_builtin_macro] pub macro derive($item:item) { diff --git a/core/src/marker.rs b/core/src/marker.rs index c79e8fc4060c1..53141aabacc45 100644 --- a/core/src/marker.rs +++ b/core/src/marker.rs @@ -846,7 +846,7 @@ impl Copy for PhantomData {} #[stable(feature = "rust1", since = "1.0.0")] impl Clone for PhantomData { fn clone(&self) -> Self { - Self + *self } } @@ -856,7 +856,7 @@ unsafe impl TrivialClone for PhantomData {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for PhantomData { +const impl Default for PhantomData { fn default() -> Self { Self } @@ -937,6 +937,8 @@ marker_impls! { {T: PointeeSized} *mut T, {T: PointeeSized} &T, {T: PointeeSized} &mut T, + {T: PointeeSized} pattern_type!(*const T is !null), + {T: PointeeSized} pattern_type!(*mut T is !null), } /// Types that do not require any pinning guarantees. @@ -1054,7 +1056,7 @@ marker_impls! { #[unstable(feature = "const_destruct", issue = "133214")] #[rustc_const_unstable(feature = "const_destruct", issue = "133214")] #[lang = "destruct"] -#[rustc_on_unimplemented(message = "can't drop `{Self}`", append_const_msg)] +#[diagnostic::on_unimplemented(message = "can't drop `{Self}`")] #[rustc_deny_explicit_impl] #[rustc_dyn_incompatible_trait] pub const trait Destruct: PointeeSized {} @@ -1088,14 +1090,18 @@ pub trait ConstParamTy_: StructuralPartialEq + Eq {} /// Derive macro generating an impl of the trait `ConstParamTy`. #[rustc_builtin_macro] #[allow_internal_unstable(const_param_ty_trait)] -#[unstable(feature = "adt_const_params", issue = "95174")] +#[unstable(feature = "min_adt_const_params", issue = "154042", implied_by = "adt_const_params")] pub macro ConstParamTy($item:item) { /* compiler built-in */ } +// For `adt_const_params` to be recognized as a feature +#[unstable(feature = "adt_const_params", issue = "95174")] +const _: () = (); + // FIXME(adt_const_params): handle `ty::FnDef`/`ty::Closure` marker_impls! { - #[unstable(feature = "adt_const_params", issue = "95174")] + #[unstable(feature = "min_adt_const_params", issue = "154042")] ConstParamTy_ for usize, u8, u16, u32, u64, u128, isize, i8, i16, i32, i64, i128, @@ -1341,3 +1347,19 @@ pub macro CoercePointee($item:item) { pub trait CoercePointeeValidated { /* compiler built-in */ } + +/// Allows value to be reborrowed as exclusive, creating a copy of the value +/// that disables the source for reads and writes for the lifetime of the copy. +#[lang = "reborrow"] +#[unstable(feature = "reborrow", issue = "145612")] +pub trait Reborrow { + /* compiler built-in */ +} + +/// Allows reborrowable value to be reborrowed as shared, creating a copy +/// that disables the source for writes for the lifetime of the copy. +#[lang = "coerce_shared"] +#[unstable(feature = "reborrow", issue = "145612")] +pub trait CoerceShared: Reborrow { + /* compiler built-in */ +} diff --git a/core/src/mem/alignment.rs b/core/src/mem/alignment.rs index a8c4c8ea78ff7..08ce7fcd55523 100644 --- a/core/src/mem/alignment.rs +++ b/core/src/mem/alignment.rs @@ -178,7 +178,7 @@ impl Alignment { /// Returns the alignment as a [NonZero]<[usize]>. #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[deprecated( - since = "CURRENT_RUSTC_VERSION", + since = "1.96.0", note = "renamed to `as_nonzero_usize`", suggestion = "as_nonzero_usize" )] @@ -265,7 +265,7 @@ impl fmt::Debug for Alignment { #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom> for Alignment { +const impl TryFrom> for Alignment { type Error = num::TryFromIntError; #[inline] @@ -276,18 +276,18 @@ impl const TryFrom> for Alignment { #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const TryFrom for Alignment { +const impl TryFrom for Alignment { type Error = num::TryFromIntError; #[inline] fn try_from(align: usize) -> Result { - Self::new(align).ok_or(num::TryFromIntError(())) + Self::new(align).ok_or(num::TryFromIntError(num::IntErrorKind::NotAPowerOfTwo)) } } #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for NonZero { +const impl From for NonZero { #[inline] fn from(align: Alignment) -> NonZero { align.as_nonzero_usize() @@ -296,7 +296,7 @@ impl const From for NonZero { #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for usize { +const impl From for usize { #[inline] fn from(align: Alignment) -> usize { align.as_usize() @@ -305,7 +305,7 @@ impl const From for usize { #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const cmp::Ord for Alignment { +const impl cmp::Ord for Alignment { #[inline] fn cmp(&self, other: &Self) -> cmp::Ordering { self.as_nonzero_usize().cmp(&other.as_nonzero_usize()) @@ -314,7 +314,7 @@ impl const cmp::Ord for Alignment { #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const cmp::PartialOrd for Alignment { +const impl cmp::PartialOrd for Alignment { #[inline] fn partial_cmp(&self, other: &Self) -> Option { Some(self.cmp(other)) @@ -332,7 +332,7 @@ impl hash::Hash for Alignment { /// Returns [`Alignment::MIN`], which is valid for any type. #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Alignment { +const impl Default for Alignment { fn default() -> Alignment { Alignment::MIN } diff --git a/core/src/mem/drop_guard.rs b/core/src/mem/drop_guard.rs index 74bf353907455..70658f0efb242 100644 --- a/core/src/mem/drop_guard.rs +++ b/core/src/mem/drop_guard.rs @@ -109,7 +109,7 @@ where #[unstable(feature = "drop_guard", issue = "144426")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for DropGuard +const impl Deref for DropGuard where F: FnOnce(T), { @@ -122,7 +122,7 @@ where #[unstable(feature = "drop_guard", issue = "144426")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for DropGuard +const impl DerefMut for DropGuard where F: FnOnce(T), { @@ -133,7 +133,7 @@ where #[unstable(feature = "drop_guard", issue = "144426")] #[rustc_const_unstable(feature = "const_drop_guard", issue = "none")] -impl const Drop for DropGuard +const impl Drop for DropGuard where F: [const] FnOnce(T), { diff --git a/core/src/mem/manually_drop.rs b/core/src/mem/manually_drop.rs index ca008a82ee6f0..4616c3dc4a373 100644 --- a/core/src/mem/manually_drop.rs +++ b/core/src/mem/manually_drop.rs @@ -270,7 +270,7 @@ impl ManuallyDrop { #[stable(feature = "manually_drop", since = "1.20.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for ManuallyDrop { +const impl Deref for ManuallyDrop { type Target = T; #[inline(always)] fn deref(&self) -> &T { @@ -280,7 +280,7 @@ impl const Deref for ManuallyDrop { #[stable(feature = "manually_drop", since = "1.20.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for ManuallyDrop { +const impl DerefMut for ManuallyDrop { #[inline(always)] fn deref_mut(&mut self) -> &mut T { self.value.as_mut() diff --git a/core/src/mem/maybe_dangling.rs b/core/src/mem/maybe_dangling.rs index c85576b5778cc..2c9c435c24085 100644 --- a/core/src/mem/maybe_dangling.rs +++ b/core/src/mem/maybe_dangling.rs @@ -1,5 +1,6 @@ #![unstable(feature = "maybe_dangling", issue = "118166")] +use crate::marker::StructuralPartialEq; use crate::{mem, ptr}; /// Allows wrapped [references] and [boxes] to dangle. @@ -109,3 +110,5 @@ impl MaybeDangling

{ x } } + +impl StructuralPartialEq for MaybeDangling {} diff --git a/core/src/mem/mod.rs b/core/src/mem/mod.rs index a987970c9bcc3..62c612e7ba2a6 100644 --- a/core/src/mem/mod.rs +++ b/core/src/mem/mod.rs @@ -32,6 +32,7 @@ use crate::alloc::Layout; use crate::clone::TrivialClone; +use crate::cmp::Ordering; use crate::marker::{Destruct, DiscriminantKind}; use crate::panic::const_assert; use crate::{clone, cmp, fmt, hash, intrinsics, ptr}; @@ -1088,6 +1089,102 @@ pub const unsafe fn transmute_copy(src: &Src) -> Dst { } } +/// Like [`transmute`], but only initializes the "common prefix" of the first +/// `min(size_of::(), size_of::())` bytes of the destination from the +/// corresponding bytes of the source. +/// +/// This is equivalent to a "union cast" through a `union` with `#[repr(C)]`. +/// +/// That means some size mismatches are not UB, like `[T; 2]` to `[T; 1]`. +/// Increasing size is usually UB from being insufficiently initialized -- like +/// `u8` to `u32` -- but isn't always. For example, going from `u8` to +/// `#[repr(C, align(4))] AlignedU8(u8);` is sound. +/// +/// Prefer normal `transmute` where possible, for the extra checking, since +/// both do exactly the same thing at runtime, if they both compile. +/// +/// # Safety +/// +/// If `size_of::() >= size_of::()`, the first `size_of::()` bytes +/// of `src` must be be *valid* when interpreted as a `Dst`. (In this case, the +/// preconditions are the same as for `transmute_copy(&ManuallyDrop::new(src))`.) +/// +/// If `size_of::() <= size_of::()`, the bytes of `src` padded with +/// uninitialized bytes afterwards up to a total size of `size_of::()` +/// must be *valid* when interpreted as a `Dst`. +/// +/// In both cases, any safety preconditions of the `Dst` type must also be upheld. +/// +/// # Examples +/// +/// ``` +/// #![feature(transmute_prefix)] +/// use std::mem::transmute_prefix; +/// +/// assert_eq!(unsafe { transmute_prefix::<[i32; 4], [i32; 2]>([1, 2, 3, 4]) }, [1, 2]); +/// +/// let expected = if cfg!(target_endian = "little") { 0x34 } else { 0x12 }; +/// assert_eq!(unsafe { transmute_prefix::(0x1234) }, expected); +/// +/// // Would be UB because the destination is incompletely initialized. +/// // transmute_prefix::(123) +/// +/// // OK because the destination is allowed to be partially initialized. +/// let _: std::mem::MaybeUninit = unsafe { transmute_prefix(123_u8) }; +/// ``` +#[unstable(feature = "transmute_prefix", issue = "155079")] +pub const unsafe fn transmute_prefix(src: Src) -> Dst { + #[repr(C)] + union Transmute { + a: ManuallyDrop, + b: ManuallyDrop, + } + + match const { Ord::cmp(&Src::SIZE, &Dst::SIZE) } { + // SAFETY: When Dst is bigger, the union is the size of Dst + Ordering::Less => unsafe { + let a = transmute_neo(src); + intrinsics::transmute_unchecked(Transmute:: { a }) + }, + // SAFETY: When they're the same size, we can use the MIR primitive + Ordering::Equal => unsafe { intrinsics::transmute_unchecked::(src) }, + // SAFETY: When Src is bigger, the union is the size of Src + Ordering::Greater => unsafe { + let u: Transmute = intrinsics::transmute_unchecked(src); + transmute_neo(u.b) + }, + } +} + +/// New version of `transmute`, exposed under this name so it can be iterated upon +/// without risking breakage to uses of "real" transmute. +/// +/// It will not be stabilized under this name. +/// +/// # Examples +/// +/// ``` +/// #![feature(transmute_neo)] +/// use std::mem::transmute_neo; +/// +/// assert_eq!(unsafe { transmute_neo::(0.0) }, 0); +/// ``` +/// +/// ```compile_fail,E0080 +/// #![feature(transmute_neo)] +/// use std::mem::transmute_neo; +/// +/// unsafe { transmute_neo::(123) }; +/// ``` +#[unstable(feature = "transmute_neo", issue = "155079")] +pub const unsafe fn transmute_neo(src: Src) -> Dst { + const { assert!(Src::SIZE == Dst::SIZE) }; + + // SAFETY: the const-assert just checked that they're the same size, + // and any other safety invariants need to be upheld by the caller. + unsafe { intrinsics::transmute_unchecked(src) } +} + /// Opaque type representing the discriminant of an enum. /// /// See the [`discriminant`] function in this module for more information. @@ -1470,6 +1567,10 @@ impl SizedTypeProperties for T {} /// [`offset_of_enum`]: https://doc.rust-lang.org/nightly/unstable-book/language-features/offset-of-enum.html /// [`offset_of_slice`]: https://doc.rust-lang.org/nightly/unstable-book/language-features/offset-of-slice.html #[stable(feature = "offset_of", since = "1.77.0")] +#[diagnostic::on_unmatch_args( + note = "this macro expects a container type and a (nested) field path, like `offset_of!(Type, field)`" +)] +#[doc(alias = "memoffset")] #[allow_internal_unstable(builtin_syntax, core_intrinsics)] pub macro offset_of($Container:ty, $($fields:expr)+ $(,)?) { // The `{}` is for better error messages @@ -1519,7 +1620,7 @@ pub macro offset_of($Container:ty, $($fields:expr)+ $(,)?) { #[rustc_const_unstable(feature = "mem_conjure_zst", issue = "95383")] pub const unsafe fn conjure_zst() -> T { const_assert!( - size_of::() == 0, + T::IS_ZST, "mem::conjure_zst invoked on a non-zero-sized type", "mem::conjure_zst invoked on type {name}, which is not zero-sized", name: &str = crate::any::type_name::() diff --git a/core/src/mem/type_info.rs b/core/src/mem/type_info.rs index e4d47dedb8606..8e7e51caad1f1 100644 --- a/core/src/mem/type_info.rs +++ b/core/src/mem/type_info.rs @@ -2,7 +2,8 @@ //! runtime or const-eval processable way. use crate::any::TypeId; -use crate::intrinsics::{type_id, type_of}; +use crate::fmt; +use crate::intrinsics::{self, type_id, type_of}; use crate::marker::PointeeSized; use crate::ptr::DynMetadata; @@ -14,8 +15,6 @@ use crate::ptr::DynMetadata; pub struct Type { /// Per-type information pub kind: TypeKind, - /// Size of the type. `None` if it is unsized - pub size: Option, } /// Info of a trait implementation, you can retrieve the vtable with [Self::get_vtable] @@ -360,3 +359,219 @@ pub enum Abi { /// C-calling convention ExternC, } + +impl TypeId { + /// Returns the size of the type represented by this `TypeId`. `None` if it is unsized. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// assert_eq!(const { TypeId::of::().size() }, Some(4)); + /// assert_eq!(const { TypeId::of::<[u8; 16]>().size() }, Some(16)); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn size(self) -> Option { + intrinsics::size_of_type_id(self) + } + + /// Returns the number of variants of the type represented by this `TypeId`. + /// + /// For enums, this is the number of variants. For structs and unions, this is always 1. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// assert_eq!(const { TypeId::of::>().variants() }, 2); + /// + /// struct Unit; + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!(const { TypeId::of::().variants() }, 1); + /// assert_eq!(const { TypeId::of::().variants() }, 1); + /// assert_eq!(const { TypeId::of::<(f32, f32)>().variants() }, 1); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn variants(self) -> usize { + intrinsics::type_id_variants(self) + } + + /// Returns the number of fields at the given `variant_index` of the type represented by this `TypeId`. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// assert_eq!(const { TypeId::of::().fields(0) }, 0); + /// + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!(const { TypeId::of::().fields(0) }, 2); + /// + /// enum Enum { + /// Unit, + /// Tuple(u32, u64), + /// Struct { x: u32, y: u32, z: String }, + /// } + /// assert_eq!(const { TypeId::of::().fields(0) }, 0); + /// assert_eq!(const { TypeId::of::().fields(1) }, 2); + /// assert_eq!(const { TypeId::of::().fields(2) }, 3); + /// ``` + /// + /// The variant index refers to the source order index of a variant in a type. + /// + /// For enums, these are always `0..variant_count`, regardless of any custom discriminants that may have been defined. + /// `struct`s, `tuples`, and `unions`s are considered to have a single variant with variant index zero. + /// + /// ``` + /// enum Number { + /// Seven = 7, // variant index == 0 + /// Six = 6, // variant index == 1 + /// } + /// ``` + /// + /// Out-of-bounds indexing will be treated as a compile-time error. + /// + /// ```compile_fail,E0080 + /// # #![feature(type_info)] + /// # use std::any::TypeId; + /// # + /// # struct Point { + /// # x: u32, + /// # y: u32, + /// # } + /// # enum Enum { + /// # Unit, + /// # Tuple(u32, u64), + /// # Struct { x: u32, y: u32, z: String }, + /// # } + /// const { + /// _ = TypeId::of::().fields(10); // error: indexing out of bounds: the len is 2 but the index is 10 + /// _ = TypeId::of::().fields(10); // error: indexing out of bounds: the len is 3 but the index is 10 + /// } + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn fields(self, variant_index: usize) -> usize { + intrinsics::type_id_fields(self, variant_index) + } + + /// Returns the field representing type at the given index of the type represented by this `TypeId`. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!(const { TypeId::of::().field(0, 0).type_id() }, TypeId::of::()); + /// assert_eq!(const { TypeId::of::().field(0, 1).type_id() }, TypeId::of::()); + /// + /// enum Enum { + /// Unit, + /// Tuple(u32, u64), + /// Struct { x: u32, y: u32, z: String }, + /// } + /// assert_eq!(const { TypeId::of::().field(1, 0).type_id() }, TypeId::of::()); + /// assert_eq!(const { TypeId::of::().field(2, 2).type_id() }, TypeId::of::()); + /// ``` + /// + /// The variant index and field index refer to the source order index of a variant in a type and + /// the source order index of a field in a variant, respectively. + /// + /// For enums, variant indexes are always `0..variant_count`, regardless of any custom discriminants that may have been defined. + /// `struct`s, `tuples`, and `unions`s are considered to have a single variant with variant index zero. + /// + /// As for field indexes, they may not be the same as the layout order for `repr(Rust)` types, but they are for `repr(C)` types. + /// + /// ``` + /// enum Enum { + /// Foo, // variant index == 0 + /// Bar { // variant index == 1 + /// a: (), // field index == 0 in `Bar` + /// b: (), // field index == 1 in `Bar` + /// } + /// } + /// ``` + /// + /// Out-of-bounds indexing will be treated as a compile-time error. + /// + /// ```compile_fail,E0080 + /// # #![feature(type_info)] + /// # use std::any::TypeId; + /// # + /// # struct Point { + /// # x: u32, + /// # y: u32, + /// # } + /// # enum Enum { + /// # Unit, + /// # Tuple(u32, u64), + /// # Struct { x: u32, y: u32, z: String }, + /// # } + /// const { + /// _ = TypeId::of::().field(0, 10); // error: indexing out of bounds: the len is 2 but the index is 10 + /// _ = TypeId::of::().field(2, 10); // error: indexing out of bounds: the len is 3 but the index is 10 + /// } + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn field(self, variant_index: usize, field_index: usize) -> FieldId { + FieldId { + frt_type_id: intrinsics::type_id_field_representing_type( + self, + variant_index, + field_index, + ), + } + } +} + +/// Field representing type ID. Representing a field of a struct, tuple or enum variant. +#[derive(Copy, PartialOrd, Ord, Hash)] +#[derive_const(Clone, PartialEq, Eq)] +#[unstable(feature = "type_info", issue = "146922")] +pub struct FieldId { + frt_type_id: TypeId, +} + +#[unstable(feature = "type_info", issue = "146922")] +impl fmt::Debug for FieldId { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "FieldId({:#034x})", self.frt_type_id.as_u128()) + } +} + +impl FieldId { + /// Returns the `TypeId` of the actual field type. + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::TypeId; + /// + /// struct Point { + /// x: u32, + /// y: u32, + /// } + /// assert_eq!( + /// const { TypeId::of::().field(0, 0).type_id() }, + /// TypeId::of::() + /// ); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn type_id(self) -> TypeId { + intrinsics::field_representing_type_actual_type_id(self.frt_type_id) + } +} diff --git a/core/src/net/ip_addr.rs b/core/src/net/ip_addr.rs index db94f52c4e8d7..f2d91b9cec649 100644 --- a/core/src/net/ip_addr.rs +++ b/core/src/net/ip_addr.rs @@ -1136,7 +1136,7 @@ impl fmt::Debug for IpAddr { #[stable(feature = "ip_from_ip", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for IpAddr { +const impl From for IpAddr { /// Copies this address to a new `IpAddr::V4`. /// /// # Examples @@ -1159,7 +1159,7 @@ impl const From for IpAddr { #[stable(feature = "ip_from_ip", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for IpAddr { +const impl From for IpAddr { /// Copies this address to a new `IpAddr::V6`. /// /// # Examples @@ -1232,7 +1232,7 @@ impl PartialEq for Ipv4Addr { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for Ipv4Addr { +const impl PartialOrd for Ipv4Addr { #[inline] fn partial_cmp(&self, other: &Ipv4Addr) -> Option { Some(self.cmp(other)) @@ -1263,7 +1263,7 @@ impl PartialOrd for Ipv4Addr { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for Ipv4Addr { +const impl Ord for Ipv4Addr { #[inline] fn cmp(&self, other: &Ipv4Addr) -> Ordering { self.octets.cmp(&other.octets) @@ -1272,7 +1272,7 @@ impl const Ord for Ipv4Addr { #[stable(feature = "ip_u32", since = "1.1.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u32 { +const impl From for u32 { /// Uses [`Ipv4Addr::to_bits`] to convert an IPv4 address to a host byte order `u32`. #[inline] fn from(ip: Ipv4Addr) -> u32 { @@ -1282,7 +1282,7 @@ impl const From for u32 { #[stable(feature = "ip_u32", since = "1.1.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Ipv4Addr { +const impl From for Ipv4Addr { /// Uses [`Ipv4Addr::from_bits`] to convert a host byte order `u32` into an IPv4 address. #[inline] fn from(ip: u32) -> Ipv4Addr { @@ -1292,7 +1292,7 @@ impl const From for Ipv4Addr { #[stable(feature = "from_slice_v4", since = "1.9.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u8; 4]> for Ipv4Addr { +const impl From<[u8; 4]> for Ipv4Addr { /// Creates an `Ipv4Addr` from a four element byte array. /// /// # Examples @@ -1311,7 +1311,7 @@ impl const From<[u8; 4]> for Ipv4Addr { #[stable(feature = "ip_from_slice", since = "1.17.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u8; 4]> for IpAddr { +const impl From<[u8; 4]> for IpAddr { /// Creates an `IpAddr::V4` from a four element byte array. /// /// # Examples @@ -2237,7 +2237,7 @@ impl PartialEq for IpAddr { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for Ipv6Addr { +const impl PartialOrd for Ipv6Addr { #[inline] fn partial_cmp(&self, other: &Ipv6Addr) -> Option { Some(self.cmp(other)) @@ -2268,7 +2268,7 @@ impl PartialOrd for Ipv6Addr { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for Ipv6Addr { +const impl Ord for Ipv6Addr { #[inline] fn cmp(&self, other: &Ipv6Addr) -> Ordering { self.segments().cmp(&other.segments()) @@ -2277,7 +2277,7 @@ impl const Ord for Ipv6Addr { #[stable(feature = "i128", since = "1.26.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for u128 { +const impl From for u128 { /// Uses [`Ipv6Addr::to_bits`] to convert an IPv6 address to a host byte order `u128`. #[inline] fn from(ip: Ipv6Addr) -> u128 { @@ -2286,7 +2286,7 @@ impl const From for u128 { } #[stable(feature = "i128", since = "1.26.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Ipv6Addr { +const impl From for Ipv6Addr { /// Uses [`Ipv6Addr::from_bits`] to convert a host byte order `u128` to an IPv6 address. #[inline] fn from(ip: u128) -> Ipv6Addr { @@ -2296,7 +2296,7 @@ impl const From for Ipv6Addr { #[stable(feature = "ipv6_from_octets", since = "1.9.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u8; 16]> for Ipv6Addr { +const impl From<[u8; 16]> for Ipv6Addr { /// Creates an `Ipv6Addr` from a sixteen element byte array. /// /// # Examples @@ -2324,7 +2324,7 @@ impl const From<[u8; 16]> for Ipv6Addr { #[stable(feature = "ipv6_from_segments", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u16; 8]> for Ipv6Addr { +const impl From<[u16; 8]> for Ipv6Addr { /// Creates an `Ipv6Addr` from an eight element 16-bit array. /// /// # Examples @@ -2353,7 +2353,7 @@ impl const From<[u16; 8]> for Ipv6Addr { #[stable(feature = "ip_from_slice", since = "1.17.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u8; 16]> for IpAddr { +const impl From<[u8; 16]> for IpAddr { /// Creates an `IpAddr::V6` from a sixteen element byte array. /// /// # Examples @@ -2381,7 +2381,7 @@ impl const From<[u8; 16]> for IpAddr { #[stable(feature = "ip_from_slice", since = "1.17.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<[u16; 8]> for IpAddr { +const impl From<[u16; 8]> for IpAddr { /// Creates an `IpAddr::V6` from an eight element 16-bit array. /// /// # Examples @@ -2409,7 +2409,7 @@ impl const From<[u16; 8]> for IpAddr { #[stable(feature = "ip_bitops", since = "1.75.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for Ipv4Addr { +const impl Not for Ipv4Addr { type Output = Ipv4Addr; #[inline] @@ -2425,7 +2425,7 @@ impl const Not for Ipv4Addr { #[stable(feature = "ip_bitops", since = "1.75.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for &'_ Ipv4Addr { +const impl Not for &'_ Ipv4Addr { type Output = Ipv4Addr; #[inline] @@ -2436,7 +2436,7 @@ impl const Not for &'_ Ipv4Addr { #[stable(feature = "ip_bitops", since = "1.75.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for Ipv6Addr { +const impl Not for Ipv6Addr { type Output = Ipv6Addr; #[inline] @@ -2452,7 +2452,7 @@ impl const Not for Ipv6Addr { #[stable(feature = "ip_bitops", since = "1.75.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for &'_ Ipv6Addr { +const impl Not for &'_ Ipv6Addr { type Output = Ipv6Addr; #[inline] diff --git a/core/src/net/socket_addr.rs b/core/src/net/socket_addr.rs index ccc53c156d3a1..4f126b23f475a 100644 --- a/core/src/net/socket_addr.rs +++ b/core/src/net/socket_addr.rs @@ -593,7 +593,7 @@ impl SocketAddrV6 { #[stable(feature = "ip_from_ip", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for SocketAddr { +const impl From for SocketAddr { /// Converts a [`SocketAddrV4`] into a [`SocketAddr::V4`]. #[inline] fn from(sock4: SocketAddrV4) -> SocketAddr { @@ -603,7 +603,7 @@ impl const From for SocketAddr { #[stable(feature = "ip_from_ip", since = "1.16.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for SocketAddr { +const impl From for SocketAddr { /// Converts a [`SocketAddrV6`] into a [`SocketAddr::V6`]. #[inline] fn from(sock6: SocketAddrV6) -> SocketAddr { @@ -613,7 +613,7 @@ impl const From for SocketAddr { #[stable(feature = "addr_from_into_ip", since = "1.17.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl> const From<(I, u16)> for SocketAddr { +const impl> From<(I, u16)> for SocketAddr { /// Converts a tuple struct (Into<[`IpAddr`]>, `u16`) into a [`SocketAddr`]. /// /// This conversion creates a [`SocketAddr::V4`] for an [`IpAddr::V4`] diff --git a/core/src/num/error.rs b/core/src/num/error.rs index 8a353dc0fbe99..d8d66cfc9b08c 100644 --- a/core/src/num/error.rs +++ b/core/src/num/error.rs @@ -7,7 +7,16 @@ use crate::fmt; /// The error type returned when a checked integral type conversion fails. #[stable(feature = "try_from", since = "1.34.0")] #[derive(Debug, Copy, Clone, PartialEq, Eq)] -pub struct TryFromIntError(pub(crate) ()); +pub struct TryFromIntError(pub(crate) IntErrorKind); + +impl TryFromIntError { + /// Outputs the detailed cause of converting an integer failing. + #[must_use] + #[unstable(feature = "try_from_int_error_kind", issue = "153978")] + pub const fn kind(&self) -> &IntErrorKind { + &self.0 + } +} #[stable(feature = "try_from", since = "1.34.0")] impl fmt::Display for TryFromIntError { @@ -21,7 +30,7 @@ impl Error for TryFromIntError {} #[stable(feature = "try_from", since = "1.34.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for TryFromIntError { +const impl From for TryFromIntError { fn from(x: Infallible) -> TryFromIntError { match x {} } @@ -29,7 +38,7 @@ impl const From for TryFromIntError { #[unstable(feature = "never_type", issue = "35121")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for TryFromIntError { +const impl From for TryFromIntError { #[inline] fn from(never: !) -> TryFromIntError { // Match rather than coerce to make sure that code like @@ -66,7 +75,8 @@ pub struct ParseIntError { pub(super) kind: IntErrorKind, } -/// Enum to store the various types of errors that can cause parsing an integer to fail. +/// Enum to store the various types of errors that can cause parsing or converting an +/// integer to fail. /// /// # Example /// @@ -103,10 +113,19 @@ pub enum IntErrorKind { NegOverflow, /// Value was Zero /// - /// This variant will be emitted when the parsing string has a value of zero, which - /// would be illegal for non-zero types. + /// This variant will be emitted when the parsing string or the converting integer + /// has a value of zero, which would be illegal for non-zero types. #[stable(feature = "int_error_matching", since = "1.55.0")] Zero, + /// Value is not a power of two. + /// + /// This variant will be emitted when converting an integer that is not a power of + /// two. This is required in some cases such as constructing an [`Alignment`]. + /// + /// [`Alignment`]: core::mem::Alignment "mem::Alignment" + #[unstable(feature = "try_from_int_error_kind", issue = "153978")] + // Also, #[unstable(feature = "ptr_alignment_type", issue = "102070")] + NotAPowerOfTwo, } impl ParseIntError { @@ -128,6 +147,7 @@ impl fmt::Display for ParseIntError { IntErrorKind::PosOverflow => "number too large to fit in target type", IntErrorKind::NegOverflow => "number too small to fit in target type", IntErrorKind::Zero => "number would be zero for non-zero type", + IntErrorKind::NotAPowerOfTwo => "number is not a power of two", } .fmt(f) } diff --git a/core/src/num/f128.rs b/core/src/num/f128.rs index d833653fdba65..cd1987aa959dd 100644 --- a/core/src/num/f128.rs +++ b/core/src/num/f128.rs @@ -33,6 +33,7 @@ pub mod consts { pub const TAU: f128 = 6.28318530717958647692528676655900576839433879875021164194989_f128; /// The golden ratio (φ) + #[doc(alias = "phi")] #[unstable(feature = "f128", issue = "116909")] pub const GOLDEN_RATIO: f128 = 1.61803398874989484820458683436563811772030917980576286213545_f128; @@ -339,14 +340,78 @@ impl f128 { #[unstable(feature = "float_exact_integer_constants", issue = "152466")] pub const MIN_EXACT_INTEGER: i128 = -Self::MAX_EXACT_INTEGER; - /// Sign bit - pub(crate) const SIGN_MASK: u128 = 0x8000_0000_0000_0000_0000_0000_0000_0000; + /// The mask of the bit used to encode the sign of an [`f128`]. + /// + /// This bit is set when the sign is negative and unset when the sign is + /// positive. + /// If you only need to check whether a value is positive or negative, + /// [`is_sign_positive`] or [`is_sign_negative`] can be used. + /// + /// [`is_sign_positive`]: f128::is_sign_positive + /// [`is_sign_negative`]: f128::is_sign_negative + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f128)] + /// # #[cfg(target_has_reliable_f128)] { + /// let sign_mask = f128::SIGN_MASK; + /// let a = 1.6552f128; + /// let a_bits = a.to_bits(); + /// + /// assert_eq!(a_bits & sign_mask, 0x0); + /// assert_eq!(f128::from_bits(a_bits ^ sign_mask), -a); + /// assert_eq!(sign_mask, (-0.0f128).to_bits()); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const SIGN_MASK: u128 = 0x8000_0000_0000_0000_0000_0000_0000_0000; - /// Exponent mask - pub(crate) const EXP_MASK: u128 = 0x7fff_0000_0000_0000_0000_0000_0000_0000; + /// The mask of the bits used to encode the exponent of an [`f128`]. + /// + /// Note that the exponent is stored as a biased value, with a bias of 16383 for `f128`. + /// + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f128)] + /// # #[cfg(target_has_reliable_f128)] { + /// fn get_exp(a: f128) -> i128 { + /// let bias = 16383; + /// let biased = a.to_bits() & f128::EXPONENT_MASK; + /// (biased >> (f128::MANTISSA_DIGITS - 1)).cast_signed() - bias + /// } + /// + /// assert_eq!(get_exp(0.5), -1); + /// assert_eq!(get_exp(1.0), 0); + /// assert_eq!(get_exp(2.0), 1); + /// assert_eq!(get_exp(4.0), 2); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const EXPONENT_MASK: u128 = 0x7fff_0000_0000_0000_0000_0000_0000_0000; - /// Mantissa mask - pub(crate) const MAN_MASK: u128 = 0x0000_ffff_ffff_ffff_ffff_ffff_ffff_ffff; + /// The mask of the bits used to encode the mantissa of an [`f128`]. + /// + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f128)] + /// # #[cfg(target_has_reliable_f128)] { + /// let mantissa_mask = f128::MANTISSA_MASK; + /// + /// assert_eq!(0f128.to_bits() & mantissa_mask, 0x0); + /// assert_eq!(1f128.to_bits() & mantissa_mask, 0x0); + /// + /// // multiplying a finite value by a power of 2 doesn't change its mantissa + /// // unless the result or initial value is not normal. + /// let a = 1.6552f128; + /// let b = 4.0 * a; + /// assert_eq!(a.to_bits() & mantissa_mask, b.to_bits() & mantissa_mask); + /// + /// // The maximum and minimum values have a saturated significand + /// assert_eq!(f128::MAX.to_bits() & f128::MANTISSA_MASK, f128::MANTISSA_MASK); + /// assert_eq!(f128::MIN.to_bits() & f128::MANTISSA_MASK, f128::MANTISSA_MASK); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const MANTISSA_MASK: u128 = 0x0000_ffff_ffff_ffff_ffff_ffff_ffff_ffff; /// Minimum representable positive value (min subnormal) const TINY_BITS: u128 = 0x1; @@ -508,11 +573,12 @@ impl f128 { /// ``` #[inline] #[unstable(feature = "f128", issue = "116909")] + #[must_use] pub const fn classify(self) -> FpCategory { let bits = self.to_bits(); - match (bits & Self::MAN_MASK, bits & Self::EXP_MASK) { - (0, Self::EXP_MASK) => FpCategory::Infinite, - (_, Self::EXP_MASK) => FpCategory::Nan, + match (bits & Self::MANTISSA_MASK, bits & Self::EXPONENT_MASK) { + (0, Self::EXPONENT_MASK) => FpCategory::Infinite, + (_, Self::EXPONENT_MASK) => FpCategory::Nan, (0, 0) => FpCategory::Zero, (_, 0) => FpCategory::Subnormal, _ => FpCategory::Normal, @@ -608,6 +674,7 @@ impl f128 { #[inline] #[doc(alias = "nextUp")] #[unstable(feature = "f128", issue = "116909")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_up(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -662,6 +729,7 @@ impl f128 { #[inline] #[doc(alias = "nextDown")] #[unstable(feature = "f128", issue = "116909")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_down(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -776,7 +844,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 1.0f128; /// let y = 2.0f128; @@ -807,7 +875,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 1.0f128; /// let y = 2.0f128; @@ -839,7 +907,7 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_minimum_maximum)] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 1.0f128; /// let y = 2.0f128; @@ -871,7 +939,7 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_minimum_maximum)] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 1.0f128; /// let y = 2.0f128; @@ -907,8 +975,10 @@ impl f128 { #[doc(alias = "average")] #[unstable(feature = "f128", issue = "116909")] #[rustc_const_unstable(feature = "f128", issue = "116909")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] pub const fn midpoint(self, other: f128) -> f128 { - const HI: f128 = f128::MAX / 2.; + const HI: f128 = f128::MAX * 0.5; let (a, b) = (self, other); let abs_a = a.abs(); @@ -916,9 +986,9 @@ impl f128 { if abs_a <= HI && abs_b <= HI { // Overflow is impossible - (a + b) / 2. + (a + b) * 0.5 } else { - (a / 2.) + (b / 2.) + (a * 0.5) + (b * 0.5) } } @@ -1551,8 +1621,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.7_f128; /// let g = 3.0_f128; @@ -1580,8 +1649,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.01_f128; /// let g = 4.0_f128; @@ -1609,8 +1677,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.3_f128; /// let g = -3.3_f128; @@ -1643,8 +1710,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.3_f128; /// let g = -3.3_f128; @@ -1675,8 +1741,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let f = 3.7_f128; /// let g = 3.0_f128; @@ -1705,8 +1770,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let x = 3.6_f128; /// let y = -3.6_f128; @@ -1744,8 +1808,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let m = 10.0_f128; /// let x = 4.0_f128; @@ -1789,8 +1852,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let a: f128 = 7.0; /// let b = 4.0; @@ -1833,8 +1895,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let a: f128 = 7.0; /// let b = 4.0; @@ -1876,12 +1937,11 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0_f128; /// let abs_difference = (x.powi(2) - (x * x)).abs(); - /// assert!(abs_difference <= f128::EPSILON); + /// assert!(abs_difference <= 1e-9); /// /// assert_eq!(f128::powi(f128::NAN, 0), 1.0); /// assert_eq!(f128::powi(0.0, 0), 1.0); @@ -1909,8 +1969,7 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f128_math)] { + /// # #[cfg(any(miri, target_has_reliable_f128_math))] { // Miri uses softfloats, always works /// /// let positive = 4.0_f128; /// let negative = -4.0_f128; diff --git a/core/src/num/f16.rs b/core/src/num/f16.rs index b0664abcdc739..ef8eb3c0b57a0 100644 --- a/core/src/num/f16.rs +++ b/core/src/num/f16.rs @@ -35,6 +35,7 @@ pub mod consts { pub const TAU: f16 = 6.28318530717958647692528676655900577_f16; /// The golden ratio (φ) + #[doc(alias = "phi")] #[unstable(feature = "f16", issue = "116909")] pub const GOLDEN_RATIO: f16 = 1.618033988749894848204586834365638118_f16; @@ -333,14 +334,80 @@ impl f16 { #[unstable(feature = "float_exact_integer_constants", issue = "152466")] pub const MIN_EXACT_INTEGER: i16 = -Self::MAX_EXACT_INTEGER; - /// Sign bit - pub(crate) const SIGN_MASK: u16 = 0x8000; + /// The mask of the bit used to encode the sign of an [`f16`]. + /// + /// This bit is set when the sign is negative and unset when the sign is + /// positive. + /// If you only need to check whether a value is positive or negative, + /// [`is_sign_positive`] or [`is_sign_negative`] can be used. + /// + /// [`is_sign_positive`]: f16::is_sign_positive + /// [`is_sign_negative`]: f16::is_sign_negative + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f16)] + /// # #[cfg(target_has_reliable_f16)] { + /// let sign_mask = f16::SIGN_MASK; + /// let a = 1.6552f16; + /// let a_bits = a.to_bits(); + /// + /// assert_eq!(a_bits & sign_mask, 0x0); + /// assert_eq!(f16::from_bits(a_bits ^ sign_mask), -a); + /// assert_eq!(sign_mask, (-0.0f16).to_bits()); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const SIGN_MASK: u16 = 0x8000; - /// Exponent mask - pub(crate) const EXP_MASK: u16 = 0x7c00; + /// The mask of the bits used to encode the exponent of an [`f16`]. + /// + /// Note that the exponent is stored as a biased value, with a bias of 15 for `f16`. + /// + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f16)] + /// # #[cfg(target_has_reliable_f16)] { + /// let exponent_mask = f16::EXPONENT_MASK; + /// + /// fn get_exp(a: f16) -> i16 { + /// let bias = 15; + /// let biased = a.to_bits() & f16::EXPONENT_MASK; + /// (biased >> (f16::MANTISSA_DIGITS - 1)).cast_signed() - bias + /// } + /// + /// assert_eq!(get_exp(0.5), -1); + /// assert_eq!(get_exp(1.0), 0); + /// assert_eq!(get_exp(2.0), 1); + /// assert_eq!(get_exp(4.0), 2); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const EXPONENT_MASK: u16 = 0x7c00; - /// Mantissa mask - pub(crate) const MAN_MASK: u16 = 0x03ff; + /// The mask of the bits used to encode the mantissa of an [`f16`]. + /// + /// ```rust + /// #![feature(float_masks)] + /// #![feature(f16)] + /// # #[cfg(target_has_reliable_f16)] { + /// let mantissa_mask = f16::MANTISSA_MASK; + /// + /// assert_eq!(0f16.to_bits() & mantissa_mask, 0x0); + /// assert_eq!(1f16.to_bits() & mantissa_mask, 0x0); + /// + /// // multiplying a finite value by a power of 2 doesn't change its mantissa + /// // unless the result or initial value is not normal. + /// let a = 1.6552f16; + /// let b = 4.0 * a; + /// assert_eq!(a.to_bits() & mantissa_mask, b.to_bits() & mantissa_mask); + /// + /// // The maximum and minimum values have a saturated significand + /// assert_eq!(f16::MAX.to_bits() & f16::MANTISSA_MASK, f16::MANTISSA_MASK); + /// assert_eq!(f16::MIN.to_bits() & f16::MANTISSA_MASK, f16::MANTISSA_MASK); + /// # } + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const MANTISSA_MASK: u16 = 0x03ff; /// Minimum representable positive value (min subnormal) const TINY_BITS: u16 = 0x1; @@ -500,11 +567,12 @@ impl f16 { /// ``` #[inline] #[unstable(feature = "f16", issue = "116909")] + #[must_use] pub const fn classify(self) -> FpCategory { let b = self.to_bits(); - match (b & Self::MAN_MASK, b & Self::EXP_MASK) { - (0, Self::EXP_MASK) => FpCategory::Infinite, - (_, Self::EXP_MASK) => FpCategory::Nan, + match (b & Self::MANTISSA_MASK, b & Self::EXPONENT_MASK) { + (0, Self::EXPONENT_MASK) => FpCategory::Infinite, + (_, Self::EXPONENT_MASK) => FpCategory::Nan, (0, 0) => FpCategory::Zero, (_, 0) => FpCategory::Subnormal, _ => FpCategory::Normal, @@ -604,6 +672,7 @@ impl f16 { #[inline] #[doc(alias = "nextUp")] #[unstable(feature = "f16", issue = "116909")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_up(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -658,6 +727,7 @@ impl f16 { #[inline] #[doc(alias = "nextDown")] #[unstable(feature = "f16", issue = "116909")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_down(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -901,8 +971,10 @@ impl f16 { #[doc(alias = "average")] #[unstable(feature = "f16", issue = "116909")] #[rustc_const_unstable(feature = "f16", issue = "116909")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] pub const fn midpoint(self, other: f16) -> f16 { - const HI: f16 = f16::MAX / 2.; + const HI: f16 = f16::MAX * 0.5; let (a, b) = (self, other); let abs_a = a.abs(); @@ -910,9 +982,9 @@ impl f16 { if abs_a <= HI && abs_b <= HI { // Overflow is impossible - (a + b) / 2. + (a + b) * 0.5 } else { - (a / 2.) + (b / 2.) + (a * 0.5) + (b * 0.5) } } @@ -1377,7 +1449,7 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(target_has_reliable_f16_math)] { + /// # #[cfg(target_has_reliable_f16)] { /// /// let x = 3.5_f16; /// let y = -3.5_f16; @@ -1442,7 +1514,7 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(target_has_reliable_f16_math)] { + /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.5_f16; /// @@ -1535,7 +1607,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.7_f16; @@ -1564,7 +1635,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.01_f16; @@ -1593,7 +1663,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.3_f16; @@ -1627,7 +1696,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.3_f16; @@ -1659,7 +1727,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let f = 3.7_f16; @@ -1689,7 +1756,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let x = 3.6_f16; @@ -1728,7 +1794,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let m = 10.0_f16; @@ -1773,7 +1838,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let a: f16 = 7.0; @@ -1817,7 +1881,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let a: f16 = 7.0; @@ -1860,12 +1923,11 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] - /// # #[cfg(target_has_reliable_f16)] { + /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0_f16; /// let abs_difference = (x.powi(2) - (x * x)).abs(); - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 0.1); /// /// assert_eq!(f16::powi(f16::NAN, 0), 1.0); /// assert_eq!(f16::powi(0.0, 0), 1.0); @@ -1893,7 +1955,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let positive = 4.0_f16; @@ -1928,7 +1989,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16)] { /// /// let x = 8.0f16; diff --git a/core/src/num/f32.rs b/core/src/num/f32.rs index b85bd2b271588..2a7506f198589 100644 --- a/core/src/num/f32.rs +++ b/core/src/num/f32.rs @@ -292,6 +292,7 @@ pub mod consts { pub const TAU: f32 = 6.28318530717958647692528676655900577_f32; /// The golden ratio (φ) + #[doc(alias = "phi")] #[stable(feature = "euler_gamma_golden_ratio", since = "1.94.0")] pub const GOLDEN_RATIO: f32 = 1.618033988749894848204586834365638118_f32; @@ -572,14 +573,69 @@ impl f32 { #[unstable(feature = "float_exact_integer_constants", issue = "152466")] pub const MIN_EXACT_INTEGER: i32 = -Self::MAX_EXACT_INTEGER; - /// Sign bit - pub(crate) const SIGN_MASK: u32 = 0x8000_0000; + /// The mask of the bit used to encode the sign of an [`f32`]. + /// + /// This bit is set when the sign is negative and unset when the sign is + /// positive. + /// If you only need to check whether a value is positive or negative, + /// [`is_sign_positive`] or [`is_sign_negative`] can be used. + /// + /// [`is_sign_positive`]: f32::is_sign_positive + /// [`is_sign_negative`]: f32::is_sign_negative + /// ```rust + /// #![feature(float_masks)] + /// let sign_mask = f32::SIGN_MASK; + /// let a = 1.6552f32; + /// let a_bits = a.to_bits(); + /// + /// assert_eq!(a_bits & sign_mask, 0x0); + /// assert_eq!(f32::from_bits(a_bits ^ sign_mask), -a); + /// assert_eq!(sign_mask, (-0.0f32).to_bits()); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const SIGN_MASK: u32 = 0x8000_0000; - /// Exponent mask - pub(crate) const EXP_MASK: u32 = 0x7f80_0000; + /// The mask of the bits used to encode the exponent of an [`f32`]. + /// + /// Note that the exponent is stored as a biased value, with a bias of 127 for `f32`. + /// + /// ```rust + /// #![feature(float_masks)] + /// fn get_exp(a: f32) -> i32 { + /// let bias = 127; + /// let biased = a.to_bits() & f32::EXPONENT_MASK; + /// (biased >> (f32::MANTISSA_DIGITS - 1)).cast_signed() - bias + /// } + /// + /// assert_eq!(get_exp(0.5), -1); + /// assert_eq!(get_exp(1.0), 0); + /// assert_eq!(get_exp(2.0), 1); + /// assert_eq!(get_exp(4.0), 2); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const EXPONENT_MASK: u32 = 0x7f80_0000; - /// Mantissa mask - pub(crate) const MAN_MASK: u32 = 0x007f_ffff; + /// The mask of the bits used to encode the mantissa of an [`f32`]. + /// + /// ```rust + /// #![feature(float_masks)] + /// let mantissa_mask = f32::MANTISSA_MASK; + /// + /// assert_eq!(0f32.to_bits() & mantissa_mask, 0x0); + /// assert_eq!(1f32.to_bits() & mantissa_mask, 0x0); + /// + /// // multiplying a finite value by a power of 2 doesn't change its mantissa + /// // unless the result or initial value is not normal. + /// let a = 1.6552f32; + /// let b = 4.0 * a; + /// assert_eq!(a.to_bits() & mantissa_mask, b.to_bits() & mantissa_mask); + /// + /// // The maximum and minimum values have a saturated significand + /// assert_eq!(f32::MAX.to_bits() & f32::MANTISSA_MASK, f32::MANTISSA_MASK); + /// assert_eq!(f32::MIN.to_bits() & f32::MANTISSA_MASK, f32::MANTISSA_MASK); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const MANTISSA_MASK: u32 = 0x007f_ffff; /// Minimum representable positive value (min subnormal) const TINY_BITS: u32 = 0x1; @@ -723,6 +779,7 @@ impl f32 { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_float_classify", since = "1.83.0")] + #[must_use] pub const fn classify(self) -> FpCategory { // We used to have complicated logic here that avoids the simple bit-based tests to work // around buggy codegen for x87 targets (see @@ -730,9 +787,9 @@ impl f32 { // of our tests is able to find any difference between the complicated and the naive // version, so now we are back to the naive version. let b = self.to_bits(); - match (b & Self::MAN_MASK, b & Self::EXP_MASK) { - (0, Self::EXP_MASK) => FpCategory::Infinite, - (_, Self::EXP_MASK) => FpCategory::Nan, + match (b & Self::MANTISSA_MASK, b & Self::EXPONENT_MASK) { + (0, Self::EXPONENT_MASK) => FpCategory::Infinite, + (_, Self::EXPONENT_MASK) => FpCategory::Nan, (0, 0) => FpCategory::Zero, (_, 0) => FpCategory::Subnormal, _ => FpCategory::Normal, @@ -822,6 +879,7 @@ impl f32 { #[doc(alias = "nextUp")] #[stable(feature = "float_next_up_down", since = "1.86.0")] #[rustc_const_stable(feature = "float_next_up_down", since = "1.86.0")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_up(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -873,6 +931,7 @@ impl f32 { #[doc(alias = "nextDown")] #[stable(feature = "float_next_up_down", since = "1.86.0")] #[rustc_const_stable(feature = "float_next_up_down", since = "1.86.0")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_down(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -1089,6 +1148,8 @@ impl f32 { #[doc(alias = "average")] #[stable(feature = "num_midpoint", since = "1.85.0")] #[rustc_const_stable(feature = "num_midpoint", since = "1.85.0")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] pub const fn midpoint(self, other: f32) -> f32 { cfg_select! { // Allow faster implementation that have known good 64-bit float @@ -1104,10 +1165,10 @@ impl f32 { target_arch = "wasm32", target_arch = "wasm64", ) => { - ((self as f64 + other as f64) / 2.0) as f32 + ((self as f64 + other as f64) * 0.5) as f32 } _ => { - const HI: f32 = f32::MAX / 2.; + const HI: f32 = f32::MAX * 0.5; let (a, b) = (self, other); let abs_a = a.abs(); @@ -1115,9 +1176,9 @@ impl f32 { if abs_a <= HI && abs_b <= HI { // Overflow is impossible - (a + b) / 2. + (a + b) * 0.5 } else { - (a / 2.) + (b / 2.) + (a * 0.5) + (b * 0.5) } } } diff --git a/core/src/num/f64.rs b/core/src/num/f64.rs index 3e7c1e792ace6..8b77a3b7b0bde 100644 --- a/core/src/num/f64.rs +++ b/core/src/num/f64.rs @@ -292,6 +292,7 @@ pub mod consts { pub const TAU: f64 = 6.28318530717958647692528676655900577_f64; /// The golden ratio (φ) + #[doc(alias = "phi")] #[stable(feature = "euler_gamma_golden_ratio", since = "1.94.0")] pub const GOLDEN_RATIO: f64 = 1.618033988749894848204586834365638118_f64; @@ -571,14 +572,69 @@ impl f64 { #[unstable(feature = "float_exact_integer_constants", issue = "152466")] pub const MIN_EXACT_INTEGER: i64 = -Self::MAX_EXACT_INTEGER; - /// Sign bit - pub(crate) const SIGN_MASK: u64 = 0x8000_0000_0000_0000; + /// The mask of the bit used to encode the sign of an [`f64`]. + /// + /// This bit is set when the sign is negative and unset when the sign is + /// positive. + /// If you only need to check whether a value is positive or negative, + /// [`is_sign_positive`] or [`is_sign_negative`] can be used. + /// + /// [`is_sign_positive`]: f64::is_sign_positive + /// [`is_sign_negative`]: f64::is_sign_negative + /// ```rust + /// #![feature(float_masks)] + /// let sign_mask = f64::SIGN_MASK; + /// let a = 1.6552f64; + /// let a_bits = a.to_bits(); + /// + /// assert_eq!(a_bits & sign_mask, 0x0); + /// assert_eq!(f64::from_bits(a_bits ^ sign_mask), -a); + /// assert_eq!(sign_mask, (-0.0f64).to_bits()); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const SIGN_MASK: u64 = 0x8000_0000_0000_0000; - /// Exponent mask - pub(crate) const EXP_MASK: u64 = 0x7ff0_0000_0000_0000; + /// The mask of the bits used to encode the exponent of an [`f64`]. + /// + /// Note that the exponent is stored as a biased value, with a bias of 1024 for `f64`. + /// + /// ```rust + /// #![feature(float_masks)] + /// fn get_exp(a: f64) -> i64 { + /// let bias = 1023; + /// let biased = a.to_bits() & f64::EXPONENT_MASK; + /// (biased >> (f64::MANTISSA_DIGITS - 1)).cast_signed() - bias + /// } + /// + /// assert_eq!(get_exp(0.5), -1); + /// assert_eq!(get_exp(1.0), 0); + /// assert_eq!(get_exp(2.0), 1); + /// assert_eq!(get_exp(4.0), 2); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const EXPONENT_MASK: u64 = 0x7ff0_0000_0000_0000; - /// Mantissa mask - pub(crate) const MAN_MASK: u64 = 0x000f_ffff_ffff_ffff; + /// The mask of the bits used to encode the mantissa of an [`f64`]. + /// + /// ```rust + /// #![feature(float_masks)] + /// let mantissa_mask = f64::MANTISSA_MASK; + /// + /// assert_eq!(0f64.to_bits() & mantissa_mask, 0x0); + /// assert_eq!(1f64.to_bits() & mantissa_mask, 0x0); + /// + /// // multiplying a finite value by a power of 2 doesn't change its mantissa + /// // unless the result or initial value is not normal. + /// let a = 1.6552f64; + /// let b = 4.0 * a; + /// assert_eq!(a.to_bits() & mantissa_mask, b.to_bits() & mantissa_mask); + /// + /// // The maximum and minimum values have a saturated significand + /// assert_eq!(f64::MAX.to_bits() & f64::MANTISSA_MASK, f64::MANTISSA_MASK); + /// assert_eq!(f64::MIN.to_bits() & f64::MANTISSA_MASK, f64::MANTISSA_MASK); + /// ``` + #[unstable(feature = "float_masks", issue = "154064")] + pub const MANTISSA_MASK: u64 = 0x000f_ffff_ffff_ffff; /// Minimum representable positive value (min subnormal) const TINY_BITS: u64 = 0x1; @@ -722,6 +778,7 @@ impl f64 { /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_float_classify", since = "1.83.0")] + #[must_use] pub const fn classify(self) -> FpCategory { // We used to have complicated logic here that avoids the simple bit-based tests to work // around buggy codegen for x87 targets (see @@ -729,9 +786,9 @@ impl f64 { // of our tests is able to find any difference between the complicated and the naive // version, so now we are back to the naive version. let b = self.to_bits(); - match (b & Self::MAN_MASK, b & Self::EXP_MASK) { - (0, Self::EXP_MASK) => FpCategory::Infinite, - (_, Self::EXP_MASK) => FpCategory::Nan, + match (b & Self::MANTISSA_MASK, b & Self::EXPONENT_MASK) { + (0, Self::EXPONENT_MASK) => FpCategory::Infinite, + (_, Self::EXPONENT_MASK) => FpCategory::Nan, (0, 0) => FpCategory::Zero, (_, 0) => FpCategory::Subnormal, _ => FpCategory::Normal, @@ -763,15 +820,6 @@ impl f64 { !self.is_sign_negative() } - #[must_use] - #[stable(feature = "rust1", since = "1.0.0")] - #[deprecated(since = "1.0.0", note = "renamed to is_sign_positive")] - #[inline] - #[doc(hidden)] - pub fn is_positive(self) -> bool { - self.is_sign_positive() - } - /// Returns `true` if `self` has a negative sign, including `-0.0`, NaNs with /// negative sign bit and negative infinity. /// @@ -799,15 +847,6 @@ impl f64 { self.to_bits() & Self::SIGN_MASK != 0 } - #[must_use] - #[stable(feature = "rust1", since = "1.0.0")] - #[deprecated(since = "1.0.0", note = "renamed to is_sign_negative")] - #[inline] - #[doc(hidden)] - pub fn is_negative(self) -> bool { - self.is_sign_negative() - } - /// Returns the least number greater than `self`. /// /// Let `TINY` be the smallest representable positive `f64`. Then, @@ -839,6 +878,7 @@ impl f64 { #[doc(alias = "nextUp")] #[stable(feature = "float_next_up_down", since = "1.86.0")] #[rustc_const_stable(feature = "float_next_up_down", since = "1.86.0")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_up(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -890,6 +930,7 @@ impl f64 { #[doc(alias = "nextDown")] #[stable(feature = "float_next_up_down", since = "1.86.0")] #[rustc_const_stable(feature = "float_next_up_down", since = "1.86.0")] + #[must_use = "method returns a new number and does not mutate the original value"] pub const fn next_down(self) -> Self { // Some targets violate Rust's assumption of IEEE semantics, e.g. by flushing // denormals to zero. This is in general unsound and unsupported, but here @@ -1107,8 +1148,10 @@ impl f64 { #[doc(alias = "average")] #[stable(feature = "num_midpoint", since = "1.85.0")] #[rustc_const_stable(feature = "num_midpoint", since = "1.85.0")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] pub const fn midpoint(self, other: f64) -> f64 { - const HI: f64 = f64::MAX / 2.; + const HI: f64 = f64::MAX * 0.5; let (a, b) = (self, other); let abs_a = a.abs(); @@ -1116,9 +1159,9 @@ impl f64 { if abs_a <= HI && abs_b <= HI { // Overflow is impossible - (a + b) / 2. + (a + b) * 0.5 } else { - (a / 2.) + (b / 2.) + (a * 0.5) + (b * 0.5) } } diff --git a/core/src/num/imp/diy_float.rs b/core/src/num/imp/diy_float.rs index e054e7f3f10a7..439b74b31a78b 100644 --- a/core/src/num/imp/diy_float.rs +++ b/core/src/num/imp/diy_float.rs @@ -22,7 +22,7 @@ pub struct Fp { impl Fp { /// Returns a correctly rounded product of itself and `other`. pub fn mul(self, other: Self) -> Self { - let (lo, hi) = self.f.widening_mul(other.f); + let (lo, hi) = self.f.carrying_mul(other.f, 0); let f = hi + (lo >> 63) /* round */; let e = self.e + other.e + 64; Self { f, e } diff --git a/core/src/num/imp/flt2dec/mod.rs b/core/src/num/imp/flt2dec/mod.rs index e79a00a865969..cf895b3e89e66 100644 --- a/core/src/num/imp/flt2dec/mod.rs +++ b/core/src/num/imp/flt2dec/mod.rs @@ -244,18 +244,21 @@ fn digits_to_dec_str<'a>( } /// Formats the given decimal digits `0.<...buf...> * 10^exp` into the exponential -/// form with at least the given number of significant digits. When `upper` is `true`, +/// form with at least the given number of fractional digits. When `upper` is `true`, /// the exponent will be prefixed by `E`; otherwise that's `e`. The result is /// stored to the supplied parts array and a slice of written parts is returned. /// -/// `min_digits` can be less than the number of actual significant digits in `buf`; +/// `frac_digits` can be less than the number of actual fractional digits in `buf`; /// it will be ignored and full digits will be printed. It is only used to print -/// additional zeroes after rendered digits. Thus, `min_digits == 0` means that +/// additional zeroes after rendered digits. Thus, `frac_digits == 0` means that /// it will only print the given digits and nothing else. +/// +/// For example, `buf = b"123", exp = 3, frac_digits = 4` yields the parts for +/// `1.2300e2`. fn digits_to_exp_str<'a>( buf: &'a [u8], exp: i16, - min_ndigits: usize, + frac_digits: usize, upper: bool, parts: &'a mut [MaybeUninit>], ) -> &'a [Part<'a>] { @@ -268,12 +271,22 @@ fn digits_to_exp_str<'a>( parts[n] = MaybeUninit::new(Part::Copy(&buf[..1])); n += 1; - if buf.len() > 1 || min_ndigits > 1 { + // The first generated digit becomes the integral digit, anything after that is already part of + // the fractional portion we can emit verbatim. + let actual_frac_digits = buf.len() - 1; + if actual_frac_digits > 0 || frac_digits > 0 { + // Emit a decimal point either when we already have fractional digits or when the requested + // precision needs trailing zeroes after the radix point. parts[n] = MaybeUninit::new(Part::Copy(b".")); - parts[n + 1] = MaybeUninit::new(Part::Copy(&buf[1..])); - n += 2; - if min_ndigits > buf.len() { - parts[n] = MaybeUninit::new(Part::Zero(min_ndigits - buf.len())); + n += 1; + if actual_frac_digits > 0 { + parts[n] = MaybeUninit::new(Part::Copy(&buf[1..])); + n += 1; + } + if frac_digits > actual_frac_digits { + // format_exact exhausted the meaningful digits, so extend the fractional part with + // zeroes up to the requested precision. + parts[n] = MaybeUninit::new(Part::Zero(frac_digits - actual_frac_digits)); n += 1; } } @@ -492,7 +505,7 @@ fn estimate_max_buf_len(exp: i16) -> usize { } /// Formats given floating point number into the exponential form with -/// exactly given number of significant digits. The result is stored to +/// exactly given number of fractional digits. The result is stored to /// the supplied parts array while utilizing given byte buffer as a scratch. /// `upper` is used to determine the case of the exponent prefix (`e` or `E`). /// The first part to be rendered is always a `Part::Sign` (which can be @@ -502,8 +515,10 @@ fn estimate_max_buf_len(exp: i16) -> usize { /// It should return the part of the buffer that it initialized. /// You probably would want `strategy::grisu::format_exact` for this. /// -/// The byte buffer should be at least `ndigits` bytes long unless `ndigits` is -/// so large that only the fixed number of digits will be ever written. +/// The returned format is `[sign][digit][.fraction?][zero padding?][e|E][exponent]`. +/// +/// The byte buffer should be at least `frac_digits + 1` bytes long unless +/// `frac_digits` is so large that only the fixed number of digits will be ever written. /// (The tipping point for `f64` is about 800, so 1000 bytes should be enough.) /// There should be at least 6 parts available, due to the worst case like /// `[+][1][.][2345][e][-][6]`. @@ -511,7 +526,7 @@ pub fn to_exact_exp_str<'a, T, F>( mut format_exact: F, v: T, sign: Sign, - ndigits: usize, + frac_digits: usize, upper: bool, buf: &'a mut [MaybeUninit], parts: &'a mut [MaybeUninit>], @@ -521,7 +536,6 @@ where F: FnMut(&Decoded, &'a mut [MaybeUninit], i16) -> (&'a [u8], i16), { assert!(parts.len() >= 6); - assert!(ndigits > 0); let (negative, full_decoded) = decode(v); let sign = determine_sign(sign, &full_decoded, negative); @@ -537,10 +551,10 @@ where Formatted { sign, parts: unsafe { parts[..1].assume_init_ref() } } } FullDecoded::Zero => { - if ndigits > 1 { + if frac_digits > 0 { // [0.][0000][e0] parts[0] = MaybeUninit::new(Part::Copy(b"0.")); - parts[1] = MaybeUninit::new(Part::Zero(ndigits - 1)); + parts[1] = MaybeUninit::new(Part::Zero(frac_digits)); parts[2] = MaybeUninit::new(Part::Copy(if upper { b"E0" } else { b"e0" })); Formatted { sign, @@ -558,11 +572,14 @@ where } FullDecoded::Finite(ref decoded) => { let maxlen = estimate_max_buf_len(decoded.exp); - assert!(buf.len() >= ndigits || buf.len() >= maxlen); - - let trunc = if ndigits < maxlen { ndigits } else { maxlen }; - let (buf, exp) = format_exact(decoded, &mut buf[..trunc], i16::MIN); - Formatted { sign, parts: digits_to_exp_str(buf, exp, ndigits, upper, parts) } + // Scratch space is only needed for the significant digits that `format_exact` can + // actually generate. Any remaining requested fractional precision becomes a trailing + // `Part::Zero`. + let sig_digits = if frac_digits < maxlen { frac_digits + 1 } else { maxlen }; + assert!(buf.len() >= sig_digits); + + let (buf, exp) = format_exact(decoded, &mut buf[..sig_digits], i16::MIN); + Formatted { sign, parts: digits_to_exp_str(buf, exp, frac_digits, upper, parts) } } } } diff --git a/core/src/num/imp/fmt.rs b/core/src/num/imp/fmt.rs index 0e4b2844d8192..db5dfb37ed423 100644 --- a/core/src/num/imp/fmt.rs +++ b/core/src/num/imp/fmt.rs @@ -68,9 +68,14 @@ pub struct Formatted<'a> { } impl<'a> Formatted<'a> { - /// Returns the exact byte length of combined formatted result. + /// Returns the byte length of combined formatted result. + /// + /// Saturates at `usize::MAX` if the actual length is larger. + /// + /// This matters on 16-bit targets, where exponential formatting can exceed + /// `usize::MAX` by emitting `u16::MAX` trailing zeroes plus `"1."` / `"e0"`. pub fn len(&self) -> usize { - self.sign.len() + self.parts.iter().map(|part| part.len()).sum::() + self.parts.iter().fold(self.sign.len(), |len, part| len.saturating_add(part.len())) } /// Writes all formatted parts into the supplied buffer. diff --git a/core/src/num/imp/int_sqrt.rs b/core/src/num/imp/int_sqrt.rs index 152841793d56e..c2bb4bf6078f4 100644 --- a/core/src/num/imp/int_sqrt.rs +++ b/core/src/num/imp/int_sqrt.rs @@ -41,36 +41,6 @@ pub(in crate::num) const fn u8(n: u8) -> u8 { U8_ISQRT_WITH_REMAINDER[n as usize].0 } -/// Generates an `i*` function that returns the [integer square root]( -/// https://en.wikipedia.org/wiki/Integer_square_root) of any **nonnegative** -/// input of a specific signed integer type. -macro_rules! signed_fn { - ($SignedT:ident, $UnsignedT:ident) => { - /// Returns the [integer square root]( - /// https://en.wikipedia.org/wiki/Integer_square_root) of any - /// **nonnegative** - #[doc = concat!("[`", stringify!($SignedT), "`](prim@", stringify!($SignedT), ")")] - /// input. - /// - /// # Safety - /// - /// This results in undefined behavior when the input is negative. - #[must_use = "this returns the result of the operation, \ - without modifying the original"] - #[inline] - pub(in crate::num) const unsafe fn $SignedT(n: $SignedT) -> $SignedT { - debug_assert!(n >= 0, "Negative input inside `isqrt`."); - $UnsignedT(n as $UnsignedT) as $SignedT - } - }; -} - -signed_fn!(i8, u8); -signed_fn!(i16, u16); -signed_fn!(i32, u32); -signed_fn!(i64, u64); -signed_fn!(i128, u128); - /// Generates a `u*` function that returns the [integer square root]( /// https://en.wikipedia.org/wiki/Integer_square_root) of any input of /// a specific unsigned integer type. diff --git a/core/src/num/imp/overflow_panic.rs b/core/src/num/imp/overflow_panic.rs index a9b91daba954b..2b699fa61f871 100644 --- a/core/src/num/imp/overflow_panic.rs +++ b/core/src/num/imp/overflow_panic.rs @@ -49,3 +49,9 @@ pub(in crate::num) const fn shr() -> ! { pub(in crate::num) const fn shl() -> ! { panic!("attempt to shift left with overflow") } + +#[cold] +#[track_caller] +pub(in crate::num) const fn cast_integer() -> ! { + panic!("attempt to cast integer with overflow") +} diff --git a/core/src/num/imp/traits.rs b/core/src/num/imp/traits.rs index 7b84f7a4a5aa2..3a7ea23f73f31 100644 --- a/core/src/num/imp/traits.rs +++ b/core/src/num/imp/traits.rs @@ -204,8 +204,8 @@ impl Float for f16 { const BITS: u32 = 16; const SIG_TOTAL_BITS: u32 = Self::MANTISSA_DIGITS; - const EXP_MASK: Self::Int = Self::EXP_MASK; - const SIG_MASK: Self::Int = Self::MAN_MASK; + const EXP_MASK: Self::Int = Self::EXPONENT_MASK; + const SIG_MASK: Self::Int = Self::MANTISSA_MASK; const MIN_EXPONENT_ROUND_TO_EVEN: i32 = -22; const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 5; @@ -238,8 +238,8 @@ impl Float for f32 { const BITS: u32 = 32; const SIG_TOTAL_BITS: u32 = Self::MANTISSA_DIGITS; - const EXP_MASK: Self::Int = Self::EXP_MASK; - const SIG_MASK: Self::Int = Self::MAN_MASK; + const EXP_MASK: Self::Int = Self::EXPONENT_MASK; + const SIG_MASK: Self::Int = Self::MANTISSA_MASK; const MIN_EXPONENT_ROUND_TO_EVEN: i32 = -17; const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 10; @@ -271,8 +271,8 @@ impl Float for f64 { const BITS: u32 = 64; const SIG_TOTAL_BITS: u32 = Self::MANTISSA_DIGITS; - const EXP_MASK: Self::Int = Self::EXP_MASK; - const SIG_MASK: Self::Int = Self::MAN_MASK; + const EXP_MASK: Self::Int = Self::EXPONENT_MASK; + const SIG_MASK: Self::Int = Self::MANTISSA_MASK; const MIN_EXPONENT_ROUND_TO_EVEN: i32 = -4; const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 23; diff --git a/core/src/num/int_macros.rs b/core/src/num/int_macros.rs index aba0eaf8d4842..01b846548547f 100644 --- a/core/src/num/int_macros.rs +++ b/core/src/num/int_macros.rs @@ -173,14 +173,13 @@ macro_rules! int_impl { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_highest_one(), 0b_01000000); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_highest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -194,14 +193,13 @@ macro_rules! int_impl { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_lowest_one(), 0b_00000100); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_lowest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -215,14 +213,13 @@ macro_rules! int_impl { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".highest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".highest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".highest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".highest_one(), Some(4));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -236,14 +233,13 @@ macro_rules! int_impl { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".lowest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".lowest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".lowest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".lowest_one(), Some(0));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -272,6 +268,94 @@ macro_rules! int_impl { self as $UnsignedT } + /// Saturating conversion of `self` to an unsigned integer of the same size. + /// + /// Negative values are clamped to `0`. + /// + /// For other kinds of unsigned integer casts, see + /// [`cast_unsigned`](Self::cast_unsigned), + /// [`checked_cast_unsigned`](Self::checked_cast_unsigned), + /// or [`strict_cast_unsigned`](Self::strict_cast_unsigned). + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_cast_extras)] + #[doc = concat!("let n = ", stringify!($SelfT), "::MIN;")] + /// + #[doc = concat!("assert_eq!(n.saturating_cast_unsigned(), 0", stringify!($UnsignedT), ");")] + #[doc = concat!("assert_eq!(64", stringify!($SelfT), ".saturating_cast_unsigned(), 64", stringify!($UnsignedT), ");")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn saturating_cast_unsigned(self) -> $UnsignedT { + if self >= 0 { + self.cast_unsigned() + } else { + 0 + } + } + + /// Checked conversion of `self` to an unsigned integer of the same size, + /// returning `None` if `self` is negative. + /// + /// For other kinds of unsigned integer casts, see + /// [`cast_unsigned`](Self::cast_unsigned), + /// [`saturating_cast_unsigned`](Self::saturating_cast_unsigned), + /// or [`strict_cast_unsigned`](Self::strict_cast_unsigned). + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_cast_extras)] + #[doc = concat!("let n = ", stringify!($SelfT), "::MIN;")] + /// + #[doc = concat!("assert_eq!(n.checked_cast_unsigned(), None);")] + #[doc = concat!("assert_eq!(64", stringify!($SelfT), ".checked_cast_unsigned(), Some(64", stringify!($UnsignedT), "));")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn checked_cast_unsigned(self) -> Option<$UnsignedT> { + if self >= 0 { + Some(self.cast_unsigned()) + } else { + None + } + } + + /// Strict conversion of `self` to an unsigned integer of the same size, + /// which panics if `self` is negative. + /// + /// For other kinds of unsigned integer casts, see + /// [`cast_unsigned`](Self::cast_unsigned), + /// [`checked_cast_unsigned`](Self::checked_cast_unsigned), + /// or [`saturating_cast_unsigned`](Self::saturating_cast_unsigned). + /// + /// # Examples + /// + /// ```should_panic + /// #![feature(integer_cast_extras)] + #[doc = concat!("let _ = ", stringify!($SelfT), "::MIN.strict_cast_unsigned();")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + #[track_caller] + pub const fn strict_cast_unsigned(self) -> $UnsignedT { + match self.checked_cast_unsigned() { + Some(n) => n, + None => imp::overflow_panic::cast_integer(), + } + } + /// Shifts the bits to the left by a specified amount, `n`, /// wrapping the truncated bits to the end of the resulting integer. /// @@ -390,13 +474,9 @@ macro_rules! int_impl { #[must_use] #[inline] pub const fn from_be(x: Self) -> Self { - #[cfg(target_endian = "big")] - { - x - } - #[cfg(not(target_endian = "big"))] - { - x.swap_bytes() + cfg_select! { + target_endian = "big" => x, + _ => x.swap_bytes(), } } @@ -422,13 +502,9 @@ macro_rules! int_impl { #[must_use] #[inline] pub const fn from_le(x: Self) -> Self { - #[cfg(target_endian = "little")] - { - x - } - #[cfg(not(target_endian = "little"))] - { - x.swap_bytes() + cfg_select! { + target_endian = "little" => x, + _ => x.swap_bytes(), } } @@ -459,13 +535,9 @@ macro_rules! int_impl { without modifying the original"] #[inline] pub const fn to_be(self) -> Self { // or not to be? - #[cfg(target_endian = "big")] - { - self - } - #[cfg(not(target_endian = "big"))] - { - self.swap_bytes() + cfg_select! { + target_endian = "big" => self, + _ => self.swap_bytes(), } } @@ -496,13 +568,9 @@ macro_rules! int_impl { without modifying the original"] #[inline] pub const fn to_le(self) -> Self { - #[cfg(target_endian = "little")] - { - self - } - #[cfg(not(target_endian = "little"))] - { - self.swap_bytes() + cfg_select! { + target_endian = "little" => self, + _ => self.swap_bytes(), } } @@ -1827,7 +1895,11 @@ macro_rules! int_impl { } } - /// Returns the square root of the number, rounded down. + /// Returns the integer square root of the number, rounded down. + /// + /// This function returns the **principal (non-negative) square root**. + /// For a given number `n`, although both `x` and `-x` satisfy x2 = n, + /// this function always returns the non-negative value. /// /// Returns `None` if `self` is negative. /// @@ -1845,10 +1917,9 @@ macro_rules! int_impl { if self < 0 { None } else { - // SAFETY: Input is nonnegative in this `else` branch. - let result = unsafe { - imp::int_sqrt::$ActualT(self as $ActualT) as $SelfT - }; + // The upper bound of `$UnsignedT::MAX.isqrt()` told to the compiler + // in the unsigned function also tells it that `result >= 0` + let result = self.cast_unsigned().isqrt().cast_signed(); // Inform the optimizer what the range of outputs is. If // testing `core` crashes with no panic message and a @@ -1862,15 +1933,9 @@ macro_rules! int_impl { // `[0, <$ActualT>::MAX]`, sqrt(n) will be bounded by // `[sqrt(0), sqrt(<$ActualT>::MAX)]`. unsafe { - // SAFETY: `<$ActualT>::MAX` is nonnegative. - const MAX_RESULT: $SelfT = unsafe { - imp::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT - }; - - crate::hint::assert_unchecked(result >= 0); + const MAX_RESULT: $SelfT = <$SelfT>::MAX.cast_unsigned().isqrt().cast_signed(); crate::hint::assert_unchecked(result <= MAX_RESULT); } - Some(result) } } @@ -2712,32 +2777,6 @@ macro_rules! int_impl { (a as Self, b) } - /// Calculates the complete product `self * rhs` without the possibility to overflow. - /// - /// This returns the low-order (wrapping) bits and the high-order (overflow) bits - /// of the result as two separate values, in that order. - /// - /// If you also need to add a carry to the wide result, then you want - /// [`Self::carrying_mul`] instead. - /// - /// # Examples - /// - /// Please note that this example is shared among integer types, which is why `i32` is used. - /// - /// ``` - /// #![feature(widening_mul)] - /// assert_eq!(5i32.widening_mul(-2), (4294967286, -1)); - /// assert_eq!(1_000_000_000i32.widening_mul(-10), (2884901888, -3)); - /// ``` - #[unstable(feature = "widening_mul", issue = "152016")] - #[rustc_const_unstable(feature = "widening_mul", issue = "152016")] - #[must_use = "this returns the result of the operation, \ - without modifying the original"] - #[inline] - pub const fn widening_mul(self, rhs: Self) -> ($UnsignedT, Self) { - Self::carrying_mul_add(self, rhs, 0, 0) - } - /// Calculates the "full multiplication" `self * rhs + carry` /// without the possibility to overflow. /// @@ -2748,8 +2787,6 @@ macro_rules! int_impl { /// additional amount of overflow. This allows for chaining together multiple /// multiplications to create "big integers" which represent larger values. /// - /// If you don't need the `carry`, then you can use [`Self::widening_mul`] instead. - /// /// # Examples /// /// Please note that this example is shared among integer types, which is why `i32` is used. @@ -2784,8 +2821,7 @@ macro_rules! int_impl { /// additional amount of overflow. This allows for chaining together multiple /// multiplications to create "big integers" which represent larger values. /// - /// If you don't need either `carry`, then you can use [`Self::widening_mul`] instead, - /// and if you only need one `carry`, then you can use [`Self::carrying_mul`] instead. + /// If you only need one `carry`, then you can use [`Self::carrying_mul`] instead. /// /// # Examples /// @@ -3122,7 +3158,11 @@ macro_rules! int_impl { } } - /// Returns the square root of the number, rounded down. + /// Returns the integer square root of the number, rounded down. + /// + /// This function returns the **principal (non-negative) square root**. + /// For a given number `n`, although both `x` and `-x` satisfy x2 = n, + /// this function always returns the non-negative value. /// /// # Panics /// @@ -3944,5 +3984,89 @@ macro_rules! int_impl { self } } + + /// Truncate an integer to an integer of the same size or smaller, preserving the least + /// significant bits. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120i8, 120", stringify!($SelfT), ".truncate());")] + #[doc = concat!("assert_eq!(-120i8, (-120", stringify!($SelfT), ").truncate());")] + /// assert_eq!(120i8, 376i32.truncate()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn truncate(self) -> Target + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_truncate(self) + } + + /// Truncate an integer to an integer of the same size or smaller, saturating at numeric bounds + /// instead of truncating. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120i8, 120", stringify!($SelfT), ".saturating_truncate());")] + #[doc = concat!("assert_eq!(-120i8, (-120", stringify!($SelfT), ").saturating_truncate());")] + /// assert_eq!(127i8, 376i32.saturating_truncate()); + /// assert_eq!(-128i8, (-1000i32).saturating_truncate()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn saturating_truncate(self) -> Target + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_saturating_truncate(self) + } + + /// Truncate an integer to an integer of the same size or smaller, returning `None` if the value + /// is outside the bounds of the smaller type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(Some(120i8), 120", stringify!($SelfT), ".checked_truncate());")] + #[doc = concat!("assert_eq!(Some(-120i8), (-120", stringify!($SelfT), ").checked_truncate());")] + /// assert_eq!(None, 376i32.checked_truncate::()); + /// assert_eq!(None, (-1000i32).checked_truncate::()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn checked_truncate(self) -> Option + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_checked_truncate(self) + } + + /// Widen to an integer of the same size or larger, preserving its value. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120i128, 120i8.widen());")] + #[doc = concat!("assert_eq!(-120i128, (-120i8).widen());")] + /// ``` + #[must_use = "this returns the widened value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn widen(self) -> Target + where Self: [const] traits::WidenTarget + { + traits::WidenTarget::internal_widen(self) + } } } diff --git a/core/src/num/mod.rs b/core/src/num/mod.rs index 333e44649d8f6..ed4624f7c9494 100644 --- a/core/src/num/mod.rs +++ b/core/src/num/mod.rs @@ -46,6 +46,7 @@ mod error; mod float_parse; mod nonzero; mod saturating; +mod traits; mod wrapping; /// 100% perma-unstable @@ -239,6 +240,39 @@ macro_rules! midpoint_impl { }; } +macro_rules! widening_mul_impl { + ($SelfT:ty, $WideT:ty) => { + /// Widening multiplication. Computes `self * rhs`, widening to a larger integer. + /// + /// The returned value is always exact and can never overflow. + /// + /// Note that this method is semantically equivalent to [`carrying_mul`] with a + /// carry of zero, with the latter instead returning a tuple denoting the low and + /// high parts of the result. Consider using it instead if you need + /// interoperability with other big int helper functions, or if this method isn't + /// available for a given type. + /// + /// [`carrying_mul`]: Self::carrying_mul + /// + /// # Examples + /// + /// ``` + /// #![feature(widening_mul)] + /// + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_mul(0_", stringify!($SelfT), "), 0);")] + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_mul(", stringify!($SelfT), "::MAX), ", stringify!($SelfT), "::MAX as ", stringify!($WideT), " * ", stringify!($SelfT), "::MAX as ", stringify!($WideT), ");")] + /// ``` + #[unstable(feature = "widening_mul", issue = "152016")] + #[rustc_const_unstable(feature = "widening_mul", issue = "152016")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + pub const fn widening_mul(self, rhs: Self) -> $WideT { + self as $WideT * rhs as $WideT + } + } +} + macro_rules! widening_carryless_mul_impl { ($SelfT:ty, $WideT:ty) => { /// Performs a widening carry-less multiplication. @@ -359,6 +393,7 @@ impl i8 { bound_condition = "", } midpoint_impl! { i8, i16, signed } + widening_mul_impl! { i8, i16 } } impl i16 { @@ -383,6 +418,7 @@ impl i16 { bound_condition = "", } midpoint_impl! { i16, i32, signed } + widening_mul_impl! { i16, i32 } } impl i32 { @@ -407,6 +443,7 @@ impl i32 { bound_condition = "", } midpoint_impl! { i32, i64, signed } + widening_mul_impl! { i32, i64 } } impl i64 { @@ -431,6 +468,7 @@ impl i64 { bound_condition = "", } midpoint_impl! { i64, signed } + widening_mul_impl! { i64, i128 } } impl i128 { @@ -459,6 +497,7 @@ impl i128 { midpoint_impl! { i128, signed } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "16")] impl isize { int_impl! { @@ -484,6 +523,7 @@ impl isize { midpoint_impl! { isize, i32, signed } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "32")] impl isize { int_impl! { @@ -509,6 +549,7 @@ impl isize { midpoint_impl! { isize, i64, signed } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "64")] impl isize { int_impl! { @@ -564,6 +605,7 @@ impl u8 { bound_condition = "", } midpoint_impl! { u8, u16, unsigned } + widening_mul_impl! { u8, u16 } widening_carryless_mul_impl! { u8, u16 } carrying_carryless_mul_impl! { u8, u16 } @@ -985,7 +1027,8 @@ impl u8 { matches!(*self, b'0'..=b'9') | matches!(*self, b'A'..=b'F') | matches!(*self, b'a'..=b'f') } - /// Checks if the value is an ASCII punctuation character: + /// Checks if the value is an ASCII punctuation or symbol character + /// (i.e. not alphanumeric, whitespace, or control): /// /// - U+0021 ..= U+002F `! " # $ % & ' ( ) * + , - . /`, or /// - U+003A ..= U+0040 `: ; < = > ? @`, or @@ -1026,7 +1069,8 @@ impl u8 { | matches!(*self, b'{'..=b'~') } - /// Checks if the value is an ASCII graphic character: + /// Checks if the value is an ASCII graphic character + /// (i.e. not whitespace or control): /// U+0021 '!' ..= U+007E '~'. /// /// # Examples @@ -1064,6 +1108,9 @@ impl u8 { /// U+0020 SPACE, U+0009 HORIZONTAL TAB, U+000A LINE FEED, /// U+000C FORM FEED, or U+000D CARRIAGE RETURN. /// + /// **Warning:** Because the list above excludes U+000B VERTICAL TAB, + /// `b.is_ascii_whitespace()` is **not** equivalent to `char::from(b).is_whitespace()`. + /// /// Rust uses the WhatWG Infra Standard's [definition of ASCII /// whitespace][infra-aw]. There are several other definitions in /// wide use. For instance, [the POSIX locale][pct] includes @@ -1206,6 +1253,7 @@ impl u16 { bound_condition = "", } midpoint_impl! { u16, u32, unsigned } + widening_mul_impl! { u16, u32 } widening_carryless_mul_impl! { u16, u32 } carrying_carryless_mul_impl! { u16, u32 } @@ -1261,6 +1309,7 @@ impl u32 { bound_condition = "", } midpoint_impl! { u32, u64, unsigned } + widening_mul_impl! { u32, u64 } widening_carryless_mul_impl! { u32, u64 } carrying_carryless_mul_impl! { u32, u64 } } @@ -1292,6 +1341,7 @@ impl u64 { bound_condition = "", } midpoint_impl! { u64, u128, unsigned } + widening_mul_impl! { u64, u128 } widening_carryless_mul_impl! { u64, u128 } carrying_carryless_mul_impl! { u64, u128 } } @@ -1328,6 +1378,7 @@ impl u128 { carrying_carryless_mul_impl! { u128, u256 } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "16")] impl usize { uint_impl! { @@ -1359,6 +1410,7 @@ impl usize { carrying_carryless_mul_impl! { usize, u32 } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "32")] impl usize { uint_impl! { @@ -1390,6 +1442,7 @@ impl usize { carrying_carryless_mul_impl! { usize, u64 } } +#[doc(auto_cfg = false)] #[cfg(target_pointer_width = "64")] impl usize { uint_impl! { @@ -1795,3 +1848,12 @@ macro_rules! from_str_int_impl { from_str_int_impl! { signed isize i8 i16 i32 i64 i128 } from_str_int_impl! { unsigned usize u8 u16 u32 u64 u128 } + +macro_rules! impl_sealed { + ($($t:ty)*) => {$( + /// Allows extension traits within `core`. + #[unstable(feature = "sealed", issue = "none")] + impl crate::sealed::Sealed for $t {} + )*} +} +impl_sealed! { isize i8 i16 i32 i64 i128 usize u8 u16 u32 u64 u128 } diff --git a/core/src/num/niche_types.rs b/core/src/num/niche_types.rs index 33b2a6741abdf..df1cdf0e65fa1 100644 --- a/core/src/num/niche_types.rs +++ b/core/src/num/niche_types.rs @@ -103,7 +103,7 @@ impl Nanoseconds { } #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Nanoseconds { +const impl Default for Nanoseconds { #[inline] fn default() -> Self { Self::ZERO diff --git a/core/src/num/nonzero.rs b/core/src/num/nonzero.rs index 3415e1d435ce0..de2d10aebdff9 100644 --- a/core/src/num/nonzero.rs +++ b/core/src/num/nonzero.rs @@ -184,7 +184,8 @@ impl_nonzero_auto_trait!(Unpin); impl_nonzero_auto_trait!(UnwindSafe); #[stable(feature = "nonzero", since = "1.28.0")] -impl Clone for NonZero +#[rustc_const_unstable(feature = "const_clone", issue = "142757")] +const impl Clone for NonZero where T: ZeroablePrimitive, { @@ -202,11 +203,12 @@ impl Copy for NonZero where T: ZeroablePrimitive {} #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] -unsafe impl TrivialClone for NonZero where T: ZeroablePrimitive {} +#[rustc_const_unstable(feature = "const_clone", issue = "142757")] +const unsafe impl TrivialClone for NonZero where T: ZeroablePrimitive {} #[stable(feature = "nonzero", since = "1.28.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for NonZero +const impl PartialEq for NonZero where T: ZeroablePrimitive + [const] PartialEq, { @@ -226,11 +228,11 @@ impl StructuralPartialEq for NonZero where T: ZeroablePrimitive + Structur #[stable(feature = "nonzero", since = "1.28.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for NonZero where T: ZeroablePrimitive + [const] Eq {} +const impl Eq for NonZero where T: ZeroablePrimitive + [const] Eq {} #[stable(feature = "nonzero", since = "1.28.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for NonZero +const impl PartialOrd for NonZero where T: ZeroablePrimitive + [const] PartialOrd, { @@ -262,7 +264,7 @@ where #[stable(feature = "nonzero", since = "1.28.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for NonZero +const impl Ord for NonZero where // FIXME(const_hack): the T: ~const Destruct should be inferred from the Self: ~const Destruct. // See https://github.com/rust-lang/rust/issues/144207 @@ -308,7 +310,7 @@ where #[stable(feature = "from_nonzero", since = "1.31.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for T +const impl From> for T where T: ZeroablePrimitive, { @@ -321,7 +323,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOr for NonZero +const impl BitOr for NonZero where T: ZeroablePrimitive + [const] BitOr, { @@ -336,7 +338,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOr for NonZero +const impl BitOr for NonZero where T: ZeroablePrimitive + [const] BitOr, { @@ -351,7 +353,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOr> for T +const impl BitOr> for T where T: ZeroablePrimitive + [const] BitOr, { @@ -366,7 +368,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOrAssign for NonZero +const impl BitOrAssign for NonZero where T: ZeroablePrimitive, Self: [const] BitOr, @@ -379,7 +381,7 @@ where #[stable(feature = "nonzero_bitor", since = "1.45.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const BitOrAssign for NonZero +const impl BitOrAssign for NonZero where T: ZeroablePrimitive, Self: [const] BitOr, @@ -648,8 +650,6 @@ macro_rules! nonzero_integer { /// # Example /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -660,7 +660,8 @@ macro_rules! nonzero_integer { /// # Some(()) /// # } /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -681,8 +682,6 @@ macro_rules! nonzero_integer { /// # Example /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -693,7 +692,8 @@ macro_rules! nonzero_integer { /// # Some(()) /// # } /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -711,8 +711,6 @@ macro_rules! nonzero_integer { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -722,7 +720,8 @@ macro_rules! nonzero_integer { /// # Some(()) /// # } /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -735,8 +734,6 @@ macro_rules! nonzero_integer { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -746,7 +743,8 @@ macro_rules! nonzero_integer { /// # Some(()) /// # } /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -1120,7 +1118,10 @@ macro_rules! nonzero_integer { /// assuming overflow cannot occur. /// Overflow is unchecked, and it is undefined behavior to overflow /// *even if the result would wrap to a non-zero value*. - /// The behavior is undefined as soon as + /// + /// # Safety + /// + /// This results in undefined behavior when #[doc = sign_dependent_expr!{ $signedness ? if signed { @@ -1478,7 +1479,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { (unsigned $Int:ty) => { #[stable(feature = "nonzero_div", since = "1.51.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Div> for $Int { + const impl Div> for $Int { type Output = $Int; /// Same as `self / other.get()`, but because `other` is a `NonZero<_>`, @@ -1497,7 +1498,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { #[stable(feature = "nonzero_div_assign", since = "1.79.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const DivAssign> for $Int { + const impl DivAssign> for $Int { /// Same as `self /= other.get()`, but because `other` is a `NonZero<_>`, /// there's never a runtime check for division-by-zero. /// @@ -1511,7 +1512,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { #[stable(feature = "nonzero_div", since = "1.51.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Rem> for $Int { + const impl Rem> for $Int { type Output = $Int; /// This operation satisfies `n % d == n - (n / d) * d`, and cannot panic. @@ -1525,7 +1526,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { #[stable(feature = "nonzero_div_assign", since = "1.79.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const RemAssign> for $Int { + const impl RemAssign> for $Int { /// This operation satisfies `n % d == n - (n / d) * d`, and cannot panic. #[inline] fn rem_assign(&mut self, other: NonZero<$Int>) { @@ -1566,7 +1567,7 @@ macro_rules! nonzero_integer_signedness_dependent_impls { (signed $Int:ty) => { #[stable(feature = "signed_nonzero_neg", since = "1.71.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Neg for NonZero<$Int> { + const impl Neg for NonZero<$Int> { type Output = Self; #[inline] @@ -1697,7 +1698,10 @@ macro_rules! nonzero_integer_signedness_dependent_methods { /// assuming overflow cannot occur. /// Overflow is unchecked, and it is undefined behavior to overflow /// *even if the result would wrap to a non-zero value*. - /// The behavior is undefined as soon as + /// + /// # Safety + /// + /// This results in undefined behavior when #[doc = concat!("`self + rhs > ", stringify!($Int), "::MAX`.")] /// /// # Examples @@ -1948,19 +1952,18 @@ macro_rules! nonzero_integer_signedness_dependent_methods { /// # Examples /// /// ``` - /// #![feature(uint_bit_width)] - /// /// # use core::num::NonZero; /// # /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { - #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::MIN.bit_width(), NonZero::new(1)?);")] + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b1)?.bit_width(), NonZero::new(1)?);")] #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b111)?.bit_width(), NonZero::new(3)?);")] #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b1110)?.bit_width(), NonZero::new(4)?);")] /// # Some(()) /// # } /// ``` - #[unstable(feature = "uint_bit_width", issue = "142326")] + #[stable(feature = "uint_bit_width", since = "1.97.0")] + #[rustc_const_stable(feature = "uint_bit_width", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] diff --git a/core/src/num/traits.rs b/core/src/num/traits.rs new file mode 100644 index 0000000000000..08012ebf1adb4 --- /dev/null +++ b/core/src/num/traits.rs @@ -0,0 +1,129 @@ +/// Definitions of traits for numeric types +// Implementation based on `num_conv` by jhpratt, under (MIT OR Apache-2.0). + +/// Trait for types that this type can be truncated to +#[unstable(feature = "num_internals", reason = "internal implementation detail", issue = "none")] +#[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] +pub const trait TruncateTarget: crate::sealed::Sealed { + #[doc(hidden)] + fn internal_truncate(self) -> Target; + + #[doc(hidden)] + fn internal_saturating_truncate(self) -> Target; + + #[doc(hidden)] + fn internal_checked_truncate(self) -> Option; +} + +/// Trait for types that this type can be widened to +#[unstable(feature = "num_internals", reason = "internal implementation detail", issue = "none")] +#[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] +pub const trait WidenTarget: crate::sealed::Sealed { + #[doc(hidden)] + fn internal_widen(self) -> Target; +} + +macro_rules! impl_truncate { + ($($from:ty => $($to:ty),+;)*) => {$($( + const _: () = assert!( + size_of::<$from>() >= size_of::<$to>(), + concat!( + "cannot truncate ", + stringify!($from), + " to ", + stringify!($to), + " because ", + stringify!($from), + " is smaller than ", + stringify!($to) + ) + ); + + #[unstable(feature = "num_internals", reason = "internal implementation detail", issue = "none")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + impl const TruncateTarget<$to> for $from { + #[inline] + fn internal_truncate(self) -> $to { + self as _ + } + + #[inline] + fn internal_saturating_truncate(self) -> $to { + if self > <$to>::MAX as Self { + <$to>::MAX + } else if self < <$to>::MIN as Self { + <$to>::MIN + } else { + self as _ + } + } + + #[inline] + fn internal_checked_truncate(self) -> Option<$to> { + if self > <$to>::MAX as Self || self < <$to>::MIN as Self { + None + } else { + Some(self as _) + } + } + } + )+)*}; +} + +macro_rules! impl_widen { + ($($from:ty => $($to:ty),+;)*) => {$($( + const _: () = assert!( + size_of::<$from>() <= size_of::<$to>(), + concat!( + "cannot widen ", + stringify!($from), + " to ", + stringify!($to), + " because ", + stringify!($from), + " is larger than ", + stringify!($to) + ) + ); + + #[unstable(feature = "num_internals", reason = "internal implementation detail", issue = "none")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + impl const WidenTarget<$to> for $from { + fn internal_widen(self) -> $to { + self as _ + } + } + )+)*}; +} + +impl_truncate! { + u8 => u8; + u16 => u16, u8; + u32 => u32, u16, u8; + u64 => u64, u32, u16, u8; + u128 => u128, u64, u32, u16, u8; + usize => usize, u16, u8; + + i8 => i8; + i16 => i16, i8; + i32 => i32, i16, i8; + i64 => i64, i32, i16, i8; + i128 => i128, i64, i32, i16, i8; + isize => isize, i16, i8; +} + +impl_widen! { + u8 => u8, u16, u32, u64, u128, usize; + u16 => u16, u32, u64, u128, usize; + u32 => u32, u64, u128; + u64 => u64, u128; + u128 => u128; + usize => usize; + + i8 => i8, i16, i32, i64, i128, isize; + i16 => i16, i32, i64, i128, isize; + i32 => i32, i64, i128; + i64 => i64, i128; + i128 => i128; + isize => isize; +} diff --git a/core/src/num/uint_macros.rs b/core/src/num/uint_macros.rs index 27dbe6d3f1d8b..3170143da9b30 100644 --- a/core/src/num/uint_macros.rs +++ b/core/src/num/uint_macros.rs @@ -232,14 +232,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(uint_bit_width)] - /// #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".bit_width(), 0);")] #[doc = concat!("assert_eq!(0b111_", stringify!($SelfT), ".bit_width(), 3);")] #[doc = concat!("assert_eq!(0b1110_", stringify!($SelfT), ".bit_width(), 4);")] #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.bit_width(), ", stringify!($BITS), ");")] /// ``` - #[unstable(feature = "uint_bit_width", issue = "142326")] + #[stable(feature = "uint_bit_width", since = "1.97.0")] + #[rustc_const_stable(feature = "uint_bit_width", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -253,14 +252,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_highest_one(), 0b_01000000); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_highest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -274,14 +272,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_lowest_one(), 0b_00000100); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_lowest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -295,14 +292,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".highest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".highest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".highest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".highest_one(), Some(4));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -319,14 +315,13 @@ macro_rules! uint_impl { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".lowest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".lowest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".lowest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".lowest_one(), Some(0));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "1.97.0")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "1.97.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -358,6 +353,98 @@ macro_rules! uint_impl { self as $SignedT } + /// Saturating conversion of `self` to a signed integer of the same size. + /// + /// The signed integer's maximum value is returned if `self` is larger + /// than the maximum positive value representable by the signed integer. + /// + /// For other kinds of signed integer casts, see + /// [`cast_signed`](Self::cast_signed), + /// [`checked_cast_signed`](Self::checked_cast_signed), + /// or [`strict_cast_signed`](Self::strict_cast_signed). + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_cast_extras)] + #[doc = concat!("let n = ", stringify!($SelfT), "::MAX;")] + /// + #[doc = concat!("assert_eq!(n.saturating_cast_signed(), ", stringify!($SignedT), "::MAX);")] + #[doc = concat!("assert_eq!(64", stringify!($SelfT), ".saturating_cast_signed(), 64", stringify!($SignedT), ");")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn saturating_cast_signed(self) -> $SignedT { + // Clamp to the signed integer max size, which is ActualT::MAX >> 1. + if self <= <$SignedT>::MAX.cast_unsigned() { + self.cast_signed() + } else { + <$SignedT>::MAX + } + } + + /// Checked conversion of `self` to a signed integer of the same size, + /// returning `None` if `self` is larger than the signed integer's + /// maximum value. + /// + /// For other kinds of signed integer casts, see + /// [`cast_signed`](Self::cast_signed), + /// [`saturating_cast_signed`](Self::saturating_cast_signed), + /// or [`strict_cast_signed`](Self::strict_cast_signed). + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_cast_extras)] + #[doc = concat!("let n = ", stringify!($SelfT), "::MAX;")] + /// + #[doc = concat!("assert_eq!(n.checked_cast_signed(), None);")] + #[doc = concat!("assert_eq!(64", stringify!($SelfT), ".checked_cast_signed(), Some(64", stringify!($SignedT), "));")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn checked_cast_signed(self) -> Option<$SignedT> { + if self <= <$SignedT>::MAX.cast_unsigned() { + Some(self.cast_signed()) + } else { + None + } + } + + /// Strict conversion of `self` to a signed integer of the same size, + /// which panics if `self` is larger than the signed integer's maximum + /// value. + /// + /// For other kinds of signed integer casts, see + /// [`cast_signed`](Self::cast_signed), + /// [`checked_cast_signed`](Self::checked_cast_signed), + /// or [`saturating_cast_signed`](Self::saturating_cast_signed). + /// + /// # Examples + /// + /// ```should_panic + /// #![feature(integer_cast_extras)] + #[doc = concat!("let _ = ", stringify!($SelfT), "::MAX.strict_cast_signed();")] + /// ``` + #[rustc_const_unstable(feature = "integer_cast_extras", issue = "154650")] + #[unstable(feature = "integer_cast_extras", issue = "154650")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + #[track_caller] + pub const fn strict_cast_signed(self) -> $SignedT { + match self.checked_cast_signed() { + Some(n) => n, + None => imp::overflow_panic::cast_integer(), + } + } + /// Shifts the bits to the left by a specified amount, `n`, /// wrapping the truncated bits to the end of the resulting integer. /// @@ -623,6 +710,7 @@ macro_rules! uint_impl { /// assert_eq!(n.extract_bits(0b0010_0100), 0b0000_0011); /// assert_eq!(n.extract_bits(0xF0), 0b0000_1011); /// ``` + #[doc(alias = "pext")] #[unstable(feature = "uint_gather_scatter_bits", issue = "149069")] #[must_use = "this returns the result of the operation, \ without modifying the original"] @@ -640,6 +728,7 @@ macro_rules! uint_impl { /// assert_eq!(n.deposit_bits(0b0101_0101), 0b0101_0001); /// assert_eq!(n.deposit_bits(0xF0), 0b1101_0000); /// ``` + #[doc(alias = "pdep")] #[unstable(feature = "uint_gather_scatter_bits", issue = "149069")] #[must_use = "this returns the result of the operation, \ without modifying the original"] @@ -690,13 +779,9 @@ macro_rules! uint_impl { #[must_use] #[inline(always)] pub const fn from_be(x: Self) -> Self { - #[cfg(target_endian = "big")] - { - x - } - #[cfg(not(target_endian = "big"))] - { - x.swap_bytes() + cfg_select! { + target_endian = "big" => x, + _ => x.swap_bytes(), } } @@ -721,13 +806,9 @@ macro_rules! uint_impl { #[must_use] #[inline(always)] pub const fn from_le(x: Self) -> Self { - #[cfg(target_endian = "little")] - { - x - } - #[cfg(not(target_endian = "little"))] - { - x.swap_bytes() + cfg_select! { + target_endian = "little" => x, + _ => x.swap_bytes(), } } @@ -753,13 +834,9 @@ macro_rules! uint_impl { without modifying the original"] #[inline(always)] pub const fn to_be(self) -> Self { // or not to be? - #[cfg(target_endian = "big")] - { - self - } - #[cfg(not(target_endian = "big"))] - { - self.swap_bytes() + cfg_select! { + target_endian = "big" => self, + _ => self.swap_bytes(), } } @@ -785,13 +862,9 @@ macro_rules! uint_impl { without modifying the original"] #[inline(always)] pub const fn to_le(self) -> Self { - #[cfg(target_endian = "little")] - { - self - } - #[cfg(not(target_endian = "little"))] - { - self.swap_bytes() + cfg_select! { + target_endian = "little" => self, + _ => self.swap_bytes(), } } @@ -871,7 +944,7 @@ macro_rules! uint_impl { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self + rhs > ", stringify!($SelfT), "::MAX` or `self + rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self + rhs > ", stringify!($SelfT), "::MAX`,")] /// i.e. when [`checked_add`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked @@ -1050,7 +1123,7 @@ macro_rules! uint_impl { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self - rhs > ", stringify!($SelfT), "::MAX` or `self - rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self - rhs < ", stringify!($SelfT), "::MIN`,")] /// i.e. when [`checked_sub`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked @@ -1259,7 +1332,7 @@ macro_rules! uint_impl { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self * rhs > ", stringify!($SelfT), "::MAX` or `self * rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self * rhs > ", stringify!($SelfT), "::MAX`,")] /// i.e. when [`checked_mul`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked @@ -3106,54 +3179,6 @@ macro_rules! uint_impl { (a as Self, b) } - /// Calculates the complete double-width product `self * rhs`. - /// - /// This returns the low-order (wrapping) bits and the high-order (overflow) bits - /// of the result as two separate values, in that order. As such, - /// `a.widening_mul(b).0` produces the same result as `a.wrapping_mul(b)`. - /// - /// If you also need to add a value and carry to the wide result, then you want - /// [`Self::carrying_mul_add`] instead. - /// - /// If you also need to add a carry to the wide result, then you want - /// [`Self::carrying_mul`] instead. - /// - /// If you just want to know *whether* the multiplication overflowed, then you - /// want [`Self::overflowing_mul`] instead. - /// - /// # Examples - /// - /// ``` - /// #![feature(widening_mul)] - #[doc = concat!("assert_eq!(5_", stringify!($SelfT), ".widening_mul(7), (35, 0));")] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_mul(", stringify!($SelfT), "::MAX), (1, ", stringify!($SelfT), "::MAX - 1));")] - /// ``` - /// - /// Compared to other `*_mul` methods: - /// ``` - /// #![feature(widening_mul)] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::widening_mul(1 << ", stringify!($BITS_MINUS_ONE), ", 6), (0, 3));")] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::overflowing_mul(1 << ", stringify!($BITS_MINUS_ONE), ", 6), (0, true));")] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::wrapping_mul(1 << ", stringify!($BITS_MINUS_ONE), ", 6), 0);")] - #[doc = concat!("assert_eq!(", stringify!($SelfT), "::checked_mul(1 << ", stringify!($BITS_MINUS_ONE), ", 6), None);")] - /// ``` - /// - /// Please note that this example is shared among integer types, which is why `u32` is used. - /// - /// ``` - /// #![feature(widening_mul)] - /// assert_eq!(5u32.widening_mul(2), (10, 0)); - /// assert_eq!(1_000_000_000u32.widening_mul(10), (1410065408, 2)); - /// ``` - #[unstable(feature = "widening_mul", issue = "152016")] - #[rustc_const_unstable(feature = "widening_mul", issue = "152016")] - #[must_use = "this returns the result of the operation, \ - without modifying the original"] - #[inline] - pub const fn widening_mul(self, rhs: Self) -> (Self, Self) { - Self::carrying_mul_add(self, rhs, 0, 0) - } - /// Calculates the "full multiplication" `self * rhs + carry` /// without the possibility to overflow. /// @@ -3595,7 +3620,7 @@ macro_rules! uint_impl { without modifying the original"] #[inline] pub const fn isqrt(self) -> Self { - let result = imp::int_sqrt::$ActualT(self as $ActualT) as $SelfT; + let result = imp::int_sqrt::$ActualT(self as $ActualT) as Self; // Inform the optimizer what the range of outputs is. If testing // `core` crashes with no panic message and a `num::int_sqrt::u*` @@ -3606,10 +3631,29 @@ macro_rules! uint_impl { // function, which means that increasing the input will never // cause the output to decrease. Thus, since the input for unsigned // integers is bounded by `[0, <$ActualT>::MAX]`, sqrt(n) will be - // bounded by `[sqrt(0), sqrt(<$ActualT>::MAX)]`. + // bounded by `[sqrt(0), sqrt(<$ActualT>::MAX)]` and bounding the + // input by `[1, <$ActualT>::MAX]` bounds sqrt(n) by + // `[sqrt(1), sqrt(<$ActualT>::MAX)]`. unsafe { const MAX_RESULT: $SelfT = imp::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT; - crate::hint::assert_unchecked(result <= MAX_RESULT); + crate::hint::assert_unchecked(result <= MAX_RESULT) + } + + if self >= 1 { + // SAFETY: The above statements about monotonicity also apply here. + // Since the input in this branch is bounded by `[1, <$ActualT>::MAX]`, + // sqrt(n) is bounded by `[sqrt(1), sqrt(<$ActualT>::MAX)]`, and + // `sqrt(1) == 1`. + unsafe { crate::hint::assert_unchecked(result >= 1) } + } + + // SAFETY: the isqrt implementation returns the square root and rounds down, + // meaning `result * result <= self`. This implies `result <= self`. + // The compiler needs both to optimize for both. + // `result * result <= self` implies the multiplication will not overflow. + unsafe { + crate::hint::assert_unchecked(result.unchecked_mul(result) <= self); + crate::hint::assert_unchecked(result <= self); } result @@ -4107,5 +4151,83 @@ macro_rules! uint_impl { #[deprecated(since = "TBD", note = "replaced by the `MAX` associated constant on this type")] #[rustc_diagnostic_item = concat!(stringify!($SelfT), "_legacy_fn_max_value")] pub const fn max_value() -> Self { Self::MAX } + + /// Truncate an integer to an integer of the same size or smaller, preserving the least + /// significant bits. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120u8, 120", stringify!($SelfT), ".truncate());")] + /// assert_eq!(120u8, 376u32.truncate()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn truncate(self) -> Target + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_truncate(self) + } + + /// Truncate an integer to an integer of the same size or smaller, saturating at numeric bounds + /// instead of truncating. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120u8, 120", stringify!($SelfT), ".saturating_truncate());")] + /// assert_eq!(255u8, 376u32.saturating_truncate()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn saturating_truncate(self) -> Target + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_saturating_truncate(self) + } + + /// Truncate an integer to an integer of the same size or smaller, returning `None` if the value + /// is outside the bounds of the smaller type. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(Some(120u8), 120", stringify!($SelfT), ".checked_truncate());")] + /// assert_eq!(None, 376u32.checked_truncate::()); + /// ``` + #[must_use = "this returns the truncated value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn checked_truncate(self) -> Option + where Self: [const] traits::TruncateTarget + { + traits::TruncateTarget::internal_checked_truncate(self) + } + + /// Widen to an integer of the same size or larger, preserving its value. + /// + /// # Examples + /// + /// ``` + /// #![feature(integer_widen_truncate)] + #[doc = concat!("assert_eq!(120u128, 120u8.widen());")] + /// ``` + #[must_use = "this returns the widened value and does not modify the original"] + #[unstable(feature = "integer_widen_truncate", issue = "154330")] + #[rustc_const_unstable(feature = "integer_widen_truncate", issue = "154330")] + #[inline] + pub const fn widen(self) -> Target + where Self: [const] traits::WidenTarget + { + traits::WidenTarget::internal_widen(self) + } } } diff --git a/core/src/num/wrapping.rs b/core/src/num/wrapping.rs index 881fe615f800f..68c5baf15fb9f 100644 --- a/core/src/num/wrapping.rs +++ b/core/src/num/wrapping.rs @@ -89,7 +89,7 @@ macro_rules! sh_impl_signed { ($t:ident, $f:ident) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shl<$f> for Wrapping<$t> { + const impl Shl<$f> for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -107,7 +107,7 @@ macro_rules! sh_impl_signed { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShlAssign<$f> for Wrapping<$t> { + const impl ShlAssign<$f> for Wrapping<$t> { #[inline] fn shl_assign(&mut self, other: $f) { *self = *self << other; @@ -119,7 +119,7 @@ macro_rules! sh_impl_signed { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shr<$f> for Wrapping<$t> { + const impl Shr<$f> for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -137,7 +137,7 @@ macro_rules! sh_impl_signed { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShrAssign<$f> for Wrapping<$t> { + const impl ShrAssign<$f> for Wrapping<$t> { #[inline] fn shr_assign(&mut self, other: $f) { *self = *self >> other; @@ -153,7 +153,7 @@ macro_rules! sh_impl_unsigned { ($t:ident, $f:ident) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shl<$f> for Wrapping<$t> { + const impl Shl<$f> for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -167,7 +167,7 @@ macro_rules! sh_impl_unsigned { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShlAssign<$f> for Wrapping<$t> { + const impl ShlAssign<$f> for Wrapping<$t> { #[inline] fn shl_assign(&mut self, other: $f) { *self = *self << other; @@ -179,7 +179,7 @@ macro_rules! sh_impl_unsigned { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shr<$f> for Wrapping<$t> { + const impl Shr<$f> for Wrapping<$t> { type Output = Wrapping<$t>; #[inline] @@ -193,7 +193,7 @@ macro_rules! sh_impl_unsigned { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShrAssign<$f> for Wrapping<$t> { + const impl ShrAssign<$f> for Wrapping<$t> { #[inline] fn shr_assign(&mut self, other: $f) { *self = *self >> other; diff --git a/core/src/offload.md b/core/src/offload.md new file mode 100644 index 0000000000000..fb3c0b87b4815 --- /dev/null +++ b/core/src/offload.md @@ -0,0 +1,39 @@ +This module provides support for gpu offloading. For technical details regarding the `offload_kernel` +and how to use it, see their respective documentation. + +## General usage +The `offload_kernel` macro can be applied to a function to generate the necessary code to launch a +kernel on the target device. + +```rust,ignore (optional component) +#[offload_kernel] +fn kernel(x: *mut [f64; 256]) { + // SAFETY: + // calling our `arch` functions and dereferencing a raw pointer is unsafe + unsafe { + let n = (*x).len(); + let i = (thread_idx_x() + block_idx_x() * block_dim_x()) as usize; + if i < n { + (*x)[i] = i as f64; + } + } +} +``` + +To launch an offloaded kernel, the only current way is to use the `core::intrinsic::offload` +intrinsic (note that intrinsics usage is discouraged outside the standard library). This +allows you to specify grid and block dimensions and pass the required arguments to the device. + +```rust,ignore (optional component) +let mut x = [0.0f64; 256]; +core::intrinsics::offload::<_, _, ()>(kernel, [256, 1, 1], [1, 1, 1], (&mut x as *mut [f64; 256],)); +``` + +For precise information on the `offload` intrinsic, see its respective documentation. + +## Current limitations: + +- Usage is restricted to types supported by the current device-mapping implementation. +- Generics and functions accepting dyn Trait are not supported. +- Kernel execution is currently restricted to intrinsics usage, which is discouraged outside of the +standard library. diff --git a/core/src/offload/mod.rs b/core/src/offload/mod.rs new file mode 100644 index 0000000000000..164bbb9f0047d --- /dev/null +++ b/core/src/offload/mod.rs @@ -0,0 +1,5 @@ +// offload module +#[unstable(feature = "gpu_offload", issue = "131513")] +pub use crate::macros::builtin::offload_kernel; +#[unstable(feature = "gpu_offload", issue = "131513")] +pub use crate::offload; diff --git a/core/src/ops/arith.rs b/core/src/ops/arith.rs index aec52424af3c4..afb814dbc6b33 100644 --- a/core/src/ops/arith.rs +++ b/core/src/ops/arith.rs @@ -70,8 +70,7 @@ on(all(Self = "{integer}", Rhs = "{float}"), message = "cannot add a float to an integer",), on(all(Self = "{float}", Rhs = "{integer}"), message = "cannot add an integer to a float",), message = "cannot add `{Rhs}` to `{Self}`", - label = "no implementation for `{Self} + {Rhs}`", - append_const_msg + label = "no implementation for `{Self} + {Rhs}`" )] #[doc(alias = "+")] pub const trait Add { @@ -181,10 +180,9 @@ add_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f16 f32 f64 f128 #[lang = "sub"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -#[rustc_on_unimplemented( +#[diagnostic::on_unimplemented( message = "cannot subtract `{Rhs}` from `{Self}`", - label = "no implementation for `{Self} - {Rhs}`", - append_const_msg + label = "no implementation for `{Self} - {Rhs}`" )] #[doc(alias = "-")] pub const trait Sub { diff --git a/core/src/ops/bit.rs b/core/src/ops/bit.rs index e347a20d2d869..b6daa0f751a31 100644 --- a/core/src/ops/bit.rs +++ b/core/src/ops/bit.rs @@ -73,7 +73,7 @@ not_impl! { bool usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 } #[stable(feature = "not_never", since = "1.60.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Not for ! { +const impl Not for ! { type Output = !; #[inline] @@ -480,7 +480,7 @@ macro_rules! shl_impl { ($t:ty, $f:ty) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shl<$f> for $t { + const impl Shl<$f> for $t { type Output = $t; #[inline] @@ -603,7 +603,7 @@ macro_rules! shr_impl { ($t:ty, $f:ty) => { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const Shr<$f> for $t { + const impl Shr<$f> for $t { type Output = $t; #[inline] @@ -958,7 +958,7 @@ macro_rules! shl_assign_impl { ($t:ty, $f:ty) => { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShlAssign<$f> for $t { + const impl ShlAssign<$f> for $t { #[inline] #[track_caller] #[rustc_inherit_overflow_checks] @@ -1045,7 +1045,7 @@ macro_rules! shr_assign_impl { ($t:ty, $f:ty) => { #[stable(feature = "op_assign_traits", since = "1.8.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] - impl const ShrAssign<$f> for $t { + const impl ShrAssign<$f> for $t { #[inline] #[track_caller] #[rustc_inherit_overflow_checks] diff --git a/core/src/ops/control_flow.rs b/core/src/ops/control_flow.rs index b15712d3599c6..227c9c43bea66 100644 --- a/core/src/ops/control_flow.rs +++ b/core/src/ops/control_flow.rs @@ -102,7 +102,7 @@ pub enum ControlFlow { #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Try for ControlFlow { +const impl ops::Try for ControlFlow { type Output = C; type Residual = ControlFlow; @@ -124,7 +124,7 @@ impl const ops::Try for ControlFlow { #[rustc_const_unstable(feature = "const_try", issue = "74935")] // Note: manually specifying the residual type instead of using the default to work around // https://github.com/rust-lang/rust/issues/99940 -impl const ops::FromResidual> for ControlFlow { +const impl ops::FromResidual> for ControlFlow { #[inline] fn from_residual(residual: ControlFlow) -> Self { match residual { @@ -134,7 +134,8 @@ impl const ops::FromResidual> for Cont } #[unstable(feature = "try_trait_v2_residual", issue = "91285")] -impl ops::Residual for ControlFlow { +#[rustc_const_unstable(feature = "const_try_residual", issue = "91285")] +const impl ops::Residual for ControlFlow { type TryType = ControlFlow; } @@ -261,8 +262,8 @@ impl ControlFlow { /// assert_eq!(res, Ok(&5)); /// ``` #[inline] - #[stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "control_flow_ok", since = "1.96.0")] + #[rustc_const_stable(feature = "control_flow_ok", since = "1.96.0")] #[rustc_allow_const_fn_unstable(const_precise_live_drops)] pub const fn break_ok(self) -> Result { match self { @@ -373,8 +374,8 @@ impl ControlFlow { /// assert_eq!(res, Err("too big value detected")); /// ``` #[inline] - #[stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "control_flow_ok", since = "1.96.0")] + #[rustc_const_stable(feature = "control_flow_ok", since = "1.96.0")] #[rustc_allow_const_fn_unstable(const_precise_live_drops)] pub const fn continue_ok(self) -> Result { match self { @@ -426,7 +427,11 @@ impl ControlFlow { impl ControlFlow { /// Creates a `ControlFlow` from any type implementing `Try`. #[inline] - pub(crate) fn from_try(r: R) -> Self { + #[rustc_const_unstable(feature = "const_control_flow", issue = "148739")] + pub(crate) const fn from_try(r: R) -> Self + where + R: [const] ops::Try, + { match R::branch(r) { ControlFlow::Continue(v) => ControlFlow::Continue(v), ControlFlow::Break(v) => ControlFlow::Break(R::from_residual(v)), @@ -435,7 +440,11 @@ impl ControlFlow { /// Converts a `ControlFlow` into any type implementing `Try`. #[inline] - pub(crate) fn into_try(self) -> R { + #[rustc_const_unstable(feature = "const_control_flow", issue = "148739")] + pub(crate) const fn into_try(self) -> R + where + R: [const] ops::Try, + { match self { ControlFlow::Continue(v) => R::from_output(v), ControlFlow::Break(v) => v, diff --git a/core/src/ops/deref.rs b/core/src/ops/deref.rs index 305861ea7b698..58bf0e2d73b97 100644 --- a/core/src/ops/deref.rs +++ b/core/src/ops/deref.rs @@ -152,7 +152,7 @@ pub const trait Deref: PointeeSized { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for &T { +const impl Deref for &T { type Target = T; #[rustc_diagnostic_item = "noop_method_deref"] @@ -166,7 +166,7 @@ impl !DerefMut for &T {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for &mut T { +const impl Deref for &mut T { type Target = T; fn deref(&self) -> &T { @@ -276,7 +276,7 @@ pub const trait DerefMut: [const] Deref + PointeeSized { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for &mut T { +const impl DerefMut for &mut T { fn deref_mut(&mut self) -> &mut T { self } @@ -293,6 +293,7 @@ impl const DerefMut for &mut T { /// unchanged. #[unstable(feature = "deref_pure_trait", issue = "87121")] #[lang = "deref_pure"] +#[rustc_dyn_incompatible_trait] pub unsafe trait DerefPure: PointeeSized {} #[unstable(feature = "deref_pure_trait", issue = "87121")] diff --git a/core/src/ops/drop.rs b/core/src/ops/drop.rs index 7125bf54701bb..138460d54cf99 100644 --- a/core/src/ops/drop.rs +++ b/core/src/ops/drop.rs @@ -1,3 +1,5 @@ +use crate::pin::Pin; + /// Custom code within the destructor. /// /// When a value is no longer needed, Rust will run a "destructor" on that value. @@ -237,5 +239,30 @@ pub const trait Drop { /// [`mem::drop`]: drop /// [`ptr::drop_in_place`]: crate::ptr::drop_in_place #[stable(feature = "rust1", since = "1.0.0")] - fn drop(&mut self); + #[rustc_default_body_unstable(feature = "pin_ergonomics", issue = "130494")] + fn drop(&mut self) { + // SAFETY: `self` is pinned till after dropped. + unsafe { Drop::pin_drop(Pin::new_unchecked(self)) } + } + + /// Execute the destructor for this type, but different to [`Drop::drop`], it requires `self` + /// to be pinned. + /// + /// By implementing this method instead of [`Drop::drop`], the receiver type [`Pin<&mut Self>`] + /// makes sure that the value is pinned until it is deallocated (See [`std::pin` module docs] for + /// more details), which enables us to support field projections of `Self` type safely. + /// + /// For types that support pin-projection (i.e., marked with `#[pin_v2]`), this method must be used. + /// + /// For any type, at least and at most one of [`Drop::drop`] and [`Drop::pin_drop`] should be + /// implemented. + /// + /// See also [`Drop::drop`] for more details. + /// + /// [`Drop::drop`]: crate::ops::Drop::drop + /// [`Drop::pin_drop`]: crate::ops::Drop::pin_drop + /// [`Pin<&mut Self>`]: crate::pin::Pin + /// [`std::pin` module docs]: crate::pin + #[unstable(feature = "pin_ergonomics", issue = "130494")] + fn pin_drop(self: Pin<&mut Self>) {} } diff --git a/core/src/ops/function.rs b/core/src/ops/function.rs index efe5c0871fb8b..25664a51a1d7b 100644 --- a/core/src/ops/function.rs +++ b/core/src/ops/function.rs @@ -67,8 +67,8 @@ use crate::marker::Tuple; // SAFETY: tidy is not smart enough to tell that the below unsafe block is a string label = "call the function in a closure: `|| unsafe {{ /* code */ }}`" ), - message = "expected a `{Trait}` closure, found `{Self}`", - label = "expected an `{Trait}` closure, found `{Self}`" + message = "expected a `{This:resolved}` closure, found `{Self}`", + label = "expected an `{This:resolved}` closure, found `{Self}`" )] #[fundamental] // so that regex can rely that `&str: !FnMut` #[must_use = "closures are lazy and do nothing unless called"] @@ -154,8 +154,8 @@ pub const trait Fn: [const] FnMut { // SAFETY: tidy is not smart enough to tell that the below unsafe block is a string label = "call the function in a closure: `|| unsafe {{ /* code */ }}`" ), - message = "expected a `{Trait}` closure, found `{Self}`", - label = "expected an `{Trait}` closure, found `{Self}`" + message = "expected a `{This:resolved}` closure, found `{Self}`", + label = "expected an `{This:resolved}` closure, found `{Self}`" )] #[fundamental] // so that regex can rely that `&str: !FnMut` #[must_use = "closures are lazy and do nothing unless called"] @@ -233,8 +233,8 @@ pub const trait FnMut: FnOnce { // SAFETY: tidy is not smart enough to tell that the below unsafe block is a string label = "call the function in a closure: `|| unsafe {{ /* code */ }}`" ), - message = "expected a `{Trait}` closure, found `{Self}`", - label = "expected an `{Trait}` closure, found `{Self}`" + message = "expected a `{This:resolved}` closure, found `{Self}`", + label = "expected an `{This:resolved}` closure, found `{Self}`" )] #[fundamental] // so that regex can rely that `&str: !FnMut` #[must_use = "closures are lazy and do nothing unless called"] @@ -255,7 +255,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const Fn for &F + const impl Fn for &F where F: [const] Fn, { @@ -266,7 +266,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const FnMut for &F + const impl FnMut for &F where F: [const] Fn, { @@ -277,7 +277,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const FnOnce for &F + const impl FnOnce for &F where F: [const] Fn, { @@ -290,7 +290,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const FnMut for &mut F + const impl FnMut for &mut F where F: [const] FnMut, { @@ -301,7 +301,7 @@ mod impls { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] - impl const FnOnce for &mut F + const impl FnOnce for &mut F where F: [const] FnMut, { diff --git a/core/src/ops/mod.rs b/core/src/ops/mod.rs index ab1ad407ee282..87dd873fdb57d 100644 --- a/core/src/ops/mod.rs +++ b/core/src/ops/mod.rs @@ -149,7 +149,6 @@ mod function; mod index; mod index_range; mod range; -mod reborrow; mod try_trait; mod unsize; @@ -190,8 +189,6 @@ pub use self::range::{Bound, RangeBounds, RangeInclusive, RangeToInclusive}; pub use self::range::{OneSidedRange, OneSidedRangeBound}; #[stable(feature = "rust1", since = "1.0.0")] pub use self::range::{Range, RangeFrom, RangeFull, RangeTo}; -#[unstable(feature = "reborrow", issue = "145612")] -pub use self::reborrow::{CoerceShared, Reborrow}; #[unstable(feature = "try_trait_v2_residual", issue = "91285")] pub use self::try_trait::Residual; #[unstable(feature = "try_trait_v2_yeet", issue = "96374")] diff --git a/core/src/ops/range.rs b/core/src/ops/range.rs index c15c8f20c16be..1875aca947098 100644 --- a/core/src/ops/range.rs +++ b/core/src/ops/range.rs @@ -1045,7 +1045,7 @@ use self::Bound::{Excluded, Included, Unbounded}; #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFull { +const impl RangeBounds for RangeFull { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1056,7 +1056,7 @@ impl const RangeBounds for RangeFull { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeFull { +const impl IntoBounds for RangeFull { fn into_bounds(self) -> (Bound, Bound) { (Unbounded, Unbounded) } @@ -1064,7 +1064,7 @@ impl const IntoBounds for RangeFull { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFrom { +const impl RangeBounds for RangeFrom { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -1075,7 +1075,7 @@ impl const RangeBounds for RangeFrom { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeFrom { +const impl IntoBounds for RangeFrom { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Unbounded) } @@ -1083,7 +1083,7 @@ impl const IntoBounds for RangeFrom { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeTo { +const impl RangeBounds for RangeTo { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1094,7 +1094,7 @@ impl const RangeBounds for RangeTo { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeTo { +const impl IntoBounds for RangeTo { fn into_bounds(self) -> (Bound, Bound) { (Unbounded, Excluded(self.end)) } @@ -1102,7 +1102,7 @@ impl const IntoBounds for RangeTo { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for Range { +const impl RangeBounds for Range { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -1113,7 +1113,7 @@ impl const RangeBounds for Range { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for Range { +const impl IntoBounds for Range { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Excluded(self.end)) } @@ -1121,7 +1121,7 @@ impl const IntoBounds for Range { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeInclusive { +const impl RangeBounds for RangeInclusive { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -1138,7 +1138,7 @@ impl const RangeBounds for RangeInclusive { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeInclusive { +const impl IntoBounds for RangeInclusive { fn into_bounds(self) -> (Bound, Bound) { ( Included(self.start), @@ -1155,7 +1155,7 @@ impl const IntoBounds for RangeInclusive { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeToInclusive { +const impl RangeBounds for RangeToInclusive { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1166,7 +1166,7 @@ impl const RangeBounds for RangeToInclusive { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeToInclusive { +const impl IntoBounds for RangeToInclusive { fn into_bounds(self) -> (Bound, Bound) { (Unbounded, Included(self.end)) } @@ -1174,7 +1174,7 @@ impl const IntoBounds for RangeToInclusive { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for (Bound, Bound) { +const impl RangeBounds for (Bound, Bound) { fn start_bound(&self) -> Bound<&T> { match *self { (Included(ref start), _) => Included(start), @@ -1194,7 +1194,7 @@ impl const RangeBounds for (Bound, Bound) { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for (Bound, Bound) { +const impl IntoBounds for (Bound, Bound) { fn into_bounds(self) -> (Bound, Bound) { self } @@ -1202,7 +1202,7 @@ impl const IntoBounds for (Bound, Bound) { #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl<'a, T: ?Sized + 'a> const RangeBounds for (Bound<&'a T>, Bound<&'a T>) { +const impl<'a, T: ?Sized + 'a> RangeBounds for (Bound<&'a T>, Bound<&'a T>) { fn start_bound(&self) -> Bound<&T> { self.0 } @@ -1220,7 +1220,7 @@ impl<'a, T: ?Sized + 'a> const RangeBounds for (Bound<&'a T>, Bound<&'a T>) { /// i.e. replace `start..` with `(Bound::Included(start), Bound::Unbounded)`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFrom<&T> { +const impl RangeBounds for RangeFrom<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -1237,7 +1237,7 @@ impl const RangeBounds for RangeFrom<&T> { /// i.e. replace `..end` with `(Bound::Unbounded, Bound::Excluded(end))`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeTo<&T> { +const impl RangeBounds for RangeTo<&T> { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1254,7 +1254,7 @@ impl const RangeBounds for RangeTo<&T> { /// i.e. replace `start..end` with `(Bound::Included(start), Bound::Excluded(end))`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for Range<&T> { +const impl RangeBounds for Range<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -1271,7 +1271,7 @@ impl const RangeBounds for Range<&T> { /// i.e. replace `start..=end` with `(Bound::Included(start), Bound::Included(end))`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeInclusive<&T> { +const impl RangeBounds for RangeInclusive<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -1288,7 +1288,7 @@ impl const RangeBounds for RangeInclusive<&T> { /// i.e. replace `..=end` with `(Bound::Unbounded, Bound::Included(end))`. #[stable(feature = "collections_range", since = "1.28.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeToInclusive<&T> { +const impl RangeBounds for RangeToInclusive<&T> { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -1326,7 +1326,7 @@ pub const trait OneSidedRange: RangeBounds { #[unstable(feature = "one_sided_range", issue = "69780")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const OneSidedRange for RangeTo +const impl OneSidedRange for RangeTo where Self: RangeBounds, { @@ -1337,7 +1337,7 @@ where #[unstable(feature = "one_sided_range", issue = "69780")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const OneSidedRange for RangeFrom +const impl OneSidedRange for RangeFrom where Self: RangeBounds, { @@ -1348,7 +1348,7 @@ where #[unstable(feature = "one_sided_range", issue = "69780")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const OneSidedRange for RangeToInclusive +const impl OneSidedRange for RangeToInclusive where Self: RangeBounds, { diff --git a/core/src/ops/reborrow.rs b/core/src/ops/reborrow.rs deleted file mode 100644 index f83f4233a4de5..0000000000000 --- a/core/src/ops/reborrow.rs +++ /dev/null @@ -1,16 +0,0 @@ -/// Allows value to be reborrowed as exclusive, creating a copy of the value -/// that disables the source for reads and writes for the lifetime of the copy. -#[lang = "reborrow"] -#[unstable(feature = "reborrow", issue = "145612")] -pub trait Reborrow { - // Empty. -} - -/// Allows reborrowable value to be reborrowed as shared, creating a copy -/// that disables the source for writes for the lifetime of the copy. -#[lang = "coerce_shared"] -#[unstable(feature = "reborrow", issue = "145612")] -pub trait CoerceShared: Reborrow { - /// The type of this value when reborrowed as shared. - type Target: Copy; -} diff --git a/core/src/ops/try_trait.rs b/core/src/ops/try_trait.rs index 34000f6d6b218..f7486cddaae5d 100644 --- a/core/src/ops/try_trait.rs +++ b/core/src/ops/try_trait.rs @@ -1,4 +1,4 @@ -use crate::marker::{Destruct, PhantomData}; +use crate::marker::Destruct; use crate::ops::ControlFlow; /// The `?` operator and `try {}` blocks. @@ -157,7 +157,7 @@ pub const trait Try: [const] FromResidual { /// type: that type will have a "hole" in the correct place, and will maintain the /// "foo-ness" of the residual so other types need to opt-in to interconversion. #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] - type Residual; + type Residual: Residual; /// Constructs the type from its `Output` type. /// @@ -398,25 +398,6 @@ pub(crate) type ChangeOutputType>, V> = /// Not currently planned to be exposed publicly, so just `pub(crate)`. #[repr(transparent)] pub(crate) struct NeverShortCircuit(pub T); -// FIXME(const-hack): replace with `|a| NeverShortCircuit(f(a))` when const closures added. -pub(crate) struct Wrapped T> { - f: F, - p: PhantomData<(T, A)>, -} -#[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl T + [const] Destruct> const FnOnce<(A,)> for Wrapped { - type Output = NeverShortCircuit; - - extern "rust-call" fn call_once(mut self, args: (A,)) -> Self::Output { - self.call_mut(args) - } -} -#[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl T> const FnMut<(A,)> for Wrapped { - extern "rust-call" fn call_mut(&mut self, (args,): (A,)) -> Self::Output { - NeverShortCircuit((self.f)(args)) - } -} impl NeverShortCircuit { /// Wraps a unary function to produce one that wraps the output into a `NeverShortCircuit`. @@ -424,23 +405,32 @@ impl NeverShortCircuit { /// This is useful for implementing infallible functions in terms of the `try_` ones, /// without accidentally capturing extra generic parameters in a closure. #[inline] - pub(crate) const fn wrap_mut_1(f: F) -> Wrapped + #[rustc_const_unstable(feature = "const_array", issue = "147606")] + pub(crate) const fn wrap_mut_1( + mut f: F, + ) -> impl [const] FnMut(A) -> Self + [const] Destruct where - F: [const] FnMut(A) -> T, + F: [const] FnMut(A) -> T + [const] Destruct, { - Wrapped { f, p: PhantomData } + const move |a| NeverShortCircuit(f(a)) } #[inline] - pub(crate) fn wrap_mut_2(mut f: impl FnMut(A, B) -> T) -> impl FnMut(A, B) -> Self { - move |a, b| NeverShortCircuit(f(a, b)) + #[rustc_const_unstable(feature = "const_array", issue = "147606")] + pub(crate) const fn wrap_mut_2( + mut f: F, + ) -> impl [const] FnMut(A, B) -> Self + [const] Destruct + where + F: [const] FnMut(A, B) -> T + [const] Destruct, + { + const move |a, b| NeverShortCircuit(f(a, b)) } } pub(crate) enum NeverShortCircuitResidual {} #[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl const Try for NeverShortCircuit { +const impl Try for NeverShortCircuit { type Output = T; type Residual = NeverShortCircuitResidual; @@ -455,14 +445,14 @@ impl const Try for NeverShortCircuit { } } #[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl const FromResidual for NeverShortCircuit { +const impl FromResidual for NeverShortCircuit { #[inline] fn from_residual(never: NeverShortCircuitResidual) -> Self { match never {} } } #[rustc_const_unstable(feature = "const_never_short_circuit", issue = "none")] -impl const Residual for NeverShortCircuitResidual { +const impl Residual for NeverShortCircuitResidual { type TryType = NeverShortCircuit; } diff --git a/core/src/ops/unsize.rs b/core/src/ops/unsize.rs index f0781ee01fd53..45a6e973ca716 100644 --- a/core/src/ops/unsize.rs +++ b/core/src/ops/unsize.rs @@ -33,7 +33,7 @@ use crate::marker::{PointeeSized, Unsize}; /// [nomicon-coerce]: ../../nomicon/coercions.html #[unstable(feature = "coerce_unsized", issue = "18598")] #[lang = "coerce_unsized"] -pub trait CoerceUnsized { +pub trait CoerceUnsized: Sized { // Empty. } @@ -116,7 +116,7 @@ impl, U: PointeeSized> CoerceUnsized<*const U> for * /// [^1]: Formerly known as *object safety*. #[unstable(feature = "dispatch_from_dyn", issue = "none")] #[lang = "dispatch_from_dyn"] -pub trait DispatchFromDyn { +pub trait DispatchFromDyn: Sized { // Empty. } diff --git a/core/src/option.rs b/core/src/option.rs index d4dd33b948193..a490a26aa0ff3 100644 --- a/core/src/option.rs +++ b/core/src/option.rs @@ -40,9 +40,6 @@ //! } //! ``` //! -// -// FIXME: Show how `Option` is used in practice, with lots of methods -// //! # Options and pointers ("nullable" pointers) //! //! Rust's pointer types must always point to a valid location; there are @@ -1751,8 +1748,12 @@ impl Option { /// ``` #[inline] #[stable(feature = "option_entry", since = "1.20.0")] - pub fn get_or_insert(&mut self, value: T) -> &mut T { - self.get_or_insert_with(|| value) + #[rustc_const_unstable(feature = "const_option_ops", issue = "143956")] + pub const fn get_or_insert(&mut self, value: T) -> &mut T + where + T: [const] Destruct, + { + self.get_or_insert_with(const || value) } /// Inserts the default value into the option if it is [`None`], then @@ -1959,7 +1960,7 @@ impl Option { mem::replace(self, Some(value)) } - /// Zips `self` with another `Option`. + /// Makes a tuple of the value in `self` and the value in another `Option`. /// /// If `self` is `Some(s)` and `other` is `Some(o)`, this method returns `Some((s, o))`. /// Otherwise, `None` is returned. @@ -1987,7 +1988,7 @@ impl Option { } } - /// Zips `self` and another `Option` with function `f`. + /// Combines the value in `self` with the value in another `Option`, using the function `f`. /// /// If `self` is `Some(s)` and `other` is `Some(o)`, this method returns `Some(f(s, o))`. /// Otherwise, `None` is returned. @@ -2266,7 +2267,7 @@ const fn expect_failed(msg: &str) -> ! { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -impl const Clone for Option +const impl Clone for Option where // FIXME(const_hack): the T: [const] Destruct should be inferred from the Self: [const] Destruct in clone_from. // See https://github.com/rust-lang/rust/issues/144207 @@ -2295,11 +2296,11 @@ impl crate::clone::UseCloned for Option where T: crate::clone::UseCloned { #[doc(hidden)] #[unstable(feature = "trivial_clone", issue = "none")] #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -unsafe impl const TrivialClone for Option where T: [const] TrivialClone + [const] Destruct {} +const unsafe impl TrivialClone for Option where T: [const] TrivialClone + [const] Destruct {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Option { +const impl Default for Option { /// Returns [`None`][Option::None]. /// /// # Examples @@ -2316,7 +2317,7 @@ impl const Default for Option { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_iter", issue = "92476")] -impl const IntoIterator for Option { +const impl IntoIterator for Option { type Item = T; type IntoIter = IntoIter; @@ -2361,7 +2362,7 @@ impl<'a, T> IntoIterator for &'a mut Option { #[stable(since = "1.12.0", feature = "option_from")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Option { +const impl From for Option { /// Moves `val` into a new [`Some`]. /// /// # Examples @@ -2378,7 +2379,7 @@ impl const From for Option { #[stable(feature = "option_ref_from_ref_option", since = "1.30.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a, T> const From<&'a Option> for Option<&'a T> { +const impl<'a, T> From<&'a Option> for Option<&'a T> { /// Converts from `&Option` to `Option<&T>`. /// /// # Examples @@ -2406,7 +2407,7 @@ impl<'a, T> const From<&'a Option> for Option<&'a T> { #[stable(feature = "option_ref_from_ref_option", since = "1.30.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl<'a, T> const From<&'a mut Option> for Option<&'a mut T> { +const impl<'a, T> From<&'a mut Option> for Option<&'a mut T> { /// Converts from `&mut Option` to `Option<&mut T>` /// /// # Examples @@ -2434,7 +2435,7 @@ impl<'a, T> const From<&'a mut Option> for Option<&'a mut T> { impl crate::marker::StructuralPartialEq for Option {} #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for Option { +const impl PartialEq for Option { #[inline] fn eq(&self, other: &Self) -> bool { // Spelling out the cases explicitly optimizes better than @@ -2453,7 +2454,7 @@ impl const PartialEq for Option { // not optimal. #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for Option { +const impl PartialOrd for Option { #[inline] fn partial_cmp(&self, other: &Self) -> Option { match (self, other) { @@ -2467,7 +2468,7 @@ impl const PartialOrd for Option { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for Option { +const impl Ord for Option { #[inline] fn cmp(&self, other: &Self) -> cmp::Ordering { match (self, other) { @@ -2489,7 +2490,7 @@ struct Item { } #[rustc_const_unstable(feature = "const_iter", issue = "92476")] -impl const Iterator for Item { +const impl Iterator for Item { type Item = A; #[inline] @@ -2624,7 +2625,7 @@ pub struct IntoIter { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_iter", issue = "92476")] -impl const Iterator for IntoIter { +const impl Iterator for IntoIter { type Item = A; #[inline] @@ -2652,7 +2653,8 @@ impl ExactSizeIterator for IntoIter {} impl FusedIterator for IntoIter {} #[unstable(feature = "trusted_len", issue = "37572")] -unsafe impl TrustedLen for IntoIter {} +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const unsafe impl TrustedLen for IntoIter {} /// The iterator produced by [`Option::into_flat_iter`]. See its documentation for more. #[derive(Clone, Debug)] @@ -2764,7 +2766,7 @@ impl> FromIterator> for Option { #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Try for Option { +const impl ops::Try for Option { type Output = T; type Residual = Option; @@ -2786,7 +2788,7 @@ impl const ops::Try for Option { #[rustc_const_unstable(feature = "const_try", issue = "74935")] // Note: manually specifying the residual type instead of using the default to work around // https://github.com/rust-lang/rust/issues/99940 -impl const ops::FromResidual> for Option { +const impl ops::FromResidual> for Option { #[inline] fn from_residual(residual: Option) -> Self { match residual { @@ -2798,7 +2800,7 @@ impl const ops::FromResidual> for Option { #[diagnostic::do_not_recommend] #[unstable(feature = "try_trait_v2_yeet", issue = "96374")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::FromResidual> for Option { +const impl ops::FromResidual> for Option { #[inline] fn from_residual(ops::Yeet(()): ops::Yeet<()>) -> Self { None @@ -2807,7 +2809,7 @@ impl const ops::FromResidual> for Option { #[unstable(feature = "try_trait_v2_residual", issue = "91285")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Residual for Option { +const impl ops::Residual for Option { type TryType = Option; } diff --git a/core/src/panic/unwind_safe.rs b/core/src/panic/unwind_safe.rs index 20f85b5ca9cd8..bf2e61dc541c6 100644 --- a/core/src/panic/unwind_safe.rs +++ b/core/src/panic/unwind_safe.rs @@ -250,7 +250,7 @@ impl RefUnwindSafe for crate::sync::atomic::AtomicPtr {} #[stable(feature = "catch_unwind", since = "1.9.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for AssertUnwindSafe { +const impl Deref for AssertUnwindSafe { type Target = T; fn deref(&self) -> &T { @@ -260,7 +260,7 @@ impl const Deref for AssertUnwindSafe { #[stable(feature = "catch_unwind", since = "1.9.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const DerefMut for AssertUnwindSafe { +const impl DerefMut for AssertUnwindSafe { fn deref_mut(&mut self) -> &mut T { &mut self.0 } @@ -317,7 +317,7 @@ impl AsyncIterator for AssertUnwindSafe { /// If a value's type is already `UnwindSafe`, /// wrapping it in `AssertUnwindSafe` is never incorrect. -#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] impl From for AssertUnwindSafe where T: UnwindSafe, diff --git a/core/src/pat.rs b/core/src/pat.rs index 2670c2614198c..77fbea510e782 100644 --- a/core/src/pat.rs +++ b/core/src/pat.rs @@ -64,7 +64,7 @@ impl_range_pat! { } #[rustc_const_unstable(feature = "pattern_type_range_trait", issue = "123646")] -impl const RangePattern for char { +const impl RangePattern for char { const MIN: Self = char::MIN; const MAX: Self = char::MAX; diff --git a/core/src/pin.rs b/core/src/pin.rs index ffdcd9fad49a5..40f774806046a 100644 --- a/core/src/pin.rs +++ b/core/src/pin.rs @@ -474,9 +474,9 @@ //! //! In an intrusive doubly-linked list, the collection itself does not own the memory in which //! each of its elements is stored. Instead, each client is free to allocate space for elements it -//! adds to the list in whichever manner it likes, including on the stack! Elements can live on a -//! stack frame that lives shorter than the collection does provided the elements that live in a -//! given stack frame are removed from the list before going out of scope. +//! adds to the list in whichever manner it likes, including on the stack! Elements can be stored +//! in a stack frame shorter-lived than the collection, provided they are removed from the list +//! before that frame goes out of scope. //! //! To make such an intrusive data structure work, every element stores pointers to its predecessor //! and successor within its own data, rather than having the list structure itself managing those @@ -740,7 +740,7 @@ //! //! While counter-intuitive, it's often the easier choice: if you do not expose a //! [Pin]<[&mut] Field>, you do not need to be careful about other code -//! moving out of that field, you just have to ensure is that you never create pinning +//! moving out of that field, you just have to ensure that you never create a pinning //! reference to that field. This does of course also mean that if you decide a field does not //! have structural pinning, you must not write [`unsafe`] code that assumes (invalidly) that the //! field *is* structurally pinned! @@ -1680,7 +1680,7 @@ impl Pin<&'static mut T> { #[stable(feature = "pin", since = "1.33.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const Deref for Pin { +const impl Deref for Pin { type Target = Ptr::Target; fn deref(&self) -> &Ptr::Target { Pin::get_ref(Pin::as_ref(self)) @@ -1723,7 +1723,7 @@ mod helper { #[unstable(feature = "pin_derefmut_internals", issue = "none")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] - impl const PinDerefMutHelper for PinHelper + const impl PinDerefMutHelper for PinHelper where Ptr::Target: crate::marker::Unpin, { @@ -1739,7 +1739,7 @@ mod helper { #[stable(feature = "pin", since = "1.33.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[cfg(not(doc))] -impl const DerefMut for Pin +const impl DerefMut for Pin where Ptr: [const] Deref, helper::PinHelper: [const] helper::PinDerefMutHelper, @@ -1765,7 +1765,7 @@ where #[stable(feature = "pin", since = "1.33.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] #[cfg(doc)] -impl const DerefMut for Pin +const impl DerefMut for Pin where Ptr: [const] DerefMut, ::Target: Unpin, @@ -2021,14 +2021,29 @@ unsafe impl PinCoerceUnsized for Pin {} /// [`Box::pin`]: ../../std/boxed/struct.Box.html#method.pin #[stable(feature = "pin_macro", since = "1.68.0")] #[rustc_macro_transparency = "semiopaque"] -#[allow_internal_unstable(super_let)] +#[allow_internal_unstable(pin_macro_internals, super_let)] #[rustc_diagnostic_item = "pin_macro"] // `super` gets removed by rustfmt #[rustfmt::skip] pub macro pin($value:expr $(,)?) { - { + 'p: { super let mut pinned = $value; // SAFETY: The value is pinned: it is the local above which cannot be named outside this macro. - unsafe { $crate::pin::Pin::new_unchecked(&mut pinned) } + break 'p unsafe { $crate::pin::Pin::new_unchecked(&mut pinned) }; + + // HACK: We need to ensure that, given `$value: T`, `pin!($value)` has type `Pin<&mut T>`. + // Otherwise, it's possible for a type annotation on the result of `pin!` to unsoundly add + // deref coercions. E.g. for `$value: &mut T`, we could get `pin!($value): Pin<&mut T>`, + // violating the pinning invariant; see . + #[expect(unreachable_code)] + $crate::pin::unreachable_pin_macro_type_constraint(pinned) } } + +/// Helper for `pin!` to enforce its type signature. +/// See . +#[unstable(feature = "pin_macro_internals", issue = "none")] +#[doc(hidden)] +pub fn unreachable_pin_macro_type_constraint<'a, T>(_: T) -> Pin<&'a mut T> { + unreachable!() +} diff --git a/core/src/pin/unsafe_pinned.rs b/core/src/pin/unsafe_pinned.rs index ae03809b4581f..483cf529798b1 100644 --- a/core/src/pin/unsafe_pinned.rs +++ b/core/src/pin/unsafe_pinned.rs @@ -149,7 +149,7 @@ impl Default for UnsafePinned { #[unstable(feature = "unsafe_pinned", issue = "125735")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for UnsafePinned { +const impl From for UnsafePinned { /// Creates a new `UnsafePinned` containing the given value. fn from(value: T) -> Self { UnsafePinned::new(value) diff --git a/core/src/prelude/v1.rs b/core/src/prelude/v1.rs index f2eb047d342bc..6122ab12ec351 100644 --- a/core/src/prelude/v1.rs +++ b/core/src/prelude/v1.rs @@ -120,9 +120,13 @@ pub use crate::trace_macros; // (no public module for them to be re-exported from). #[stable(feature = "builtin_macro_prelude", since = "1.38.0")] pub use crate::macros::builtin::{ - alloc_error_handler, bench, derive, global_allocator, test, test_case, + alloc_error_handler, bench, global_allocator, test, test_case, }; +#[stable(feature = "builtin_macro_prelude", since = "1.38.0")] +#[doc(no_inline)] +pub use crate::macros::builtin::derive; + #[unstable(feature = "derive_const", issue = "118304")] pub use crate::macros::builtin::derive_const; diff --git a/core/src/primitive_docs.rs b/core/src/primitive_docs.rs index 3a4e1e657a3da..9efcabcf3f194 100644 --- a/core/src/primitive_docs.rs +++ b/core/src/primitive_docs.rs @@ -1777,7 +1777,7 @@ mod prim_ref {} /// However, a direct cast back is not possible. You need to use `transmute`: /// /// ```rust -/// # #[cfg(not(miri))] { // FIXME: use strict provenance APIs once they are stable, then remove this `cfg` +/// # #[cfg(not(miri))] { // disabled because it fails with -Zmiri-strict-provenance /// # let fnptr: fn(i32) -> i32 = |x| x+2; /// # let fnptr_addr = fnptr as usize; /// let fnptr = fnptr_addr as *const (); @@ -1794,6 +1794,7 @@ mod prim_ref {} /// have different sizes. /// /// ### ABI compatibility +/// [ABI compatibility]: #abi-compatibility /// /// Generally, when a function is declared with one signature and called via a function pointer with /// a different signature, the two signatures must be *ABI-compatible* or else calling the function @@ -1831,7 +1832,7 @@ mod prim_ref {} /// - `*const T`, `*mut T`, `&T`, `&mut T`, `Box` (specifically, only `Box`), and /// `NonNull` are all ABI-compatible with each other for all `T`. They are also ABI-compatible /// with each other for _different_ `T` if they have the same metadata type (`::Metadata`). +/// Pointee>::Metadata`). However, see the [Control Flow Integrity][cfi-docs] docs for caveats. /// - `usize` is ABI-compatible with the `uN` integer type of the same size, and likewise `isize` is /// ABI-compatible with the `iN` integer type of the same size. /// - `char` is ABI-compatible with `u32`. @@ -1890,6 +1891,8 @@ mod prim_ref {} /// Behavior since transmuting `None::>` to `NonZero` violates the non-zero /// requirement. /// +/// [cfi-docs]: https://doc.rust-lang.org/beta/unstable-book/compiler-flags/sanitizer.html#controlflowintegrity +/// /// ### Trait implementations /// /// In this documentation the shorthand `fn(T₁, T₂, …, Tₙ)` is used to represent non-variadic diff --git a/core/src/process.rs b/core/src/process.rs new file mode 100644 index 0000000000000..81481b2cba26e --- /dev/null +++ b/core/src/process.rs @@ -0,0 +1,43 @@ +//! A module for working with processes. +//! +//! Most process-related functionality requires std, but [`abort_immediate`] +//! is available on all targets. + +/// Terminates the process in a violent fashion. +/// +/// The function will never return and will immediately terminate the current +/// process in a platform specific "abnormal" manner. As a consequence, +/// no destructors on the current stack or any other thread's stack +/// will be run, Rust IO buffers (eg, from `BufWriter`) will not be flushed, +/// and C stdio buffers will not be flushed. +/// +/// Unlike [`abort`](../../std/process/fn.abort.html), `abort_immediate` does +/// not attempt to match C `abort()` or otherwise perform a "clean" abort. +/// Instead, it emits code that will crash the process with as little overhead +/// as possible, such as a "halt and catch fire" style instruction. You should +/// generally prefer using `abort` instead except where the absolute minimum +/// overhead is required. +/// +/// # Platform-specific behavior +/// +/// `abort_immediate` lowers to a trap instruction on *most* architectures; on +/// some architectures it simply lowers to call the unmangled `abort` function. +/// The exact behavior is architecture and system dependent. +/// +/// On bare-metal (no OS) systems the trap instruction usually causes a +/// *hardware* exception to be raised in a *synchronous* fashion; hardware +/// exceptions have nothing to do with C++ exceptions and are closer in +/// semantics to POSIX signals. +/// +/// On hosted applications (applications running under an OS), the trap +/// instruction *usually* terminates the whole process with an exit code that +/// corresponds to `SIGILL` or equivalent, *unless* this signal is handled. +/// Other signals such as `SIGABRT`, `SIGTRAP`, `SIGSEGV`, and `SIGBUS` may be +/// produced instead, depending on specifics. This is not an exhaustive list. +#[unstable(feature = "abort_immediate", issue = "154601")] +#[cold] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +#[doc(alias = "halt")] +pub fn abort_immediate() -> ! { + crate::intrinsics::abort() +} diff --git a/core/src/ptr/const_ptr.rs b/core/src/ptr/const_ptr.rs index 8b7b08bf82317..5cbbebf9f4788 100644 --- a/core/src/ptr/const_ptr.rs +++ b/core/src/ptr/const_ptr.rs @@ -1400,11 +1400,11 @@ impl *const T { /// /// ```rust /// #![feature(ptr_cast_slice)] + /// /// // create a slice pointer when starting out with a pointer to the first element /// let x = [5, 6, 7]; - /// let raw_pointer = x.as_ptr(); - /// let slice = raw_pointer.cast_slice(3); - /// assert_eq!(unsafe { &*slice }[2], 7); + /// let raw_slice = x.as_ptr().cast_slice(3); + /// assert_eq!(unsafe { &*raw_slice }[2], 7); /// ``` /// /// You must ensure that the pointer is valid and not null before dereferencing diff --git a/core/src/ptr/mod.rs b/core/src/ptr/mod.rs index ddeb1ccc72af7..ff2c18d685b65 100644 --- a/core/src/ptr/mod.rs +++ b/core/src/ptr/mod.rs @@ -262,16 +262,15 @@ //! [`with_addr`] method: //! //! ```text -//! /// Creates a new pointer with the given address. -//! /// -//! /// This performs the same operation as an `addr as ptr` cast, but copies -//! /// the *provenance* of `self` to the new pointer. -//! /// This allows us to dynamically preserve and propagate this important -//! /// information in a way that is otherwise impossible with a unary cast. -//! /// -//! /// This is equivalent to using `wrapping_offset` to offset `self` to the -//! /// given address, and therefore has all the same capabilities and restrictions. -//! pub fn with_addr(self, addr: usize) -> Self; +//! /// Creates a new pointer with the given address and the provenance of `self`. +//! /// +//! /// This is similar to a `addr as *const T` cast, +//! /// but copies the provenance of `self` to the new pointer. +//! /// This avoids the inherent ambiguity of the unary cast. +//! /// +//! /// This is equivalent to using `wrapping_offset` to offset `self` to the given address, +//! /// and therefore has all the same capabilities and restrictions. +//! pub fn with_addr(self, addr: usize) -> Self; //! ``` //! //! So you're still able to drop down to the address representation and do whatever @@ -413,7 +412,7 @@ use crate::num::NonZero; use crate::{fmt, hash, intrinsics, ub_checks}; #[unstable(feature = "ptr_alignment_type", issue = "102070")] -#[deprecated(since = "CURRENT_RUSTC_VERSION", note = "moved from `ptr` to `mem`")] +#[deprecated(since = "1.96.0", note = "moved from `ptr` to `mem`")] /// Deprecated re-export of [mem::Alignment]. pub type Alignment = mem::Alignment; @@ -802,20 +801,33 @@ pub const unsafe fn write_bytes(dst: *mut T, val: u8, count: usize) { /// // Ensure that the last item was dropped. /// assert!(weak.upgrade().is_none()); /// ``` +#[inline(always)] #[stable(feature = "drop_in_place", since = "1.8.0")] -#[lang = "drop_in_place"] -#[allow(unconditional_recursion)] #[rustc_diagnostic_item = "ptr_drop_in_place"] #[rustc_const_unstable(feature = "const_drop_in_place", issue = "109342")] pub const unsafe fn drop_in_place(to_drop: *mut T) +where + T: [const] Destruct, +{ + // Due to historic reasons, `drop_in_place` takes a pointer rather than a reference, + // which results in worse codegen since we don't apply noalias/dereferenceable llvm + // attributes to pointer arguments. To workaround this without breaking public + // interface, `drop_in_place` calls the lang item, rather than being one directly. + + // SAFETY: + // - compiler glue has the same safety requirements as this function + // - the pointer must be valid as per the safety requirement of this function + unsafe { drop_glue(&mut *to_drop) } +} + +/// Helper function for `drop_in_place`. The compiler replaces this by the actual drop glue. +#[lang = "drop_glue"] +pub(crate) const unsafe fn drop_glue(_: &mut T) where T: [const] Destruct, { // Code here does not matter - this is replaced by the // real drop glue by the compiler. - - // SAFETY: see comment above - unsafe { drop_in_place(to_drop) } } /// Creates a null raw pointer. @@ -2042,6 +2054,21 @@ pub const unsafe fn write_unaligned(dst: *mut T, src: T) { /// [allocation]: crate::ptr#allocated-object /// [atomic]: crate::sync::atomic#memory-model-for-atomic-accesses /// +/// # Load splitting +/// +/// Exactly which hardware loads are performed by this function is, in general, highly target-dependent. +/// +/// For a simple scalar, such as when `T` is a thin pointer, this will typically be one load assuming +/// your target supports a load of exactly that size and alignment. +/// +/// For anything else, it will be split into multiple loads in some unspecified way. +/// This can happen even for scalars: notably, on many targets loading a `u128` will still need to be split, +/// despite being "one" scalar. On many targets loading anything larger than a pointer will need to be split. +/// On all current targets a load larger than 64 bytes will need to be split. +/// Any load whose size is not a power of two will also almost certainly need to be split. +/// +/// There is no stability guarantee on how that splitting happens. It may change at any point. +/// /// # Safety /// /// Like [`read`], `read_volatile` creates a bitwise copy of `T`, regardless of whether `T` is @@ -2135,6 +2162,21 @@ pub unsafe fn read_volatile(src: *const T) -> T { /// [allocation]: crate::ptr#allocated-object /// [atomic]: crate::sync::atomic#memory-model-for-atomic-accesses /// +/// # Store splitting +/// +/// Exactly which hardware stores are performed by this function is, in general, highly target-dependent. +/// +/// For a simple scalar, such as when `T` is a thin pointer, this will typically be one store assuming +/// your target supports a store of exactly that size and alignment. +/// +/// For anything else, it will be split into multiple stores in some unspecified way. +/// This can happen even for scalars: notably, on many targets storing a `u128` will still need to be split, +/// despite being "one" scalar. On many targets storing anything larger than a pointer will need to be split. +/// On all current targets a store larger than 64 bytes will need to be split. +/// Any store whose size is not a power of two will also almost certainly need to be split. +/// +/// There is no stability guarantee on how that splitting happens. It may change at any point. +/// /// # Safety /// /// Behavior is undefined if any of the following conditions are violated: diff --git a/core/src/ptr/mut_ptr.rs b/core/src/ptr/mut_ptr.rs index 289dd972f679c..53ef7f754d201 100644 --- a/core/src/ptr/mut_ptr.rs +++ b/core/src/ptr/mut_ptr.rs @@ -594,7 +594,7 @@ impl *mut T { /// /// [`as_mut`]: #method.as_mut /// [`as_uninit_mut`]: #method.as_uninit_mut - /// [`as_ref_unchecked`]: #method.as_mut_unchecked + /// [`as_ref_unchecked`]: #method.as_ref_unchecked /// /// # Safety /// @@ -1675,13 +1675,13 @@ impl *mut T { /// #![feature(ptr_cast_slice)] /// /// let x = &mut [5, 6, 7]; - /// let slice = x.as_mut_ptr().cast_slice(3); + /// let raw_mut_slice = x.as_mut_ptr().cast_slice(3); /// /// unsafe { - /// (*slice)[2] = 99; // assign a value at an index in the slice + /// (*raw_mut_slice)[2] = 99; // assign a value at an index in the slice /// }; /// - /// assert_eq!(unsafe { &*slice }[2], 99); + /// assert_eq!(unsafe { &*raw_mut_slice }[2], 99); /// ``` /// /// You must ensure that the pointer is valid and not null before dereferencing @@ -1701,6 +1701,7 @@ impl *mut T { slice_from_raw_parts_mut(self, len) } } + impl *mut MaybeUninit { /// Casts from a maybe-uninitialized type to its initialized version. /// diff --git a/core/src/ptr/non_null.rs b/core/src/ptr/non_null.rs index 90f27ca8bdb0a..86e9d01381a51 100644 --- a/core/src/ptr/non_null.rs +++ b/core/src/ptr/non_null.rs @@ -69,13 +69,10 @@ use crate::{fmt, hash, intrinsics, mem, ptr}; /// [null pointer optimization]: crate::option#representation #[stable(feature = "nonnull", since = "1.25.0")] #[repr(transparent)] -#[rustc_layout_scalar_valid_range_start(1)] #[rustc_nonnull_optimization_guaranteed] #[rustc_diagnostic_item = "NonNull"] pub struct NonNull { - // Remember to use `.as_ptr()` instead of `.pointer`, as field projecting to - // this is banned by . - pointer: *const T, + pointer: crate::pattern_type!(*const T is !null), } /// `NonNull` pointers are not `Send` because the data they reference may be aliased. @@ -1119,12 +1116,12 @@ impl NonNull { #[inline(always)] #[stable(feature = "non_null_convenience", since = "1.80.0")] #[rustc_const_unstable(feature = "const_drop_in_place", issue = "109342")] - pub const unsafe fn drop_in_place(self) + pub const unsafe fn drop_in_place(mut self) where T: [const] Destruct, { // SAFETY: the caller must uphold the safety contract for `drop_in_place`. - unsafe { ptr::drop_in_place(self.as_ptr()) } + unsafe { ptr::drop_glue(self.as_mut()) } } /// Overwrites a memory location with the given value without reading or @@ -1447,7 +1444,7 @@ impl NonNull<[T]> { #[inline] pub const fn slice_from_raw_parts(data: NonNull, len: usize) -> Self { // SAFETY: `data` is a `NonNull` pointer which is necessarily non-null - unsafe { Self::new_unchecked(super::slice_from_raw_parts_mut(data.as_ptr(), len)) } + unsafe { Self::new_unchecked(data.as_ptr().cast_slice(len)) } } /// Returns the length of a non-null raw slice. @@ -1746,7 +1743,7 @@ impl hash::Hash for NonNull { #[unstable(feature = "ptr_internals", issue = "none")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for NonNull { +const impl From> for NonNull { #[inline] fn from(unique: Unique) -> Self { unique.as_non_null_ptr() @@ -1755,7 +1752,7 @@ impl const From> for NonNull { #[stable(feature = "nonnull", since = "1.25.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<&mut T> for NonNull { +const impl From<&mut T> for NonNull { /// Converts a `&mut T` to a `NonNull`. /// /// This conversion is safe and infallible since references cannot be null. @@ -1767,7 +1764,7 @@ impl const From<&mut T> for NonNull { #[stable(feature = "nonnull", since = "1.25.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<&T> for NonNull { +const impl From<&T> for NonNull { /// Converts a `&T` to a `NonNull`. /// /// This conversion is safe and infallible since references cannot be null. diff --git a/core/src/ptr/unique.rs b/core/src/ptr/unique.rs index 6e55f0e71bec7..dedabf7043cd6 100644 --- a/core/src/ptr/unique.rs +++ b/core/src/ptr/unique.rs @@ -191,7 +191,7 @@ impl fmt::Pointer for Unique { #[unstable(feature = "ptr_internals", issue = "none")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<&mut T> for Unique { +const impl From<&mut T> for Unique { /// Converts a `&mut T` to a `Unique`. /// /// This conversion is infallible since references cannot be null. @@ -203,7 +203,7 @@ impl const From<&mut T> for Unique { #[unstable(feature = "ptr_internals", issue = "none")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for Unique { +const impl From> for Unique { /// Converts a `NonNull` to a `Unique`. /// /// This conversion is infallible since `NonNull` cannot be null. diff --git a/core/src/range.rs b/core/src/range.rs index d4be1b67d3862..87e6ad6931249 100644 --- a/core/src/range.rs +++ b/core/src/range.rs @@ -24,13 +24,13 @@ mod iter; pub mod legacy; #[doc(inline)] -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] pub use iter::RangeFromIter; #[doc(inline)] #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub use iter::RangeInclusiveIter; #[doc(inline)] -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] pub use iter::RangeIter; // FIXME(#125687): re-exports temporarily removed @@ -47,10 +47,9 @@ use crate::iter::Step; use crate::ops::Bound::{self, Excluded, Included, Unbounded}; use crate::ops::{IntoBounds, OneSidedRange, OneSidedRangeBound, RangeBounds}; -/// A (half-open) range bounded inclusively below and exclusively above -/// (`start..end` in a future edition). +/// A (half-open) range bounded inclusively below and exclusively above. /// -/// The range `start..end` contains all values with `start <= x < end`. +/// The `Range` contains all values with `start <= x < end`. /// It is empty if `start >= end`. /// /// # Examples @@ -61,20 +60,25 @@ use crate::ops::{IntoBounds, OneSidedRange, OneSidedRangeBound, RangeBounds}; /// assert_eq!(Range::from(3..5), Range { start: 3, end: 5 }); /// assert_eq!(3 + 4 + 5, Range::from(3..6).into_iter().sum()); /// ``` +/// +/// # Edition notes +/// +/// It is planned that the syntax `start..end` will construct this +/// type in a future edition, but it does not do so today. #[lang = "RangeCopy"] #[derive(Copy, Hash)] #[derive_const(Clone, Default, PartialEq, Eq)] -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] pub struct Range { /// The lower bound of the range (inclusive). - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] pub start: Idx, /// The upper bound of the range (exclusive). - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] pub end: Idx, } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl fmt::Debug for Range { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -99,7 +103,7 @@ impl Range { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[inline] pub fn iter(&self) -> RangeIter { self.clone().into_iter() @@ -128,7 +132,7 @@ impl> Range { /// assert!(!Range::from(f32::NAN..1.0).contains(&0.5)); /// ``` #[inline] - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -160,7 +164,7 @@ impl> Range { /// assert!( Range::from(f32::NAN..5.0).is_empty()); /// ``` #[inline] - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn is_empty(&self) -> bool where @@ -170,9 +174,9 @@ impl> Range { } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for Range { +const impl RangeBounds for Range { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -187,9 +191,9 @@ impl const RangeBounds for Range { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..end` with `(Bound::Included(start), Bound::Excluded(end))`. -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for Range<&T> { +const impl RangeBounds for Range<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -200,44 +204,47 @@ impl const RangeBounds for Range<&T> { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for Range { +const impl IntoBounds for Range { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Excluded(self.end)) } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for legacy::Range { +const impl From> for legacy::Range { #[inline] fn from(value: Range) -> Self { Self { start: value.start, end: value.end } } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for Range { +const impl From> for Range { #[inline] fn from(value: legacy::Range) -> Self { Self { start: value.start, end: value.end } } } -/// A range bounded inclusively below and above (`start..=last`). +/// A range bounded inclusively below and above. /// -/// The `RangeInclusive` `start..=last` contains all values with `x >= start` +/// The `RangeInclusive` contains all values with `x >= start` /// and `x <= last`. It is empty unless `start <= last`. /// /// # Examples /// -/// The `start..=last` syntax is a `RangeInclusive`: -/// /// ``` /// use core::range::RangeInclusive; /// /// assert_eq!(RangeInclusive::from(3..=5), RangeInclusive { start: 3, last: 5 }); /// assert_eq!(3 + 4 + 5, RangeInclusive::from(3..=5).into_iter().sum()); /// ``` +/// +/// # Edition notes +/// +/// It is planned that the syntax `start..=last` will construct this +/// type in a future edition, but it does not do so today. #[lang = "RangeInclusiveCopy"] #[derive(Clone, Copy, PartialEq, Eq, Hash)] #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] @@ -349,7 +356,7 @@ impl RangeInclusive { #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeInclusive { +const impl RangeBounds for RangeInclusive { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -366,7 +373,7 @@ impl const RangeBounds for RangeInclusive { /// i.e. replace `start..=end` with `(Bound::Included(start), Bound::Included(end))`. #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeInclusive<&T> { +const impl RangeBounds for RangeInclusive<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -378,7 +385,7 @@ impl const RangeBounds for RangeInclusive<&T> { // #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeInclusive { +const impl IntoBounds for RangeInclusive { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Included(self.last)) } @@ -386,7 +393,7 @@ impl const IntoBounds for RangeInclusive { #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for legacy::RangeInclusive { +const impl From> for legacy::RangeInclusive { #[inline] fn from(value: RangeInclusive) -> Self { Self::new(value.start, value.last) @@ -394,7 +401,7 @@ impl const From> for legacy::RangeInclusive { } #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From> for RangeInclusive { +const impl From> for RangeInclusive { #[inline] fn from(value: legacy::RangeInclusive) -> Self { assert!( @@ -407,9 +414,9 @@ impl const From> for RangeInclusive { } } -/// A range only bounded inclusively below (`start..`). +/// A range only bounded inclusively below. /// -/// The `RangeFrom` `start..` contains all values with `x >= start`. +/// The `RangeFrom` contains all values with `x >= start`. /// /// *Note*: Overflow in the [`IntoIterator`] implementation (when the contained /// data type reaches its numerical limit) is allowed to panic, wrap, or @@ -423,25 +430,28 @@ impl const From> for RangeInclusive { /// /// # Examples /// -/// The `start..` syntax is a `RangeFrom`: -/// /// ``` /// use core::range::RangeFrom; /// /// assert_eq!(RangeFrom::from(2..), core::range::RangeFrom { start: 2 }); /// assert_eq!(2 + 3 + 4, RangeFrom::from(2..).into_iter().take(3).sum()); /// ``` +/// +/// # Edition notes +/// +/// It is planned that the syntax `start..` will construct this +/// type in a future edition, but it does not do so today. #[lang = "RangeFromCopy"] #[derive(Copy, Hash)] #[derive_const(Clone, PartialEq, Eq)] -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] pub struct RangeFrom { /// The lower bound of the range (inclusive). - #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] pub start: Idx, } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl fmt::Debug for RangeFrom { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -465,7 +475,7 @@ impl RangeFrom { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] #[inline] pub fn iter(&self) -> RangeFromIter { self.clone().into_iter() @@ -489,7 +499,7 @@ impl> RangeFrom { /// assert!(!RangeFrom::from(f32::NAN..).contains(&0.5)); /// ``` #[inline] - #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -500,9 +510,9 @@ impl> RangeFrom { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFrom { +const impl RangeBounds for RangeFrom { fn start_bound(&self) -> Bound<&T> { Included(&self.start) } @@ -517,9 +527,9 @@ impl const RangeBounds for RangeFrom { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..` with `(Bound::Included(start), Bound::Unbounded)`. -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeFrom<&T> { +const impl RangeBounds for RangeFrom<&T> { fn start_bound(&self) -> Bound<&T> { Included(self.start) } @@ -530,7 +540,7 @@ impl const RangeBounds for RangeFrom<&T> { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeFrom { +const impl IntoBounds for RangeFrom { fn into_bounds(self) -> (Bound, Bound) { (Included(self.start), Unbounded) } @@ -538,7 +548,7 @@ impl const IntoBounds for RangeFrom { #[unstable(feature = "one_sided_range", issue = "69780")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const OneSidedRange for RangeFrom +const impl OneSidedRange for RangeFrom where Self: RangeBounds, { @@ -547,32 +557,30 @@ where } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const From> for legacy::RangeFrom { +const impl From> for legacy::RangeFrom { #[inline] fn from(value: RangeFrom) -> Self { Self { start: value.start } } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const From> for RangeFrom { +const impl From> for RangeFrom { #[inline] fn from(value: legacy::RangeFrom) -> Self { Self { start: value.start } } } -/// A range only bounded inclusively above (`..=last`). +/// A range only bounded inclusively above. /// -/// The `RangeToInclusive` `..=last` contains all values with `x <= last`. +/// The `RangeToInclusive` contains all values with `x <= last`. /// It cannot serve as an [`Iterator`] because it doesn't have a starting point. /// /// # Examples /// -/// The `..=last` syntax is a `RangeToInclusive`: -/// /// ```standalone_crate /// #![feature(new_range)] /// assert_eq!((..=5), std::range::RangeToInclusive { last: 5 }); @@ -603,17 +611,22 @@ impl const From> for RangeFrom { /// ``` /// /// [slicing index]: crate::slice::SliceIndex +/// +/// # Edition notes +/// +/// It is planned that the syntax `..=last` will construct this +/// type in a future edition, but it does not do so today. #[lang = "RangeToInclusiveCopy"] #[doc(alias = "..=")] #[derive(Copy, Clone, PartialEq, Eq, Hash)] -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] pub struct RangeToInclusive { /// The upper bound of the range (inclusive) - #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] pub last: Idx, } -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl fmt::Debug for RangeToInclusive { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { write!(fmt, "..=")?; @@ -637,7 +650,7 @@ impl> RangeToInclusive { /// assert!(!(..=f32::NAN).contains(&0.5)); /// ``` #[inline] - #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -648,13 +661,13 @@ impl> RangeToInclusive { } } -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl From> for RangeToInclusive { fn from(value: legacy::RangeToInclusive) -> Self { Self { last: value.end } } } -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl From> for legacy::RangeToInclusive { fn from(value: RangeToInclusive) -> Self { Self { end: value.last } @@ -664,9 +677,9 @@ impl From> for legacy::RangeToInclusive { // RangeToInclusive cannot impl From> // because underflow would be possible with (..0).into() -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeToInclusive { +const impl RangeBounds for RangeToInclusive { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -675,9 +688,9 @@ impl const RangeBounds for RangeToInclusive { } } -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const RangeBounds for RangeToInclusive<&T> { +const impl RangeBounds for RangeToInclusive<&T> { fn start_bound(&self) -> Bound<&T> { Unbounded } @@ -688,7 +701,7 @@ impl const RangeBounds for RangeToInclusive<&T> { #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const IntoBounds for RangeToInclusive { +const impl IntoBounds for RangeToInclusive { fn into_bounds(self) -> (Bound, Bound) { (Unbounded, Included(self.last)) } @@ -696,7 +709,7 @@ impl const IntoBounds for RangeToInclusive { #[unstable(feature = "one_sided_range", issue = "69780")] #[rustc_const_unstable(feature = "const_range", issue = "none")] -impl const OneSidedRange for RangeToInclusive +const impl OneSidedRange for RangeToInclusive where Self: RangeBounds, { diff --git a/core/src/range/iter.rs b/core/src/range/iter.rs index a5db3699bc402..01b69554a0b1b 100644 --- a/core/src/range/iter.rs +++ b/core/src/range/iter.rs @@ -6,7 +6,7 @@ use crate::range::{Range, RangeFrom, RangeInclusive, legacy}; use crate::{intrinsics, mem}; /// By-value [`Range`] iterator. -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[derive(Debug, Clone)] pub struct RangeIter(legacy::Range); @@ -64,7 +64,7 @@ unsafe_range_trusted_random_access_impl! { u64 i64 } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl Iterator for RangeIter { type Item = A; @@ -132,7 +132,7 @@ impl Iterator for RangeIter { } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl DoubleEndedIterator for RangeIter { #[inline] fn next_back(&mut self) -> Option { @@ -153,10 +153,10 @@ impl DoubleEndedIterator for RangeIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeIter {} -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl FusedIterator for RangeIter {} -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl IntoIterator for Range { type Item = A; type IntoIter = RangeIter; @@ -299,7 +299,7 @@ impl IntoIterator for RangeInclusive { // since e.g. `(0..=u64::MAX).len()` would be `u64::MAX + 1`. macro_rules! range_exact_iter_impl { ($($t:ty)*) => ($( - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] impl ExactSizeIterator for RangeIter<$t> { } )*) } @@ -322,7 +322,7 @@ range_incl_exact_iter_impl! { } /// By-value [`RangeFrom`] iterator. -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[derive(Debug, Clone)] pub struct RangeFromIter { start: A, @@ -361,7 +361,7 @@ impl RangeFromIter { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl Iterator for RangeFromIter { type Item = A; @@ -432,10 +432,10 @@ impl Iterator for RangeFromIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeFromIter {} -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl FusedIterator for RangeFromIter {} -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl IntoIterator for RangeFrom { type Item = A; type IntoIter = RangeFromIter; diff --git a/core/src/result.rs b/core/src/result.rs index 5f438d72ac13c..f0e1a1def49d1 100644 --- a/core/src/result.rs +++ b/core/src/result.rs @@ -1682,7 +1682,12 @@ impl Result { #[inline] #[track_caller] #[stable(feature = "option_result_unwrap_unchecked", since = "1.58.0")] - pub unsafe fn unwrap_err_unchecked(self) -> E { + #[rustc_const_unstable(feature = "const_result_unwrap_unchecked", issue = "148714")] + pub const unsafe fn unwrap_err_unchecked(self) -> E + where + T: [const] Destruct, + E: [const] Destruct, + { match self { // SAFETY: the safety contract must be upheld by the caller. Ok(_) => unsafe { hint::unreachable_unchecked() }, @@ -2159,7 +2164,7 @@ impl> FromIterator> for Result { #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Try for Result { +const impl ops::Try for Result { type Output = T; type Residual = Result; @@ -2179,7 +2184,7 @@ impl const ops::Try for Result { #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl> const ops::FromResidual> +const impl> ops::FromResidual> for Result { #[inline] @@ -2193,7 +2198,7 @@ impl> const ops::FromResidual> const ops::FromResidual> for Result { +const impl> ops::FromResidual> for Result { #[inline] fn from_residual(ops::Yeet(e): ops::Yeet) -> Self { Err(From::from(e)) @@ -2202,6 +2207,6 @@ impl> const ops::FromResidual> for Result< #[unstable(feature = "try_trait_v2_residual", issue = "91285")] #[rustc_const_unstable(feature = "const_try", issue = "74935")] -impl const ops::Residual for Result { +const impl ops::Residual for Result { type TryType = Result; } diff --git a/core/src/slice/ascii.rs b/core/src/slice/ascii.rs index edf058c96a522..9db07d8abbbef 100644 --- a/core/src/slice/ascii.rs +++ b/core/src/slice/ascii.rs @@ -222,7 +222,11 @@ impl [u8] { /// Returns a byte slice with leading ASCII whitespace bytes removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_start`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -251,7 +255,11 @@ impl [u8] { /// Returns a byte slice with trailing ASCII whitespace bytes removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_end`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -281,7 +289,11 @@ impl [u8] { /// removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// diff --git a/core/src/slice/cmp.rs b/core/src/slice/cmp.rs index 69a01eef88f97..10a0088477162 100644 --- a/core/src/slice/cmp.rs +++ b/core/src/slice/cmp.rs @@ -3,7 +3,6 @@ use super::{from_raw_parts, memchr}; use crate::ascii; use crate::cmp::{self, BytewiseEq, Ordering}; -use crate::convert::Infallible; use crate::intrinsics::compare_bytes; use crate::marker::Destruct; use crate::mem::SizedTypeProperties; @@ -12,7 +11,7 @@ use crate::ops::ControlFlow; #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq<[U]> for [T] +const impl PartialEq<[U]> for [T] where T: [const] PartialEq, { @@ -31,12 +30,12 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for [T] {} +const impl Eq for [T] {} /// Implements comparison of slices [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Ord for [T] { +const impl Ord for [T] { fn cmp(&self, other: &[T]) -> Ordering { SliceOrd::compare(self, other) } @@ -56,7 +55,7 @@ const fn as_underlying(x: ControlFlow) -> u8 { /// Implements comparison of slices [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialOrd for [T] { +const impl PartialOrd for [T] { #[inline] fn partial_cmp(&self, other: &[T]) -> Option { SlicePartialOrd::partial_compare(self, other) @@ -114,7 +113,7 @@ const trait SlicePartialEq { // Generic slice equality #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialEq for A +const impl SlicePartialEq for A where A: [const] PartialEq, { @@ -144,7 +143,7 @@ where // When each element can be compared byte-wise, we can compare all the bytes // from the whole size in one call to the intrinsics. #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialEq for A +const impl SlicePartialEq for A where A: [const] BytewiseEq, { @@ -180,22 +179,14 @@ const trait SliceChain: Sized { type AlwaysBreak = ControlFlow; #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialOrd for A { +const impl SlicePartialOrd for A { default fn partial_compare(left: &[A], right: &[A]) -> Option { - // FIXME(const-hack): revert this to a const closure once possible - #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - const fn elem_chain(a: &A, b: &A) -> ControlFlow> { - match PartialOrd::partial_cmp(a, b) { - Some(Ordering::Equal) => ControlFlow::Continue(()), - non_eq => ControlFlow::Break(non_eq), - } - } + let elem_chain = const |a, b| match PartialOrd::partial_cmp(a, b) { + Some(Ordering::Equal) => ControlFlow::Continue(()), + non_eq => ControlFlow::Break(non_eq), + }; - // FIXME(const-hack): revert this to a const closure once possible - #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - const fn len_chain(a: &usize, b: &usize) -> ControlFlow, Infallible> { - ControlFlow::Break(usize::partial_cmp(a, b)) - } + let len_chain = const |a: &_, b: &_| ControlFlow::Break(usize::partial_cmp(a, b)); let AlwaysBreak::Break(b) = chaining_impl(left, right, elem_chain, len_chain); b @@ -203,7 +194,7 @@ impl const SlicePartialOrd for A { } #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SliceChain for A { +const impl SliceChain for A { default fn chaining_lt(left: &[Self], right: &[Self]) -> ControlFlow { chaining_impl(left, right, PartialOrd::__chaining_lt, usize::__chaining_lt) } @@ -257,7 +248,7 @@ where */ #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialOrd for A { +const impl SlicePartialOrd for A { fn partial_compare(left: &[A], right: &[A]) -> Option { Some(SliceOrd::compare(left, right)) } @@ -291,22 +282,14 @@ const trait SliceOrd: Sized { } #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SliceOrd for A { +const impl SliceOrd for A { default fn compare(left: &[Self], right: &[Self]) -> Ordering { - // FIXME(const-hack): revert this to a const closure once possible - #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - const fn elem_chain(a: &A, b: &A) -> ControlFlow { - match Ord::cmp(a, b) { - Ordering::Equal => ControlFlow::Continue(()), - non_eq => ControlFlow::Break(non_eq), - } - } + let elem_chain = const |a, b| match Ord::cmp(a, b) { + Ordering::Equal => ControlFlow::Continue(()), + non_eq => ControlFlow::Break(non_eq), + }; - // FIXME(const-hack): revert this to a const closure once possible - #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] - const fn len_chain(a: &usize, b: &usize) -> ControlFlow { - ControlFlow::Break(usize::cmp(a, b)) - } + let len_chain = const |a: &_, b: &_| ControlFlow::Break(usize::cmp(a, b)); let AlwaysBreak::Break(b) = chaining_impl(left, right, elem_chain, len_chain); b @@ -324,20 +307,20 @@ impl const SliceOrd for A { const unsafe trait UnsignedBytewiseOrd: [const] Ord {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for bool {} +const unsafe impl UnsignedBytewiseOrd for bool {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for u8 {} +const unsafe impl UnsignedBytewiseOrd for u8 {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for NonZero {} +const unsafe impl UnsignedBytewiseOrd for NonZero {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for Option> {} +const unsafe impl UnsignedBytewiseOrd for Option> {} #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -unsafe impl const UnsignedBytewiseOrd for ascii::Char {} +const unsafe impl UnsignedBytewiseOrd for ascii::Char {} // `compare_bytes` compares a sequence of unsigned bytes lexicographically, so // use it if the requirements for `UnsignedBytewiseOrd` are fulfilled. #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SliceOrd for A { +const impl SliceOrd for A { #[inline] fn compare(left: &[Self], right: &[Self]) -> Ordering { // Since the length of a slice is always less than or equal to @@ -364,7 +347,7 @@ impl const SliceOrd for A { // Don't generate our own chaining loops for `memcmp`-able things either. #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SliceChain for A { +const impl SliceChain for A { #[inline] fn chaining_lt(left: &[Self], right: &[Self]) -> ControlFlow { match SliceOrd::compare(left, right) { diff --git a/core/src/slice/index.rs b/core/src/slice/index.rs index f1727a1f629cb..56eeb63bca45d 100644 --- a/core/src/slice/index.rs +++ b/core/src/slice/index.rs @@ -8,7 +8,7 @@ use crate::{ops, range}; #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const ops::Index for [T] +const impl ops::Index for [T] where I: [const] SliceIndex<[T]>, { @@ -22,7 +22,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const ops::IndexMut for [T] +const impl ops::IndexMut for [T] where I: [const] SliceIndex<[T]>, { @@ -125,13 +125,13 @@ mod private_slice_index { #[stable(feature = "slice_index_with_ops_bound_pair", since = "1.53.0")] impl Sealed for (ops::Bound, ops::Bound) {} - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] impl Sealed for range::Range {} #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl Sealed for range::RangeInclusive {} - #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl Sealed for range::RangeToInclusive {} - #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] impl Sealed for range::RangeFrom {} impl Sealed for ops::IndexRange {} @@ -211,7 +211,7 @@ pub const unsafe trait SliceIndex: private_slice_index::Sealed { /// The methods `index` and `index_mut` panic if the index is out of bounds. #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for usize { +const unsafe impl SliceIndex<[T]> for usize { type Output = T; #[inline] @@ -282,7 +282,7 @@ unsafe impl const SliceIndex<[T]> for usize { /// Because `IndexRange` guarantees `start <= end`, fewer checks are needed here /// than there are for a general `Range` (which might be `100..3`). #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::IndexRange { +const unsafe impl SliceIndex<[T]> for ops::IndexRange { type Output = [T]; #[inline] @@ -359,7 +359,7 @@ unsafe impl const SliceIndex<[T]> for ops::IndexRange { /// - the end of the range is out of bounds. #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::Range { +const unsafe impl SliceIndex<[T]> for ops::Range { type Output = [T]; #[inline] @@ -458,9 +458,9 @@ unsafe impl const SliceIndex<[T]> for ops::Range { } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for range::Range { +const unsafe impl SliceIndex<[T]> for range::Range { type Output = [T]; #[inline] @@ -499,7 +499,7 @@ unsafe impl const SliceIndex<[T]> for range::Range { /// The methods `index` and `index_mut` panic if the end of the range is out of bounds. #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeTo { +const unsafe impl SliceIndex<[T]> for ops::RangeTo { type Output = [T]; #[inline] @@ -538,7 +538,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeTo { /// The methods `index` and `index_mut` panic if the start of the range is out of bounds. #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeFrom { +const unsafe impl SliceIndex<[T]> for ops::RangeFrom { type Output = [T]; #[inline] @@ -588,9 +588,9 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFrom { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for range::RangeFrom { +const unsafe impl SliceIndex<[T]> for range::RangeFrom { type Output = [T]; #[inline] @@ -628,7 +628,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeFrom { #[stable(feature = "slice_get_slice_impls", since = "1.15.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeFull { +const unsafe impl SliceIndex<[T]> for ops::RangeFull { type Output = [T]; #[inline] @@ -667,7 +667,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFull { /// - the end of the range is out of bounds. #[stable(feature = "inclusive_range", since = "1.26.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { +const unsafe impl SliceIndex<[T]> for ops::RangeInclusive { type Output = [T]; #[inline] @@ -725,7 +725,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for range::RangeInclusive { +const unsafe impl SliceIndex<[T]> for range::RangeInclusive { type Output = [T]; #[inline] @@ -764,7 +764,7 @@ unsafe impl const SliceIndex<[T]> for range::RangeInclusive { /// The methods `index` and `index_mut` panic if the end of the range is out of bounds. #[stable(feature = "inclusive_range", since = "1.26.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for ops::RangeToInclusive { +const unsafe impl SliceIndex<[T]> for ops::RangeToInclusive { type Output = [T]; #[inline] @@ -801,9 +801,9 @@ unsafe impl const SliceIndex<[T]> for ops::RangeToInclusive { } /// The methods `index` and `index_mut` panic if the end of the range is out of bounds. -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex<[T]> for range::RangeToInclusive { +const unsafe impl SliceIndex<[T]> for range::RangeToInclusive { type Output = [T]; #[inline] diff --git a/core/src/slice/iter.rs b/core/src/slice/iter.rs index ac096afb38af0..18abdbed5af6f 100644 --- a/core/src/slice/iter.rs +++ b/core/src/slice/iter.rs @@ -5,9 +5,7 @@ mod macros; use super::{from_raw_parts, from_raw_parts_mut}; use crate::hint::assert_unchecked; -use crate::iter::{ - FusedIterator, TrustedLen, TrustedRandomAccess, TrustedRandomAccessNoCoerce, UncheckedIterator, -}; +use crate::iter::{FusedIterator, TrustedLen, TrustedRandomAccess, TrustedRandomAccessNoCoerce}; use crate::marker::PhantomData; use crate::mem::{self, SizedTypeProperties}; use crate::num::NonZero; diff --git a/core/src/slice/iter/macros.rs b/core/src/slice/iter/macros.rs index 236bdf9d89cae..1c8a4d5ba3c2b 100644 --- a/core/src/slice/iter/macros.rs +++ b/core/src/slice/iter/macros.rs @@ -238,7 +238,7 @@ macro_rules! iterator { // SAFETY: We are in bounds. `post_inc_start` does the right thing even for ZSTs. unsafe { self.post_inc_start(n); - Some(self.next_unchecked()) + Some(self.post_inc_start(1).$into_ref()) } } @@ -481,16 +481,6 @@ macro_rules! iterator { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for $name<'_, T> {} - impl<'a, T> UncheckedIterator for $name<'a, T> { - #[inline] - unsafe fn next_unchecked(&mut self) -> $elem { - // SAFETY: The caller promised there's at least one more item. - unsafe { - self.post_inc_start(1).$into_ref() - } - } - } - #[stable(feature = "default_iters", since = "1.70.0")] impl Default for $name<'_, T> { /// Creates an empty slice iterator. diff --git a/core/src/slice/mod.rs b/core/src/slice/mod.rs index 36dd4d6782ac1..5601716b73044 100644 --- a/core/src/slice/mod.rs +++ b/core/src/slice/mod.rs @@ -754,6 +754,7 @@ impl [T] { #[rustc_as_ptr] #[inline(always)] #[must_use] + #[rustc_no_writable] pub const fn as_mut_ptr(&mut self) -> *mut T { self as *mut [T] as *mut T } @@ -4349,6 +4350,7 @@ impl [T] { /// /// assert_eq!(&bytes, b"Hello, Wello!"); /// ``` + #[inline] #[stable(feature = "copy_within", since = "1.37.0")] #[track_caller] pub fn copy_within>(&mut self, src: R, dest: usize) @@ -5297,6 +5299,7 @@ impl [T] { /// Basic usage: /// ``` /// #![feature(substr_range)] + /// use core::range::Range; /// /// let nums = &[0, 5, 10, 0, 0, 5]; /// @@ -5304,14 +5307,14 @@ impl [T] { /// .split(|t| *t == 0) /// .map(|n| nums.subslice_range(n).unwrap()); /// - /// assert_eq!(iter.next(), Some(0..0)); - /// assert_eq!(iter.next(), Some(1..3)); - /// assert_eq!(iter.next(), Some(4..4)); - /// assert_eq!(iter.next(), Some(5..6)); + /// assert_eq!(iter.next(), Some(Range { start: 0, end: 0 })); + /// assert_eq!(iter.next(), Some(Range { start: 1, end: 3 })); + /// assert_eq!(iter.next(), Some(Range { start: 4, end: 4 })); + /// assert_eq!(iter.next(), Some(Range { start: 5, end: 6 })); /// ``` #[must_use] #[unstable(feature = "substr_range", issue = "126769")] - pub fn subslice_range(&self, subslice: &[T]) -> Option> { + pub fn subslice_range(&self, subslice: &[T]) -> Option> { if T::IS_ZST { panic!("elements are zero-sized"); } @@ -5328,7 +5331,11 @@ impl [T] { let start = byte_start / size_of::(); let end = start.wrapping_add(subslice.len()); - if start <= self.len() && end <= self.len() { Some(start..end) } else { None } + if start <= self.len() && end <= self.len() { + Some(core::range::Range { start, end }) + } else { + None + } } /// Returns the same slice `&[T]`. @@ -5588,7 +5595,7 @@ const trait CloneFromSpec { } #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -impl const CloneFromSpec for [T] +const impl CloneFromSpec for [T] where T: [const] Clone + [const] Destruct, { @@ -5610,7 +5617,7 @@ where } #[rustc_const_unstable(feature = "const_clone", issue = "142757")] -impl const CloneFromSpec for [T] +const impl CloneFromSpec for [T] where T: [const] TrivialClone + [const] Destruct, { @@ -5625,7 +5632,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for &[T] { +const impl Default for &[T] { /// Creates an empty slice. fn default() -> Self { &[] @@ -5634,7 +5641,7 @@ impl const Default for &[T] { #[stable(feature = "mut_slice_default", since = "1.5.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for &mut [T] { +const impl Default for &mut [T] { /// Creates a mutable empty slice. fn default() -> Self { &mut [] diff --git a/core/src/slice/sort/shared/smallsort.rs b/core/src/slice/sort/shared/smallsort.rs index e555fce440872..0017feb75b641 100644 --- a/core/src/slice/sort/shared/smallsort.rs +++ b/core/src/slice/sort/shared/smallsort.rs @@ -284,7 +284,7 @@ fn small_sort_general_with_scratch bool>( // permutation of the input through drop_guard. This technique is similar // to ping-pong merging. bidirectional_merge( - &*ptr::slice_from_raw_parts(drop_guard.src, drop_guard.len), + slice::from_raw_parts(drop_guard.src, drop_guard.len), drop_guard.dst, is_less, ); @@ -332,7 +332,7 @@ where let v_base = v.as_mut_ptr(); let initial_region_len = if no_merge { len } else { len_div_2 }; // SAFETY: Both possible values of `initial_region_len` are in-bounds. - let mut region = unsafe { &mut *ptr::slice_from_raw_parts_mut(v_base, initial_region_len) }; + let mut region = unsafe { slice::from_raw_parts_mut(v_base, initial_region_len) }; // Avoid compiler unrolling, we *really* don't want that to happen here for binary-size reasons. loop { @@ -357,9 +357,7 @@ where } // SAFETY: The right side of `v` based on `len_div_2` is guaranteed in-bounds. - unsafe { - region = &mut *ptr::slice_from_raw_parts_mut(v_base.add(len_div_2), len - len_div_2) - }; + unsafe { region = slice::from_raw_parts_mut(v_base.add(len_div_2), len - len_div_2) }; } // SAFETY: We checked that T is Freeze and thus observation safe. @@ -367,11 +365,7 @@ where // scratch and v must not alias and scratch has v.len() space. unsafe { let scratch_base = stack_array.as_mut_ptr() as *mut T; - bidirectional_merge( - &mut *ptr::slice_from_raw_parts_mut(v_base, len), - scratch_base, - is_less, - ); + bidirectional_merge(slice::from_raw_parts_mut(v_base, len), scratch_base, is_less); ptr::copy_nonoverlapping(scratch_base, v_base, len); } } @@ -675,7 +669,7 @@ unsafe fn sort8_stable bool>( // SAFETY: scratch_base[0..8] is now initialized, allowing us to merge back // into dst. unsafe { - bidirectional_merge(&*ptr::slice_from_raw_parts(scratch_base, 8), dst, is_less); + bidirectional_merge(slice::from_raw_parts(scratch_base, 8), dst, is_less); } } diff --git a/core/src/str/lossy.rs b/core/src/str/lossy.rs index d2dc650910f63..18ad28f8f3b97 100644 --- a/core/src/str/lossy.rs +++ b/core/src/str/lossy.rs @@ -211,12 +211,7 @@ impl<'a> Iterator for Utf8Chunks<'a> { let mut i = 0; let mut valid_up_to = 0; - while i < self.source.len() { - // SAFETY: `i < self.source.len()` per previous line. - // For some reason the following are both significantly slower: - // while let Some(&byte) = self.source.get(i) { - // while let Some(byte) = self.source.get(i).copied() { - let byte = unsafe { *self.source.get_unchecked(i) }; + while let Some(byte) = self.source.get(i).copied() { i += 1; if byte < 128 { diff --git a/core/src/str/mod.rs b/core/src/str/mod.rs index 0d52bfb8c9aa4..fe8ed6c8e637e 100644 --- a/core/src/str/mod.rs +++ b/core/src/str/mod.rs @@ -15,7 +15,7 @@ mod validations; use self::pattern::{DoubleEndedSearcher, Pattern, ReverseSearcher, Searcher}; use crate::char::{self, EscapeDebugExtArgs}; -use crate::ops::Range; +use crate::range::Range; use crate::slice::{self, SliceIndex}; use crate::ub_checks::assert_unsafe_precondition; use crate::{ascii, mem}; @@ -589,6 +589,7 @@ impl str { #[rustc_as_ptr] #[must_use] #[inline(always)] + #[rustc_no_writable] pub const fn as_mut_ptr(&mut self) -> *mut u8 { self as *mut str as *mut u8 } @@ -1202,6 +1203,9 @@ impl str { /// /// This uses the same definition as [`char::is_ascii_whitespace`]. /// To split by Unicode `Whitespace` instead, use [`split_whitespace`]. + /// Note that because of this difference in definition, even if `s.is_ascii()` + /// is `true`, `s.split_ascii_whitespace()` behavior will differ from `s.split_whitespace()` + /// if `s` contains U+000B VERTICAL TAB. /// /// [`split_whitespace`]: str::split_whitespace /// @@ -2896,9 +2900,12 @@ impl str { /// Returns a string slice with leading ASCII whitespace removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_start`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -2921,9 +2928,12 @@ impl str { /// Returns a string slice with trailing ASCII whitespace removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_end`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -2947,9 +2957,12 @@ impl str { /// removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -3112,14 +3125,15 @@ impl str { /// # Examples /// ``` /// #![feature(substr_range)] + /// use core::range::Range; /// /// let data = "a, b, b, a"; /// let mut iter = data.split(", ").map(|s| data.substr_range(s).unwrap()); /// - /// assert_eq!(iter.next(), Some(0..1)); - /// assert_eq!(iter.next(), Some(3..4)); - /// assert_eq!(iter.next(), Some(6..7)); - /// assert_eq!(iter.next(), Some(9..10)); + /// assert_eq!(iter.next(), Some(Range { start: 0, end: 1 })); + /// assert_eq!(iter.next(), Some(Range { start: 3, end: 4 })); + /// assert_eq!(iter.next(), Some(Range { start: 6, end: 7 })); + /// assert_eq!(iter.next(), Some(Range { start: 9, end: 10 })); /// ``` #[must_use] #[unstable(feature = "substr_range", issue = "126769")] @@ -3141,7 +3155,7 @@ impl str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef<[u8]> for str { +const impl AsRef<[u8]> for str { #[inline] fn as_ref(&self) -> &[u8] { self.as_bytes() @@ -3150,7 +3164,7 @@ impl const AsRef<[u8]> for str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for &str { +const impl Default for &str { /// Creates an empty str #[inline] fn default() -> Self { @@ -3160,7 +3174,7 @@ impl const Default for &str { #[stable(feature = "default_mut_str", since = "1.28.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for &mut str { +const impl Default for &mut str { /// Creates an empty mutable str #[inline] fn default() -> Self { diff --git a/core/src/str/pattern.rs b/core/src/str/pattern.rs index 25202ffd67313..77e0093d3ce84 100644 --- a/core/src/str/pattern.rs +++ b/core/src/str/pattern.rs @@ -161,7 +161,7 @@ pub trait Pattern: Sized { } } - /// Returns the pattern as utf-8 bytes if possible. + /// Returns the pattern as UTF-8 if possible. fn as_utf8_pattern(&self) -> Option> { None } @@ -172,7 +172,9 @@ pub trait Pattern: Sized { #[derive(Copy, Clone, Eq, PartialEq, Debug)] pub enum Utf8Pattern<'a> { /// Type returned by String and str types. - StringPattern(&'a [u8]), + /// This stores `str` rather than bytes so callers cannot describe + /// non-UTF-8 string patterns through this API. + StringPattern(&'a str), /// Type returned by char types. CharPattern(char), } @@ -1049,7 +1051,7 @@ impl<'b> Pattern for &'b str { #[inline] fn as_utf8_pattern(&self) -> Option> { - Some(Utf8Pattern::StringPattern(self.as_bytes())) + Some(Utf8Pattern::StringPattern(*self)) } } diff --git a/core/src/str/traits.rs b/core/src/str/traits.rs index da0039f055fde..fb0fee3cb0869 100644 --- a/core/src/str/traits.rs +++ b/core/src/str/traits.rs @@ -5,7 +5,7 @@ use crate::cmp::Ordering; use crate::intrinsics::unchecked_sub; use crate::slice::SliceIndex; use crate::ub_checks::assert_unsafe_precondition; -use crate::{ops, ptr, range}; +use crate::{ops, range}; /// Implements ordering of strings. /// @@ -24,7 +24,7 @@ impl Ord for str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const PartialEq for str { +const impl PartialEq for str { #[inline] fn eq(&self, other: &str) -> bool { self.as_bytes() == other.as_bytes() @@ -33,7 +33,7 @@ impl const PartialEq for str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const Eq for str {} +const impl Eq for str {} /// Implements comparison operations on strings. /// @@ -52,7 +52,7 @@ impl PartialOrd for str { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const ops::Index for str +const impl ops::Index for str where I: [const] SliceIndex, { @@ -66,7 +66,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -impl const ops::IndexMut for str +const impl ops::IndexMut for str where I: [const] SliceIndex, { @@ -90,7 +90,7 @@ where /// Equivalent to `&self[0 .. len]` or `&mut self[0 .. len]`. #[stable(feature = "str_checked_slicing", since = "1.20.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeFull { +const unsafe impl SliceIndex for ops::RangeFull { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -155,7 +155,7 @@ unsafe impl const SliceIndex for ops::RangeFull { /// ``` #[stable(feature = "str_checked_slicing", since = "1.20.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::Range { +const unsafe impl SliceIndex for ops::Range { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -209,7 +209,7 @@ unsafe impl const SliceIndex for ops::Range { // which satisfies all the conditions for `add`. unsafe { let new_len = unchecked_sub(self.end, self.start); - ptr::slice_from_raw_parts(slice.as_ptr().add(self.start), new_len) as *const str + slice.as_ptr().add(self.start).cast_slice(new_len) as *const str } } #[inline] @@ -230,7 +230,7 @@ unsafe impl const SliceIndex for ops::Range { // SAFETY: see comments for `get_unchecked`. unsafe { let new_len = unchecked_sub(self.end, self.start); - ptr::slice_from_raw_parts_mut(slice.as_mut_ptr().add(self.start), new_len) as *mut str + slice.as_mut_ptr().add(self.start).cast_slice(new_len) as *mut str } } #[inline] @@ -258,9 +258,9 @@ unsafe impl const SliceIndex for ops::Range { } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for range::Range { +const unsafe impl SliceIndex for range::Range { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -314,7 +314,7 @@ unsafe impl const SliceIndex for range::Range { // which satisfies all the conditions for `add`. unsafe { let new_len = unchecked_sub(self.end, self.start); - ptr::slice_from_raw_parts(slice.as_ptr().add(self.start), new_len) as *const str + slice.as_ptr().add(self.start).cast_slice(new_len) as *const str } } #[inline] @@ -335,7 +335,7 @@ unsafe impl const SliceIndex for range::Range { // SAFETY: see comments for `get_unchecked`. unsafe { let new_len = unchecked_sub(self.end, self.start); - ptr::slice_from_raw_parts_mut(slice.as_mut_ptr().add(self.start), new_len) as *mut str + slice.as_mut_ptr().add(self.start).cast_slice(new_len) as *mut str } } #[inline] @@ -432,7 +432,7 @@ unsafe impl SliceIndex for (ops::Bound, ops::Bound) { /// character (as defined by `is_char_boundary`), or if `end > len`. #[stable(feature = "str_checked_slicing", since = "1.20.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeTo { +const unsafe impl SliceIndex for ops::RangeTo { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -501,7 +501,7 @@ unsafe impl const SliceIndex for ops::RangeTo { /// a character (as defined by `is_char_boundary`), or if `begin > len`. #[stable(feature = "str_checked_slicing", since = "1.20.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeFrom { +const unsafe impl SliceIndex for ops::RangeFrom { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -555,9 +555,9 @@ unsafe impl const SliceIndex for ops::RangeFrom { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for range::RangeFrom { +const unsafe impl SliceIndex for range::RangeFrom { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -629,7 +629,7 @@ unsafe impl const SliceIndex for range::RangeFrom { /// byte offset or equal to `len`), if `begin > end`, or if `end >= len`. #[stable(feature = "inclusive_range", since = "1.26.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeInclusive { +const unsafe impl SliceIndex for ops::RangeInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -687,7 +687,7 @@ unsafe impl const SliceIndex for ops::RangeInclusive { #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for range::RangeInclusive { +const unsafe impl SliceIndex for range::RangeInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -733,7 +733,7 @@ unsafe impl const SliceIndex for range::RangeInclusive { /// `is_char_boundary`, or equal to `len`), or if `end >= len`. #[stable(feature = "inclusive_range", since = "1.26.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for ops::RangeToInclusive { +const unsafe impl SliceIndex for ops::RangeToInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { @@ -777,9 +777,9 @@ unsafe impl const SliceIndex for ops::RangeToInclusive { /// Panics if `last` does not point to the ending byte offset of a character /// (`last + 1` is either a starting byte offset as defined by /// `is_char_boundary`, or equal to `len`), or if `last >= len`. -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] -unsafe impl const SliceIndex for range::RangeToInclusive { +const unsafe impl SliceIndex for range::RangeToInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { diff --git a/core/src/sync/atomic.rs b/core/src/sync/atomic.rs index 004772267da74..4f2faa7e5fbd6 100644 --- a/core/src/sync/atomic.rs +++ b/core/src/sync/atomic.rs @@ -622,7 +622,7 @@ impl AtomicBool { /// assert_eq!(some_bool, false); /// ``` #[inline] - #[cfg(target_has_atomic_equal_alignment = "8")] + #[cfg(target_has_atomic_primitive_alignment = "8")] #[unstable(feature = "atomic_from_mut", issue = "76314")] pub fn from_mut(v: &mut bool) -> &mut Self { // SAFETY: the mutable reference guarantees unique ownership, and @@ -682,7 +682,7 @@ impl AtomicBool { /// assert_eq!(some_bools, [true; 10]); /// ``` #[inline] - #[cfg(target_has_atomic_equal_alignment = "8")] + #[cfg(target_has_atomic_primitive_alignment = "8")] #[unstable(feature = "atomic_from_mut", issue = "76314")] pub fn from_mut_slice(v: &mut [bool]) -> &mut [Self] { // SAFETY: the mutable reference guarantees unique ownership, and @@ -1593,7 +1593,7 @@ impl AtomicPtr { /// assert_eq!(unsafe { *some_ptr }, 456); /// ``` #[inline] - #[cfg(target_has_atomic_equal_alignment = "ptr")] + #[cfg(target_has_atomic_primitive_alignment = "ptr")] #[unstable(feature = "atomic_from_mut", issue = "76314")] pub fn from_mut(v: &mut *mut T) -> &mut Self { let [] = [(); align_of::>() - align_of::<*mut ()>()]; @@ -1672,7 +1672,7 @@ impl AtomicPtr { /// } /// ``` #[inline] - #[cfg(target_has_atomic_equal_alignment = "ptr")] + #[cfg(target_has_atomic_primitive_alignment = "ptr")] #[unstable(feature = "atomic_from_mut", issue = "76314")] pub fn from_mut_slice(v: &mut [*mut T]) -> &mut [Self] { // SAFETY: @@ -2504,7 +2504,7 @@ impl AtomicPtr { #[cfg(target_has_atomic_load_store = "8")] #[stable(feature = "atomic_bool_from", since = "1.24.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for AtomicBool { +const impl From for AtomicBool { /// Converts a `bool` into an `AtomicBool`. /// /// # Examples @@ -2523,7 +2523,7 @@ impl const From for AtomicBool { #[cfg(target_has_atomic_load_store = "ptr")] #[stable(feature = "atomic_from", since = "1.23.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From<*mut T> for AtomicPtr { +const impl From<*mut T> for AtomicPtr { /// Converts a `*mut T` into an `AtomicPtr`. #[inline] fn from(p: *mut T) -> Self { @@ -3621,7 +3621,7 @@ macro_rules! atomic_int { #[cfg(target_has_atomic_load_store = "8")] atomic_int! { cfg(target_has_atomic = "8"), - cfg(target_has_atomic_equal_alignment = "8"), + cfg(target_has_atomic_primitive_alignment = "8"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3639,7 +3639,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "8")] atomic_int! { cfg(target_has_atomic = "8"), - cfg(target_has_atomic_equal_alignment = "8"), + cfg(target_has_atomic_primitive_alignment = "8"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3657,7 +3657,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "16")] atomic_int! { cfg(target_has_atomic = "16"), - cfg(target_has_atomic_equal_alignment = "16"), + cfg(target_has_atomic_primitive_alignment = "16"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3675,7 +3675,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "16")] atomic_int! { cfg(target_has_atomic = "16"), - cfg(target_has_atomic_equal_alignment = "16"), + cfg(target_has_atomic_primitive_alignment = "16"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3693,7 +3693,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "32")] atomic_int! { cfg(target_has_atomic = "32"), - cfg(target_has_atomic_equal_alignment = "32"), + cfg(target_has_atomic_primitive_alignment = "32"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3711,7 +3711,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "32")] atomic_int! { cfg(target_has_atomic = "32"), - cfg(target_has_atomic_equal_alignment = "32"), + cfg(target_has_atomic_primitive_alignment = "32"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3729,7 +3729,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "64")] atomic_int! { cfg(target_has_atomic = "64"), - cfg(target_has_atomic_equal_alignment = "64"), + cfg(target_has_atomic_primitive_alignment = "64"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3747,7 +3747,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "64")] atomic_int! { cfg(target_has_atomic = "64"), - cfg(target_has_atomic_equal_alignment = "64"), + cfg(target_has_atomic_primitive_alignment = "64"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), stable(feature = "integer_atomics_stable", since = "1.34.0"), @@ -3765,7 +3765,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "128")] atomic_int! { cfg(target_has_atomic = "128"), - cfg(target_has_atomic_equal_alignment = "128"), + cfg(target_has_atomic_primitive_alignment = "128"), unstable(feature = "integer_atomics", issue = "99069"), unstable(feature = "integer_atomics", issue = "99069"), unstable(feature = "integer_atomics", issue = "99069"), @@ -3783,7 +3783,7 @@ atomic_int! { #[cfg(target_has_atomic_load_store = "128")] atomic_int! { cfg(target_has_atomic = "128"), - cfg(target_has_atomic_equal_alignment = "128"), + cfg(target_has_atomic_primitive_alignment = "128"), unstable(feature = "integer_atomics", issue = "99069"), unstable(feature = "integer_atomics", issue = "99069"), unstable(feature = "integer_atomics", issue = "99069"), @@ -3805,7 +3805,7 @@ macro_rules! atomic_int_ptr_sized { #[cfg(target_pointer_width = $target_pointer_width)] atomic_int! { cfg(target_has_atomic = "ptr"), - cfg(target_has_atomic_equal_alignment = "ptr"), + cfg(target_has_atomic_primitive_alignment = "ptr"), stable(feature = "rust1", since = "1.0.0"), stable(feature = "extended_compare_and_swap", since = "1.10.0"), stable(feature = "atomic_debug", since = "1.3.0"), @@ -3823,7 +3823,7 @@ macro_rules! atomic_int_ptr_sized { #[cfg(target_pointer_width = $target_pointer_width)] atomic_int! { cfg(target_has_atomic = "ptr"), - cfg(target_has_atomic_equal_alignment = "ptr"), + cfg(target_has_atomic_primitive_alignment = "ptr"), stable(feature = "rust1", since = "1.0.0"), stable(feature = "extended_compare_and_swap", since = "1.10.0"), stable(feature = "atomic_debug", since = "1.3.0"), diff --git a/core/src/sync/exclusive.rs b/core/src/sync/exclusive.rs deleted file mode 100644 index 35b8120995187..0000000000000 --- a/core/src/sync/exclusive.rs +++ /dev/null @@ -1,322 +0,0 @@ -//! Defines [`Exclusive`]. - -use core::clone::TrivialClone; -use core::cmp::Ordering; -use core::fmt; -use core::future::Future; -use core::hash::{Hash, Hasher}; -use core::marker::{StructuralPartialEq, Tuple}; -use core::ops::{Coroutine, CoroutineState}; -use core::pin::Pin; -use core::task::{Context, Poll}; - -/// `Exclusive` provides _mutable_ access, also referred to as _exclusive_ -/// access to the underlying value. However, it only permits _immutable_, or _shared_ -/// access to the underlying value when that value is [`Sync`]. -/// -/// While this may seem not very useful, it allows `Exclusive` to _unconditionally_ -/// implement `Sync`. Indeed, the safety requirements of `Sync` state that for `Exclusive` -/// to be `Sync`, it must be sound to _share_ across threads, that is, it must be sound -/// for `&Exclusive` to cross thread boundaries. By design, a `&Exclusive` for non-`Sync` T -/// has no API whatsoever, making it useless, thus harmless, thus memory safe. -/// -/// Certain constructs like [`Future`]s can only be used with _exclusive_ access, -/// and are often `Send` but not `Sync`, so `Exclusive` can be used as hint to the -/// Rust compiler that something is `Sync` in practice. -/// -/// ## Examples -/// -/// Using a non-`Sync` future prevents the wrapping struct from being `Sync`: -/// -/// ```compile_fail -/// use core::cell::Cell; -/// -/// async fn other() {} -/// fn assert_sync(t: T) {} -/// struct State { -/// future: F -/// } -/// -/// assert_sync(State { -/// future: async { -/// let cell = Cell::new(1); -/// let cell_ref = &cell; -/// other().await; -/// let value = cell_ref.get(); -/// } -/// }); -/// ``` -/// -/// `Exclusive` ensures the struct is `Sync` without stripping the future of its -/// functionality: -/// -/// ``` -/// #![feature(exclusive_wrapper)] -/// use core::cell::Cell; -/// use core::sync::Exclusive; -/// -/// async fn other() {} -/// fn assert_sync(t: T) {} -/// struct State { -/// future: Exclusive -/// } -/// -/// assert_sync(State { -/// future: Exclusive::new(async { -/// let cell = Cell::new(1); -/// let cell_ref = &cell; -/// other().await; -/// let value = cell_ref.get(); -/// }) -/// }); -/// ``` -/// -/// ## Parallels with a mutex -/// -/// In some sense, `Exclusive` can be thought of as a _compile-time_ version of -/// a mutex, as the borrow-checker guarantees that only one `&mut` can exist -/// for any value. This is a parallel with the fact that -/// `&` and `&mut` references together can be thought of as a _compile-time_ -/// version of a read-write lock. -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -#[doc(alias = "SyncWrapper")] -#[doc(alias = "SyncCell")] -#[doc(alias = "Unique")] -// `Exclusive` can't have derived `PartialOrd`, `Clone`, etc. impls as they would -// use `&` access to the inner value, violating the `Sync` impl's safety -// requirements. -#[derive(Default)] -#[repr(transparent)] -pub struct Exclusive { - inner: T, -} - -// See `Exclusive`'s docs for justification. -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -unsafe impl Sync for Exclusive {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl fmt::Debug for Exclusive { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> Result<(), fmt::Error> { - f.debug_struct("Exclusive").finish_non_exhaustive() - } -} - -impl Exclusive { - /// Wrap a value in an `Exclusive` - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn new(t: T) -> Self { - Self { inner: t } - } - - /// Unwrap the value contained in the `Exclusive` - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn into_inner(self) -> T { - self.inner - } -} - -impl Exclusive { - /// Gets exclusive access to the underlying value. - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn get_mut(&mut self) -> &mut T { - &mut self.inner - } - - /// Gets pinned exclusive access to the underlying value. - /// - /// `Exclusive` is considered to _structurally pin_ the underlying - /// value, which means _unpinned_ `Exclusive`s can produce _unpinned_ - /// access to the underlying value, but _pinned_ `Exclusive`s only - /// produce _pinned_ access to the underlying value. - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn get_pin_mut(self: Pin<&mut Self>) -> Pin<&mut T> { - // SAFETY: `Exclusive` can only produce `&mut T` if itself is unpinned - // `Pin::map_unchecked_mut` is not const, so we do this conversion manually - unsafe { Pin::new_unchecked(&mut self.get_unchecked_mut().inner) } - } - - /// Build a _mutable_ reference to an `Exclusive` from - /// a _mutable_ reference to a `T`. This allows you to skip - /// building an `Exclusive` with [`Exclusive::new`]. - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn from_mut(r: &'_ mut T) -> &'_ mut Exclusive { - // SAFETY: repr is ≥ C, so refs have the same layout; and `Exclusive` properties are `&mut`-agnostic - unsafe { &mut *(r as *mut T as *mut Exclusive) } - } - - /// Build a _pinned mutable_ reference to an `Exclusive` from - /// a _pinned mutable_ reference to a `T`. This allows you to skip - /// building an `Exclusive` with [`Exclusive::new`]. - #[unstable(feature = "exclusive_wrapper", issue = "98407")] - #[must_use] - #[inline] - pub const fn from_pin_mut(r: Pin<&'_ mut T>) -> Pin<&'_ mut Exclusive> { - // SAFETY: `Exclusive` can only produce `&mut T` if itself is unpinned - // `Pin::map_unchecked_mut` is not const, so we do this conversion manually - unsafe { Pin::new_unchecked(Self::from_mut(r.get_unchecked_mut())) } - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -#[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Exclusive { - #[inline] - fn from(t: T) -> Self { - Self::new(t) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl FnOnce for Exclusive -where - F: FnOnce, - Args: Tuple, -{ - type Output = F::Output; - - extern "rust-call" fn call_once(self, args: Args) -> Self::Output { - self.into_inner().call_once(args) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl FnMut for Exclusive -where - F: FnMut, - Args: Tuple, -{ - extern "rust-call" fn call_mut(&mut self, args: Args) -> Self::Output { - self.get_mut().call_mut(args) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Fn for Exclusive -where - F: Sync + Fn, - Args: Tuple, -{ - extern "rust-call" fn call(&self, args: Args) -> Self::Output { - self.as_ref().call(args) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Future for Exclusive -where - T: Future + ?Sized, -{ - type Output = T::Output; - - #[inline] - fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll { - self.get_pin_mut().poll(cx) - } -} - -#[unstable(feature = "coroutine_trait", issue = "43122")] // also #98407 -impl Coroutine for Exclusive -where - G: Coroutine + ?Sized, -{ - type Yield = G::Yield; - type Return = G::Return; - - #[inline] - fn resume(self: Pin<&mut Self>, arg: R) -> CoroutineState { - G::resume(self.get_pin_mut(), arg) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl AsRef for Exclusive -where - T: Sync + ?Sized, -{ - #[inline] - fn as_ref(&self) -> &T { - &self.inner - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Clone for Exclusive -where - T: Sync + Clone, -{ - #[inline] - fn clone(&self) -> Self { - Self { inner: self.inner.clone() } - } -} - -#[doc(hidden)] -#[unstable(feature = "trivial_clone", issue = "none")] -unsafe impl TrivialClone for Exclusive where T: Sync + TrivialClone {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Copy for Exclusive where T: Sync + Copy {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl PartialEq> for Exclusive -where - T: Sync + PartialEq + ?Sized, - U: Sync + ?Sized, -{ - #[inline] - fn eq(&self, other: &Exclusive) -> bool { - self.inner == other.inner - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl StructuralPartialEq for Exclusive where T: Sync + StructuralPartialEq + ?Sized {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Eq for Exclusive where T: Sync + Eq + ?Sized {} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Hash for Exclusive -where - T: Sync + Hash + ?Sized, -{ - #[inline] - fn hash(&self, state: &mut H) { - Hash::hash(&self.inner, state) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl PartialOrd> for Exclusive -where - T: Sync + PartialOrd + ?Sized, - U: Sync + ?Sized, -{ - #[inline] - fn partial_cmp(&self, other: &Exclusive) -> Option { - self.inner.partial_cmp(&other.inner) - } -} - -#[unstable(feature = "exclusive_wrapper", issue = "98407")] -impl Ord for Exclusive -where - T: Sync + Ord + ?Sized, -{ - #[inline] - fn cmp(&self, other: &Self) -> Ordering { - self.inner.cmp(&other.inner) - } -} diff --git a/core/src/sync/mod.rs b/core/src/sync/mod.rs index 4365e4cb250ca..6c2660263a705 100644 --- a/core/src/sync/mod.rs +++ b/core/src/sync/mod.rs @@ -3,6 +3,6 @@ #![stable(feature = "rust1", since = "1.0.0")] pub mod atomic; -mod exclusive; +mod sync_view; #[unstable(feature = "exclusive_wrapper", issue = "98407")] -pub use exclusive::Exclusive; +pub use sync_view::SyncView; diff --git a/core/src/sync/sync_view.rs b/core/src/sync/sync_view.rs new file mode 100644 index 0000000000000..3b02c4c727ca8 --- /dev/null +++ b/core/src/sync/sync_view.rs @@ -0,0 +1,414 @@ +//! Defines [`SyncView`]. + +use core::clone::TrivialClone; +use core::cmp::Ordering; +use core::fmt; +use core::future::Future; +use core::hash::{Hash, Hasher}; +use core::marker::{StructuralPartialEq, Tuple}; +use core::ops::{Coroutine, CoroutineState}; +use core::pin::Pin; +use core::task::{Context, Poll}; + +/// `SyncView` provides _mutable_ access, also referred to as _exclusive_ +/// access to the underlying value. However, it only permits _immutable_, or _shared_ +/// access to the underlying value when that value is [`Sync`]. +/// +/// While this may seem not very useful, it allows `SyncView` to _unconditionally_ +/// implement `Sync`. Indeed, the safety requirements of `Sync` state that for `SyncView` +/// to be `Sync`, it must be sound to _share_ across threads, that is, it must be sound +/// for `&SyncView` to cross thread boundaries. By design, a `&SyncView` for non-`Sync` +/// `T` has no API whatsoever, making it useless, thus harmless, thus memory safe. +/// +/// Certain constructs like [`Future`]s can only be used with _exclusive_ access, +/// and are often [`Send`] but not `Sync`, so `SyncView` can be used as hint to the +/// Rust compiler that something is `Sync` in practice. +/// +/// ## Examples +/// +/// Using a non-`Sync` future prevents the wrapping struct from being `Sync`: +/// +/// ```compile_fail +/// use core::cell::Cell; +/// +/// async fn other() {} +/// fn assert_sync(t: T) {} +/// struct State { +/// future: F +/// } +/// +/// assert_sync(State { +/// future: async { +/// let cell = Cell::new(1); +/// let cell_ref = &cell; +/// other().await; +/// let value = cell_ref.get(); +/// } +/// }); +/// ``` +/// +/// `SyncView` ensures the struct is `Sync` without stripping the future of its +/// functionality: +/// +/// ``` +/// #![feature(exclusive_wrapper)] +/// use core::cell::Cell; +/// use core::sync::SyncView; +/// +/// async fn other() {} +/// fn assert_sync(t: T) {} +/// struct State { +/// future: SyncView +/// } +/// +/// assert_sync(State { +/// future: SyncView::new(async { +/// let cell = Cell::new(1); +/// let cell_ref = &cell; +/// other().await; +/// let value = cell_ref.get(); +/// }) +/// }); +/// ``` +/// +/// ## Parallels with a mutex +/// +/// In some sense, `SyncView` can be thought of as a _compile-time_ version of +/// a mutex, as the borrow-checker guarantees that only one `&mut` can exist +/// for any value. This is a parallel with the fact that +/// `&` and `&mut` references together can be thought of as a _compile-time_ +/// version of a read-write lock. +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[doc(alias = "SyncWrapper")] +#[doc(alias = "SyncCell")] +#[doc(alias = "Unique")] +#[doc(alias = "Exclusive")] +// `SyncView` can't have derived `PartialOrd`, `Clone`, etc. impls as they would +// use `&` access to the inner value, violating the `Sync` impl's safety +// requirements. +#[repr(transparent)] +pub struct SyncView { + inner: T, +} + +// See `SyncView`'s docs for justification. +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +unsafe impl Sync for SyncView {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for SyncView +where + T: [const] Default, +{ + #[inline] + fn default() -> Self { + Self { inner: Default::default() } + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl fmt::Debug for SyncView { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> Result<(), fmt::Error> { + f.debug_struct("SyncView").finish_non_exhaustive() + } +} + +impl SyncView { + /// Wrap a value in an `SyncView` + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn new(t: T) -> Self { + Self { inner: t } + } + + /// Unwrap the value contained in the `SyncView` + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn into_inner(self) -> T { + self.inner + } +} + +impl SyncView { + /// Gets pinned exclusive access to the underlying value. + /// + /// `SyncView` is considered to _structurally pin_ the underlying + /// value, which means _unpinned_ `SyncView`s can produce _unpinned_ + /// access to the underlying value, but _pinned_ `SyncView`s only + /// produce _pinned_ access to the underlying value. + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn as_pin_mut(self: Pin<&mut Self>) -> Pin<&mut T> { + // SAFETY: `SyncView` can only produce `&mut T` if itself is unpinned + // `Pin::map_unchecked_mut` is not const, so we do this conversion manually + unsafe { Pin::new_unchecked(&mut self.get_unchecked_mut().inner) } + } + + /// Build a _mutable_ reference to an `SyncView` from + /// a _mutable_ reference to a `T`. This allows you to skip + /// building an `SyncView` with [`SyncView::new`]. + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn from_mut(r: &'_ mut T) -> &'_ mut SyncView { + // SAFETY: repr is ≥ C, so refs have the same layout; and `SyncView` properties are `&mut`-agnostic + unsafe { &mut *(r as *mut T as *mut SyncView) } + } + + /// Build a _pinned mutable_ reference to an `SyncView` from + /// a _pinned mutable_ reference to a `T`. This allows you to skip + /// building an `SyncView` with [`SyncView::new`]. + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn from_pin_mut(r: Pin<&'_ mut T>) -> Pin<&'_ mut SyncView> { + // SAFETY: `SyncView` can only produce `&mut T` if itself is unpinned + // `Pin::map_unchecked_mut` is not const, so we do this conversion manually + unsafe { Pin::new_unchecked(Self::from_mut(r.get_unchecked_mut())) } + } +} + +impl SyncView { + /// Gets pinned shared access to the underlying value. + /// + /// `SyncView` is considered to _structurally pin_ the underlying + /// value, which means _unpinned_ `SyncView`s can produce _unpinned_ + /// access to the underlying value, but _pinned_ `SyncView`s only + /// produce _pinned_ access to the underlying value. + #[unstable(feature = "exclusive_wrapper", issue = "98407")] + #[rustc_const_unstable(feature = "exclusive_wrapper", issue = "98407")] + #[must_use] + #[inline] + pub const fn as_pin(self: Pin<&Self>) -> Pin<&T> { + // SAFETY: `SyncView` can only produce `&T` if itself is unpinned + // `Pin::map_unchecked` is not const, so we do this conversion manually + unsafe { Pin::new_unchecked(&self.get_ref().inner) } + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl From for SyncView { + #[inline] + fn from(t: T) -> Self { + Self::new(t) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] +const impl FnOnce for SyncView +where + F: [const] FnOnce, + Args: Tuple, +{ + type Output = F::Output; + + extern "rust-call" fn call_once(self, args: Args) -> Self::Output { + self.into_inner().call_once(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] +const impl FnMut for SyncView +where + F: [const] FnMut, + Args: Tuple, +{ + extern "rust-call" fn call_mut(&mut self, args: Args) -> Self::Output { + self.as_mut().call_mut(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_trait_impl", issue = "143874")] +const impl Fn for SyncView +where + F: Sync + [const] Fn, + Args: Tuple, +{ + extern "rust-call" fn call(&self, args: Args) -> Self::Output { + self.as_ref().call(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl AsyncFnOnce for SyncView +where + F: AsyncFnOnce, + Args: Tuple, +{ + type CallOnceFuture = F::CallOnceFuture; + + type Output = F::Output; + + extern "rust-call" fn async_call_once(self, args: Args) -> Self::CallOnceFuture { + self.into_inner().async_call_once(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl AsyncFnMut for SyncView +where + F: AsyncFnMut, + Args: Tuple, +{ + type CallRefFuture<'a> + = F::CallRefFuture<'a> + where + F: 'a; + + extern "rust-call" fn async_call_mut(&mut self, args: Args) -> Self::CallRefFuture<'_> { + self.as_mut().async_call_mut(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl AsyncFn for SyncView +where + F: Sync + AsyncFn, + Args: Tuple, +{ + extern "rust-call" fn async_call(&self, args: Args) -> Self::CallRefFuture<'_> { + self.as_ref().async_call(args) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl Future for SyncView +where + T: Future + ?Sized, +{ + type Output = T::Output; + + #[inline] + fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll { + self.as_pin_mut().poll(cx) + } +} + +#[unstable(feature = "coroutine_trait", issue = "43122")] // also #98407 +impl Coroutine for SyncView +where + G: Coroutine + ?Sized, +{ + type Yield = G::Yield; + type Return = G::Return; + + #[inline] + fn resume(self: Pin<&mut Self>, arg: R) -> CoroutineState { + G::resume(self.as_pin_mut(), arg) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl AsRef for SyncView +where + T: Sync + ?Sized, +{ + /// Gets shared access to the underlying value. + #[inline] + fn as_ref(&self) -> &T { + &self.inner + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_convert", issue = "143773")] +const impl AsMut for SyncView +where + T: ?Sized, +{ + /// Gets exclusive access to the underlying value. + #[inline] + fn as_mut(&mut self) -> &mut T { + &mut self.inner + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_clone", issue = "142757")] +const impl Clone for SyncView +where + T: Sync + [const] Clone, +{ + #[inline] + fn clone(&self) -> Self { + Self { inner: self.inner.clone() } + } +} + +#[doc(hidden)] +#[unstable(feature = "trivial_clone", issue = "none")] +#[rustc_const_unstable(feature = "const_clone", issue = "142757")] +const unsafe impl TrivialClone for SyncView where T: Sync + [const] TrivialClone {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl Copy for SyncView where T: Sync + Copy {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl PartialEq> for SyncView +where + T: Sync + [const] PartialEq + ?Sized, + U: Sync + ?Sized, +{ + #[inline] + fn eq(&self, other: &SyncView) -> bool { + self.inner == other.inner + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl StructuralPartialEq for SyncView where T: Sync + StructuralPartialEq + ?Sized {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl Eq for SyncView where T: Sync + [const] Eq + ?Sized {} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +impl Hash for SyncView +where + T: Sync + Hash + ?Sized, +{ + #[inline] + fn hash(&self, state: &mut H) { + Hash::hash(&self.inner, state) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl PartialOrd> for SyncView +where + T: Sync + [const] PartialOrd + ?Sized, + U: Sync + ?Sized, +{ + #[inline] + fn partial_cmp(&self, other: &SyncView) -> Option { + self.inner.partial_cmp(&other.inner) + } +} + +#[unstable(feature = "exclusive_wrapper", issue = "98407")] +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +const impl Ord for SyncView +where + T: Sync + [const] Ord + ?Sized, +{ + #[inline] + fn cmp(&self, other: &Self) -> Ordering { + self.inner.cmp(&other.inner) + } +} diff --git a/core/src/task/poll.rs b/core/src/task/poll.rs index 380abac0ae95f..87f8830a6b176 100644 --- a/core/src/task/poll.rs +++ b/core/src/task/poll.rs @@ -216,7 +216,7 @@ impl Poll>> { #[stable(feature = "futures_api", since = "1.36.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const From for Poll { +const impl From for Poll { /// Moves the value into a [`Poll::Ready`] to make a `Poll`. /// /// # Example diff --git a/core/src/task/wake.rs b/core/src/task/wake.rs index c22a9da0385b5..14f0980ff6045 100644 --- a/core/src/task/wake.rs +++ b/core/src/task/wake.rs @@ -946,7 +946,7 @@ impl Clone for LocalWaker { #[unstable(feature = "local_waker", issue = "118959")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for Waker { +const impl AsRef for Waker { fn as_ref(&self) -> &LocalWaker { // SAFETY: LocalWaker is just Waker without thread safety unsafe { transmute(self) } diff --git a/core/src/time.rs b/core/src/time.rs index a5b654033ba14..682a61a07d10f 100644 --- a/core/src/time.rs +++ b/core/src/time.rs @@ -1006,6 +1006,7 @@ impl Duration { /// This method will panic if result is negative, overflows `Duration` or not finite. /// /// # Examples + /// /// ``` /// use std::time::Duration; /// @@ -1013,6 +1014,37 @@ impl Duration { /// assert_eq!(dur.mul_f64(3.14), Duration::new(8, 478_000_000)); /// assert_eq!(dur.mul_f64(3.14e5), Duration::new(847_800, 0)); /// ``` + /// + /// Note that `f64` does not have enough bits ([`f64::MANTISSA_DIGITS`]) to represent the full + /// range of possible `Duration` with nanosecond precision, so rounding may occur even for + /// trivial operations like multiplying by 1. + /// + /// ``` + /// # #![feature(float_exact_integer_constants)] + /// use std::time::Duration; + /// + /// // This is about 14.9 weeks, remaining precise to the nanosecond: + /// let weeks = Duration::from_nanos(f64::MAX_EXACT_INTEGER as u64); + /// assert_eq!(weeks, weeks.mul_f64(1.0)); + /// + /// // A larger value incurs rounding in the floating-point operation: + /// let weeks = Duration::from_nanos(u64::MAX); + /// assert_ne!(weeks, weeks.mul_f64(1.0)); + /// + /// // This is over 285 million years, remaining precise to the second: + /// let years = Duration::from_secs(f64::MAX_EXACT_INTEGER as u64); + /// assert_eq!(years, years.mul_f64(1.0)); + /// + /// // And again larger values incur rounding: + /// let years = Duration::from_secs(u64::MAX / 2); + /// assert_ne!(years, years.mul_f64(1.0)); + /// ``` + /// + /// ```should_panic + /// # use std::time::Duration; + /// // In the extreme, rounding can even overflow `Duration`, which panics. + /// let _ = Duration::from_secs(u64::MAX).mul_f64(1.0); + /// ``` #[stable(feature = "duration_float", since = "1.38.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] @@ -1023,6 +1055,10 @@ impl Duration { /// Multiplies `Duration` by `f32`. /// + /// Since the significand of `f32` is quite limited compared to the range of `Duration` + /// -- only about 16.8ms of exact nanosecond precision -- this method currently forwards + /// to [`mul_f64`][Self::mul_f64] for greater accuracy. + /// /// # Panics /// This method will panic if result is negative, overflows `Duration` or not finite. /// @@ -1031,7 +1067,10 @@ impl Duration { /// use std::time::Duration; /// /// let dur = Duration::new(2, 700_000_000); - /// assert_eq!(dur.mul_f32(3.14), Duration::new(8, 478_000_641)); + /// // Note that this `3.14_f32` argument already has more floating-point + /// // representation error than a direct `3.14_f64` would, so the result + /// // is slightly different from the ideal 8.478s. + /// assert_eq!(dur.mul_f32(3.14), Duration::new(8, 478_000_283)); /// assert_eq!(dur.mul_f32(3.14e5), Duration::new(847_800, 0)); /// ``` #[stable(feature = "duration_float", since = "1.38.0")] @@ -1039,7 +1078,7 @@ impl Duration { without modifying the original"] #[inline] pub fn mul_f32(self, rhs: f32) -> Duration { - Duration::from_secs_f32(rhs * self.as_secs_f32()) + self.mul_f64(rhs.into()) } /// Divides `Duration` by `f64`. @@ -1048,6 +1087,7 @@ impl Duration { /// This method will panic if result is negative, overflows `Duration` or not finite. /// /// # Examples + /// /// ``` /// use std::time::Duration; /// @@ -1055,6 +1095,37 @@ impl Duration { /// assert_eq!(dur.div_f64(3.14), Duration::new(0, 859_872_611)); /// assert_eq!(dur.div_f64(3.14e5), Duration::new(0, 8_599)); /// ``` + /// + /// Note that `f64` does not have enough bits ([`f64::MANTISSA_DIGITS`]) to represent the full + /// range of possible `Duration` with nanosecond precision, so rounding may occur even for + /// trivial operations like dividing by 1. + /// + /// ``` + /// # #![feature(float_exact_integer_constants)] + /// use std::time::Duration; + /// + /// // This is about 14.9 weeks, remaining precise to the nanosecond: + /// let weeks = Duration::from_nanos(f64::MAX_EXACT_INTEGER as u64); + /// assert_eq!(weeks, weeks.div_f64(1.0)); + /// + /// // A larger value incurs rounding in the floating-point operation: + /// let weeks = Duration::from_nanos(u64::MAX); + /// assert_ne!(weeks, weeks.div_f64(1.0)); + /// + /// // This is over 285 million years, remaining precise to the second: + /// let years = Duration::from_secs(f64::MAX_EXACT_INTEGER as u64); + /// assert_eq!(years, years.div_f64(1.0)); + /// + /// // And again larger values incur rounding: + /// let years = Duration::from_secs(u64::MAX / 2); + /// assert_ne!(years, years.div_f64(1.0)); + /// ``` + /// + /// ```should_panic + /// # use std::time::Duration; + /// // In the extreme, rounding can even overflow `Duration`, which panics. + /// let _ = Duration::from_secs(u64::MAX).div_f64(1.0); + /// ``` #[stable(feature = "duration_float", since = "1.38.0")] #[must_use = "this returns the result of the operation, \ without modifying the original"] @@ -1065,6 +1136,10 @@ impl Duration { /// Divides `Duration` by `f32`. /// + /// Since the significand of `f32` is quite limited compared to the range of `Duration` + /// -- only about 16.8ms of exact nanosecond precision -- this method currently forwards + /// to [`div_f64`][Self::div_f64] for greater accuracy. + /// /// # Panics /// This method will panic if result is negative, overflows `Duration` or not finite. /// @@ -1073,9 +1148,10 @@ impl Duration { /// use std::time::Duration; /// /// let dur = Duration::new(2, 700_000_000); - /// // note that due to rounding errors result is slightly - /// // different from 0.859_872_611 - /// assert_eq!(dur.div_f32(3.14), Duration::new(0, 859_872_580)); + /// // Note that this `3.14_f32` argument already has more floating-point + /// // representation error than a direct `3.14_f64` would, so the result + /// // is slightly different from the ideally rounded 0.859_872_611. + /// assert_eq!(dur.div_f32(3.14), Duration::new(0, 859_872_583)); /// assert_eq!(dur.div_f32(3.14e5), Duration::new(0, 8_599)); /// ``` #[stable(feature = "duration_float", since = "1.38.0")] @@ -1083,7 +1159,7 @@ impl Duration { without modifying the original"] #[inline] pub fn div_f32(self, rhs: f32) -> Duration { - Duration::from_secs_f32(self.as_secs_f32() / rhs) + self.div_f64(rhs.into()) } /// Divides `Duration` by `Duration` and returns `f64`. @@ -1173,7 +1249,7 @@ impl Duration { #[stable(feature = "duration", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Add for Duration { +const impl Add for Duration { type Output = Duration; #[inline] @@ -1184,7 +1260,7 @@ impl const Add for Duration { #[stable(feature = "time_augmented_assignment", since = "1.9.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const AddAssign for Duration { +const impl AddAssign for Duration { #[inline] fn add_assign(&mut self, rhs: Duration) { *self = *self + rhs; @@ -1193,7 +1269,7 @@ impl const AddAssign for Duration { #[stable(feature = "duration", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Sub for Duration { +const impl Sub for Duration { type Output = Duration; #[inline] @@ -1204,7 +1280,7 @@ impl const Sub for Duration { #[stable(feature = "time_augmented_assignment", since = "1.9.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const SubAssign for Duration { +const impl SubAssign for Duration { #[inline] fn sub_assign(&mut self, rhs: Duration) { *self = *self - rhs; @@ -1213,7 +1289,7 @@ impl const SubAssign for Duration { #[stable(feature = "duration", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Mul for Duration { +const impl Mul for Duration { type Output = Duration; #[inline] @@ -1224,7 +1300,7 @@ impl const Mul for Duration { #[stable(feature = "symmetric_u32_duration_mul", since = "1.31.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Mul for u32 { +const impl Mul for u32 { type Output = Duration; #[inline] @@ -1235,7 +1311,7 @@ impl const Mul for u32 { #[stable(feature = "time_augmented_assignment", since = "1.9.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const MulAssign for Duration { +const impl MulAssign for Duration { #[inline] fn mul_assign(&mut self, rhs: u32) { *self = *self * rhs; @@ -1244,7 +1320,7 @@ impl const MulAssign for Duration { #[stable(feature = "duration", since = "1.3.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const Div for Duration { +const impl Div for Duration { type Output = Duration; #[inline] @@ -1256,7 +1332,7 @@ impl const Div for Duration { #[stable(feature = "time_augmented_assignment", since = "1.9.0")] #[rustc_const_unstable(feature = "const_ops", issue = "143802")] -impl const DivAssign for Duration { +const impl DivAssign for Duration { #[inline] #[track_caller] fn div_assign(&mut self, rhs: u32) { diff --git a/core/src/tuple.rs b/core/src/tuple.rs index 58f81372aff75..adfb027667fac 100644 --- a/core/src/tuple.rs +++ b/core/src/tuple.rs @@ -47,8 +47,7 @@ macro_rules! tuple_impls { maybe_tuple_doc! { $($T)+ @ - #[unstable(feature = "adt_const_params", issue = "95174")] - #[unstable_feature_bound(unsized_const_params)] + #[unstable(feature = "min_adt_const_params", issue = "154042")] impl<$($T: ConstParamTy_),+> ConstParamTy_ for ($($T,)+) {} } @@ -121,7 +120,8 @@ macro_rules! tuple_impls { maybe_tuple_doc! { $($T)+ @ #[stable(feature = "rust1", since = "1.0.0")] - impl<$($T: Default),+> Default for ($($T,)+) { + #[rustc_const_unstable(feature = "const_default", issue = "143894")] + impl<$($T: [const] Default),+> const Default for ($($T,)+) { #[inline] fn default() -> ($($T,)+) { ($({ let x: $T = Default::default(); x},)+) diff --git a/core/src/unicode/mod.rs b/core/src/unicode/mod.rs index 22a1166fdf168..8b2c526a08878 100644 --- a/core/src/unicode/mod.rs +++ b/core/src/unicode/mod.rs @@ -9,9 +9,9 @@ pub use unicode_data::conversions; #[rustfmt::skip] pub(crate) use unicode_data::alphabetic::lookup as Alphabetic; pub(crate) use unicode_data::case_ignorable::lookup as Case_Ignorable; -pub(crate) use unicode_data::cased::lookup as Cased; pub(crate) use unicode_data::grapheme_extend::lookup as Grapheme_Extend; pub(crate) use unicode_data::lowercase::lookup as Lowercase; +pub(crate) use unicode_data::lt::lookup as Lt; pub(crate) use unicode_data::n::lookup as N; pub(crate) use unicode_data::uppercase::lookup as Uppercase; pub(crate) use unicode_data::white_space::lookup as White_Space; diff --git a/core/src/unicode/unicode_data.rs b/core/src/unicode/unicode_data.rs index f602cd5c5b6b3..83d3808051840 100644 --- a/core/src/unicode/unicode_data.rs +++ b/core/src/unicode/unicode_data.rs @@ -1,16 +1,16 @@ //! This file is generated by `./x run src/tools/unicode-table-generator`; do not edit manually! // Alphabetic : 1723 bytes, 147369 codepoints in 759 ranges (U+0000AA - U+03347A) using skiplist // Case_Ignorable : 1063 bytes, 2789 codepoints in 459 ranges (U+0000A8 - U+0E01F0) using skiplist -// Cased : 401 bytes, 4580 codepoints in 156 ranges (U+0000AA - U+01F18A) using skiplist // Grapheme_Extend : 899 bytes, 2232 codepoints in 383 ranges (U+000300 - U+0E01F0) using skiplist // Lowercase : 943 bytes, 2569 codepoints in 676 ranges (U+0000AA - U+01E944) using bitset +// Lt : 33 bytes, 31 codepoints in 10 ranges (U+0001C5 - U+001FFD) using skiplist // N : 463 bytes, 1914 codepoints in 145 ranges (U+0000B2 - U+01FBFA) using skiplist // Uppercase : 799 bytes, 1980 codepoints in 659 ranges (U+0000C0 - U+01F18A) using bitset // White_Space : 256 bytes, 19 codepoints in 8 ranges (U+000085 - U+003001) using cascading // to_lower : 1112 bytes, 1462 codepoints in 185 ranges (U+0000C0 - U+01E921) using 2-level LUT // to_upper : 1998 bytes, 1554 codepoints in 299 ranges (U+0000B5 - U+01E943) using 2-level LUT // to_title : 340 bytes, 135 codepoints in 49 ranges (U+0000DF - U+00FB17) using 2-level LUT -// Total : 9997 bytes +// Total : 9629 bytes #[inline(always)] const fn bitset_search< @@ -337,59 +337,6 @@ pub mod case_ignorable { } } -#[rustfmt::skip] -pub mod cased { - use super::ShortOffsetRunHeader; - - static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 22] = [ - ShortOffsetRunHeader::new(0, 4256), ShortOffsetRunHeader::new(51, 5024), - ShortOffsetRunHeader::new(61, 7296), ShortOffsetRunHeader::new(65, 7958), - ShortOffsetRunHeader::new(74, 9398), ShortOffsetRunHeader::new(149, 11264), - ShortOffsetRunHeader::new(151, 42560), ShortOffsetRunHeader::new(163, 43824), - ShortOffsetRunHeader::new(177, 64256), ShortOffsetRunHeader::new(183, 65313), - ShortOffsetRunHeader::new(187, 66560), ShortOffsetRunHeader::new(191, 67456), - ShortOffsetRunHeader::new(213, 68736), ShortOffsetRunHeader::new(221, 71840), - ShortOffsetRunHeader::new(229, 93760), ShortOffsetRunHeader::new(231, 119808), - ShortOffsetRunHeader::new(237, 120486), ShortOffsetRunHeader::new(274, 122624), - ShortOffsetRunHeader::new(297, 122928), ShortOffsetRunHeader::new(303, 125184), - ShortOffsetRunHeader::new(305, 127280), ShortOffsetRunHeader::new(307, 1241482), - ]; - static OFFSETS: [u8; 313] = [ - 170, 1, 10, 1, 4, 1, 5, 23, 1, 31, 1, 195, 1, 4, 4, 208, 2, 35, 7, 2, 30, 5, 96, 1, 42, 4, - 2, 2, 2, 4, 1, 1, 6, 1, 1, 3, 1, 1, 1, 20, 1, 83, 1, 139, 8, 166, 1, 38, 9, 41, 0, 38, 1, 1, - 5, 1, 2, 43, 1, 4, 0, 86, 2, 6, 0, 11, 5, 43, 2, 3, 64, 192, 64, 0, 2, 6, 2, 38, 2, 6, 2, 8, - 1, 1, 1, 1, 1, 1, 1, 31, 2, 53, 1, 7, 1, 1, 3, 3, 1, 7, 3, 4, 2, 6, 4, 13, 5, 3, 1, 7, 116, - 1, 13, 1, 16, 13, 101, 1, 4, 1, 2, 10, 1, 1, 3, 5, 6, 1, 1, 1, 1, 1, 1, 4, 1, 6, 4, 1, 2, 4, - 5, 5, 4, 1, 17, 32, 3, 2, 0, 52, 0, 229, 6, 4, 3, 2, 12, 38, 1, 1, 5, 1, 0, 46, 18, 30, 132, - 102, 3, 4, 1, 77, 20, 6, 1, 3, 0, 43, 1, 14, 6, 80, 0, 7, 12, 5, 0, 26, 6, 26, 0, 80, 96, - 36, 4, 36, 116, 11, 1, 15, 1, 7, 1, 2, 1, 11, 1, 15, 1, 7, 1, 2, 0, 1, 2, 3, 1, 42, 1, 9, 0, - 51, 13, 51, 93, 22, 10, 22, 0, 64, 0, 64, 32, 25, 2, 25, 0, 85, 1, 71, 1, 2, 2, 1, 2, 2, 2, - 4, 1, 12, 1, 1, 1, 7, 1, 65, 1, 4, 2, 8, 1, 7, 1, 28, 1, 4, 1, 5, 1, 1, 3, 7, 1, 0, 2, 25, - 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 8, 0, 10, 1, 20, 6, 6, 0, - 62, 0, 68, 0, 26, 6, 26, 6, 26, 0, - ]; - #[inline] - pub fn lookup(c: char) -> bool { - debug_assert!(!c.is_ascii()); - (c as u32) >= 0xaa && lookup_slow(c) - } - - #[inline(never)] - fn lookup_slow(c: char) -> bool { - const { - assert!(SHORT_OFFSET_RUNS.last().unwrap().0 > char::MAX as u32); - let mut i = 0; - while i < SHORT_OFFSET_RUNS.len() { - assert!(SHORT_OFFSET_RUNS[i].start_index() < OFFSETS.len()); - i += 1; - } - } - // SAFETY: We just ensured the last element of `SHORT_OFFSET_RUNS` is greater than `std::char::MAX` - // and the start indices of all elements in `SHORT_OFFSET_RUNS` are smaller than `OFFSETS.len()`. - unsafe { super::skip_search(c, &SHORT_OFFSET_RUNS, &OFFSETS) } - } -} - #[rustfmt::skip] pub mod grapheme_extend { use super::ShortOffsetRunHeader; @@ -574,6 +521,39 @@ pub mod lowercase { } } +#[rustfmt::skip] +pub mod lt { + use super::ShortOffsetRunHeader; + + static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 3] = [ + ShortOffsetRunHeader::new(0, 453), ShortOffsetRunHeader::new(1, 8072), + ShortOffsetRunHeader::new(9, 1122301), + ]; + static OFFSETS: [u8; 21] = [ + 0, 1, 2, 1, 2, 1, 38, 1, 0, 8, 8, 8, 8, 8, 12, 1, 15, 1, 47, 1, 0, + ]; + #[inline] + pub fn lookup(c: char) -> bool { + debug_assert!(!c.is_ascii()); + (c as u32) >= 0x1c5 && lookup_slow(c) + } + + #[inline(never)] + fn lookup_slow(c: char) -> bool { + const { + assert!(SHORT_OFFSET_RUNS.last().unwrap().0 > char::MAX as u32); + let mut i = 0; + while i < SHORT_OFFSET_RUNS.len() { + assert!(SHORT_OFFSET_RUNS[i].start_index() < OFFSETS.len()); + i += 1; + } + } + // SAFETY: We just ensured the last element of `SHORT_OFFSET_RUNS` is greater than `std::char::MAX` + // and the start indices of all elements in `SHORT_OFFSET_RUNS` are smaller than `OFFSETS.len()`. + unsafe { super::skip_search(c, &SHORT_OFFSET_RUNS, &OFFSETS) } + } +} + #[rustfmt::skip] pub mod n { use super::ShortOffsetRunHeader; diff --git a/core/src/wtf8.rs b/core/src/wtf8.rs index a0978c3dafb48..698e17a6b8e6d 100644 --- a/core/src/wtf8.rs +++ b/core/src/wtf8.rs @@ -454,25 +454,50 @@ impl Wtf8 { #[track_caller] #[inline] pub fn check_utf8_boundary(&self, index: usize) { + let Err(err) = self.try_check_utf8_boundary(index) else { return }; + match err { + Utf8BoundaryError::NotABoundary => { + panic!("byte index {index} is not a codepoint boundary") + } + Utf8BoundaryError::OutOfBounds => panic!("byte index {index} is out of bounds"), + Utf8BoundaryError::BetweenSurrogates => { + panic!("byte index {index} lies between surrogate codepoints") + } + } + } + + #[track_caller] + #[inline] + pub fn try_check_utf8_boundary(&self, index: usize) -> Result<(), Utf8BoundaryError> { if index == 0 { - return; + return Ok(()); } match self.bytes.get(index) { Some(0xED) => (), // Might be a surrogate - Some(&b) if (b as i8) >= -0x40 => return, - Some(_) => panic!("byte index {index} is not a codepoint boundary"), - None if index == self.len() => return, - None => panic!("byte index {index} is out of bounds"), + Some(&b) if (b as i8) >= -0x40 => return Ok(()), + Some(_) => return Err(Utf8BoundaryError::NotABoundary), + None if index == self.len() => return Ok(()), + None => return Err(Utf8BoundaryError::OutOfBounds), } if self.bytes[index + 1] >= 0xA0 { // There's a surrogate after index. Now check before index. if index >= 3 && self.bytes[index - 3] == 0xED && self.bytes[index - 2] >= 0xA0 { - panic!("byte index {index} lies between surrogate codepoints"); + return Err(Utf8BoundaryError::BetweenSurrogates); } } + Ok(()) } } +// This error type is only used temporarily to provide better panic messages +// It does not implement Error. +#[derive(Debug)] +pub enum Utf8BoundaryError { + NotABoundary, + OutOfBounds, + BetweenSurrogates, +} + /// Copied from core::str::raw::slice_unchecked #[inline] unsafe fn slice_unchecked(s: &Wtf8, begin: usize, end: usize) -> &Wtf8 { diff --git a/coretests/tests/array.rs b/coretests/tests/array.rs index 43fed944e9280..5b35d05d6a032 100644 --- a/coretests/tests/array.rs +++ b/coretests/tests/array.rs @@ -1,3 +1,4 @@ +use core::cell::Cell; use core::num::NonZero; use core::sync::atomic::{AtomicUsize, Ordering}; use core::{array, assert_eq}; @@ -105,6 +106,34 @@ fn iterator_clone() { assert_eq!(clone.next_back(), Some(4)); assert_eq!(it.next(), Some(2)); assert_eq!(clone.next(), Some(2)); + assert_eq!(it.next(), None); + assert_eq!(clone.next(), None); +} + +#[test] +fn iterator_clone_spec() { + #[derive(Debug, PartialEq)] + struct Foo(i32); + + impl Clone for Foo { + fn clone(&self) -> Self { + // nontrivial clone + Foo(-self.0) + } + } + + let mut it = IntoIterator::into_iter([Foo(0), Foo(2), Foo(4), Foo(6), Foo(8)]); + assert_eq!(it.next(), Some(Foo(0))); + assert_eq!(it.next_back(), Some(Foo(8))); + let mut clone = it.clone(); + assert_eq!(it.next_back(), Some(Foo(6))); + assert_eq!(clone.next_back(), Some(Foo(-6))); + assert_eq!(it.next_back(), Some(Foo(4))); + assert_eq!(clone.next_back(), Some(Foo(-4))); + assert_eq!(it.next(), Some(Foo(2))); + assert_eq!(clone.next(), Some(Foo(-2))); + assert_eq!(it.next(), None); + assert_eq!(clone.next(), None); } #[test] @@ -168,8 +197,6 @@ fn iterator_debug() { #[test] fn iterator_drops() { - use core::cell::Cell; - // This test makes sure the correct number of elements are dropped. The `R` // type is just a reference to a `Cell` that is incremented when an `R` is // dropped. @@ -337,8 +364,6 @@ fn array_map_drop_safety() { #[test] fn cell_allows_array_cycle() { - use core::cell::Cell; - #[derive(Debug)] struct B<'a> { a: [Cell>>; 2], @@ -513,7 +538,6 @@ fn array_rsplit_array_mut_out_of_bounds() { #[test] fn array_intoiter_advance_by() { - use std::cell::Cell; struct DropCounter<'a>(usize, &'a Cell); impl Drop for DropCounter<'_> { fn drop(&mut self) { @@ -566,7 +590,6 @@ fn array_intoiter_advance_by() { #[test] fn array_intoiter_advance_back_by() { - use std::cell::Cell; struct DropCounter<'a>(usize, &'a Cell); impl Drop for DropCounter<'_> { fn drop(&mut self) { @@ -718,6 +741,33 @@ fn array_map_drops_unmapped_elements_on_panic() { } } +#[cfg(not(panic = "abort"))] +#[test] +fn array_map_drops_unmapped_zst_elements_on_panic() { + use std::sync::ReentrantLock; + + static DROPPED: ReentrantLock> = ReentrantLock::new(Cell::new(0)); + + struct ZstDrop; + impl Drop for ZstDrop { + fn drop(&mut self) { + DROPPED.lock().update(|x| x + 1); + } + } + + let dropped = DROPPED.lock(); + dropped.set(0); + let array = [const { ZstDrop }; 5]; + let success = std::panic::catch_unwind(std::panic::AssertUnwindSafe(|| { + let _ = array.map(|x| { + drop(x); + assert_eq!(dropped.get(), 1); + }); + })); + assert!(success.is_err()); + assert_eq!(dropped.get(), 5); +} + // This covers the `PartialEq::<[T]>::eq` impl for `[T; N]` when it returns false. #[test] fn array_eq() { @@ -748,7 +798,7 @@ const fn extra_const_array_ops() { { std::array::from_fn(const |i| i + 4).map(const |x| x * 2).map(const |x| x as _) }; let y = 4; struct Z(u16); - impl const Drop for Z { + const impl Drop for Z { fn drop(&mut self) {} } let w = Z(2); diff --git a/coretests/tests/cmp.rs b/coretests/tests/cmp.rs index 0a14470060c3d..e6af3575293d6 100644 --- a/coretests/tests/cmp.rs +++ b/coretests/tests/cmp.rs @@ -48,6 +48,40 @@ fn test_ord_min_max_by() { assert_eq!(cmp::max_by(2, -1, f), 2); } +// Regression test for #136307 / #139357: ensure compare() receives (v1, v2), not (v2, v1). +#[test] +fn min_by_compare_argument_order() { + let mut order = vec![]; + let res = cmp::min_by(1i32, 2, |a, b| { + order.push((*a, *b)); + a.cmp(b) + }); + assert_eq!(res, 1); + assert_eq!(order, [(1, 2)]); +} + +#[test] +fn max_by_compare_argument_order() { + let mut order = vec![]; + let res = cmp::max_by(1i32, 2, |a, b| { + order.push((*a, *b)); + a.cmp(b) + }); + assert_eq!(res, 2); + assert_eq!(order, [(1, 2)]); +} + +#[test] +fn minmax_by_compare_argument_order() { + let mut order = vec![]; + let res = cmp::minmax_by(1i32, 2, |a, b| { + order.push((*a, *b)); + a.cmp(b) + }); + assert_eq!(res, [1, 2]); + assert_eq!(order, [(1, 2)]); +} + #[test] fn test_ord_min_max_by_key() { let f = |x: &i32| x.abs(); @@ -220,13 +254,13 @@ mod const_cmp { struct S(i32); - impl const PartialEq for S { + const impl PartialEq for S { fn eq(&self, other: &Self) -> bool { self.0 == other.0 } } - impl const PartialOrd for S { + const impl PartialOrd for S { fn partial_cmp(&self, other: &Self) -> Option { let ret = match (self.0, other.0) { (a, b) if a > b => Ordering::Greater, diff --git a/coretests/tests/ffi/cstr.rs b/coretests/tests/ffi/cstr.rs index 7d669cc1c3fff..0fb98036b2675 100644 --- a/coretests/tests/ffi/cstr.rs +++ b/coretests/tests/ffi/cstr.rs @@ -1,5 +1,11 @@ use core::ffi::CStr; +#[test] +fn const_default() { + const S: &CStr = <_>::default(); + assert_eq!(S, c""); +} + #[test] fn compares_as_u8s() { let a: &CStr = c"Hello!"; // Starts with ascii diff --git a/coretests/tests/fmt/float.rs b/coretests/tests/fmt/float.rs index 003782f34dc93..4f7357761744b 100644 --- a/coretests/tests/fmt/float.rs +++ b/coretests/tests/fmt/float.rs @@ -1,3 +1,5 @@ +use core::fmt::{self, Write}; + #[test] fn test_format_f64() { assert_eq!("1", format!("{:.0}", 1.0f64)); @@ -170,6 +172,72 @@ fn test_format_f32_rounds_ties_to_even() { assert_eq!("-1.28E2", format!("{:.2E}", -128.5f32)); } +#[test] +fn test_format_f64_max_precision_exponential() { + struct ExactExpWriter { + prefix: &'static [u8], + zeroes_remaining: u32, + suffix: &'static [u8], + prefix_pos: usize, + suffix_pos: usize, + total_len: u32, + } + + impl ExactExpWriter { + fn new(prefix: &'static str, suffix: &'static str) -> Self { + Self { + prefix: prefix.as_bytes(), + zeroes_remaining: u16::MAX.into(), + suffix: suffix.as_bytes(), + prefix_pos: 0, + suffix_pos: 0, + total_len: 0, + } + } + + fn finish(self) { + assert_eq!(self.prefix_pos, self.prefix.len()); + assert_eq!(self.zeroes_remaining, 0); + assert_eq!(self.suffix_pos, self.suffix.len()); + assert_eq!(self.total_len, u32::from(u16::MAX) + 4); + } + } + + impl Write for ExactExpWriter { + fn write_str(&mut self, s: &str) -> fmt::Result { + for byte in s.bytes() { + self.total_len += 1; + + if self.prefix_pos < self.prefix.len() { + assert_eq!(byte, self.prefix[self.prefix_pos]); + self.prefix_pos += 1; + } else if self.zeroes_remaining > 0 { + assert_eq!(byte, b'0'); + self.zeroes_remaining -= 1; + } else { + assert!(self.suffix_pos < self.suffix.len()); + assert_eq!(byte, self.suffix[self.suffix_pos]); + self.suffix_pos += 1; + } + } + + Ok(()) + } + } + + fn assert_exact_exp(args: fmt::Arguments<'_>, prefix: &'static str, suffix: &'static str) { + let mut writer = ExactExpWriter::new(prefix, suffix); + fmt::write(&mut writer, args).unwrap(); + writer.finish(); + } + + assert_exact_exp(format_args!("{:.65535e}", 0.0f64), "0.", "e0"); + assert_exact_exp(format_args!("{:.65535e}", 1.0f64), "1.", "e0"); + assert_exact_exp(format_args!("{:.65535E}", 0.0f64), "0.", "E0"); + assert_exact_exp(format_args!("{:.65535E}", 1.0f64), "1.", "E0"); + assert_exact_exp(format_args!("{:65535.65535e}", 1.0f64), "1.", "e0"); +} + fn is_exponential(s: &str) -> bool { s.contains("e") || s.contains("E") } diff --git a/coretests/tests/hint.rs b/coretests/tests/hint.rs index d15730823eb5b..8eeb86b29a65f 100644 --- a/coretests/tests/hint.rs +++ b/coretests/tests/hint.rs @@ -3,7 +3,7 @@ fn select_unpredictable_drop() { use core::cell::Cell; struct X<'a>(&'a Cell); - impl const Drop for X<'_> { + const impl Drop for X<'_> { fn drop(&mut self) { self.0.set(true); } diff --git a/coretests/tests/io/borrowed_buf.rs b/coretests/tests/io/borrowed_buf.rs index aaa98d26ff8b9..de241e0cb85c9 100644 --- a/coretests/tests/io/borrowed_buf.rs +++ b/coretests/tests/io/borrowed_buf.rs @@ -8,7 +8,7 @@ fn new() { let mut rbuf: BorrowedBuf<'_> = buf.into(); assert_eq!(rbuf.filled().len(), 0); - assert_eq!(rbuf.init_len(), 16); + assert!(rbuf.is_init()); assert_eq!(rbuf.capacity(), 16); assert_eq!(rbuf.unfilled().capacity(), 16); } @@ -20,7 +20,7 @@ fn uninit() { let mut rbuf: BorrowedBuf<'_> = buf.into(); assert_eq!(rbuf.filled().len(), 0); - assert_eq!(rbuf.init_len(), 0); + assert!(!rbuf.is_init()); assert_eq!(rbuf.capacity(), 16); assert_eq!(rbuf.unfilled().capacity(), 16); } @@ -32,7 +32,7 @@ fn initialize_unfilled() { rbuf.unfilled().ensure_init(); - assert_eq!(rbuf.init_len(), 16); + assert!(rbuf.is_init()); } #[test] @@ -40,7 +40,7 @@ fn advance_filled() { let buf: &mut [_] = &mut [0; 16]; let mut rbuf: BorrowedBuf<'_> = buf.into(); - rbuf.unfilled().advance(1); + rbuf.unfilled().advance_checked(1); assert_eq!(rbuf.filled().len(), 1); assert_eq!(rbuf.unfilled().capacity(), 15); @@ -51,7 +51,7 @@ fn clear() { let buf: &mut [_] = &mut [255; 16]; let mut rbuf: BorrowedBuf<'_> = buf.into(); - rbuf.unfilled().advance(16); + rbuf.unfilled().advance_checked(16); assert_eq!(rbuf.filled().len(), 16); assert_eq!(rbuf.unfilled().capacity(), 0); @@ -61,7 +61,7 @@ fn clear() { assert_eq!(rbuf.filled().len(), 0); assert_eq!(rbuf.unfilled().capacity(), 16); - assert_eq!(rbuf.unfilled().init_mut(), [255; 16]); + assert_eq!(rbuf.unfilled().ensure_init(), [255; 16]); } #[test] @@ -70,24 +70,10 @@ fn set_init() { let mut rbuf: BorrowedBuf<'_> = buf.into(); unsafe { - rbuf.set_init(8); + rbuf.set_init(); } - assert_eq!(rbuf.init_len(), 8); - - rbuf.unfilled().advance(4); - - unsafe { - rbuf.set_init(2); - } - - assert_eq!(rbuf.init_len(), 8); - - unsafe { - rbuf.set_init(8); - } - - assert_eq!(rbuf.init_len(), 8); + assert!(rbuf.is_init()); } #[test] @@ -97,7 +83,7 @@ fn append() { rbuf.unfilled().append(&[0; 8]); - assert_eq!(rbuf.init_len(), 8); + assert!(!rbuf.is_init()); assert_eq!(rbuf.filled().len(), 8); assert_eq!(rbuf.filled(), [0; 8]); @@ -105,7 +91,7 @@ fn append() { rbuf.unfilled().append(&[1; 16]); - assert_eq!(rbuf.init_len(), 16); + assert!(!rbuf.is_init()); assert_eq!(rbuf.filled().len(), 16); assert_eq!(rbuf.filled(), [1; 16]); } @@ -125,7 +111,7 @@ fn reborrow_written() { assert_eq!(cursor.written(), 32); assert_eq!(buf.unfilled().written(), 32); - assert_eq!(buf.init_len(), 32); + assert!(!buf.is_init()); assert_eq!(buf.filled().len(), 32); let filled = buf.filled(); assert_eq!(&filled[..16], [1; 16]); @@ -136,30 +122,20 @@ fn reborrow_written() { fn cursor_set_init() { let buf: &mut [_] = &mut [MaybeUninit::zeroed(); 16]; let mut rbuf: BorrowedBuf<'_> = buf.into(); + let mut cursor = rbuf.unfilled(); unsafe { - rbuf.unfilled().set_init(8); + cursor.set_init(); } - assert_eq!(rbuf.init_len(), 8); - assert_eq!(rbuf.unfilled().init_mut().len(), 8); - assert_eq!(unsafe { rbuf.unfilled().as_mut().len() }, 16); - - rbuf.unfilled().advance(4); - - unsafe { - rbuf.unfilled().set_init(2); - } + assert!(cursor.is_init()); + assert_eq!(unsafe { cursor.as_mut().len() }, 16); - assert_eq!(rbuf.init_len(), 8); + cursor.advance_checked(4); - unsafe { - rbuf.unfilled().set_init(8); - } + assert_eq!(unsafe { cursor.as_mut().len() }, 12); - assert_eq!(rbuf.init_len(), 12); - assert_eq!(rbuf.unfilled().init_mut().len(), 8); - assert_eq!(unsafe { rbuf.unfilled().as_mut().len() }, 12); + assert!(rbuf.is_init()); } #[test] @@ -173,26 +149,26 @@ fn cursor_with_unfilled_buf() { assert_eq!(buf.filled(), &[1, 2, 3]); }); - assert_eq!(cursor.init_mut().len(), 0); + assert!(!cursor.is_init()); assert_eq!(cursor.written(), 3); cursor.with_unfilled_buf(|buf| { assert_eq!(buf.capacity(), 13); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); buf.unfilled().ensure_init(); - buf.unfilled().advance(4); + buf.unfilled().advance_checked(4); }); - assert_eq!(cursor.init_mut().len(), 9); + assert!(cursor.is_init()); assert_eq!(cursor.written(), 7); cursor.with_unfilled_buf(|buf| { assert_eq!(buf.capacity(), 9); - assert_eq!(buf.init_len(), 9); + assert!(buf.is_init()); }); - assert_eq!(cursor.init_mut().len(), 9); + assert!(cursor.is_init()); assert_eq!(cursor.written(), 7); assert_eq!(rbuf.filled(), &[1, 2, 3, 0, 0, 0, 0]); diff --git a/coretests/tests/io/io_slice.rs b/coretests/tests/io/io_slice.rs new file mode 100644 index 0000000000000..4639ef2c6ac41 --- /dev/null +++ b/coretests/tests/io/io_slice.rs @@ -0,0 +1,100 @@ +use core::io::{IoSlice, IoSliceMut}; +use core::ops::Deref; + +#[test] +fn io_slice_mut_advance_slices() { + let mut buf1 = [1; 8]; + let mut buf2 = [2; 16]; + let mut buf3 = [3; 8]; + let mut bufs = &mut [ + IoSliceMut::new(&mut buf1), + IoSliceMut::new(&mut buf2), + IoSliceMut::new(&mut buf3), + ][..]; + + // Only in a single buffer.. + IoSliceMut::advance_slices(&mut bufs, 1); + assert_eq!(bufs[0].deref(), [1; 7].as_ref()); + assert_eq!(bufs[1].deref(), [2; 16].as_ref()); + assert_eq!(bufs[2].deref(), [3; 8].as_ref()); + + // Removing a buffer, leaving others as is. + IoSliceMut::advance_slices(&mut bufs, 7); + assert_eq!(bufs[0].deref(), [2; 16].as_ref()); + assert_eq!(bufs[1].deref(), [3; 8].as_ref()); + + // Removing a buffer and removing from the next buffer. + IoSliceMut::advance_slices(&mut bufs, 18); + assert_eq!(bufs[0].deref(), [3; 6].as_ref()); +} + +#[test] +#[should_panic] +fn io_slice_mut_advance_slices_empty_slice() { + let mut empty_bufs = &mut [][..]; + IoSliceMut::advance_slices(&mut empty_bufs, 1); +} + +#[test] +#[should_panic] +fn io_slice_mut_advance_slices_beyond_total_length() { + let mut buf1 = [1; 8]; + let mut bufs = &mut [IoSliceMut::new(&mut buf1)][..]; + + IoSliceMut::advance_slices(&mut bufs, 9); + assert!(bufs.is_empty()); +} + +#[test] +fn io_slice_advance_slices() { + let buf1 = [1; 8]; + let buf2 = [2; 16]; + let buf3 = [3; 8]; + let mut bufs = &mut [IoSlice::new(&buf1), IoSlice::new(&buf2), IoSlice::new(&buf3)][..]; + + // Only in a single buffer.. + IoSlice::advance_slices(&mut bufs, 1); + assert_eq!(bufs[0].deref(), [1; 7].as_ref()); + assert_eq!(bufs[1].deref(), [2; 16].as_ref()); + assert_eq!(bufs[2].deref(), [3; 8].as_ref()); + + // Removing a buffer, leaving others as is. + IoSlice::advance_slices(&mut bufs, 7); + assert_eq!(bufs[0].deref(), [2; 16].as_ref()); + assert_eq!(bufs[1].deref(), [3; 8].as_ref()); + + // Removing a buffer and removing from the next buffer. + IoSlice::advance_slices(&mut bufs, 18); + assert_eq!(bufs[0].deref(), [3; 6].as_ref()); +} + +#[test] +#[should_panic] +fn io_slice_advance_slices_empty_slice() { + let mut empty_bufs = &mut [][..]; + IoSlice::advance_slices(&mut empty_bufs, 1); +} + +#[test] +#[should_panic] +fn io_slice_advance_slices_beyond_total_length() { + let buf1 = [1; 8]; + let mut bufs = &mut [IoSlice::new(&buf1)][..]; + + IoSlice::advance_slices(&mut bufs, 9); + assert!(bufs.is_empty()); +} + +#[test] +fn io_slice_as_slice() { + let buf = [1; 8]; + let slice = IoSlice::new(&buf).as_slice(); + assert_eq!(slice, buf); +} + +#[test] +fn io_slice_into_slice() { + let mut buf = [1; 8]; + let slice = IoSliceMut::new(&mut buf).into_slice(); + assert_eq!(slice, [1; 8]); +} diff --git a/coretests/tests/io/mod.rs b/coretests/tests/io/mod.rs index a24893a525a9d..7683131a54034 100644 --- a/coretests/tests/io/mod.rs +++ b/coretests/tests/io/mod.rs @@ -1 +1,2 @@ mod borrowed_buf; +mod io_slice; diff --git a/coretests/tests/iter/range.rs b/coretests/tests/iter/range.rs index d5d2b8bf2b047..4a00e6f96bda8 100644 --- a/coretests/tests/iter/range.rs +++ b/coretests/tests/iter/range.rs @@ -502,3 +502,142 @@ fn test_double_ended_range() { panic!("unreachable"); } } + +macro_rules! nz { + (NonZero<$type:ident>($val:literal)) => { + ::core::num::NonZero::<$type>::new($val).unwrap() + }; + (NonZero<$type:ident>::MAX) => { + ::core::num::NonZero::<$type>::new($type::MAX).unwrap() + }; +} + +macro_rules! nonzero_array { + (NonZero<$type:ident>[$($val:literal),*]) => { + [$(nz!(NonZero<$type>($val))),*] + } +} + +macro_rules! nonzero_range { + (NonZero<$type:ident>($($left:literal)?..$($right:literal)?)) => { + nz!(NonZero<$type>($($left)?))..nz!(NonZero<$type>($($right)?)) + }; + (NonZero<$type:ident>($($left:literal)?..MAX)) => { + nz!(NonZero<$type>($($left)?))..nz!(NonZero<$type>::MAX) + }; + (NonZero<$type:ident>($($left:literal)?..=$right:literal)) => { + nz!(NonZero<$type>($($left)?))..=nz!(NonZero<$type>($right)) + }; + (NonZero<$type:ident>($($left:literal)?..=MAX)) => { + nz!(NonZero<$type>($($left)?))..=nz!(NonZero<$type>::MAX) + }; +} + +#[test] +fn test_nonzero_range() { + assert_eq!( + nonzero_range!(NonZero(1..=21)).step_by(5).collect::>(), + nonzero_array!(NonZero[1, 6, 11, 16, 21]) + ); + assert_eq!( + nonzero_range!(NonZero(1..=20)).step_by(5).collect::>(), + nonzero_array!(NonZero[1, 6, 11, 16]) + ); + assert_eq!( + nonzero_range!(NonZero(1..20)).step_by(5).collect::>(), + nonzero_array!(NonZero[1, 6, 11, 16]) + ); + assert_eq!( + nonzero_range!(NonZero(1..21)).rev().step_by(5).collect::>(), + nonzero_array!(NonZero[20, 15, 10, 5]) + ); + assert_eq!( + nonzero_range!(NonZero(1..21)).rev().step_by(6).collect::>(), + nonzero_array!(NonZero[20, 14, 8, 2]) + ); + assert_eq!( + nonzero_range!(NonZero(200..255)).step_by(50).collect::>(), + nonzero_array!(NonZero[200, 250]) + ); + assert_eq!( + nonzero_range!(NonZero(200..5)).step_by(1).collect::>(), + nonzero_array!(NonZero[]) + ); + assert_eq!( + nonzero_range!(NonZero(200..200)).step_by(1).collect::>(), + nonzero_array!(NonZero[]) + ); + + assert_eq!(nonzero_range!(NonZero(10..20)).step_by(1).size_hint(), (10, Some(10))); + assert_eq!(nonzero_range!(NonZero(10..20)).step_by(5).size_hint(), (2, Some(2))); + assert_eq!(nonzero_range!(NonZero(1..21)).rev().step_by(5).size_hint(), (4, Some(4))); + assert_eq!(nonzero_range!(NonZero(1..21)).rev().step_by(6).size_hint(), (4, Some(4))); + assert_eq!(nonzero_range!(NonZero(20..1)).step_by(1).size_hint(), (0, Some(0))); + assert_eq!(nonzero_range!(NonZero(20..20)).step_by(1).size_hint(), (0, Some(0))); + + // ExactSizeIterator + assert_eq!(nonzero_range!(NonZero(1..=MAX)).step_by(1).len(), usize::from(u8::MAX)); + assert_eq!(nonzero_range!(NonZero(1..=MAX)).step_by(1).len(), usize::from(u16::MAX)); + assert_eq!(nonzero_range!(NonZero(1..=MAX)).step_by(1).len(), usize::MAX); + + // Limits (next) + let mut range = nonzero_range!(NonZero(254..=MAX)); + assert_eq!(range.next(), Some(nz!(NonZero(254)))); + assert_eq!(range.next(), Some(nz!(NonZero(255)))); + assert_eq!(range.next(), None); + + let mut range = nonzero_range!(NonZero(65534..=MAX)); + assert_eq!(range.next(), Some(nz!(NonZero(65534)))); + assert_eq!(range.next(), Some(nz!(NonZero(65535)))); + assert_eq!(range.next(), None); + + // Limits (size_hint, exclusive range) + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (u8::MAX as usize - 1, Some(u8::MAX as usize - 1)) + ); + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (u16::MAX as usize - 1, Some(u16::MAX as usize - 1)) + ); + #[cfg(any(target_pointer_width = "32", target_pointer_width = "64"))] + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (u32::MAX as usize - 1, Some(u32::MAX as usize - 1)) + ); + #[cfg(target_pointer_width = "64")] + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (u64::MAX as usize - 1, Some(u64::MAX as usize - 1)) + ); + assert_eq!(nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), (usize::MAX, None)); + assert_eq!( + nonzero_range!(NonZero(1..MAX)).step_by(1).size_hint(), + (usize::MAX - 1, Some(usize::MAX - 1)) + ); + + // Limits (size_hint, inclusive range) + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (u8::MAX as usize, Some(u8::MAX as usize)) + ); + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (u16::MAX as usize, Some(u16::MAX as usize)) + ); + #[cfg(any(target_pointer_width = "32", target_pointer_width = "64"))] + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (u32::MAX as usize, Some(u32::MAX as usize)) + ); + #[cfg(target_pointer_width = "64")] + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (u64::MAX as usize, Some(u64::MAX as usize)) + ); + assert_eq!(nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), (usize::MAX, None)); + assert_eq!( + nonzero_range!(NonZero(1..=MAX)).step_by(1).size_hint(), + (usize::MAX, Some(usize::MAX)) + ); +} diff --git a/coretests/tests/iter/sources.rs b/coretests/tests/iter/sources.rs index 420f3088e6ee4..c1df278b54064 100644 --- a/coretests/tests/iter/sources.rs +++ b/coretests/tests/iter/sources.rs @@ -192,3 +192,19 @@ fn test_repeat_n_soundness() { let _z = y; assert_eq!(0, *x); } + +#[test] +fn test_repeat_n_default() { + #[derive(Clone)] + pub struct PanicOnDrop; + + impl Drop for PanicOnDrop { + fn drop(&mut self) { + unreachable!() + } + } + + // The default is an empty iterator, so there's never any item to drop. + let iter = RepeatN::::default(); + assert_eq!(iter.count(), 0); +} diff --git a/coretests/tests/iter/traits/iterator.rs b/coretests/tests/iter/traits/iterator.rs index 5ef1f797ae55d..386946461e9fe 100644 --- a/coretests/tests/iter/traits/iterator.rs +++ b/coretests/tests/iter/traits/iterator.rs @@ -619,6 +619,23 @@ fn test_next_chunk() { assert_eq!(it.next_chunk::<0>().unwrap(), []); } +#[test] +fn test_next_chunk_untrusted() { + struct Untrusted(I); + impl Iterator for Untrusted { + type Item = I::Item; + + fn next(&mut self) -> Option { + self.0.next() + } + } + let mut it = Untrusted(0..12); + assert_eq!(it.next_chunk().unwrap(), [0, 1, 2, 3]); + assert_eq!(it.next_chunk().unwrap(), []); + assert_eq!(it.next_chunk().unwrap(), [4, 5, 6, 7, 8, 9]); + assert_eq!(it.next_chunk::<4>().unwrap_err().as_slice(), &[10, 11]); +} + #[test] fn test_collect_into_tuples() { let a = vec![(1, 2, 3), (4, 5, 6), (7, 8, 9)]; diff --git a/coretests/tests/lib.rs b/coretests/tests/lib.rs index 90a33aeead150..89e8d5d8185ee 100644 --- a/coretests/tests/lib.rs +++ b/coretests/tests/lib.rs @@ -1,4 +1,5 @@ // tidy-alphabetical-start +#![cfg_attr(not(panic = "abort"), feature(reentrant_lock))] #![cfg_attr(target_has_atomic = "128", feature(integer_atomics))] #![feature(array_ptr_get)] #![feature(array_try_from_fn)] @@ -7,12 +8,12 @@ #![feature(ascii_char_variants)] #![feature(async_iter_from_iter)] #![feature(async_iterator)] -#![feature(bool_to_result)] +#![feature(borrowed_buf_init)] #![feature(bstr)] #![feature(cfg_target_has_reliable_f16_f128)] #![feature(char_internals)] -#![feature(char_max_len)] #![feature(clone_to_uninit)] +#![feature(cmp_minmax)] #![feature(const_array)] #![feature(const_bool)] #![feature(const_cell_traits)] @@ -35,6 +36,7 @@ #![feature(const_unsigned_bigint_helpers)] #![feature(core_intrinsics)] #![feature(core_intrinsics_fallbacks)] +#![feature(core_io)] #![feature(core_io_borrowed_buf)] #![feature(core_private_bignum)] #![feature(core_private_diy_float)] @@ -64,11 +66,10 @@ #![feature(hasher_prefixfree_extras)] #![feature(hashmap_internals)] #![feature(int_from_ascii)] -#![feature(int_lowest_highest_one)] #![feature(int_roundings)] +#![feature(io_slice_as_bytes)] #![feature(ip)] #![feature(is_ascii_octdigit)] -#![feature(isolate_most_least_significant_one)] #![feature(iter_advance_by)] #![feature(iter_array_chunks)] #![feature(iter_collect_into)] @@ -117,15 +118,14 @@ #![feature(trusted_random_access)] #![feature(try_blocks)] #![feature(try_find)] +#![feature(try_from_int_error_kind)] #![feature(try_trait_v2)] #![feature(type_info)] -#![feature(uint_bit_width)] #![feature(uint_carryless_mul)] #![feature(uint_gather_scatter_bits)] #![feature(unicode_internals)] #![feature(unsize)] #![feature(unwrap_infallible)] -#![feature(widening_mul)] // tidy-alphabetical-end #![allow(internal_features)] #![deny(fuzzy_provenance_casts)] diff --git a/coretests/tests/macros.rs b/coretests/tests/macros.rs index 50b5eb63e43a7..9f73ebd253c3b 100644 --- a/coretests/tests/macros.rs +++ b/coretests/tests/macros.rs @@ -1,5 +1,7 @@ #![allow(unused_must_use)] +use std::{assert_matches, debug_assert_matches}; + #[allow(dead_code)] trait Trait { fn blah(&self); @@ -219,3 +221,27 @@ fn _matches_does_not_trigger_non_exhaustive_omitted_patterns_lint(o: core::sync: // Ordering is a #[non_exhaustive] enum from a separate crate let _m = matches!(o, core::sync::atomic::Ordering::Relaxed); } + +struct MutRefWithDrop<'a>(&'a mut u32); + +// MutRefWithDrop needs to have a non-trivial drop to encounter potential lifetime issues if the +// macros don't introduce a temporary scope. +impl Drop for MutRefWithDrop<'_> { + fn drop(&mut self) { + *self.0 = u32::MAX; + } +} + +#[test] +fn temporary_scope_introduction() { + // Fails to compile if the macros don't introduce a temporary scope, since `&mut val` would + // create a second mutable borrow while `MutRefWithDrop` still holds a unique ref. + // See https://github.com/rust-lang/rust/issues/154406 for reference. + let mut val = 0; + + (assert_matches!(*MutRefWithDrop(&mut val).0, 0), std::mem::take(&mut val)); + (assert_matches!(*MutRefWithDrop(&mut val).0, 0, "msg"), std::mem::take(&mut val)); + + (debug_assert_matches!(*MutRefWithDrop(&mut val).0, 0), std::mem::take(&mut val)); + (debug_assert_matches!(*MutRefWithDrop(&mut val).0, 0, "msg"), std::mem::take(&mut val)); +} diff --git a/coretests/tests/manually_drop.rs b/coretests/tests/manually_drop.rs index 1638c82b161b4..db0cb9c31e174 100644 --- a/coretests/tests/manually_drop.rs +++ b/coretests/tests/manually_drop.rs @@ -40,7 +40,7 @@ fn const_drop_in_place() { struct Test<'a>(Dropped<'a>); struct Dropped<'a>(&'a Cell); - impl const Drop for Dropped<'_> { + const impl Drop for Dropped<'_> { fn drop(&mut self) { self.0.set(self.0.get() + 1); } diff --git a/coretests/tests/mem/type_info.rs b/coretests/tests/mem/type_info.rs index 2483b4c2aacd7..9a37a2ba0db5f 100644 --- a/coretests/tests/mem/type_info.rs +++ b/coretests/tests/mem/type_info.rs @@ -67,6 +67,26 @@ fn test_tuples() { _ => unreachable!(), } } + + const { + let ty_id = TypeId::of::<()>(); + assert!(ty_id.size() == Some(size_of::<()>())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 0); + + let ty_id = TypeId::of::<(u8,)>(); + assert!(ty_id.size() == Some(size_of::<(u8,)>())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 1); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + + let ty_id = TypeId::of::<(u8, u16)>(); + assert!(ty_id.size() == Some(size_of::<(u8, u16)>())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 2); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 1).type_id() == TypeId::of::()); + } } #[test] @@ -80,8 +100,7 @@ fn test_structs() { reference: &'static u16, } - let Type { kind: Struct(ty), size, .. } = Type::of::() else { panic!() }; - assert!(size == Some(size_of::())); + let Type { kind: Struct(ty), .. } = Type::of::() else { panic!() }; assert!(!ty.non_exhaustive); assert!(ty.fields.len() == 3); assert!(ty.fields[0].name == "first"); @@ -93,6 +112,14 @@ fn test_structs() { assert!(ty.fields[2].name == "reference"); assert!(ty.fields[2].ty == TypeId::of::<&'static u16>()); assert!(ty.fields[2].offset == offset_of!(TestStruct, reference)); + + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 3); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 1).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 2).type_id() == TypeId::of::<&u16>()); } const { @@ -114,6 +141,13 @@ fn test_structs() { assert!(ty.fields[0].ty == TypeId::of::()); assert!(ty.fields[1].name == "1"); assert!(ty.fields[1].ty == TypeId::of::()); + + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 2); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 1).type_id() == TypeId::of::()); } const { @@ -145,13 +179,19 @@ fn test_unions() { second: u16, } - let Type { kind: Union(ty), size, .. } = Type::of::() else { panic!() }; - assert!(size == Some(size_of::())); + let Type { kind: Union(ty), .. } = Type::of::() else { panic!() }; assert!(ty.fields.len() == 2); assert!(ty.fields[0].name == "first"); assert!(ty.fields[0].offset == offset_of!(TestUnion, first)); assert!(ty.fields[1].name == "second"); assert!(ty.fields[1].offset == offset_of!(TestUnion, second)); + + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + assert!(ty_id.fields(0) == 2); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(0, 1).type_id() == TypeId::of::()); } const { @@ -191,8 +231,7 @@ fn test_enums() { }, } - let Type { kind: Enum(ty), size, .. } = Type::of::() else { panic!() }; - assert!(size == Some(size_of::())); + let Type { kind: Enum(ty), .. } = Type::of::() else { panic!() }; assert!(ty.variants.len() == 3); assert!(ty.variants[0].name == "Some"); @@ -206,15 +245,31 @@ fn test_enums() { assert!(ty.variants[2].name == "Foomp"); assert!(ty.variants[2].non_exhaustive); assert!(ty.variants[2].fields.len() == 2); + + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 3); + assert!(ty_id.fields(0) == 1); + assert!(ty_id.fields(1) == 0); + assert!(ty_id.fields(2) == 2); + assert!(ty_id.field(0, 0).type_id() == TypeId::of::()); + assert!(ty_id.field(2, 0).type_id() == TypeId::of::<()>()); + assert!(ty_id.field(2, 1).type_id() == TypeId::of::<&str>()); } const { - let Type { kind: Enum(ty), size, .. } = Type::of::>() else { panic!() }; - assert!(size == Some(size_of::>())); + let Type { kind: Enum(ty), .. } = Type::of::>() else { panic!() }; assert!(ty.variants.len() == 2); assert!(ty.generics.len() == 1); let Generic::Type(GenericType { ty: generic_ty, .. }) = ty.generics[0] else { panic!() }; assert!(generic_ty == TypeId::of::()); + + let ty_id = TypeId::of::>(); + assert!(ty_id.size() == Some(size_of::>())); + assert!(ty_id.variants() == 2); + assert!(ty_id.fields(0) == 0); + assert!(ty_id.fields(1) == 1); + assert!(ty_id.field(1, 0).type_id() == TypeId::of::()); } } @@ -222,38 +277,56 @@ fn test_enums() { fn test_primitives() { use TypeKind::*; - let Type { kind: Bool(_ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(1)); - - let Type { kind: Char(_ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(4)); - - let Type { kind: Int(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(4)); - assert_eq!(ty.bits, 32); - assert!(ty.signed); - - let Type { kind: Int(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(size_of::())); - assert_eq!(ty.bits as usize, size_of::() * 8); - assert!(ty.signed); - - let Type { kind: Int(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(4)); - assert_eq!(ty.bits, 32); - assert!(!ty.signed); - - let Type { kind: Int(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(size_of::())); - assert_eq!(ty.bits as usize, size_of::() * 8); - assert!(!ty.signed); - - let Type { kind: Float(ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, Some(4)); - assert_eq!(ty.bits, 32); - - let Type { kind: Str(_ty), size, .. } = (const { Type::of::() }) else { panic!() }; - assert_eq!(size, None); + const { + let Type { kind: Bool(_ty), .. } = (const { Type::of::() }) else { panic!() }; + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Char(_ty), .. } = (const { Type::of::() }) else { panic!() }; + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Int(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits == 32); + assert!(ty.signed); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Int(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits as usize == size_of::() * 8); + assert!(ty.signed); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Int(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits == 32); + assert!(!ty.signed); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Int(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits as usize == size_of::() * 8); + assert!(!ty.signed); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Float(ty), .. } = (const { Type::of::() }) else { panic!() }; + assert!(ty.bits == 32); + let ty_id = TypeId::of::(); + assert!(ty_id.size() == Some(size_of::())); + assert!(ty_id.variants() == 1); + + let Type { kind: Str(_ty), .. } = (const { Type::of::() }) else { panic!() }; + let ty_id = TypeId::of::(); + assert!(ty_id.size() == None); + assert!(ty_id.variants() == 1); + } } #[test] diff --git a/coretests/tests/net/ip_addr.rs b/coretests/tests/net/ip_addr.rs index 3fec59d67b748..ea78d7c58e9e4 100644 --- a/coretests/tests/net/ip_addr.rs +++ b/coretests/tests/net/ip_addr.rs @@ -218,18 +218,15 @@ fn ipv6_to_ipv4() { #[test] fn ip_properties() { - macro_rules! ip { - ($s:expr) => { - IpAddr::from_str($s).unwrap() - }; - } - macro_rules! check { ($s:expr) => { check!($s, 0); }; ($s:expr, $mask:expr) => {{ + let ip = IpAddr::from_str($s).unwrap(); + assert_eq!($s, ip.to_string()); + let unspec: u8 = 1 << 0; let loopback: u8 = 1 << 1; let global: u8 = 1 << 2; @@ -238,39 +235,39 @@ fn ip_properties() { let benchmarking: u8 = 1 << 5; if ($mask & unspec) == unspec { - assert!(ip!($s).is_unspecified()); + assert!(ip.is_unspecified()); } else { - assert!(!ip!($s).is_unspecified()); + assert!(!ip.is_unspecified()); } if ($mask & loopback) == loopback { - assert!(ip!($s).is_loopback()); + assert!(ip.is_loopback()); } else { - assert!(!ip!($s).is_loopback()); + assert!(!ip.is_loopback()); } if ($mask & global) == global { - assert!(ip!($s).is_global()); + assert!(ip.is_global()); } else { - assert!(!ip!($s).is_global()); + assert!(!ip.is_global()); } if ($mask & multicast) == multicast { - assert!(ip!($s).is_multicast()); + assert!(ip.is_multicast()); } else { - assert!(!ip!($s).is_multicast()); + assert!(!ip.is_multicast()); } if ($mask & doc) == doc { - assert!(ip!($s).is_documentation()); + assert!(ip.is_documentation()); } else { - assert!(!ip!($s).is_documentation()); + assert!(!ip.is_documentation()); } if ($mask & benchmarking) == benchmarking { - assert!(ip!($s).is_benchmarking()); + assert!(ip.is_benchmarking()); } else { - assert!(!ip!($s).is_benchmarking()); + assert!(!ip.is_benchmarking()); } }}; } @@ -339,18 +336,15 @@ fn ip_properties() { #[test] fn ipv4_properties() { - macro_rules! ip { - ($s:expr) => { - Ipv4Addr::from_str($s).unwrap() - }; - } - macro_rules! check { ($s:expr) => { check!($s, 0); }; ($s:expr, $mask:expr) => {{ + let ip = Ipv4Addr::from_str($s).unwrap(); + assert_eq!($s, ip.to_string()); + let unspec: u16 = 1 << 0; let loopback: u16 = 1 << 1; let private: u16 = 1 << 2; @@ -364,69 +358,69 @@ fn ipv4_properties() { let shared: u16 = 1 << 11; if ($mask & unspec) == unspec { - assert!(ip!($s).is_unspecified()); + assert!(ip.is_unspecified()); } else { - assert!(!ip!($s).is_unspecified()); + assert!(!ip.is_unspecified()); } if ($mask & loopback) == loopback { - assert!(ip!($s).is_loopback()); + assert!(ip.is_loopback()); } else { - assert!(!ip!($s).is_loopback()); + assert!(!ip.is_loopback()); } if ($mask & private) == private { - assert!(ip!($s).is_private()); + assert!(ip.is_private()); } else { - assert!(!ip!($s).is_private()); + assert!(!ip.is_private()); } if ($mask & link_local) == link_local { - assert!(ip!($s).is_link_local()); + assert!(ip.is_link_local()); } else { - assert!(!ip!($s).is_link_local()); + assert!(!ip.is_link_local()); } if ($mask & global) == global { - assert!(ip!($s).is_global()); + assert!(ip.is_global()); } else { - assert!(!ip!($s).is_global()); + assert!(!ip.is_global()); } if ($mask & multicast) == multicast { - assert!(ip!($s).is_multicast()); + assert!(ip.is_multicast()); } else { - assert!(!ip!($s).is_multicast()); + assert!(!ip.is_multicast()); } if ($mask & broadcast) == broadcast { - assert!(ip!($s).is_broadcast()); + assert!(ip.is_broadcast()); } else { - assert!(!ip!($s).is_broadcast()); + assert!(!ip.is_broadcast()); } if ($mask & documentation) == documentation { - assert!(ip!($s).is_documentation()); + assert!(ip.is_documentation()); } else { - assert!(!ip!($s).is_documentation()); + assert!(!ip.is_documentation()); } if ($mask & benchmarking) == benchmarking { - assert!(ip!($s).is_benchmarking()); + assert!(ip.is_benchmarking()); } else { - assert!(!ip!($s).is_benchmarking()); + assert!(!ip.is_benchmarking()); } if ($mask & reserved) == reserved { - assert!(ip!($s).is_reserved()); + assert!(ip.is_reserved()); } else { - assert!(!ip!($s).is_reserved()); + assert!(!ip.is_reserved()); } if ($mask & shared) == shared { - assert!(ip!($s).is_shared()); + assert!(ip.is_shared()); } else { - assert!(!ip!($s).is_shared()); + assert!(!ip.is_shared()); } }}; } @@ -479,23 +473,19 @@ fn ipv4_properties() { #[test] fn ipv6_properties() { - macro_rules! ip { - ($s:expr) => { - Ipv6Addr::from_str($s).unwrap() - }; - } - macro_rules! check { ($s:expr, &[$($octet:expr),*]) => { check!($s, &[$($octet),*], 0); }; ($s:expr, &[$($octet:expr),*], $mask:expr) => { - assert_eq!($s, ip!($s).to_string()); + let ip = Ipv6Addr::from_str($s).unwrap(); + assert_eq!($s, ip.to_string()); + let octets = &[$($octet),*]; - assert_eq!(&ip!($s).octets(), octets); - assert_eq!(Ipv6Addr::from(*octets), ip!($s)); - assert_eq!(Ipv6Addr::from_octets(*octets), ip!($s)); + assert_eq!(&ip.octets(), octets); + assert_eq!(Ipv6Addr::from(*octets), ip); + assert_eq!(Ipv6Addr::from_octets(*octets), ip); let unspecified: u32 = 1 << 0; let loopback: u32 = 1 << 1; @@ -522,84 +512,84 @@ fn ipv6_properties() { let ipv4_mapped: u32 = 1 << 17; if ($mask & unspecified) == unspecified { - assert!(ip!($s).is_unspecified()); + assert!(ip.is_unspecified()); } else { - assert!(!ip!($s).is_unspecified()); + assert!(!ip.is_unspecified()); } if ($mask & loopback) == loopback { - assert!(ip!($s).is_loopback()); + assert!(ip.is_loopback()); } else { - assert!(!ip!($s).is_loopback()); + assert!(!ip.is_loopback()); } if ($mask & unique_local) == unique_local { - assert!(ip!($s).is_unique_local()); + assert!(ip.is_unique_local()); } else { - assert!(!ip!($s).is_unique_local()); + assert!(!ip.is_unique_local()); } if ($mask & global) == global { - assert!(ip!($s).is_global()); + assert!(ip.is_global()); } else { - assert!(!ip!($s).is_global()); + assert!(!ip.is_global()); } if ($mask & unicast_link_local) == unicast_link_local { - assert!(ip!($s).is_unicast_link_local()); + assert!(ip.is_unicast_link_local()); } else { - assert!(!ip!($s).is_unicast_link_local()); + assert!(!ip.is_unicast_link_local()); } if ($mask & unicast_global) == unicast_global { - assert!(ip!($s).is_unicast_global()); + assert!(ip.is_unicast_global()); } else { - assert!(!ip!($s).is_unicast_global()); + assert!(!ip.is_unicast_global()); } if ($mask & documentation) == documentation { - assert!(ip!($s).is_documentation()); + assert!(ip.is_documentation()); } else { - assert!(!ip!($s).is_documentation()); + assert!(!ip.is_documentation()); } if ($mask & benchmarking) == benchmarking { - assert!(ip!($s).is_benchmarking()); + assert!(ip.is_benchmarking()); } else { - assert!(!ip!($s).is_benchmarking()); + assert!(!ip.is_benchmarking()); } if ($mask & multicast) != 0 { - assert!(ip!($s).multicast_scope().is_some()); - assert!(ip!($s).is_multicast()); + assert!(ip.multicast_scope().is_some()); + assert!(ip.is_multicast()); } else { - assert!(ip!($s).multicast_scope().is_none()); - assert!(!ip!($s).is_multicast()); + assert!(ip.multicast_scope().is_none()); + assert!(!ip.is_multicast()); } if ($mask & multicast_interface_local) == multicast_interface_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::InterfaceLocal); } if ($mask & multicast_link_local) == multicast_link_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::LinkLocal); } if ($mask & multicast_realm_local) == multicast_realm_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::RealmLocal); } if ($mask & multicast_admin_local) == multicast_admin_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::AdminLocal); } if ($mask & multicast_site_local) == multicast_site_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::SiteLocal); } if ($mask & multicast_organization_local) == multicast_organization_local { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::OrganizationLocal); } if ($mask & multicast_global) == multicast_global { - assert_eq!(ip!($s).multicast_scope().unwrap(), + assert_eq!(ip.multicast_scope().unwrap(), Ipv6MulticastScope::Global); } if ($mask & ipv4_mapped) == ipv4_mapped { - assert!(ip!($s).is_ipv4_mapped()); + assert!(ip.is_ipv4_mapped()); } else { - assert!(!ip!($s).is_ipv4_mapped()); + assert!(!ip.is_ipv4_mapped()); } } } diff --git a/coretests/tests/nonzero.rs b/coretests/tests/nonzero.rs index 861e9e05081fc..55d479efb4b40 100644 --- a/coretests/tests/nonzero.rs +++ b/coretests/tests/nonzero.rs @@ -282,11 +282,11 @@ fn test_nonzero_from_int_on_success() { #[test] fn test_nonzero_from_int_on_err() { - assert!(NonZero::::try_from(0).is_err()); - assert!(NonZero::::try_from(0).is_err()); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); - assert!(NonZero::::try_from(0).is_err()); - assert!(NonZero::::try_from(0).is_err()); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); } #[test] diff --git a/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs b/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs index 2a82ae326c223..c0ff8175eef30 100644 --- a/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs +++ b/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs @@ -51,7 +51,7 @@ float_test! { name: preserve_signed_zero, attrs: { const: #[cfg(false)], - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], f128: #[cfg(false)], }, test { @@ -67,7 +67,7 @@ float_test! { name: preserve_signed_infinity, attrs: { const: #[cfg(false)], - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], f128: #[cfg(false)], }, test { @@ -83,7 +83,7 @@ float_test! { name: infinity_to_str, attrs: { const: #[cfg(false)], - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], f128: #[cfg(false)], }, test { @@ -109,7 +109,7 @@ float_test! { name: nan_to_str, attrs: { const: #[cfg(false)], - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], f128: #[cfg(false)], }, test { @@ -127,7 +127,7 @@ float_test! { name: infinity_from_str, attrs: { const: #[cfg(false)], - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], f128: #[cfg(false)], }, test { @@ -152,7 +152,7 @@ float_test! { name: qnan_from_str, attrs: { const: #[cfg(false)], - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], f128: #[cfg(false)], }, test { diff --git a/coretests/tests/num/floats.rs b/coretests/tests/num/floats.rs index d87f850944503..1d7956b41c9d1 100644 --- a/coretests/tests/num/floats.rs +++ b/coretests/tests/num/floats.rs @@ -2,6 +2,9 @@ use std::hint::black_box; use std::num::FpCategory as Fp; use std::ops::{Add, Div, Mul, Rem, Sub}; +/// i586 has issues with floating point precision. +const I586: bool = cfg!(target_arch = "x86") && cfg!(not(target_feature = "sse2")); + pub(crate) trait TestableFloat: Sized { const BITS: u32; /// Unsigned int with the same size, for converting to/from bits. @@ -59,17 +62,22 @@ pub(crate) trait TestableFloat: Sized { const NEG_MUL_ADD_RESULT: Self; /// Reciprocal of the maximum val const MAX_RECIP: Self; + const ASINH_ACOSH_MAX: Self; } impl TestableFloat for f16 { const BITS: u32 = 16; type Int = u16; type SInt = i16; - const APPROX: Self = 1e-3; - const POWF_APPROX: Self = 5e-1; + /// Miri adds some extra errors to float functions; make sure the tests still pass. + /// These values are purely used as a canary to test against and are thus not a stable guarantee Rust provides. + /// They serve as a way to get an idea of the real precision of floating point operations on different platforms. + const APPROX: Self = if cfg!(miri) { 1e-2 } else { 1e-3 }; + const POWF_APPROX: Self = if cfg!(miri) { 1e-0 } else { 5e-1 }; const _180_TO_RADIANS_APPROX: Self = 1e-2; const PI_TO_DEGREES_APPROX: Self = 0.125; - const EXP_APPROX: Self = 1e-2; + const EXP_APPROX: Self = if cfg!(miri) { 5e-1 } else { 1e-2 }; // for values on the order of 150, 4 ULP are more than 0.1... + const POWI_APPROX: Self = if cfg!(miri) { 1e-1 } else { Self::APPROX }; const LN_APPROX: Self = 1e-2; const LOG_APPROX: Self = 1e-2; const LOG2_APPROX: Self = 1e-2; @@ -103,6 +111,7 @@ impl TestableFloat for f16 { const MUL_ADD_RESULT: Self = 62.031; const NEG_MUL_ADD_RESULT: Self = 48.625; const MAX_RECIP: Self = 1.526624e-5; + const ASINH_ACOSH_MAX: Self = 11.781; } impl TestableFloat for f32 { @@ -120,8 +129,20 @@ impl TestableFloat for f32 { const LOG_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; const LOG2_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; const LOG10_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; - const ASINH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; - const ACOSH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const ASINH_APPROX: Self = if cfg!(miri) { + 1e-3 + } else if I586 { + 1e-5 + } else { + Self::APPROX + }; + const ACOSH_APPROX: Self = if cfg!(miri) { + 1e-3 + } else if I586 { + 1e-5 + } else { + Self::APPROX + }; const ATANH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; const GAMMA_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; const GAMMA_APPROX_LOOSE: Self = if cfg!(miri) { 1e-2 } else { 1e-4 }; @@ -149,6 +170,7 @@ impl TestableFloat for f32 { const MUL_ADD_RESULT: Self = 62.05; const NEG_MUL_ADD_RESULT: Self = 48.65; const MAX_RECIP: Self = 2.938736e-39; + const ASINH_ACOSH_MAX: Self = 89.4159851; } impl TestableFloat for f64 { @@ -180,6 +202,7 @@ impl TestableFloat for f64 { const MUL_ADD_RESULT: Self = 62.050000000000004; const NEG_MUL_ADD_RESULT: Self = 48.650000000000006; const MAX_RECIP: Self = 5.562684646268003e-309; + const ASINH_ACOSH_MAX: Self = 710.47586007394398; } impl TestableFloat for f128 { @@ -221,6 +244,7 @@ impl TestableFloat for f128 { const MUL_ADD_RESULT: Self = 62.0500000000000000000000000000000037; const NEG_MUL_ADD_RESULT: Self = 48.6500000000000000000000000000000049; const MAX_RECIP: Self = 8.40525785778023376565669454330438228902076605e-4933; + const ASINH_ACOSH_MAX: Self = 11357.216553474703894801348310092223; } /// Determine the tolerance for values of the argument type. @@ -420,8 +444,8 @@ pub(crate) use float_test; float_test! { name: num, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let two: Float = 2.0; @@ -438,6 +462,7 @@ float_test! { float_test! { name: num_rem, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -451,8 +476,8 @@ float_test! { float_test! { name: nan, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let nan: Float = Float::NAN; @@ -471,8 +496,8 @@ float_test! { float_test! { name: infinity, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let inf: Float = Float::INFINITY; @@ -489,8 +514,8 @@ float_test! { float_test! { name: neg_infinity, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let neg_inf: Float = Float::NEG_INFINITY; @@ -507,8 +532,8 @@ float_test! { float_test! { name: zero, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { assert_biteq!(0.0, Float::ZERO); @@ -525,8 +550,8 @@ float_test! { float_test! { name: neg_zero, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let neg_zero: Float = -0.0; @@ -545,8 +570,8 @@ float_test! { float_test! { name: one, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { assert_biteq!(1.0, Float::ONE); @@ -563,8 +588,8 @@ float_test! { float_test! { name: is_nan, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let nan: Float = Float::NAN; @@ -584,8 +609,8 @@ float_test! { float_test! { name: is_infinite, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let nan: Float = Float::NAN; @@ -605,8 +630,8 @@ float_test! { float_test! { name: is_finite, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let nan: Float = Float::NAN; @@ -626,8 +651,8 @@ float_test! { float_test! { name: is_normal, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let nan: Float = Float::NAN; @@ -648,7 +673,7 @@ float_test! { float_test! { name: classify, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], }, test { let nan: Float = Float::NAN; @@ -669,6 +694,7 @@ float_test! { float_test! { name: min, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -710,6 +736,7 @@ float_test! { float_test! { name: max, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -752,6 +779,7 @@ float_test! { float_test! { name: minimum, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -783,6 +811,7 @@ float_test! { float_test! { name: maximum, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -815,6 +844,7 @@ float_test! { float_test! { name: midpoint, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -867,9 +897,9 @@ float_test! { name: midpoint_large_magnitude, attrs: { const: #[cfg(false)], - // FIXME(f16_f128): `powi` does not work in Miri for these types - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + // Needs powi + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { // test if large differences in magnitude are still correctly computed. @@ -898,6 +928,7 @@ float_test! { float_test! { name: abs, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -916,6 +947,7 @@ float_test! { float_test! { name: copysign, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -931,6 +963,7 @@ float_test! { name: rem_euclid, attrs: { const: #[cfg(false)], + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -948,6 +981,7 @@ float_test! { name: div_euclid, attrs: { const: #[cfg(false)], + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -963,6 +997,7 @@ float_test! { float_test! { name: floor, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -992,6 +1027,7 @@ float_test! { float_test! { name: ceil, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1021,6 +1057,7 @@ float_test! { float_test! { name: round, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1051,6 +1088,7 @@ float_test! { float_test! { name: round_ties_even, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1081,6 +1119,7 @@ float_test! { float_test! { name: trunc, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1110,6 +1149,7 @@ float_test! { float_test! { name: fract, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1141,6 +1181,7 @@ float_test! { float_test! { name: signum, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1159,8 +1200,8 @@ float_test! { float_test! { name: is_sign_positive, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { assert!(Float::INFINITY.is_sign_positive()); @@ -1178,8 +1219,8 @@ float_test! { float_test! { name: is_sign_negative, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { assert!(!Float::INFINITY.is_sign_negative()); @@ -1197,8 +1238,8 @@ float_test! { float_test! { name: next_up, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { assert_biteq!(Float::NEG_INFINITY.next_up(), Float::MIN); @@ -1228,8 +1269,8 @@ float_test! { float_test! { name: next_down, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { assert_biteq!(Float::NEG_INFINITY.next_down(), Float::NEG_INFINITY); @@ -1261,6 +1302,7 @@ float_test! { name: sqrt_domain, attrs: { const: #[cfg(false)], + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1279,10 +1321,10 @@ float_test! { name: clamp_min_greater_than_max, attrs: { const: #[cfg(false)], - f16: #[should_panic, cfg(any(miri, target_has_reliable_f16))], + f16: #[should_panic, cfg(target_has_reliable_f16)], f32: #[should_panic], f64: #[should_panic], - f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], + f128: #[should_panic, cfg(target_has_reliable_f128)], }, test { let _ = Float::ONE.clamp(3.0, 1.0); @@ -1293,10 +1335,10 @@ float_test! { name: clamp_min_is_nan, attrs: { const: #[cfg(false)], - f16: #[should_panic, cfg(any(miri, target_has_reliable_f16))], + f16: #[should_panic, cfg(target_has_reliable_f16)], f32: #[should_panic], f64: #[should_panic], - f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], + f128: #[should_panic, cfg(target_has_reliable_f128)], }, test { let _ = Float::ONE.clamp(Float::NAN, 1.0); @@ -1307,10 +1349,10 @@ float_test! { name: clamp_max_is_nan, attrs: { const: #[cfg(false)], - f16: #[should_panic, cfg(any(miri, target_has_reliable_f16))], + f16: #[should_panic, cfg(target_has_reliable_f16)], f32: #[should_panic], f64: #[should_panic], - f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], + f128: #[should_panic, cfg(target_has_reliable_f128)], }, test { let _ = Float::ONE.clamp(3.0, Float::NAN); @@ -1320,6 +1362,7 @@ float_test! { float_test! { name: total_cmp, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1425,6 +1468,7 @@ float_test! { name: total_cmp_s_nan, attrs: { const: #[cfg(false)], + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1481,6 +1525,7 @@ float_test! { float_test! { name: recip, attrs: { + // Miri only uses softfloats here, so that always works f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, @@ -1504,9 +1549,8 @@ float_test! { name: powi, attrs: { const: #[cfg(false)], - // FIXME(f16_f128): `powi` does not work in Miri for these types - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { let nan: Float = Float::NAN; @@ -1526,8 +1570,8 @@ float_test! { name: powf, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { let nan: Float = Float::NAN; @@ -1549,8 +1593,8 @@ float_test! { name: exp, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { assert_biteq!(1.0, flt(0.0).exp()); @@ -1570,8 +1614,8 @@ float_test! { name: exp2, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { assert_approx_eq!(32.0, flt(5.0).exp2(), Float::EXP_APPROX); @@ -1590,8 +1634,8 @@ float_test! { name: ln, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { let nan: Float = Float::NAN; @@ -1612,8 +1656,8 @@ float_test! { name: log, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { let nan: Float = Float::NAN; @@ -1637,8 +1681,8 @@ float_test! { name: log2, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { let nan: Float = Float::NAN; @@ -1660,8 +1704,8 @@ float_test! { name: log10, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { let nan: Float = Float::NAN; @@ -1684,8 +1728,8 @@ float_test! { name: asinh, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { assert_biteq!(flt(0.0).asinh(), 0.0); @@ -1705,6 +1749,9 @@ float_test! { assert_approx_eq!(flt(-200.0).asinh(), -5.991470797049389, Float::ASINH_APPROX); + // issue 153878: large values were rounding to infinity + assert_approx_eq!(Float::MAX.asinh(), Float::ASINH_ACOSH_MAX, Float::ASINH_APPROX); + #[allow(overflowing_literals)] if Float::MAX > flt(66000.0) { // regression test for the catastrophic cancellation fixed in 72486 @@ -1717,8 +1764,8 @@ float_test! { name: acosh, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { assert_biteq!(flt(1.0).acosh(), 0.0); @@ -1733,6 +1780,9 @@ float_test! { assert_approx_eq!(flt(2.0).acosh(), 1.31695789692481670862504634730796844, Float::ACOSH_APPROX); assert_approx_eq!(flt(3.0).acosh(), 1.76274717403908605046521864995958461, Float::ACOSH_APPROX); + // issue 153878: large values were rounding to infinity + assert_approx_eq!(Float::MAX.acosh(), Float::ASINH_ACOSH_MAX, Float::ACOSH_APPROX); + #[allow(overflowing_literals)] if Float::MAX > flt(66000.0) { // test for low accuracy from issue 104548 @@ -1745,8 +1795,8 @@ float_test! { name: atanh, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { assert_biteq!(flt(0.0).atanh(), 0.0); @@ -1771,8 +1821,8 @@ float_test! { name: gamma, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { assert_approx_eq!(flt(1.0).gamma(), 1.0, Float::GAMMA_APPROX); @@ -1806,8 +1856,8 @@ float_test! { name: ln_gamma, attrs: { const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { assert_approx_eq!(flt(1.0).ln_gamma().0, 0.0, Float::LNGAMMA_APPROX); @@ -1824,8 +1874,8 @@ float_test! { float_test! { name: to_degrees, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let pi: Float = consts::PI; @@ -1845,8 +1895,8 @@ float_test! { float_test! { name: to_radians, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let pi: Float = consts::PI; @@ -1866,8 +1916,8 @@ float_test! { float_test! { name: to_algebraic, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { let a: Float = flt(123.0); @@ -1890,8 +1940,8 @@ float_test! { float_test! { name: to_bits_conv, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { assert_biteq!(flt(1.0), Float::RAW_1); @@ -1917,11 +1967,11 @@ float_test! { float_test! { name: mul_add, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], + f16: #[cfg(target_has_reliable_f16)], // FIXME(#140515): mingw has an incorrect fma https://sourceforge.net/p/mingw-w64/bugs/848/ f32: #[cfg_attr(all(target_os = "windows", target_env = "gnu", not(target_abi = "llvm")), ignore)], f64: #[cfg_attr(all(target_os = "windows", target_env = "gnu", not(target_abi = "llvm")), ignore)], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f128: #[cfg(target_has_reliable_f128)], }, test { let nan: Float = Float::NAN; @@ -1942,8 +1992,8 @@ float_test! { float_test! { name: from, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { assert_biteq!(Float::from(false), Float::ZERO); @@ -1964,7 +2014,7 @@ float_test! { attrs: { f16: #[cfg(false)], const f16: #[cfg(false)], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f128: #[cfg(target_has_reliable_f128)], }, test { assert_biteq!(Float::from(u16::MIN), Float::ZERO); @@ -1983,7 +2033,7 @@ float_test! { const f16: #[cfg(false)], f32: #[cfg(false)], const f32: #[cfg(false)], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f128: #[cfg(target_has_reliable_f128)], }, test { assert_biteq!(Float::from(u32::MIN), Float::ZERO); @@ -1999,8 +2049,8 @@ float_test! { float_test! { name: max_exact_integer_constant, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { // The maximum integer that converts to a unique floating point @@ -2041,8 +2091,8 @@ float_test! { float_test! { name: min_exact_integer_constant, attrs: { - f16: #[cfg(any(miri, target_has_reliable_f16))], - f128: #[cfg(any(miri, target_has_reliable_f128))], + f16: #[cfg(target_has_reliable_f16)], + f128: #[cfg(target_has_reliable_f128)], }, test { // The minimum integer that converts to a unique floating point @@ -2089,7 +2139,7 @@ float_test! { // f16: #[cfg(false)], // f32: #[cfg(false)], // f64: #[cfg(false)], -// f128: #[cfg(any(miri, target_has_reliable_f128))], +// f128: #[cfg(target_has_reliable_f128)], // }, // test { // assert_biteq!(Float::from(u64::MIN), Float::ZERO); @@ -2106,8 +2156,8 @@ float_test! { attrs: { // FIXME(f16_f128): add math tests when available const: #[cfg(false)], - f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], - f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + f16: #[cfg(target_has_reliable_f16_math)], + f128: #[cfg(target_has_reliable_f128_math)], }, test { let pi: Float = consts::PI; diff --git a/coretests/tests/num/flt2dec/mod.rs b/coretests/tests/num/flt2dec/mod.rs index 4888d9d1de06a..02a5d31553da1 100644 --- a/coretests/tests/num/flt2dec/mod.rs +++ b/coretests/tests/num/flt2dec/mod.rs @@ -793,7 +793,15 @@ where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit], i16) -> (&'a [u8], i16), { to_string_with_parts(|buf, parts| { - to_exact_exp_str(|d, b, l| f(d, b, l), v, sign, ndigits, upper, buf, parts) + to_exact_exp_str( + |d, b, l| f(d, b, l), + v, + sign, + ndigits.saturating_sub(1), + upper, + buf, + parts, + ) }) } diff --git a/coretests/tests/num/int_log.rs b/coretests/tests/num/int_log.rs index e8d35fc21ce6e..c8eebebc27515 100644 --- a/coretests/tests/num/int_log.rs +++ b/coretests/tests/num/int_log.rs @@ -3,9 +3,9 @@ /// Rounds the argument down to the next integer, except that we account for potential imprecision /// in the input, so if `f` is very close to an integer, it will round to that. fn round_down_imprecise(f: f32) -> u32 { - // Rounds up for values less than 16*EPSILON below an integer, + // Rounds up for values less than 32*EPSILON below an integer, // and rounds down for everything else. - (f + 16.0 * f32::EPSILON) as u32 + (f + 32.0 * f32::EPSILON) as u32 } #[test] @@ -50,7 +50,6 @@ fn checked_ilog() { } #[test] -#[cfg_attr(miri, ignore)] // FIXME test is broken on Miri: https://github.com/rust-lang/rust/issues/137591 fn checked_ilog2() { assert_eq!(5u32.checked_ilog2(), Some(2)); assert_eq!(0u64.checked_ilog2(), None); diff --git a/coretests/tests/num/int_macros.rs b/coretests/tests/num/int_macros.rs index 2b641f595eba4..1334881aad68d 100644 --- a/coretests/tests/num/int_macros.rs +++ b/coretests/tests/num/int_macros.rs @@ -433,12 +433,6 @@ macro_rules! int_module { assert_eq_const_safe!(($T, bool): (0 as $T).borrowing_sub(MIN, true), (MAX, false)); } - fn test_widening_mul() { - assert_eq_const_safe!(($U, $T): MAX.widening_mul(MAX), (1, MAX / 2)); - assert_eq_const_safe!(($U, $T): MIN.widening_mul(MAX), (MIN as $U, MIN / 2)); - assert_eq_const_safe!(($U, $T): MIN.widening_mul(MIN), (0, MAX / 2 + 1)); - } - fn test_carrying_mul() { assert_eq_const_safe!(($U, $T): MAX.carrying_mul(MAX, 0), (1, MAX / 2)); assert_eq_const_safe!(($U, $T): diff --git a/coretests/tests/num/midpoint.rs b/coretests/tests/num/midpoint.rs index 71e980067842a..240a4e8d68aa6 100644 --- a/coretests/tests/num/midpoint.rs +++ b/coretests/tests/num/midpoint.rs @@ -4,7 +4,7 @@ //! - midpoint(-a, -b) == -midpoint(a, b) #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_obvious_impl_i8() { for a in i8::MIN..=i8::MAX { for b in i8::MIN..=i8::MAX { @@ -14,7 +14,7 @@ fn midpoint_obvious_impl_i8() { } #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_obvious_impl_u8() { for a in u8::MIN..=u8::MAX { for b in u8::MIN..=u8::MAX { @@ -24,7 +24,7 @@ fn midpoint_obvious_impl_u8() { } #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_order_expectation_i8() { for a in i8::MIN..=i8::MAX { for b in i8::MIN..=i8::MAX { @@ -34,7 +34,7 @@ fn midpoint_order_expectation_i8() { } #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_order_expectation_u8() { for a in u8::MIN..=u8::MAX { for b in u8::MIN..=u8::MAX { @@ -44,7 +44,7 @@ fn midpoint_order_expectation_u8() { } #[test] -#[cfg(not(miri))] +#[cfg(not(miri))] // Miri is too slow fn midpoint_negative_expectation() { for a in 0..=i8::MAX { for b in 0..=i8::MAX { diff --git a/coretests/tests/num/mod.rs b/coretests/tests/num/mod.rs index e0214c6ae6868..a82ac6fcd45f0 100644 --- a/coretests/tests/num/mod.rs +++ b/coretests/tests/num/mod.rs @@ -374,6 +374,43 @@ fn test_f32f64() { assert!(nan.is_nan()); } +/// Conversions where $source can be represented as bool. +macro_rules! test_impl_try_from_integer_to_bool { + ($fn_name:ident, $source:ty) => { + #[test] + fn $fn_name() { + let max: $source = <$source>::MAX; + let min: $source = <$source>::MIN; + let zero: $source = 0; + let one: $source = 1; + let two: $source = 2; + assert_eq!(bool::try_from(max).unwrap_err().kind(), &IntErrorKind::PosOverflow); + if min != 0 { + assert_eq!(bool::try_from(min).unwrap_err().kind(), &IntErrorKind::NegOverflow); + assert_eq!( + bool::try_from(zero - 1).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); + } + assert_eq!(bool::try_from(zero).unwrap(), false); + assert_eq!(bool::try_from(one).unwrap(), true); + assert_eq!(bool::try_from(two).unwrap_err().kind(), &IntErrorKind::PosOverflow); + } + }; +} + +test_impl_try_from_integer_to_bool! { test_try_u8bool, u8 } +test_impl_try_from_integer_to_bool! { test_try_u16bool, u16 } +test_impl_try_from_integer_to_bool! { test_try_u32bool, u32 } +test_impl_try_from_integer_to_bool! { test_try_u64bool, u64 } +test_impl_try_from_integer_to_bool! { test_try_u128bool, u128 } + +test_impl_try_from_integer_to_bool! { test_try_i8bool, i8 } +test_impl_try_from_integer_to_bool! { test_try_i16bool, i16 } +test_impl_try_from_integer_to_bool! { test_try_i32bool, i32 } +test_impl_try_from_integer_to_bool! { test_try_i64bool, i64 } +test_impl_try_from_integer_to_bool! { test_try_i128bool, i128 } + /// Conversions where the full width of $source can be represented as $target macro_rules! test_impl_try_from_always_ok { ($fn_name:ident, $source:ty, $target: ty) => { @@ -497,9 +534,15 @@ macro_rules! test_impl_try_from_signed_to_unsigned_upper_ok { let zero: $source = 0; let neg_one: $source = -1; assert_eq!(<$target as TryFrom<$source>>::try_from(max).unwrap(), max as $target); - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); - assert!(<$target as TryFrom<$source>>::try_from(neg_one).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(neg_one).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); } }; } @@ -560,7 +603,10 @@ macro_rules! test_impl_try_from_unsigned_to_signed_upper_err { let max = <$source>::MAX; let min = <$source>::MIN; let zero: $source = 0; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(min).unwrap(), min as $target); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); } @@ -623,9 +669,15 @@ macro_rules! test_impl_try_from_same_sign_err { let zero: $source = 0; let t_max = <$target>::MAX; let t_min = <$target>::MIN; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); if min != 0 { - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); } assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); assert_eq!( @@ -712,8 +764,14 @@ macro_rules! test_impl_try_from_signed_to_unsigned_err { let zero: $source = 0; let t_max = <$target>::MAX; let t_min = <$target>::MIN; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); assert_eq!( <$target as TryFrom<$source>>::try_from(t_max as $source).unwrap(), diff --git a/coretests/tests/num/uint_macros.rs b/coretests/tests/num/uint_macros.rs index 8dfa0924bd369..b686df0d14f2d 100644 --- a/coretests/tests/num/uint_macros.rs +++ b/coretests/tests/num/uint_macros.rs @@ -504,10 +504,6 @@ macro_rules! uint_module { assert_eq_const_safe!(($T, bool): $T::MAX.borrowing_sub($T::MAX, true), ($T::MAX, true)); } - fn test_widening_mul() { - assert_eq_const_safe!(($T, $T): $T::MAX.widening_mul($T::MAX), (1, $T::MAX - 1)); - } - fn test_carrying_mul() { assert_eq_const_safe!(($T, $T): $T::MAX.carrying_mul($T::MAX, 0), (1, $T::MAX - 1)); assert_eq_const_safe!(($T, $T): $T::MAX.carrying_mul($T::MAX, $T::MAX), (0, $T::MAX)); diff --git a/coretests/tests/unicode.rs b/coretests/tests/unicode.rs index a8a221db8f955..12eed25a1feae 100644 --- a/coretests/tests/unicode.rs +++ b/coretests/tests/unicode.rs @@ -60,9 +60,9 @@ fn case_ignorable() { #[test] #[cfg_attr(miri, ignore)] // Miri is too slow -fn cased() { - test_boolean_property(test_data::CASED, unicode_data::cased::lookup); - test_boolean_property(test_data::CASED, char::is_cased); +fn lt() { + test_boolean_property(test_data::LT, unicode_data::lt::lookup); + test_boolean_property(test_data::LT, char::is_titlecase); } #[test] diff --git a/coretests/tests/unicode/test_data.rs b/coretests/tests/unicode/test_data.rs index 3071aedcae07a..962770a0ff830 100644 --- a/coretests/tests/unicode/test_data.rs +++ b/coretests/tests/unicode/test_data.rs @@ -392,60 +392,6 @@ pub(super) static CASE_IGNORABLE: &[RangeInclusive; 459] = &[ '\u{e0100}'..='\u{e01ef}', ]; -#[rustfmt::skip] -pub(super) static CASED: &[RangeInclusive; 156] = &[ - '\u{aa}'..='\u{aa}', '\u{b5}'..='\u{b5}', '\u{ba}'..='\u{ba}', '\u{c0}'..='\u{d6}', - '\u{d8}'..='\u{f6}', '\u{f8}'..='\u{1ba}', '\u{1bc}'..='\u{1bf}', '\u{1c4}'..='\u{293}', - '\u{296}'..='\u{2b8}', '\u{2c0}'..='\u{2c1}', '\u{2e0}'..='\u{2e4}', '\u{345}'..='\u{345}', - '\u{370}'..='\u{373}', '\u{376}'..='\u{377}', '\u{37a}'..='\u{37d}', '\u{37f}'..='\u{37f}', - '\u{386}'..='\u{386}', '\u{388}'..='\u{38a}', '\u{38c}'..='\u{38c}', '\u{38e}'..='\u{3a1}', - '\u{3a3}'..='\u{3f5}', '\u{3f7}'..='\u{481}', '\u{48a}'..='\u{52f}', '\u{531}'..='\u{556}', - '\u{560}'..='\u{588}', '\u{10a0}'..='\u{10c5}', '\u{10c7}'..='\u{10c7}', - '\u{10cd}'..='\u{10cd}', '\u{10d0}'..='\u{10fa}', '\u{10fc}'..='\u{10ff}', - '\u{13a0}'..='\u{13f5}', '\u{13f8}'..='\u{13fd}', '\u{1c80}'..='\u{1c8a}', - '\u{1c90}'..='\u{1cba}', '\u{1cbd}'..='\u{1cbf}', '\u{1d00}'..='\u{1dbf}', - '\u{1e00}'..='\u{1f15}', '\u{1f18}'..='\u{1f1d}', '\u{1f20}'..='\u{1f45}', - '\u{1f48}'..='\u{1f4d}', '\u{1f50}'..='\u{1f57}', '\u{1f59}'..='\u{1f59}', - '\u{1f5b}'..='\u{1f5b}', '\u{1f5d}'..='\u{1f5d}', '\u{1f5f}'..='\u{1f7d}', - '\u{1f80}'..='\u{1fb4}', '\u{1fb6}'..='\u{1fbc}', '\u{1fbe}'..='\u{1fbe}', - '\u{1fc2}'..='\u{1fc4}', '\u{1fc6}'..='\u{1fcc}', '\u{1fd0}'..='\u{1fd3}', - '\u{1fd6}'..='\u{1fdb}', '\u{1fe0}'..='\u{1fec}', '\u{1ff2}'..='\u{1ff4}', - '\u{1ff6}'..='\u{1ffc}', '\u{2071}'..='\u{2071}', '\u{207f}'..='\u{207f}', - '\u{2090}'..='\u{209c}', '\u{2102}'..='\u{2102}', '\u{2107}'..='\u{2107}', - '\u{210a}'..='\u{2113}', '\u{2115}'..='\u{2115}', '\u{2119}'..='\u{211d}', - '\u{2124}'..='\u{2124}', '\u{2126}'..='\u{2126}', '\u{2128}'..='\u{2128}', - '\u{212a}'..='\u{212d}', '\u{212f}'..='\u{2134}', '\u{2139}'..='\u{2139}', - '\u{213c}'..='\u{213f}', '\u{2145}'..='\u{2149}', '\u{214e}'..='\u{214e}', - '\u{2160}'..='\u{217f}', '\u{2183}'..='\u{2184}', '\u{24b6}'..='\u{24e9}', - '\u{2c00}'..='\u{2ce4}', '\u{2ceb}'..='\u{2cee}', '\u{2cf2}'..='\u{2cf3}', - '\u{2d00}'..='\u{2d25}', '\u{2d27}'..='\u{2d27}', '\u{2d2d}'..='\u{2d2d}', - '\u{a640}'..='\u{a66d}', '\u{a680}'..='\u{a69d}', '\u{a722}'..='\u{a787}', - '\u{a78b}'..='\u{a78e}', '\u{a790}'..='\u{a7dc}', '\u{a7f1}'..='\u{a7f6}', - '\u{a7f8}'..='\u{a7fa}', '\u{ab30}'..='\u{ab5a}', '\u{ab5c}'..='\u{ab69}', - '\u{ab70}'..='\u{abbf}', '\u{fb00}'..='\u{fb06}', '\u{fb13}'..='\u{fb17}', - '\u{ff21}'..='\u{ff3a}', '\u{ff41}'..='\u{ff5a}', '\u{10400}'..='\u{1044f}', - '\u{104b0}'..='\u{104d3}', '\u{104d8}'..='\u{104fb}', '\u{10570}'..='\u{1057a}', - '\u{1057c}'..='\u{1058a}', '\u{1058c}'..='\u{10592}', '\u{10594}'..='\u{10595}', - '\u{10597}'..='\u{105a1}', '\u{105a3}'..='\u{105b1}', '\u{105b3}'..='\u{105b9}', - '\u{105bb}'..='\u{105bc}', '\u{10780}'..='\u{10780}', '\u{10783}'..='\u{10785}', - '\u{10787}'..='\u{107b0}', '\u{107b2}'..='\u{107ba}', '\u{10c80}'..='\u{10cb2}', - '\u{10cc0}'..='\u{10cf2}', '\u{10d50}'..='\u{10d65}', '\u{10d70}'..='\u{10d85}', - '\u{118a0}'..='\u{118df}', '\u{16e40}'..='\u{16e7f}', '\u{16ea0}'..='\u{16eb8}', - '\u{16ebb}'..='\u{16ed3}', '\u{1d400}'..='\u{1d454}', '\u{1d456}'..='\u{1d49c}', - '\u{1d49e}'..='\u{1d49f}', '\u{1d4a2}'..='\u{1d4a2}', '\u{1d4a5}'..='\u{1d4a6}', - '\u{1d4a9}'..='\u{1d4ac}', '\u{1d4ae}'..='\u{1d4b9}', '\u{1d4bb}'..='\u{1d4bb}', - '\u{1d4bd}'..='\u{1d4c3}', '\u{1d4c5}'..='\u{1d505}', '\u{1d507}'..='\u{1d50a}', - '\u{1d50d}'..='\u{1d514}', '\u{1d516}'..='\u{1d51c}', '\u{1d51e}'..='\u{1d539}', - '\u{1d53b}'..='\u{1d53e}', '\u{1d540}'..='\u{1d544}', '\u{1d546}'..='\u{1d546}', - '\u{1d54a}'..='\u{1d550}', '\u{1d552}'..='\u{1d6a5}', '\u{1d6a8}'..='\u{1d6c0}', - '\u{1d6c2}'..='\u{1d6da}', '\u{1d6dc}'..='\u{1d6fa}', '\u{1d6fc}'..='\u{1d714}', - '\u{1d716}'..='\u{1d734}', '\u{1d736}'..='\u{1d74e}', '\u{1d750}'..='\u{1d76e}', - '\u{1d770}'..='\u{1d788}', '\u{1d78a}'..='\u{1d7a8}', '\u{1d7aa}'..='\u{1d7c2}', - '\u{1d7c4}'..='\u{1d7cb}', '\u{1df00}'..='\u{1df09}', '\u{1df0b}'..='\u{1df1e}', - '\u{1df25}'..='\u{1df2a}', '\u{1e030}'..='\u{1e06d}', '\u{1e900}'..='\u{1e943}', - '\u{1f130}'..='\u{1f149}', '\u{1f150}'..='\u{1f169}', '\u{1f170}'..='\u{1f189}', -]; - #[rustfmt::skip] pub(super) static GRAPHEME_EXTEND: &[RangeInclusive; 383] = &[ '\u{300}'..='\u{36f}', '\u{483}'..='\u{489}', '\u{591}'..='\u{5bd}', '\u{5bf}'..='\u{5bf}', @@ -776,6 +722,13 @@ pub(super) static LOWERCASE: &[RangeInclusive; 676] = &[ '\u{1e030}'..='\u{1e06d}', '\u{1e922}'..='\u{1e943}', ]; +#[rustfmt::skip] +pub(super) static LT: &[RangeInclusive; 10] = &[ + '\u{1c5}'..='\u{1c5}', '\u{1c8}'..='\u{1c8}', '\u{1cb}'..='\u{1cb}', '\u{1f2}'..='\u{1f2}', + '\u{1f88}'..='\u{1f8f}', '\u{1f98}'..='\u{1f9f}', '\u{1fa8}'..='\u{1faf}', + '\u{1fbc}'..='\u{1fbc}', '\u{1fcc}'..='\u{1fcc}', '\u{1ffc}'..='\u{1ffc}', +]; + #[rustfmt::skip] pub(super) static N: &[RangeInclusive; 145] = &[ '\u{b2}'..='\u{b3}', '\u{b9}'..='\u{b9}', '\u{bc}'..='\u{be}', '\u{660}'..='\u{669}', diff --git a/portable-simd/.github/PULL_REQUEST_TEMPLATE.md b/portable-simd/.github/PULL_REQUEST_TEMPLATE.md index 31422b7934501..5d354305e56de 100644 --- a/portable-simd/.github/PULL_REQUEST_TEMPLATE.md +++ b/portable-simd/.github/PULL_REQUEST_TEMPLATE.md @@ -10,7 +10,7 @@ For a given vector math operation on TxN, please add tests for interactions with - [ ] 0 -For a given vector math operation on TxN where T is a float, please add tests for test interactions with: +For a given vector math operation on TxN where T is a float, please add tests for interactions with: - [ ] a really large number, larger than the mantissa - [ ] a really small "subnormal" number - [ ] NaN diff --git a/portable-simd/Cargo.lock b/portable-simd/Cargo.lock index 5a5f0d8907ae3..c3b950bd5069c 100644 --- a/portable-simd/Cargo.lock +++ b/portable-simd/Cargo.lock @@ -2,6 +2,17 @@ # It is not intended for manual editing. version = 4 +[[package]] +name = "async-trait" +version = "0.1.89" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9035ad2d096bed7955a320ee7e2230574d28fd3c3a0f186cbea1ff3c7eed5dbb" +dependencies = [ + "proc-macro2", + "quote", + "syn", +] + [[package]] name = "autocfg" version = "1.5.0" @@ -10,41 +21,43 @@ checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" [[package]] name = "bitflags" -version = "1.3.2" +version = "2.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" +checksum = "843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af" [[package]] name = "bumpalo" -version = "3.19.0" +version = "3.20.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "46c5e41b57b8bba42a04676d81cb89e9ee8e859a1a66f80a5a72e1cb76b34d43" +checksum = "5d20789868f4b01b2f2caec9f5c4e0213b41e3e5702a50157d699ae31ced2fcb" [[package]] -name = "byteorder" -version = "1.5.0" +name = "cast" +version = "0.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b" +checksum = "37b2a672a2cb129a2e41c10b1224bb368f9f37a2b16b612598138befd7b37eb5" [[package]] name = "cc" -version = "1.2.33" +version = "1.2.58" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3ee0f8803222ba5a7e2777dd72ca451868909b1ac410621b676adf07280e9b5f" +checksum = "e1e928d4b69e3077709075a938a05ffbedfa53a84c8f766efbf8220bb1ff60e1" dependencies = [ + "find-msvc-tools", "shlex", ] [[package]] name = "cfg-if" -version = "1.0.1" +version = "1.0.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9555578bc9e57714c812a1f84e4fc5b4d21fcb063490c624de019f7464c91268" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" [[package]] name = "core_simd" version = "0.1.0" dependencies = [ + "getrandom", "proptest", "std_float", "test_helpers", @@ -52,6 +65,12 @@ dependencies = [ "wasm-bindgen-test", ] +[[package]] +name = "find-msvc-tools" +version = "0.1.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582" + [[package]] name = "float-cmp" version = "0.10.0" @@ -61,32 +80,99 @@ dependencies = [ "num-traits", ] +[[package]] +name = "futures-core" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7e3450815272ef58cec6d564423f6e755e25379b217b0bc688e295ba24df6b1d" + +[[package]] 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= [ "proc-macro2", "quote", "syn", ] + +[[package]] +name = "zmij" +version = "1.0.21" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b8848ee67ecc8aedbaf3e4122217aff892639231befc6a1b58d29fff4c2cabaa" diff --git a/portable-simd/Cargo.toml b/portable-simd/Cargo.toml index 21d4584a9f4d9..883140bae3f62 100644 --- a/portable-simd/Cargo.toml +++ b/portable-simd/Cargo.toml @@ -11,3 +11,8 @@ opt-level = 2 [profile.test.package.test_helpers] opt-level = 2 + +[workspace.dependencies.proptest] +version = "1.11" +default-features = false +features = ["alloc", "f16"] diff --git a/portable-simd/beginners-guide.md b/portable-simd/beginners-guide.md index 4250a18315a6e..c56873ea4b8d7 100644 --- a/portable-simd/beginners-guide.md +++ b/portable-simd/beginners-guide.md @@ -56,7 +56,7 @@ The list notes the bit widths available at each feature level, though the operat ### Selecting Additional Target Features -If you want to enable support for a target feature within your build, generally you should use a [target-feature](https://rust-lang.github.io/packed_simd/perf-guide/target-feature/rustflags.html#target-feature) setting within you `RUSTFLAGS` setting. +If you want to enable support for a target feature within your build, generally you should use a [target-feature](https://rust-lang.github.io/packed_simd/perf-guide/target-feature/rustflags.html#target-feature) setting within your `RUSTFLAGS` setting. If you know that you're targeting a specific CPU you can instead use the [target-cpu](https://rust-lang.github.io/packed_simd/perf-guide/target-feature/rustflags.html#target-cpu) flag and the compiler will enable the correct set of features for that CPU. diff --git a/portable-simd/crates/core_simd/Cargo.toml b/portable-simd/crates/core_simd/Cargo.toml index 537ce459c07cd..6e576084ecfba 100644 --- a/portable-simd/crates/core_simd/Cargo.toml +++ b/portable-simd/crates/core_simd/Cargo.toml @@ -18,9 +18,13 @@ wasm-bindgen = "0.2" wasm-bindgen-test = "0.3" [dev-dependencies.proptest] -version = "0.10" +workspace = true + +# Enable the `wasm_js` feature so that getrandom works on wasm32-unknown-unknown. +[dev-dependencies.getrandom] +version = "0.3.4" default-features = false -features = ["alloc"] +features = ["wasm_js"] [dev-dependencies.test_helpers] path = "../test_helpers" diff --git a/portable-simd/crates/core_simd/src/alias.rs b/portable-simd/crates/core_simd/src/alias.rs index 23f121c46197c..6dcfcb660c26a 100644 --- a/portable-simd/crates/core_simd/src/alias.rs +++ b/portable-simd/crates/core_simd/src/alias.rs @@ -153,6 +153,16 @@ alias! { usizex64 64 } + f16 = { + f16x1 1 + f16x2 2 + f16x4 4 + f16x8 8 + f16x16 16 + f16x32 32 + f16x64 64 + } + f32 = { f32x1 1 f32x2 2 diff --git a/portable-simd/crates/core_simd/src/cast.rs b/portable-simd/crates/core_simd/src/cast.rs index 1c3592f807578..69dc7ba50d58d 100644 --- a/portable-simd/crates/core_simd/src/cast.rs +++ b/portable-simd/crates/core_simd/src/cast.rs @@ -44,6 +44,9 @@ impl SimdCast for u64 {} unsafe impl Sealed for usize {} impl SimdCast for usize {} // Safety: primitive number types can be cast to other primitive number types +unsafe impl Sealed for f16 {} +impl SimdCast for f16 {} +// Safety: primitive number types can be cast to other primitive number types unsafe impl Sealed for f32 {} impl SimdCast for f32 {} // Safety: primitive number types can be cast to other primitive number types diff --git a/portable-simd/crates/core_simd/src/lib.rs b/portable-simd/crates/core_simd/src/lib.rs index fe26d99b9194c..413a886f6c5b8 100644 --- a/portable-simd/crates/core_simd/src/lib.rs +++ b/portable-simd/crates/core_simd/src/lib.rs @@ -1,17 +1,16 @@ #![no_std] #![feature( - const_eval_select, convert_float_to_int, + f16, core_intrinsics, decl_macro, - intra_doc_pointers, repr_simd, - simd_ffi, staged_api, prelude_import, ptr_metadata, rustc_attrs )] +#![cfg_attr(doc, feature(intra_doc_pointers))] #![cfg_attr( all( any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm",), @@ -31,6 +30,7 @@ any(target_arch = "powerpc", target_arch = "powerpc64"), feature(stdarch_powerpc) )] +#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))] #![warn(missing_docs, clippy::missing_inline_in_public_items)] // basically all items, really #![deny( unsafe_op_in_unsafe_fn, diff --git a/portable-simd/crates/core_simd/src/masks.rs b/portable-simd/crates/core_simd/src/masks.rs index 3e2209556b66b..cb5d54020f7fc 100644 --- a/portable-simd/crates/core_simd/src/masks.rs +++ b/portable-simd/crates/core_simd/src/masks.rs @@ -371,22 +371,20 @@ where // * perform _unsigned_ reduce-min // * check if the result is -1 or an index - let index = Simd::from_array( - const { - let mut index = [0; N]; - let mut i = 0; - while i < N { - index[i] = i; - i += 1; - } - index - }, - ); + let index: Simd = const { + let mut index = [0; N]; + let mut i = 0; + while i < N { + index[i] = i; + i += 1; + } + // Safety: the input and output are integer vectors + unsafe { core::intrinsics::simd::simd_cast(Simd::from_array(index)) } + }; // Safety: the input and output are integer vectors - let index: Simd = unsafe { core::intrinsics::simd::simd_cast(index) }; - - let masked_index = self.select(index, Self::splat(true).to_simd()); + let masked_index: Simd = + unsafe { core::intrinsics::simd::simd_or((!self).to_simd(), index) }; // Safety: the input and output are integer vectors let masked_index: Simd = @@ -402,7 +400,15 @@ where if min_index.eq(T::TRUE) { None } else { - Some(min_index.to_usize()) + let min_index = min_index.to_usize(); + + // Allow eliminating bounds checks when using the index + // Safety: the index can't exceed the number of elements in the vector + unsafe { + core::hint::assert_unchecked(min_index < N); + } + + Some(min_index) } } } diff --git a/portable-simd/crates/core_simd/src/ops.rs b/portable-simd/crates/core_simd/src/ops.rs index eb6601f734831..c0a06ed465129 100644 --- a/portable-simd/crates/core_simd/src/ops.rs +++ b/portable-simd/crates/core_simd/src/ops.rs @@ -245,7 +245,7 @@ for_base_ops! { // We don't need any special precautions here: // Floats always accept arithmetic ops, but may become NaN. for_base_ops! { - T = (f32, f64); + T = (f16, f32, f64); type Lhs = Simd; type Rhs = Simd; type Output = Self; diff --git a/portable-simd/crates/core_simd/src/ops/unary.rs b/portable-simd/crates/core_simd/src/ops/unary.rs index e1c06167f9790..af7aa8a823d99 100644 --- a/portable-simd/crates/core_simd/src/ops/unary.rs +++ b/portable-simd/crates/core_simd/src/ops/unary.rs @@ -19,6 +19,8 @@ macro_rules! neg { } neg! { + impl Neg for Simd + impl Neg for Simd impl Neg for Simd diff --git a/portable-simd/crates/core_simd/src/simd/cmp/eq.rs b/portable-simd/crates/core_simd/src/simd/cmp/eq.rs index d553d6c040c91..76836404cbc4e 100644 --- a/portable-simd/crates/core_simd/src/simd/cmp/eq.rs +++ b/portable-simd/crates/core_simd/src/simd/cmp/eq.rs @@ -42,7 +42,7 @@ macro_rules! impl_number { } } -impl_number! { f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize } +impl_number! { f16, f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize } macro_rules! impl_mask { { $($integer:ty),* } => { diff --git a/portable-simd/crates/core_simd/src/simd/cmp/ord.rs b/portable-simd/crates/core_simd/src/simd/cmp/ord.rs index 5672fbbf54caa..5a4e74c753b5a 100644 --- a/portable-simd/crates/core_simd/src/simd/cmp/ord.rs +++ b/portable-simd/crates/core_simd/src/simd/cmp/ord.rs @@ -144,7 +144,7 @@ macro_rules! impl_float { } } -impl_float! { f32, f64 } +impl_float! { f16, f32, f64 } macro_rules! impl_mask { { $($integer:ty),* } => { diff --git a/portable-simd/crates/core_simd/src/simd/num/float.rs b/portable-simd/crates/core_simd/src/simd/num/float.rs index 175cbce4f58be..14a31b527872b 100644 --- a/portable-simd/crates/core_simd/src/simd/num/float.rs +++ b/portable-simd/crates/core_simd/src/simd/num/float.rs @@ -430,18 +430,18 @@ macro_rules! impl_trait { #[inline] fn reduce_max(self) -> Self::Scalar { - // Safety: `self` is a float vector - unsafe { core::intrinsics::simd::simd_reduce_max(self) } + // LLVM has no intrinsic we can use here + // (https://github.com/llvm/llvm-project/issues/185827). + self.as_array().iter().copied().fold(Self::Scalar::NAN, Self::Scalar::max) } #[inline] fn reduce_min(self) -> Self::Scalar { - // Safety: `self` is a float vector - unsafe { core::intrinsics::simd::simd_reduce_min(self) } + self.as_array().iter().copied().fold(Self::Scalar::NAN, Self::Scalar::min) } } )* } } -impl_trait! { f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } } +impl_trait! { f16 { bits: u16, mask: i16 }, f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } } diff --git a/portable-simd/crates/core_simd/src/simd/prelude.rs b/portable-simd/crates/core_simd/src/simd/prelude.rs index e5d7a2aeb73df..51b8def3d6eed 100644 --- a/portable-simd/crates/core_simd/src/simd/prelude.rs +++ b/portable-simd/crates/core_simd/src/simd/prelude.rs @@ -7,13 +7,17 @@ #[doc(no_inline)] pub use super::{ - Mask, Simd, + Mask, Select, Simd, ToBytes, cmp::{SimdOrd, SimdPartialEq, SimdPartialOrd}, num::{SimdFloat, SimdInt, SimdUint}, ptr::{SimdConstPtr, SimdMutPtr}, simd_swizzle, }; +#[rustfmt::skip] +#[doc(no_inline)] +pub use super::{f16x1, f16x2, f16x4, f16x8, f16x16, f16x32, f16x64}; + #[rustfmt::skip] #[doc(no_inline)] pub use super::{f32x1, f32x2, f32x4, f32x8, f32x16, f32x32, f32x64}; diff --git a/portable-simd/crates/core_simd/src/vector.rs b/portable-simd/crates/core_simd/src/vector.rs index 5b3a689f3611b..fbef69f267aa5 100644 --- a/portable-simd/crates/core_simd/src/vector.rs +++ b/portable-simd/crates/core_simd/src/vector.rs @@ -363,7 +363,7 @@ where /// corresponding element in `enable` is `true`. /// /// When the element is disabled or out of bounds for the slice, that memory location - /// is not accessed and the corresponding value from `or` is passed through. + /// is not accessed and the default value for the element type is returned. /// /// # Examples /// ``` @@ -371,12 +371,11 @@ where /// # #[cfg(feature = "as_crate")] use core_simd::simd; /// # #[cfg(not(feature = "as_crate"))] use core::simd; /// # use simd::{Simd, Mask}; - /// let vec: Vec = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; - /// let enable = Mask::from_array([true, true, false, true]); - /// let or = Simd::from_array([-5, -4, -3, -2]); + /// let vec: Vec = vec![10, 11, 12]; + /// let enable = Mask::from_array([false, true, true, true]); /// - /// let result = Simd::load_select(&vec, enable, or); - /// assert_eq!(result, Simd::from_array([10, 11, -3, 13])); + /// let result = Simd::load_select_or_default(&vec, enable); + /// assert_eq!(result, Simd::from_array([0, 11, 12, 0])); /// ``` #[must_use] #[inline] @@ -1147,6 +1146,13 @@ unsafe impl SimdElement for isize { type Mask = isize; } +impl Sealed for f16 {} + +// Safety: f16 is a valid SIMD element type, and is supported by this API +unsafe impl SimdElement for f16 { + type Mask = i16; +} + impl Sealed for f32 {} // Safety: f32 is a valid SIMD element type, and is supported by this API diff --git a/portable-simd/crates/core_simd/src/vendor.rs b/portable-simd/crates/core_simd/src/vendor.rs index 57536e4fc77dc..6b3c640c2f7c5 100644 --- a/portable-simd/crates/core_simd/src/vendor.rs +++ b/portable-simd/crates/core_simd/src/vendor.rs @@ -32,3 +32,6 @@ mod powerpc; #[cfg(target_arch = "loongarch64")] mod loongarch64; + +#[cfg(target_arch = "hexagon")] +mod hexagon; diff --git a/portable-simd/crates/core_simd/src/vendor/hexagon.rs b/portable-simd/crates/core_simd/src/vendor/hexagon.rs new file mode 100644 index 0000000000000..2b8ea55fde659 --- /dev/null +++ b/portable-simd/crates/core_simd/src/vendor/hexagon.rs @@ -0,0 +1,40 @@ +//! Conversions to Hexagon HVX SIMD types. + +use crate::simd::*; + +// HVX 128-byte mode (1024-bit vectors) +// Enable with: -C target-feature=+hvx-length128b +#[cfg(target_feature = "hvx-length128b")] +mod hvx_128b { + use super::*; + use core::arch::hexagon::v128::HvxVector; + + // Full vectors (1024-bit) map to HvxVector + from_transmute! { unsafe u16x64 => HvxVector } + from_transmute! { unsafe i16x64 => HvxVector } + from_transmute! { unsafe u32x32 => HvxVector } + from_transmute! { unsafe i32x32 => HvxVector } + from_transmute! { unsafe u64x16 => HvxVector } + from_transmute! { unsafe i64x16 => HvxVector } + + // FIXME: u8x128/i8x128 don't exist in portable-simd (max lane count is 64) + // u8x64/i8x64 are only 512-bit (half of HvxVector in 128B mode) +} + +// HVX 64-byte mode (512-bit vectors) +// Default when hvx-length128b is not specified +#[cfg(not(target_feature = "hvx-length128b"))] +mod hvx_64b { + use super::*; + use core::arch::hexagon::v64::HvxVector; + + // Full vectors (512-bit) map to HvxVector + from_transmute! { unsafe u8x64 => HvxVector } + from_transmute! { unsafe i8x64 => HvxVector } + from_transmute! { unsafe u16x32 => HvxVector } + from_transmute! { unsafe i16x32 => HvxVector } + from_transmute! { unsafe u32x16 => HvxVector } + from_transmute! { unsafe i32x16 => HvxVector } + from_transmute! { unsafe u64x8 => HvxVector } + from_transmute! { unsafe i64x8 => HvxVector } +} diff --git a/portable-simd/crates/core_simd/tests/f16_ops.rs b/portable-simd/crates/core_simd/tests/f16_ops.rs new file mode 100644 index 0000000000000..f89bdf4738f8b --- /dev/null +++ b/portable-simd/crates/core_simd/tests/f16_ops.rs @@ -0,0 +1,10 @@ +#![feature(portable_simd)] +#![feature(f16)] + +#[macro_use] +mod ops_macros; + +// FIXME: some f16 operations cause rustc to hang on wasm simd +// https://github.com/llvm/llvm-project/issues/189251 +#[cfg(not(all(target_arch = "wasm32", target_feature = "simd128")))] +impl_float_tests! { f16, i16 } diff --git a/portable-simd/crates/core_simd/tests/masks.rs b/portable-simd/crates/core_simd/tests/masks.rs index 53fb2367b6055..98a74be8e3955 100644 --- a/portable-simd/crates/core_simd/tests/masks.rs +++ b/portable-simd/crates/core_simd/tests/masks.rs @@ -133,6 +133,19 @@ macro_rules! test_mask_api { cast_impl::(); cast_impl::(); } + + #[test] + fn first_set() { + for bitmask in 0..=u8::MAX { + let mask = Mask::<$type, 8>::from_bitmask(bitmask as u64); + let expected = if bitmask == 0 { + None + } else { + Some(bitmask.trailing_zeros() as usize) + }; + assert_eq!(mask.first_set(), expected); + } + } } } } diff --git a/portable-simd/crates/core_simd/tests/round.rs b/portable-simd/crates/core_simd/tests/round.rs index 4c1ac3c36f894..95b17f415822b 100644 --- a/portable-simd/crates/core_simd/tests/round.rs +++ b/portable-simd/crates/core_simd/tests/round.rs @@ -42,6 +42,14 @@ macro_rules! float_rounding_test { ) } + fn round_ties_even() { + test_helpers::test_unary_elementwise( + &Vector::::round_ties_even, + &Scalar::round_ties_even, + &|_| true, + ) + } + fn fract() { test_helpers::test_unary_elementwise_flush_subnormals( &Vector::::fract, diff --git a/portable-simd/crates/std_float/src/lib.rs b/portable-simd/crates/std_float/src/lib.rs index b269efc9b1d76..ff3525452231a 100644 --- a/portable-simd/crates/std_float/src/lib.rs +++ b/portable-simd/crates/std_float/src/lib.rs @@ -2,6 +2,7 @@ feature = "as_crate", feature(core_intrinsics), feature(portable_simd), + feature(f16), allow(internal_features) )] #[cfg(not(feature = "as_crate"))] @@ -156,14 +157,30 @@ pub trait StdFloat: Sealed + Sized { unsafe { intrinsics::simd_trunc(self) } } + /// Rounds each element to the nearest integer-valued float. + /// Ties are resolved by rounding to the number with an even least significant digit. + #[must_use = "method returns a new vector and does not mutate the original value"] + #[inline] + fn round_ties_even(self) -> Self { + unsafe { intrinsics::simd_round_ties_even(self) } + } + /// Returns the floating point's fractional value, with its integer part removed. #[must_use = "method returns a new vector and does not mutate the original value"] fn fract(self) -> Self; } +impl Sealed for Simd {} impl Sealed for Simd {} impl Sealed for Simd {} +impl StdFloat for Simd { + #[inline] + fn fract(self) -> Self { + self - self.trunc() + } +} + impl StdFloat for Simd { #[inline] fn fract(self) -> Self { diff --git a/portable-simd/crates/std_float/tests/float.rs b/portable-simd/crates/std_float/tests/float.rs index c608ba49564e0..f97e1123c8527 100644 --- a/portable-simd/crates/std_float/tests/float.rs +++ b/portable-simd/crates/std_float/tests/float.rs @@ -25,23 +25,6 @@ macro_rules! unary_approx_test { &core_simd::simd::Simd::<$scalar, LANES>::$func, &$scalar::$func, &|_| true, - 8, - ) - } - )* - } - } -} - -macro_rules! binary_approx_test { - { $scalar:tt, $($func:tt),+ } => { - test_helpers::test_lanes! { - $( - fn $func() { - test_helpers::test_binary_elementwise_approx( - &core_simd::simd::Simd::<$scalar, LANES>::$func, - &$scalar::$func, - &|_, _| true, 16, ) } @@ -71,12 +54,24 @@ macro_rules! impl_tests { mod $scalar { use std_float::StdFloat; - unary_test! { $scalar, sqrt, ceil, floor, round, trunc } + unary_test! { $scalar, sqrt, ceil, floor, round, trunc, round_ties_even } ternary_test! { $scalar, mul_add } // https://github.com/rust-lang/miri/issues/3555 unary_approx_test! { $scalar, sin, cos, exp, exp2, ln, log2, log10 } - binary_approx_test! { $scalar, log } + + // The implementation of log is a.ln() / b.ln(), so there are 2 inexact operations, + // hence a larger ulps is needed. + test_helpers::test_lanes! { + fn log() { + test_helpers::test_binary_elementwise_approx( + &core_simd::simd::Simd::<$scalar, LANES>::log, + &$scalar::log, + &|_, _| true, + 32, + ) + } + } test_helpers::test_lanes! { fn fract() { diff --git a/portable-simd/crates/test_helpers/Cargo.toml b/portable-simd/crates/test_helpers/Cargo.toml index 408bb04c7aa40..da7ef7bd9945c 100644 --- a/portable-simd/crates/test_helpers/Cargo.toml +++ b/portable-simd/crates/test_helpers/Cargo.toml @@ -5,5 +5,5 @@ edition = "2021" publish = false [dependencies] -proptest = { version = "0.10", default-features = false, features = ["alloc"] } +proptest = { workspace = true, features = ["alloc", "std"] } float-cmp = "0.10" diff --git a/portable-simd/crates/test_helpers/src/biteq.rs b/portable-simd/crates/test_helpers/src/biteq.rs index cbc20cda0d626..36761e37dea76 100644 --- a/portable-simd/crates/test_helpers/src/biteq.rs +++ b/portable-simd/crates/test_helpers/src/biteq.rs @@ -53,7 +53,7 @@ macro_rules! impl_float_biteq { }; } -impl_float_biteq! { f32, f64 } +impl_float_biteq! { f16, f32, f64 } impl BitEq for *const T { fn biteq(&self, other: &Self) -> bool { diff --git a/portable-simd/crates/test_helpers/src/lib.rs b/portable-simd/crates/test_helpers/src/lib.rs index eb3d3f68bc2ea..ce3680ac2c306 100644 --- a/portable-simd/crates/test_helpers/src/lib.rs +++ b/portable-simd/crates/test_helpers/src/lib.rs @@ -1,7 +1,7 @@ -#![feature(powerpc_target_feature)] +#![feature(f16)] #![cfg_attr( any(target_arch = "powerpc", target_arch = "powerpc64"), - feature(stdarch_powerpc) + feature(powerpc_target_feature, stdarch_powerpc) )] pub mod array; @@ -47,6 +47,7 @@ impl_num! { u16 } impl_num! { u32 } impl_num! { u64 } impl_num! { usize } +impl_num! { f16 } impl_num! { f32 } impl_num! { f64 } @@ -121,12 +122,23 @@ pub fn make_runner() -> proptest::test_runner::TestRunner { proptest::test_runner::TestRunner::new(proptest::test_runner::Config::with_cases(4)) } +#[track_caller] +fn unwrap_test_error( + x: Result>, +) -> T { + // Using the `Display` instance of the error is much more readable. + match x { + Ok(v) => v, + Err(e) => panic!("{e}"), + } +} + /// Test a function that takes a single value. pub fn test_1( f: &dyn Fn(A) -> proptest::test_runner::TestCaseResult, ) { let mut runner = make_runner(); - runner.run(&A::default_strategy(), f).unwrap(); + unwrap_test_error(runner.run(&A::default_strategy(), f)) } /// Test a function that takes two values. @@ -134,11 +146,11 @@ pub fn test_2 proptest::test_runner::TestCaseResult, ) { let mut runner = make_runner(); - runner - .run(&(A::default_strategy(), B::default_strategy()), |(a, b)| { + unwrap_test_error( + runner.run(&(A::default_strategy(), B::default_strategy()), |(a, b)| { f(a, b) - }) - .unwrap(); + }), + ) } /// Test a function that takes two values. @@ -150,16 +162,14 @@ pub fn test_3< f: &dyn Fn(A, B, C) -> proptest::test_runner::TestCaseResult, ) { let mut runner = make_runner(); - runner - .run( - &( - A::default_strategy(), - B::default_strategy(), - C::default_strategy(), - ), - |(a, b, c)| f(a, b, c), - ) - .unwrap(); + unwrap_test_error(runner.run( + &( + A::default_strategy(), + B::default_strategy(), + C::default_strategy(), + ), + |(a, b, c)| f(a, b, c), + )); } /// Test a unary vector function against a unary scalar function, applied elementwise. diff --git a/portable-simd/crates/test_helpers/src/subnormals.rs b/portable-simd/crates/test_helpers/src/subnormals.rs index b5f19ba47b819..44dfbb3d6c955 100644 --- a/portable-simd/crates/test_helpers/src/subnormals.rs +++ b/portable-simd/crates/test_helpers/src/subnormals.rs @@ -39,7 +39,7 @@ macro_rules! impl_else { } } -impl_float! { f32, f64 } +impl_float! { f16, f32, f64 } impl_else! { i8, i16, i32, i64, isize, u8, u16, u32, u64, usize } /// AltiVec should flush subnormal inputs to zero, but QEMU seems to only flush outputs. diff --git a/portable-simd/rust-toolchain.toml b/portable-simd/rust-toolchain.toml index 639d07df73374..27d2dd6efbbb8 100644 --- a/portable-simd/rust-toolchain.toml +++ b/portable-simd/rust-toolchain.toml @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2026-01-26" +channel = "nightly-2026-04-28" components = ["rustfmt", "clippy", "miri", "rust-src"] diff --git a/portable-simd/triagebot.toml b/portable-simd/triagebot.toml new file mode 100644 index 0000000000000..43048b5e4514c --- /dev/null +++ b/portable-simd/triagebot.toml @@ -0,0 +1,44 @@ +## See for documentation +## of these features. + +# Allow users to use labels commands. +# Documentation at: https://forge.rust-lang.org/triagebot/labeling.html +[relabel] +allow-unauthenticated = [ + "A-*", + "C-*", + "E-*", + "F-*", + "I-*", + "ISA-*", + "O-*", +] + +# Allow users to assign 'r?` someone to an issue or PR. +# Documentation at: https://forge.rust-lang.org/triagebot/issue-assignment.html +[assign] +warn_non_default_branch = true + +# Warns when a PR contains merge commits +# Documentation at: https://forge.rust-lang.org/triagebot/no-merge.html +[no-merges] +exclude_titles = ["Sync from"] + +# Canonicalize issue numbers to avoid closing the wrong issue +# when commits are included in upstream sync, as well as warning links in commits. +# Documentation at: https://forge.rust-lang.org/triagebot/issue-links.html +[issue-links] +check-commits = "uncanonicalized" + +# Enable issue transfers within the org +# Documentation at: https://forge.rust-lang.org/triagebot/transfer.html +[transfer] + +# Enable comments linking to triagebot range-diff when a PR is rebased +# onto a different base commit +# Documentation at: https://forge.rust-lang.org/triagebot/range-diff.html +[range-diff] + +# Add link to the review body to review changes since posting it. +# Documentation at: https://forge.rust-lang.org/triagebot/review-changes-since.html +[review-changes-since] diff --git a/proc_macro/src/bridge/arena.rs b/proc_macro/src/bridge/arena.rs index 5e0393e98fdd2..d4879021f9d87 100644 --- a/proc_macro/src/bridge/arena.rs +++ b/proc_macro/src/bridge/arena.rs @@ -58,11 +58,10 @@ impl Arena { // Also ensure that this chunk can fit `additional`. new_cap = cmp::max(additional, new_cap); - let mut chunk = Box::new_uninit_slice(new_cap); + let chunk = chunks.push_mut(Box::new_uninit_slice(new_cap)); let Range { start, end } = chunk.as_mut_ptr_range(); self.start.set(start); self.end.set(end); - chunks.push(chunk); } /// Allocates a byte slice with specified size from the current memory diff --git a/proc_macro/src/bridge/client.rs b/proc_macro/src/bridge/client.rs index 696cd4ee3d887..3d8ad719f7176 100644 --- a/proc_macro/src/bridge/client.rs +++ b/proc_macro/src/bridge/client.rs @@ -2,19 +2,9 @@ use std::cell::RefCell; use std::marker::PhantomData; -use std::sync::atomic::AtomicU32; use super::*; -#[repr(C)] -pub(super) struct HandleCounters { - pub(super) token_stream: AtomicU32, - pub(super) span: AtomicU32, -} - -static COUNTERS: HandleCounters = - HandleCounters { token_stream: AtomicU32::new(1), span: AtomicU32::new(1) }; - pub(crate) struct TokenStream { handle: handle::Handle, } @@ -47,6 +37,18 @@ impl Decode<'_, '_, S> for TokenStream { } } +impl Encode<()> for crate::TokenStream { + fn encode(self, w: &mut Buffer, s: &mut ()) { + self.0.encode(w, s) + } +} + +impl Decode<'_, '_, ()> for crate::TokenStream { + fn decode(r: &mut &[u8], s: &mut ()) -> Self { + crate::TokenStream(Some(Decode::decode(r, s))) + } +} + #[derive(Copy, Clone, PartialEq, Eq, Hash)] pub(crate) struct Span { handle: handle::Handle, @@ -209,8 +211,6 @@ pub(crate) fn is_available() -> bool { /// and forcing the use of APIs that take/return `S::TokenStream`, server-side. #[repr(C)] pub struct Client { - pub(super) handle_counters: &'static HandleCounters, - pub(super) run: extern "C" fn(BridgeConfig<'_>) -> Buffer, pub(super) _marker: PhantomData O>, @@ -243,14 +243,13 @@ fn maybe_install_panic_hook(force_show_panics: bool) { /// Client-side helper for handling client panics, entering the bridge, /// deserializing input and serializing output. -// FIXME(eddyb) maybe replace `Bridge::enter` with this? -fn run_client Decode<'a, 's, ()>, R: Encode<()>>( +fn run_client Decode<'a, 's, ()>>( config: BridgeConfig<'_>, - f: impl FnOnce(A) -> R, + f: impl FnOnce(A) -> crate::TokenStream, ) -> Buffer { let BridgeConfig { input: mut buf, dispatch, force_show_panics, .. } = config; - panic::catch_unwind(panic::AssertUnwindSafe(|| { + let res = panic::catch_unwind(panic::AssertUnwindSafe(|| { maybe_install_panic_hook(force_show_panics); // Make sure the symbol store is empty before decoding inputs. @@ -267,23 +266,12 @@ fn run_client Decode<'a, 's, ()>, R: Encode<()>>( // Take the `cached_buffer` back out, for the output value. buf = RefCell::into_inner(state).cached_buffer; - // HACK(eddyb) Separate encoding a success value (`Ok(output)`) - // from encoding a panic (`Err(e: PanicMessage)`) to avoid - // having handles outside the `bridge.enter(|| ...)` scope, and - // to catch panics that could happen while encoding the success. - // - // Note that panics should be impossible beyond this point, but - // this is defensively trying to avoid any accidental panicking - // reaching the `extern "C"` (which should `abort` but might not - // at the moment, so this is also potentially preventing UB). - buf.clear(); - Ok::<_, ()>(output).encode(&mut buf, &mut ()); - })) - .map_err(PanicMessage::from) - .unwrap_or_else(|e| { - buf.clear(); - Err::<(), _>(e).encode(&mut buf, &mut ()); - }); + output + })); + + // Serialize response of type `Result`. + buf.clear(); + res.map_err(PanicMessage::from).encode(&mut buf, &mut ()); // Now that a response has been serialized, invalidate all symbols // registered with the interner. @@ -294,9 +282,8 @@ fn run_client Decode<'a, 's, ()>, R: Encode<()>>( impl Client { pub const fn expand1(f: impl Fn(crate::TokenStream) -> crate::TokenStream + Copy) -> Self { Client { - handle_counters: &COUNTERS, run: super::selfless_reify::reify_to_extern_c_fn_hrt_bridge(move |bridge| { - run_client(bridge, |input| f(crate::TokenStream(Some(input))).0) + run_client(bridge, |input| f(input)) }), _marker: PhantomData, } @@ -308,11 +295,8 @@ impl Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream> { f: impl Fn(crate::TokenStream, crate::TokenStream) -> crate::TokenStream + Copy, ) -> Self { Client { - handle_counters: &COUNTERS, run: super::selfless_reify::reify_to_extern_c_fn_hrt_bridge(move |bridge| { - run_client(bridge, |(input, input2)| { - f(crate::TokenStream(Some(input)), crate::TokenStream(Some(input2))).0 - }) + run_client(bridge, |(input, input2)| f(input, input2)) }), _marker: PhantomData, } diff --git a/proc_macro/src/bridge/rpc.rs b/proc_macro/src/bridge/rpc.rs index 7fee8654bc788..8804cf8459abf 100644 --- a/proc_macro/src/bridge/rpc.rs +++ b/proc_macro/src/bridge/rpc.rs @@ -15,20 +15,30 @@ pub(super) trait Decode<'a, 's, S>: Sized { } macro_rules! rpc_encode_decode { - (le $ty:ty) => { + (le $ty:ident $size:literal) => { impl Encode for $ty { fn encode(self, w: &mut Buffer, _: &mut S) { - w.extend_from_array(&self.to_le_bytes()); + const N: usize = size_of::<$ty>(); + + // We can pad with zeros without changing the value because of + // little endian encoding. + let mut bytes = [0; $size]; + bytes[..N].copy_from_slice(&self.to_le_bytes()); + + w.extend_from_array(&bytes); } } impl Decode<'_, '_, S> for $ty { fn decode(r: &mut &[u8], _: &mut S) -> Self { const N: usize = size_of::<$ty>(); + const { + assert!(N <= $size); + } let mut bytes = [0; N]; bytes.copy_from_slice(&r[..N]); - *r = &r[N..]; + *r = &r[$size..]; Self::from_le_bytes(bytes) } @@ -108,8 +118,8 @@ impl Decode<'_, '_, S> for u8 { } } -rpc_encode_decode!(le u32); -rpc_encode_decode!(le usize); +rpc_encode_decode!(le u32 4); +rpc_encode_decode!(le usize 8); impl Encode for bool { fn encode(self, w: &mut Buffer, s: &mut S) { @@ -244,6 +254,14 @@ impl PanicMessage { PanicMessage::Unknown => None, } } + + pub fn into_string(self) -> Option { + match self { + PanicMessage::StaticStr(s) => Some(s.into()), + PanicMessage::String(s) => Some(s), + PanicMessage::Unknown => None, + } + } } impl Encode for PanicMessage { diff --git a/proc_macro/src/bridge/server.rs b/proc_macro/src/bridge/server.rs index 1151798fccf40..6a739da7641d1 100644 --- a/proc_macro/src/bridge/server.rs +++ b/proc_macro/src/bridge/server.rs @@ -1,6 +1,7 @@ //! Server-side traits. use std::cell::Cell; +use std::sync::atomic::AtomicU32; use std::sync::mpsc; use super::*; @@ -11,10 +12,13 @@ pub(super) struct HandleStore { } impl HandleStore { - fn new(handle_counters: &'static client::HandleCounters) -> Self { + fn new() -> Self { + static TOKEN_STREAM: AtomicU32 = AtomicU32::new(1); + static SPAN: AtomicU32 = AtomicU32::new(1); + HandleStore { - token_stream: handle::OwnedStore::new(&handle_counters.token_stream), - span: handle::InternedStore::new(&handle_counters.span), + token_stream: handle::OwnedStore::new(&TOKEN_STREAM), + span: handle::InternedStore::new(&SPAN), } } } @@ -246,13 +250,12 @@ fn run_server< O: for<'a, 's> Decode<'a, 's, HandleStore>, >( strategy: &impl ExecutionStrategy, - handle_counters: &'static client::HandleCounters, server: S, input: I, run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, force_show_panics: bool, ) -> Result { - let mut dispatcher = Dispatcher { handle_store: HandleStore::new(handle_counters), server }; + let mut dispatcher = Dispatcher { handle_store: HandleStore::new(), server }; let globals = dispatcher.server.globals(); @@ -276,16 +279,9 @@ impl client::Client { where S: Server, { - let client::Client { handle_counters, run, _marker } = *self; - run_server( - strategy, - handle_counters, - server, - >::mark(input), - run, - force_show_panics, - ) - .map(|s| >>::unmark(s).unwrap_or_default()) + let client::Client { run, _marker } = *self; + run_server(strategy, server, >::mark(input), run, force_show_panics) + .map(|s| >>::unmark(s).unwrap_or_default()) } } @@ -301,10 +297,9 @@ impl client::Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream where S: Server, { - let client::Client { handle_counters, run, _marker } = *self; + let client::Client { run, _marker } = *self; run_server( strategy, - handle_counters, server, (>::mark(input), >::mark(input2)), run, diff --git a/rtstartup/rsbegin.rs b/rtstartup/rsbegin.rs index 6ee06cce5c630..d268090fe77ae 100644 --- a/rtstartup/rsbegin.rs +++ b/rtstartup/rsbegin.rs @@ -39,12 +39,9 @@ auto trait Freeze {} impl Copy for *mut T {} -#[lang = "drop_in_place"] +#[lang = "drop_glue"] #[inline] -#[allow(unconditional_recursion)] -pub unsafe fn drop_in_place(to_drop: *mut T) { - drop_in_place(to_drop); -} +pub unsafe fn drop_glue(_to_drop: &mut T) {} // Frame unwind info registration // diff --git a/rtstartup/rsend.rs b/rtstartup/rsend.rs index d763971445069..8121135debef3 100644 --- a/rtstartup/rsend.rs +++ b/rtstartup/rsend.rs @@ -27,12 +27,9 @@ auto trait Freeze {} impl Copy for *mut T {} -#[lang = "drop_in_place"] +#[lang = "drop_glue"] #[inline] -#[allow(unconditional_recursion)] -pub unsafe fn drop_in_place(to_drop: *mut T) { - drop_in_place(to_drop); -} +pub unsafe fn drop_glue(_to_drop: &mut T) {} #[cfg(all(target_os = "windows", target_arch = "x86", target_env = "gnu"))] pub mod eh_frames { diff --git a/std/Cargo.toml b/std/Cargo.toml index f7bc729598cd3..4c433d4970cda 100644 --- a/std/Cargo.toml +++ b/std/Cargo.toml @@ -20,7 +20,7 @@ panic_unwind = { path = "../panic_unwind", optional = true } panic_abort = { path = "../panic_abort" } core = { path = "../core", public = true } unwind = { path = "../unwind" } -hashbrown = { version = "0.16.1", default-features = false, features = [ +hashbrown = { version = "0.17.1", default-features = false, features = [ 'rustc-dep-of-std', ] } std_detect = { path = "../std_detect", public = true } @@ -33,7 +33,7 @@ miniz_oxide = { version = "0.8.0", optional = true, default-features = false } addr2line = { version = "0.25.0", optional = true, default-features = false } [target.'cfg(not(all(windows, target_env = "msvc")))'.dependencies] -libc = { version = "0.2.183", default-features = false, features = [ +libc = { version = "0.2.185", default-features = false, features = [ 'rustc-dep-of-std', ], public = true } @@ -79,19 +79,19 @@ hermit-abi = { version = "0.5.0", features = [ ], public = true } [target.'cfg(all(target_os = "wasi", target_env = "p1"))'.dependencies] -wasi = { version = "0.11.0", features = [ +wasip1 = { version = "1.0.0", features = [ 'rustc-dep-of-std', ], default-features = false } [target.'cfg(all(target_os = "wasi", target_env = "p2"))'.dependencies] -wasip2 = { version = '0.14.4', features = [ +wasip2 = { version = '1.0.3', features = [ 'rustc-dep-of-std', -], default-features = false, package = 'wasi' } +], default-features = false } [target.'cfg(all(target_os = "wasi", target_env = "p3"))'.dependencies] -wasip2 = { version = '0.14.4', features = [ +wasip3 = { version = '0.6.0', features = [ 'rustc-dep-of-std', -], default-features = false, package = 'wasi' } +], default-features = false } [target.'cfg(target_os = "uefi")'.dependencies] r-efi = { version = "5.2.0", features = ['rustc-dep-of-std'] } diff --git a/std/src/alloc.rs b/std/src/alloc.rs index ed0322e2cf5d0..7a576e083df7c 100644 --- a/std/src/alloc.rs +++ b/std/src/alloc.rs @@ -142,7 +142,7 @@ impl System { #[inline] fn alloc_impl(&self, layout: Layout, zeroed: bool) -> Result, AllocError> { match layout.size() { - 0 => Ok(NonNull::slice_from_raw_parts(layout.dangling_ptr(), 0)), + 0 => Ok(layout.dangling_ptr().cast_slice(0)), // SAFETY: `layout` is non-zero in size, size => unsafe { let raw_ptr = if zeroed { @@ -151,7 +151,7 @@ impl System { GlobalAlloc::alloc(self, layout) }; let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; - Ok(NonNull::slice_from_raw_parts(ptr, size)) + Ok(ptr.cast_slice(size)) }, } } @@ -187,7 +187,7 @@ impl System { if zeroed { raw_ptr.add(old_size).write_bytes(0, new_size - old_size); } - Ok(NonNull::slice_from_raw_parts(ptr, new_size)) + Ok(ptr.cast_slice(new_size)) }, // SAFETY: because `new_layout.size()` must be greater than or equal to `old_size`, @@ -266,7 +266,7 @@ unsafe impl Allocator for System { // SAFETY: conditions must be upheld by the caller 0 => unsafe { Allocator::deallocate(self, ptr, old_layout); - Ok(NonNull::slice_from_raw_parts(new_layout.dangling_ptr(), 0)) + Ok(new_layout.dangling_ptr().cast_slice(0)) }, // SAFETY: `new_size` is non-zero. Other conditions must be upheld by the caller @@ -276,7 +276,7 @@ unsafe impl Allocator for System { let raw_ptr = GlobalAlloc::realloc(self, ptr.as_ptr(), old_layout, new_size); let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; - Ok(NonNull::slice_from_raw_parts(ptr, new_size)) + Ok(ptr.cast_slice(new_size)) }, // SAFETY: because `new_size` must be smaller than or equal to `old_layout.size()`, diff --git a/std/src/collections/hash/map.rs b/std/src/collections/hash/map.rs index fe49660325e65..887efd12f550f 100644 --- a/std/src/collections/hash/map.rs +++ b/std/src/collections/hash/map.rs @@ -1,13 +1,12 @@ #[cfg(test)] mod tests; -use hashbrown::hash_map as base; +use hashbrown::hash_map::{self as base, RustcOccupiedError}; use self::Entry::*; use crate::alloc::{Allocator, Global}; use crate::borrow::Borrow; use crate::collections::{TryReserveError, TryReserveErrorKind}; -use crate::error::Error; use crate::fmt::{self, Debug}; use crate::hash::{BuildHasher, Hash, RandomState}; use crate::iter::FusedIterator; @@ -20,7 +19,7 @@ use crate::ops::Index; /// reasonable best-effort is made to generate this seed from a high quality, /// secure source of randomness provided by the host without blocking the /// program. Because of this, the randomness of the seed depends on the output -/// quality of the system's random number coroutine when the seed is created. +/// quality of the system's random number generator when the seed is created. /// In particular, seeds generated when the system's entropy pool is abnormally /// low such as during system boot may be of a lower quality. /// @@ -301,8 +300,11 @@ impl HashMap { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] /// use std::collections::HashMap; - /// let mut map: HashMap<&str, i32> = HashMap::new(); + /// use std::alloc::Global; + /// + /// let map: HashMap = HashMap::new_in(Global); /// ``` #[inline] #[must_use] @@ -321,8 +323,11 @@ impl HashMap { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] /// use std::collections::HashMap; - /// let mut map: HashMap<&str, i32> = HashMap::with_capacity(10); + /// use std::alloc::Global; + /// + /// let map: HashMap = HashMap::with_capacity_in(10, Global); /// ``` #[inline] #[must_use] @@ -410,6 +415,18 @@ impl HashMap { /// /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashMap` to be useful, see its documentation for details. + /// + /// # Examples + /// + /// ``` + /// #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashMap; + /// use std::hash::RandomState; + /// + /// let s = RandomState::new(); + /// let map: HashMap = HashMap::with_hasher_in(s, Global); + /// ``` #[inline] #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] @@ -432,6 +449,17 @@ impl HashMap { /// The `hasher` passed should implement the [`BuildHasher`] trait for /// the `HashMap` to be useful, see its documentation for details. /// + /// # Examples + /// + /// ``` + /// #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashMap; + /// use std::hash::RandomState; + /// + /// let s = RandomState::new(); + /// let map: HashMap = HashMap::with_capacity_and_hasher_in(10, s, Global); + /// ``` #[inline] #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] @@ -465,15 +493,16 @@ impl HashMap { /// ``` /// use std::collections::HashMap; /// - /// let map = HashMap::from([ + /// let map: HashMap<&str, i32> = HashMap::from([ /// ("a", 1), /// ("b", 2), /// ("c", 3), /// ]); /// - /// for key in map.keys() { - /// println!("{key}"); - /// } + /// let mut values: Vec<_> = map.keys().copied().collect(); + /// values.sort(); + /// + /// assert_eq!(values, vec!["a", "b", "c"]); /// ``` /// /// # Performance @@ -527,15 +556,16 @@ impl HashMap { /// ``` /// use std::collections::HashMap; /// - /// let map = HashMap::from([ + /// let map: HashMap<&str, i32> = HashMap::from([ /// ("a", 1), /// ("b", 2), /// ("c", 3), /// ]); /// - /// for val in map.values() { - /// println!("{val}"); - /// } + /// let mut values: Vec<_> = map.values().copied().collect(); + /// values.sort(); + /// + /// assert_eq!(values, vec![1, 2, 3]); /// ``` /// /// # Performance @@ -563,12 +593,12 @@ impl HashMap { /// ]); /// /// for val in map.values_mut() { - /// *val = *val + 10; + /// *val += 10; /// } /// - /// for val in map.values() { - /// println!("{val}"); - /// } + /// assert_eq!(map.get("a"), Some(&11)); + /// assert_eq!(map.get("b"), Some(&12)); + /// assert_eq!(map.get("c"), Some(&13)); /// ``` /// /// # Performance @@ -628,9 +658,13 @@ impl HashMap { /// ("c", 3), /// ]); /// - /// for (key, val) in map.iter() { - /// println!("key: {key} val: {val}"); + /// let mut count = 0; + /// + /// for (_key, _val) in map.iter() { + /// count += 1; /// } + /// + /// assert_eq!(count, 3); /// ``` /// /// # Performance @@ -663,9 +697,9 @@ impl HashMap { /// *val *= 2; /// } /// - /// for (key, val) in &map { - /// println!("key: {key} val: {val}"); - /// } + /// assert_eq!(map.get("a"), Some(&2)); + /// assert_eq!(map.get("b"), Some(&4)); + /// assert_eq!(map.get("c"), Some(&6)); /// ``` /// /// # Performance @@ -1304,7 +1338,7 @@ where /// a mutable reference to the value in the entry. /// /// If the map already had this key present, nothing is updated, and - /// an error containing the occupied entry and the value is returned. + /// an error containing the occupied entry, key, and the value is returned. /// /// # Examples /// @@ -1321,13 +1355,16 @@ where /// let err = map.try_insert(37, "b").unwrap_err(); /// assert_eq!(err.entry.key(), &37); /// assert_eq!(err.entry.get(), &"a"); + /// assert_eq!(err.key, 37); /// assert_eq!(err.value, "b"); /// ``` #[unstable(feature = "map_try_insert", issue = "82766")] pub fn try_insert(&mut self, key: K, value: V) -> Result<&mut V, OccupiedError<'_, K, V, A>> { - match self.entry(key) { - Occupied(entry) => Err(OccupiedError { entry, value }), - Vacant(entry) => Ok(entry.insert(value)), + match self.base.rustc_try_insert(key, value) { + Result::Ok(value) => Ok(value), + Result::Err(RustcOccupiedError { entry, key, value, .. }) => { + Err(OccupiedError { entry: OccupiedEntry { base: entry }, key, value }) + } } } @@ -1449,7 +1486,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for HashMap +const impl Default for HashMap where S: [const] Default, { @@ -1978,8 +2015,9 @@ impl Debug for VacantEntry<'_, K, V, A> { /// The error returned by [`try_insert`](HashMap::try_insert) when the key already exists. /// -/// Contains the occupied entry, and the value that was not inserted. +/// Contains the occupied entry, key, and the value that was not inserted. #[unstable(feature = "map_try_insert", issue = "82766")] +#[non_exhaustive] pub struct OccupiedError< 'a, K: 'a, @@ -1988,6 +2026,8 @@ pub struct OccupiedError< > { /// The entry in the map that was already occupied. pub entry: OccupiedEntry<'a, K, V, A>, + /// The key which was not inserted, because the entry was already occupied. + pub key: K, /// The value which was not inserted, because the entry was already occupied. pub value: V, } @@ -1997,28 +2037,13 @@ impl Debug for OccupiedError<'_, K, V, A> { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("OccupiedError") .field("key", self.entry.key()) + .field("uninserted_key", &self.key) .field("old_value", self.entry.get()) .field("new_value", &self.value) .finish_non_exhaustive() } } -#[unstable(feature = "map_try_insert", issue = "82766")] -impl<'a, K: Debug, V: Debug, A: Allocator> fmt::Display for OccupiedError<'a, K, V, A> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - write!( - f, - "failed to insert {:?}, key {:?} already exists with value {:?}", - self.value, - self.entry.key(), - self.entry.get(), - ) - } -} - -#[unstable(feature = "map_try_insert", issue = "82766")] -impl<'a, K: Debug, V: Debug, A: Allocator> Error for OccupiedError<'a, K, V, A> {} - #[stable(feature = "rust1", since = "1.0.0")] impl<'a, K, V, S, A: Allocator> IntoIterator for &'a HashMap { type Item = (&'a K, &'a V); diff --git a/std/src/collections/hash/set.rs b/std/src/collections/hash/set.rs index 0fe26848fe7bb..b0a8e8ff42149 100644 --- a/std/src/collections/hash/set.rs +++ b/std/src/collections/hash/set.rs @@ -176,6 +176,15 @@ impl HashSet { /// /// The hash set is initially created with a capacity of 0, so it will not allocate until it /// is first inserted into. + /// # Examples + /// + /// ``` + /// # #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashSet; + /// + /// let set: HashSet = HashSet::new_in(Global); + /// ``` #[inline] #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] @@ -192,9 +201,11 @@ impl HashSet { /// # Examples /// /// ``` + /// # #![feature(allocator_api)] /// use std::collections::HashSet; - /// let set: HashSet = HashSet::with_capacity(10); - /// assert!(set.capacity() >= 10); + /// use std::alloc::Global; + /// + /// let set: HashSet = HashSet::with_capacity_in(10, Global); /// ``` #[inline] #[must_use] @@ -282,6 +293,18 @@ impl HashSet { /// /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashSet` to be useful, see its documentation for details. + /// + /// # Examples + /// + /// ``` + /// # #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashSet; + /// use std::hash::RandomState; + /// + /// let s = RandomState::new(); + /// let set: HashSet = HashSet::with_hasher_in(s, Global); + /// ``` #[inline] #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] @@ -303,6 +326,18 @@ impl HashSet { /// /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashSet` to be useful, see its documentation for details. + /// + /// # Examples + /// + /// ``` + /// # #![feature(allocator_api)] + /// use std::alloc::Global; + /// use std::collections::HashSet; + /// use std::hash::RandomState; + /// + /// let s = RandomState::new(); + /// let set: HashSet = HashSet::with_capacity_and_hasher_in(10, s, Global); + /// ``` #[inline] #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] @@ -1241,7 +1276,7 @@ where #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for HashSet +const impl Default for HashSet where S: [const] Default, { diff --git a/std/src/env.rs b/std/src/env.rs index d3e4417656e9a..a4a5e8561dfcf 100644 --- a/std/src/env.rs +++ b/std/src/env.rs @@ -220,14 +220,13 @@ impl fmt::Debug for VarsOs { /// ``` #[stable(feature = "env", since = "1.0.0")] pub fn var>(key: K) -> Result { - _var(key.as_ref()) -} - -fn _var(key: &OsStr) -> Result { - match var_os(key) { - Some(s) => s.into_string().map_err(VarError::NotUnicode), - None => Err(VarError::NotPresent), + fn inner(key: &OsStr) -> Result { + env_imp::getenv(key) + .ok_or(VarError::NotPresent)? + .into_string() + .map_err(VarError::NotUnicode) } + inner(key.as_ref()) } /// Fetches the environment variable `key` from the current process, returning @@ -257,11 +256,7 @@ fn _var(key: &OsStr) -> Result { #[must_use] #[stable(feature = "env", since = "1.0.0")] pub fn var_os>(key: K) -> Option { - _var_os(key.as_ref()) -} - -fn _var_os(key: &OsStr) -> Option { - env_imp::getenv(key) + env_imp::getenv(key.as_ref()) } /// The error type for operations interacting with environment variables. @@ -303,12 +298,12 @@ impl Error for VarError {} /// /// # Safety /// -/// This function is safe to call in a single-threaded program. +/// This function is sound to call in a single-threaded program. /// -/// This function is also always safe to call on Windows, in single-threaded +/// This function is also always sound to call on Windows, in single-threaded /// and multi-threaded programs. /// -/// In multi-threaded programs on other operating systems, the only safe option is +/// In multi-threaded programs on other operating systems, the only sound option is /// to not use `set_var` or `remove_var` at all. /// /// The exact requirement is: you @@ -322,7 +317,7 @@ impl Error for VarError {} /// lookups from [`std::net::ToSocketAddrs`]. No stable guarantee is made about /// which functions may read from the environment in future versions of a /// library. All this makes it not practically possible for you to guarantee -/// that no other thread will read the environment, so the only safe option is +/// that no other thread will read the environment, so the only sound option is /// to not use `set_var` or `remove_var` in multi-threaded programs at all. /// /// Discussion of this unsafety on Unix may be found in: @@ -366,12 +361,12 @@ pub unsafe fn set_var, V: AsRef>(key: K, value: V) { /// /// # Safety /// -/// This function is safe to call in a single-threaded program. +/// This function is sound to call in a single-threaded program. /// -/// This function is also always safe to call on Windows, in single-threaded +/// This function is also always sound to call on Windows, in single-threaded /// and multi-threaded programs. /// -/// In multi-threaded programs on other operating systems, the only safe option is +/// In multi-threaded programs on other operating systems, the only sound option is /// to not use `set_var` or `remove_var` at all. /// /// The exact requirement is: you @@ -385,7 +380,7 @@ pub unsafe fn set_var, V: AsRef>(key: K, value: V) { /// lookups from [`std::net::ToSocketAddrs`]. No stable guarantee is made about /// which functions may read from the environment in future versions of a /// library. All this makes it not practically possible for you to guarantee -/// that no other thread will read the environment, so the only safe option is +/// that no other thread will read the environment, so the only sound option is /// to not use `set_var` or `remove_var` in multi-threaded programs at all. /// /// Discussion of this unsafety on Unix may be found in: @@ -640,6 +635,7 @@ impl Error for JoinPathsError { /// ``` #[must_use] #[stable(feature = "env", since = "1.0.0")] +#[doc(alias = "home")] pub fn home_dir() -> Option { paths_imp::home_dir() } @@ -689,7 +685,7 @@ pub fn home_dir() -> Option { /// [GetTempPath]: https://docs.microsoft.com/en-us/windows/win32/api/fileapi/nf-fileapi-gettemppatha /// [appledoc]: https://developer.apple.com/library/archive/documentation/Security/Conceptual/SecureCodingGuide/Articles/RaceConditions.html#//apple_ref/doc/uid/TP40002585-SW10 /// -/// ```no_run +/// ``` /// use std::env; /// /// fn main() { @@ -1071,41 +1067,42 @@ pub mod consts { /// ///

Full list of possible values /// - /// * `"linux"` - /// * `"windows"` - /// * `"macos"` - /// * `"android"` - /// * `"ios"` - /// * `"openbsd"` - /// * `"freebsd"` - /// * `"netbsd"` - /// * `"wasi"` - /// * `"hermit"` + // tidy-alphabetical-start /// * `"aix"` + /// * `"android"` /// * `"apple"` /// * `"dragonfly"` /// * `"emscripten"` /// * `"espidf"` /// * `"fortanix"` - /// * `"uefi"` + /// * `"freebsd"` /// * `"fuchsia"` /// * `"haiku"` /// * `"hermit"` - /// * `"watchos"` - /// * `"visionos"` - /// * `"tvos"` /// * `"horizon"` /// * `"hurd"` /// * `"illumos"` + /// * `"ios"` /// * `"l4re"` + /// * `"linux"` + /// * `"macos"` + /// * `"netbsd"` /// * `"nto"` + /// * `"openbsd"` /// * `"redox"` /// * `"solaris"` /// * `"solid_asp3"` + /// * `"tvos"` + /// * `"uefi"` /// * `"vexos"` + /// * `"visionos"` /// * `"vita"` /// * `"vxworks"` + /// * `"wasi"` + /// * `"watchos"` + /// * `"windows"` /// * `"xous"` + // tidy-alphabetical-end /// ///
#[stable(feature = "env", since = "1.0.0")] diff --git a/std/src/ffi/os_str.rs b/std/src/ffi/os_str.rs index f0cebb05c76a5..4e74479faa2cc 100644 --- a/std/src/ffi/os_str.rs +++ b/std/src/ffi/os_str.rs @@ -1055,6 +1055,61 @@ impl OsStr { OsString { inner: Buf::from_box(boxed) } } + /// Divides one string slice into two at an index. + /// + /// The two slices returned go from the start of the string slice to `mid`, and from `mid` to the end of the string slice. + /// + /// The argument, `mid`, should be a byte offset from the start of the string. + /// It must also be on a valid `OsStr` boundary. + /// See [`split_at_checked`][Self::split_at_checked] for the definition of a valid boundary. + /// + /// Panics + /// + /// Panics if `mid` is not on a valid boundary, or if it is past the end of the last code point of the string slice. + /// For a non-panicking alternative see [`split_at_checked`][Self::split_at_checked]. + #[unstable(feature = "os_str_split_at", issue = "none")] + pub fn split_at(&self, mid: usize) -> (&OsStr, &OsStr) { + self.inner.check_public_boundary(mid); + + // SAFETY: we've checked it's in bounds and a valid boundary + unsafe { self.split_at_unchecked(mid) } + } + + /// Divides one string slice into two at an index. + /// + /// The two slices returned go from the start of the string slice to `mid`, and from `mid` to the end of the string slice. + /// + /// The argument, `mid`, should be a valid byte offset from the start of the string. + /// It must also be on a valid `OsStr` boundary. + /// The method returns `None` if that’s not the case. + /// A valid `OsStr` boundary is one of: + /// - The start of the string + /// - The end of the string + /// - The start of a valid non-empty UTF-8 substring + /// - Immediately follows a valid non-empty UTF-8 substring + #[unstable(feature = "os_str_split_at", issue = "none")] + pub fn split_at_checked(&self, mid: usize) -> Option<(&OsStr, &OsStr)> { + self.inner.try_check_public_boundary(mid)?; + + // SAFETY: we've checked it's in bounds and a valid boundary + unsafe { Some(self.split_at_unchecked(mid)) } + } + + /// Splits an `OsStr` without checking if `mid` is a valid boundary. + /// You should use `split_at` or `split_at_checked` instead. + /// + /// # Safety + /// + /// Any caller must ensure `mid` is within bounds and lies on + /// a valid `OsStr` boundary for the platform. + unsafe fn split_at_unchecked(&self, mid: usize) -> (&OsStr, &OsStr) { + // SAFETY: it's up to the caller to ensure this is safe. + unsafe { + let (first, second) = self.as_encoded_bytes().split_at_unchecked(mid); + (Self::from_encoded_bytes_unchecked(first), Self::from_encoded_bytes_unchecked(second)) + } + } + /// Converts an OS string slice to a byte slice. To convert the byte slice back into an OS /// string slice, use the [`OsStr::from_encoded_bytes_unchecked`] function. /// @@ -1703,7 +1758,7 @@ impl ToOwned for OsStr { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for OsStr { +const impl AsRef for OsStr { #[inline] fn as_ref(&self) -> &OsStr { self diff --git a/std/src/ffi/os_str/tests.rs b/std/src/ffi/os_str/tests.rs index 3474f0ab50684..1075c43e0b3bf 100644 --- a/std/src/ffi/os_str/tests.rs +++ b/std/src/ffi/os_str/tests.rs @@ -289,6 +289,108 @@ fn slice_surrogate_edge() { assert_eq!(post_crab.slice_encoded_bytes(4..), surrogate); } +#[test] +fn os_str_slice_at() { + #[track_caller] + fn slice_at_ok(input: &OsStr, index: usize, expected: (&str, &str)) { + let expected = (OsStr::new(expected.0), OsStr::new(expected.1)); + assert_eq!(input.split_at(index), expected); + assert_eq!(input.split_at_checked(index), Some(expected)); + } + + let os_str = OsStr::new("123გ🦀4"); + slice_at_ok(os_str, 0, ("", "123გ🦀4")); + slice_at_ok(os_str, 1, ("1", "23გ🦀4")); + slice_at_ok(os_str, 2, ("12", "3გ🦀4")); + slice_at_ok(os_str, 3, ("123", "გ🦀4")); + slice_at_ok(os_str, 6, ("123გ", "🦀4")); + slice_at_ok(os_str, 10, ("123გ🦀", "4")); + slice_at_ok(os_str, 11, ("123გ🦀4", "")); + + // Invalid boundaries should fail. + assert!(os_str.split_at_checked(4).is_none()); + assert!(os_str.split_at_checked(5).is_none()); + assert!(os_str.split_at_checked(7).is_none()); + assert!(os_str.split_at_checked(8).is_none()); + assert!(os_str.split_at_checked(9).is_none()); + // Out of bounds + assert!(os_str.split_at_checked(12).is_none()); +} + +#[test] +#[should_panic] +fn os_str_slice_at_out_of_bounds() { + let crab = OsStr::new("🦀"); + let _ = crab.split_at(5); +} + +#[test] +#[should_panic] +fn os_str_slice_at_mid_char() { + let crab = OsStr::new("🦀"); + let _ = crab.split_at(2); +} + +#[cfg(unix)] +#[test] +fn os_str_slice_at_unix() { + use crate::os::unix::ffi::OsStrExt; + + let broken_utf8 = OsStr::from_bytes(&"🦀".as_bytes()[..3]); + let invalid = OsStr::from_bytes(b"\xFF"); + + // Check that broken UTF-8 isn't treated as if it's valid. + let mut os_string = invalid.to_os_string(); + os_string.push(broken_utf8); + assert_eq!(os_string.split_at_checked(1), None); + + // We should be able to split on ascii with invalid UTF-8 between + let os_string = OsStr::from_bytes(b"a\xFFa"); + assert_eq!(os_string.split_at_checked(1), Some(("a".as_ref(), OsStr::from_bytes(b"\xFFa")))); + assert_eq!(os_string.split_at_checked(2), Some((OsStr::from_bytes(b"a\xFF"), "a".as_ref(),))); + + let os_string = OsStr::from_bytes(&"abc🦀".as_bytes()[..6]); + assert_eq!( + os_string.split_at_checked(3), + Some(("abc".as_ref(), OsStr::from_bytes(b"\xF0\x9F\xA6"))) + ); + + let mut os_string = invalid.to_os_string(); + os_string.push("🦀"); + assert_eq!(os_string.split_at_checked(1), Some((invalid, "🦀".as_ref()))); +} + +#[test] +#[cfg(windows)] +fn os_str_slice_at_windows() { + use crate::os::windows::ffi::OsStringExt; + + // slicing between unpaired surrogates should not be possible + // checking is implemented as a loop so we're agnostic towards + // the internal encoding + let os_string = OsString::from_wide(&[0xD800, 0xD800]); + for i in 1..os_string.len() { + assert_eq!(os_string.split_at_checked(i), None); + } + // For completeness, check that splitting at the start and end still works. + assert!(os_string.split_at_checked(0).is_some()); + assert!(os_string.split_at_checked(os_string.len()).is_some()); + + // check that slicing before and after unpaired surrogates work + let surrogate = OsString::from_wide(&[0xD800]); + + let mut os_string = surrogate.clone(); + os_string.push("🦀"); + assert_eq!( + os_string.split_at_checked(surrogate.len()), + Some((surrogate.as_ref(), "🦀".as_ref())) + ); + + let mut os_string = OsString::from("🦀"); + os_string.push(&surrogate); + assert_eq!(os_string.split_at_checked("🦀".len()), Some(("🦀".as_ref(), surrogate.as_ref()))); +} + #[test] fn clone_to_uninit() { let a = OsStr::new("hello.txt"); diff --git a/std/src/fs.rs b/std/src/fs.rs index 9643d3fcae662..3f0db7a6b7435 100644 --- a/std/src/fs.rs +++ b/std/src/fs.rs @@ -45,7 +45,6 @@ use crate::ffi::OsString; use crate::io::{self, BorrowedCursor, IoSlice, IoSliceMut, Read, Seek, SeekFrom, Write}; use crate::path::{Path, PathBuf}; use crate::sealed::Sealed; -use crate::sync::Arc; use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner, fs as fs_imp}; use crate::time::SystemTime; use crate::{error, fmt}; @@ -132,6 +131,7 @@ use crate::{error, fmt}; /// [`read`]: File::read #[stable(feature = "rust1", since = "1.0.0")] #[cfg_attr(not(test), rustc_diagnostic_item = "File")] +#[diagnostic::on_move(note = "you can use `File::try_clone` to duplicate a `File` instance")] pub struct File { inner: fs_imp::File, } @@ -815,18 +815,17 @@ impl File { /// Acquire an exclusive lock on the file. Blocks until the lock can be acquired. /// - /// This acquires an exclusive lock; no other file handle to this file, in this or any other + /// This acquires an exclusive lock. No *other* file handle to this file, in this or any other /// process, may acquire another lock. + /// If this file handle/descriptor, or a clone of it, already holds a lock, the exact behavior + /// is unspecified and platform dependent, including the possibility that it will deadlock. + /// However, if this method returns, then an exclusive lock is held. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with /// other methods, such as [`read`] and [`write`] are platform specific, and it may or may not /// cause non-lockholders to block. /// - /// If this file handle/descriptor, or a clone of it, already holds a lock the exact behavior - /// is unspecified and platform dependent, including the possibility that it will deadlock. - /// However, if this method returns, then an exclusive lock is held. - /// /// If the file is not open for writing, it is unspecified whether this function returns an error. /// /// The lock will be released when this file (along with any other file descriptors/handles @@ -869,18 +868,18 @@ impl File { /// Acquire a shared (non-exclusive) lock on the file. Blocks until the lock can be acquired. /// - /// This acquires a shared lock; more than one file handle, in this or any other process, may - /// hold a shared lock, but none may hold an exclusive lock at the same time. + /// This acquires a shared lock. More than one file handle to this file, in this or any other + /// process, may hold a shared lock, but no *other* file handle may hold an exclusive lock at + /// the same time. + /// If this file handle/descriptor, or a clone of it, already holds a lock, the exact + /// behavior is unspecified and platform dependent, including the possibility that it will + /// deadlock. However, if this method returns, then a shared lock is held. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with /// other methods, such as [`read`] and [`write`] are platform specific, and it may or may not /// cause non-lockholders to block. /// - /// If this file handle/descriptor, or a clone of it, already holds a lock, the exact behavior - /// is unspecified and platform dependent, including the possibility that it will deadlock. - /// However, if this method returns, then a shared lock is held. - /// /// The lock will be released when this file (along with any other file descriptors/handles /// duplicated or inherited from it) is closed, or if the [`unlock`] method is called. /// @@ -1265,6 +1264,7 @@ impl File { #[doc(alias = "futimens")] #[doc(alias = "futimes")] #[doc(alias = "SetFileTime")] + #[doc(alias = "filetime")] pub fn set_times(&self, times: FileTimes) -> io::Result<()> { self.inner.set_times(times.0) } @@ -1541,58 +1541,7 @@ impl Seek for File { (&*self).stream_position() } } - -#[stable(feature = "io_traits_arc", since = "1.73.0")] -impl Read for Arc { - fn read(&mut self, buf: &mut [u8]) -> io::Result { - (&**self).read(buf) - } - fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { - (&**self).read_vectored(bufs) - } - fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { - (&**self).read_buf(cursor) - } - #[inline] - fn is_read_vectored(&self) -> bool { - (&**self).is_read_vectored() - } - fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { - (&**self).read_to_end(buf) - } - fn read_to_string(&mut self, buf: &mut String) -> io::Result { - (&**self).read_to_string(buf) - } -} -#[stable(feature = "io_traits_arc", since = "1.73.0")] -impl Write for Arc { - fn write(&mut self, buf: &[u8]) -> io::Result { - (&**self).write(buf) - } - fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - (&**self).write_vectored(bufs) - } - #[inline] - fn is_write_vectored(&self) -> bool { - (&**self).is_write_vectored() - } - #[inline] - fn flush(&mut self) -> io::Result<()> { - (&**self).flush() - } -} -#[stable(feature = "io_traits_arc", since = "1.73.0")] -impl Seek for Arc { - fn seek(&mut self, pos: SeekFrom) -> io::Result { - (&**self).seek(pos) - } - fn stream_len(&mut self) -> io::Result { - (&**self).stream_len() - } - fn stream_position(&mut self) -> io::Result { - (&**self).stream_position() - } -} +impl crate::io::IoHandle for File {} impl Dir { /// Attempts to open a directory at `path` in read-only mode. @@ -1649,6 +1598,25 @@ impl Dir { .open_file(path.as_ref(), &OpenOptions::new().read(true).0) .map(|f| File { inner: f }) } + + /// Queries metadata about the underlying directory. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(dirfd)] + /// use std::fs::Dir; + /// + /// fn main() -> std::io::Result<()> { + /// let dir = Dir::open("foo")?; + /// let metadata = dir.metadata()?; + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "dirfd", issue = "120426")] + pub fn metadata(&self) -> io::Result { + self.inner.metadata().map(Metadata) + } } impl AsInner for Dir { @@ -2198,6 +2166,12 @@ impl fmt::Debug for Metadata { } } +impl IntoInner for Metadata { + fn into_inner(self) -> fs_imp::FileAttr { + self.0 + } +} + impl AsInner for Metadata { #[inline] fn as_inner(&self) -> &fs_imp::FileAttr { @@ -2841,8 +2815,9 @@ pub fn rename, Q: AsRef>(from: P, to: Q) -> io::Result<()> /// with `O_RDONLY` for `from` and `O_WRONLY`, `O_CREAT`, and `O_TRUNC` for `to`. /// `O_CLOEXEC` is set for returned file descriptors. /// -/// On Linux (including Android), this function attempts to use `copy_file_range(2)`, -/// and falls back to reading and writing if that is not possible. +/// On Linux (including Android), this function uses copy_file_range(2), +/// sendfile(2), or splice(2) syscalls to move data directly between files +/// if possible. /// /// On Windows, this function currently corresponds to `CopyFileEx`. Alternate /// NTFS streams are copied but only the size of the main stream is returned by @@ -2896,7 +2871,7 @@ pub fn copy, Q: AsRef>(from: P, to: Q) -> io::Result { /// /// # Platform-specific behavior /// -/// This function currently corresponds the `CreateHardLink` function on Windows. +/// This function currently corresponds to the `CreateHardLink` function on Windows. /// On most Unix systems, it corresponds to the `linkat` function with no flags. /// On Android, VxWorks, and Redox, it instead corresponds to the `link` function. /// On MacOS, it uses the `linkat` function if it is available, but on very old @@ -3195,8 +3170,8 @@ pub fn remove_dir>(path: P) -> io::Result<()> { /// not be used in security-sensitive contexts: /// - **Miri**: Even when emulating targets where the underlying implementation will protect against /// TOCTOU races, Miri will not do so. -/// - **Redox OS**: This function does not protect against TOCTOU races, as Redox does not implement -/// the required platform support to do so. +/// - **QNX**, **Redox OS**, **VxWorks**: This function does not protect against TOCTOU races, as +/// the underlying platform does not implement the required platform support to do so. /// /// [TOCTOU]: self#time-of-check-to-time-of-use-toctou /// [changes]: io#platform-specific-behavior diff --git a/std/src/fs/tests.rs b/std/src/fs/tests.rs index 42f3ccc340b27..bd198b726c6ad 100644 --- a/std/src/fs/tests.rs +++ b/std/src/fs/tests.rs @@ -1,10 +1,7 @@ use rand::RngCore; -#[cfg(not(miri))] use super::Dir; use crate::fs::{self, File, FileTimes, OpenOptions, TryLockError}; -#[cfg(not(miri))] -use crate::io; use crate::io::prelude::*; use crate::io::{BorrowedBuf, ErrorKind, SeekFrom}; use crate::mem::MaybeUninit; @@ -20,7 +17,7 @@ use crate::path::Path; use crate::sync::Arc; use crate::test_helpers::{TempDir, tmpdir}; use crate::time::{Duration, Instant, SystemTime}; -use crate::{assert_matches, env, str, thread}; +use crate::{assert_matches, env, io, str, thread}; macro_rules! check { ($e:expr) => { @@ -31,25 +28,6 @@ macro_rules! check { }; } -#[cfg(windows)] -macro_rules! error { - ($e:expr, $s:expr) => { - match $e { - Ok(_) => panic!("Unexpected success. Should've been: {:?}", $s), - Err(ref err) => { - assert!(err.raw_os_error() == Some($s), "`{}` did not have a code of `{}`", err, $s) - } - } - }; -} - -#[cfg(unix)] -macro_rules! error { - ($e:expr, $s:expr) => { - error_contains!($e, $s) - }; -} - macro_rules! error_contains { ($e:expr, $s:expr) => { match $e { @@ -105,14 +83,8 @@ fn file_test_io_smoke_test() { fn invalid_path_raises() { let tmpdir = tmpdir(); let filename = &tmpdir.join("file_that_does_not_exist.txt"); - let result = File::open(filename); - - #[cfg(all(unix, not(target_os = "vxworks")))] - error!(result, "No such file or directory"); - #[cfg(target_os = "vxworks")] - error!(result, "no such file or directory"); - #[cfg(windows)] - error!(result, 2); // ERROR_FILE_NOT_FOUND + let err = File::open(filename).unwrap_err(); + assert_eq!(err.kind(), ErrorKind::NotFound); } #[test] @@ -120,14 +92,8 @@ fn file_test_iounlinking_invalid_path_should_raise_condition() { let tmpdir = tmpdir(); let filename = &tmpdir.join("file_another_file_that_does_not_exist.txt"); - let result = fs::remove_file(filename); - - #[cfg(all(unix, not(target_os = "vxworks")))] - error!(result, "No such file or directory"); - #[cfg(target_os = "vxworks")] - error!(result, "no such file or directory"); - #[cfg(windows)] - error!(result, 2); // ERROR_FILE_NOT_FOUND + let err = fs::remove_file(filename).unwrap_err(); + assert_eq!(err.kind(), ErrorKind::NotFound); } #[test] @@ -221,6 +187,7 @@ fn file_test_io_seek_and_write() { target_os = "netbsd", target_os = "openbsd", target_os = "solaris", + target_os = "android", target_vendor = "apple", )), should_panic @@ -254,6 +221,7 @@ fn file_lock_multiple_shared() { target_os = "netbsd", target_os = "openbsd", target_os = "solaris", + target_os = "android", target_vendor = "apple", )), should_panic @@ -288,6 +256,7 @@ fn file_lock_blocking() { target_os = "netbsd", target_os = "openbsd", target_os = "solaris", + target_os = "android", target_vendor = "apple", )), should_panic @@ -319,6 +288,7 @@ fn file_lock_drop() { target_os = "netbsd", target_os = "openbsd", target_os = "solaris", + target_os = "android", target_vendor = "apple", )), should_panic @@ -339,18 +309,43 @@ fn file_lock_dup() { } #[test] -#[cfg(windows)] -fn file_lock_double_unlock() { +#[cfg_attr( + not(any( + windows, + target_os = "aix", + target_os = "cygwin", + target_os = "freebsd", + target_os = "fuchsia", + target_os = "hurd", + target_os = "illumos", + target_os = "linux", + target_os = "netbsd", + target_os = "openbsd", + target_os = "solaris", + target_os = "android", + target_vendor = "apple", + )), + should_panic +)] +fn file_lock_double() { let tmpdir = tmpdir(); - let filename = &tmpdir.join("file_lock_double_unlock_test.txt"); + let filename = &tmpdir.join("file_lock_double_test.txt"); let f1 = check!(File::create(filename)); let f2 = check!(OpenOptions::new().write(true).open(filename)); - // On Windows a file handle may acquire both a shared and exclusive lock. - // Check that both are released by unlock() + // A file handle may acquire both a shared and exclusive lock. check!(f1.lock()); check!(f1.lock_shared()); + // The behavior here differs between Windows and Unix: on Windows, f1 holds both locks; + // on Unix, the lock got downgraded so f1 only holds the shared lock. assert_matches!(f2.try_lock(), Err(TryLockError::WouldBlock)); + if cfg!(windows) { + assert_matches!(f2.try_lock_shared(), Err(TryLockError::WouldBlock)); + } else { + check!(f2.try_lock_shared()); + check!(f2.unlock()); + } + // Check that both are released by unlock(). check!(f1.unlock()); check!(f2.try_lock()); } @@ -717,7 +712,7 @@ fn file_test_read_buf() { check!(file.read_buf(buf.unfilled())); assert_eq!(buf.filled(), &[1, 2, 3, 4]); // File::read_buf should omit buffer initialization. - assert_eq!(buf.init_len(), 4); + assert!(!buf.is_init()); check!(fs::remove_file(filename)); } @@ -856,10 +851,12 @@ fn recursive_mkdir_failure() { #[test] fn concurrent_recursive_mkdir() { - for _ in 0..100 { + let count = if cfg!(miri) { 10 } else { 100 }; + let nest = if cfg!(miri) { 10 } else { 40 }; + for _ in 0..count { let dir = tmpdir(); let mut dir = dir.join("a"); - for _ in 0..40 { + for _ in 0..nest { dir = dir.join("a"); } let mut join = vec![]; @@ -939,12 +936,8 @@ fn recursive_rmdir_of_file_fails() { let tmpdir = tmpdir(); let canary = tmpdir.join("do_not_delete"); check!(check!(File::create(&canary)).write(b"foo")); - let result = fs::remove_dir_all(&canary); - #[cfg(unix)] - error!(result, "Not a directory"); - #[cfg(windows)] - error!(result, 267); // ERROR_DIRECTORY - The directory name is invalid. - assert!(result.is_err()); + let err = fs::remove_dir_all(&canary).unwrap_err(); + assert_eq!(err.kind(), ErrorKind::NotADirectory); assert!(canary.exists()); } @@ -1404,6 +1397,7 @@ fn open_flavors() { let mut ra = OO::new(); ra.read(true).append(true); + // This error string is set by std itself so we are not at the whim of the OS here. let invalid_options = "creating or truncating a file requires write or append access"; // Test various combinations of creation modes and access modes. @@ -1731,6 +1725,8 @@ fn create_dir_all_with_junctions() { #[test] fn metadata_access_times() { + let start_time = SystemTime::now(); + let tmpdir = tmpdir(); let b = tmpdir.join("b"); @@ -1751,7 +1747,14 @@ fn metadata_access_times() { if cfg!(target_os = "linux") { // Not always available match (a.created(), b.created()) { - (Ok(t1), Ok(t2)) => assert!(t1 <= t2), + // It could be that, when the system clock goes backwards (e.g., due time change) + // b, that gets created after a, has a greater creation date than a. + // When such rare case occurs we skip the test, since the test to check that b + // should be created after a would fail. + (Ok(t1), Ok(t2)) => match start_time.elapsed() { + Ok(_) => assert!(t1 <= t2), + Err(_) => {} + }, (Err(e1), Err(e2)) if e1.kind() == ErrorKind::Uncategorized && e2.kind() == ErrorKind::Uncategorized @@ -1860,7 +1863,7 @@ fn create_dir_long_paths() { fn read_large_dir() { let tmpdir = tmpdir(); - let count = 32 * 1024; + let count = if cfg!(miri) { 1024 } else { 32 * 1024 }; for i in 0..count { check!(fs::File::create(tmpdir.join(&i.to_string()))); } @@ -1945,6 +1948,7 @@ fn test_eq_windows_file_type() { /// Regression test for https://github.com/rust-lang/rust/issues/50619. #[test] #[cfg(target_os = "linux")] +#[cfg_attr(miri, ignore)] // Cannot spawn processes on Miri fn test_read_dir_infinite_loop() { use crate::io::ErrorKind; use crate::process::Command; @@ -2139,7 +2143,6 @@ fn test_hidden_file_truncation() { // See https://github.com/rust-lang/rust/pull/131072 for more details about why // these two tests are disabled under Windows 7 here. -#[cfg(windows)] #[test] #[cfg_attr(target_vendor = "win7", ignore = "Unsupported under Windows 7.")] fn test_rename_file_over_open_file() { @@ -2165,10 +2168,9 @@ fn test_rename_file_over_open_file() { } #[test] -#[cfg(windows)] #[cfg_attr(target_vendor = "win7", ignore = "Unsupported under Windows 7.")] fn test_rename_directory_to_non_empty_directory() { - // Renaming a directory over a non-empty existing directory should fail on Windows. + // Renaming a directory over a non-empty existing directory should fail. let tmpdir: TempDir = tmpdir(); let source_path = tmpdir.join("source_directory"); @@ -2179,7 +2181,8 @@ fn test_rename_directory_to_non_empty_directory() { fs::write(target_path.join("target_file.txt"), b"target hello world").unwrap(); - error!(fs::rename(source_path, target_path), 145); // ERROR_DIR_NOT_EMPTY + let err = fs::rename(source_path, target_path).unwrap_err(); + assert_eq!(err.kind(), ErrorKind::DirectoryNotEmpty); } #[test] @@ -2521,8 +2524,6 @@ fn test_fs_set_times_nofollow() { } #[test] -// FIXME: libc calls fail on miri -#[cfg(not(miri))] fn test_dir_smoke_test() { let tmpdir = tmpdir(); let dir = Dir::open(tmpdir.path()); @@ -2530,8 +2531,6 @@ fn test_dir_smoke_test() { } #[test] -// FIXME: libc calls fail on miri -#[cfg(not(miri))] fn test_dir_read_file() { let tmpdir = tmpdir(); let mut f = check!(File::create(tmpdir.join("foo.txt"))); @@ -2546,3 +2545,11 @@ fn test_dir_read_file() { let buf = check!(io::read_to_string(f)); assert_eq!("bar", &buf); } + +#[test] +fn test_dir_metadata() { + let tmpdir = tmpdir(); + let dir = check!(Dir::open(tmpdir.path())); + let metadata = check!(dir.metadata()); + assert!(metadata.is_dir()); +} diff --git a/std/src/hash/random.rs b/std/src/hash/random.rs index 3c1b21eec9759..b9c21ab2d6a65 100644 --- a/std/src/hash/random.rs +++ b/std/src/hash/random.rs @@ -110,7 +110,7 @@ impl DefaultHasher { #[stable(feature = "hashmap_default_hasher", since = "1.13.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for DefaultHasher { +const impl Default for DefaultHasher { /// Creates a new `DefaultHasher` using [`new`]. /// See its documentation for more. /// diff --git a/std/src/io/buffered/bufreader.rs b/std/src/io/buffered/bufreader.rs index 40441dc057d0d..36bf329a946e0 100644 --- a/std/src/io/buffered/bufreader.rs +++ b/std/src/io/buffered/bufreader.rs @@ -48,6 +48,7 @@ use crate::io::{ /// } /// ``` #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoBufReader")] pub struct BufReader { buf: Buffer, inner: R, @@ -288,7 +289,7 @@ impl BufReader { #[cfg(test)] impl BufReader { #[allow(missing_docs)] - pub fn initialized(&self) -> usize { + pub fn initialized(&self) -> bool { self.buf.initialized() } } diff --git a/std/src/io/buffered/bufreader/buffer.rs b/std/src/io/buffered/bufreader/buffer.rs index ad8608bf61908..f2efcc5ab8601 100644 --- a/std/src/io/buffered/bufreader/buffer.rs +++ b/std/src/io/buffered/bufreader/buffer.rs @@ -21,25 +21,24 @@ pub struct Buffer { // Each call to `fill_buf` sets `filled` to indicate how many bytes at the start of `buf` are // initialized with bytes from a read. filled: usize, - // This is the max number of bytes returned across all `fill_buf` calls. We track this so that we - // can accurately tell `read_buf` how many bytes of buf are initialized, to bypass as much of its - // defensive initialization as possible. Note that while this often the same as `filled`, it - // doesn't need to be. Calls to `fill_buf` are not required to actually fill the buffer, and - // omitting this is a huge perf regression for `Read` impls that do not. - initialized: usize, + // Whether `buf` has been fully initialized. We track this so that we can accurately tell + // `read_buf` how many bytes of buf are initialized, to bypass as much of its defensive + // initialization as possible. Calls to `fill_buf` are not required to actually fill the buffer, + // and omitting this is a huge perf regression for `Read` impls that do not. + initialized: bool, } impl Buffer { #[inline] pub fn with_capacity(capacity: usize) -> Self { let buf = Box::new_uninit_slice(capacity); - Self { buf, pos: 0, filled: 0, initialized: 0 } + Self { buf, pos: 0, filled: 0, initialized: false } } #[inline] pub fn try_with_capacity(capacity: usize) -> io::Result { match Box::try_new_uninit_slice(capacity) { - Ok(buf) => Ok(Self { buf, pos: 0, filled: 0, initialized: 0 }), + Ok(buf) => Ok(Self { buf, pos: 0, filled: 0, initialized: false }), Err(_) => { Err(io::const_error!(ErrorKind::OutOfMemory, "failed to allocate read buffer")) } @@ -70,7 +69,7 @@ impl Buffer { // This is only used by a test which asserts that the initialization-tracking is correct. #[cfg(test)] - pub fn initialized(&self) -> usize { + pub fn initialized(&self) -> bool { self.initialized } @@ -110,13 +109,17 @@ impl Buffer { /// Read more bytes into the buffer without discarding any of its contents pub fn read_more(&mut self, mut reader: impl Read) -> io::Result { let mut buf = BorrowedBuf::from(&mut self.buf[self.filled..]); - let old_init = self.initialized - self.filled; - unsafe { - buf.set_init(old_init); + + if self.initialized { + // SAFETY: `self.initialized` is only set after `self.buf` was + // fully initialized, and once `self.buf` is fully initialized + // no part will become uninitialized. + unsafe { buf.set_init() }; } + reader.read_buf(buf.unfilled())?; self.filled += buf.len(); - self.initialized += buf.init_len() - old_init; + self.initialized = buf.is_init(); Ok(buf.len()) } @@ -137,16 +140,19 @@ impl Buffer { debug_assert!(self.pos == self.filled); let mut buf = BorrowedBuf::from(&mut *self.buf); - // SAFETY: `self.filled` bytes will always have been initialized. - unsafe { - buf.set_init(self.initialized); + + if self.initialized { + // SAFETY: `self.initialized` is only set after `self.buf` was + // fully initialized, and once `self.buf` is fully initialized + // no part will become uninitialized. + unsafe { buf.set_init() }; } let result = reader.read_buf(buf.unfilled()); self.pos = 0; self.filled = buf.len(); - self.initialized = buf.init_len(); + self.initialized = buf.is_init(); result?; } diff --git a/std/src/io/buffered/bufwriter.rs b/std/src/io/buffered/bufwriter.rs index d569fed24c561..1a5cc911c0e43 100644 --- a/std/src/io/buffered/bufwriter.rs +++ b/std/src/io/buffered/bufwriter.rs @@ -193,6 +193,10 @@ impl BufWriter { /// `write`), any 0-length writes from `inner` must be reported as i/o /// errors from this method. pub(in crate::io) fn flush_buf(&mut self) -> io::Result<()> { + // SAFETY: `::copy_from` assumes that + // this will not de-initialize any elements of `self.buf`'s spare + // capacity. + /// Helper struct to ensure the buffer is updated after all the writes /// are complete. It tracks the number of written bytes and drains them /// all from the front of the buffer when dropped. @@ -225,7 +229,16 @@ impl BufWriter { impl Drop for BufGuard<'_> { fn drop(&mut self) { if self.written > 0 { - self.buffer.drain(..self.written); + // Like `self.buffer.drain(..self.written)` but more obviously + // preserving the spare capacity; see note above. + let new_len = self.buffer.len() - self.written; + // SAFETY: Assumes `Vec::as_mut_slice` will not + // de-initialize any elements of `self.buf`'s spare capacity, + // and that `<&mut [u8]>::copy_within` will not do so either. + self.buffer.as_mut_slice().copy_within(self.written.., 0); + // SAFETY: Assumes `Vec::truncate` will not de-initialize + // any elements of `self.buf`'s spare capacity, + self.buffer.truncate(new_len); } } } @@ -641,7 +654,8 @@ impl Write for BufWriter { } fn flush(&mut self) -> io::Result<()> { - self.flush_buf().and_then(|()| self.get_mut().flush()) + self.flush_buf()?; + self.get_mut().flush() } } diff --git a/std/src/io/buffered/tests.rs b/std/src/io/buffered/tests.rs index e335d8afdc483..742e753f9b951 100644 --- a/std/src/io/buffered/tests.rs +++ b/std/src/io/buffered/tests.rs @@ -1067,13 +1067,13 @@ fn bufreader_full_initialize() { } let mut reader = BufReader::new(OneByteReader); // Nothing is initialized yet. - assert_eq!(reader.initialized(), 0); + assert!(!reader.initialized()); let buf = reader.fill_buf().unwrap(); // We read one byte... assert_eq!(buf.len(), 1); // But we initialized the whole buffer! - assert_eq!(reader.initialized(), reader.capacity()); + assert!(reader.initialized()); } /// This is a regression test for https://github.com/rust-lang/rust/issues/127584. diff --git a/std/src/io/copy.rs b/std/src/io/copy.rs index 2b558efb8885e..0feadf2b3f8bb 100644 --- a/std/src/io/copy.rs +++ b/std/src/io/copy.rs @@ -214,15 +214,16 @@ impl BufferedWriterSpec for BufWriter { } let mut len = 0; - let mut init = 0; + let mut init = false; loop { let buf = self.buffer_mut(); let mut read_buf: BorrowedBuf<'_> = buf.spare_capacity_mut().into(); - unsafe { - // SAFETY: init is either 0 or the init_len from the previous iteration. - read_buf.set_init(init); + if init { + // SAFETY: `init` is only true after `reader` initializes + // `read_buf`. See the comment about `flush_buf` below. + unsafe { read_buf.set_init() }; } if read_buf.capacity() >= DEFAULT_BUF_SIZE { @@ -235,7 +236,7 @@ impl BufferedWriterSpec for BufWriter { return Ok(len); } - init = read_buf.init_len() - bytes_read; + init = read_buf.is_init(); len += bytes_read as u64; // SAFETY: BorrowedBuf guarantees all of its filled bytes are init @@ -248,10 +249,8 @@ impl BufferedWriterSpec for BufWriter { Err(e) => return Err(e), } } else { - // All the bytes that were already in the buffer are initialized, - // treat them as such when the buffer is flushed. - init += buf.len(); - + // SAFETY: `flush_buf` will not de-initialize any elements of + // the spare capacity so we can remember `init` across this. self.flush_buf()?; } } diff --git a/std/src/io/cursor.rs b/std/src/io/cursor.rs index d7131e2fe92fd..9cd6d013f472c 100644 --- a/std/src/io/cursor.rs +++ b/std/src/io/cursor.rs @@ -1,290 +1,14 @@ #[cfg(test)] mod tests; +#[stable(feature = "rust1", since = "1.0.0")] +pub use core::io::Cursor; + use crate::alloc::Allocator; use crate::cmp; use crate::io::prelude::*; use crate::io::{self, BorrowedCursor, ErrorKind, IoSlice, IoSliceMut, SeekFrom}; -/// A `Cursor` wraps an in-memory buffer and provides it with a -/// [`Seek`] implementation. -/// -/// `Cursor`s are used with in-memory buffers, anything implementing -/// [AsRef]<\[u8]>, to allow them to implement [`Read`] and/or [`Write`], -/// allowing these buffers to be used anywhere you might use a reader or writer -/// that does actual I/O. -/// -/// The standard library implements some I/O traits on various types which -/// are commonly used as a buffer, like Cursor<[Vec]\> and -/// Cursor<[&\[u8\]][bytes]>. -/// -/// # Examples -/// -/// We may want to write bytes to a [`File`] in our production -/// code, but use an in-memory buffer in our tests. We can do this with -/// `Cursor`: -/// -/// [bytes]: crate::slice "slice" -/// [`File`]: crate::fs::File -/// -/// ```no_run -/// use std::io::prelude::*; -/// use std::io::{self, SeekFrom}; -/// use std::fs::File; -/// -/// // a library function we've written -/// fn write_ten_bytes_at_end(mut writer: W) -> io::Result<()> { -/// writer.seek(SeekFrom::End(-10))?; -/// -/// for i in 0..10 { -/// writer.write(&[i])?; -/// } -/// -/// // all went well -/// Ok(()) -/// } -/// -/// # fn foo() -> io::Result<()> { -/// // Here's some code that uses this library function. -/// // -/// // We might want to use a BufReader here for efficiency, but let's -/// // keep this example focused. -/// let mut file = File::create("foo.txt")?; -/// // First, we need to allocate 10 bytes to be able to write into. -/// file.set_len(10)?; -/// -/// write_ten_bytes_at_end(&mut file)?; -/// # Ok(()) -/// # } -/// -/// // now let's write a test -/// #[test] -/// fn test_writes_bytes() { -/// // setting up a real File is much slower than an in-memory buffer, -/// // let's use a cursor instead -/// use std::io::Cursor; -/// let mut buff = Cursor::new(vec![0; 15]); -/// -/// write_ten_bytes_at_end(&mut buff).unwrap(); -/// -/// assert_eq!(&buff.get_ref()[5..15], &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9]); -/// } -/// ``` -#[stable(feature = "rust1", since = "1.0.0")] -#[derive(Debug, Default, Eq, PartialEq)] -pub struct Cursor { - inner: T, - pos: u64, -} - -impl Cursor { - /// Creates a new cursor wrapping the provided underlying in-memory buffer. - /// - /// Cursor initial position is `0` even if underlying buffer (e.g., [`Vec`]) - /// is not empty. So writing to cursor starts with overwriting [`Vec`] - /// content, not with appending to it. - /// - /// # Examples - /// - /// ``` - /// use std::io::Cursor; - /// - /// let buff = Cursor::new(Vec::new()); - /// # fn force_inference(_: &Cursor>) {} - /// # force_inference(&buff); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] - pub const fn new(inner: T) -> Cursor { - Cursor { pos: 0, inner } - } - - /// Consumes this cursor, returning the underlying value. - /// - /// # Examples - /// - /// ``` - /// use std::io::Cursor; - /// - /// let buff = Cursor::new(Vec::new()); - /// # fn force_inference(_: &Cursor>) {} - /// # force_inference(&buff); - /// - /// let vec = buff.into_inner(); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - pub fn into_inner(self) -> T { - self.inner - } - - /// Gets a reference to the underlying value in this cursor. - /// - /// # Examples - /// - /// ``` - /// use std::io::Cursor; - /// - /// let buff = Cursor::new(Vec::new()); - /// # fn force_inference(_: &Cursor>) {} - /// # force_inference(&buff); - /// - /// let reference = buff.get_ref(); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] - pub const fn get_ref(&self) -> &T { - &self.inner - } - - /// Gets a mutable reference to the underlying value in this cursor. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying value as it may corrupt this cursor's position. - /// - /// # Examples - /// - /// ``` - /// use std::io::Cursor; - /// - /// let mut buff = Cursor::new(Vec::new()); - /// # fn force_inference(_: &Cursor>) {} - /// # force_inference(&buff); - /// - /// let reference = buff.get_mut(); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_const_stable(feature = "const_mut_cursor", since = "1.86.0")] - pub const fn get_mut(&mut self) -> &mut T { - &mut self.inner - } - - /// Returns the current position of this cursor. - /// - /// # Examples - /// - /// ``` - /// use std::io::Cursor; - /// use std::io::prelude::*; - /// use std::io::SeekFrom; - /// - /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]); - /// - /// assert_eq!(buff.position(), 0); - /// - /// buff.seek(SeekFrom::Current(2)).unwrap(); - /// assert_eq!(buff.position(), 2); - /// - /// buff.seek(SeekFrom::Current(-1)).unwrap(); - /// assert_eq!(buff.position(), 1); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] - pub const fn position(&self) -> u64 { - self.pos - } - - /// Sets the position of this cursor. - /// - /// # Examples - /// - /// ``` - /// use std::io::Cursor; - /// - /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]); - /// - /// assert_eq!(buff.position(), 0); - /// - /// buff.set_position(2); - /// assert_eq!(buff.position(), 2); - /// - /// buff.set_position(4); - /// assert_eq!(buff.position(), 4); - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - #[rustc_const_stable(feature = "const_mut_cursor", since = "1.86.0")] - pub const fn set_position(&mut self, pos: u64) { - self.pos = pos; - } -} - -impl Cursor -where - T: AsRef<[u8]>, -{ - /// Splits the underlying slice at the cursor position and returns them. - /// - /// # Examples - /// - /// ``` - /// #![feature(cursor_split)] - /// use std::io::Cursor; - /// - /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]); - /// - /// assert_eq!(buff.split(), ([].as_slice(), [1, 2, 3, 4, 5].as_slice())); - /// - /// buff.set_position(2); - /// assert_eq!(buff.split(), ([1, 2].as_slice(), [3, 4, 5].as_slice())); - /// - /// buff.set_position(6); - /// assert_eq!(buff.split(), ([1, 2, 3, 4, 5].as_slice(), [].as_slice())); - /// ``` - #[unstable(feature = "cursor_split", issue = "86369")] - pub fn split(&self) -> (&[u8], &[u8]) { - let slice = self.inner.as_ref(); - let pos = self.pos.min(slice.len() as u64); - slice.split_at(pos as usize) - } -} - -impl Cursor -where - T: AsMut<[u8]>, -{ - /// Splits the underlying slice at the cursor position and returns them - /// mutably. - /// - /// # Examples - /// - /// ``` - /// #![feature(cursor_split)] - /// use std::io::Cursor; - /// - /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]); - /// - /// assert_eq!(buff.split_mut(), ([].as_mut_slice(), [1, 2, 3, 4, 5].as_mut_slice())); - /// - /// buff.set_position(2); - /// assert_eq!(buff.split_mut(), ([1, 2].as_mut_slice(), [3, 4, 5].as_mut_slice())); - /// - /// buff.set_position(6); - /// assert_eq!(buff.split_mut(), ([1, 2, 3, 4, 5].as_mut_slice(), [].as_mut_slice())); - /// ``` - #[unstable(feature = "cursor_split", issue = "86369")] - pub fn split_mut(&mut self) -> (&mut [u8], &mut [u8]) { - let slice = self.inner.as_mut(); - let pos = self.pos.min(slice.len() as u64); - slice.split_at_mut(pos as usize) - } -} - -#[stable(feature = "rust1", since = "1.0.0")] -impl Clone for Cursor -where - T: Clone, -{ - #[inline] - fn clone(&self) -> Self { - Cursor { inner: self.inner.clone(), pos: self.pos } - } - - #[inline] - fn clone_from(&mut self, other: &Self) { - self.inner.clone_from(&other.inner); - self.pos = other.pos; - } -} - #[stable(feature = "rust1", since = "1.0.0")] impl io::Seek for Cursor where @@ -293,16 +17,16 @@ where fn seek(&mut self, style: SeekFrom) -> io::Result { let (base_pos, offset) = match style { SeekFrom::Start(n) => { - self.pos = n; + self.set_position(n); return Ok(n); } - SeekFrom::End(n) => (self.inner.as_ref().len() as u64, n), - SeekFrom::Current(n) => (self.pos, n), + SeekFrom::End(n) => (self.get_ref().as_ref().len() as u64, n), + SeekFrom::Current(n) => (self.position(), n), }; match base_pos.checked_add_signed(offset) { Some(n) => { - self.pos = n; - Ok(self.pos) + self.set_position(n); + Ok(n) } None => Err(io::const_error!( ErrorKind::InvalidInput, @@ -312,11 +36,11 @@ where } fn stream_len(&mut self) -> io::Result { - Ok(self.inner.as_ref().len() as u64) + Ok(self.get_ref().as_ref().len() as u64) } fn stream_position(&mut self) -> io::Result { - Ok(self.pos) + Ok(self.position()) } } @@ -327,7 +51,7 @@ where { fn read(&mut self, buf: &mut [u8]) -> io::Result { let n = Read::read(&mut Cursor::split(self).1, buf)?; - self.pos += n as u64; + self.set_position(self.position() + n as u64); Ok(n) } @@ -336,7 +60,7 @@ where Read::read_buf(&mut Cursor::split(self).1, cursor.reborrow())?; - self.pos += (cursor.written() - prev_written) as u64; + self.set_position(self.position() + (cursor.written() - prev_written) as u64); Ok(()) } @@ -361,9 +85,9 @@ where let result = Read::read_exact(&mut Cursor::split(self).1, buf); match result { - Ok(_) => self.pos += buf.len() as u64, + Ok(_) => self.set_position(self.position() + buf.len() as u64), // The only possible error condition is EOF, so place the cursor at "EOF" - Err(_) => self.pos = self.inner.as_ref().len() as u64, + Err(_) => self.set_position(self.get_ref().as_ref().len() as u64), } result @@ -373,7 +97,7 @@ where let prev_written = cursor.written(); let result = Read::read_buf_exact(&mut Cursor::split(self).1, cursor.reborrow()); - self.pos += (cursor.written() - prev_written) as u64; + self.set_position(self.position() + (cursor.written() - prev_written) as u64); result } @@ -383,7 +107,7 @@ where let len = content.len(); buf.try_reserve(len)?; buf.extend_from_slice(content); - self.pos += len as u64; + self.set_position(self.position() + len as u64); Ok(len) } @@ -394,7 +118,7 @@ where let len = content.len(); buf.try_reserve(len)?; buf.push_str(content); - self.pos += len as u64; + self.set_position(self.position() + len as u64); Ok(len) } @@ -409,7 +133,7 @@ where Ok(Cursor::split(self).1) } fn consume(&mut self, amt: usize) { - self.pos += amt as u64; + self.set_position(self.position() + amt as u64); } } @@ -590,12 +314,14 @@ where impl Write for Cursor<&mut [u8]> { #[inline] fn write(&mut self, buf: &[u8]) -> io::Result { - slice_write(&mut self.pos, self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write(pos, inner, buf) } #[inline] fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - slice_write_vectored(&mut self.pos, self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_vectored(pos, inner, bufs) } #[inline] @@ -605,12 +331,14 @@ impl Write for Cursor<&mut [u8]> { #[inline] fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - slice_write_all(&mut self.pos, self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write_all(pos, inner, buf) } #[inline] fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - slice_write_all_vectored(&mut self.pos, self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_all_vectored(pos, inner, bufs) } #[inline] @@ -625,11 +353,13 @@ where A: Allocator, { fn write(&mut self, buf: &[u8]) -> io::Result { - vec_write_all(&mut self.pos, self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + vec_write_all(pos, inner, buf) } fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - vec_write_all_vectored(&mut self.pos, self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + vec_write_all_vectored(pos, inner, bufs) } #[inline] @@ -638,12 +368,14 @@ where } fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - vec_write_all(&mut self.pos, self.inner, buf)?; + let (pos, inner) = self.into_parts_mut(); + vec_write_all(pos, inner, buf)?; Ok(()) } fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - vec_write_all_vectored(&mut self.pos, self.inner, bufs)?; + let (pos, inner) = self.into_parts_mut(); + vec_write_all_vectored(pos, inner, bufs)?; Ok(()) } @@ -659,11 +391,13 @@ where A: Allocator, { fn write(&mut self, buf: &[u8]) -> io::Result { - vec_write_all(&mut self.pos, &mut self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + vec_write_all(pos, inner, buf) } fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - vec_write_all_vectored(&mut self.pos, &mut self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + vec_write_all_vectored(pos, inner, bufs) } #[inline] @@ -672,12 +406,14 @@ where } fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - vec_write_all(&mut self.pos, &mut self.inner, buf)?; + let (pos, inner) = self.into_parts_mut(); + vec_write_all(pos, inner, buf)?; Ok(()) } fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - vec_write_all_vectored(&mut self.pos, &mut self.inner, bufs)?; + let (pos, inner) = self.into_parts_mut(); + vec_write_all_vectored(pos, inner, bufs)?; Ok(()) } @@ -694,12 +430,14 @@ where { #[inline] fn write(&mut self, buf: &[u8]) -> io::Result { - slice_write(&mut self.pos, &mut self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write(pos, inner, buf) } #[inline] fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - slice_write_vectored(&mut self.pos, &mut self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_vectored(pos, inner, bufs) } #[inline] @@ -709,12 +447,14 @@ where #[inline] fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - slice_write_all(&mut self.pos, &mut self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write_all(pos, inner, buf) } #[inline] fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - slice_write_all_vectored(&mut self.pos, &mut self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_all_vectored(pos, inner, bufs) } #[inline] @@ -727,12 +467,14 @@ where impl Write for Cursor<[u8; N]> { #[inline] fn write(&mut self, buf: &[u8]) -> io::Result { - slice_write(&mut self.pos, &mut self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write(pos, inner, buf) } #[inline] fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { - slice_write_vectored(&mut self.pos, &mut self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_vectored(pos, inner, bufs) } #[inline] @@ -742,12 +484,14 @@ impl Write for Cursor<[u8; N]> { #[inline] fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { - slice_write_all(&mut self.pos, &mut self.inner, buf) + let (pos, inner) = self.into_parts_mut(); + slice_write_all(pos, inner, buf) } #[inline] fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { - slice_write_all_vectored(&mut self.pos, &mut self.inner, bufs) + let (pos, inner) = self.into_parts_mut(); + slice_write_all_vectored(pos, inner, bufs) } #[inline] diff --git a/std/src/io/error.rs b/std/src/io/error.rs index e6c6f7d766c02..360ca83c65a91 100644 --- a/std/src/io/error.rs +++ b/std/src/io/error.rs @@ -1,6 +1,11 @@ #[cfg(test)] mod tests; +#[stable(feature = "rust1", since = "1.0.0")] +pub use core::io::ErrorKind; +#[unstable(feature = "raw_os_error_ty", issue = "107792")] +pub use core::io::RawOsError; + // On 64-bit platforms, `io::Error` may use a bit-packed representation to // reduce size. However, this representation assumes that error codes are // always 32-bit wide. @@ -137,17 +142,6 @@ enum ErrorData { Custom(C), } -/// The type of raw OS error codes returned by [`Error::raw_os_error`]. -/// -/// This is an [`i32`] on all currently supported platforms, but platforms -/// added in the future (such as UEFI) may use a different primitive type like -/// [`usize`]. Use `as`or [`into`] conversions where applicable to ensure maximum -/// portability. -/// -/// [`into`]: Into::into -#[unstable(feature = "raw_os_error_ty", issue = "107792")] -pub type RawOsError = sys::io::RawOsError; - // `#[repr(align(4))]` is probably redundant, it should have that value or // higher already. We include it just because repr_bitpacked.rs's encoding // requires an alignment >= 4 (note that `#[repr(align)]` will not reduce the @@ -206,323 +200,6 @@ struct Custom { error: Box, } -/// A list specifying general categories of I/O error. -/// -/// This list is intended to grow over time and it is not recommended to -/// exhaustively match against it. -/// -/// It is used with the [`io::Error`] type. -/// -/// [`io::Error`]: Error -/// -/// # Handling errors and matching on `ErrorKind` -/// -/// In application code, use `match` for the `ErrorKind` values you are -/// expecting; use `_` to match "all other errors". -/// -/// In comprehensive and thorough tests that want to verify that a test doesn't -/// return any known incorrect error kind, you may want to cut-and-paste the -/// current full list of errors from here into your test code, and then match -/// `_` as the correct case. This seems counterintuitive, but it will make your -/// tests more robust. In particular, if you want to verify that your code does -/// produce an unrecognized error kind, the robust solution is to check for all -/// the recognized error kinds and fail in those cases. -#[derive(Clone, Copy, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)] -#[stable(feature = "rust1", since = "1.0.0")] -#[cfg_attr(not(test), rustc_diagnostic_item = "io_errorkind")] -#[allow(deprecated)] -#[non_exhaustive] -pub enum ErrorKind { - /// An entity was not found, often a file. - #[stable(feature = "rust1", since = "1.0.0")] - NotFound, - /// The operation lacked the necessary privileges to complete. - #[stable(feature = "rust1", since = "1.0.0")] - PermissionDenied, - /// The connection was refused by the remote server. - #[stable(feature = "rust1", since = "1.0.0")] - ConnectionRefused, - /// The connection was reset by the remote server. - #[stable(feature = "rust1", since = "1.0.0")] - ConnectionReset, - /// The remote host is not reachable. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - HostUnreachable, - /// The network containing the remote host is not reachable. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - NetworkUnreachable, - /// The connection was aborted (terminated) by the remote server. - #[stable(feature = "rust1", since = "1.0.0")] - ConnectionAborted, - /// The network operation failed because it was not connected yet. - #[stable(feature = "rust1", since = "1.0.0")] - NotConnected, - /// A socket address could not be bound because the address is already in - /// use elsewhere. - #[stable(feature = "rust1", since = "1.0.0")] - AddrInUse, - /// A nonexistent interface was requested or the requested address was not - /// local. - #[stable(feature = "rust1", since = "1.0.0")] - AddrNotAvailable, - /// The system's networking is down. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - NetworkDown, - /// The operation failed because a pipe was closed. - #[stable(feature = "rust1", since = "1.0.0")] - BrokenPipe, - /// An entity already exists, often a file. - #[stable(feature = "rust1", since = "1.0.0")] - AlreadyExists, - /// The operation needs to block to complete, but the blocking operation was - /// requested to not occur. - #[stable(feature = "rust1", since = "1.0.0")] - WouldBlock, - /// A filesystem object is, unexpectedly, not a directory. - /// - /// For example, a filesystem path was specified where one of the intermediate directory - /// components was, in fact, a plain file. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - NotADirectory, - /// The filesystem object is, unexpectedly, a directory. - /// - /// A directory was specified when a non-directory was expected. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - IsADirectory, - /// A non-empty directory was specified where an empty directory was expected. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - DirectoryNotEmpty, - /// The filesystem or storage medium is read-only, but a write operation was attempted. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - ReadOnlyFilesystem, - /// Loop in the filesystem or IO subsystem; often, too many levels of symbolic links. - /// - /// There was a loop (or excessively long chain) resolving a filesystem object - /// or file IO object. - /// - /// On Unix this is usually the result of a symbolic link loop; or, of exceeding the - /// system-specific limit on the depth of symlink traversal. - #[unstable(feature = "io_error_more", issue = "86442")] - FilesystemLoop, - /// Stale network file handle. - /// - /// With some network filesystems, notably NFS, an open file (or directory) can be invalidated - /// by problems with the network or server. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - StaleNetworkFileHandle, - /// A parameter was incorrect. - #[stable(feature = "rust1", since = "1.0.0")] - InvalidInput, - /// Data not valid for the operation were encountered. - /// - /// Unlike [`InvalidInput`], this typically means that the operation - /// parameters were valid, however the error was caused by malformed - /// input data. - /// - /// For example, a function that reads a file into a string will error with - /// `InvalidData` if the file's contents are not valid UTF-8. - /// - /// [`InvalidInput`]: ErrorKind::InvalidInput - #[stable(feature = "io_invalid_data", since = "1.2.0")] - InvalidData, - /// The I/O operation's timeout expired, causing it to be canceled. - #[stable(feature = "rust1", since = "1.0.0")] - TimedOut, - /// An error returned when an operation could not be completed because a - /// call to [`write`] returned [`Ok(0)`]. - /// - /// This typically means that an operation could only succeed if it wrote a - /// particular number of bytes but only a smaller number of bytes could be - /// written. - /// - /// [`write`]: crate::io::Write::write - /// [`Ok(0)`]: Ok - #[stable(feature = "rust1", since = "1.0.0")] - WriteZero, - /// The underlying storage (typically, a filesystem) is full. - /// - /// This does not include out of quota errors. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - StorageFull, - /// Seek on unseekable file. - /// - /// Seeking was attempted on an open file handle which is not suitable for seeking - for - /// example, on Unix, a named pipe opened with `File::open`. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - NotSeekable, - /// Filesystem quota or some other kind of quota was exceeded. - #[stable(feature = "io_error_quota_exceeded", since = "1.85.0")] - QuotaExceeded, - /// File larger than allowed or supported. - /// - /// This might arise from a hard limit of the underlying filesystem or file access API, or from - /// an administratively imposed resource limitation. Simple disk full, and out of quota, have - /// their own errors. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - FileTooLarge, - /// Resource is busy. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - ResourceBusy, - /// Executable file is busy. - /// - /// An attempt was made to write to a file which is also in use as a running program. (Not all - /// operating systems detect this situation.) - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - ExecutableFileBusy, - /// Deadlock (avoided). - /// - /// A file locking operation would result in deadlock. This situation is typically detected, if - /// at all, on a best-effort basis. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - Deadlock, - /// Cross-device or cross-filesystem (hard) link or rename. - #[stable(feature = "io_error_crosses_devices", since = "1.85.0")] - CrossesDevices, - /// Too many (hard) links to the same filesystem object. - /// - /// The filesystem does not support making so many hardlinks to the same file. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - TooManyLinks, - /// A filename was invalid. - /// - /// This error can also occur if a length limit for a name was exceeded. - #[stable(feature = "io_error_invalid_filename", since = "1.87.0")] - InvalidFilename, - /// Program argument list too long. - /// - /// When trying to run an external program, a system or process limit on the size of the - /// arguments would have been exceeded. - #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] - ArgumentListTooLong, - /// This operation was interrupted. - /// - /// Interrupted operations can typically be retried. - #[stable(feature = "rust1", since = "1.0.0")] - Interrupted, - - /// This operation is unsupported on this platform. - /// - /// This means that the operation can never succeed. - #[stable(feature = "unsupported_error", since = "1.53.0")] - Unsupported, - - // ErrorKinds which are primarily categorisations for OS error - // codes should be added above. - // - /// An error returned when an operation could not be completed because an - /// "end of file" was reached prematurely. - /// - /// This typically means that an operation could only succeed if it read a - /// particular number of bytes but only a smaller number of bytes could be - /// read. - #[stable(feature = "read_exact", since = "1.6.0")] - UnexpectedEof, - - /// An operation could not be completed, because it failed - /// to allocate enough memory. - #[stable(feature = "out_of_memory_error", since = "1.54.0")] - OutOfMemory, - - /// The operation was partially successful and needs to be checked - /// later on due to not blocking. - #[unstable(feature = "io_error_inprogress", issue = "130840")] - InProgress, - - // "Unusual" error kinds which do not correspond simply to (sets - // of) OS error codes, should be added just above this comment. - // `Other` and `Uncategorized` should remain at the end: - // - /// A custom error that does not fall under any other I/O error kind. - /// - /// This can be used to construct your own [`Error`]s that do not match any - /// [`ErrorKind`]. - /// - /// This [`ErrorKind`] is not used by the standard library. - /// - /// Errors from the standard library that do not fall under any of the I/O - /// error kinds cannot be `match`ed on, and will only match a wildcard (`_`) pattern. - /// New [`ErrorKind`]s might be added in the future for some of those. - #[stable(feature = "rust1", since = "1.0.0")] - Other, - - /// Any I/O error from the standard library that's not part of this list. - /// - /// Errors that are `Uncategorized` now may move to a different or a new - /// [`ErrorKind`] variant in the future. It is not recommended to match - /// an error against `Uncategorized`; use a wildcard match (`_`) instead. - #[unstable(feature = "io_error_uncategorized", issue = "none")] - #[doc(hidden)] - Uncategorized, -} - -impl ErrorKind { - pub(crate) fn as_str(&self) -> &'static str { - use ErrorKind::*; - match *self { - // tidy-alphabetical-start - AddrInUse => "address in use", - AddrNotAvailable => "address not available", - AlreadyExists => "entity already exists", - ArgumentListTooLong => "argument list too long", - BrokenPipe => "broken pipe", - ConnectionAborted => "connection aborted", - ConnectionRefused => "connection refused", - ConnectionReset => "connection reset", - CrossesDevices => "cross-device link or rename", - Deadlock => "deadlock", - DirectoryNotEmpty => "directory not empty", - ExecutableFileBusy => "executable file busy", - FileTooLarge => "file too large", - FilesystemLoop => "filesystem loop or indirection limit (e.g. symlink loop)", - HostUnreachable => "host unreachable", - InProgress => "in progress", - Interrupted => "operation interrupted", - InvalidData => "invalid data", - InvalidFilename => "invalid filename", - InvalidInput => "invalid input parameter", - IsADirectory => "is a directory", - NetworkDown => "network down", - NetworkUnreachable => "network unreachable", - NotADirectory => "not a directory", - NotConnected => "not connected", - NotFound => "entity not found", - NotSeekable => "seek on unseekable file", - Other => "other error", - OutOfMemory => "out of memory", - PermissionDenied => "permission denied", - QuotaExceeded => "quota exceeded", - ReadOnlyFilesystem => "read-only filesystem or storage medium", - ResourceBusy => "resource busy", - StaleNetworkFileHandle => "stale network file handle", - StorageFull => "no storage space", - TimedOut => "timed out", - TooManyLinks => "too many links", - Uncategorized => "uncategorized error", - UnexpectedEof => "unexpected end of file", - Unsupported => "unsupported", - WouldBlock => "operation would block", - WriteZero => "write zero", - // tidy-alphabetical-end - } - } -} - -#[stable(feature = "io_errorkind_display", since = "1.60.0")] -impl fmt::Display for ErrorKind { - /// Shows a human-readable description of the `ErrorKind`. - /// - /// This is similar to `impl Display for Error`, but doesn't require first converting to Error. - /// - /// # Examples - /// ``` - /// use std::io::ErrorKind; - /// assert_eq!("entity not found", ErrorKind::NotFound.to_string()); - /// ``` - fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt.write_str(self.as_str()) - } -} - /// Intended for use for errors not exposed to the user, where allocating onto /// the heap (for normal construction via Error::new) is too costly. #[stable(feature = "io_error_from_errorkind", since = "1.14.0")] @@ -1051,7 +728,7 @@ impl fmt::Display for Error { write!(fmt, "{detail} (os error {code})") } ErrorData::Custom(ref c) => c.error.fmt(fmt), - ErrorData::Simple(kind) => write!(fmt, "{}", kind.as_str()), + ErrorData::Simple(kind) => kind.fmt(fmt), ErrorData::SimpleMessage(msg) => msg.message.fmt(fmt), } } diff --git a/std/src/io/error/repr_bitpacked.rs b/std/src/io/error/repr_bitpacked.rs index 7353816a8171b..7c237825459af 100644 --- a/std/src/io/error/repr_bitpacked.rs +++ b/std/src/io/error/repr_bitpacked.rs @@ -253,7 +253,7 @@ where } TAG_SIMPLE => { let kind_bits = (bits >> 32) as u32; - let kind = kind_from_prim(kind_bits).unwrap_or_else(|| { + let kind = ErrorKind::from_prim(kind_bits).unwrap_or_else(|| { debug_assert!(false, "Invalid io::error::Repr bits: `Repr({:#018x})`", bits); // This means the `ptr` passed in was not valid, which violates // the unsafe contract of `decode_repr`. @@ -283,69 +283,6 @@ where } } -// This compiles to the same code as the check+transmute, but doesn't require -// unsafe, or to hard-code max ErrorKind or its size in a way the compiler -// couldn't verify. -#[inline] -fn kind_from_prim(ek: u32) -> Option { - macro_rules! from_prim { - ($prim:expr => $Enum:ident { $($Variant:ident),* $(,)? }) => {{ - // Force a compile error if the list gets out of date. - const _: fn(e: $Enum) = |e: $Enum| match e { - $($Enum::$Variant => ()),* - }; - match $prim { - $(v if v == ($Enum::$Variant as _) => Some($Enum::$Variant),)* - _ => None, - } - }} - } - from_prim!(ek => ErrorKind { - NotFound, - PermissionDenied, - ConnectionRefused, - ConnectionReset, - HostUnreachable, - NetworkUnreachable, - ConnectionAborted, - NotConnected, - AddrInUse, - AddrNotAvailable, - NetworkDown, - BrokenPipe, - AlreadyExists, - WouldBlock, - NotADirectory, - IsADirectory, - DirectoryNotEmpty, - ReadOnlyFilesystem, - FilesystemLoop, - StaleNetworkFileHandle, - InvalidInput, - InvalidData, - TimedOut, - WriteZero, - StorageFull, - NotSeekable, - QuotaExceeded, - FileTooLarge, - ResourceBusy, - ExecutableFileBusy, - Deadlock, - CrossesDevices, - TooManyLinks, - InvalidFilename, - ArgumentListTooLong, - Interrupted, - Other, - UnexpectedEof, - Unsupported, - OutOfMemory, - InProgress, - Uncategorized, - }) -} - // Some static checking to alert us if a change breaks any of the assumptions // that our encoding relies on for correctness and soundness. (Some of these are // a bit overly thorough/cautious, admittedly) diff --git a/std/src/io/impls.rs b/std/src/io/impls.rs index d0245f3d4984c..f0b7764b4cc5e 100644 --- a/std/src/io/impls.rs +++ b/std/src/io/impls.rs @@ -4,6 +4,7 @@ mod tests; use crate::alloc::Allocator; use crate::collections::VecDeque; use crate::io::{self, BorrowedCursor, BufRead, IoSlice, IoSliceMut, Read, Seek, SeekFrom, Write}; +use crate::sync::Arc; use crate::{cmp, fmt, mem, str}; // ============================================================================= @@ -715,3 +716,122 @@ impl<'a> io::Write for core::io::BorrowedCursor<'a> { Ok(()) } } + +#[stable(feature = "io_traits_arc", since = "1.73.0")] +impl Read for Arc +where + for<'a> &'a R: Read, + R: crate::io::IoHandle, +{ + #[inline] + fn read(&mut self, buf: &mut [u8]) -> io::Result { + (&**self).read(buf) + } + + #[inline] + fn read_buf(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + (&**self).read_buf(cursor) + } + + #[inline] + fn read_vectored(&mut self, bufs: &mut [IoSliceMut<'_>]) -> io::Result { + (&**self).read_vectored(bufs) + } + + #[inline] + fn is_read_vectored(&self) -> bool { + (&**self).is_read_vectored() + } + + #[inline] + fn read_to_end(&mut self, buf: &mut Vec) -> io::Result { + (&**self).read_to_end(buf) + } + + #[inline] + fn read_to_string(&mut self, buf: &mut String) -> io::Result { + (&**self).read_to_string(buf) + } + + #[inline] + fn read_exact(&mut self, buf: &mut [u8]) -> io::Result<()> { + (&**self).read_exact(buf) + } + + #[inline] + fn read_buf_exact(&mut self, cursor: BorrowedCursor<'_>) -> io::Result<()> { + (&**self).read_buf_exact(cursor) + } +} +#[stable(feature = "io_traits_arc", since = "1.73.0")] +impl Write for Arc +where + for<'a> &'a W: Write, + W: crate::io::IoHandle, +{ + #[inline] + fn write(&mut self, buf: &[u8]) -> io::Result { + (&**self).write(buf) + } + + #[inline] + fn write_vectored(&mut self, bufs: &[IoSlice<'_>]) -> io::Result { + (&**self).write_vectored(bufs) + } + + #[inline] + fn is_write_vectored(&self) -> bool { + (&**self).is_write_vectored() + } + + #[inline] + fn flush(&mut self) -> io::Result<()> { + (&**self).flush() + } + + #[inline] + fn write_all(&mut self, buf: &[u8]) -> io::Result<()> { + (&**self).write_all(buf) + } + + #[inline] + fn write_all_vectored(&mut self, bufs: &mut [IoSlice<'_>]) -> io::Result<()> { + (&**self).write_all_vectored(bufs) + } + + #[inline] + fn write_fmt(&mut self, fmt: fmt::Arguments<'_>) -> io::Result<()> { + (&**self).write_fmt(fmt) + } +} +#[stable(feature = "io_traits_arc", since = "1.73.0")] +impl Seek for Arc +where + for<'a> &'a S: Seek, + S: crate::io::IoHandle, +{ + #[inline] + fn seek(&mut self, pos: SeekFrom) -> io::Result { + (&**self).seek(pos) + } + + #[inline] + fn rewind(&mut self) -> io::Result<()> { + (&**self).rewind() + } + + #[inline] + fn stream_len(&mut self) -> io::Result { + (&**self).stream_len() + } + + #[inline] + fn stream_position(&mut self) -> io::Result { + (&**self).stream_position() + } + + #[inline] + fn seek_relative(&mut self, offset: i64) -> io::Result<()> { + (&**self).seek_relative(offset) + } +} diff --git a/std/src/io/mod.rs b/std/src/io/mod.rs index cba578cd3a6fa..91092579a884e 100644 --- a/std/src/io/mod.rs +++ b/std/src/io/mod.rs @@ -299,6 +299,10 @@ mod tests; #[unstable(feature = "read_buf", issue = "78485")] pub use core::io::{BorrowedBuf, BorrowedCursor}; +#[stable(feature = "rust1", since = "1.0.0")] +pub use core::io::{Chain, Empty, Repeat, Sink, Take, empty, repeat, sink}; +#[stable(feature = "iovec", since = "1.36.0")] +pub use core::io::{IoSlice, IoSliceMut}; use core::slice::memchr; #[stable(feature = "bufwriter_into_parts", since = "1.56.0")] @@ -328,11 +332,9 @@ pub use self::{ cursor::Cursor, error::{Error, ErrorKind, Result}, stdio::{Stderr, StderrLock, Stdin, StdinLock, Stdout, StdoutLock, stderr, stdin, stdout}, - util::{Empty, Repeat, Sink, empty, repeat, sink}, }; -use crate::mem::{MaybeUninit, take}; -use crate::ops::{Deref, DerefMut}; -use crate::{cmp, fmt, slice, str, sys}; +use crate::mem::MaybeUninit; +use crate::{cmp, fmt, slice, str}; mod buffered; pub(crate) mod copy; @@ -419,8 +421,6 @@ pub(crate) fn default_read_to_end( .and_then(|s| s.checked_add(1024)?.checked_next_multiple_of(DEFAULT_BUF_SIZE)) .unwrap_or(DEFAULT_BUF_SIZE); - let mut initialized = 0; // Extra initialized bytes from previous loop iteration - const PROBE_SIZE: usize = 32; fn small_probe_read(r: &mut R, buf: &mut Vec) -> Result { @@ -449,8 +449,6 @@ pub(crate) fn default_read_to_end( } } - let mut consecutive_short_reads = 0; - loop { if buf.len() == buf.capacity() && buf.capacity() == start_cap { // The buffer might be an exact fit. Let's read into a probe buffer @@ -474,11 +472,8 @@ pub(crate) fn default_read_to_end( spare = &mut spare[..buf_len]; let mut read_buf: BorrowedBuf<'_> = spare.into(); - // SAFETY: These bytes were initialized but not filled in the previous loop - unsafe { - read_buf.set_init(initialized); - } - + // Note that we don't track already initialized bytes here, but this is fine + // because we explicitly limit the read size let mut cursor = read_buf.unfilled(); let result = loop { match r.read_buf(cursor.reborrow()) { @@ -489,9 +484,8 @@ pub(crate) fn default_read_to_end( } }; - let unfilled_but_initialized = cursor.init_mut().len(); let bytes_read = cursor.written(); - let was_fully_initialized = read_buf.init_len() == buf_len; + let is_init = read_buf.is_init(); // SAFETY: BorrowedBuf's invariants mean this much memory is initialized. unsafe { @@ -506,15 +500,6 @@ pub(crate) fn default_read_to_end( return Ok(buf.len() - start_len); } - if bytes_read < buf_len { - consecutive_short_reads += 1; - } else { - consecutive_short_reads = 0; - } - - // store how much was initialized but not filled - initialized = unfilled_but_initialized; - // Use heuristics to determine the max read size if no initial size hint was provided if size_hint.is_none() { // The reader is returning short reads but it doesn't call ensure_init(). @@ -523,13 +508,12 @@ pub(crate) fn default_read_to_end( // When reading from disk we usually don't get any short reads except at EOF. // So we wait for at least 2 short reads before uncapping the read buffer; // this helps with the Windows issue. - if !was_fully_initialized && consecutive_short_reads > 1 { + if !is_init { max_read_size = usize::MAX; } - // we have passed a larger buffer than previously and the // reader still hasn't returned a short read - if buf_len >= max_read_size && bytes_read == buf_len { + else if buf_len >= max_read_size && bytes_read == buf_len { max_read_size = max_read_size.saturating_mul(2); } } @@ -587,8 +571,8 @@ pub(crate) fn default_read_buf(read: F, mut cursor: BorrowedCursor<'_>) -> Re where F: FnOnce(&mut [u8]) -> Result, { - let n = read(cursor.ensure_init().init_mut())?; - cursor.advance(n); + let n = read(cursor.ensure_init())?; + cursor.advance_checked(n); Ok(()) } @@ -1201,7 +1185,7 @@ pub trait Read { where Self: Sized, { - Chain { first: self, second: next, done_first: false } + core::io::chain(self, next) } /// Creates an adapter which will read at most `limit` bytes from it. @@ -1240,7 +1224,7 @@ pub trait Read { where Self: Sized, { - Take { inner: self, len: limit, limit } + core::io::take(self, limit) } /// Read and return a fixed array of bytes from this source. @@ -1349,323 +1333,6 @@ pub fn read_to_string(mut reader: R) -> Result { Ok(buf) } -/// A buffer type used with `Read::read_vectored`. -/// -/// It is semantically a wrapper around a `&mut [u8]`, but is guaranteed to be -/// ABI compatible with the `iovec` type on Unix platforms and `WSABUF` on -/// Windows. -#[stable(feature = "iovec", since = "1.36.0")] -#[repr(transparent)] -pub struct IoSliceMut<'a>(sys::io::IoSliceMut<'a>); - -#[stable(feature = "iovec_send_sync", since = "1.44.0")] -unsafe impl<'a> Send for IoSliceMut<'a> {} - -#[stable(feature = "iovec_send_sync", since = "1.44.0")] -unsafe impl<'a> Sync for IoSliceMut<'a> {} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> fmt::Debug for IoSliceMut<'a> { - fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Debug::fmt(self.0.as_slice(), fmt) - } -} - -impl<'a> IoSliceMut<'a> { - /// Creates a new `IoSliceMut` wrapping a byte slice. - /// - /// # Panics - /// - /// Panics on Windows if the slice is larger than 4GB. - #[stable(feature = "iovec", since = "1.36.0")] - #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { - IoSliceMut(sys::io::IoSliceMut::new(buf)) - } - - /// Advance the internal cursor of the slice. - /// - /// Also see [`IoSliceMut::advance_slices`] to advance the cursors of - /// multiple buffers. - /// - /// # Panics - /// - /// Panics when trying to advance beyond the end of the slice. - /// - /// # Examples - /// - /// ``` - /// use std::io::IoSliceMut; - /// use std::ops::Deref; - /// - /// let mut data = [1; 8]; - /// let mut buf = IoSliceMut::new(&mut data); - /// - /// // Mark 3 bytes as read. - /// buf.advance(3); - /// assert_eq!(buf.deref(), [1; 5].as_ref()); - /// ``` - #[stable(feature = "io_slice_advance", since = "1.81.0")] - #[inline] - pub fn advance(&mut self, n: usize) { - self.0.advance(n) - } - - /// Advance a slice of slices. - /// - /// Shrinks the slice to remove any `IoSliceMut`s that are fully advanced over. - /// If the cursor ends up in the middle of an `IoSliceMut`, it is modified - /// to start at that cursor. - /// - /// For example, if we have a slice of two 8-byte `IoSliceMut`s, and we advance by 10 bytes, - /// the result will only include the second `IoSliceMut`, advanced by 2 bytes. - /// - /// # Panics - /// - /// Panics when trying to advance beyond the end of the slices. - /// - /// # Examples - /// - /// ``` - /// use std::io::IoSliceMut; - /// use std::ops::Deref; - /// - /// let mut buf1 = [1; 8]; - /// let mut buf2 = [2; 16]; - /// let mut buf3 = [3; 8]; - /// let mut bufs = &mut [ - /// IoSliceMut::new(&mut buf1), - /// IoSliceMut::new(&mut buf2), - /// IoSliceMut::new(&mut buf3), - /// ][..]; - /// - /// // Mark 10 bytes as read. - /// IoSliceMut::advance_slices(&mut bufs, 10); - /// assert_eq!(bufs[0].deref(), [2; 14].as_ref()); - /// assert_eq!(bufs[1].deref(), [3; 8].as_ref()); - /// ``` - #[stable(feature = "io_slice_advance", since = "1.81.0")] - #[inline] - pub fn advance_slices(bufs: &mut &mut [IoSliceMut<'a>], n: usize) { - // Number of buffers to remove. - let mut remove = 0; - // Remaining length before reaching n. - let mut left = n; - for buf in bufs.iter() { - if let Some(remainder) = left.checked_sub(buf.len()) { - left = remainder; - remove += 1; - } else { - break; - } - } - - *bufs = &mut take(bufs)[remove..]; - if bufs.is_empty() { - assert!(left == 0, "advancing io slices beyond their length"); - } else { - bufs[0].advance(left); - } - } - - /// Get the underlying bytes as a mutable slice with the original lifetime. - /// - /// # Examples - /// - /// ``` - /// #![feature(io_slice_as_bytes)] - /// use std::io::IoSliceMut; - /// - /// let mut data = *b"abcdef"; - /// let io_slice = IoSliceMut::new(&mut data); - /// io_slice.into_slice()[0] = b'A'; - /// - /// assert_eq!(&data, b"Abcdef"); - /// ``` - #[unstable(feature = "io_slice_as_bytes", issue = "132818")] - pub const fn into_slice(self) -> &'a mut [u8] { - self.0.into_slice() - } -} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> Deref for IoSliceMut<'a> { - type Target = [u8]; - - #[inline] - fn deref(&self) -> &[u8] { - self.0.as_slice() - } -} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> DerefMut for IoSliceMut<'a> { - #[inline] - fn deref_mut(&mut self) -> &mut [u8] { - self.0.as_mut_slice() - } -} - -/// A buffer type used with `Write::write_vectored`. -/// -/// It is semantically a wrapper around a `&[u8]`, but is guaranteed to be -/// ABI compatible with the `iovec` type on Unix platforms and `WSABUF` on -/// Windows. -#[stable(feature = "iovec", since = "1.36.0")] -#[derive(Copy, Clone)] -#[repr(transparent)] -pub struct IoSlice<'a>(sys::io::IoSlice<'a>); - -#[stable(feature = "iovec_send_sync", since = "1.44.0")] -unsafe impl<'a> Send for IoSlice<'a> {} - -#[stable(feature = "iovec_send_sync", since = "1.44.0")] -unsafe impl<'a> Sync for IoSlice<'a> {} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> fmt::Debug for IoSlice<'a> { - fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Debug::fmt(self.0.as_slice(), fmt) - } -} - -impl<'a> IoSlice<'a> { - /// Creates a new `IoSlice` wrapping a byte slice. - /// - /// # Panics - /// - /// Panics on Windows if the slice is larger than 4GB. - #[stable(feature = "iovec", since = "1.36.0")] - #[must_use] - #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { - IoSlice(sys::io::IoSlice::new(buf)) - } - - /// Advance the internal cursor of the slice. - /// - /// Also see [`IoSlice::advance_slices`] to advance the cursors of multiple - /// buffers. - /// - /// # Panics - /// - /// Panics when trying to advance beyond the end of the slice. - /// - /// # Examples - /// - /// ``` - /// use std::io::IoSlice; - /// use std::ops::Deref; - /// - /// let data = [1; 8]; - /// let mut buf = IoSlice::new(&data); - /// - /// // Mark 3 bytes as read. - /// buf.advance(3); - /// assert_eq!(buf.deref(), [1; 5].as_ref()); - /// ``` - #[stable(feature = "io_slice_advance", since = "1.81.0")] - #[inline] - pub fn advance(&mut self, n: usize) { - self.0.advance(n) - } - - /// Advance a slice of slices. - /// - /// Shrinks the slice to remove any `IoSlice`s that are fully advanced over. - /// If the cursor ends up in the middle of an `IoSlice`, it is modified - /// to start at that cursor. - /// - /// For example, if we have a slice of two 8-byte `IoSlice`s, and we advance by 10 bytes, - /// the result will only include the second `IoSlice`, advanced by 2 bytes. - /// - /// # Panics - /// - /// Panics when trying to advance beyond the end of the slices. - /// - /// # Examples - /// - /// ``` - /// use std::io::IoSlice; - /// use std::ops::Deref; - /// - /// let buf1 = [1; 8]; - /// let buf2 = [2; 16]; - /// let buf3 = [3; 8]; - /// let mut bufs = &mut [ - /// IoSlice::new(&buf1), - /// IoSlice::new(&buf2), - /// IoSlice::new(&buf3), - /// ][..]; - /// - /// // Mark 10 bytes as written. - /// IoSlice::advance_slices(&mut bufs, 10); - /// assert_eq!(bufs[0].deref(), [2; 14].as_ref()); - /// assert_eq!(bufs[1].deref(), [3; 8].as_ref()); - #[stable(feature = "io_slice_advance", since = "1.81.0")] - #[inline] - pub fn advance_slices(bufs: &mut &mut [IoSlice<'a>], n: usize) { - // Number of buffers to remove. - let mut remove = 0; - // Remaining length before reaching n. This prevents overflow - // that could happen if the length of slices in `bufs` were instead - // accumulated. Those slice may be aliased and, if they are large - // enough, their added length may overflow a `usize`. - let mut left = n; - for buf in bufs.iter() { - if let Some(remainder) = left.checked_sub(buf.len()) { - left = remainder; - remove += 1; - } else { - break; - } - } - - *bufs = &mut take(bufs)[remove..]; - if bufs.is_empty() { - assert!(left == 0, "advancing io slices beyond their length"); - } else { - bufs[0].advance(left); - } - } - - /// Get the underlying bytes as a slice with the original lifetime. - /// - /// This doesn't borrow from `self`, so is less restrictive than calling - /// `.deref()`, which does. - /// - /// # Examples - /// - /// ``` - /// #![feature(io_slice_as_bytes)] - /// use std::io::IoSlice; - /// - /// let data = b"abcdef"; - /// - /// let mut io_slice = IoSlice::new(data); - /// let tail = &io_slice.as_slice()[3..]; - /// - /// // This works because `tail` doesn't borrow `io_slice` - /// io_slice = IoSlice::new(tail); - /// - /// assert_eq!(io_slice.as_slice(), b"def"); - /// ``` - #[unstable(feature = "io_slice_as_bytes", issue = "132818")] - pub const fn as_slice(self) -> &'a [u8] { - self.0.as_slice() - } -} - -#[stable(feature = "iovec", since = "1.36.0")] -impl<'a> Deref for IoSlice<'a> { - type Target = [u8]; - - #[inline] - fn deref(&self) -> &[u8] { - self.0.as_slice() - } -} - /// A trait for objects which are byte-oriented sinks. /// /// Implementors of the `Write` trait are sometimes called 'writers'. @@ -2244,6 +1911,21 @@ pub enum SeekFrom { Current(#[stable(feature = "rust1", since = "1.0.0")] i64), } +/// Marks that a type `T` can have IO traits such as [`Seek`], [`Write`], etc. automatically +/// implemented for handle types like [`Arc`][arc] as well. +/// +/// This trait should only be implemented for types where `<&T as Trait>::method(&mut &value, ..)` +/// would be identical to `::method(&mut value, ..)`. +/// +/// [`File`][file] passes this test, as operations on `&File` and `File` both affect +/// the same underlying file. +/// `[u8]` fails, because any modification to `&mut &[u8]` would only affect a temporary +/// and be lost after the method has been called. +/// +/// [file]: crate::fs::File +/// [arc]: crate::sync::Arc +pub(crate) trait IoHandle {} + fn read_until(r: &mut R, delim: u8, buf: &mut Vec) -> Result { let mut read = 0; loop { @@ -2707,99 +2389,6 @@ pub trait BufRead: Read { } } -/// Adapter to chain together two readers. -/// -/// This struct is generally created by calling [`chain`] on a reader. -/// Please see the documentation of [`chain`] for more details. -/// -/// [`chain`]: Read::chain -#[stable(feature = "rust1", since = "1.0.0")] -#[derive(Debug)] -pub struct Chain { - first: T, - second: U, - done_first: bool, -} - -impl Chain { - /// Consumes the `Chain`, returning the wrapped readers. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut foo_file = File::open("foo.txt")?; - /// let mut bar_file = File::open("bar.txt")?; - /// - /// let chain = foo_file.chain(bar_file); - /// let (foo_file, bar_file) = chain.into_inner(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn into_inner(self) -> (T, U) { - (self.first, self.second) - } - - /// Gets references to the underlying readers in this `Chain`. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying readers as doing so may corrupt the internal state of this - /// `Chain`. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut foo_file = File::open("foo.txt")?; - /// let mut bar_file = File::open("bar.txt")?; - /// - /// let chain = foo_file.chain(bar_file); - /// let (foo_file, bar_file) = chain.get_ref(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn get_ref(&self) -> (&T, &U) { - (&self.first, &self.second) - } - - /// Gets mutable references to the underlying readers in this `Chain`. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying readers as doing so may corrupt the internal state of this - /// `Chain`. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut foo_file = File::open("foo.txt")?; - /// let mut bar_file = File::open("bar.txt")?; - /// - /// let mut chain = foo_file.chain(bar_file); - /// let (foo_file, bar_file) = chain.get_mut(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn get_mut(&mut self) -> (&mut T, &mut U) { - (&mut self.first, &mut self.second) - } -} - #[stable(feature = "rust1", since = "1.0.0")] impl Read for Chain { fn read(&mut self, buf: &mut [u8]) -> Result { @@ -2909,170 +2498,6 @@ impl SizeHint for Chain { } } -/// Reader adapter which limits the bytes read from an underlying reader. -/// -/// This struct is generally created by calling [`take`] on a reader. -/// Please see the documentation of [`take`] for more details. -/// -/// [`take`]: Read::take -#[stable(feature = "rust1", since = "1.0.0")] -#[derive(Debug)] -pub struct Take { - inner: T, - len: u64, - limit: u64, -} - -impl Take { - /// Returns the number of bytes that can be read before this instance will - /// return EOF. - /// - /// # Note - /// - /// This instance may reach `EOF` after reading fewer bytes than indicated by - /// this method if the underlying [`Read`] instance reaches EOF. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let f = File::open("foo.txt")?; - /// - /// // read at most five bytes - /// let handle = f.take(5); - /// - /// println!("limit: {}", handle.limit()); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "rust1", since = "1.0.0")] - pub fn limit(&self) -> u64 { - self.limit - } - - /// Returns the number of bytes read so far. - #[unstable(feature = "seek_io_take_position", issue = "97227")] - pub fn position(&self) -> u64 { - self.len - self.limit - } - - /// Sets the number of bytes that can be read before this instance will - /// return EOF. This is the same as constructing a new `Take` instance, so - /// the amount of bytes read and the previous limit value don't matter when - /// calling this method. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let f = File::open("foo.txt")?; - /// - /// // read at most five bytes - /// let mut handle = f.take(5); - /// handle.set_limit(10); - /// - /// assert_eq!(handle.limit(), 10); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "take_set_limit", since = "1.27.0")] - pub fn set_limit(&mut self, limit: u64) { - self.len = limit; - self.limit = limit; - } - - /// Consumes the `Take`, returning the wrapped reader. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut file = File::open("foo.txt")?; - /// - /// let mut buffer = [0; 5]; - /// let mut handle = file.take(5); - /// handle.read(&mut buffer)?; - /// - /// let file = handle.into_inner(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "io_take_into_inner", since = "1.15.0")] - pub fn into_inner(self) -> T { - self.inner - } - - /// Gets a reference to the underlying reader. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying reader as doing so may corrupt the internal limit of this - /// `Take`. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut file = File::open("foo.txt")?; - /// - /// let mut buffer = [0; 5]; - /// let mut handle = file.take(5); - /// handle.read(&mut buffer)?; - /// - /// let file = handle.get_ref(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn get_ref(&self) -> &T { - &self.inner - } - - /// Gets a mutable reference to the underlying reader. - /// - /// Care should be taken to avoid modifying the internal I/O state of the - /// underlying reader as doing so may corrupt the internal limit of this - /// `Take`. - /// - /// # Examples - /// - /// ```no_run - /// use std::io; - /// use std::io::prelude::*; - /// use std::fs::File; - /// - /// fn main() -> io::Result<()> { - /// let mut file = File::open("foo.txt")?; - /// - /// let mut buffer = [0; 5]; - /// let mut handle = file.take(5); - /// handle.read(&mut buffer)?; - /// - /// let file = handle.get_mut(); - /// Ok(()) - /// } - /// ``` - #[stable(feature = "more_io_inner_methods", since = "1.20.0")] - pub fn get_mut(&mut self) -> &mut T { - &mut self.inner - } -} - #[stable(feature = "rust1", since = "1.0.0")] impl Read for Take { fn read(&mut self, buf: &mut [u8]) -> Result { @@ -3098,31 +2523,40 @@ impl Read for Take { // The condition above guarantees that `self.limit` fits in `usize`. let limit = self.limit as usize; - let extra_init = cmp::min(limit, buf.init_mut().len()); + let is_init = buf.is_init(); // SAFETY: no uninit data is written to ibuf - let ibuf = unsafe { &mut buf.as_mut()[..limit] }; + let mut sliced_buf = BorrowedBuf::from(unsafe { &mut buf.as_mut()[..limit] }); - let mut sliced_buf: BorrowedBuf<'_> = ibuf.into(); - - // SAFETY: extra_init bytes of ibuf are known to be initialized - unsafe { - sliced_buf.set_init(extra_init); + if is_init { + // SAFETY: `sliced_buf` is a subslice of `buf`, so if `buf` was initialized then + // `sliced_buf` is. + unsafe { sliced_buf.set_init() }; } - let mut cursor = sliced_buf.unfilled(); - let result = self.inner.read_buf(cursor.reborrow()); + let result = self.inner.read_buf(sliced_buf.unfilled()); - let new_init = cursor.init_mut().len(); + let did_init_up_to_limit = sliced_buf.is_init(); let filled = sliced_buf.len(); - // cursor / sliced_buf / ibuf must drop here + // sliced_buf must drop here + + // Avoid accidentally quadratic behaviour by initializing the whole + // cursor if only part of it was initialized. + if did_init_up_to_limit && !is_init { + // SAFETY: No uninit data will be written. + let unfilled_before_advance = unsafe { buf.as_mut() }; + + unfilled_before_advance[limit..].write_filled(0); + + // SAFETY: `unfilled_before_advance[..limit]` was initialized by `T::read_buf`, and + // `unfilled_before_advance[limit..]` was just initialized. + unsafe { buf.set_init() }; + } unsafe { - // SAFETY: filled bytes have been filled and therefore initialized - buf.advance_unchecked(filled); - // SAFETY: new_init bytes of buf's unfilled buffer have been initialized - buf.set_init(new_init); + // SAFETY: filled bytes have been filled + buf.advance(filled); } self.limit -= filled as u64; diff --git a/std/src/io/pipe.rs b/std/src/io/pipe.rs index 61b81cf074a6e..e05ccb32a122d 100644 --- a/std/src/io/pipe.rs +++ b/std/src/io/pipe.rs @@ -40,8 +40,6 @@ use crate::sys::{FromInner, IntoInner, pipe as imp}; /// # Example /// /// ```no_run -/// # #[cfg(miri)] fn main() {} -/// # #[cfg(not(miri))] /// # fn main() -> std::io::Result<()> { /// use std::io::{Read, Write, pipe}; /// use std::process::Command; @@ -126,8 +124,6 @@ impl PipeReader { /// # Examples /// /// ```no_run - /// # #[cfg(miri)] fn main() {} - /// # #[cfg(not(miri))] /// # fn main() -> std::io::Result<()> { /// use std::fs; /// use std::io::{pipe, Write}; @@ -185,8 +181,6 @@ impl PipeWriter { /// # Examples /// /// ```no_run - /// # #[cfg(miri)] fn main() {} - /// # #[cfg(not(miri))] /// # fn main() -> std::io::Result<()> { /// use std::process::Command; /// use std::io::{pipe, Read}; diff --git a/std/src/io/pipe/tests.rs b/std/src/io/pipe/tests.rs index f113b157459d3..2c2d35cc63d9e 100644 --- a/std/src/io/pipe/tests.rs +++ b/std/src/io/pipe/tests.rs @@ -1,7 +1,6 @@ use crate::io::{Read, Write, pipe}; #[test] -#[cfg(all(any(unix, windows), not(miri)))] fn pipe_creation_clone_and_rw() { let (rx, tx) = pipe().unwrap(); diff --git a/std/src/io/stdio.rs b/std/src/io/stdio.rs index 2d80fe49e80a7..5498ccd11b26b 100644 --- a/std/src/io/stdio.rs +++ b/std/src/io/stdio.rs @@ -285,6 +285,7 @@ pub struct Stdin { /// ``` #[must_use = "if unused stdin will immediately unlock"] #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "StdinLock")] pub struct StdinLock<'a> { inner: MutexGuard<'a, BufReader>, } @@ -1242,7 +1243,7 @@ pub trait IsTerminal: crate::sealed::Sealed { /// /// [changes]: io#platform-specific-behavior /// [`Stdin`]: crate::io::Stdin - #[doc(alias = "isatty")] + #[doc(alias = "isatty", alias = "atty")] #[stable(feature = "is_terminal", since = "1.70.0")] fn is_terminal(&self) -> bool; } diff --git a/std/src/io/tests.rs b/std/src/io/tests.rs index a56359dae765b..56d3bd678e104 100644 --- a/std/src/io/tests.rs +++ b/std/src/io/tests.rs @@ -1,10 +1,7 @@ use super::{BorrowedBuf, Cursor, SeekFrom, repeat}; use crate::cmp::{self, min}; -use crate::io::{ - self, BufRead, BufReader, DEFAULT_BUF_SIZE, IoSlice, IoSliceMut, Read, Seek, Write, -}; +use crate::io::{self, BufRead, BufReader, DEFAULT_BUF_SIZE, IoSlice, Read, Seek, Write}; use crate::mem::MaybeUninit; -use crate::ops::Deref; #[test] fn read_until() { @@ -214,8 +211,8 @@ fn read_buf_exact() { fn borrowed_cursor_advance_overflow() { let mut buf = [0; 512]; let mut buf = BorrowedBuf::from(&mut buf[..]); - buf.unfilled().advance(1); - buf.unfilled().advance(usize::MAX); + buf.unfilled().advance_checked(1); + buf.unfilled().advance_checked(usize::MAX); } #[test] @@ -565,104 +562,6 @@ fn test_read_to_end_capacity() -> io::Result<()> { Ok(()) } -#[test] -fn io_slice_mut_advance_slices() { - let mut buf1 = [1; 8]; - let mut buf2 = [2; 16]; - let mut buf3 = [3; 8]; - let mut bufs = &mut [ - IoSliceMut::new(&mut buf1), - IoSliceMut::new(&mut buf2), - IoSliceMut::new(&mut buf3), - ][..]; - - // Only in a single buffer.. - IoSliceMut::advance_slices(&mut bufs, 1); - assert_eq!(bufs[0].deref(), [1; 7].as_ref()); - assert_eq!(bufs[1].deref(), [2; 16].as_ref()); - assert_eq!(bufs[2].deref(), [3; 8].as_ref()); - - // Removing a buffer, leaving others as is. - IoSliceMut::advance_slices(&mut bufs, 7); - assert_eq!(bufs[0].deref(), [2; 16].as_ref()); - assert_eq!(bufs[1].deref(), [3; 8].as_ref()); - - // Removing a buffer and removing from the next buffer. - IoSliceMut::advance_slices(&mut bufs, 18); - assert_eq!(bufs[0].deref(), [3; 6].as_ref()); -} - -#[test] -#[should_panic] -fn io_slice_mut_advance_slices_empty_slice() { - let mut empty_bufs = &mut [][..]; - IoSliceMut::advance_slices(&mut empty_bufs, 1); -} - -#[test] -#[should_panic] -fn io_slice_mut_advance_slices_beyond_total_length() { - let mut buf1 = [1; 8]; - let mut bufs = &mut [IoSliceMut::new(&mut buf1)][..]; - - IoSliceMut::advance_slices(&mut bufs, 9); - assert!(bufs.is_empty()); -} - -#[test] -fn io_slice_advance_slices() { - let buf1 = [1; 8]; - let buf2 = [2; 16]; - let buf3 = [3; 8]; - let mut bufs = &mut [IoSlice::new(&buf1), IoSlice::new(&buf2), IoSlice::new(&buf3)][..]; - - // Only in a single buffer.. - IoSlice::advance_slices(&mut bufs, 1); - assert_eq!(bufs[0].deref(), [1; 7].as_ref()); - assert_eq!(bufs[1].deref(), [2; 16].as_ref()); - assert_eq!(bufs[2].deref(), [3; 8].as_ref()); - - // Removing a buffer, leaving others as is. - IoSlice::advance_slices(&mut bufs, 7); - assert_eq!(bufs[0].deref(), [2; 16].as_ref()); - assert_eq!(bufs[1].deref(), [3; 8].as_ref()); - - // Removing a buffer and removing from the next buffer. - IoSlice::advance_slices(&mut bufs, 18); - assert_eq!(bufs[0].deref(), [3; 6].as_ref()); -} - -#[test] -#[should_panic] -fn io_slice_advance_slices_empty_slice() { - let mut empty_bufs = &mut [][..]; - IoSlice::advance_slices(&mut empty_bufs, 1); -} - -#[test] -#[should_panic] -fn io_slice_advance_slices_beyond_total_length() { - let buf1 = [1; 8]; - let mut bufs = &mut [IoSlice::new(&buf1)][..]; - - IoSlice::advance_slices(&mut bufs, 9); - assert!(bufs.is_empty()); -} - -#[test] -fn io_slice_as_slice() { - let buf = [1; 8]; - let slice = IoSlice::new(&buf).as_slice(); - assert_eq!(slice, buf); -} - -#[test] -fn io_slice_into_slice() { - let mut buf = [1; 8]; - let slice = IoSliceMut::new(&mut buf).into_slice(); - assert_eq!(slice, [1; 8]); -} - /// Creates a new writer that reads from at most `n_bufs` and reads /// `per_call` bytes (in total) per call to write. fn test_writer(n_bufs: usize, per_call: usize) -> TestWriter { diff --git a/std/src/io/util.rs b/std/src/io/util.rs index 0410df3ef1a3e..3f207939c7389 100644 --- a/std/src/io/util.rs +++ b/std/src/io/util.rs @@ -5,57 +5,10 @@ mod tests; use crate::fmt; use crate::io::{ - self, BorrowedCursor, BufRead, IoSlice, IoSliceMut, Read, Seek, SeekFrom, SizeHint, Write, + self, BorrowedCursor, BufRead, Empty, IoSlice, IoSliceMut, Read, Repeat, Seek, SeekFrom, Sink, + SizeHint, Write, }; -/// `Empty` ignores any data written via [`Write`], and will always be empty -/// (returning zero bytes) when read via [`Read`]. -/// -/// This struct is generally created by calling [`empty()`]. Please -/// see the documentation of [`empty()`] for more details. -#[stable(feature = "rust1", since = "1.0.0")] -#[non_exhaustive] -#[derive(Copy, Clone, Debug, Default)] -pub struct Empty; - -/// Creates a value that is always at EOF for reads, and ignores all data written. -/// -/// All calls to [`write`] on the returned instance will return [`Ok(buf.len())`] -/// and the contents of the buffer will not be inspected. -/// -/// All calls to [`read`] from the returned reader will return [`Ok(0)`]. -/// -/// [`Ok(buf.len())`]: Ok -/// [`Ok(0)`]: Ok -/// -/// [`write`]: Write::write -/// [`read`]: Read::read -/// -/// # Examples -/// -/// ```rust -/// use std::io::{self, Write}; -/// -/// let buffer = vec![1, 2, 3, 5, 8]; -/// let num_bytes = io::empty().write(&buffer).unwrap(); -/// assert_eq!(num_bytes, 5); -/// ``` -/// -/// -/// ```rust -/// use std::io::{self, Read}; -/// -/// let mut buffer = String::new(); -/// io::empty().read_to_string(&mut buffer).unwrap(); -/// assert!(buffer.is_empty()); -/// ``` -#[must_use] -#[stable(feature = "rust1", since = "1.0.0")] -#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] -pub const fn empty() -> Empty { - Empty -} - #[stable(feature = "rust1", since = "1.0.0")] impl Read for Empty { #[inline] @@ -234,36 +187,6 @@ impl Write for &Empty { } } -/// A reader which yields one byte over and over and over and over and over and... -/// -/// This struct is generally created by calling [`repeat()`]. Please -/// see the documentation of [`repeat()`] for more details. -#[stable(feature = "rust1", since = "1.0.0")] -pub struct Repeat { - byte: u8, -} - -/// Creates an instance of a reader that infinitely repeats one byte. -/// -/// All reads from this reader will succeed by filling the specified buffer with -/// the given byte. -/// -/// # Examples -/// -/// ``` -/// use std::io::{self, Read}; -/// -/// let mut buffer = [0; 3]; -/// io::repeat(0b101).read_exact(&mut buffer).unwrap(); -/// assert_eq!(buffer, [0b101, 0b101, 0b101]); -/// ``` -#[must_use] -#[stable(feature = "rust1", since = "1.0.0")] -#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] -pub const fn repeat(byte: u8) -> Repeat { - Repeat { byte } -} - #[stable(feature = "rust1", since = "1.0.0")] impl Read for Repeat { #[inline] @@ -283,7 +206,7 @@ impl Read for Repeat { // SAFETY: No uninit bytes are being written. unsafe { buf.as_mut() }.write_filled(self.byte); // SAFETY: the entire unfilled portion of buf has been initialized. - unsafe { buf.advance_unchecked(buf.capacity()) }; + unsafe { buf.advance(buf.capacity()) }; Ok(()) } @@ -329,46 +252,6 @@ impl SizeHint for Repeat { } } -#[stable(feature = "std_debug", since = "1.16.0")] -impl fmt::Debug for Repeat { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_struct("Repeat").finish_non_exhaustive() - } -} - -/// A writer which will move data into the void. -/// -/// This struct is generally created by calling [`sink()`]. Please -/// see the documentation of [`sink()`] for more details. -#[stable(feature = "rust1", since = "1.0.0")] -#[non_exhaustive] -#[derive(Copy, Clone, Debug, Default)] -pub struct Sink; - -/// Creates an instance of a writer which will successfully consume all data. -/// -/// All calls to [`write`] on the returned instance will return [`Ok(buf.len())`] -/// and the contents of the buffer will not be inspected. -/// -/// [`write`]: Write::write -/// [`Ok(buf.len())`]: Ok -/// -/// # Examples -/// -/// ```rust -/// use std::io::{self, Write}; -/// -/// let buffer = vec![1, 2, 3, 5, 8]; -/// let num_bytes = io::sink().write(&buffer).unwrap(); -/// assert_eq!(num_bytes, 5); -/// ``` -#[must_use] -#[stable(feature = "rust1", since = "1.0.0")] -#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] -pub const fn sink() -> Sink { - Sink -} - #[stable(feature = "rust1", since = "1.0.0")] impl Write for Sink { #[inline] diff --git a/std/src/io/util/tests.rs b/std/src/io/util/tests.rs index d0f106d7af416..fa1193f2b00fa 100644 --- a/std/src/io/util/tests.rs +++ b/std/src/io/util/tests.rs @@ -75,43 +75,43 @@ fn empty_reads() { let mut buf: BorrowedBuf<'_> = buf.into(); e.read_buf(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit()]; let mut buf: BorrowedBuf<'_> = buf.into(); e.read_buf(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1024]; let mut buf: BorrowedBuf<'_> = buf.into(); e.read_buf(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1024]; let mut buf: BorrowedBuf<'_> = buf.into(); Read::by_ref(&mut e).read_buf(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [MaybeUninit<_>] = &mut []; let mut buf: BorrowedBuf<'_> = buf.into(); e.read_buf_exact(buf.unfilled()).unwrap(); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit()]; let mut buf: BorrowedBuf<'_> = buf.into(); assert_eq!(e.read_buf_exact(buf.unfilled()).unwrap_err().kind(), ErrorKind::UnexpectedEof); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1024]; let mut buf: BorrowedBuf<'_> = buf.into(); assert_eq!(e.read_buf_exact(buf.unfilled()).unwrap_err().kind(), ErrorKind::UnexpectedEof); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let buf: &mut [_] = &mut [MaybeUninit::uninit(); 1024]; let mut buf: BorrowedBuf<'_> = buf.into(); @@ -120,7 +120,7 @@ fn empty_reads() { ErrorKind::UnexpectedEof, ); assert_eq!(buf.len(), 0); - assert_eq!(buf.init_len(), 0); + assert!(!buf.is_init()); let mut buf = Vec::new(); assert_eq!(e.read_to_end(&mut buf).unwrap(), 0); diff --git a/std/src/keyword_docs.rs b/std/src/keyword_docs.rs index dc0d11b07a9f3..5f94a13dad22a 100644 --- a/std/src/keyword_docs.rs +++ b/std/src/keyword_docs.rs @@ -238,7 +238,7 @@ mod break_keyword {} /// /// Turning a `fn` into a `const fn` has no effect on run-time uses of that function. /// -/// ## Other uses of `const` +/// ## raw pointers /// /// The `const` keyword is also used in raw pointers in combination with `mut`, as seen in `*const /// T` and `*mut T`. More about `const` as used in raw pointers can be read at the Rust docs for the [pointer primitive]. @@ -418,7 +418,7 @@ mod else_keyword {} /// The first enum shown is the usual kind of enum you'd find in a C-style language. The second /// shows off a hypothetical example of something storing location data, with `Coord` being any /// other type that's needed, for example a struct. The third example demonstrates the kind of -/// data a variant can store, ranging from nothing, to a tuple, to an anonymous struct. +/// data a variant can store, ranging from nothing, to a tuple, to a struct-like variant. /// /// Instantiating enum variants involves explicitly using the enum's name as its namespace, /// followed by one of its variants. `SimpleEnum::SecondVariant` would be an example from above. @@ -961,14 +961,14 @@ mod loop_keyword {} /// returned. /// /// ```rust -/// let opt = Option::None::; +/// let opt: Option = None; /// let x = match opt { /// Some(int) => int, /// None => 10, /// }; /// assert_eq!(x, 10); /// -/// let a_number = Option::Some(10); +/// let a_number = Some(10); /// match a_number { /// Some(x) if x <= 5 => println!("0 to 5 num = {x}"), /// Some(x @ 6..=10) => println!("6 to 10 num = {x}"), @@ -2042,10 +2042,19 @@ mod type_keyword {} /// system. /// /// The `unsafe` keyword has two uses: -/// - to declare the existence of contracts the compiler can't check (`unsafe fn` and `unsafe -/// trait`), -/// - and to declare that a programmer has checked that these contracts have been upheld (`unsafe -/// {}` and `unsafe impl`, but also `unsafe fn` -- see below). +/// - to declare the existence of contracts the compiler can't check, +/// - and to declare that a programmer has checked that these contracts have been upheld. +/// +/// Typically, each `unsafe` is either of the first or second kind: `unsafe fn` and `unsafe trait` +/// declare the existence of an unsafe contract; `unsafe {}` and `unsafe impl` declare that an +/// unsafe contract (which must have been declared elsewhere) is being upheld. +/// +/// However, historically, these two are not mutually exclusive: the body of an `unsafe fn` is, on +/// old editions, treated like an unsafe block, which means that this use of `unsafe` both declares +/// the existence of a contract to call the current function, and declares that the contracts of the +/// unsafe operations inside this function are being upheld. The `unsafe_op_in_unsafe_fn` lint can +/// be enabled to change that and make `unsafe fn` only play the former role. That lint is enabled +/// by default since edition 2024. /// /// # Unsafe abilities /// @@ -2088,6 +2097,13 @@ mod type_keyword {} /// - `unsafe impl`: the contract necessary to implement the trait has been /// checked by the programmer and is guaranteed to be respected. /// +/// On old editions, `unsafe fn` also acts like an `unsafe {}` block around the code inside the +/// function. This means it is not just a signal to the caller, but also promises that the +/// preconditions for the operations inside the function are upheld. Mixing these two meanings can +/// be confusing, so the `unsafe_op_in_unsafe_fn` lint has been introduced and enabled by default +/// since edition 2024 to warn against that and require explicit unsafe blocks even inside `unsafe +/// fn`. +/// /// See the [Rustonomicon] and the [Reference] for more information. /// /// # Examples diff --git a/std/src/lib.rs b/std/src/lib.rs index 1730742dffe93..8086cab34cf44 100644 --- a/std/src/lib.rs +++ b/std/src/lib.rs @@ -255,7 +255,10 @@ #![allow(unused_features)] // // Features: -#![cfg_attr(test, feature(internal_output_capture, print_internals, update_panic_count, rt))] +#![cfg_attr( + test, + feature(internal_output_capture, print_internals, super_let, update_panic_count, rt) +)] #![cfg_attr( all(target_vendor = "fortanix", target_env = "sgx"), feature(slice_index_methods, coerce_unsized, sgx_platform) @@ -278,6 +281,7 @@ #![feature(const_trait_impl)] #![feature(decl_macro)] #![feature(deprecated_suggestion)] +#![feature(diagnostic_on_move)] #![feature(doc_cfg)] #![feature(doc_masked)] #![feature(doc_notable_trait)] @@ -285,6 +289,7 @@ #![feature(f16)] #![feature(f128)] #![feature(ffi_const)] +#![feature(gpu_offload)] #![feature(intra_doc_pointers)] #![feature(lang_items)] #![feature(link_cfg)] @@ -302,7 +307,6 @@ #![feature(staged_api)] #![feature(stmt_expr_attributes)] #![feature(strict_provenance_lints)] -#![feature(target_feature_inline_always)] #![feature(thread_local)] #![feature(try_blocks)] #![feature(try_trait_v2)] @@ -311,6 +315,7 @@ // // Library features (core): // tidy-alphabetical-start +#![feature(borrowed_buf_init)] #![feature(bstr)] #![feature(bstr_internals)] #![feature(cast_maybe_uninit)] @@ -320,8 +325,11 @@ #![feature(const_default)] #![feature(core_float_math)] #![feature(core_intrinsics)] +#![feature(core_io)] #![feature(core_io_borrowed_buf)] +#![feature(core_io_internals)] #![feature(cstr_display)] +#![feature(cursor_split)] #![feature(drop_guard)] #![feature(duration_constants)] #![feature(error_generic_member_access)] @@ -343,9 +351,14 @@ #![feature(hashmap_internals)] #![feature(hint_must_use)] #![feature(int_from_ascii)] +#![feature(io_error_inprogress)] +#![feature(io_error_more)] +#![feature(io_error_uncategorized)] +#![feature(io_slice_as_bytes)] #![feature(ip)] #![feature(iter_advance_by)] #![feature(iter_next_chunk)] +#![feature(maybe_dangling)] #![feature(maybe_uninit_array_assume_init)] #![feature(maybe_uninit_fill)] #![feature(panic_can_unwind)] @@ -354,8 +367,12 @@ #![feature(pointer_is_aligned_to)] #![feature(portable_simd)] #![feature(ptr_as_uninit)] +#![feature(ptr_cast_slice)] #![feature(ptr_mask)] #![feature(random)] +#![feature(raw_os_error_ty)] +#![feature(seek_io_take_position)] +#![feature(share_trait)] #![feature(slice_internals)] #![feature(slice_ptr_get)] #![feature(slice_range)] @@ -417,6 +434,13 @@ // tidy-alphabetical-end // #![default_lib_allocator] +// Removed features +#![unstable_removed( + feature = "concat_idents", + reason = "Replaced by the macro_metavar_expr_concat feature", + link = "https://github.com/rust-lang/rust/issues/29599#issuecomment-2986866250", + since = "1.90.0" +)] // The Rust prelude // The compiler expects the prelude definition to be defined before its use statement. @@ -470,9 +494,7 @@ extern crate std as realstd; // The standard macros that are not built-in to the compiler. #[macro_use] -#[doc(hidden)] -#[unstable(feature = "std_internals", issue = "none")] -pub mod macros; +mod macros; // The runtime entry point and a few unstable public functions used by the // compiler @@ -537,7 +559,7 @@ pub use core::option; pub use core::pin; #[stable(feature = "rust1", since = "1.0.0")] pub use core::ptr; -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] pub use core::range; #[stable(feature = "rust1", since = "1.0.0")] pub use core::result; @@ -636,12 +658,18 @@ pub mod simd { } #[unstable(feature = "autodiff", issue = "124509")] -/// This module provides support for automatic differentiation. +#[doc = include_str!("../../core/src/autodiff.md")] pub mod autodiff { /// This macro handles automatic differentiation. pub use core::autodiff::{autodiff_forward, autodiff_reverse}; } +#[unstable(feature = "gpu_offload", issue = "131513")] +#[doc = include_str!("../../core/src/offload.md")] +pub mod offload { + pub use core::offload::{offload, offload_kernel}; +} + #[stable(feature = "futures_api", since = "1.36.0")] pub mod task { //! Types and Traits for working with asynchronous tasks. @@ -706,6 +734,8 @@ pub use core::cfg_select; reason = "`concat_bytes` is not stable enough for use and is subject to change" )] pub use core::concat_bytes; +#[unstable(feature = "derive_macro_global_path", issue = "154645")] +pub use core::derive; #[stable(feature = "matches_macro", since = "1.42.0")] #[allow(deprecated, deprecated_in_future)] pub use core::matches; @@ -728,7 +758,7 @@ pub use core::{ assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, r#try, unimplemented, unreachable, write, writeln, }; -#[stable(feature = "assert_matches", since = "1.95.0")] +#[stable(feature = "assert_matches", since = "1.96.0")] pub use core::{assert_matches, debug_assert_matches}; // Re-export unstable derive macro defined through core. diff --git a/std/src/macros.rs b/std/src/macros.rs index 108cd3cd98eb5..8bcf870e9aeb4 100644 --- a/std/src/macros.rs +++ b/std/src/macros.rs @@ -350,73 +350,37 @@ macro_rules! eprintln { /// [`debug!`]: https://docs.rs/log/*/log/macro.debug.html /// [`log`]: https://crates.io/crates/log #[macro_export] -#[allow_internal_unstable(std_internals)] #[cfg_attr(not(test), rustc_diagnostic_item = "dbg_macro")] #[stable(feature = "dbg_macro", since = "1.32.0")] macro_rules! dbg { + // NOTE: We cannot use `concat!` to make a static string as a format argument + // of `eprintln!` because `file!` could contain a `{` or + // `$val` expression could be a block (`{ .. }`), in which case the `eprintln!` + // will be malformed. () => { $crate::eprintln!("[{}:{}:{}]", $crate::file!(), $crate::line!(), $crate::column!()) }; - ($($val:expr),+ $(,)?) => { - $crate::macros::dbg_internal!(() () ($($val),+)) - }; -} - -/// Internal macro that processes a list of expressions, binds their results -/// with `match`, calls `eprint!` with the collected information, and returns -/// all the evaluated expressions in a tuple. -/// -/// E.g. `dbg_internal!(() () (1, 2))` expands into -/// ```rust, ignore -/// match (1, 2) { -/// (tmp_1, tmp_2) => { -/// eprint!("...", &tmp_1, &tmp_2, /* some other arguments */); -/// (tmp_1, tmp_2) -/// } -/// } -/// ``` -/// -/// This is necessary so that `dbg!` outputs don't get torn, see #136703. -#[doc(hidden)] -#[rustc_macro_transparency = "semiopaque"] -pub macro dbg_internal { - (($($piece:literal),+) ($($processed:expr => $bound:ident),+) ()) => { + ($val:expr $(,)?) => { // Use of `match` here is intentional because it affects the lifetimes // of temporaries - https://stackoverflow.com/a/48732525/1063961 - // Always put the arguments in a tuple to avoid an unused parens lint on the pattern. - match ($($processed,)+) { - ($($bound,)+) => { - $crate::eprint!( - $crate::concat!($($piece),+), - $( - $crate::stringify!($processed), - // The `&T: Debug` check happens here (not in the format literal desugaring) - // to avoid format literal related messages and suggestions. - &&$bound as &dyn $crate::fmt::Debug - ),+, - // The location returned here is that of the macro invocation, so - // it will be the same for all expressions. Thus, label these - // arguments so that they can be reused in every piece of the - // formatting template. - file=$crate::file!(), - line=$crate::line!(), - column=$crate::column!() + match $val { + tmp => { + $crate::eprintln!("[{}:{}:{}] {} = {:#?}", + $crate::file!(), + $crate::line!(), + $crate::column!(), + $crate::stringify!($val), + // The `&T: Debug` check happens here (not in the format literal desugaring) + // to avoid format literal related messages and suggestions. + &&tmp as &dyn $crate::fmt::Debug, ); - // Comma separate the variables only when necessary so that this will - // not yield a tuple for a single expression, but rather just parenthesize - // the expression. - ($($bound),+) - + tmp } } - }, - (($($piece:literal),*) ($($processed:expr => $bound:ident),*) ($val:expr $(,$rest:expr)*)) => { - $crate::macros::dbg_internal!( - ($($piece,)* "[{file}:{line}:{column}] {} = {:#?}\n") - ($($processed => $bound,)* $val => tmp) - ($($rest),*) - ) - }, + }; + ($($val:expr),+ $(,)?) => { + ($($crate::dbg!($val)),+,) + }; } #[doc(hidden)] diff --git a/std/src/macros/tests.rs b/std/src/macros/tests.rs index db2be925ff30a..1ad4cf8c4c039 100644 --- a/std/src/macros/tests.rs +++ b/std/src/macros/tests.rs @@ -1,5 +1,7 @@ // ignore-tidy-dbg +use core::fmt::Debug; + /// Test for : /// `dbg!` shouldn't drop arguments' temporaries. #[test] @@ -11,3 +13,55 @@ fn no_dropping_temps() { *dbg!(0, &temp()).1; *dbg!(0, &temp(), 2).1; } + +/// Test for : +/// `dbg!` shouldn't create a temporary that lives past its invocation. +#[test] +fn no_leaking_internal_temps_from_dbg() { + #[derive(Debug)] + struct Foo; + + #[derive(Debug)] + struct Bar<'a>(#[allow(unused)] &'a Foo); + impl Drop for Bar<'_> { + fn drop(&mut self) {} + } + + let foo = Foo; + let bar = Bar(&foo); + // If `dbg!` creates a `(Bar<'_>,)` temporary that lasts past its expansion, this will fail + // to compile, because it will be dropped after `foo`, which it borrows from. The tuple + // mimics the drop order of block tail expressions before Rust 2024: first the result of `dbg!` + // is dropped, then `foo`, then any temporaries left over from `dbg!` are dropped, if present. + (drop(dbg!(bar)), drop(foo)); +} + +/// Test for : +/// `dbg!` shouldn't create a temporary that borrowck thinks can live past its invocation on a false +/// unwind path. +#[test] +fn no_leaking_internal_temps_from_dbg_even_on_false_unwind() { + #[derive(Debug)] + struct Foo; + impl Drop for Foo { + fn drop(&mut self) {} + } + + #[derive(Debug)] + struct Bar<'a>(#[allow(unused)] &'a Foo); + impl Drop for Bar<'_> { + fn drop(&mut self) {} + } + + { + let foo = Foo; + let bar = Bar(&foo); + // The temporaries of this `super let`'s scrutinee will outlive `bar` and `foo`, emulating + // the drop order of block tail expressions before Rust 2024. If borrowck thinks that a + // panic from moving `bar` is possible and that a `Bar<'_>`-containing temporary lives past + // the end of the block because of that, this will fail to compile. Because `Foo` implements + // `Drop`, it's an error for `foo` to be dropped before such a temporary when unwinding; + // otherwise, `foo` would just live to the end of the stack frame when unwinding. + super let _ = drop(dbg!(bar)); + } +} diff --git a/std/src/net/socket_addr.rs b/std/src/net/socket_addr.rs index 8214ad381f1f7..cae14e34e73e7 100644 --- a/std/src/net/socket_addr.rs +++ b/std/src/net/socket_addr.rs @@ -189,11 +189,6 @@ impl ToSocketAddrs for (Ipv6Addr, u16) { } } -fn lookup_host(host: &str, port: u16) -> io::Result> { - let addrs = crate::sys::net::lookup_host(host, port)?; - Ok(Vec::from_iter(addrs).into_iter()) -} - #[stable(feature = "rust1", since = "1.0.0")] impl ToSocketAddrs for (&str, u16) { type Iter = vec::IntoIter; @@ -207,7 +202,7 @@ impl ToSocketAddrs for (&str, u16) { } // Otherwise, make the system look it up. - lookup_host(host, port) + crate::sys::net::lookup_host(host, port).map(|addrs| Vec::from_iter(addrs).into_iter()) } } @@ -229,16 +224,8 @@ impl ToSocketAddrs for str { return Ok(vec![addr].into_iter()); } - // Otherwise, split the string by ':' and convert the second part to u16... - let Some((host, port_str)) = self.rsplit_once(':') else { - return Err(io::const_error!(io::ErrorKind::InvalidInput, "invalid socket address")); - }; - let Ok(port) = port_str.parse::() else { - return Err(io::const_error!(io::ErrorKind::InvalidInput, "invalid port value")); - }; - - // ... and make the system look up the host. - lookup_host(host, port) + // Otherwise, make the system look it up. + crate::sys::net::lookup_host_string(self).map(|addrs| Vec::from_iter(addrs).into_iter()) } } diff --git a/std/src/net/tcp.rs b/std/src/net/tcp.rs index dac568e419f3f..6001869dbf284 100644 --- a/std/src/net/tcp.rs +++ b/std/src/net/tcp.rs @@ -474,6 +474,57 @@ impl TcpStream { self.0.linger() } + /// Sets the value of the `SO_KEEPALIVE` option on this socket. + /// + /// If set to `true`, the operating system will periodically send keepalive + /// probes on an idle connection to verify that the remote peer is still + /// reachable. If the peer fails to respond after a system-determined number + /// of probes, the connection is considered broken and subsequent I/O calls + /// will return an error. + /// + /// This is useful for detecting dead peers on long-lived connections where + /// no application-level traffic is exchanged, such as database or SSH + /// connections. + /// + /// The timing and frequency of keepalive probes are controlled by + /// system-level settings and are not configured by this method alone. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(tcp_keepalive)] + /// + /// use std::net::TcpStream; + /// + /// let stream = TcpStream::connect("127.0.0.1:8080") + /// .expect("Couldn't connect to the server..."); + /// stream.set_keepalive(true).expect("set_keepalive call failed"); + #[unstable(feature = "tcp_keepalive", issue = "155889")] + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + self.0.set_keepalive(keepalive) + } + + /// Gets the value of the `SO_KEEPALIVE` option on this socket. + /// + /// For more information about this option, see [`TcpStream::set_keepalive`]. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(tcp_keepalive)] + /// + /// use std::net::TcpStream; + /// + /// let stream = TcpStream::connect("127.0.0.1:8080") + /// .expect("Couldn't connect to the server..."); + /// stream.set_keepalive(true).expect("set_keepalive call failed"); + /// assert_eq!(stream.keepalive().unwrap_or(false), true); + /// ``` + #[unstable(feature = "tcp_keepalive", issue = "155889")] + pub fn keepalive(&self) -> io::Result { + self.0.keepalive() + } + /// Sets the value of the `TCP_NODELAY` option on this socket. /// /// If set, this option disables the Nagle algorithm. This means that @@ -582,8 +633,8 @@ impl TcpStream { /// to be retried, an error with kind [`io::ErrorKind::WouldBlock`] is /// returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples @@ -988,8 +1039,8 @@ impl TcpListener { /// IO operation could not be completed and needs to be retried, an error /// with kind [`io::ErrorKind::WouldBlock`] is returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples diff --git a/std/src/net/tcp/tests.rs b/std/src/net/tcp/tests.rs index e4a30b80e3df4..8a3a7ee7c5cba 100644 --- a/std/src/net/tcp/tests.rs +++ b/std/src/net/tcp/tests.rs @@ -1,17 +1,14 @@ +use rand::Rng; + use crate::io::prelude::*; use crate::io::{BorrowedBuf, ErrorKind, IoSlice, IoSliceMut}; use crate::mem::MaybeUninit; -use crate::net::test::{next_test_ip4, next_test_ip6}; +use crate::net::test::{LOCALHOST_IP4, LOCALHOST_IP6}; use crate::net::*; use crate::sync::mpsc::channel; use crate::time::{Duration, Instant}; use crate::{fmt, thread}; -fn each_ip(f: &mut dyn FnMut(SocketAddr)) { - f(next_test_ip4()); - f(next_test_ip6()); -} - macro_rules! t { ($e:expr) => { match $e { @@ -21,6 +18,11 @@ macro_rules! t { }; } +fn each_ip(f: &mut dyn FnMut(TcpListener)) { + f(t!(TcpListener::bind(LOCALHOST_IP4))); + f(t!(TcpListener::bind(LOCALHOST_IP6))); +} + #[test] fn bind_error() { match TcpListener::bind("1.1.1.1:9999") { @@ -46,10 +48,18 @@ fn connect_error() { } } +/// Regression test for `Duration::MAX` timeout issue +/// (https://github.com/rust-lang/rust/issues/112405). #[test] #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 fn connect_timeout_error() { - let socket_addr = next_test_ip4(); + // Pick a random port, but not in the range usually used by the OS's automatic port assignment + // so we cannot conflict with the other tests. + let mut rng = crate::test_helpers::test_rng(); + let port = rng.random_range((16 * 1024)..(48 * 1024)); + let socket_addr = SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(127, 0, 0, 1), port)); + + // Ensure we error immediately rather than timing out. let result = TcpStream::connect_timeout(&socket_addr, Duration::MAX); assert!(!matches!(result, Err(e) if e.kind() == ErrorKind::TimedOut)); @@ -60,11 +70,11 @@ fn connect_timeout_error() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn listen_localhost() { - let socket_addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&socket_addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let addr = t!(listener.local_addr()); let _t = thread::spawn(move || { - let mut stream = t!(TcpStream::connect(&("localhost", socket_addr.port()))); + let mut stream = t!(TcpStream::connect(addr)); t!(stream.write(&[144])); }); @@ -77,15 +87,11 @@ fn listen_localhost() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn connect_loopback() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { - let host = match addr { - SocketAddr::V4(..) => "127.0.0.1", - SocketAddr::V6(..) => "::1", - }; - let mut stream = t!(TcpStream::connect(&(host, addr.port()))); + let mut stream = t!(TcpStream::connect(addr)); t!(stream.write(&[66])); }); @@ -99,8 +105,8 @@ fn connect_loopback() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn smoke_test() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let (tx, rx) = channel(); let _t = thread::spawn(move || { @@ -120,8 +126,8 @@ fn smoke_test() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn read_eof() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { let _stream = t!(TcpStream::connect(&addr)); @@ -140,8 +146,8 @@ fn read_eof() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn write_close() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let (tx, rx) = channel(); let _t = thread::spawn(move || { @@ -169,9 +175,9 @@ fn write_close() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn multiple_connect_serial() { - each_ip(&mut |addr| { + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let max = 10; - let acceptor = t!(TcpListener::bind(&addr)); let _t = thread::spawn(move || { for _ in 0..max { @@ -193,8 +199,8 @@ fn multiple_connect_serial() { #[cfg_attr(target_os = "wasi", ignore)] // no threads fn multiple_connect_interleaved_greedy_schedule() { const MAX: usize = 10; - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { let acceptor = acceptor; @@ -231,8 +237,8 @@ fn multiple_connect_interleaved_greedy_schedule() { #[cfg_attr(target_os = "wasi", ignore)] // no threads fn multiple_connect_interleaved_lazy_schedule() { const MAX: usize = 10; - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { for stream in acceptor.incoming().take(MAX) { @@ -266,25 +272,25 @@ fn multiple_connect_interleaved_lazy_schedule() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn socket_and_peer_name() { - each_ip(&mut |addr| { - let listener = t!(TcpListener::bind(&addr)); - let so_name = t!(listener.local_addr()); - assert_eq!(addr, so_name); - let _t = thread::spawn(move || { - t!(listener.accept()); - }); + each_ip(&mut |listener| { + let addr = t!(listener.local_addr()); + let other_stream = thread::spawn(move || t!(listener.accept())); let stream = t!(TcpStream::connect(&addr)); assert_eq!(addr, t!(stream.peer_addr())); + let (other_stream, other_peer) = other_stream.join().unwrap(); + assert_eq!(addr, t!(other_stream.local_addr())); + assert_eq!(other_peer, t!(other_stream.peer_addr())); + assert_eq!(other_peer, t!(stream.local_addr())); }) } #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn partial_read() { - each_ip(&mut |addr| { + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); let (tx, rx) = channel(); - let srv = t!(TcpListener::bind(&addr)); let _t = thread::spawn(move || { let mut cl = t!(srv.accept()).0; cl.write(&[10]).unwrap(); @@ -304,8 +310,8 @@ fn partial_read() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn read_buf() { - each_ip(&mut |addr| { - let srv = t!(TcpListener::bind(&addr)); + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); let t = thread::spawn(move || { let mut s = t!(TcpStream::connect(&addr)); s.write_all(&[1, 2, 3, 4]).unwrap(); @@ -317,7 +323,7 @@ fn read_buf() { t!(s.read_buf(buf.unfilled())); assert_eq!(buf.filled(), &[1, 2, 3, 4]); // TcpStream::read_buf should omit buffer initialization. - assert_eq!(buf.init_len(), 4); + assert!(!buf.is_init()); t.join().ok().expect("thread panicked"); }) @@ -325,8 +331,8 @@ fn read_buf() { #[test] fn read_vectored() { - each_ip(&mut |addr| { - let srv = t!(TcpListener::bind(&addr)); + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); let mut s1 = t!(TcpStream::connect(&addr)); let mut s2 = t!(srv.accept()).0; @@ -350,8 +356,8 @@ fn read_vectored() { #[test] fn write_vectored() { - each_ip(&mut |addr| { - let srv = t!(TcpListener::bind(&addr)); + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); let mut s1 = t!(TcpStream::connect(&addr)); let mut s2 = t!(srv.accept()).0; @@ -374,8 +380,8 @@ fn write_vectored() { #[test] fn double_bind() { - each_ip(&mut |addr| { - let listener1 = t!(TcpListener::bind(&addr)); + each_ip(&mut |listener1| { + let addr = t!(listener1.local_addr()); match TcpListener::bind(&addr) { Ok(listener2) => panic!( "This system (perhaps due to options set by TcpListener::bind) \ @@ -399,8 +405,8 @@ fn double_bind() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn tcp_clone_smoke() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { let mut s = t!(TcpStream::connect(&addr)); @@ -431,8 +437,8 @@ fn tcp_clone_smoke() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn tcp_clone_two_read() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let (tx1, rx) = channel(); let tx2 = tx1.clone(); @@ -466,8 +472,8 @@ fn tcp_clone_two_read() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn tcp_clone_two_write() { - each_ip(&mut |addr| { - let acceptor = t!(TcpListener::bind(&addr)); + each_ip(&mut |acceptor| { + let addr = t!(acceptor.local_addr()); let _t = thread::spawn(move || { let mut s = t!(TcpStream::connect(&addr)); @@ -496,8 +502,8 @@ fn tcp_clone_two_write() { #[cfg_attr(target_env = "sgx", ignore)] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn shutdown_smoke() { - each_ip(&mut |addr| { - let a = t!(TcpListener::bind(&addr)); + each_ip(&mut |a| { + let addr = t!(a.local_addr()); let _t = thread::spawn(move || { let mut c = t!(a.accept()).0; let mut b = [0]; @@ -519,8 +525,8 @@ fn shutdown_smoke() { #[cfg_attr(target_env = "sgx", ignore)] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn close_readwrite_smoke() { - each_ip(&mut |addr| { - let a = t!(TcpListener::bind(&addr)); + each_ip(&mut |a| { + let addr = t!(a.local_addr()); let (tx, rx) = channel::<()>(); let _t = thread::spawn(move || { let _s = t!(a.accept()); @@ -562,8 +568,8 @@ fn close_readwrite_smoke() { #[cfg_attr(windows, ignore)] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn close_read_wakes_up() { - each_ip(&mut |addr| { - let listener = t!(TcpListener::bind(&addr)); + each_ip(&mut |listener| { + let addr = t!(listener.local_addr()); let _t = thread::spawn(move || { let (stream, _) = t!(listener.accept()); stream @@ -590,8 +596,8 @@ fn close_read_wakes_up() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn clone_while_reading() { - each_ip(&mut |addr| { - let accept = t!(TcpListener::bind(&addr)); + each_ip(&mut |accept| { + let addr = t!(accept.local_addr()); // Enqueue a thread to write to a socket let (tx, rx) = channel(); @@ -631,8 +637,8 @@ fn clone_while_reading() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn clone_accept_smoke() { - each_ip(&mut |addr| { - let a = t!(TcpListener::bind(&addr)); + each_ip(&mut |a| { + let addr = t!(a.local_addr()); let a2 = t!(a.try_clone()); let _t = thread::spawn(move || { @@ -650,8 +656,8 @@ fn clone_accept_smoke() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn clone_accept_concurrent() { - each_ip(&mut |addr| { - let a = t!(TcpListener::bind(&addr)); + each_ip(&mut |a| { + let addr = t!(a.local_addr()); let a2 = t!(a.try_clone()); let (tx, rx) = channel(); @@ -701,9 +707,9 @@ fn debug() { } let inner_name = if cfg!(windows) { "socket" } else { "fd" }; - let socket_addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&socket_addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let socket_addr = t!(listener.local_addr()); let compare = format!( "TcpListener {{ addr: {:?}, {}: {:?} }}", render_socket_addr(&socket_addr), @@ -734,10 +740,9 @@ fn debug() { #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported #[test] fn timeouts() { - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); let dur = Duration::new(15410, 0); assert_eq!(None, t!(stream.read_timeout())); @@ -762,10 +767,9 @@ fn timeouts() { #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported fn test_read_timeout() { - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let mut stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let mut stream = t!(TcpStream::connect(t!(listener.local_addr()))); t!(stream.set_read_timeout(Some(Duration::from_millis(1000)))); let mut buf = [0; 10]; @@ -784,10 +788,9 @@ fn test_read_timeout() { #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported fn test_read_with_timeout() { - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let mut stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let mut stream = t!(TcpStream::connect(t!(listener.local_addr()))); t!(stream.set_read_timeout(Some(Duration::from_millis(1000)))); let mut other_end = t!(listener.accept()).0; @@ -812,10 +815,8 @@ fn test_read_with_timeout() { // when passed zero Durations #[test] fn test_timeout_zero_duration() { - let addr = next_test_ip4(); - - let listener = t!(TcpListener::bind(&addr)); - let stream = t!(TcpStream::connect(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); let result = stream.set_write_timeout(Some(Duration::new(0, 0))); let err = result.unwrap_err(); @@ -832,10 +833,9 @@ fn test_timeout_zero_duration() { #[cfg_attr(target_env = "sgx", ignore)] #[cfg_attr(target_os = "wasi", ignore)] // linger not supported fn linger() { - let addr = next_test_ip4(); - let _listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); assert_eq!(None, t!(stream.linger())); t!(stream.set_linger(Some(Duration::from_secs(1)))); @@ -844,13 +844,26 @@ fn linger() { assert_eq!(None, t!(stream.linger())); } +#[test] +#[cfg_attr(target_env = "sgx", ignore)] +#[cfg_attr(target_os = "wasi", ignore)] +fn keepalive() { + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); + + assert_eq!(false, t!(stream.keepalive())); + t!(stream.set_keepalive(true)); + assert_eq!(true, t!(stream.keepalive())); + t!(stream.set_keepalive(false)); + assert_eq!(false, t!(stream.keepalive())); +} + #[test] #[cfg_attr(target_env = "sgx", ignore)] fn nodelay() { - let addr = next_test_ip4(); - let _listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); - let stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); assert_eq!(false, t!(stream.nodelay())); t!(stream.set_nodelay(true)); @@ -864,13 +877,12 @@ fn nodelay() { fn ttl() { let ttl = 100; - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); t!(listener.set_ttl(ttl)); assert_eq!(ttl, t!(listener.ttl())); - let stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let stream = t!(TcpStream::connect(t!(listener.local_addr()))); t!(stream.set_ttl(ttl)); assert_eq!(ttl, t!(stream.ttl())); @@ -879,13 +891,12 @@ fn ttl() { #[test] #[cfg_attr(target_env = "sgx", ignore)] fn set_nonblocking() { - let addr = next_test_ip4(); - let listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); t!(listener.set_nonblocking(true)); t!(listener.set_nonblocking(false)); - let mut stream = t!(TcpStream::connect(&("localhost", addr.port()))); + let mut stream = t!(TcpStream::connect(t!(listener.local_addr()))); t!(stream.set_nonblocking(false)); t!(stream.set_nonblocking(true)); @@ -902,10 +913,11 @@ fn set_nonblocking() { #[cfg_attr(target_env = "sgx", ignore)] // FIXME: https://github.com/fortanix/rust-sgx/issues/31 #[cfg_attr(target_os = "wasi", ignore)] // no threads fn peek() { - each_ip(&mut |addr| { + each_ip(&mut |srv| { + let addr = t!(srv.local_addr()); + let (txdone, rxdone) = channel(); - let srv = t!(TcpListener::bind(&addr)); let _t = thread::spawn(move || { let mut cl = t!(srv.accept()).0; cl.write(&[1, 3, 3, 7]).unwrap(); diff --git a/std/src/net/test.rs b/std/src/net/test.rs index df48b2f2420c3..5002bb5c8e083 100644 --- a/std/src/net/test.rs +++ b/std/src/net/test.rs @@ -4,18 +4,12 @@ use crate::env; use crate::net::{Ipv4Addr, Ipv6Addr, SocketAddr, SocketAddrV4, SocketAddrV6, ToSocketAddrs}; use crate::sync::atomic::{AtomicUsize, Ordering}; -static PORT: AtomicUsize = AtomicUsize::new(0); -const BASE_PORT: u16 = 19600; - -pub fn next_test_ip4() -> SocketAddr { - let port = PORT.fetch_add(1, Ordering::Relaxed) as u16 + BASE_PORT; - SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(127, 0, 0, 1), port)) -} - -pub fn next_test_ip6() -> SocketAddr { - let port = PORT.fetch_add(1, Ordering::Relaxed) as u16 + BASE_PORT; - SocketAddr::V6(SocketAddrV6::new(Ipv6Addr::new(0, 0, 0, 0, 0, 0, 0, 1), port, 0, 0)) -} +/// A localhost address whose port will be picked automatically by the OS. +pub const LOCALHOST_IP4: SocketAddr = + SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(127, 0, 0, 1), 0)); +/// A localhost address whose port will be picked automatically by the OS. +pub const LOCALHOST_IP6: SocketAddr = + SocketAddr::V6(SocketAddrV6::new(Ipv6Addr::new(0, 0, 0, 0, 0, 0, 0, 1), 0, 0, 0)); pub fn sa4(a: Ipv4Addr, p: u16) -> SocketAddr { SocketAddr::V4(SocketAddrV4::new(a, p)) diff --git a/std/src/net/udp.rs b/std/src/net/udp.rs index 136803ab16f1f..cd925b9bdfdf8 100644 --- a/std/src/net/udp.rs +++ b/std/src/net/udp.rs @@ -129,6 +129,10 @@ impl UdpSocket { /// hold the message bytes. If a message is too long to fit in the supplied buffer, /// excess bytes may be discarded. /// + /// Refer to the platform-specific documentation on this function; it is considered + /// correct for its behavior to differ from [`UdpSocket::recv`] if the underlying system + /// call does so. + /// /// # Examples /// /// ```no_run @@ -711,6 +715,10 @@ impl UdpSocket { /// [`UdpSocket::connect`] will connect this socket to a remote address. This /// method will fail if the socket is not connected. /// + /// Refer to the platform-specific documentation on this function; it is considered + /// correct for its behavior to differ from [`UdpSocket::recv_from`] if the underlying + /// system call does so. + /// /// # Examples /// /// ```no_run @@ -778,8 +786,8 @@ impl UdpSocket { /// and needs to be retried, an error with kind /// [`io::ErrorKind::WouldBlock`] is returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples diff --git a/std/src/net/udp/tests.rs b/std/src/net/udp/tests.rs index 0638b36c54f9d..ede0240fbda57 100644 --- a/std/src/net/udp/tests.rs +++ b/std/src/net/udp/tests.rs @@ -1,15 +1,10 @@ use crate::io::ErrorKind; -use crate::net::test::{compare_ignore_zoneid, next_test_ip4, next_test_ip6}; +use crate::net::test::{LOCALHOST_IP4, LOCALHOST_IP6, compare_ignore_zoneid}; use crate::net::*; use crate::sync::mpsc::channel; use crate::thread; use crate::time::{Duration, Instant}; -fn each_ip(f: &mut dyn FnMut(SocketAddr, SocketAddr)) { - f(next_test_ip4(), next_test_ip4()); - f(next_test_ip6(), next_test_ip6()); -} - macro_rules! t { ($e:expr) => { match $e { @@ -19,6 +14,11 @@ macro_rules! t { }; } +fn each_ip(f: &mut dyn FnMut(UdpSocket, UdpSocket)) { + f(t!(UdpSocket::bind(LOCALHOST_IP4)), t!(UdpSocket::bind(LOCALHOST_IP4))); + f(t!(UdpSocket::bind(LOCALHOST_IP6)), t!(UdpSocket::bind(LOCALHOST_IP6))); +} + #[test] fn bind_error() { match UdpSocket::bind("1.1.1.1:9999") { @@ -30,18 +30,19 @@ fn bind_error() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn socket_smoke_test_ip4() { - each_ip(&mut |server_ip, client_ip| { + each_ip(&mut |server, client| { + let server_ip = t!(server.local_addr()); + let client_ip = t!(client.local_addr()); + let (tx1, rx1) = channel(); let (tx2, rx2) = channel(); let _t = thread::spawn(move || { - let client = t!(UdpSocket::bind(&client_ip)); rx1.recv().unwrap(); t!(client.send_to(&[99], &server_ip)); tx2.send(()).unwrap(); }); - let server = t!(UdpSocket::bind(&server_ip)); tx1.send(()).unwrap(); let mut buf = [0]; let (nread, src) = t!(server.recv_from(&mut buf)); @@ -53,29 +54,28 @@ fn socket_smoke_test_ip4() { } #[test] -fn socket_name() { - each_ip(&mut |addr, _| { - let server = t!(UdpSocket::bind(&addr)); - assert_eq!(addr, t!(server.local_addr())); - }) -} +fn socket_and_peer_name() { + each_ip(&mut |sock1, sock2| { + let addr1 = t!(sock1.local_addr()); + let addr2 = t!(sock2.local_addr()); -#[test] -fn socket_peer() { - each_ip(&mut |addr1, addr2| { - let server = t!(UdpSocket::bind(&addr1)); - assert_eq!(server.peer_addr().unwrap_err().kind(), ErrorKind::NotConnected); - t!(server.connect(&addr2)); - assert_eq!(addr2, t!(server.peer_addr())); + assert_eq!(sock1.peer_addr().unwrap_err().kind(), ErrorKind::NotConnected); + assert!(addr1.ip() == LOCALHOST_IP4.ip() || addr1.ip() == LOCALHOST_IP6.ip()); + + t!(sock1.connect(addr2)); + t!(sock2.connect(addr1)); + + assert_eq!(addr2, t!(sock1.peer_addr())); + assert_eq!(addr1, t!(sock2.peer_addr())); }) } #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn udp_clone_smoke() { - each_ip(&mut |addr1, addr2| { - let sock1 = t!(UdpSocket::bind(&addr1)); - let sock2 = t!(UdpSocket::bind(&addr2)); + each_ip(&mut |sock1, sock2| { + let addr1 = t!(sock1.local_addr()); + let addr2 = t!(sock2.local_addr()); let _t = thread::spawn(move || { let mut buf = [0, 0]; @@ -107,9 +107,9 @@ fn udp_clone_smoke() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn udp_clone_two_read() { - each_ip(&mut |addr1, addr2| { - let sock1 = t!(UdpSocket::bind(&addr1)); - let sock2 = t!(UdpSocket::bind(&addr2)); + each_ip(&mut |sock1, sock2| { + let addr1 = t!(sock1.local_addr()); + let (tx1, rx) = channel(); let tx2 = tx1.clone(); @@ -140,9 +140,8 @@ fn udp_clone_two_read() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // no threads fn udp_clone_two_write() { - each_ip(&mut |addr1, addr2| { - let sock1 = t!(UdpSocket::bind(&addr1)); - let sock2 = t!(UdpSocket::bind(&addr2)); + each_ip(&mut |sock1, sock2| { + let addr2 = t!(sock2.local_addr()); let (tx, rx) = channel(); let (serv_tx, serv_rx) = channel(); @@ -177,9 +176,9 @@ fn udp_clone_two_write() { #[test] fn debug() { let name = if cfg!(windows) { "socket" } else { "fd" }; - let socket_addr = next_test_ip4(); - let udpsock = t!(UdpSocket::bind(&socket_addr)); + let udpsock = t!(UdpSocket::bind(LOCALHOST_IP4)); + let socket_addr = t!(udpsock.local_addr()); let udpsock_inner = udpsock.0.socket().as_raw(); let compare = format!("UdpSocket {{ addr: {socket_addr:?}, {name}: {udpsock_inner:?} }}"); assert_eq!(format!("{udpsock:?}"), compare); @@ -195,9 +194,7 @@ fn debug() { #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported #[test] fn timeouts() { - let addr = next_test_ip4(); - - let stream = t!(UdpSocket::bind(&addr)); + let stream = t!(UdpSocket::bind(LOCALHOST_IP4)); let dur = Duration::new(15410, 0); assert_eq!(None, t!(stream.read_timeout())); @@ -220,9 +217,7 @@ fn timeouts() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported fn test_read_timeout() { - let addr = next_test_ip4(); - - let stream = t!(UdpSocket::bind(&addr)); + let stream = t!(UdpSocket::bind(LOCALHOST_IP4)); t!(stream.set_read_timeout(Some(Duration::from_millis(1000)))); let mut buf = [0; 10]; @@ -245,9 +240,8 @@ fn test_read_timeout() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // timeout not supported fn test_read_with_timeout() { - let addr = next_test_ip4(); - - let stream = t!(UdpSocket::bind(&addr)); + let stream = t!(UdpSocket::bind(LOCALHOST_IP4)); + let addr = t!(stream.local_addr()); t!(stream.set_read_timeout(Some(Duration::from_millis(1000)))); t!(stream.send_to(b"hello world", &addr)); @@ -275,9 +269,7 @@ fn test_read_with_timeout() { // when passed zero Durations #[test] fn test_timeout_zero_duration() { - let addr = next_test_ip4(); - - let socket = t!(UdpSocket::bind(&addr)); + let socket = t!(UdpSocket::bind(LOCALHOST_IP4)); let result = socket.set_write_timeout(Some(Duration::new(0, 0))); let err = result.unwrap_err(); @@ -290,9 +282,8 @@ fn test_timeout_zero_duration() { #[test] fn connect_send_recv() { - let addr = next_test_ip4(); - - let socket = t!(UdpSocket::bind(&addr)); + let socket = t!(UdpSocket::bind(LOCALHOST_IP4)); + let addr = t!(socket.local_addr()); t!(socket.connect(addr)); t!(socket.send(b"hello world")); @@ -305,8 +296,8 @@ fn connect_send_recv() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // peek not supported fn connect_send_peek_recv() { - each_ip(&mut |addr, _| { - let socket = t!(UdpSocket::bind(&addr)); + each_ip(&mut |socket, _| { + let addr = t!(socket.local_addr()); t!(socket.connect(addr)); t!(socket.send(b"hello world")); @@ -328,8 +319,8 @@ fn connect_send_peek_recv() { #[test] #[cfg_attr(target_os = "wasi", ignore)] // peek_from not supported fn peek_from() { - each_ip(&mut |addr, _| { - let socket = t!(UdpSocket::bind(&addr)); + each_ip(&mut |socket, _| { + let addr = t!(socket.local_addr()); t!(socket.send_to(b"hello world", &addr)); for _ in 1..3 { @@ -350,9 +341,7 @@ fn peek_from() { fn ttl() { let ttl = 100; - let addr = next_test_ip4(); - - let stream = t!(UdpSocket::bind(&addr)); + let stream = t!(UdpSocket::bind(LOCALHOST_IP4)); t!(stream.set_ttl(ttl)); assert_eq!(ttl, t!(stream.ttl())); @@ -360,8 +349,8 @@ fn ttl() { #[test] fn set_nonblocking() { - each_ip(&mut |addr, _| { - let socket = t!(UdpSocket::bind(&addr)); + each_ip(&mut |socket, _| { + let addr = t!(socket.local_addr()); t!(socket.set_nonblocking(true)); t!(socket.set_nonblocking(false)); diff --git a/std/src/num/f128.rs b/std/src/num/f128.rs index 2c8898a6aa86a..aaf9c1b54efb8 100644 --- a/std/src/num/f128.rs +++ b/std/src/num/f128.rs @@ -34,7 +34,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0_f128; @@ -65,7 +64,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let one = 1.0f128; @@ -97,7 +95,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let f = 2.0f128; @@ -129,7 +126,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let one = 1.0f128; @@ -146,7 +142,6 @@ impl f128 { /// Non-positive values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!(0_f128.ln(), f128::NEG_INFINITY); @@ -178,7 +173,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let five = 5.0f128; @@ -193,7 +187,6 @@ impl f128 { /// Non-positive values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!(0_f128.log(10.0), f128::NEG_INFINITY); @@ -221,7 +214,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let two = 2.0f128; @@ -236,7 +228,6 @@ impl f128 { /// Non-positive values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!(0_f128.log2(), f128::NEG_INFINITY); @@ -264,7 +255,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let ten = 10.0f128; @@ -279,7 +269,6 @@ impl f128 { /// Non-positive values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!(0_f128.log10(), f128::NEG_INFINITY); @@ -309,7 +298,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 8.0f128; @@ -346,7 +334,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0f128; @@ -377,7 +364,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = std::f128::consts::FRAC_PI_2; @@ -406,7 +392,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0 * std::f128::consts::PI; @@ -438,7 +423,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = std::f128::consts::FRAC_PI_4; @@ -471,7 +455,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let f = std::f128::consts::FRAC_PI_4; @@ -507,7 +490,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let f = std::f128::consts::FRAC_PI_4; @@ -542,7 +524,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let f = 1.0f128; @@ -583,7 +564,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// // Positive angles measured counter-clockwise @@ -626,7 +606,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = std::f128::consts::FRAC_PI_4; @@ -643,6 +622,7 @@ impl f128 { #[doc(alias = "sincos")] #[rustc_allow_incoherent_impl] #[unstable(feature = "f128", issue = "116909")] + #[must_use = "this returns the result of the operation, without modifying the original"] pub fn sin_cos(self) -> (f128, f128) { (self.sin(), self.cos()) } @@ -662,7 +642,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 1e-8_f128; @@ -699,7 +678,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 1e-8_f128; @@ -715,7 +693,6 @@ impl f128 { /// Out-of-range values: /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// assert_eq!((-1.0_f128).ln_1p(), f128::NEG_INFINITY); @@ -745,7 +722,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let e = std::f128::consts::E; @@ -781,7 +757,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let e = std::f128::consts::E; @@ -817,7 +792,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let e = std::f128::consts::E; @@ -850,7 +824,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 1.0f128; @@ -867,9 +840,7 @@ impl f128 { #[unstable(feature = "f128", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub fn asinh(self) -> f128 { - let ax = self.abs(); - let ix = 1.0 / ax; - (ax + (ax / (Self::hypot(1.0, ix) + ix))).ln_1p().copysign(self) + cmath::asinhf128(self) } /// Inverse hyperbolic cosine function. @@ -883,7 +854,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 1.0f128; @@ -900,11 +870,7 @@ impl f128 { #[unstable(feature = "f128", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub fn acosh(self) -> f128 { - if self < 1.0 { - Self::NAN - } else { - (self + ((self - 1.0).sqrt() * (self + 1.0).sqrt())).ln() - } + cmath::acoshf128(self) } /// Inverse hyperbolic tangent function. @@ -918,7 +884,6 @@ impl f128 { /// /// ``` /// #![feature(f128)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = std::f128::consts::FRAC_PI_6; @@ -953,7 +918,6 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_gamma)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 5.0f128; @@ -989,7 +953,6 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_gamma)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// let x = 2.0f128; @@ -1025,7 +988,6 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_erf)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// /// The error function relates what percent of a normal distribution lies /// /// within `x` standard deviations (scaled by `1/sqrt(2)`). @@ -1065,7 +1027,6 @@ impl f128 { /// ``` /// #![feature(f128)] /// #![feature(float_erf)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f128_math)] { /// let x: f128 = 0.123; /// diff --git a/std/src/num/f16.rs b/std/src/num/f16.rs index 7ca266c8a5f60..4a7493fb5a5ed 100644 --- a/std/src/num/f16.rs +++ b/std/src/num/f16.rs @@ -34,12 +34,11 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0_f16; /// let abs_difference = (x.powf(2.0) - (x * x)).abs(); - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-1); /// /// assert_eq!(f16::powf(1.0, f16::NAN), 1.0); /// assert_eq!(f16::powf(f16::NAN, 0.0), 1.0); @@ -65,7 +64,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let one = 1.0f16; @@ -75,7 +73,7 @@ impl f16 { /// // ln(e) - 1 == 0 /// let abs_difference = (e.ln() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -97,7 +95,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let f = 2.0f16; @@ -105,7 +102,7 @@ impl f16 { /// // 2^2 - 4 == 0 /// let abs_difference = (f.exp2() - 4.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-1); /// # } /// ``` #[inline] @@ -129,7 +126,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let one = 1.0f16; @@ -139,14 +135,13 @@ impl f16 { /// // ln(e) - 1 == 0 /// let abs_difference = (e.ln() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` /// /// Non-positive values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!(0_f16.ln(), f16::NEG_INFINITY); @@ -178,7 +173,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let five = 5.0f16; @@ -186,14 +180,13 @@ impl f16 { /// // log5(5) - 1 == 0 /// let abs_difference = (five.log(5.0) - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` /// /// Non-positive values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!(0_f16.log(10.0), f16::NEG_INFINITY); @@ -221,7 +214,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let two = 2.0f16; @@ -229,14 +221,13 @@ impl f16 { /// // log2(2) - 1 == 0 /// let abs_difference = (two.log2() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` /// /// Non-positive values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!(0_f16.log2(), f16::NEG_INFINITY); @@ -264,7 +255,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let ten = 10.0f16; @@ -272,14 +262,13 @@ impl f16 { /// // log10(10) - 1 == 0 /// let abs_difference = (ten.log10() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` /// /// Non-positive values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!(0_f16.log10(), f16::NEG_INFINITY); @@ -311,7 +300,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0f16; @@ -320,7 +308,7 @@ impl f16 { /// // sqrt(x^2 + y^2) /// let abs_difference = (x.hypot(y) - (x.powi(2) + y.powi(2)).sqrt()).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -342,14 +330,13 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = std::f16::consts::FRAC_PI_2; /// /// let abs_difference = (x.sin() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -371,14 +358,13 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0 * std::f16::consts::PI; /// /// let abs_difference = (x.cos() - 1.0).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -403,7 +389,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = std::f16::consts::FRAC_PI_4; @@ -436,7 +421,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let f = std::f16::consts::FRAC_PI_4; @@ -444,7 +428,7 @@ impl f16 { /// // asin(sin(pi/2)) /// let abs_difference = (f.sin().asin() - f).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -472,7 +456,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let f = std::f16::consts::FRAC_PI_4; @@ -480,7 +463,7 @@ impl f16 { /// // acos(cos(pi/4)) /// let abs_difference = (f.cos().acos() - std::f16::consts::FRAC_PI_4).abs(); /// - /// assert!(abs_difference <= f16::EPSILON); + /// assert!(abs_difference <= 1e-2); /// # } /// ``` #[inline] @@ -507,7 +490,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let f = 1.0f16; @@ -548,7 +530,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// // Positive angles measured counter-clockwise @@ -591,7 +572,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = std::f16::consts::FRAC_PI_4; @@ -600,14 +580,15 @@ impl f16 { /// let abs_difference_0 = (f.0 - x.sin()).abs(); /// let abs_difference_1 = (f.1 - x.cos()).abs(); /// - /// assert!(abs_difference_0 <= f16::EPSILON); - /// assert!(abs_difference_1 <= f16::EPSILON); + /// assert!(abs_difference_0 <= 1e-2); + /// assert!(abs_difference_1 <= 1e-2); /// # } /// ``` #[inline] #[doc(alias = "sincos")] #[rustc_allow_incoherent_impl] #[unstable(feature = "f16", issue = "116909")] + #[must_use = "this returns the result of the operation, without modifying the original"] pub fn sin_cos(self) -> (f16, f16) { (self.sin(), self.cos()) } @@ -627,7 +608,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 1e-4_f16; @@ -664,7 +644,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 1e-4_f16; @@ -680,7 +659,6 @@ impl f16 { /// Out-of-range values: /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// assert_eq!((-1.0_f16).ln_1p(), f16::NEG_INFINITY); @@ -710,7 +688,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let e = std::f16::consts::E; @@ -746,7 +723,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let e = std::f16::consts::E; @@ -782,7 +758,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let e = std::f16::consts::E; @@ -815,7 +790,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 1.0f16; @@ -832,9 +806,7 @@ impl f16 { #[unstable(feature = "f16", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub fn asinh(self) -> f16 { - let ax = self.abs(); - let ix = 1.0 / ax; - (ax + (ax / (Self::hypot(1.0, ix) + ix))).ln_1p().copysign(self) + cmath::asinhf(self as f32) as f16 } /// Inverse hyperbolic cosine function. @@ -848,7 +820,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 1.0f16; @@ -865,11 +836,7 @@ impl f16 { #[unstable(feature = "f16", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub fn acosh(self) -> f16 { - if self < 1.0 { - Self::NAN - } else { - (self + ((self - 1.0).sqrt() * (self + 1.0).sqrt())).ln() - } + cmath::acoshf(self as f32) as f16 } /// Inverse hyperbolic tangent function. @@ -883,7 +850,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = std::f16::consts::FRAC_PI_6; @@ -917,7 +883,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 5.0f16; @@ -952,7 +917,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// let x = 2.0f16; @@ -987,7 +951,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// The error function relates what percent of a normal distribution lies /// /// within `x` standard deviations (scaled by `1/sqrt(2)`). @@ -1026,7 +989,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// let x: f16 = 0.123; /// diff --git a/std/src/num/f32.rs b/std/src/num/f32.rs index 77e6824784605..3c1778cae6e22 100644 --- a/std/src/num/f32.rs +++ b/std/src/num/f32.rs @@ -26,7 +26,7 @@ use crate::sys::cmath; #[cfg(not(test))] impl f32 { - /// Returns the largest integer less than or equal to `self`. + /// Returns the largest integer that is less than or equal to `self`. /// /// This function always returns the precise result. /// @@ -50,7 +50,7 @@ impl f32 { core::f32::math::floor(self) } - /// Returns the smallest integer greater than or equal to `self`. + /// Returns the smallest integer that is greater than or equal to `self`. /// /// This function always returns the precise result. /// @@ -59,9 +59,11 @@ impl f32 { /// ``` /// let f = 3.01_f32; /// let g = 4.0_f32; + /// let h = -3.01_f32; /// /// assert_eq!(f.ceil(), 4.0); /// assert_eq!(g.ceil(), 4.0); + /// assert_eq!(h.ceil(), -3.0); /// ``` #[doc(alias = "ceiling")] #[rustc_allow_incoherent_impl] @@ -907,6 +909,7 @@ impl f32 { #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] #[inline] + #[must_use = "this returns the result of the operation, without modifying the original"] pub fn sin_cos(self) -> (f32, f32) { (self.sin(), self.cos()) } @@ -1091,9 +1094,7 @@ impl f32 { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn asinh(self) -> f32 { - let ax = self.abs(); - let ix = 1.0 / ax; - (ax + (ax / (Self::hypot(1.0, ix) + ix))).ln_1p().copysign(self) + cmath::asinhf(self) } /// Inverse hyperbolic cosine function. @@ -1119,11 +1120,7 @@ impl f32 { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn acosh(self) -> f32 { - if self < 1.0 { - Self::NAN - } else { - (self + ((self - 1.0).sqrt() * (self + 1.0).sqrt())).ln() - } + cmath::acoshf(self) } /// Inverse hyperbolic tangent function. diff --git a/std/src/num/f64.rs b/std/src/num/f64.rs index e0b9948a924db..af262474f1b0f 100644 --- a/std/src/num/f64.rs +++ b/std/src/num/f64.rs @@ -26,7 +26,7 @@ use crate::sys::cmath; #[cfg(not(test))] impl f64 { - /// Returns the largest integer less than or equal to `self`. + /// Returns the largest integer that is less than or equal to `self`. /// /// This function always returns the precise result. /// @@ -50,7 +50,7 @@ impl f64 { core::f64::math::floor(self) } - /// Returns the smallest integer greater than or equal to `self`. + /// Returns the smallest integer that is greater than or equal to `self`. /// /// This function always returns the precise result. /// @@ -59,9 +59,11 @@ impl f64 { /// ``` /// let f = 3.01_f64; /// let g = 4.0_f64; + /// let h = -3.01_f64; /// /// assert_eq!(f.ceil(), 4.0); /// assert_eq!(g.ceil(), 4.0); + /// assert_eq!(h.ceil(), -3.0); /// ``` #[doc(alias = "ceiling")] #[rustc_allow_incoherent_impl] @@ -907,6 +909,7 @@ impl f64 { #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] #[inline] + #[must_use = "this returns the result of the operation, without modifying the original"] pub fn sin_cos(self) -> (f64, f64) { (self.sin(), self.cos()) } @@ -1091,9 +1094,7 @@ impl f64 { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn asinh(self) -> f64 { - let ax = self.abs(); - let ix = 1.0 / ax; - (ax + (ax / (Self::hypot(1.0, ix) + ix))).ln_1p().copysign(self) + cmath::asinh(self) } /// Inverse hyperbolic cosine function. @@ -1119,11 +1120,7 @@ impl f64 { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn acosh(self) -> f64 { - if self < 1.0 { - Self::NAN - } else { - (self + ((self - 1.0).sqrt() * (self + 1.0).sqrt())).ln() - } + cmath::acosh(self) } /// Inverse hyperbolic tangent function. diff --git a/std/src/os/aix/fs.rs b/std/src/os/aix/fs.rs index 2a940c6b9c97c..36e56f23cc555 100644 --- a/std/src/os/aix/fs.rs +++ b/std/src/os/aix/fs.rs @@ -322,22 +322,22 @@ impl MetadataExt for Metadata { self.as_inner().as_inner().st_size as u64 } fn st_atime(&self) -> i64 { - self.as_inner().as_inner().st_atime.tv_sec as i64 + self.as_inner().as_inner().st_atim.tv_sec as i64 } fn st_atime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_atime.tv_nsec as i64 + self.as_inner().as_inner().st_atim.tv_nsec as i64 } fn st_mtime(&self) -> i64 { - self.as_inner().as_inner().st_mtime.tv_sec as i64 + self.as_inner().as_inner().st_mtim.tv_sec as i64 } fn st_mtime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_mtime.tv_nsec as i64 + self.as_inner().as_inner().st_mtim.tv_nsec as i64 } fn st_ctime(&self) -> i64 { - self.as_inner().as_inner().st_ctime.tv_sec as i64 + self.as_inner().as_inner().st_ctim.tv_sec as i64 } fn st_ctime_nsec(&self) -> i64 { - self.as_inner().as_inner().st_ctime.tv_nsec as i64 + self.as_inner().as_inner().st_ctim.tv_nsec as i64 } fn st_blksize(&self) -> u64 { self.as_inner().as_inner().st_blksize as u64 diff --git a/std/src/os/linux/raw.rs b/std/src/os/linux/raw.rs index 6483f0861139b..6f2da15a98d69 100644 --- a/std/src/os/linux/raw.rs +++ b/std/src/os/linux/raw.rs @@ -31,7 +31,6 @@ pub use self::arch::{blkcnt_t, blksize_t, ino_t, nlink_t, off_t, stat, time_t}; target_arch = "powerpc", target_arch = "sparc", target_arch = "arm", - target_arch = "wasm32" ))] mod arch { use crate::os::raw::{c_long, c_short, c_uint}; @@ -311,7 +310,9 @@ mod arch { } } -#[cfg(any(target_arch = "x86_64", target_arch = "powerpc64"))] +#[cfg(any(target_arch = "x86_64", target_arch = "powerpc64", + // `wasm32-wali-linux-musl` uses ABI similar to x86_64 + target_arch = "wasm32"))] mod arch { use crate::os::raw::{c_int, c_long}; diff --git a/std/src/os/net/linux_ext/tests.rs b/std/src/os/net/linux_ext/tests.rs index 0758b426ccc59..02839ee6a2aad 100644 --- a/std/src/os/net/linux_ext/tests.rs +++ b/std/src/os/net/linux_ext/tests.rs @@ -1,6 +1,6 @@ #[test] fn quickack() { - use crate::net::test::next_test_ip4; + use crate::net::test::LOCALHOST_IP4; use crate::net::{TcpListener, TcpStream}; use crate::os::net::linux_ext::tcp::TcpStreamExt; @@ -13,8 +13,8 @@ fn quickack() { }; } - let addr = next_test_ip4(); - let _listener = t!(TcpListener::bind(&addr)); + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let addr = t!(listener.local_addr()); let stream = t!(TcpStream::connect(&("localhost", addr.port()))); @@ -29,7 +29,7 @@ fn quickack() { #[test] #[cfg(target_os = "linux")] fn deferaccept() { - use crate::net::test::next_test_ip4; + use crate::net::test::LOCALHOST_IP4; use crate::net::{TcpListener, TcpStream}; use crate::os::net::linux_ext::tcp::TcpStreamExt; use crate::time::Duration; @@ -43,10 +43,11 @@ fn deferaccept() { }; } - let addr = next_test_ip4(); let one = Duration::from_secs(1u64); let zero = Duration::from_secs(0u64); - let _listener = t!(TcpListener::bind(&addr)); + + let listener = t!(TcpListener::bind(LOCALHOST_IP4)); + let addr = t!(listener.local_addr()); let stream = t!(TcpStream::connect(&("localhost", addr.port()))); stream.set_deferaccept(one).expect("set_deferaccept failed"); assert_eq!(stream.deferaccept().unwrap(), one); diff --git a/std/src/os/unix/io/tests.rs b/std/src/os/unix/io/tests.rs index fc147730578ac..ce5e7aac5a99d 100644 --- a/std/src/os/unix/io/tests.rs +++ b/std/src/os/unix/io/tests.rs @@ -2,8 +2,7 @@ use crate::os::unix::io::RawFd; #[test] fn test_raw_fd_layout() { - // `OwnedFd` and `BorrowedFd` use `rustc_layout_scalar_valid_range_start` - // and `rustc_layout_scalar_valid_range_end`, with values that depend on + // `OwnedFd` and `BorrowedFd` use pattern types, with ranges that depend on // the bit width of `RawFd`. If this ever changes, those values will need // to be updated. assert_eq!(size_of::(), 4); diff --git a/std/src/os/unix/process.rs b/std/src/os/unix/process.rs index a739d6ad2a90d..71896d73670fd 100644 --- a/std/src/os/unix/process.rs +++ b/std/src/os/unix/process.rs @@ -420,6 +420,68 @@ pub trait ChildExt: Sealed { /// } /// ``` fn send_signal(&self, signal: i32) -> io::Result<()>; + + /// Sends a signal to a child process's process group. + /// + /// # Errors + /// + /// This function will return an error if the signal is invalid or if the + /// child process does not have a process group. The integer values + /// associated with signals are implementation-specific, so it's encouraged + /// to use a crate that provides posix bindings. + /// + /// # Examples + /// + /// ```rust + /// #![feature(unix_send_signal)] + /// + /// use std::{io, os::unix::process::{ChildExt, CommandExt}, process::{Command, Stdio}}; + /// + /// use libc::SIGTERM; + /// + /// fn main() -> io::Result<()> { + /// # if cfg!(not(all(target_vendor = "apple", not(target_os = "macos")))) { + /// let child = Command::new("cat") + /// .stdin(Stdio::piped()) + /// .process_group(0) + /// .spawn()?; + /// child.send_process_group_signal(SIGTERM)?; + /// # } + /// Ok(()) + /// } + /// ``` + #[unstable(feature = "unix_send_signal", issue = "141975")] + fn send_process_group_signal(&self, signal: i32) -> io::Result<()>; + + /// Forces the child process's process group to exit. + /// + /// This is analogous to [`Child::kill`] but applies to every process in + /// the child process's process group. + /// + /// Use [`CommandExt::process_group`] to assign a child process to an + /// existing process group, or to make it the leader of a new process group. + /// By default spawned processes are in the parent's process group. + /// + /// # Examples + /// + /// ```rust + /// #![feature(unix_kill_process_group)] + /// + /// use std::{os::unix::process::{ChildExt, CommandExt}, process::{Command, Stdio}}; + /// + /// fn main() -> std::io::Result<()> { + /// let mut child = Command::new("cat") + /// .stdin(Stdio::piped()) + /// .process_group(0) + /// .spawn()?; + /// child.kill_process_group()?; + /// Ok(()) + /// } + /// ``` + /// + /// [`Child::kill`]: process::Child::kill + #[unstable(feature = "unix_kill_process_group", issue = "156537")] + fn kill_process_group(&mut self) -> io::Result<()>; } #[unstable(feature = "unix_send_signal", issue = "141975")] @@ -427,6 +489,23 @@ impl ChildExt for process::Child { fn send_signal(&self, signal: i32) -> io::Result<()> { self.handle.send_signal(signal) } + + fn send_process_group_signal(&self, signal: i32) -> io::Result<()> { + self.handle.send_process_group_signal(signal) + } + + #[cfg(not(target_os = "espidf"))] + fn kill_process_group(&mut self) -> io::Result<()> { + self.handle.send_process_group_signal(libc::SIGKILL) + } + + #[cfg(target_os = "espidf")] + fn kill_process_group(&mut self) -> io::Result<()> { + Err(io::Error::new( + io::ErrorKind::Unsupported, + "process groups are not supported on espidf", + )) + } } #[stable(feature = "process_extensions", since = "1.2.0")] diff --git a/std/src/os/wasi/fs.rs b/std/src/os/wasi/fs.rs index 248112cb369dc..ffc8737df16f2 100644 --- a/std/src/os/wasi/fs.rs +++ b/std/src/os/wasi/fs.rs @@ -246,13 +246,15 @@ impl FileExt for File { #[cfg(target_env = "p1")] fn fdstat_set_flags(&self, flags: u16) -> io::Result<()> { - unsafe { wasi::fd_fdstat_set_flags(self.as_raw_fd() as wasi::Fd, flags).map_err(err2io) } + unsafe { + wasip1::fd_fdstat_set_flags(self.as_raw_fd() as wasip1::Fd, flags).map_err(err2io) + } } #[cfg(target_env = "p1")] fn fdstat_set_rights(&self, rights: u64, inheriting: u64) -> io::Result<()> { unsafe { - wasi::fd_fdstat_set_rights(self.as_raw_fd() as wasi::Fd, rights, inheriting) + wasip1::fd_fdstat_set_rights(self.as_raw_fd() as wasip1::Fd, rights, inheriting) .map_err(err2io) } } @@ -260,12 +262,12 @@ impl FileExt for File { #[cfg(target_env = "p1")] fn advise(&self, offset: u64, len: u64, advice: u8) -> io::Result<()> { let advice = match advice { - a if a == wasi::ADVICE_NORMAL.raw() => wasi::ADVICE_NORMAL, - a if a == wasi::ADVICE_SEQUENTIAL.raw() => wasi::ADVICE_SEQUENTIAL, - a if a == wasi::ADVICE_RANDOM.raw() => wasi::ADVICE_RANDOM, - a if a == wasi::ADVICE_WILLNEED.raw() => wasi::ADVICE_WILLNEED, - a if a == wasi::ADVICE_DONTNEED.raw() => wasi::ADVICE_DONTNEED, - a if a == wasi::ADVICE_NOREUSE.raw() => wasi::ADVICE_NOREUSE, + a if a == wasip1::ADVICE_NORMAL.raw() => wasip1::ADVICE_NORMAL, + a if a == wasip1::ADVICE_SEQUENTIAL.raw() => wasip1::ADVICE_SEQUENTIAL, + a if a == wasip1::ADVICE_RANDOM.raw() => wasip1::ADVICE_RANDOM, + a if a == wasip1::ADVICE_WILLNEED.raw() => wasip1::ADVICE_WILLNEED, + a if a == wasip1::ADVICE_DONTNEED.raw() => wasip1::ADVICE_DONTNEED, + a if a == wasip1::ADVICE_NOREUSE.raw() => wasip1::ADVICE_NOREUSE, _ => { return Err(io::const_error!( io::ErrorKind::InvalidInput, @@ -275,31 +277,35 @@ impl FileExt for File { }; unsafe { - wasi::fd_advise(self.as_raw_fd() as wasi::Fd, offset, len, advice).map_err(err2io) + wasip1::fd_advise(self.as_raw_fd() as wasip1::Fd, offset, len, advice).map_err(err2io) } } #[cfg(target_env = "p1")] fn allocate(&self, offset: u64, len: u64) -> io::Result<()> { - unsafe { wasi::fd_allocate(self.as_raw_fd() as wasi::Fd, offset, len).map_err(err2io) } + unsafe { wasip1::fd_allocate(self.as_raw_fd() as wasip1::Fd, offset, len).map_err(err2io) } } #[cfg(target_env = "p1")] fn create_directory>(&self, dir: P) -> io::Result<()> { let path = osstr2str(dir.as_ref().as_ref())?; - unsafe { wasi::path_create_directory(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { + wasip1::path_create_directory(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) + } } #[cfg(target_env = "p1")] fn remove_file>(&self, path: P) -> io::Result<()> { let path = osstr2str(path.as_ref().as_ref())?; - unsafe { wasi::path_unlink_file(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { wasip1::path_unlink_file(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) } } #[cfg(target_env = "p1")] fn remove_directory>(&self, path: P) -> io::Result<()> { let path = osstr2str(path.as_ref().as_ref())?; - unsafe { wasi::path_remove_directory(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { + wasip1::path_remove_directory(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) + } } } @@ -388,11 +394,11 @@ pub fn link, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_link( - old_fd.as_raw_fd() as wasi::Fd, + wasip1::path_link( + old_fd.as_raw_fd() as wasip1::Fd, old_flags, osstr2str(old_path.as_ref().as_ref())?, - new_fd.as_raw_fd() as wasi::Fd, + new_fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) @@ -411,10 +417,10 @@ pub fn rename, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_rename( - old_fd.as_raw_fd() as wasi::Fd, + wasip1::path_rename( + old_fd.as_raw_fd() as wasip1::Fd, osstr2str(old_path.as_ref().as_ref())?, - new_fd.as_raw_fd() as wasi::Fd, + new_fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) @@ -432,9 +438,9 @@ pub fn symlink, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_symlink( + wasip1::path_symlink( osstr2str(old_path.as_ref().as_ref())?, - fd.as_raw_fd() as wasi::Fd, + fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) diff --git a/std/src/os/wasi/io/tests.rs b/std/src/os/wasi/io/tests.rs index c5c6a19a6c885..d18b9fe10cab0 100644 --- a/std/src/os/wasi/io/tests.rs +++ b/std/src/os/wasi/io/tests.rs @@ -2,8 +2,7 @@ use crate::os::wasi::io::RawFd; #[test] fn test_raw_fd_layout() { - // `OwnedFd` and `BorrowedFd` use `rustc_layout_scalar_valid_range_start` - // and `rustc_layout_scalar_valid_range_end`, with values that depend on + // `OwnedFd` and `BorrowedFd` use pattern types with ranges that depend on // the bit width of `RawFd`. If this ever changes, those values will need // to be updated. assert_eq!(size_of::(), 4); diff --git a/std/src/os/wasi/net/mod.rs b/std/src/os/wasi/net/mod.rs index 9430cd3b05eee..fd5889bf9b7b5 100644 --- a/std/src/os/wasi/net/mod.rs +++ b/std/src/os/wasi/net/mod.rs @@ -18,6 +18,6 @@ pub trait TcpListenerExt { impl TcpListenerExt for net::TcpListener { fn sock_accept(&self, flags: u16) -> io::Result { - unsafe { wasi::sock_accept(self.as_raw_fd() as wasi::Fd, flags).map_err(err2io) } + unsafe { wasip1::sock_accept(self.as_raw_fd() as wasip1::Fd, flags).map_err(err2io) } } } diff --git a/std/src/os/windows/fs.rs b/std/src/os/windows/fs.rs index 7fd46b31f7d83..54d5cafe15ec6 100644 --- a/std/src/os/windows/fs.rs +++ b/std/src/os/windows/fs.rs @@ -4,11 +4,11 @@ #![stable(feature = "rust1", since = "1.0.0")] -use crate::fs::{self, Metadata, OpenOptions}; +use crate::fs::{self, Metadata, OpenOptions, Permissions}; use crate::io::BorrowedCursor; use crate::path::Path; use crate::sealed::Sealed; -use crate::sys::{AsInner, AsInnerMut, IntoInner}; +use crate::sys::{AsInner, AsInnerMut, FromInner, IntoInner}; use crate::time::SystemTime; use crate::{io, sys}; @@ -368,6 +368,68 @@ impl OpenOptionsExt2 for OpenOptions { } } +/// Windows-specific extensions to [`fs::Permissions`]. This extension trait +/// provides extra utilities to shows what Windows file attributes are enabled +/// in [`Permissions`] and to manually set file attributes on [`Permissions`]. +/// +/// See Microsoft's [`File Attribute Constants`] page to know what file +/// attribute metadata are defined and stored on Windows files. +/// +/// [`Permissions`]: fs::Permissions +/// [`File Attribute Constants`]: +/// https://learn.microsoft.com/en-us/windows/win32/fileio/file-attribute-constants +/// +/// # Example +/// +/// ```no_run +/// #![feature(windows_permissions_ext)] +/// use std::fs::Permissions; +/// use std::os::windows::fs::PermissionsExt; +/// +/// const FILE_ATTRIBUTE_SYSTEM: u32 = 0x4; +/// const FILE_ATTRIBUTE_ARCHIVE: u32 = 0x20; +/// let my_file_attr = FILE_ATTRIBUTE_SYSTEM | FILE_ATTRIBUTE_ARCHIVE; +/// let mut permissions = Permissions::from_file_attributes(my_file_attr); +/// assert_eq!(permissions.file_attributes(), my_file_attr); +/// +/// const FILE_ATTRIBUTE_HIDDEN: u32 = 0x2; +/// let new_file_attr = permissions.file_attributes() | FILE_ATTRIBUTE_HIDDEN; +/// permissions.set_file_attributes(new_file_attr); +/// assert_eq!(permissions.file_attributes(), new_file_attr); +/// ``` +#[unstable(feature = "windows_permissions_ext", issue = "152956")] +pub trait PermissionsExt: Sealed { + /// Returns the file attribute bits. + #[unstable(feature = "windows_permissions_ext", issue = "152956")] + fn file_attributes(&self) -> u32; + + /// Sets the file attribute bits. + #[unstable(feature = "windows_permissions_ext", issue = "152956")] + fn set_file_attributes(&mut self, mask: u32); + + /// Creates a new instance from the given file attribute bits. + #[unstable(feature = "windows_permissions_ext", issue = "152956")] + fn from_file_attributes(mask: u32) -> Self; +} + +#[unstable(feature = "windows_permissions_ext", issue = "152956")] +impl Sealed for fs::Permissions {} + +#[unstable(feature = "windows_permissions_ext", issue = "152956")] +impl PermissionsExt for fs::Permissions { + fn file_attributes(&self) -> u32 { + self.as_inner().file_attributes() + } + + fn set_file_attributes(&mut self, mask: u32) { + *self = Permissions::from_inner(FromInner::from_inner(mask)); + } + + fn from_file_attributes(mask: u32) -> Self { + Permissions::from_inner(FromInner::from_inner(mask)) + } +} + /// Windows-specific extensions to [`fs::Metadata`]. /// /// The data members that this trait exposes correspond to the members diff --git a/std/src/panicking.rs b/std/src/panicking.rs index a4a974d0447b8..6bd3d9a290e44 100644 --- a/std/src/panicking.rs +++ b/std/src/panicking.rs @@ -530,7 +530,6 @@ pub unsafe fn catch_unwind R>(f: F) -> Result R>(f: F) -> Result, data_ptr, do_catch::) == 0 { - Ok(ManuallyDrop::into_inner(data.r)) - } else { + return if intrinsics::catch_unwind(do_call, &raw mut data, do_catch) { Err(ManuallyDrop::into_inner(data.p)) + } else { + Ok(ManuallyDrop::into_inner(data.r)) }; } @@ -568,17 +567,12 @@ pub unsafe fn catch_unwind R>(f: F) -> Result` // Its must contains a valid `f` (type: F) value that can be use to fill // `data.r`. - // - // This function cannot be marked as `unsafe` because `intrinsics::catch_unwind` - // expects normal function pointers. #[inline] - fn do_call R, R>(data: *mut u8) { + unsafe fn do_call R, R>(data: *mut Data) { // SAFETY: this is the responsibility of the caller, see above. unsafe { - let data = data as *mut Data; - let data = &mut (*data); - let f = ManuallyDrop::take(&mut data.f); - data.r = ManuallyDrop::new(f()); + let f = ManuallyDrop::take(&mut (*data).f); + (*data).r = ManuallyDrop::new(f()); } } @@ -590,22 +584,17 @@ pub unsafe fn catch_unwind R>(f: F) -> Result` // Since this uses `cleanup` it also hinges on a correct implementation of // `__rustc_panic_cleanup`. - // - // This function cannot be marked as `unsafe` because `intrinsics::catch_unwind` - // expects normal function pointers. #[inline] #[rustc_nounwind] // `intrinsic::catch_unwind` requires catch fn to be nounwind - fn do_catch R, R>(data: *mut u8, payload: *mut u8) { + unsafe fn do_catch R, R>(data: *mut Data, payload: *mut u8) { // SAFETY: this is the responsibility of the caller, see above. // // When `__rustc_panic_cleaner` is correctly implemented we can rely // on `obj` being the correct thing to pass to `data.p` (after wrapping // in `ManuallyDrop`). unsafe { - let data = data as *mut Data; - let data = &mut (*data); let obj = cleanup(payload); - data.p = ManuallyDrop::new(obj); + (*data).p = ManuallyDrop::new(obj); } } } diff --git a/std/src/path.rs b/std/src/path.rs index 6b894f6bf4243..2d1f6a2d7e9b0 100644 --- a/std/src/path.rs +++ b/std/src/path.rs @@ -1796,6 +1796,25 @@ impl PathBuf { self.inner } + /// Converts the `PathBuf` into a `String` if it contains valid Unicode data. + /// + /// On failure, ownership of the original `PathBuf` is returned. + /// + /// # Examples + /// + /// ``` + /// #![feature(pathbuf_into_string)] + /// use std::path::PathBuf; + /// + /// let path_buf = PathBuf::from("foo"); + /// let string = path_buf.into_string(); + /// assert_eq!(string, Ok(String::from("foo"))); + /// ``` + #[unstable(feature = "pathbuf_into_string", issue = "156203")] + pub fn into_string(self) -> Result { + self.into_os_string().into_string().map_err(PathBuf::from) + } + /// Converts this `PathBuf` into a [boxed](Box) [`Path`]. #[stable(feature = "into_boxed_path", since = "1.20.0")] #[must_use = "`self` will be dropped if the result is not used"] @@ -2828,10 +2847,13 @@ impl Path { /// Checks whether the `Path` is empty. /// + /// Passing an empty path to most OS filesystem APIs will always result in an error. + /// + /// [Pushing][PathBuf::push] an empty path to an existing path will append a directory separator unless it already ends with a separator or the existing path is itself empty. + /// /// # Examples /// /// ``` - /// #![feature(path_is_empty)] /// use std::path::Path; /// /// let path = Path::new(""); @@ -2843,7 +2865,7 @@ impl Path { /// let path = Path::new("."); /// assert!(!path.is_empty()); /// ``` - #[unstable(feature = "path_is_empty", issue = "148494")] + #[stable(feature = "path_is_empty", since = "CURRENT_RUSTC_VERSION")] pub fn is_empty(&self) -> bool { self.as_os_str().is_empty() } @@ -3667,7 +3689,7 @@ unsafe impl CloneToUninit for Path { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for Path { +const impl AsRef for Path { #[inline] fn as_ref(&self) -> &OsStr { &self.inner @@ -3838,7 +3860,7 @@ impl Ord for Path { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for Path { +const impl AsRef for Path { #[inline] fn as_ref(&self) -> &Path { self @@ -3847,7 +3869,7 @@ impl const AsRef for Path { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] -impl const AsRef for OsStr { +const impl AsRef for OsStr { #[inline] fn as_ref(&self) -> &Path { Path::new(self) diff --git a/std/src/prelude/v1.rs b/std/src/prelude/v1.rs index ee57e031c959c..aeefec8b9e084 100644 --- a/std/src/prelude/v1.rs +++ b/std/src/prelude/v1.rs @@ -115,9 +115,13 @@ pub use core::prelude::v1::trace_macros; // (no public module for them to be re-exported from). #[stable(feature = "builtin_macro_prelude", since = "1.38.0")] pub use core::prelude::v1::{ - alloc_error_handler, bench, derive, global_allocator, test, test_case, + alloc_error_handler, bench, global_allocator, test, test_case, }; +#[stable(feature = "builtin_macro_prelude", since = "1.38.0")] +#[doc(no_inline)] +pub use core::prelude::v1::derive; + #[unstable(feature = "derive_const", issue = "118304")] pub use core::prelude::v1::derive_const; diff --git a/std/src/process.rs b/std/src/process.rs index 321b68b3225ad..0b8db439a6370 100644 --- a/std/src/process.rs +++ b/std/src/process.rs @@ -617,21 +617,50 @@ impl Command { /// Builder methods are provided to change these defaults and /// otherwise configure the process. /// - /// If `program` is not an absolute path, the `PATH` will be searched in - /// an OS-defined way. - /// - /// The search path to be used may be controlled by setting the - /// `PATH` environment variable on the Command, - /// but this has some implementation limitations on Windows - /// (see issue #37519). + /// If `program` is not an absolute path, the `PATH` environment variable + /// will be searched in an OS-defined way. /// /// # Platform-specific behavior /// - /// Note on Windows: For executable files with the .exe extension, - /// it can be omitted when specifying the program for this Command. - /// However, if the file has a different extension, - /// a filename including the extension needs to be provided, - /// otherwise the file won't be found. + /// The details below describe the current behavior, but these details + /// may change in future versions of Rust. + /// + /// On Unix, the `PATH` searched comes from the child's environment: + /// + /// - If the environment is unmodified, the child inherits the parent's + /// `PATH` and that is what is searched. + /// - If `PATH` is explicitly set via [`env`], that new value is searched. + /// - If [`env_clear`] or [`env_remove`] removes `PATH` without a + /// replacement, `execvp` falls back to an OS-defined default (typically + /// `/bin:/usr/bin`), **not** the parent's `PATH`. This may fail to find + /// programs that rely on the parent's `PATH`. + /// + /// To avoid surprises, use an absolute path or explicitly set `PATH` on + /// the `Command` when modifying the child's environment. + /// + /// On Windows, Rust resolves the executable path before spawning, rather + /// than passing the name to `CreateProcessW` for resolution. When + /// `program` is not an absolute path, the following locations are searched + /// in order: + /// + /// 1. The child's `PATH`, if explicitly set via [`env`]. + /// 2. The directory of the current executable. + /// 3. The system directory (`GetSystemDirectoryW`). + /// 4. The Windows directory (`GetWindowsDirectoryW`). + /// 5. The parent process's `PATH`. + /// + /// Note: when `PATH` is cleared via [`env_clear`] or [`env_remove`] on + /// Windows, step 1 is skipped but the parent process's `PATH` is still + /// searched at step 5, unlike on Unix. + /// + /// For executable files, the `.exe` extension may be omitted. Files with + /// other extensions must include the extension, otherwise they will not be + /// found. Note that this behavior has some known limitations + /// (see issue #37519). + /// + /// [`env`]: Self::env + /// [`env_remove`]: Self::env_remove + /// [`env_clear`]: Self::env_clear /// /// # Examples /// @@ -1156,7 +1185,8 @@ impl Command { /// [`Command::env_remove`] can be retrieved with this method. /// /// Note that this output does not include environment variables inherited from the parent - /// process. + /// process. To see the full list of environment variables, including those inherited from the + /// parent process, use [`Command::get_resolved_envs`]. /// /// Each element is a tuple key/value pair `(&OsStr, Option<&OsStr>)`. A [`None`] value /// indicates its key was explicitly removed via [`Command::env_remove`]. The associated key for @@ -1185,6 +1215,42 @@ impl Command { CommandEnvs { iter: self.inner.get_envs() } } + /// Returns an iterator of the environment variables that will be set when the process is spawned. + /// + /// This returns the environment as it would be if the command were executed at the time of calling + /// this method. The returned environment includes: + /// - All inherited environment variables from the parent process (unless [`Command::env_clear`] was called) + /// - All environment variables explicitly set via [`Command::env`] or [`Command::envs`] + /// - Excluding any environment variables removed via [`Command::env_remove`] + /// + /// Note that the returned environment is a snapshot at the time this method is called and will not + /// reflect any subsequent changes to the `Command` or the parent process's environment. Additionally, + /// it will not reflect changes made in a `pre_exec` hook (on Unix platforms). + /// + /// Each element is a tuple `(OsString, OsString)` representing an environment variable key and value. + /// + /// # Examples + /// + /// ``` + /// #![feature(command_resolved_envs)] + /// use std::process::Command; + /// use std::ffi::{OsString, OsStr}; + /// use std::env; + /// use std::collections::HashMap; + /// + /// let mut cmd = Command::new("ls"); + /// cmd.env("TZ", "UTC"); + /// unsafe { env::set_var("EDITOR", "vim"); } + /// + /// let resolved: HashMap = cmd.get_resolved_envs().collect(); + /// assert_eq!(resolved.get(OsStr::new("TZ")), Some(&OsString::from("UTC"))); + /// assert_eq!(resolved.get(OsStr::new("EDITOR")), Some(&OsString::from("vim"))); + /// ``` + #[unstable(feature = "command_resolved_envs", issue = "149070")] + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + self.inner.get_resolved_envs() + } + /// Returns the working directory for the child process. /// /// This returns [`None`] if the working directory will not be changed. @@ -1338,6 +1404,9 @@ impl<'a> fmt::Debug for CommandEnvs<'a> { } } +#[unstable(feature = "command_resolved_envs", issue = "149070")] +pub use imp::CommandResolvedEnvs; + /// The output of a finished process. /// /// This is returned in a Result by either the [`output`] method of a @@ -2536,6 +2605,10 @@ pub fn abort() -> ! { crate::sys::abort_internal(); } +#[doc(inline)] +#[unstable(feature = "abort_immediate", issue = "154601")] +pub use core::process::abort_immediate; + /// Returns the OS-assigned process identifier associated with this process. /// /// # Examples diff --git a/std/src/process/tests.rs b/std/src/process/tests.rs index 12c5130defe5a..68c62a861075f 100644 --- a/std/src/process/tests.rs +++ b/std/src/process/tests.rs @@ -188,10 +188,10 @@ fn child_stdout_read_buf() { // ChildStdout::read_buf should omit buffer initialization. if cfg!(target_os = "windows") { assert_eq!(buf.filled(), b"abc\r\n"); - assert_eq!(buf.init_len(), 5); + assert!(!buf.is_init()); } else { assert_eq!(buf.filled(), b"abc\n"); - assert_eq!(buf.init_len(), 4); + assert!(!buf.is_init()); }; } diff --git a/std/src/sync/lazy_lock.rs b/std/src/sync/lazy_lock.rs index 9bdde0ae4a537..9bb25287275b2 100644 --- a/std/src/sync/lazy_lock.rs +++ b/std/src/sync/lazy_lock.rs @@ -375,7 +375,8 @@ impl T> DerefMut for LazyLock { } #[stable(feature = "lazy_cell", since = "1.80.0")] -impl Default for LazyLock { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +const impl Default for LazyLock { /// Creates a new lazy value using `Default` as the initializing function. #[inline] fn default() -> LazyLock { @@ -395,7 +396,7 @@ impl fmt::Debug for LazyLock { } } -#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] impl From for LazyLock { /// Constructs a `LazyLock` that starts already initialized /// with the provided value. diff --git a/std/src/sync/mod.rs b/std/src/sync/mod.rs index 5da50480c7232..439b5b09a5ac0 100644 --- a/std/src/sync/mod.rs +++ b/std/src/sync/mod.rs @@ -172,7 +172,7 @@ // These come from `core` & `alloc` and only in one flavor: no poisoning. #[unstable(feature = "exclusive_wrapper", issue = "98407")] -pub use core::sync::Exclusive; +pub use core::sync::SyncView; #[stable(feature = "rust1", since = "1.0.0")] pub use core::sync::atomic; diff --git a/std/src/sync/mpmc/mod.rs b/std/src/sync/mpmc/mod.rs index 16ae8a88370be..a687f39431697 100644 --- a/std/src/sync/mpmc/mod.rs +++ b/std/src/sync/mpmc/mod.rs @@ -297,6 +297,7 @@ pub fn sync_channel(cap: usize) -> (Sender, Receiver) { /// assert_eq!(3, msg + msg2); /// ``` #[unstable(feature = "mpmc_channel", issue = "126840")] +#[cfg_attr(not(test), rustc_diagnostic_item = "MpmcSender")] pub struct Sender { flavor: SenderFlavor, } @@ -722,6 +723,7 @@ impl fmt::Debug for Sender { /// rx_thread_2.join().unwrap(); /// ``` #[unstable(feature = "mpmc_channel", issue = "126840")] +#[cfg_attr(not(test), rustc_diagnostic_item = "MpmcReceiver")] pub struct Receiver { flavor: ReceiverFlavor, } diff --git a/std/src/sync/mpsc.rs b/std/src/sync/mpsc.rs index a1c49bb83010c..b74f84ff465c0 100644 --- a/std/src/sync/mpsc.rs +++ b/std/src/sync/mpsc.rs @@ -142,6 +142,8 @@ // not exposed publicly, but if you are curious about the implementation, // that's where everything is. +use core::clone::Share; + use crate::sync::mpmc; use crate::time::{Duration, Instant}; use crate::{error, fmt}; @@ -173,7 +175,7 @@ use crate::{error, fmt}; /// println!("{}", recv.recv().unwrap()); // Received after 2 seconds /// ``` #[stable(feature = "rust1", since = "1.0.0")] -#[cfg_attr(not(test), rustc_diagnostic_item = "Receiver")] +#[cfg_attr(not(test), rustc_diagnostic_item = "MpscReceiver")] pub struct Receiver { inner: mpmc::Receiver, } @@ -330,6 +332,7 @@ pub struct IntoIter { /// assert_eq!(3, msg + msg2); /// ``` #[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "MpscSender")] pub struct Sender { inner: mpmc::Sender, } @@ -644,6 +647,9 @@ impl Clone for Sender { } } +#[unstable(feature = "share_trait", issue = "156756")] +impl Share for Sender {} + #[stable(feature = "mpsc_debug", since = "1.8.0")] impl fmt::Debug for Sender { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -773,6 +779,9 @@ impl Clone for SyncSender { } } +#[unstable(feature = "share_trait", issue = "156756")] +impl Share for SyncSender {} + #[stable(feature = "mpsc_debug", since = "1.8.0")] impl fmt::Debug for SyncSender { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { diff --git a/std/src/sync/once_lock.rs b/std/src/sync/once_lock.rs index f6ea3c1a039b2..8e69e7a22ad8e 100644 --- a/std/src/sync/once_lock.rs +++ b/std/src/sync/once_lock.rs @@ -592,7 +592,7 @@ impl UnwindSafe for OnceLock {} #[stable(feature = "once_cell", since = "1.70.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for OnceLock { +const impl Default for OnceLock { /// Creates a new uninitialized cell. /// /// # Example diff --git a/std/src/sync/poison/rwlock.rs b/std/src/sync/poison/rwlock.rs index c01ee17eecda3..4cfd9d19df74a 100644 --- a/std/src/sync/poison/rwlock.rs +++ b/std/src/sync/poison/rwlock.rs @@ -16,7 +16,7 @@ use crate::sys::sync as sys; /// /// In comparison, a [`Mutex`] does not distinguish between readers or writers /// that acquire the lock, therefore blocking any threads waiting for the lock to -/// become available. An `RwLock` will allow any number of readers to acquire the +/// become available. An `RwLock` will allow multiple readers to acquire the /// lock as long as a writer is not holding the lock. /// /// The priority policy of the lock is dependent on the underlying operating diff --git a/std/src/sys/alloc/windows.rs b/std/src/sys/alloc/windows.rs index 90da0b7e9965c..9336a6ec085aa 100644 --- a/std/src/sys/alloc/windows.rs +++ b/std/src/sys/alloc/windows.rs @@ -118,6 +118,9 @@ unsafe fn allocate(layout: Layout, zeroed: bool) -> *mut u8 { process_heap_alloc(MaybeUninit::uninit(), flags, layout.size()) as *mut u8 } else { // Allocate extra padding in order to be able to satisfy the alignment. + // This addition does not overflow due to `Layout` type invariants, + // `size()` is at most `isize::MAX` while + // `align()` is at most `1 << (bits in usize - 2)` if `size()` is non-zero. let total = layout.align() + layout.size(); let ptr = process_heap_alloc(MaybeUninit::uninit(), flags, total) as *mut u8; diff --git a/std/src/sys/args/mod.rs b/std/src/sys/args/mod.rs index 5424d40a15883..2659750f49eff 100644 --- a/std/src/sys/args/mod.rs +++ b/std/src/sys/args/mod.rs @@ -15,7 +15,7 @@ mod common; cfg_select! { any( - all(target_family = "unix", not(any(target_os = "espidf", target_os = "vita"))), + all(target_family = "unix", not(any(all(target_family = "wasm", target_os = "linux"), target_os = "espidf", target_os = "vita"))), target_os = "hermit", ) => { mod unix; @@ -42,8 +42,12 @@ cfg_select! { pub use wasip1::*; } all(target_os = "wasi", any(target_env = "p2", target_env = "p3")) => { - mod wasip2; - pub use wasip2::*; + mod wasi; + pub use wasi::*; + } + all(target_family = "wasm", target_os = "linux") => { + mod wali; + pub use wali::*; } target_os = "xous" => { mod xous; diff --git a/std/src/sys/args/wali.rs b/std/src/sys/args/wali.rs new file mode 100644 index 0000000000000..dc6295a483334 --- /dev/null +++ b/std/src/sys/args/wali.rs @@ -0,0 +1,54 @@ +pub use super::common::Args; + +/// One-time global initialization. +pub unsafe fn init(argc: isize, argv: *const *const u8) { + unsafe { imp::init(argc, argv) } +} + +/// Returns the command line arguments +pub fn args() -> Args { + imp::args() +} + +mod imp { + use super::Args; + use crate::ffi::{CString, OsString}; + use crate::os::raw::{c_uint as WaliArgIdx, c_uint}; + use crate::os::unix::prelude::*; + use crate::sync::OnceLock; + + #[link(wasm_import_module = "wali")] + unsafe extern "C" { + pub fn __cl_get_argc() -> WaliArgIdx; + pub fn __cl_get_argv_len(offset: WaliArgIdx) -> c_uint; + pub fn __cl_copy_argv(buf: *mut i8, offset: WaliArgIdx) -> c_uint; + } + + static ARGS: OnceLock> = OnceLock::new(); + + pub unsafe fn init(_argc: isize, _argv: *const *const u8) { + // Uses the WALI arguments API + ARGS.set(argc_argv()).ok(); + } + + unsafe fn load_arg(idx: c_uint) -> OsString { + let arg_len = unsafe { __cl_get_argv_len(idx) }; + let arg_buf = CString::new(vec![b'x'; arg_len as usize]).unwrap(); + let ptr = arg_buf.into_raw(); + let arg_buf = unsafe { + __cl_copy_argv(ptr, idx); + CString::from_raw(ptr) + }; + OsStringExt::from_vec(arg_buf.into_bytes()) + } + + fn argc_argv() -> Vec { + let argc = unsafe { __cl_get_argc() }; + (0..argc).map(|x| unsafe { load_arg(x) }).collect() + } + + pub fn args() -> Args { + let cached = ARGS.get().cloned().unwrap_or_default(); + Args::new(cached) + } +} diff --git a/std/src/sys/args/wasi.rs b/std/src/sys/args/wasi.rs new file mode 100644 index 0000000000000..3d26a76ad6db6 --- /dev/null +++ b/std/src/sys/args/wasi.rs @@ -0,0 +1,11 @@ +#[cfg(target_env = "p2")] +use wasip2 as wasi; +#[cfg(target_env = "p3")] +use wasip3 as wasi; + +pub use super::common::Args; + +/// Returns the command line arguments +pub fn args() -> Args { + Args::new(wasi::cli::environment::get_arguments().into_iter().map(|arg| arg.into()).collect()) +} diff --git a/std/src/sys/args/wasip1.rs b/std/src/sys/args/wasip1.rs index 72063a87dc9f5..c09175a23f50f 100644 --- a/std/src/sys/args/wasip1.rs +++ b/std/src/sys/args/wasip1.rs @@ -11,10 +11,10 @@ pub fn args() -> Args { fn maybe_args() -> Option> { unsafe { - let (argc, buf_size) = wasi::args_sizes_get().ok()?; + let (argc, buf_size) = wasip1::args_sizes_get().ok()?; let mut argv = Vec::with_capacity(argc); let mut buf = Vec::with_capacity(buf_size); - wasi::args_get(argv.as_mut_ptr(), buf.as_mut_ptr()).ok()?; + wasip1::args_get(argv.as_mut_ptr(), buf.as_mut_ptr()).ok()?; argv.set_len(argc); let mut ret = Vec::with_capacity(argc); for ptr in argv { diff --git a/std/src/sys/args/wasip2.rs b/std/src/sys/args/wasip2.rs deleted file mode 100644 index a57e4b97786d0..0000000000000 --- a/std/src/sys/args/wasip2.rs +++ /dev/null @@ -1,6 +0,0 @@ -pub use super::common::Args; - -/// Returns the command line arguments -pub fn args() -> Args { - Args::new(wasip2::cli::environment::get_arguments().into_iter().map(|arg| arg.into()).collect()) -} diff --git a/std/src/sys/cmath.rs b/std/src/sys/cmath.rs index 1592218ead8b0..2104087141d1a 100644 --- a/std/src/sys/cmath.rs +++ b/std/src/sys/cmath.rs @@ -4,7 +4,9 @@ // or by `compiler-builtins` on unsupported platforms. unsafe extern "C" { pub safe fn acos(n: f64) -> f64; + pub safe fn acosh(n: f64) -> f64; pub safe fn asin(n: f64) -> f64; + pub safe fn asinh(n: f64) -> f64; pub safe fn atan(n: f64) -> f64; pub safe fn atan2(a: f64, b: f64) -> f64; pub safe fn cosh(n: f64) -> f64; @@ -30,7 +32,9 @@ unsafe extern "C" { pub safe fn erfcf(n: f32) -> f32; pub safe fn acosf128(n: f128) -> f128; + pub safe fn acoshf128(n: f128) -> f128; pub safe fn asinf128(n: f128) -> f128; + pub safe fn asinhf128(n: f128) -> f128; pub safe fn atanf128(n: f128) -> f128; pub safe fn atan2f128(a: f128, b: f128) -> f128; pub safe fn cbrtf128(n: f128) -> f128; @@ -57,6 +61,16 @@ cfg_select! { f64::acos(n as f64) as f32 } + #[inline] + pub fn acoshf(n: f32) -> f32 { + f64::acosh(n as f64) as f32 + } + + #[inline] + pub fn asinhf(n: f32) -> f32 { + f64::asinh(n as f64) as f32 + } + #[inline] pub fn asinf(n: f32) -> f32 { f64::asin(n as f64) as f32 @@ -95,7 +109,9 @@ cfg_select! { _ => { unsafe extern "C" { pub safe fn acosf(n: f32) -> f32; + pub safe fn acoshf(n: f32) -> f32; pub safe fn asinf(n: f32) -> f32; + pub safe fn asinhf(n: f32) -> f32; pub safe fn atan2f(a: f32, b: f32) -> f32; pub safe fn atanf(n: f32) -> f32; pub safe fn coshf(n: f32) -> f32; diff --git a/std/src/sys/fd/hermit.rs b/std/src/sys/fd/hermit.rs index 2666da16420c4..28fafdaf57d8a 100644 --- a/std/src/sys/fd/hermit.rs +++ b/std/src/sys/fd/hermit.rs @@ -33,7 +33,7 @@ impl FileDesc { ) })?; // SAFETY: Exactly `result` bytes have been filled. - unsafe { buf.advance_unchecked(result as usize) }; + unsafe { buf.advance(result as usize) }; Ok(()) } diff --git a/std/src/sys/fd/unix.rs b/std/src/sys/fd/unix.rs index bb6c0ac9e18e6..c5e8646dada1e 100644 --- a/std/src/sys/fd/unix.rs +++ b/std/src/sys/fd/unix.rs @@ -185,7 +185,7 @@ impl FileDesc { // SAFETY: `ret` bytes were written to the initialized portion of the buffer unsafe { - cursor.advance_unchecked(ret as usize); + cursor.advance(ret as usize); } Ok(()) } @@ -203,7 +203,7 @@ impl FileDesc { // SAFETY: `ret` bytes were written to the initialized portion of the buffer unsafe { - cursor.advance_unchecked(ret as usize); + cursor.advance(ret as usize); } Ok(()) } diff --git a/std/src/sys/fs/common.rs b/std/src/sys/fs/common.rs index 4d47d392a8268..0df91d56b8a19 100644 --- a/std/src/sys/fs/common.rs +++ b/std/src/sys/fs/common.rs @@ -2,7 +2,8 @@ use crate::io::{self, Error, ErrorKind}; use crate::path::{Path, PathBuf}; -use crate::sys::fs::{File, OpenOptions}; +use crate::sys::IntoInner; +use crate::sys::fs::{File, FileAttr, OpenOptions}; use crate::sys::helpers::ignore_notfound; use crate::{fmt, fs}; @@ -72,6 +73,10 @@ impl Dir { pub fn open_file(&self, path: &Path, opts: &OpenOptions) -> io::Result { File::open(&self.path.join(path), &opts) } + + pub fn metadata(&self) -> io::Result { + self.path.metadata().map(|m| m.into_inner()) + } } impl fmt::Debug for Dir { diff --git a/std/src/sys/fs/solid.rs b/std/src/sys/fs/solid.rs index 114ffda57bc52..f15a152146ee5 100644 --- a/std/src/sys/fs/solid.rs +++ b/std/src/sys/fs/solid.rs @@ -401,7 +401,7 @@ impl File { // Safety: `num_bytes_read` bytes were written to the unfilled // portion of the buffer - cursor.advance_unchecked(num_bytes_read); + cursor.advance(num_bytes_read); Ok(()) } diff --git a/std/src/sys/fs/uefi.rs b/std/src/sys/fs/uefi.rs index 8135519317a02..ef523a9807f1c 100644 --- a/std/src/sys/fs/uefi.rs +++ b/std/src/sys/fs/uefi.rs @@ -588,6 +588,11 @@ mod uefi_fs { path: crate::path::PathBuf, } + // SAFETY: UEFI has no regular threads, and as per + // std does not support being invoked from "irregular threads" such as interrupt handlers or other + // CPU cores that run outside the scope of UEFI. + unsafe impl Send for File {} + impl File { pub(crate) fn from_path(path: &Path, open_mode: u64, attr: u64) -> io::Result { let absolute = crate::path::absolute(path)?; diff --git a/std/src/sys/fs/unix.rs b/std/src/sys/fs/unix.rs index 9b0ef5539d32b..eefec06f68f54 100644 --- a/std/src/sys/fs/unix.rs +++ b/std/src/sys/fs/unix.rs @@ -339,7 +339,7 @@ fn get_path_from_fd(fd: c_int) -> Option { // alternatives. If a better method is invented, it should be used // instead. let mut buf = vec![0; libc::PATH_MAX as usize]; - let n = unsafe { libc::fcntl(fd, libc::F_GETPATH, buf.as_ptr()) }; + let n = unsafe { libc::fcntl(fd, libc::F_GETPATH, buf.as_mut_ptr()) }; if n == -1 { cfg_select! { target_os = "netbsd" => { @@ -375,7 +375,7 @@ fn get_path_from_fd(fd: c_int) -> Option { #[cfg(target_os = "vxworks")] fn get_path(fd: c_int) -> Option { let mut buf = vec![0; libc::PATH_MAX as usize]; - let n = unsafe { libc::ioctl(fd, libc::FIOGETNAME, buf.as_ptr()) }; + let n = unsafe { libc::ioctl(fd, libc::FIOGETNAME, buf.as_mut_ptr()) }; if n == -1 { return None; } @@ -599,15 +599,15 @@ impl FileAttr { #[cfg(target_os = "aix")] impl FileAttr { pub fn modified(&self) -> io::Result { - SystemTime::new(self.stat.st_mtime.tv_sec as i64, self.stat.st_mtime.tv_nsec as i64) + SystemTime::new(self.stat.st_mtim.tv_sec as i64, self.stat.st_mtim.tv_nsec as i64) } pub fn accessed(&self) -> io::Result { - SystemTime::new(self.stat.st_atime.tv_sec as i64, self.stat.st_atime.tv_nsec as i64) + SystemTime::new(self.stat.st_atim.tv_sec as i64, self.stat.st_atim.tv_nsec as i64) } pub fn created(&self) -> io::Result { - SystemTime::new(self.stat.st_ctime.tv_sec as i64, self.stat.st_ctime.tv_nsec as i64) + SystemTime::new(self.stat.st_ctim.tv_sec as i64, self.stat.st_ctim.tv_nsec as i64) } } @@ -1090,7 +1090,7 @@ impl DirEntry { target_os = "illumos", target_vendor = "apple", )), - miri + miri // no dirfd on Miri ))] pub fn metadata(&self) -> io::Result { run_path_with_cstr(&self.path(), &lstat) @@ -1451,6 +1451,7 @@ impl File { target_os = "cygwin", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", ))] pub fn lock(&self) -> io::Result<()> { @@ -1478,6 +1479,7 @@ impl File { target_os = "solaris", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", )))] pub fn lock(&self) -> io::Result<()> { @@ -1494,6 +1496,7 @@ impl File { target_os = "cygwin", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", ))] pub fn lock_shared(&self) -> io::Result<()> { @@ -1521,6 +1524,7 @@ impl File { target_os = "solaris", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", )))] pub fn lock_shared(&self) -> io::Result<()> { @@ -1537,6 +1541,7 @@ impl File { target_os = "cygwin", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", ))] pub fn try_lock(&self) -> Result<(), TryLockError> { @@ -1580,6 +1585,7 @@ impl File { target_os = "solaris", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", )))] pub fn try_lock(&self) -> Result<(), TryLockError> { @@ -1599,6 +1605,7 @@ impl File { target_os = "cygwin", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", ))] pub fn try_lock_shared(&self) -> Result<(), TryLockError> { @@ -1642,6 +1649,7 @@ impl File { target_os = "solaris", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", )))] pub fn try_lock_shared(&self) -> Result<(), TryLockError> { @@ -1661,6 +1669,7 @@ impl File { target_os = "cygwin", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", ))] pub fn unlock(&self) -> io::Result<()> { @@ -1688,6 +1697,7 @@ impl File { target_os = "solaris", target_os = "illumos", target_os = "aix", + target_os = "android", target_vendor = "apple", )))] pub fn unlock(&self) -> io::Result<()> { diff --git a/std/src/sys/fs/unix/dir.rs b/std/src/sys/fs/unix/dir.rs index 094d1bfd31685..b3b4d25b27a84 100644 --- a/std/src/sys/fs/unix/dir.rs +++ b/std/src/sys/fs/unix/dir.rs @@ -25,7 +25,7 @@ use crate::os::wasi::io::{AsRawFd, FromRawFd}; use crate::path::Path; use crate::sys::fd::FileDesc; use crate::sys::fs::OpenOptions; -use crate::sys::fs::unix::{File, debug_path_fd}; +use crate::sys::fs::unix::{File, FileAttr, debug_path_fd}; use crate::sys::helpers::run_path_with_cstr; use crate::sys::{AsInner, FromInner, IntoInner, cvt_r}; use crate::{fmt, fs, io}; @@ -41,6 +41,16 @@ impl Dir { run_path_with_cstr(path.as_ref(), &|path| self.open_file_c(path, &opts)) } + pub fn metadata(&self) -> io::Result { + // Reuse the implementation for files, which should work for all FDs. + let fd = self.0.as_raw_fd(); + let f = core::mem::ManuallyDrop::new(File( + // SAFETY: we borrowed `self` so the FD will not be closed while this function runs. + unsafe { FileDesc::from_raw_fd(fd) }, + )); + f.file_attr() + } + pub fn open_with_c(path: &CStr, opts: &OpenOptions) -> io::Result { let flags = libc::O_CLOEXEC | libc::O_DIRECTORY diff --git a/std/src/sys/fs/windows.rs b/std/src/sys/fs/windows.rs index 74854cdeb498d..e0b02670264d9 100644 --- a/std/src/sys/fs/windows.rs +++ b/std/src/sys/fs/windows.rs @@ -1167,6 +1167,16 @@ impl FilePermissions { self.attrs &= !c::FILE_ATTRIBUTE_READONLY; } } + + pub fn file_attributes(&self) -> u32 { + self.attrs as u32 + } +} + +impl FromInner for FilePermissions { + fn from_inner(attrs: u32) -> FilePermissions { + FilePermissions { attrs } + } } impl FileTimes { diff --git a/std/src/sys/fs/windows/dir.rs b/std/src/sys/fs/windows/dir.rs index 3f617806c6c36..d8203cfcc82b5 100644 --- a/std/src/sys/fs/windows/dir.rs +++ b/std/src/sys/fs/windows/dir.rs @@ -5,7 +5,7 @@ use crate::os::windows::io::{ use crate::path::Path; use crate::sys::api::{UnicodeStrRef, WinError}; use crate::sys::fs::windows::debug_path_handle; -use crate::sys::fs::{File, OpenOptions}; +use crate::sys::fs::{File, FileAttr, OpenOptions}; use crate::sys::handle::Handle; use crate::sys::path::{WCStr, with_native_path}; use crate::sys::{AsInner, FromInner, IntoInner, IoResult, c, to_u16s}; @@ -101,6 +101,16 @@ impl Dir { }; unsafe { nt_create_file(opts, &object_attributes, c::FILE_NON_DIRECTORY_FILE) } } + + pub fn metadata(&self) -> io::Result { + // Reuse the implementation for files, which should work for all handles. + let handle = self.handle.as_raw_handle(); + let f = core::mem::ManuallyDrop::new(File { + // SAFETY: we borrowed `self` so the handle will not be closed while this function runs. + handle: unsafe { Handle::from_raw_handle(handle) }, + }); + f.file_attr() + } } impl fmt::Debug for Dir { diff --git a/std/src/sys/io/error/mod.rs b/std/src/sys/io/error/mod.rs index d7a0b9b4b301d..cc8cda9aec045 100644 --- a/std/src/sys/io/error/mod.rs +++ b/std/src/sys/io/error/mod.rs @@ -43,13 +43,9 @@ cfg_select! { target_os = "vexos", target_family = "wasm", target_os = "zkvm", + target_os = "trusty", ) => { mod generic; pub use generic::*; } } - -pub type RawOsError = cfg_select! { - target_os = "uefi" => usize, - _ => i32, -}; diff --git a/std/src/sys/io/error/motor.rs b/std/src/sys/io/error/motor.rs index 7d612d817cdd7..3c22d5fcb7b06 100644 --- a/std/src/sys/io/error/motor.rs +++ b/std/src/sys/io/error/motor.rs @@ -1,7 +1,6 @@ use crate::io; -use crate::sys::io::RawOsError; -pub fn errno() -> RawOsError { +pub fn errno() -> io::RawOsError { // Not used in Motor OS because it is ambiguous: Motor OS // is micro-kernel-based, and I/O happens via a shared-memory // ring buffer, so an I/O operation that on a unix is a syscall @@ -57,7 +56,7 @@ pub fn decode_error_kind(code: io::RawOsError) -> io::ErrorKind { } } -pub fn error_string(errno: RawOsError) -> String { +pub fn error_string(errno: io::RawOsError) -> String { let error: moto_rt::Error = match errno { x if x < 0 => moto_rt::Error::Unknown, x if x > u16::MAX.into() => moto_rt::Error::Unknown, diff --git a/std/src/sys/io/error/sgx.rs b/std/src/sys/io/error/sgx.rs index 8b3e08b0b661b..b7b4030422e12 100644 --- a/std/src/sys/io/error/sgx.rs +++ b/std/src/sys/io/error/sgx.rs @@ -60,6 +60,6 @@ pub fn error_string(errno: i32) -> String { } else if ((Error::UserRangeStart as _)..=(Error::UserRangeEnd as _)).contains(&errno) { format!("user-specified error {errno:08x}") } else { - decode_error_kind(errno).as_str().into() + format!("{}", decode_error_kind(errno)) } } diff --git a/std/src/sys/io/error/windows.rs b/std/src/sys/io/error/windows.rs index c093443f30339..3c2f41a907813 100644 --- a/std/src/sys/io/error/windows.rs +++ b/std/src/sys/io/error/windows.rs @@ -81,6 +81,10 @@ pub fn decode_error_kind(errno: i32) -> io::ErrorKind { c::WSAENETDOWN => NetworkDown, c::WSAENETUNREACH => NetworkUnreachable, c::WSAEDQUOT => QuotaExceeded, + // Not a perfect mapping but this error is only returned when writing to + // a socket after shutting down the write-end. On Unix targets, EPIPE is + // returned in those cases. + c::WSAESHUTDOWN => BrokenPipe, _ => Uncategorized, } diff --git a/std/src/sys/io/io_slice/windows.rs b/std/src/sys/io/io_slice/windows.rs deleted file mode 100644 index c3d8ec87c19e3..0000000000000 --- a/std/src/sys/io/io_slice/windows.rs +++ /dev/null @@ -1,82 +0,0 @@ -use crate::marker::PhantomData; -use crate::slice; -use crate::sys::c; - -#[derive(Copy, Clone)] -#[repr(transparent)] -pub struct IoSlice<'a> { - vec: c::WSABUF, - _p: PhantomData<&'a [u8]>, -} - -impl<'a> IoSlice<'a> { - #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { - assert!(buf.len() <= u32::MAX as usize); - IoSlice { - vec: c::WSABUF { len: buf.len() as u32, buf: buf.as_ptr() as *mut u8 }, - _p: PhantomData, - } - } - - #[inline] - pub fn advance(&mut self, n: usize) { - if (self.vec.len as usize) < n { - panic!("advancing IoSlice beyond its length"); - } - - unsafe { - self.vec.len -= n as u32; - self.vec.buf = self.vec.buf.add(n); - } - } - - #[inline] - pub const fn as_slice(&self) -> &'a [u8] { - unsafe { slice::from_raw_parts(self.vec.buf, self.vec.len as usize) } - } -} - -#[repr(transparent)] -pub struct IoSliceMut<'a> { - vec: c::WSABUF, - _p: PhantomData<&'a mut [u8]>, -} - -impl<'a> IoSliceMut<'a> { - #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { - assert!(buf.len() <= u32::MAX as usize); - IoSliceMut { - vec: c::WSABUF { len: buf.len() as u32, buf: buf.as_mut_ptr() }, - _p: PhantomData, - } - } - - #[inline] - pub fn advance(&mut self, n: usize) { - if (self.vec.len as usize) < n { - panic!("advancing IoSliceMut beyond its length"); - } - - unsafe { - self.vec.len -= n as u32; - self.vec.buf = self.vec.buf.add(n); - } - } - - #[inline] - pub fn as_slice(&self) -> &[u8] { - unsafe { slice::from_raw_parts(self.vec.buf, self.vec.len as usize) } - } - - #[inline] - pub const fn into_slice(self) -> &'a mut [u8] { - unsafe { slice::from_raw_parts_mut(self.vec.buf, self.vec.len as usize) } - } - - #[inline] - pub fn as_mut_slice(&mut self) -> &mut [u8] { - unsafe { slice::from_raw_parts_mut(self.vec.buf, self.vec.len as usize) } - } -} diff --git a/std/src/sys/io/kernel_copy/linux/tests.rs b/std/src/sys/io/kernel_copy/linux/tests.rs index 9b2d9cbef9902..ba0828039dddb 100644 --- a/std/src/sys/io/kernel_copy/linux/tests.rs +++ b/std/src/sys/io/kernel_copy/linux/tests.rs @@ -166,10 +166,14 @@ fn bench_file_to_socket_copy(b: &mut test::Bencher) { let mut sink = crate::net::TcpStream::connect(sink_drainer.local_addr().unwrap()).unwrap(); let mut sink_drainer = sink_drainer.accept().unwrap().0; - crate::thread::spawn(move || { + let t = crate::thread::spawn(move || { let mut sink_buf = vec![0u8; 1024 * 1024]; loop { - sink_drainer.read(&mut sink_buf[..]).unwrap(); + let n = sink_drainer.read(&mut sink_buf[..]).unwrap(); + if n == 0 { + // EOF + break; + } } }); @@ -178,6 +182,9 @@ fn bench_file_to_socket_copy(b: &mut test::Bencher) { src.seek(SeekFrom::Start(0)).unwrap(); assert_eq!(BYTES as u64, io::copy(&mut src, &mut sink).unwrap()); }); + + drop(sink); // close our end, so that the thread goes down + t.join().unwrap(); } #[bench] @@ -196,10 +203,14 @@ fn bench_file_to_uds_copy(b: &mut test::Bencher) { let (mut sink, mut sink_drainer) = crate::os::unix::net::UnixStream::pair().unwrap(); - crate::thread::spawn(move || { + let t = crate::thread::spawn(move || { let mut sink_buf = vec![0u8; 1024 * 1024]; loop { - sink_drainer.read(&mut sink_buf[..]).unwrap(); + let n = sink_drainer.read(&mut sink_buf[..]).unwrap(); + if n == 0 { + // EOF + break; + } } }); @@ -208,6 +219,9 @@ fn bench_file_to_uds_copy(b: &mut test::Bencher) { src.seek(SeekFrom::Start(0)).unwrap(); assert_eq!(BYTES as u64, io::copy(&mut src, &mut sink).unwrap()); }); + + drop(sink); // close our end, so that the thread goes down + t.join().unwrap(); } #[cfg(any(target_os = "linux", target_os = "android"))] diff --git a/std/src/sys/io/mod.rs b/std/src/sys/io/mod.rs index b3587ab63696a..0158137174087 100644 --- a/std/src/sys/io/mod.rs +++ b/std/src/sys/io/mod.rs @@ -2,27 +2,6 @@ mod error; -mod io_slice { - cfg_select! { - any(target_family = "unix", target_os = "hermit", target_os = "solid_asp3", target_os = "trusty", target_os = "wasi") => { - mod iovec; - pub use iovec::*; - } - target_os = "windows" => { - mod windows; - pub use windows::*; - } - target_os = "uefi" => { - mod uefi; - pub use uefi::*; - } - _ => { - mod unsupported; - pub use unsupported::*; - } - } -} - mod is_terminal { cfg_select! { any(target_family = "unix", target_os = "wasi") => { @@ -62,8 +41,7 @@ pub use error::errno_location; target_os = "wasi", ))] pub use error::set_errno; -pub use error::{RawOsError, decode_error_kind, errno, error_string, is_interrupted}; -pub use io_slice::{IoSlice, IoSliceMut}; +pub use error::{decode_error_kind, errno, error_string, is_interrupted}; pub use is_terminal::is_terminal; pub use kernel_copy::{CopyState, kernel_copy}; diff --git a/std/src/sys/net/connection/mod.rs b/std/src/sys/net/connection/mod.rs index 2f064914a8317..84b53fd375c93 100644 --- a/std/src/sys/net/connection/mod.rs +++ b/std/src/sys/net/connection/mod.rs @@ -59,3 +59,22 @@ where None => Err(Error::NO_ADDRESSES), } } + +// Default implementation, may be overridden by platform-specific implementations. +#[cfg(not(all(target_vendor = "fortanix", target_env = "sgx")))] +pub(crate) fn lookup_host_string( + addr: &str, +) -> crate::io::Result> { + use crate::io; + + // Split the string by ':' and convert the second part to u16... + let Some((host, port_str)) = addr.rsplit_once(':') else { + return Err(io::const_error!(io::ErrorKind::InvalidInput, "invalid socket address")); + }; + let Ok(port) = port_str.parse::() else { + return Err(io::const_error!(io::ErrorKind::InvalidInput, "invalid port value")); + }; + + // ... and make the system look up the host. + crate::sys::net::lookup_host(host, port) +} diff --git a/std/src/sys/net/connection/motor.rs b/std/src/sys/net/connection/motor.rs index 79a528792106c..be879f43b0bb4 100644 --- a/std/src/sys/net/connection/motor.rs +++ b/std/src/sys/net/connection/motor.rs @@ -5,7 +5,7 @@ use crate::net::SocketAddr::{V4, V6}; use crate::net::{Ipv4Addr, Ipv6Addr, Shutdown, SocketAddr, ToSocketAddrs}; use crate::os::fd::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, RawFd}; use crate::sys::fd::FileDesc; -use crate::sys::{AsInner, FromInner, IntoInner, map_motor_error}; +use crate::sys::{AsInner, FromInner, IntoInner, map_motor_error, unsupported}; use crate::time::Duration; // We want to re-use as much of Rust's stdlib code as possible, @@ -127,6 +127,14 @@ impl TcpStream { moto_rt::net::linger(self.inner.as_raw_fd()).map_err(map_motor_error) } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unsupported() + } + + pub fn keepalive(&self) -> io::Result { + unsupported() + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { moto_rt::net::set_nodelay(self.inner.as_raw_fd(), nodelay).map_err(map_motor_error) } diff --git a/std/src/sys/net/connection/sgx.rs b/std/src/sys/net/connection/sgx.rs index 6a625664494b5..c72581cf69f0b 100644 --- a/std/src/sys/net/connection/sgx.rs +++ b/std/src/sys/net/connection/sgx.rs @@ -219,6 +219,14 @@ impl TcpStream { sgx_ineffective(None) } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + sgx_ineffective(()) + } + + pub fn keepalive(&self) -> io::Result { + sgx_ineffective(false) + } + pub fn set_nodelay(&self, _: bool) -> io::Result<()> { sgx_ineffective(()) } @@ -506,9 +514,23 @@ impl Iterator for LookupHost { } } +pub(crate) fn lookup_host_string(addr: impl Into) -> io::Result { + Err(io::Error::new(io::ErrorKind::Uncategorized, NonIpSockAddr { host: addr.into() })) +} + pub fn lookup_host(host: &str, port: u16) -> io::Result { - Err(io::Error::new( - io::ErrorKind::Uncategorized, - NonIpSockAddr { host: format!("{host}:{port}") }, - )) + lookup_host_string(format!("{host}:{port}")) +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn unparseable_sockaddr() { + let addr = "local"; + let error = addr.to_socket_addrs().unwrap_err(); + let non_ip_addr = error.downcast::().unwrap(); + assert_eq!(addr, non_ip_addr.host); + } } diff --git a/std/src/sys/net/connection/socket/hermit.rs b/std/src/sys/net/connection/socket/hermit.rs index 59f515d31aff9..09953cc515af7 100644 --- a/std/src/sys/net/connection/socket/hermit.rs +++ b/std/src/sys/net/connection/socket/hermit.rs @@ -142,7 +142,7 @@ impl Socket { ) })?; unsafe { - buf.advance_unchecked(ret as usize); + buf.advance(ret as usize); } Ok(()) } @@ -260,7 +260,7 @@ impl Socket { pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = netc::linger { l_onoff: linger.is_some() as i32, - l_linger: linger.unwrap_or_default().as_secs() as libc::c_int, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), c_int::MAX as u64) as c_int, }; unsafe { setsockopt(self, netc::SOL_SOCKET, netc::SO_LINGER, linger) } @@ -272,6 +272,15 @@ impl Socket { Ok((val.l_onoff != 0).then(|| Duration::from_secs(val.l_linger as u64))) } + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + unsafe { setsockopt(self, netc::SOL_SOCKET, netc::SO_KEEPALIVE, keepalive as c_int) } + } + + pub fn keepalive(&self) -> io::Result { + let raw: c_int = unsafe { getsockopt(self, netc::SOL_SOCKET, netc::SO_KEEPALIVE)? }; + Ok(raw != 0) + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { let value: i32 = if nodelay { 1 } else { 0 }; unsafe { setsockopt(self, netc::IPPROTO_TCP, netc::TCP_NODELAY, value) } diff --git a/std/src/sys/net/connection/socket/mod.rs b/std/src/sys/net/connection/socket/mod.rs index 256b99dfa9874..8efe8bd785149 100644 --- a/std/src/sys/net/connection/socket/mod.rs +++ b/std/src/sys/net/connection/socket/mod.rs @@ -468,6 +468,14 @@ impl TcpStream { self.inner.linger() } + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + self.inner.set_keepalive(keepalive) + } + + pub fn keepalive(&self) -> io::Result { + self.inner.keepalive() + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { self.inner.set_nodelay(nodelay) } diff --git a/std/src/sys/net/connection/socket/solid.rs b/std/src/sys/net/connection/socket/solid.rs index e20a3fbb76b72..79e6c12d6ab33 100644 --- a/std/src/sys/net/connection/socket/solid.rs +++ b/std/src/sys/net/connection/socket/solid.rs @@ -6,6 +6,7 @@ use crate::ffi::CStr; use crate::io::{self, BorrowedBuf, BorrowedCursor, ErrorKind, IoSlice, IoSliceMut}; use crate::net::{Shutdown, SocketAddr}; use crate::os::solid::io::{AsFd, AsRawFd, BorrowedFd, FromRawFd, IntoRawFd, OwnedFd}; +use crate::sys::pal::unsupported; use crate::sys::{FromInner, IntoInner, abi}; use crate::time::Duration; use crate::{cmp, mem, ptr, str}; @@ -190,7 +191,7 @@ impl Socket { netc::recv(self.as_raw_fd(), buf.as_mut().as_mut_ptr().cast(), buf.capacity(), flags) })?; unsafe { - buf.advance_unchecked(ret as usize); + buf.advance(ret as usize); } Ok(()) } @@ -319,7 +320,8 @@ impl Socket { pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = netc::linger { l_onoff: linger.is_some() as netc::c_int, - l_linger: linger.unwrap_or_default().as_secs() as netc::c_int, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), netc::c_int::MAX as u64) + as netc::c_int, }; unsafe { setsockopt(self, netc::SOL_SOCKET, netc::SO_LINGER, linger) } @@ -331,6 +333,14 @@ impl Socket { Ok((val.l_onoff != 0).then(|| Duration::from_secs(val.l_linger as u64))) } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unsupported() + } + + pub fn keepalive(&self) -> io::Result { + unsupported() + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { unsafe { setsockopt(self, netc::IPPROTO_TCP, netc::TCP_NODELAY, nodelay as c_int) } } diff --git a/std/src/sys/net/connection/socket/unix.rs b/std/src/sys/net/connection/socket/unix.rs index f3c860804de03..936dd4c93233c 100644 --- a/std/src/sys/net/connection/socket/unix.rs +++ b/std/src/sys/net/connection/socket/unix.rs @@ -294,7 +294,7 @@ impl Socket { ) })?; unsafe { - buf.advance_unchecked(ret as usize); + buf.advance(ret as usize); } Ok(()) } @@ -432,8 +432,8 @@ impl Socket { #[cfg(not(target_os = "cygwin"))] pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = libc::linger { - l_onoff: linger.is_some() as libc::c_int, - l_linger: linger.unwrap_or_default().as_secs() as libc::c_int, + l_onoff: linger.is_some() as c_int, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), c_int::MAX as u64) as c_int, }; unsafe { setsockopt(self, libc::SOL_SOCKET, SO_LINGER, linger) } @@ -443,7 +443,8 @@ impl Socket { pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = libc::linger { l_onoff: linger.is_some() as libc::c_ushort, - l_linger: linger.unwrap_or_default().as_secs() as libc::c_ushort, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), libc::c_ushort::MAX as u64) + as libc::c_ushort, }; unsafe { setsockopt(self, libc::SOL_SOCKET, SO_LINGER, linger) } @@ -455,6 +456,15 @@ impl Socket { Ok((val.l_onoff != 0).then(|| Duration::from_secs(val.l_linger as u64))) } + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + unsafe { setsockopt(self, libc::SOL_SOCKET, libc::SO_KEEPALIVE, keepalive as c_int) } + } + + pub fn keepalive(&self) -> io::Result { + let raw: c_int = unsafe { getsockopt(self, libc::SOL_SOCKET, libc::SO_KEEPALIVE)? }; + Ok(raw != 0) + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { unsafe { setsockopt(self, libc::IPPROTO_TCP, libc::TCP_NODELAY, nodelay as c_int) } } diff --git a/std/src/sys/net/connection/socket/windows.rs b/std/src/sys/net/connection/socket/windows.rs index b23fb9c09f871..0ea139cad6a04 100644 --- a/std/src/sys/net/connection/socket/windows.rs +++ b/std/src/sys/net/connection/socket/windows.rs @@ -243,7 +243,7 @@ impl Socket { } } _ => { - unsafe { buf.advance_unchecked(result as usize) }; + unsafe { buf.advance(result as usize) }; Ok(()) } } @@ -413,7 +413,8 @@ impl Socket { pub fn set_linger(&self, linger: Option) -> io::Result<()> { let linger = c::LINGER { l_onoff: linger.is_some() as c_ushort, - l_linger: linger.unwrap_or_default().as_secs() as c_ushort, + l_linger: cmp::min(linger.unwrap_or_default().as_secs(), c_ushort::MAX as u64) + as c_ushort, }; unsafe { setsockopt(self, c::SOL_SOCKET, c::SO_LINGER, linger) } @@ -425,6 +426,15 @@ impl Socket { Ok((val.l_onoff != 0).then(|| Duration::from_secs(val.l_linger as u64))) } + pub fn set_keepalive(&self, keepalive: bool) -> io::Result<()> { + unsafe { setsockopt(self, c::SOL_SOCKET, c::SO_KEEPALIVE, keepalive as c::BOOL) } + } + + pub fn keepalive(&self) -> io::Result { + let raw: c::BOOL = unsafe { getsockopt(self, c::SOL_SOCKET, c::SO_KEEPALIVE)? }; + Ok(raw != 0) + } + pub fn set_nodelay(&self, nodelay: bool) -> io::Result<()> { unsafe { setsockopt(self, c::IPPROTO_TCP, c::TCP_NODELAY, nodelay as c::BOOL) } } diff --git a/std/src/sys/net/connection/uefi/mod.rs b/std/src/sys/net/connection/uefi/mod.rs index 107a3e23733de..b32316a709903 100644 --- a/std/src/sys/net/connection/uefi/mod.rs +++ b/std/src/sys/net/connection/uefi/mod.rs @@ -112,6 +112,14 @@ impl TcpStream { unsupported() } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unsupported() + } + + pub fn keepalive(&self) -> io::Result { + unsupported() + } + pub fn set_nodelay(&self, _: bool) -> io::Result<()> { unsupported() } diff --git a/std/src/sys/net/connection/unsupported.rs b/std/src/sys/net/connection/unsupported.rs index fb18e8dec557c..c019ec1c9e521 100644 --- a/std/src/sys/net/connection/unsupported.rs +++ b/std/src/sys/net/connection/unsupported.rs @@ -87,6 +87,14 @@ impl TcpStream { self.0 } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + self.0 + } + + pub fn keepalive(&self) -> io::Result { + self.0 + } + pub fn set_nodelay(&self, _: bool) -> io::Result<()> { self.0 } diff --git a/std/src/sys/net/connection/wasip1.rs b/std/src/sys/net/connection/wasip1.rs index 95a4ab2fbf0fd..93cb777a70842 100644 --- a/std/src/sys/net/connection/wasip1.rs +++ b/std/src/sys/net/connection/wasip1.rs @@ -125,12 +125,12 @@ impl TcpStream { pub fn shutdown(&self, how: Shutdown) -> io::Result<()> { let wasi_how = match how { - Shutdown::Read => wasi::SDFLAGS_RD, - Shutdown::Write => wasi::SDFLAGS_WR, - Shutdown::Both => wasi::SDFLAGS_RD | wasi::SDFLAGS_WR, + Shutdown::Read => wasip1::SDFLAGS_RD, + Shutdown::Write => wasip1::SDFLAGS_WR, + Shutdown::Both => wasip1::SDFLAGS_RD | wasip1::SDFLAGS_WR, }; - unsafe { wasi::sock_shutdown(self.socket().as_raw_fd() as _, wasi_how).map_err(err2io) } + unsafe { wasip1::sock_shutdown(self.socket().as_raw_fd() as _, wasi_how).map_err(err2io) } } pub fn duplicate(&self) -> io::Result { @@ -145,6 +145,14 @@ impl TcpStream { unsupported() } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unsupported() + } + + pub fn keepalive(&self) -> io::Result { + unsupported() + } + pub fn set_nodelay(&self, _: bool) -> io::Result<()> { unsupported() } @@ -167,19 +175,20 @@ impl TcpStream { pub fn set_nonblocking(&self, state: bool) -> io::Result<()> { let fdstat = unsafe { - wasi::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasi::Fd).map_err(err2io)? + wasip1::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasip1::Fd) + .map_err(err2io)? }; let mut flags = fdstat.fs_flags; if state { - flags |= wasi::FDFLAGS_NONBLOCK; + flags |= wasip1::FDFLAGS_NONBLOCK; } else { - flags &= !wasi::FDFLAGS_NONBLOCK; + flags &= !wasip1::FDFLAGS_NONBLOCK; } unsafe { - wasi::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasi::Fd, flags) + wasip1::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasip1::Fd, flags) .map_err(err2io) } } @@ -221,7 +230,7 @@ impl TcpListener { pub fn accept(&self) -> io::Result<(TcpStream, SocketAddr)> { let fd = unsafe { - wasi::sock_accept(self.as_inner().as_inner().as_raw_fd() as _, 0).map_err(err2io)? + wasip1::sock_accept(self.as_inner().as_inner().as_raw_fd() as _, 0).map_err(err2io)? }; Ok(( @@ -258,19 +267,20 @@ impl TcpListener { pub fn set_nonblocking(&self, state: bool) -> io::Result<()> { let fdstat = unsafe { - wasi::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasi::Fd).map_err(err2io)? + wasip1::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasip1::Fd) + .map_err(err2io)? }; let mut flags = fdstat.fs_flags; if state { - flags |= wasi::FDFLAGS_NONBLOCK; + flags |= wasip1::FDFLAGS_NONBLOCK; } else { - flags &= !wasi::FDFLAGS_NONBLOCK; + flags &= !wasip1::FDFLAGS_NONBLOCK; } unsafe { - wasi::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasi::Fd, flags) + wasip1::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasip1::Fd, flags) .map_err(err2io) } } diff --git a/std/src/sys/net/connection/xous/tcpstream.rs b/std/src/sys/net/connection/xous/tcpstream.rs index 4df75453d1f45..521d24e3c496e 100644 --- a/std/src/sys/net/connection/xous/tcpstream.rs +++ b/std/src/sys/net/connection/xous/tcpstream.rs @@ -353,6 +353,14 @@ impl TcpStream { unimpl!(); } + pub fn set_keepalive(&self, _: bool) -> io::Result<()> { + unimpl!(); + } + + pub fn keepalive(&self) -> io::Result { + unimpl!(); + } + pub fn set_nodelay(&self, enabled: bool) -> io::Result<()> { crate::os::xous::ffi::blocking_scalar( services::net_server(), diff --git a/std/src/sys/os_str/bytes.rs b/std/src/sys/os_str/bytes.rs index 5482663ef0079..a57da01a5d85d 100644 --- a/std/src/sys/os_str/bytes.rs +++ b/std/src/sys/os_str/bytes.rs @@ -238,16 +238,24 @@ impl Slice { #[track_caller] #[inline] pub fn check_public_boundary(&self, index: usize) { + if self.try_check_public_boundary(index).is_none() { + panic!("byte index {index} is not an OsStr boundary"); + } + } + + #[track_caller] + #[inline] + pub fn try_check_public_boundary(&self, index: usize) -> Option<()> { if index == 0 || index == self.inner.len() { - return; + return Some(()); } if index < self.inner.len() && (self.inner[index - 1].is_ascii() || self.inner[index].is_ascii()) { - return; + return Some(()); } - slow_path(&self.inner, index); + return slow_path(&self.inner, index); /// We're betting that typical splits will involve an ASCII character. /// @@ -255,26 +263,26 @@ impl Slice { /// better assembly. #[track_caller] #[inline(never)] - fn slow_path(bytes: &[u8], index: usize) { - let (before, after) = bytes.split_at(index); + fn slow_path(bytes: &[u8], index: usize) -> Option<()> { + let (before, after) = bytes.split_at_checked(index)?; // UTF-8 takes at most 4 bytes per codepoint, so we don't // need to check more than that. let after = after.get(..4).unwrap_or(after); match str::from_utf8(after) { - Ok(_) => return, - Err(err) if err.valid_up_to() != 0 => return, + Ok(_) => return Some(()), + Err(err) if err.valid_up_to() != 0 => return Some(()), Err(_) => (), } for len in 2..=4.min(index) { let before = &before[index - len..]; if str::from_utf8(before).is_ok() { - return; + return Some(()); } } - panic!("byte index {index} is not an OsStr boundary"); + None } } diff --git a/std/src/sys/os_str/utf8.rs b/std/src/sys/os_str/utf8.rs index a324a478325e6..289f58aa480f7 100644 --- a/std/src/sys/os_str/utf8.rs +++ b/std/src/sys/os_str/utf8.rs @@ -224,10 +224,16 @@ impl Slice { Slice::from_str(unsafe { str::from_utf8_unchecked(s) }) } + #[track_caller] + #[inline] + pub fn try_check_public_boundary(&self, index: usize) -> Option<()> { + if self.inner.is_char_boundary(index) { Some(()) } else { None } + } + #[track_caller] #[inline] pub fn check_public_boundary(&self, index: usize) { - if !self.inner.is_char_boundary(index) { + if self.try_check_public_boundary(index).is_none() { panic!("byte index {index} is not an OsStr boundary"); } } diff --git a/std/src/sys/os_str/wtf8.rs b/std/src/sys/os_str/wtf8.rs index 1f130d91cf393..9a32ab3f3ea12 100644 --- a/std/src/sys/os_str/wtf8.rs +++ b/std/src/sys/os_str/wtf8.rs @@ -240,6 +240,11 @@ impl Slice { unsafe { mem::transmute(Wtf8::from_bytes_unchecked(s)) } } + #[inline] + pub fn try_check_public_boundary(&self, index: usize) -> Option<()> { + self.inner.try_check_utf8_boundary(index).ok() + } + #[track_caller] #[inline] pub fn check_public_boundary(&self, index: usize) { diff --git a/std/src/sys/pal/motor/mod.rs b/std/src/sys/pal/motor/mod.rs index 705413cbe0a79..ac10d81ecfb89 100644 --- a/std/src/sys/pal/motor/mod.rs +++ b/std/src/sys/pal/motor/mod.rs @@ -42,5 +42,5 @@ pub fn unsupported_err() -> io::Error { } pub fn abort_internal() -> ! { - core::intrinsics::abort(); + moto_rt::process::exit(-1) } diff --git a/std/src/sys/pal/sgx/abi/usercalls/alloc.rs b/std/src/sys/pal/sgx/abi/usercalls/alloc.rs index c2694316249a3..f4115ca6124a7 100644 --- a/std/src/sys/pal/sgx/abi/usercalls/alloc.rs +++ b/std/src/sys/pal/sgx/abi/usercalls/alloc.rs @@ -151,7 +151,7 @@ unsafe impl UserSafe for [T] { let elem_size = size_of::(); assert_eq!(size % elem_size, 0); let len = size / elem_size; - ptr::slice_from_raw_parts_mut(ptr as _, len) + ptr.cast::().cast_slice(len) } } diff --git a/std/src/sys/pal/sgx/abi/usercalls/mod.rs b/std/src/sys/pal/sgx/abi/usercalls/mod.rs index f49e940c5044c..e413bae6ab43b 100644 --- a/std/src/sys/pal/sgx/abi/usercalls/mod.rs +++ b/std/src/sys/pal/sgx/abi/usercalls/mod.rs @@ -44,7 +44,7 @@ pub fn read_buf(fd: Fd, mut buf: BorrowedCursor<'_>) -> io::Result<()> { let mut userbuf = alloc::User::<[u8]>::uninitialized(buf.capacity()); let len = raw::read(fd, userbuf.as_mut_ptr().cast(), userbuf.len()).from_sgx_result()?; userbuf[..len].copy_to_enclave(&mut buf.as_mut()[..len]); - buf.advance_unchecked(len); + buf.advance(len); Ok(()) } } diff --git a/std/src/sys/pal/unix/conf.rs b/std/src/sys/pal/unix/conf.rs index a97173a1a35a1..4c00379a88439 100644 --- a/std/src/sys/pal/unix/conf.rs +++ b/std/src/sys/pal/unix/conf.rs @@ -12,9 +12,7 @@ pub fn page_size() -> usize { /// /// [posix_confstr]: /// https://pubs.opengroup.org/onlinepubs/9699919799/functions/confstr.html -// -// FIXME: Support `confstr` in Miri. -#[cfg(all(target_vendor = "apple", not(miri)))] +#[cfg(target_vendor = "apple")] pub fn confstr( key: crate::ffi::c_int, size_hint: Option, diff --git a/std/src/sys/pal/unix/conf/tests.rs b/std/src/sys/pal/unix/conf/tests.rs index 63a1cc1e94a1d..a84086037ce0b 100644 --- a/std/src/sys/pal/unix/conf/tests.rs +++ b/std/src/sys/pal/unix/conf/tests.rs @@ -25,7 +25,7 @@ fn test_parse_glibc_version() { // Smoke check `confstr`, do it for several hint values, to ensure our resizing // logic is correct. #[test] -#[cfg(all(target_vendor = "apple", not(miri)))] +#[cfg(target_vendor = "apple")] fn test_confstr() { for key in [libc::_CS_DARWIN_USER_TEMP_DIR, libc::_CS_PATH] { let value_nohint = super::confstr(key, None).unwrap_or_else(|e| { diff --git a/std/src/sys/pal/unix/linux/pidfd.rs b/std/src/sys/pal/unix/linux/pidfd.rs index 671046949aa16..ac376c1a81af6 100644 --- a/std/src/sys/pal/unix/linux/pidfd.rs +++ b/std/src/sys/pal/unix/linux/pidfd.rs @@ -95,6 +95,21 @@ impl PidFd { .map(drop) } + pub(crate) fn send_process_group_signal(&self, signal: i32) -> io::Result<()> { + // since kernel 6.9 + // https://lore.kernel.org/all/20240210-chihuahua-hinzog-3945b6abd44a@brauner/ + cvt(unsafe { + libc::syscall( + libc::SYS_pidfd_send_signal, + self.0.as_raw_fd(), + signal, + crate::ptr::null::<()>(), + libc::PIDFD_SIGNAL_PROCESS_GROUP, + ) + }) + .map(drop) + } + pub fn wait(&self) -> io::Result { let r = self.waitid(libc::WEXITED)?; match r { diff --git a/std/src/sys/pal/unix/mod.rs b/std/src/sys/pal/unix/mod.rs index 0be150a0bfaa8..cfd7acdb08ab2 100644 --- a/std/src/sys/pal/unix/mod.rs +++ b/std/src/sys/pal/unix/mod.rs @@ -78,7 +78,7 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { // fast path with a single syscall for systems with poll() #[cfg(not(any( - miri, + miri, // no `poll` target_os = "emscripten", target_os = "fuchsia", target_os = "vxworks", @@ -125,8 +125,6 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { // fallback in case poll isn't available or limited by RLIMIT_NOFILE #[cfg(not(any( - // The standard fds are always available in Miri. - miri, target_os = "emscripten", target_os = "fuchsia", target_os = "vxworks", diff --git a/std/src/sys/pal/unix/stack_overflow.rs b/std/src/sys/pal/unix/stack_overflow.rs index 5d53de7fb7e21..3b951899dfec9 100644 --- a/std/src/sys/pal/unix/stack_overflow.rs +++ b/std/src/sys/pal/unix/stack_overflow.rs @@ -305,7 +305,7 @@ mod imp { } /// Modern kernels on modern hardware can have dynamic signal stack sizes. - #[cfg(any(target_os = "linux", target_os = "android"))] + #[cfg(all(any(target_os = "linux", target_os = "android"), not(target_env = "uclibc")))] fn sigstack_size() -> usize { let dynamic_sigstksz = unsafe { libc::getauxval(libc::AT_MINSIGSTKSZ) }; // If getauxval couldn't find the entry, it returns 0, @@ -315,7 +315,7 @@ mod imp { } /// Not all OS support hardware where this is needed. - #[cfg(not(any(target_os = "linux", target_os = "android")))] + #[cfg(not(all(any(target_os = "linux", target_os = "android"), not(target_env = "uclibc"))))] fn sigstack_size() -> usize { libc::SIGSTKSZ } diff --git a/std/src/sys/pal/wasi/mod.rs b/std/src/sys/pal/wasi/mod.rs index 6f60993509253..8ea26faca7e70 100644 --- a/std/src/sys/pal/wasi/mod.rs +++ b/std/src/sys/pal/wasi/mod.rs @@ -29,7 +29,7 @@ pub fn abort_internal() -> ! { #[inline] #[cfg(target_env = "p1")] -pub(crate) fn err2io(err: wasi::Errno) -> crate::io::Error { +pub(crate) fn err2io(err: wasip1::Errno) -> crate::io::Error { crate::io::Error::from_raw_os_error(err.raw().into()) } diff --git a/std/src/sys/pal/windows/c/bindings.txt b/std/src/sys/pal/windows/c/bindings.txt index c21d1de81341f..7b5abbc363786 100644 --- a/std/src/sys/pal/windows/c/bindings.txt +++ b/std/src/sys/pal/windows/c/bindings.txt @@ -2388,6 +2388,7 @@ SleepConditionVariableSRW SleepEx SO_BROADCAST SO_ERROR +SO_KEEPALIVE SO_LINGER SO_RCVTIMEO SO_SNDTIMEO diff --git a/std/src/sys/pal/windows/c/windows_sys.rs b/std/src/sys/pal/windows/c/windows_sys.rs index eb54efd1c1fe0..7cef71097a784 100644 --- a/std/src/sys/pal/windows/c/windows_sys.rs +++ b/std/src/sys/pal/windows/c/windows_sys.rs @@ -3189,6 +3189,7 @@ pub const SOCK_STREAM: WINSOCK_SOCKET_TYPE = 1i32; pub const SOL_SOCKET: i32 = 65535i32; pub const SO_BROADCAST: i32 = 32i32; pub const SO_ERROR: i32 = 4103i32; +pub const SO_KEEPALIVE: i32 = 8i32; pub const SO_LINGER: i32 = 128i32; pub const SO_RCVTIMEO: i32 = 4102i32; pub const SO_SNDTIMEO: i32 = 4101i32; diff --git a/std/src/sys/pal/windows/handle.rs b/std/src/sys/pal/windows/handle.rs index 9b92cd79c06f4..ed10639e36ed5 100644 --- a/std/src/sys/pal/windows/handle.rs +++ b/std/src/sys/pal/windows/handle.rs @@ -117,7 +117,7 @@ impl Handle { Ok(read) => { // Safety: `read` bytes were written to the initialized portion of the buffer unsafe { - cursor.advance_unchecked(read); + cursor.advance(read); } Ok(()) } @@ -140,7 +140,7 @@ impl Handle { // SAFETY: `read` bytes were written to the initialized portion of the buffer unsafe { - cursor.advance_unchecked(read); + cursor.advance(read); } Ok(()) } diff --git a/std/src/sys/paths/unix.rs b/std/src/sys/paths/unix.rs index 544d495340db7..e0b1aafda6eb0 100644 --- a/std/src/sys/paths/unix.rs +++ b/std/src/sys/paths/unix.rs @@ -207,7 +207,7 @@ pub fn current_exe() -> io::Result { cvt(libc::sysctl( mib.as_ptr(), mib.len() as libc::c_uint, - path.as_ptr() as *mut libc::c_void, + path.as_mut_ptr() as *mut libc::c_void, &mut path_len, ptr::null(), 0, @@ -393,7 +393,7 @@ pub fn current_exe() -> io::Result { if !path.is_absolute() { getcwd().map(|cwd| cwd.join(path)) } else { Ok(path) } } -#[cfg(all(target_vendor = "apple", not(miri)))] +#[cfg(target_vendor = "apple")] fn darwin_temp_dir() -> PathBuf { crate::sys::pal::conf::confstr(libc::_CS_DARWIN_USER_TEMP_DIR, Some(64)) .map(PathBuf::from) @@ -407,7 +407,7 @@ fn darwin_temp_dir() -> PathBuf { pub fn temp_dir() -> PathBuf { crate::env::var_os("TMPDIR").map(PathBuf::from).unwrap_or_else(|| { cfg_select! { - all(target_vendor = "apple", not(miri)) => darwin_temp_dir(), + target_vendor = "apple" => darwin_temp_dir(), target_os = "android" => PathBuf::from("/data/local/tmp"), _ => PathBuf::from("/tmp"), } diff --git a/std/src/sys/process/env.rs b/std/src/sys/process/env.rs index e08b476540ef9..15065c6e2c922 100644 --- a/std/src/sys/process/env.rs +++ b/std/src/sys/process/env.rs @@ -113,3 +113,34 @@ impl<'a> ExactSizeIterator for CommandEnvs<'a> { self.iter.is_empty() } } + +/// An iterator over the fully resolved environment variables. +/// +/// This struct is created by +/// [`Command::get_resolved_envs`][crate::process::Command::get_resolved_envs]. See its +/// documentation for more. +#[derive(Debug)] +#[must_use = "iterators are lazy and do nothing unless consumed"] +#[unstable(feature = "command_resolved_envs", issue = "149070")] +pub struct CommandResolvedEnvs { + inner: crate::collections::btree_map::IntoIter, +} + +impl CommandResolvedEnvs { + pub(crate) fn new(map: BTreeMap) -> Self { + Self { inner: map.into_iter() } + } +} + +#[unstable(feature = "command_resolved_envs", issue = "149070")] +impl Iterator for CommandResolvedEnvs { + type Item = (OsString, OsString); + + fn next(&mut self) -> Option { + self.inner.next().map(|(key, value)| (key.into(), value)) + } + + fn size_hint(&self) -> (usize, Option) { + self.inner.size_hint() + } +} diff --git a/std/src/sys/process/mod.rs b/std/src/sys/process/mod.rs index 46f4ebf6db421..3eb20dae083ca 100644 --- a/std/src/sys/process/mod.rs +++ b/std/src/sys/process/mod.rs @@ -27,6 +27,8 @@ cfg_select! { mod env; pub use env::CommandEnvs; +#[unstable(feature = "command_resolved_envs", issue = "149070")] +pub use env::CommandResolvedEnvs; #[cfg(target_family = "unix")] pub use imp::getppid; pub use imp::{ diff --git a/std/src/sys/process/motor.rs b/std/src/sys/process/motor.rs index 133633f7bc67b..080da9be3af92 100644 --- a/std/src/sys/process/motor.rs +++ b/std/src/sys/process/motor.rs @@ -1,5 +1,5 @@ use super::CommandEnvs; -use super::env::CommandEnv; +use super::env::{CommandEnv, CommandResolvedEnvs}; use crate::ffi::OsStr; pub use crate::ffi::OsString as EnvKey; use crate::num::NonZeroI32; @@ -100,6 +100,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { self.cwd.as_ref().map(Path::new) } diff --git a/std/src/sys/process/uefi.rs b/std/src/sys/process/uefi.rs index 88dd4c899b377..e0c4fa579275a 100644 --- a/std/src/sys/process/uefi.rs +++ b/std/src/sys/process/uefi.rs @@ -1,11 +1,11 @@ use r_efi::protocols::{simple_text_input, simple_text_output}; -use super::env::{CommandEnv, CommandEnvs}; +use super::env::{CommandEnv, CommandEnvs, CommandResolvedEnvs}; use crate::collections::BTreeMap; pub use crate::ffi::OsString as EnvKey; use crate::ffi::{OsStr, OsString}; use crate::num::{NonZero, NonZeroI32}; -use crate::path::Path; +use crate::path::{Path, PathBuf}; use crate::process::StdioPipes; use crate::sys::fs::File; use crate::sys::io::error_string; @@ -27,11 +27,13 @@ pub struct Command { env: CommandEnv, } -#[derive(Copy, Clone, Debug)] +#[derive(Debug)] pub enum Stdio { Inherit, Null, MakePipe, + #[allow(dead_code)] // This variant exists only for the Debug impl + InheritFile(File), } impl Command { @@ -86,6 +88,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { None } @@ -116,6 +122,7 @@ impl Command { ) } .map(Some), + Stdio::InheritFile(_) => Err(unsupported()?), Stdio::Inherit => Ok(None), } } @@ -131,6 +138,7 @@ impl Command { ) } .map(Some), + Stdio::InheritFile(_) => Err(unsupported()?), Stdio::Inherit => Ok(None), Stdio::MakePipe => unsupported(), } @@ -138,7 +146,9 @@ impl Command { } pub fn output(command: &mut Command) -> io::Result<(ExitStatus, Vec, Vec)> { - let mut cmd = uefi_command_internal::Image::load_image(&command.prog)?; + let prog_path = resolve_program(&command.prog) + .ok_or(io::const_error!(io::ErrorKind::NotFound, "could not find the program."))?; + let mut cmd = uefi_command_internal::Image::load_image(prog_path.as_os_str())?; // UEFI adds the bin name by default if !command.args.is_empty() { @@ -147,7 +157,7 @@ pub fn output(command: &mut Command) -> io::Result<(ExitStatus, Vec, Vec } // Setup Stdout - let stdout = command.stdout.unwrap_or(Stdio::MakePipe); + let stdout = command.stdout.take().unwrap_or(Stdio::MakePipe); let stdout = Command::create_pipe(stdout)?; if let Some(con) = stdout { cmd.stdout_init(con) @@ -156,7 +166,7 @@ pub fn output(command: &mut Command) -> io::Result<(ExitStatus, Vec, Vec }; // Setup Stderr - let stderr = command.stderr.unwrap_or(Stdio::MakePipe); + let stderr = command.stderr.take().unwrap_or(Stdio::MakePipe); let stderr = Command::create_pipe(stderr)?; if let Some(con) = stderr { cmd.stderr_init(con) @@ -165,7 +175,7 @@ pub fn output(command: &mut Command) -> io::Result<(ExitStatus, Vec, Vec }; // Setup Stdin - let stdin = command.stdin.unwrap_or(Stdio::Null); + let stdin = command.stdin.take().unwrap_or(Stdio::Null); let stdin = Command::create_stdin(stdin)?; if let Some(con) = stdin { cmd.stdin_init(con) @@ -211,25 +221,19 @@ impl From for Stdio { impl From for Stdio { fn from(_: io::Stdout) -> Stdio { - // FIXME: This is wrong. - // Instead, the Stdio we have here should be a unit struct. - panic!("unsupported") + Stdio::Inherit } } impl From for Stdio { fn from(_: io::Stderr) -> Stdio { - // FIXME: This is wrong. - // Instead, the Stdio we have here should be a unit struct. - panic!("unsupported") + Stdio::Inherit } } impl From for Stdio { - fn from(_file: File) -> Stdio { - // FIXME: This is wrong. - // Instead, the Stdio we have here should be a unit struct. - panic!("unsupported") + fn from(file: File) -> Stdio { + Stdio::InheritFile(file) } } @@ -366,6 +370,36 @@ pub fn read_output( match out.diverge() {} } +// Search for programs similar to UEFI Shell defined in Section 3.6.1. It follows the following flow: +// 1. If program is already absolute path, just check if it exists. +// 2. For non-absolute path, search relative to current directory. +// 3. Search the path list sequentially. +// +// [UEFI Shell Specification](https://uefi.org/sites/default/files/resources/UEFI_Shell_2_2.pdf). +fn resolve_program + ?Sized>(prog: &S) -> Option { + let absolute_prog_path = crate::path::absolute(prog.as_ref()).ok()?; + + match crate::fs::exists(&absolute_prog_path) { + Ok(true) => return Some(absolute_prog_path), + // If program path was already absolute and is not found, then stop. + Ok(false) if Path::new(prog.as_ref()).is_absolute() => return None, + _ => {} + } + + // Search for the program in path. + if let Ok(path_var) = crate::env::var("path") { + for p in crate::env::split_paths(&path_var) { + let temp = p.join(prog.as_ref()); + + if let Ok(true) = crate::fs::exists(&temp) { + return Some(temp); + } + } + } + + None +} + #[allow(dead_code)] mod uefi_command_internal { use r_efi::protocols::{loaded_image, simple_text_input, simple_text_output}; @@ -606,7 +640,7 @@ mod uefi_command_internal { } if let Some((ptr, len)) = self.args { - let _ = unsafe { Box::from_raw(crate::ptr::slice_from_raw_parts_mut(ptr, len)) }; + let _ = unsafe { Box::from_raw(ptr.cast_slice(len)) }; } } } diff --git a/std/src/sys/process/unix/common.rs b/std/src/sys/process/unix/common.rs index 2d83782b7d0b9..8215b196127ac 100644 --- a/std/src/sys/process/unix/common.rs +++ b/std/src/sys/process/unix/common.rs @@ -15,7 +15,7 @@ use crate::sys::fs::File; #[cfg(not(target_os = "fuchsia"))] use crate::sys::fs::OpenOptions; use crate::sys::pipe::pipe; -use crate::sys::process::env::{CommandEnv, CommandEnvs}; +use crate::sys::process::env::{CommandEnv, CommandEnvs, CommandResolvedEnvs}; use crate::sys::{FromInner, IntoInner, cvt_r}; use crate::{fmt, io, mem}; @@ -267,6 +267,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { self.cwd.as_ref().map(|cs| Path::new(OsStr::from_bytes(cs.as_bytes()))) } diff --git a/std/src/sys/process/unix/common/cstring_array.rs b/std/src/sys/process/unix/common/cstring_array.rs index 1c840a85df9ba..c2a3fcf677522 100644 --- a/std/src/sys/process/unix/common/cstring_array.rs +++ b/std/src/sys/process/unix/common/cstring_array.rs @@ -35,10 +35,12 @@ impl CStringArray { /// Push an additional string to the array. pub fn push(&mut self, item: CString) { let argc = self.ptrs.len() - 1; - // Replace the null pointer at the end of the array... - self.ptrs[argc] = item.into_raw(); - // ... and recreate it to restore the data structure invariant. + // Amend the array by another null pointer first, to ensure that the + // array is null-terminated even when the `push` panics, in which case + // the array will be left undisturbed (see #155748). self.ptrs.push(ptr::null()); + // Now, replace the previous null pointer. + self.ptrs[argc] = item.into_raw(); } /// Returns a pointer to the C-string array managed by this type. diff --git a/std/src/sys/process/unix/fuchsia.rs b/std/src/sys/process/unix/fuchsia.rs index 3fae5ec1468b1..65ef7bf8c60c8 100644 --- a/std/src/sys/process/unix/fuchsia.rs +++ b/std/src/sys/process/unix/fuchsia.rs @@ -158,6 +158,11 @@ impl Process { unimplemented!() } + pub fn send_process_group_signal(&self, _signal: i32) -> io::Result<()> { + // Fuchsia doesn't have a direct equivalent for signals + unimplemented!() + } + pub fn wait(&mut self) -> io::Result { let mut proc_info: zx_info_process_t = Default::default(); let mut actual: size_t = 0; diff --git a/std/src/sys/process/unix/unix.rs b/std/src/sys/process/unix/unix.rs index a68be2543bc23..d476072a6449f 100644 --- a/std/src/sys/process/unix/unix.rs +++ b/std/src/sys/process/unix/unix.rs @@ -1002,6 +1002,19 @@ impl Process { cvt(unsafe { libc::kill(self.pid, signal) }).map(drop) } + pub(crate) fn send_process_group_signal(&self, signal: i32) -> io::Result<()> { + // See note in `send_signal` regarding recycled PIDs. + if self.status.is_some() { + return Ok(()); + } + #[cfg(target_os = "linux")] + if let Some(pid_fd) = self.pidfd.as_ref() { + // The `PIDFD_SIGNAL_PROCESS_GROUP` flag requires kernel >= 6.9 + return pid_fd.send_process_group_signal(signal); + } + cvt(unsafe { libc::killpg(self.pid, signal) }).map(drop) + } + pub fn wait(&mut self) -> io::Result { use crate::sys::cvt_r; if let Some(status) = self.status { diff --git a/std/src/sys/process/unix/unsupported.rs b/std/src/sys/process/unix/unsupported.rs index 9bda394f24659..17421d1e2e35d 100644 --- a/std/src/sys/process/unix/unsupported.rs +++ b/std/src/sys/process/unix/unsupported.rs @@ -49,6 +49,10 @@ impl Process { unsupported() } + pub fn send_process_group_signal(&self, _signal: i32) -> io::Result<()> { + unsupported() + } + pub fn wait(&mut self) -> io::Result { unsupported() } diff --git a/std/src/sys/process/unix/vxworks.rs b/std/src/sys/process/unix/vxworks.rs index 346ca6d74c9bd..c5acff2bdd3c5 100644 --- a/std/src/sys/process/unix/vxworks.rs +++ b/std/src/sys/process/unix/vxworks.rs @@ -161,6 +161,14 @@ impl Process { } } + pub fn send_process_group_signal(&self, signal: i32) -> io::Result<()> { + // See note in `send_signal` regarding recycled PIDs. + if self.status.is_some() { + return Ok(()); + } + cvt(unsafe { libc::killpg(self.pid, signal) }).map(drop) + } + pub fn wait(&mut self) -> io::Result { use crate::sys::cvt_r; if let Some(status) = self.status { diff --git a/std/src/sys/process/unsupported.rs b/std/src/sys/process/unsupported.rs index 9ed66a559117c..114f0001b7faf 100644 --- a/std/src/sys/process/unsupported.rs +++ b/std/src/sys/process/unsupported.rs @@ -1,4 +1,4 @@ -use super::env::{CommandEnv, CommandEnvs}; +use super::env::{CommandEnv, CommandEnvs, CommandResolvedEnvs}; pub use crate::ffi::OsString as EnvKey; use crate::ffi::{OsStr, OsString}; use crate::num::NonZero; @@ -89,6 +89,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { self.cwd.as_ref().map(|cs| Path::new(cs)) } diff --git a/std/src/sys/process/windows.rs b/std/src/sys/process/windows.rs index deb4243d314e2..a747ef048d901 100644 --- a/std/src/sys/process/windows.rs +++ b/std/src/sys/process/windows.rs @@ -5,7 +5,7 @@ mod tests; use core::ffi::c_void; -use super::env::{CommandEnv, CommandEnvs}; +use super::env::{CommandEnv, CommandEnvs, CommandResolvedEnvs}; use crate::collections::BTreeMap; use crate::env::consts::{EXE_EXTENSION, EXE_SUFFIX}; use crate::ffi::{OsStr, OsString}; @@ -256,6 +256,10 @@ impl Command { self.env.does_clear() } + pub fn get_resolved_envs(&self) -> CommandResolvedEnvs { + CommandResolvedEnvs::new(self.env.capture()) + } + pub fn get_current_dir(&self) -> Option<&Path> { self.cwd.as_ref().map(Path::new) } diff --git a/std/src/sys/process/windows/child_pipe.rs b/std/src/sys/process/windows/child_pipe.rs index da7a86ca072e3..8d71e1c61f82d 100644 --- a/std/src/sys/process/windows/child_pipe.rs +++ b/std/src/sys/process/windows/child_pipe.rs @@ -1,6 +1,8 @@ use crate::io::{self, BorrowedCursor, IoSlice, IoSliceMut}; use crate::ops::Neg; use crate::os::windows::prelude::*; +use crate::sync::atomic::Atomic; +use crate::sync::atomic::Ordering::Relaxed; use crate::sys::handle::Handle; use crate::sys::{FromInner, IntoInner, api, c}; use crate::{mem, ptr}; @@ -70,10 +72,19 @@ pub(super) fn child_pipe(ours_readable: bool, their_handle_inheritable: bool) -> let mut object_attributes = c::OBJECT_ATTRIBUTES::default(); object_attributes.Length = size_of::() as u32; - // Open a handle to the pipe filesystem (`\??\PIPE\`). - // This will be used when creating a new annon pipe. - let pipe_fs = { - let path = api::unicode_str!(r"\??\PIPE\"); + // Open a handle to the pipe filesystem (`\Device\NamedPipe\`). + // This will be used when creating a new anonymous pipe. + // + // We cache the handle once so we can reuse it without needing to reopen it each time. + // NOTE: this means the handle may appear to be leaked but that's fine because + // it's only one handle and the OS will clean it up when the process exits. + static PIPE_FS: Atomic = Atomic::::new(ptr::null_mut()); + let pipe_fs = if let handle = PIPE_FS.load(Relaxed) + && !handle.is_null() + { + handle + } else { + let path = api::unicode_str!(r"\Device\NamedPipe\"); object_attributes.ObjectName = path.as_ptr(); let mut pipe_fs = ptr::null_mut(); let status = c::NtOpenFile( @@ -85,7 +96,13 @@ pub(super) fn child_pipe(ours_readable: bool, their_handle_inheritable: bool) -> c::FILE_SYNCHRONOUS_IO_NONALERT, // synchronous access ); if c::nt_success(status) { - Handle::from_raw_handle(pipe_fs) + match PIPE_FS.compare_exchange(ptr::null_mut(), pipe_fs, Relaxed, Relaxed) { + Ok(_) => pipe_fs, + Err(existing) => { + c::CloseHandle(pipe_fs); + existing + } + } } else { return Err(io::Error::from_raw_os_error(c::RtlNtStatusToDosError(status) as i32)); } @@ -104,7 +121,7 @@ pub(super) fn child_pipe(ours_readable: bool, their_handle_inheritable: bool) -> let ours = { // Use the pipe filesystem as the root directory. // With no name provided, an anonymous pipe will be created. - object_attributes.RootDirectory = pipe_fs.as_raw_handle(); + object_attributes.RootDirectory = pipe_fs; // A negative timeout value is a relative time (rather than an absolute time). // The time is given in 100's of nanoseconds so this is 50 milliseconds. @@ -260,7 +277,7 @@ impl ChildPipe { Err(e) => Err(e), Ok(n) => { unsafe { - buf.advance_unchecked(n); + buf.advance(n); } Ok(()) } diff --git a/std/src/sys/random/mod.rs b/std/src/sys/random/mod.rs index 91f72d0738790..12346ef5a2edd 100644 --- a/std/src/sys/random/mod.rs +++ b/std/src/sys/random/mod.rs @@ -95,8 +95,8 @@ cfg_select! { pub use wasip1::fill_bytes; } all(target_os = "wasi", any(target_env = "p2", target_env = "p3")) => { - mod wasip2; - pub use wasip2::{fill_bytes, hashmap_random_keys}; + mod wasi; + pub use wasi::{fill_bytes, hashmap_random_keys}; } target_os = "zkvm" => { mod zkvm; diff --git a/std/src/sys/random/wasi.rs b/std/src/sys/random/wasi.rs new file mode 100644 index 0000000000000..80a9153bdb923 --- /dev/null +++ b/std/src/sys/random/wasi.rs @@ -0,0 +1,12 @@ +#[cfg(target_env = "p2")] +use wasip2::random::{insecure_seed::insecure_seed as get_insecure_seed, random::get_random_bytes}; +#[cfg(target_env = "p3")] +use wasip3::random::{insecure_seed::get_insecure_seed, random::get_random_bytes}; + +pub fn fill_bytes(bytes: &mut [u8]) { + bytes.copy_from_slice(&get_random_bytes(u64::try_from(bytes.len()).unwrap())); +} + +pub fn hashmap_random_keys() -> (u64, u64) { + get_insecure_seed() +} diff --git a/std/src/sys/random/wasip1.rs b/std/src/sys/random/wasip1.rs index d41da3751fc04..cb91575fe30ef 100644 --- a/std/src/sys/random/wasip1.rs +++ b/std/src/sys/random/wasip1.rs @@ -1,5 +1,5 @@ pub fn fill_bytes(bytes: &mut [u8]) { unsafe { - wasi::random_get(bytes.as_mut_ptr(), bytes.len()).expect("failed to generate random data") + wasip1::random_get(bytes.as_mut_ptr(), bytes.len()).expect("failed to generate random data") } } diff --git a/std/src/sys/random/wasip2.rs b/std/src/sys/random/wasip2.rs deleted file mode 100644 index a67c8a6428d18..0000000000000 --- a/std/src/sys/random/wasip2.rs +++ /dev/null @@ -1,9 +0,0 @@ -pub fn fill_bytes(bytes: &mut [u8]) { - bytes.copy_from_slice(&wasip2::random::random::get_random_bytes( - u64::try_from(bytes.len()).unwrap(), - )); -} - -pub fn hashmap_random_keys() -> (u64, u64) { - wasip2::random::insecure_seed::insecure_seed() -} diff --git a/std/src/sys/stdio/zkvm.rs b/std/src/sys/stdio/zkvm.rs index f31c6c26e87cd..84496ac937363 100644 --- a/std/src/sys/stdio/zkvm.rs +++ b/std/src/sys/stdio/zkvm.rs @@ -19,7 +19,7 @@ impl io::Read for Stdin { fn read_buf(&mut self, mut buf: BorrowedCursor<'_>) -> io::Result<()> { unsafe { let n = abi::sys_read(fileno::STDIN, buf.as_mut().as_mut_ptr().cast(), buf.capacity()); - buf.advance_unchecked(n); + buf.advance(n); } Ok(()) } diff --git a/std/src/sys/sync/mutex/no_threads.rs b/std/src/sys/sync/mutex/no_threads.rs index 57c78f454c57c..a1c2696079f86 100644 --- a/std/src/sys/sync/mutex/no_threads.rs +++ b/std/src/sys/sync/mutex/no_threads.rs @@ -26,6 +26,6 @@ impl Mutex { #[inline] pub fn try_lock(&self) -> bool { - self.locked.replace(true) == false + !self.locked.replace(true) } } diff --git a/std/src/sys/sync/rwlock/no_threads.rs b/std/src/sys/sync/rwlock/no_threads.rs index 6b919bde80bb5..6de5577504c43 100644 --- a/std/src/sys/sync/rwlock/no_threads.rs +++ b/std/src/sys/sync/rwlock/no_threads.rs @@ -18,7 +18,7 @@ impl RwLock { pub fn read(&self) { let m = self.mode.get(); if m >= 0 { - self.mode.set(m + 1); + self.mode.set(m.checked_add(1).expect("rwlock overflowed read locks")); } else { rtabort!("rwlock locked for writing"); } @@ -28,6 +28,9 @@ impl RwLock { pub fn try_read(&self) -> bool { let m = self.mode.get(); if m >= 0 { + if m == isize::MAX { + return false; + } self.mode.set(m + 1); true } else { @@ -56,16 +59,19 @@ impl RwLock { #[inline] pub unsafe fn read_unlock(&self) { - self.mode.set(self.mode.get() - 1); + assert!( + self.mode.replace(self.mode.get() - 1) > 0, + "rwlock has not been locked for reading" + ); } #[inline] pub unsafe fn write_unlock(&self) { - assert_eq!(self.mode.replace(0), -1); + assert_eq!(self.mode.replace(0), -1, "rwlock has not been locked for writing"); } #[inline] pub unsafe fn downgrade(&self) { - assert_eq!(self.mode.replace(1), -1); + assert_eq!(self.mode.replace(1), -1, "rwlock has not been locked for writing"); } } diff --git a/std/src/sys/thread/unix.rs b/std/src/sys/thread/unix.rs index 2f3ef1741cdfc..eb3fcff05ea9e 100644 --- a/std/src/sys/thread/unix.rs +++ b/std/src/sys/thread/unix.rs @@ -155,6 +155,8 @@ pub fn available_parallelism() -> io::Result> { target_os = "aix", target_vendor = "apple", target_os = "cygwin", + target_os = "redox", + target_os = "wasi", ) => { #[allow(unused_assignments)] #[allow(unused_mut)] @@ -315,7 +317,7 @@ pub fn available_parallelism() -> io::Result> { } } _ => { - // FIXME: implement on Redox, l4re + // FIXME: implement on l4re Err(io::const_error!(io::ErrorKind::Unsupported, "getting the number of hardware threads is not supported on the target platform")) } } diff --git a/std/src/sys/time/hermit.rs b/std/src/sys/time/hermit.rs index 4e8e5dfe21c8a..461319b162cc1 100644 --- a/std/src/sys/time/hermit.rs +++ b/std/src/sys/time/hermit.rs @@ -1,12 +1,13 @@ use hermit_abi::{self, CLOCK_MONOTONIC, CLOCK_REALTIME}; use crate::io; +use crate::sys::cvt; use crate::sys::pal::time::Timespec; use crate::time::Duration; fn clock_gettime(clock: hermit_abi::clockid_t) -> Timespec { let mut t = hermit_abi::timespec { tv_sec: 0, tv_nsec: 0 }; - unsafe { hermit_abi::clock_gettime(clock, &raw mut t) }.unwrap(); + cvt(unsafe { hermit_abi::clock_gettime(clock, &raw mut t) }).unwrap(); Timespec::new(t.tv_sec, t.tv_nsec.into()).unwrap() } diff --git a/std/src/sys/time/windows.rs b/std/src/sys/time/windows.rs index 2e38dbf5cf288..b2abee4219fe3 100644 --- a/std/src/sys/time/windows.rs +++ b/std/src/sys/time/windows.rs @@ -35,7 +35,14 @@ impl Instant { let freq = perf_counter::frequency() as u64; let now = perf_counter::now(); + + // We convert now to `u64` to be able to use `Duration`. let instant_nsec = mul_div_u64(now as u64, NANOS_PER_SEC, freq); + // We can add an arbitrary offset to shift the epoch of this clock. We do that to avoid + // being too close to 0 which would lead to underflow when computing times in the past. Also + // see . + let instant_nsec = instant_nsec + (u64::MAX / 4); + Self { t: Duration::from_nanos(instant_nsec) } } diff --git a/std/src/thread/lifecycle.rs b/std/src/thread/lifecycle.rs index 0bb1f347ffaad..af239bee55189 100644 --- a/std/src/thread/lifecycle.rs +++ b/std/src/thread/lifecycle.rs @@ -7,7 +7,7 @@ use super::thread::Thread; use super::{Result, spawnhook}; use crate::cell::UnsafeCell; use crate::marker::PhantomData; -use crate::mem::{ManuallyDrop, MaybeUninit}; +use crate::mem::MaybeDangling; use crate::sync::Arc; use crate::sync::atomic::{Atomic, AtomicUsize, Ordering}; use crate::sys::{AsInner, IntoInner, thread as imp}; @@ -57,29 +57,8 @@ where Arc::new(Packet { scope: scope_data, result: UnsafeCell::new(None), _marker: PhantomData }); let their_packet = my_packet.clone(); - // Pass `f` in `MaybeUninit` because actually that closure might *run longer than the lifetime of `F`*. + // Pass `f` in `MaybeDangling` because actually that closure might *run longer than the lifetime of `F`*. // See for more details. - // To prevent leaks we use a wrapper that drops its contents. - #[repr(transparent)] - struct MaybeDangling(MaybeUninit); - impl MaybeDangling { - fn new(x: T) -> Self { - MaybeDangling(MaybeUninit::new(x)) - } - fn into_inner(self) -> T { - // Make sure we don't drop. - let this = ManuallyDrop::new(self); - // SAFETY: we are always initialized. - unsafe { this.0.assume_init_read() } - } - } - impl Drop for MaybeDangling { - fn drop(&mut self) { - // SAFETY: we are always initialized. - unsafe { self.0.assume_init_drop() }; - } - } - let f = MaybeDangling::new(f); // The entrypoint of the Rust thread, after platform-specific thread diff --git a/std/src/thread/scoped.rs b/std/src/thread/scoped.rs index 929f7fdc6dcac..d8e018bde7471 100644 --- a/std/src/thread/scoped.rs +++ b/std/src/thread/scoped.rs @@ -177,7 +177,7 @@ impl<'scope, 'env> Scope<'scope, 'env> { /// Spawns a new thread within a scope, returning a [`ScopedJoinHandle`] for it. /// /// Unlike non-scoped threads, threads spawned with this function may - /// borrow non-`'static` data from the outside the scope. See [`scope`] for + /// borrow non-`'static` data from outside the scope. See [`scope`] for /// details. /// /// The join handle provides a [`join`] method that can be used to join the spawned diff --git a/std/src/time.rs b/std/src/time.rs index 1805d8926098d..1f31ea5ced9d7 100644 --- a/std/src/time.rs +++ b/std/src/time.rs @@ -425,6 +425,7 @@ impl Add for Instant { /// /// This function may panic if the resulting point in time cannot be represented by the /// underlying data structure. See [`Instant::checked_add`] for a version without panic. + #[track_caller] fn add(self, other: Duration) -> Instant { self.checked_add(other).expect("overflow when adding duration to instant") } @@ -441,6 +442,7 @@ impl AddAssign for Instant { impl Sub for Instant { type Output = Instant; + #[track_caller] fn sub(self, other: Duration) -> Instant { self.checked_sub(other).expect("overflow when subtracting duration from instant") } @@ -742,8 +744,9 @@ impl Add for SystemTime { /// /// This function may panic if the resulting point in time cannot be represented by the /// underlying data structure. See [`SystemTime::checked_add`] for a version without panic. + #[track_caller] fn add(self, dur: Duration) -> SystemTime { - self.checked_add(dur).expect("overflow when adding duration to instant") + self.checked_add(dur).expect("overflow when adding duration to `SystemTime`") } } @@ -758,8 +761,9 @@ impl AddAssign for SystemTime { impl Sub for SystemTime { type Output = SystemTime; + #[track_caller] fn sub(self, dur: Duration) -> SystemTime { - self.checked_sub(dur).expect("overflow when subtracting duration from instant") + self.checked_sub(dur).expect("overflow when subtracting duration from `SystemTime`") } } diff --git a/std/tests/pipe_subprocess.rs b/std/tests/pipe_subprocess.rs index c51a4459e718b..dad1ea6c57377 100644 --- a/std/tests/pipe_subprocess.rs +++ b/std/tests/pipe_subprocess.rs @@ -1,4 +1,5 @@ fn main() { + // No `Command` on Miri and emscripten #[cfg(all(not(miri), any(unix, windows), not(target_os = "emscripten")))] { use std::io::{Read, pipe}; diff --git a/std/tests/sync/lazy_lock.rs b/std/tests/sync/lazy_lock.rs index 68aeea834b4fa..c549094dd1381 100644 --- a/std/tests/sync/lazy_lock.rs +++ b/std/tests/sync/lazy_lock.rs @@ -33,6 +33,15 @@ fn lazy_default() { assert_eq!(CALLED.load(SeqCst), 1); } +#[test] +fn const_lazy_default() { + // using Box as it cannot be initialized in const contexts + const X: LazyLock> = <_>::default(); + const Y: LazyCell> = <_>::default(); + assert_eq!(**X, 0); + assert_eq!(**Y, 0); +} + #[test] #[cfg_attr(any(target_os = "emscripten", target_os = "wasi"), ignore)] // no threads fn sync_lazy_new() { diff --git a/std/tests/sync/lib.rs b/std/tests/sync/lib.rs index 32a7efde2a257..92c4c2f511be3 100644 --- a/std/tests/sync/lib.rs +++ b/std/tests/sync/lib.rs @@ -1,3 +1,5 @@ +#![feature(const_default)] +#![feature(const_trait_impl)] #![feature(mapped_lock_guards)] #![feature(mpmc_channel)] #![feature(oneshot_channel)] diff --git a/std/tests/sync/mpmc.rs b/std/tests/sync/mpmc.rs index db221ff15890e..e8ed5ab13d009 100644 --- a/std/tests/sync/mpmc.rs +++ b/std/tests/sync/mpmc.rs @@ -419,34 +419,48 @@ fn oneshot_multi_thread_send_recv_stress() { #[test] fn stream_send_recv_stress() { - for _ in 0..stress_factor() { - let (tx, rx) = channel(); - - send(tx, 0); - recv(rx, 0); + thread::scope(|s| { + for _ in 0..stress_factor() { + let (tx, rx) = channel(); + + send(tx, 0, s); + recv(rx, 0, s); + + fn send<'scope, 'env>( + tx: Sender>, + i: i32, + s: &'scope thread::Scope<'scope, 'env>, + ) where + 'env: 'scope, + { + if i == 10 { + return; + } - fn send(tx: Sender>, i: i32) { - if i == 10 { - return; + s.spawn(move || { + tx.send(Box::new(i)).unwrap(); + send(tx, i + 1, s); + }); } - thread::spawn(move || { - tx.send(Box::new(i)).unwrap(); - send(tx, i + 1); - }); - } + fn recv<'scope, 'env>( + rx: Receiver>, + i: i32, + s: &'scope thread::Scope<'scope, 'env>, + ) where + 'env: 'scope, + { + if i == 10 { + return; + } - fn recv(rx: Receiver>, i: i32) { - if i == 10 { - return; + s.spawn(move || { + assert!(*rx.recv().unwrap() == i); + recv(rx, i + 1, s); + }); } - - thread::spawn(move || { - assert!(*rx.recv().unwrap() == i); - recv(rx, i + 1); - }); } - } + }) } #[test] diff --git a/std/tests/sync/mpsc.rs b/std/tests/sync/mpsc.rs index 4dc4b955da7c2..f1364dda713a1 100644 --- a/std/tests/sync/mpsc.rs +++ b/std/tests/sync/mpsc.rs @@ -382,34 +382,48 @@ fn oneshot_multi_thread_send_recv_stress() { #[test] fn stream_send_recv_stress() { - for _ in 0..stress_factor() { - let (tx, rx) = channel(); - - send(tx, 0); - recv(rx, 0); + thread::scope(|s| { + for _ in 0..stress_factor() { + let (tx, rx) = channel(); + + send(tx, 0, s); + recv(rx, 0, s); + + fn send<'scope, 'env>( + tx: Sender>, + i: i32, + s: &'scope thread::Scope<'scope, 'env>, + ) where + 'env: 'scope, + { + if i == 10 { + return; + } - fn send(tx: Sender>, i: i32) { - if i == 10 { - return; + s.spawn(move || { + tx.send(Box::new(i)).unwrap(); + send(tx, i + 1, s); + }); } - thread::spawn(move || { - tx.send(Box::new(i)).unwrap(); - send(tx, i + 1); - }); - } + fn recv<'scope, 'env>( + rx: Receiver>, + i: i32, + s: &'scope thread::Scope<'scope, 'env>, + ) where + 'env: 'scope, + { + if i == 10 { + return; + } - fn recv(rx: Receiver>, i: i32) { - if i == 10 { - return; + s.spawn(move || { + assert!(*rx.recv().unwrap() == i); + recv(rx, i + 1, s); + }); } - - thread::spawn(move || { - assert!(*rx.recv().unwrap() == i); - recv(rx, i + 1); - }); } - } + }) } #[test] diff --git a/std/tests/sync/rwlock.rs b/std/tests/sync/rwlock.rs index 392c45c8ba05d..7369d671f873a 100644 --- a/std/tests/sync/rwlock.rs +++ b/std/tests/sync/rwlock.rs @@ -7,7 +7,7 @@ use std::sync::{ Arc, MappedRwLockReadGuard, MappedRwLockWriteGuard, RwLock, RwLockReadGuard, RwLockWriteGuard, TryLockError, }; -use std::{hint, mem, thread}; +use std::{hint, mem, thread, u32}; use rand::Rng; @@ -883,3 +883,70 @@ fn test_rwlock_with_mut() { assert_eq!(*rwlock.read(), 5); assert_eq!(result, 10); } + +// To note: there are (currently) four different implementations of Rwlock: +// - On Windows (but not Win 7), Linux, Android, FreeBSD, OpenBSD, DragonFly, +// Fuchsia, WASM, Hermit, and Motor OSs, it relies on rwlock/futex.rs, which has +// a max reader of 1 << 30 - 2 (or 1073741822). A "too many active reader" error +// is displayed after it exceeds the max number of readers. +// - On Unix, Win 7, Fortranix (target env of sgx), Xous, and TeeOS, it leans +// on rwlock/queue.rs, which uses a linked list under the hood stored on the stack +// to hold a queue of waiters. Assuming no stack overflow, the max number of readers +// that can be queued up at one time is limited to usize::MAX - (1 << 4) as the first +// four bits are reserved for LOCKED, QUEUED, QUEUE_LOCKED, and DOWNGRADED flags. Any +// pending readers after that max count, parks the thread and tries to acquire a read lock +// again when the thread wakes up. +// - On SolidASP3, it leans on rwlock/solid.rs, which utilizes rwl_loc_rdl, so the max +// number of readers depends on the internal implementation of rwl_loc_rdl. +// - Every other platforms utilizes rwlock/no_threads.rs, which has a max reader of +// isize::MAX. An arithmetic overflow error occurs if it exceeds the max reader count. +#[test] +fn test_rwlock_max_readers() { + let mut read_lock_ctr: u32 = 0; + let rwlock: RwLock = RwLock::new(0); + + const MAX_READERS: u32 = cfg_select! { + miri => 100, + any( + all(target_os = "windows", not(target_vendor = "win7")), + target_os = "linux", + target_os = "android", + target_os = "freebsd", + target_os = "openbsd", + target_os = "dragonfly", + target_os = "fuchsia", + all(target_family = "wasm", target_feature = "atomics"), + target_os = "hermit", + target_os = "motor", + ) => { + (1 << 30) - 2 + }, + any( + target_family = "unix", + all(target_os = "windows", target_vendor = "win7", target_pointer_width = "64"), + all(target_vendor = "fortanix", target_env = "sgx"), + target_os = "xous", + target_os = "teeos", + ) => { + u32::MAX + }, + // Otherwise a form of deadlock is observed. + all(target_os = "windows", target_vendor = "win7", target_pointer_width = "32") => { + (1 << 28) - 1 + }, + target_os = "solid_asp3" => { + (1 << 30) + }, + _ => { + u32::MAX + } + }; + + while read_lock_ctr < MAX_READERS { + let lock = rwlock.read(); + mem::forget(lock); + read_lock_ctr += 1; + } + + assert_eq!(read_lock_ctr, MAX_READERS); +} diff --git a/std/tests/thread.rs b/std/tests/thread.rs index dc8eadd75148b..ef13ce44d3180 100644 --- a/std/tests/thread.rs +++ b/std/tests/thread.rs @@ -85,7 +85,6 @@ fn thread_local_hygeiene() { target_env = "sgx", target_os = "solid_asp3", target_os = "teeos", - target_os = "wasi" ), should_panic )] diff --git a/std/tests/time.rs b/std/tests/time.rs index b73e7bc3962eb..d6736e25ace18 100644 --- a/std/tests/time.rs +++ b/std/tests/time.rs @@ -1,4 +1,5 @@ #![feature(duration_constants)] +#![feature(duration_constructors)] #![feature(time_systemtime_limits)] #![feature(time_saturating_systemtime)] @@ -104,7 +105,8 @@ fn instant_math_is_associative() { #[test] fn instant_duration_since_saturates() { let a = Instant::now(); - assert_eq!((a - Duration::SECOND).duration_since(a), Duration::ZERO); + // This also checks that computing an instant before program startup works. + assert_eq!((a - Duration::from_days(1)).duration_since(a), Duration::ZERO); } #[test] diff --git a/std/tests/windows_unix_socket.rs b/std/tests/windows_unix_socket.rs index 1d16ec9ed8414..dd71b1f135dce 100644 --- a/std/tests/windows_unix_socket.rs +++ b/std/tests/windows_unix_socket.rs @@ -1,5 +1,5 @@ #![cfg(windows)] -#![cfg(not(miri))] // no socket support in Miri +#![cfg(not(miri))] // no Windows socket support in Miri #![feature(windows_unix_domain_sockets)] // Now only test windows_unix_domain_sockets feature // in the future, will test both unix and windows uds diff --git a/std_detect/src/detect/arch/loongarch.rs b/std_detect/src/detect/arch/loongarch.rs index 6299627738111..b37f44972a74f 100644 --- a/std_detect/src/detect/arch/loongarch.rs +++ b/std_detect/src/detect/arch/loongarch.rs @@ -35,19 +35,19 @@ features! { /// D @FEATURE: #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] frecipe: "frecipe"; /// Frecipe - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] div32: "div32"; + @FEATURE: #[stable(feature = "stdarch_loongarch_div32", since = "1.97.0")] div32: "div32"; /// Div32 @FEATURE: #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] lsx: "lsx"; /// LSX @FEATURE: #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] lasx: "lasx"; /// LASX - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] lam_bh: "lam-bh"; + @FEATURE: #[stable(feature = "stdarch_loongarch_lam_bh", since = "1.97.0")] lam_bh: "lam-bh"; /// LAM-BH - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] lamcas: "lamcas"; + @FEATURE: #[stable(feature = "stdarch_loongarch_lamcas", since = "1.97.0")] lamcas: "lamcas"; /// LAM-CAS - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] ld_seq_sa: "ld-seq-sa"; + @FEATURE: #[stable(feature = "stdarch_loongarch_ld_seq_sa", since = "1.97.0")] ld_seq_sa: "ld-seq-sa"; /// LD-SEQ-SA - @FEATURE: #[unstable(feature = "stdarch_loongarch_feature_detection", issue = "117425")] scq: "scq"; + @FEATURE: #[stable(feature = "stdarch_loongarch_scq", since = "1.97.0")] scq: "scq"; /// SCQ @FEATURE: #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] lbt: "lbt"; /// LBT diff --git a/std_detect/src/detect/arch/x86.rs b/std_detect/src/detect/arch/x86.rs index 4c3a71ebc5ee7..ede4a80c088ed 100644 --- a/std_detect/src/detect/arch/x86.rs +++ b/std_detect/src/detect/arch/x86.rs @@ -106,6 +106,7 @@ features! { /// * `"xsaves"` /// * `"xsavec"` /// * `"cmpxchg16b"` + /// * `"clflushopt"` /// * `"kl"` /// * `"widekl"` /// * `"adx"` @@ -261,6 +262,8 @@ features! { /// XSAVEC (Save Processor Extended States Compacted) @FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] cmpxchg16b: "cmpxchg16b"; /// CMPXCH16B (16-byte compare-and-swap instruction) + @FEATURE: #[unstable(feature = "clflushopt_target_feature", issue = "157096")] clflushopt: "clflushopt"; + /// CLFLUSHOPT (Cache Line Flush Optimized) @FEATURE: #[stable(feature = "keylocker_x86", since = "1.89.0")] kl: "kl"; /// Intel Key Locker @FEATURE: #[stable(feature = "keylocker_x86", since = "1.89.0")] widekl: "widekl"; diff --git a/std_detect/src/detect/os/windows/aarch64.rs b/std_detect/src/detect/os/windows/aarch64.rs index 937f9f26eedc1..825e16bc2f864 100644 --- a/std_detect/src/detect/os/windows/aarch64.rs +++ b/std_detect/src/detect/os/windows/aarch64.rs @@ -31,8 +31,14 @@ pub(crate) fn detect_features() -> cache::Initializer { const PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE: u32 = 55; const PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE: u32 = 56; // const PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE: u32 = 57; - // const PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE: u32 = 58; - // const PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE: u32 = 59; + const PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE: u32 = 58; + const PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE: u32 = 59; + const PF_ARM_LSE2_AVAILABLE: u32 = 62; + const PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE: u32 = 64; + const PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE: u32 = 65; + const PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE: u32 = 66; + const PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE: u32 = 67; + const PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE: u32 = 68; unsafe extern "system" { fn IsProcessorFeaturePresent(ProcessorFeature: DWORD) -> BOOL; @@ -46,9 +52,11 @@ pub(crate) fn detect_features() -> cache::Initializer { } }; - // Some features may be supported on current CPU, - // but no way to detect it by OS API. - // Also, we require unsafe block for the extern "system" calls. + // Some features may be supported on the current CPU but have no + // detection path through the Win32 API; those report `false`. + // SAFETY: `IsProcessorFeaturePresent` is a Win32 entry point taking a + // `DWORD` by value and returning a `BOOL`. No pointer parameters, + // no out-parameters, no thread-safety constraints. unsafe { enable_feature( Feature::fp, @@ -112,6 +120,46 @@ pub(crate) fn detect_features() -> cache::Initializer { Feature::sve2_sm4, IsProcessorFeaturePresent(PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE) != FALSE, ); + enable_feature( + Feature::f32mm, + IsProcessorFeaturePresent(PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::f64mm, + IsProcessorFeaturePresent(PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::lse2, + IsProcessorFeaturePresent(PF_ARM_LSE2_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::fp16, + IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::i8mm, + IsProcessorFeaturePresent(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + enable_feature( + Feature::bf16, + IsProcessorFeaturePresent(PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + // stdarch `sha3` is FEAT_SHA3 + FEAT_SHA512 together; Windows + // exposes them as two separate flags. + enable_feature( + Feature::sha3, + IsProcessorFeaturePresent(PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE) != FALSE + && IsProcessorFeaturePresent(PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE) != FALSE, + ); + // No PF_ARM_RDM_* constant exists. Derive FEAT_RDM from FEAT_DotProd: + // DotProd is an optional v8.2-A feature only present on cores that + // implement at least v8.1-A; v8.1-A with AdvSIMD mandates FEAT_RDM + // (Arm ARM K.a §D17.2.91), and AdvSIMD is universal on Windows-on-ARM. + // Same inference shipped in .NET 10 (dotnet/runtime PR 109493). + enable_feature( + Feature::rdm, + IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != FALSE, + ); // PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE means aes, sha1, sha2 and // pmull support let crypto = diff --git a/std_detect/src/detect/os/x86.rs b/std_detect/src/detect/os/x86.rs index b24ef6a37ef55..2b75cd6257087 100644 --- a/std_detect/src/detect/os/x86.rs +++ b/std_detect/src/detect/os/x86.rs @@ -127,6 +127,8 @@ pub(crate) fn detect_features() -> cache::Initializer { enable(extended_features_ebx, 9, Feature::ermsb); + enable(extended_features_ebx, 23, Feature::clflushopt); + enable(extended_features_eax_leaf_1, 31, Feature::movrs); // Detect if CPUID.19h available diff --git a/std_detect/tests/cpu-detection.rs b/std_detect/tests/cpu-detection.rs index 0aad088af7de5..f0b276072108d 100644 --- a/std_detect/tests/cpu-detection.rs +++ b/std_detect/tests/cpu-detection.rs @@ -150,14 +150,22 @@ fn aarch64_linux() { fn aarch64_windows() { println!("asimd: {:?}", is_aarch64_feature_detected!("asimd")); println!("fp: {:?}", is_aarch64_feature_detected!("fp")); + println!("fp16: {:?}", is_aarch64_feature_detected!("fp16")); println!("crc: {:?}", is_aarch64_feature_detected!("crc")); println!("lse: {:?}", is_aarch64_feature_detected!("lse")); + println!("lse2: {:?}", is_aarch64_feature_detected!("lse2")); + println!("rdm: {:?}", is_aarch64_feature_detected!("rdm")); println!("dotprod: {:?}", is_aarch64_feature_detected!("dotprod")); + println!("i8mm: {:?}", is_aarch64_feature_detected!("i8mm")); + println!("bf16: {:?}", is_aarch64_feature_detected!("bf16")); println!("jsconv: {:?}", is_aarch64_feature_detected!("jsconv")); println!("rcpc: {:?}", is_aarch64_feature_detected!("rcpc")); println!("aes: {:?}", is_aarch64_feature_detected!("aes")); println!("pmull: {:?}", is_aarch64_feature_detected!("pmull")); println!("sha2: {:?}", is_aarch64_feature_detected!("sha2")); + println!("sha3: {:?}", is_aarch64_feature_detected!("sha3")); + println!("f32mm: {:?}", is_aarch64_feature_detected!("f32mm")); + println!("f64mm: {:?}", is_aarch64_feature_detected!("f64mm")); } #[test] diff --git a/std_detect/tests/x86-specific.rs b/std_detect/tests/x86-specific.rs index 90ca32208e78d..4b02f78b7944e 100644 --- a/std_detect/tests/x86-specific.rs +++ b/std_detect/tests/x86-specific.rs @@ -1,6 +1,12 @@ #![cfg(any(target_arch = "x86", target_arch = "x86_64"))] #![allow(internal_features)] -#![feature(stdarch_internal, x86_amx_intrinsics, xop_target_feature, movrs_target_feature)] +#![feature( + stdarch_internal, + x86_amx_intrinsics, + xop_target_feature, + movrs_target_feature, + clflushopt_target_feature +)] #[macro_use] extern crate std_detect; @@ -58,6 +64,7 @@ fn dump() { println!("xsaves: {:?}", is_x86_feature_detected!("xsaves")); println!("xsavec: {:?}", is_x86_feature_detected!("xsavec")); println!("cmpxchg16b: {:?}", is_x86_feature_detected!("cmpxchg16b")); + println!("clflushopt: {:?}", is_x86_feature_detected!("clflushopt")); println!("adx: {:?}", is_x86_feature_detected!("adx")); println!("rtm: {:?}", is_x86_feature_detected!("rtm")); println!("movbe: {:?}", is_x86_feature_detected!("movbe")); diff --git a/stdarch/.github/workflows/main.yml b/stdarch/.github/workflows/main.yml index 3749ed1f6ac81..98f6b842d135f 100644 --- a/stdarch/.github/workflows/main.yml +++ b/stdarch/.github/workflows/main.yml @@ -96,16 +96,17 @@ jobs: os: ubuntu-latest - tuple: loongarch64-unknown-linux-gnu os: ubuntu-latest - - tuple: hexagon-unknown-linux-musl - os: ubuntu-latest + # hexagon doesn't build at the moment due to a libc issue. + # - tuple: hexagon-unknown-linux-musl + # os: ubuntu-latest - tuple: wasm32-wasip1 os: ubuntu-latest # macOS targets - tuple: x86_64-apple-darwin - os: macos-15-large + os: macos-15-intel - tuple: x86_64-apple-ios-macabi - os: macos-15-large + os: macos-15-intel - tuple: aarch64-apple-darwin os: macos-15 - tuple: aarch64-apple-ios-macabi @@ -209,11 +210,12 @@ jobs: tuple: amdgcn-amd-amdhsa os: ubuntu-latest norun: true - - target: - tuple: hexagon-unknown-linux-musl - os: ubuntu-latest - norun: true - build_std: true + # hexagon doesn't build at the moment due to a libc issue. + # - target: + # tuple: hexagon-unknown-linux-musl + # os: ubuntu-latest + # norun: true + # build_std: true steps: - uses: actions/checkout@v6 @@ -270,20 +272,28 @@ jobs: intrinsic-test: needs: [style] name: Intrinsic Test - runs-on: ubuntu-latest + runs-on: ubuntu-latest strategy: matrix: target: - aarch64-unknown-linux-gnu - aarch64_be-unknown-linux-gnu - armv7-unknown-linux-gnueabihf - - arm-unknown-linux-gnueabihf - x86_64-unknown-linux-gnu profile: [dev, release] + cc: [clang, gcc] include: - target: aarch64_be-unknown-linux-gnu build_std: true - + - target: x86_64-unknown-linux-gnu + cc: icx + profile: dev + - target: x86_64-unknown-linux-gnu + cc: icx + profile: release + exclude: + - target: armv7-unknown-linux-gnueabihf + cc: gcc steps: - uses: actions/checkout@v6 - name: Install Rust @@ -296,10 +306,11 @@ jobs: rustup component add rust-src echo "CARGO_UNSTABLE_BUILD_STD=std" >> $GITHUB_ENV if: ${{ matrix.build_std }} + - run: rustup component add rustfmt # Configure some env vars based on matrix configuration - run: echo "PROFILE=${{ matrix.profile }}" >> $GITHUB_ENV - - run: ./ci/intrinsic-test-docker.sh ${{ matrix.target }} + - run: ./ci/intrinsic-test-docker.sh ${{ matrix.target }} ${{ matrix.cc }} if: ${{ !startsWith(matrix.target, 'thumb') }} env: TARGET: ${{ matrix.target }} @@ -307,7 +318,7 @@ jobs: # Check that the generated files agree with the checked-in versions. check-stdarch-gen: needs: [style] - name: Check stdarch-gen-{arm, loongarch, hexagon} output + name: Check stdarch-gen-{arm, loongarch, hexagon, hexagon-scalar} output runs-on: ubuntu-latest steps: - uses: actions/checkout@v6 @@ -329,12 +340,39 @@ jobs: run: | cargo run -p stdarch-gen-hexagon --release git diff --exit-code + - name: Check hexagon scalar + run: | + cargo run -p stdarch-gen-hexagon-scalar --release + git diff --exit-code + + # Run some tests with Miri. Most stdarch functions use platform-specific intrinsics + # that Miri does not support. Also Miri is reltively slow. + # + # Below we run some tests where Miri might catch UB, for instance on intrinsics that read from + # or write to pointers. + miri: + needs: [style] + name: Run some tests with miri + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v6 + - name: Install Rust + run: rustup update nightly && rustup default nightly && rustup component add miri + - name: Run miri tests + env: + TARGET: "aarch64-unknown-linux-gnu" + RUSTFLAGS: "-Ctarget-cpu=neoverse-v3" + run: | + # read filters and join them with a space. + FILTERS=$(cat aarch64-miri-tests.txt | tr '\n' ' ') + cargo miri test -p core_arch --target aarch64-unknown-linux-gnu -- $FILTERS conclusion: needs: - docs - verify - test + - miri - intrinsic-test - check-stdarch-gen runs-on: ubuntu-latest diff --git a/stdarch/.github/workflows/rustc-pull.yml b/stdarch/.github/workflows/rustc-pull.yml index ee0c498878f42..d2feb1add6344 100644 --- a/stdarch/.github/workflows/rustc-pull.yml +++ b/stdarch/.github/workflows/rustc-pull.yml @@ -13,6 +13,7 @@ jobs: uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main with: github-app-id: ${{ vars.APP_CLIENT_ID }} + pr-author: "workflows-stdarch[bot]" # https://rust-lang.zulipchat.com/#narrow/channel/208962-t-libs.2Fstdarch/topic/Subtree.20sync.20automation/with/528461782 zulip-stream-id: 208962 zulip-bot-email: "stdarch-ci-bot@rust-lang.zulipchat.com" diff --git a/stdarch/Cargo.lock b/stdarch/Cargo.lock index 7e7cb592889a8..a1c31fa9f0cea 100644 --- a/stdarch/Cargo.lock +++ b/stdarch/Cargo.lock @@ -13,9 +13,9 @@ dependencies = [ [[package]] name = "anstream" -version = "0.6.21" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "43d5b281e737544384e969a5ccad3f1cdd24b48086a0fc1b2a5262a26b8f4f4a" +checksum = "824a212faf96e9acacdbd09febd34438f8f711fb84e09a8916013cd7815ca28d" dependencies = [ "anstyle", "anstyle-parse", @@ -28,15 +28,15 @@ dependencies = [ [[package]] name = "anstyle" -version = "1.0.13" +version = "1.0.14" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5192cca8006f1fd4f7237516f40fa183bb07f8fbdfedaa0036de5ea9b0b45e78" +checksum = "940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000" [[package]] name = "anstyle-parse" -version = "0.2.7" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4e7644824f0aa2c7b9384579234ef10eb7efb6a0deb83f9630a49594dd9c15c2" +checksum = "52ce7f38b242319f7cabaa6813055467063ecdc9d355bbb4ce0c68908cd8130e" dependencies = [ "utf8parse", ] @@ -63,9 +63,9 @@ dependencies = [ [[package]] name = "anyhow" -version = "1.0.101" +version = "1.0.102" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5f0e0fee31ef5ed1ba1316088939cea399010ed7731dba877ed44aeb407a75ea" +checksum = "7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c" [[package]] name = "assert-instr-macro" @@ -84,15 +84,15 @@ checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" [[package]] name = "bitflags" -version = "2.10.0" +version = "2.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "812e12b5285cc515a9c72a5c1d3b6d46a19dac5acfef5265968c166106e31dd3" +checksum = "843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af" [[package]] name = "cc" -version = "1.2.55" +version = "1.2.59" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "47b26a0954ae34af09b50f0de26458fa95369a0d478d8236d3f93082b219bd29" +checksum = "b7a4d3ec6524d28a329fc53654bbadc9bdd7b0431f5d65f1a56ffb28a1ee5283" dependencies = [ "find-msvc-tools", "shlex", @@ -106,9 +106,9 @@ checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" [[package]] name = "clap" -version = "4.5.58" +version = "4.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "63be97961acde393029492ce0be7a1af7e323e6bae9511ebfac33751be5e6806" +checksum = "b193af5b67834b676abd72466a96c1024e6a6ad978a1f484bd90b85c94041351" dependencies = [ "clap_builder", "clap_derive", @@ -116,9 +116,9 @@ dependencies = [ [[package]] name = "clap_builder" -version = "4.5.58" +version = "4.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7f13174bda5dfd69d7e947827e5af4b0f2f94a4a3ee92912fba07a66150f21e2" +checksum = "714a53001bf66416adb0e2ef5ac857140e7dc3a0c48fb28b2f10762fc4b5069f" dependencies = [ "anstream", "anstyle", @@ -128,9 +128,9 @@ dependencies = [ [[package]] name = "clap_derive" -version = "4.5.55" +version = "4.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a92793da1a46a5f2a02a6f4c46c6496b28c43638adea8306fcb0caa1634f24e5" +checksum = "1110bd8a634a1ab8cb04345d8d878267d57c3cf1b38d91b71af6686408bbca6a" dependencies = [ "heck", "proc-macro2", @@ -140,15 +140,15 @@ dependencies = [ [[package]] name = "clap_lex" -version = "1.0.0" +version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3a822ea5bc7590f9d40f1ba12c0dc3c2760f3482c6984db1573ad11031420831" +checksum = "c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9" [[package]] name = "colorchoice" -version = "1.0.4" +version = "1.0.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b05b61dc5112cbb17e4b6cd61790d9845d13888356391624cbe7e41efeac1e75" +checksum = "1d07550c9036bf2ae0c684c4297d503f838287c83c53686d05370d0e139ae570" [[package]] name = "core_arch" @@ -185,9 +185,9 @@ checksum = "d0a5c400df2834b80a4c3327b3aad3a4c4cd4de0629063962b03235697506a28" [[package]] name = "darling" -version = "0.21.3" +version = "0.23.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9cdf337090841a411e2a7f3deb9187445851f91b309c0c0a29e05f74a00a48c0" +checksum = "25ae13da2f202d56bd7f91c25fba009e7717a1e4a1cc98a76d844b65ae912e9d" dependencies = [ "darling_core", "darling_macro", @@ -195,11 +195,10 @@ dependencies = [ [[package]] name = "darling_core" -version = "0.21.3" +version = "0.23.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1247195ecd7e3c85f83c8d2a366e4210d588e802133e1e355180a9870b517ea4" +checksum = "9865a50f7c335f53564bb694ef660825eb8610e0a53d3e11bf1b0d3df31e03b0" dependencies = [ - "fnv", "ident_case", "proc-macro2", "quote", @@ -209,9 +208,9 @@ dependencies = [ [[package]] name = "darling_macro" -version = "0.21.3" +version = "0.23.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d38308df82d1080de0afee5d069fa14b0326a88c14f15c5ccda35b4a6c414c81" +checksum = "ac3984ec7bd6cfa798e62b4a642426a5be0e68f9401cfc2a01e3fa9ea2fcdb8d" dependencies = [ "darling_core", "quote", @@ -232,9 +231,9 @@ checksum = "48c757948c5ede0e46177b7add2e67155f70e33c07fea8284df6576da70b3719" [[package]] name = "env_filter" -version = "1.0.0" +version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7a1c3cc8e57274ec99de65301228b537f1e4eedc1b8e0f9411c6caac8ae7308f" +checksum = "32e90c2accc4b07a8456ea0debdc2e7587bdd890680d71173a15d4ae604f6eef" dependencies = [ "log", "regex", @@ -255,9 +254,9 @@ dependencies = [ [[package]] name = "env_logger" -version = "0.11.9" +version = "0.11.10" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b2daee4ea451f429a58296525ddf28b45a3b64f1acf6587e2067437bb11e218d" +checksum = "0621c04f2196ac3f488dd583365b9c09be011a4ab8b9f37248ffcc8f6198b56a" dependencies = [ "env_filter", "log", @@ -275,12 +274,6 @@ version = "0.1.9" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582" -[[package]] -name = "fnv" -version = "1.0.7" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1" - [[package]] name = "foldhash" version = "0.1.5" @@ -300,9 +293,9 @@ dependencies = [ [[package]] name = "getrandom" -version = "0.4.1" +version = "0.4.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "139ef39800118c7683f2fd3c98c1b23c09ae076556b435f8e9064ae108aaeeec" +checksum = "0de51e6874e94e7bf76d726fc5d13ba782deca734ff60d5bb2fb2607c7406555" dependencies = [ "cfg-if", "libc", @@ -375,9 +368,9 @@ dependencies = [ [[package]] name = "indexmap" -version = "2.13.0" +version = "2.13.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017" +checksum = "45a8a2b9cb3e0b0c1803dbb0758ffac5de2f425b23c28f518faabd9d805342ff" dependencies = [ "equivalent", "hashbrown 0.16.1", @@ -430,9 +423,9 @@ dependencies = [ [[package]] name = "itoa" -version = "1.0.17" +version = "1.0.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "92ecc6618181def0457392ccd0ee51198e065e016d1d527a7ac1b6dc7c1f09d2" +checksum = "8f42a60cbdf9a97f5d2305f08a87dc4e09308d1276d28c869c684d7777685682" [[package]] name = "leb128fmt" @@ -442,9 +435,9 @@ checksum = "09edd9e8b54e49e587e4f6295a7d29c3ea94d469cb40ab8ca70b288248a81db2" [[package]] name = "libc" -version = "0.2.181" +version = "0.2.184" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "459427e2af2b9c839b132acb702a1c654d95e10f8c326bfc2ad11310e458b1c5" +checksum = "48f5d2a454e16a5ea0f4ced81bd44e4cfc7bd3a507b61887c99fd3538b28e4af" [[package]] name = "linked-hash-map" @@ -534,25 +527,25 @@ version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "95c589f335db0f6aaa168a7cd27b1fc6920f5e1470c804f814d9cd6e62a0f70b" dependencies = [ - "env_logger 0.11.9", + "env_logger 0.11.10", "log", "rand 0.10.0", ] [[package]] name = "quote" -version = "1.0.44" +version = "1.0.45" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "21b2ebcf727b7760c461f091f9f0f539b77b8e87f2fd88131e7f1b433b3cece4" +checksum = "41f2619966050689382d2b44f664f4bc593e129785a36d6ee376ddf37259b924" dependencies = [ "proc-macro2", ] [[package]] name = "r-efi" -version = "5.3.0" +version = "6.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f" +checksum = "f8dcc9c7d52a811697d2151c701e0d08956f92b0e24136cf4cf27b57a6a0d9bf" [[package]] name = "rand" @@ -571,7 +564,7 @@ version = "0.10.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "bc266eb313df6c5c09c1c7b1fbe2510961e5bcd3add930c1e31f7ed9da0feff8" dependencies = [ - "getrandom 0.4.1", + "getrandom 0.4.2", "rand_core 0.10.0", ] @@ -645,9 +638,9 @@ dependencies = [ [[package]] name = "regex-syntax" -version = "0.8.9" +version = "0.8.10" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a96887878f22d7bad8a3b6dc5b7440e0ada9a245242924394987b21cf2210a4c" +checksum = "dc897dd8d9e8bd1ed8cdad82b5966c3e0ecae09fb1907d58efaa013543185d0a" [[package]] name = "rustc-demangle" @@ -672,9 +665,9 @@ dependencies = [ [[package]] name = "semver" -version = "1.0.27" +version = "1.0.28" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d767eb0aabc880b29956c35734170f26ed551a859dbd361d140cdbeca61ab1e2" +checksum = "8a7852d02fc848982e0c167ef163aaff9cd91dc640ba85e263cb1ce46fae51cd" [[package]] name = "serde" @@ -733,9 +726,9 @@ dependencies = [ [[package]] name = "serde_with" -version = "3.16.1" +version = "3.18.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4fa237f2807440d238e0364a218270b98f767a00d3dada77b1c53ae88940e2e7" +checksum = "dd5414fad8e6907dbdd5bc441a50ae8d6e26151a03b1de04d89a5576de61d01f" dependencies = [ "serde_core", "serde_with_macros", @@ -743,9 +736,9 @@ dependencies = [ [[package]] name = "serde_with_macros" -version = "3.16.1" +version = "3.18.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "52a8e3ca0ca629121f70ab50f95249e5a6f925cc0f6ffe8256c45b728875706c" +checksum = "d3db8978e608f1fe7357e211969fd9abdcae80bac1ba7a3369bb7eb6b404eb65" dependencies = [ "darling", "proc-macro2", @@ -801,6 +794,13 @@ dependencies = [ "regex", ] +[[package]] +name = "stdarch-gen-hexagon-scalar" +version = "0.1.0" +dependencies = [ + "regex", +] + [[package]] name = "stdarch-gen-loongarch" version = "0.1.0" @@ -849,9 +849,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f" [[package]] name = "syn" -version = "2.0.115" +version = "2.0.117" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6e614ed320ac28113fa64972c4262d5dbc89deacdfd00c34a3e4cea073243c12" +checksum = "e665b8803e7b1d2a727f4023456bbbbe74da67099c585258af0ad9c5013b9b99" dependencies = [ "proc-macro2", "quote", @@ -895,9 +895,9 @@ dependencies = [ [[package]] name = "unicode-ident" -version = "1.0.23" +version = "1.0.24" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "537dd038a89878be9b64dd4bd1b260315c1bb94f4d784956b81e27a088d9a09e" +checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75" [[package]] name = "unicode-xid" @@ -962,7 +962,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "bb0e353e6a2fbdc176932bbaab493762eb1255a7900fe0fea1a2f96c296cc909" dependencies = [ "anyhow", - "indexmap 2.13.0", + "indexmap 2.13.1", "wasm-encoder", "wasmparser 0.244.0", ] @@ -974,7 +974,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "161296c618fa2d63f6ed5fffd1112937e803cb9ec71b32b01a76321555660917" dependencies = [ "bitflags", - "indexmap 2.13.0", + "indexmap 2.13.1", "semver", ] @@ -986,7 +986,7 @@ checksum = "47b807c72e1bac69382b3a6fb3dbe8ea4c0ed87ff5629b8685ae6b9a611028fe" dependencies = [ "bitflags", "hashbrown 0.15.5", - "indexmap 2.13.0", + "indexmap 2.13.1", "semver", ] @@ -1053,7 +1053,7 @@ checksum = "b7c566e0f4b284dd6561c786d9cb0142da491f46a9fbed79ea69cdad5db17f21" dependencies = [ "anyhow", "heck", - "indexmap 2.13.0", + "indexmap 2.13.1", "prettyplease", "syn", "wasm-metadata", @@ -1084,7 +1084,7 @@ checksum = "9d66ea20e9553b30172b5e831994e35fbde2d165325bec84fc43dbf6f4eb9cb2" dependencies = [ "anyhow", "bitflags", - "indexmap 2.13.0", + "indexmap 2.13.1", "log", "serde", "serde_derive", @@ -1103,7 +1103,7 @@ checksum = "ecc8ac4bc1dc3381b7f59c34f00b67e18f910c2c0f50015669dde7def656a736" dependencies = [ "anyhow", "id-arena", - "indexmap 2.13.0", + "indexmap 2.13.1", "log", "semver", "serde", @@ -1130,18 +1130,18 @@ dependencies = [ [[package]] name = "zerocopy" -version = "0.8.39" +version = "0.8.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "db6d35d663eadb6c932438e763b262fe1a70987f9ae936e60158176d710cae4a" +checksum = "eed437bf9d6692032087e337407a86f04cd8d6a16a37199ed57949d415bd68e9" dependencies = [ "zerocopy-derive", ] [[package]] name = "zerocopy-derive" -version = "0.8.39" +version = "0.8.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517" +checksum = "70e3cd084b1788766f53af483dd21f93881ff30d7320490ec3ef7526d203bad4" dependencies = [ "proc-macro2", "quote", diff --git a/stdarch/aarch64-miri-tests.txt b/stdarch/aarch64-miri-tests.txt new file mode 100644 index 0000000000000..2c0dbb8297a1f --- /dev/null +++ b/stdarch/aarch64-miri-tests.txt @@ -0,0 +1,4 @@ +test_vld3 +test_vld4 +neon::load_tests +neon::store_tests diff --git a/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile b/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile index 2768c521ebccc..1b61dd0c1b87a 100644 --- a/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile +++ b/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile @@ -1,17 +1,22 @@ FROM ubuntu:25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc \ - g++ \ ca-certificates \ libc6-dev \ gcc-aarch64-linux-gnu \ - g++-aarch64-linux-gnu \ libc6-dev-arm64-cross \ qemu-user \ make \ file \ - clang \ - lld + xz-utils \ + wget + +RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz +RUN mkdir llvm +RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm + +ENV CLANG_PATH="/llvm/bin/clang" +ENV GCC_PATH=aarch64-linux-gnu-gcc ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \ CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64 -cpu max -L /usr/aarch64-linux-gnu" \ diff --git a/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile b/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile index f85c6a2592e99..70acc2d22a418 100644 --- a/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile +++ b/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile @@ -2,17 +2,15 @@ FROM ubuntu:25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc \ - g++ \ ca-certificates \ libc6-dev \ libc6-dev-arm64-cross \ qemu-user \ make \ file \ - clang \ curl \ xz-utils \ - lld + wget ENV TOOLCHAIN="arm-gnu-toolchain-14.3.rel1-x86_64-aarch64_be-none-linux-gnu" @@ -21,9 +19,16 @@ RUN curl -L "https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/bin RUN tar -xvf "${TOOLCHAIN}.tar.xz" RUN mkdir /toolchains && mv "./${TOOLCHAIN}" /toolchains +RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz +RUN mkdir llvm +RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm + ENV AARCH64_BE_TOOLCHAIN="/toolchains/${TOOLCHAIN}" ENV AARCH64_BE_LIBC="${AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc" +ENV CLANG_PATH="/llvm/bin/clang" +ENV GCC_PATH="${AARCH64_BE_TOOLCHAIN}/bin/aarch64_be-none-linux-gnu-gcc" + ENV CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_LINKER="${AARCH64_BE_TOOLCHAIN}/bin/aarch64_be-none-linux-gnu-gcc" ENV CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64_be -cpu max -L ${AARCH64_BE_LIBC}" ENV OBJDUMP="${AARCH64_BE_TOOLCHAIN}/bin/aarch64_be-none-linux-gnu-objdump" diff --git a/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile b/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile index 6d4ff24828672..23e4d5a341152 100644 --- a/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile +++ b/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile @@ -7,7 +7,9 @@ RUN apt-get update && apt-get install -y --no-install-recommends \ libc6-dev-armhf-cross \ qemu-user \ make \ - file + file \ + clang \ + lld ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \ CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -cpu max -L /usr/arm-linux-gnueabihf" \ OBJDUMP=arm-linux-gnueabihf-objdump diff --git a/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile b/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile index 602249c0ece5a..3c8a1b5add27f 100644 --- a/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile +++ b/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile @@ -1,17 +1,22 @@ FROM ubuntu:24.04 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc \ - g++ \ ca-certificates \ libc6-dev \ gcc-arm-linux-gnueabihf \ - g++-arm-linux-gnueabihf \ libc6-dev-armhf-cross \ qemu-user \ make \ file \ - clang \ - lld + wget + +RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz +RUN mkdir llvm +RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm + +ENV CLANG_PATH="/llvm/bin/clang" +ENV GCC_PATH=arm-linux-gnueabihf-gcc + ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \ CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -cpu max -L /usr/arm-linux-gnueabihf" \ OBJDUMP=arm-linux-gnueabihf-objdump diff --git a/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile b/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile index a8b352881e813..8bcd6409453c4 100644 --- a/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile +++ b/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -FROM ubuntu:25.10 +FROM ubuntu:25.04 # gcc-mips64-linux-gnuabi64 not available in 25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc libc6-dev qemu-user ca-certificates \ diff --git a/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile b/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile index 147a3df614554..9aa0ce05783c5 100644 --- a/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile +++ b/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -FROM ubuntu:25.10 +FROM ubuntu:25.04 # gcc-mips64el-linux-gnuabi64 not available in 25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc libc6-dev qemu-user ca-certificates \ diff --git a/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile index a357449d51e3d..efbb2b0853371 100644 --- a/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile +++ b/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile @@ -7,14 +7,29 @@ RUN apt-get update && apt-get install -y --no-install-recommends \ ca-certificates \ wget \ xz-utils \ - clang \ - libstdc++-14-dev \ - build-essential \ - lld + gpg -RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-10.5.0-2026-01-13-lin.tar.xz -O sde.tar.xz +RUN wget http://ci-mirrors.rust-lang.org/sde-external-10.8.0-2026-03-15-lin.tar.xz -O sde.tar.xz RUN mkdir intel-sde RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde + +RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz +RUN mkdir llvm +RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm + +RUN wget -O- https://apt.repos.intel.com/intel-gpg-keys/GPG-PUB-KEY-INTEL-SW-PRODUCTS.PUB |\ + gpg --dearmor |\ + tee /usr/share/keyrings/oneapi-archive-keyring.gpg > /dev/null + +RUN echo "deb [signed-by=/usr/share/keyrings/oneapi-archive-keyring.gpg] https://apt.repos.intel.com/oneapi all main" |\ + tee /etc/apt/sources.list.d/oneAPI.list + +RUN apt-get update && apt-get install -y --no-install-recommends intel-oneapi-compiler-dpcpp-cpp + +ENV CLANG_PATH="/llvm/bin/clang" +ENV GCC_PATH="gcc" +ENV ICX_PATH="/opt/intel/oneapi/compiler/2026.0/bin/icx" + ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \ -cpuid-in /checkout/ci/docker/x86_64-unknown-linux-gnu/cpuid.def \ -rtm-mode full -tsx --" diff --git a/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def b/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def index acf023ed0dc49..3bd657873e553 100644 --- a/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def +++ b/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def @@ -1,4 +1,4 @@ -# Copyright (C) 2017-2025 Intel Corporation. +# Copyright (C) 2017-2026 Intel Corporation. # # This software and the related documents are Intel copyrighted materials, and your # use of them is governed by the express license under which they were provided to @@ -23,8 +23,9 @@ 00000004 00000004 => 00000000 00000000 00000000 00000000 00000005 ******** => 00000040 00000040 00000003 00042120 #MONITOR/MWAIT 00000006 ******** => 00000077 00000002 00000001 00000000 #Thermal and Power -00000007 00000000 => 00000001 f3bfbfbf bac05ffe 03d54130 #Extended Features +00000007 00000000 => 00000002 f3bfbfbf bac05ffe 03d54130 #Extended Features 00000007 00000001 => 98ee00bf 00000002 00000020 1d29cd3e +00000007 00000002 => 00000000 00000000 00000000 00000010 00000008 ******** => 00000000 00000000 00000000 00000000 00000009 ******** => 00000000 00000000 00000000 00000000 #Direct Cache 0000000a ******** => 07300403 00000000 00000000 00000603 diff --git a/stdarch/ci/intrinsic-test-docker.sh b/stdarch/ci/intrinsic-test-docker.sh index beeff42c76212..c1d44dca91c5e 100755 --- a/stdarch/ci/intrinsic-test-docker.sh +++ b/stdarch/ci/intrinsic-test-docker.sh @@ -5,8 +5,8 @@ set -ex -if [ $# -lt 1 ]; then - >&2 echo "Usage: $0 " +if [ $# -lt 2 ]; then + >&2 echo "Usage: $0 " exit 1 fi @@ -29,7 +29,6 @@ run() { --user "$(id -u)":"$(id -g)" \ --env CARGO_HOME=/cargo \ --env CARGO_TARGET_DIR=/checkout/target \ - --env TARGET="${1}" \ --env PROFILE \ --env "${HOST_LINKER}"="cc" \ --env STDARCH_DISABLE_ASSERT_INSTR \ @@ -48,12 +47,12 @@ run() { --workdir /checkout \ --privileged \ stdarch \ - sh -c "HOME=/tmp PATH=\$PATH:/rust/bin exec ci/intrinsic-test.sh ${1}" + sh -c "HOME=/tmp PATH=\$PATH:/rust/bin exec ci/intrinsic-test.sh ${1} ${2}" } if [ -z "$1" ]; then >&2 echo "No target specified!" exit 1 else - run "${1}" + run "${1}" "${2}" fi diff --git a/stdarch/ci/intrinsic-test.sh b/stdarch/ci/intrinsic-test.sh index 89104e2672ad9..0441611f38fd2 100755 --- a/stdarch/ci/intrinsic-test.sh +++ b/stdarch/ci/intrinsic-test.sh @@ -2,130 +2,82 @@ set -ex -: "${TARGET?The TARGET environment variable must be set.}" +if [ $# -lt 2 ]; then + >&2 echo "Usage: $0 " + exit 1 +fi -export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled -Z verify-llvm-ir" -export HOST_RUSTFLAGS="${RUSTFLAGS}" -export PROFILE="${PROFILE:="release"}" - -case ${TARGET} in - # On 32-bit use a static relocation model which avoids some extra - # instructions when dealing with static data, notably allowing some - # instruction assertion checks to pass below the 20 instruction limit. If - # this is the default, dynamic, then too many instructions are generated - # when we assert the instruction for a function and it causes tests to fail. - i686-* | i586-*) - export RUSTFLAGS="${RUSTFLAGS} -C relocation-model=static" +case ${2} in + clang) + export CC="${CLANG_PATH}" + CC_ARG_STYLE=clang ;; - # Some x86_64 targets enable by default more features beyond SSE2, - # which cause some instruction assertion checks to fail. - x86_64-*) - export RUSTFLAGS="${RUSTFLAGS} -C target-feature=-sse3" + gcc) + export CC="${GCC_PATH}" + CC_ARG_STYLE=gcc ;; - #Unoptimized build uses fast-isel which breaks with msa - mips-* | mipsel-*) - export RUSTFLAGS="${RUSTFLAGS} -C llvm-args=-fast-isel=false" - ;; - armv7-*eabihf | thumbv7-*eabihf) - export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+neon" + icx) + export CC="${ICX_PATH}" + # `icx` uses clang-style arguments + CC_ARG_STYLE=clang ;; - # Some of our test dependencies use the deprecated `gcc` crates which - # doesn't detect RISC-V compilers automatically, so do it manually here. - riscv*) - export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+zk,+zks,+zbb,+zbc" + *) + >&2 echo "Unknown compiler: ${2}" + exit 1 ;; esac +export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled -Z verify-llvm-ir" +export PROFILE="${PROFILE:="release"}" + echo "RUSTFLAGS=${RUSTFLAGS}" -echo "OBJDUMP=${OBJDUMP}" echo "PROFILE=${PROFILE}" INTRINSIC_TEST="--manifest-path=crates/intrinsic-test/Cargo.toml" -# Test targets compiled with extra features. -case ${TARGET} in - # Setup aarch64 & armv7 specific variables, the runner, along with some - # tests to skip - aarch64-unknown-linux-gnu*) - TEST_CPPFLAGS="-fuse-ld=lld -I/usr/aarch64-linux-gnu/include/ -I/usr/aarch64-linux-gnu/include/c++/9/aarch64-linux-gnu/" - TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt - TEST_CXX_COMPILER="clang++" - TEST_RUNNER="${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}" - : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}" +case ${1} in + aarch64_be*) + export CFLAGS="-I${AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc/usr/include --sysroot={AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc -Wno-nonportable-vector-initialization" + ARCH=aarch64_be ;; - aarch64_be-unknown-linux-gnu*) - TEST_CPPFLAGS="-fuse-ld=lld" - TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64_be.txt - TEST_CXX_COMPILER="clang++" - TEST_RUNNER="${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER}" - : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}" + aarch64*) + export CFLAGS="-I/usr/aarch64-linux-gnu/include/" + ARCH=aarch64 ;; - armv7-unknown-linux-gnueabihf*) - TEST_CPPFLAGS="-fuse-ld=lld -I/usr/arm-linux-gnueabihf/include/ -I/usr/arm-linux-gnueabihf/include/c++/9/arm-linux-gnueabihf/" - TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_arm.txt - TEST_CXX_COMPILER="clang++" - TEST_RUNNER="${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}" - : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=100}" + armv7*) + export CFLAGS="-I/usr/arm-linux-gnueabihf/include/" + ARCH=arm ;; - x86_64-unknown-linux-gnu*) - TEST_CPPFLAGS="-fuse-ld=lld -I/usr/include/x86_64-linux-gnu/" - TEST_CXX_COMPILER="clang++" - TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}" - TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt - : "${TEST_SAMPLE_INTRINSICS_PERCENTAGE:=20}" + x86_64*) + export CFLAGS="-I/usr/include/x86_64-linux-gnu/" + ARCH=x86 ;; *) ;; esac -# Arm specific -case "${TARGET}" in - aarch64-unknown-linux-gnu*|armv7-unknown-linux-gnueabihf*) - CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=warn \ - cargo run "${INTRINSIC_TEST}" --release \ - --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \ - --runner "${TEST_RUNNER}" \ - --cppcompiler "${TEST_CXX_COMPILER}" \ - --skip "${TEST_SKIP_INTRINSICS}" \ - --target "${TARGET}" \ - --profile "${PROFILE}" \ - --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}" - ;; - - aarch64_be-unknown-linux-gnu*) - CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" RUST_LOG=warn \ - cargo run "${INTRINSIC_TEST}" --release \ - --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \ - --runner "${TEST_RUNNER}" \ - --cppcompiler "${TEST_CXX_COMPILER}" \ - --skip "${TEST_SKIP_INTRINSICS}" \ - --target "${TARGET}" \ - --profile "${PROFILE}" \ - --linker "${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_LINKER}" \ - --cxx-toolchain-dir "${AARCH64_BE_TOOLCHAIN}" \ - --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}" - ;; - +case "${1}" in x86_64-unknown-linux-gnu*) - # `CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER` is not necessary for `intrinsic-test` - # because the binary needs to run directly on the host. - # Hence the use of `env -u`. env -u CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER \ - CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" \ - RUST_LOG=warn RUST_BACKTRACE=1 \ cargo run "${INTRINSIC_TEST}" --release \ --bin intrinsic-test -- intrinsics_data/x86-intel.xml \ - --runner "${TEST_RUNNER}" \ - --skip "${TEST_SKIP_INTRINSICS}" \ - --cppcompiler "${TEST_CXX_COMPILER}" \ - --target "${TARGET}" \ - --profile "${PROFILE}" \ - --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}" + --skip "crates/intrinsic-test/missing_${ARCH}_common.txt" \ + --skip "crates/intrinsic-test/missing_${ARCH}_${2}.txt" \ + --target "${1}" \ + --cc-arg-style "${CC_ARG_STYLE}" ;; - *) + *) + cargo run "${INTRINSIC_TEST}" --release \ + --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json \ + --skip "crates/intrinsic-test/missing_${ARCH}_common.txt" \ + --skip "crates/intrinsic-test/missing_${ARCH}_${2}.txt" \ + --target "${1}" \ + --cc-arg-style "${CC_ARG_STYLE}" ;; esac + +cargo test --manifest-path=rust_programs/Cargo.toml --target "${1}" --profile "${PROFILE}" --tests diff --git a/stdarch/crates/assert-instr-macro/src/lib.rs b/stdarch/crates/assert-instr-macro/src/lib.rs index 13c3c3851b43c..839aae67cb2b0 100644 --- a/stdarch/crates/assert-instr-macro/src/lib.rs +++ b/stdarch/crates/assert-instr-macro/src/lib.rs @@ -14,6 +14,7 @@ extern crate quote; use proc_macro2::TokenStream; use quote::ToTokens; +use syn::spanned::Spanned; #[proc_macro_attribute] pub fn assert_instr( @@ -67,21 +68,21 @@ pub fn assert_instr( ); let mut inputs = Vec::new(); let mut input_vals = Vec::new(); - let mut const_vals = Vec::new(); + let mut param_vals = Vec::new(); let ret = &func.sig.output; for arg in func.sig.inputs.iter() { let capture = match *arg { - syn::FnArg::Typed(ref c) => c, + syn::FnArg::Typed(ref c) => c.to_owned(), ref v => panic!( "arguments must not have patterns: `{:?}`", v.clone().into_token_stream() ), }; - let ident = match *capture.pat { - syn::Pat::Ident(ref i) => &i.ident, + let ident = match capture.pat.as_ref() { + syn::Pat::Ident(i) => &i.ident.to_owned(), _ => panic!("must have bare arguments"), }; - if let Some((_, tokens)) = invoc.args.iter().find(|a| *ident == a.0) { + if let Some(&(_, ref tokens)) = invoc.args.iter().find(|a| *ident == a.0) { input_vals.push(quote! { #tokens }); } else { inputs.push(capture); @@ -89,18 +90,48 @@ pub fn assert_instr( } } for arg in func.sig.generics.params.iter() { - let c = match *arg { - syn::GenericParam::Const(ref c) => c, + match *arg { + syn::GenericParam::Const(ref c) => { + if let Some((_, tokens)) = invoc.args.iter().find(|a| c.ident == a.0) { + param_vals.push(quote! { #tokens }); + } else { + panic!("const generics must have a value for tests"); + } + } + syn::GenericParam::Type(ref t) => { + if let Some((_, tokens)) = invoc.args.iter().find(|a| t.ident == a.0) + && let syn::Expr::Path(syn::ExprPath { qself, path, .. }) = tokens + { + param_vals.push(syn::Token![_](tokens.span()).to_token_stream()); + + let generic_ty_value = syn::TypePath { + qself: qself.clone(), + path: path.clone(), + }; + + // Replace any function arguments that use generic parameters with the + // instantiation provided in the macro invocation. + inputs.iter_mut().for_each(|arg| { + update_type_path(arg.ty.as_mut(), |type_path: &mut syn::TypePath| { + if let Some(syn::PathSegment { + ident: last_ident, .. + }) = type_path.path.segments.last_mut() + { + if *last_ident == t.ident { + *type_path = generic_ty_value.to_owned() + } + } + }) + }); + } else { + panic!("type generics must have a type for tests"); + } + } ref v => panic!( - "only const generics are allowed: `{:?}`", + "only type and const generics are allowed: `{:?}`", v.clone().into_token_stream() ), }; - if let Some((_, tokens)) = invoc.args.iter().find(|a| c.ident == a.0) { - const_vals.push(quote! { #tokens }); - } else { - panic!("const generics must have a value for tests"); - } } let attrs = func @@ -138,7 +169,7 @@ pub fn assert_instr( #[unsafe(no_mangle)] #[inline(never)] pub unsafe extern #abi fn #shim_name(#(#inputs),*) #ret { - #name::<#(#const_vals),*>(#(#input_vals),*) + #name::<#(#param_vals),*>(#(#input_vals),*) } }; @@ -222,3 +253,23 @@ where } } } + +/// Calls `update` on type paths so that type generics can be replaced with the instantiation from +/// the attribute. +fn update_type_path(ty: &mut syn::Type, update: F) +where + F: Fn(&mut syn::TypePath), +{ + use syn::Type::*; + match ty { + Array(syn::TypeArray { elem, .. }) + | Group(syn::TypeGroup { elem, .. }) + | Paren(syn::TypeParen { elem, .. }) + | Ptr(syn::TypePtr { elem, .. }) + | Reference(syn::TypeReference { elem, .. }) + | Slice(syn::TypeSlice { elem, .. }) => update_type_path(elem.as_mut(), update), + Path(path @ syn::TypePath { .. }) => update(path), + Tuple(..) => panic!("tuples and generic types together are not yet supported"), + _ => {} + } +} diff --git a/stdarch/crates/core_arch/missing-x86.md b/stdarch/crates/core_arch/missing-x86.md index 640ec7d0fe7d1..e9f68eb9e6abe 100644 --- a/stdarch/crates/core_arch/missing-x86.md +++ b/stdarch/crates/core_arch/missing-x86.md @@ -44,22 +44,6 @@

-
["AVX512_VP2INTERSECT", "AVX512F"]

- - * [ ] [`_mm512_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi32) - * [ ] [`_mm512_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi64) -

- - -
["AVX512_VP2INTERSECT", "AVX512VL"]

- - * [ ] [`_mm256_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi32) - * [ ] [`_mm256_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi64) - * [ ] [`_mm_2intersect_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi32) - * [ ] [`_mm_2intersect_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi64) -

- -
["CET_SS"]

* [ ] [`_clrssbsy`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_clrssbsy) diff --git a/stdarch/crates/core_arch/src/aarch64/mod.rs b/stdarch/crates/core_arch/src/aarch64/mod.rs index d7295659c3c9a..0292be2e0d778 100644 --- a/stdarch/crates/core_arch/src/aarch64/mod.rs +++ b/stdarch/crates/core_arch/src/aarch64/mod.rs @@ -25,6 +25,20 @@ mod neon; #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub use self::neon::*; +// The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`. +#[cfg(any(target_arch = "aarch64", doc))] +mod sve; +#[cfg(any(target_arch = "aarch64", doc))] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::sve::*; + +// The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`. +#[cfg(any(target_arch = "aarch64", doc))] +mod sve2; +#[cfg(any(target_arch = "aarch64", doc))] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::sve2::*; + mod prefetch; #[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")] pub use self::prefetch::*; diff --git a/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index 74af50016690b..8d701d9b88056 100644 --- a/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -14,7 +14,7 @@ use super::*; #[doc = "CRC32-C single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(test, assert_instr(crc32cx))] #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")] @@ -30,7 +30,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 { } #[doc = "CRC32 single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(test, assert_instr(crc32x))] #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")] @@ -46,7 +46,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 { } #[doc = "Floating-point JavaScript convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__jcvt)"] -#[inline(always)] +#[inline] #[target_feature(enable = "jsconv")] #[cfg_attr(test, assert_instr(fjcvtzs))] #[stable(feature = "stdarch_aarch64_jscvt", since = "1.95.0")] @@ -62,94 +62,106 @@ pub fn __jcvt(a: f64) -> i32 { } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(sabal2) +)] pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { + let d = vget_high_s8(b); + let e = vget_high_s8(c); + let f = vabd_s8(d, e); unsafe { - let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: int8x8_t = vabd_s8(d, e); let f: uint8x8_t = simd_cast(f); simd_add(a, simd_cast(f)) } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(sabal2) +)] pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + let d = vget_high_s16(b); + let e = vget_high_s16(c); + let f = vabd_s16(d, e); unsafe { - let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - let f: int16x4_t = vabd_s16(d, e); let f: uint16x4_t = simd_cast(f); simd_add(a, simd_cast(f)) } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(sabal2) +)] pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + let d = vget_high_s32(b); + let e = vget_high_s32(c); + let f = vabd_s32(d, e); unsafe { - let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: int32x2_t = simd_shuffle!(c, c, [2, 3]); - let f: int32x2_t = vabd_s32(d, e); let f: uint32x2_t = simd_cast(f); simd_add(a, simd_cast(f)) } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uabal2) +)] pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - unsafe { - let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: uint8x8_t = vabd_u8(d, e); - simd_add(a, simd_cast(f)) - } + let d = vget_high_u8(b); + let e = vget_high_u8(c); + let f = vabd_u8(d, e); + unsafe { simd_add(a, simd_cast(f)) } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uabal2) +)] pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - unsafe { - let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - let f: uint16x4_t = vabd_u16(d, e); - simd_add(a, simd_cast(f)) - } + let d = vget_high_u16(b); + let e = vget_high_u16(c); + let f = vabd_u16(d, e); + unsafe { simd_add(a, simd_cast(f)) } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uabal2) +)] pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - unsafe { - let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - let f: uint32x2_t = vabd_u32(d, e); - simd_add(a, simd_cast(f)) - } + let d = vget_high_u32(b); + let e = vget_high_u32(c); + let f = vabd_u32(d, e); + unsafe { simd_add(a, simd_cast(f)) } } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] @@ -165,7 +177,7 @@ pub fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] @@ -181,116 +193,110 @@ pub fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] pub fn vabdd_f64(a: f64, b: f64) -> f64 { - unsafe { simd_extract!(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_f64::<0>(vabd_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] pub fn vabds_f32(a: f32, b: f32) -> f32 { - unsafe { simd_extract!(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_f32::<0>(vabd_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fabd))] pub fn vabdh_f16(a: f16, b: f16) -> f16 { - unsafe { simd_extract!(vabd_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_f16::<0>(vabd_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Signed Absolute difference Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sabdl2))] -pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))] +pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + let c = vget_high_s8(a); + let d = vget_high_s8(b); unsafe { - let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: uint16x4_t = simd_cast(vabd_s16(c, d)); + let e: uint8x8_t = simd_cast(vabd_s8(c, d)); simd_cast(e) } } #[doc = "Signed Absolute difference Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sabdl2))] -pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))] +pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + let c = vget_high_s16(a); + let d = vget_high_s16(b); unsafe { - let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: uint32x2_t = simd_cast(vabd_s32(c, d)); + let e: uint16x4_t = simd_cast(vabd_s16(c, d)); simd_cast(e) } } #[doc = "Signed Absolute difference Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sabdl2))] -pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))] +pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + let c = vget_high_s32(a); + let d = vget_high_s32(b); unsafe { - let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: uint8x8_t = simd_cast(vabd_s8(c, d)); + let e: uint32x2_t = simd_cast(vabd_s32(c, d)); simd_cast(e) } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uabdl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))] pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - unsafe { - let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_cast(vabd_u8(c, d)) - } + let c = vget_high_u8(a); + let d = vget_high_u8(b); + unsafe { simd_cast(vabd_u8(c, d)) } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uabdl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))] pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - unsafe { - let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_cast(vabd_u16(c, d)) - } + let c = vget_high_u16(a); + let d = vget_high_u16(b); + unsafe { simd_cast(vabd_u16(c, d)) } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uabdl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))] pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - unsafe { - let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_cast(vabd_u32(c, d)) - } + let c = vget_high_u32(a); + let d = vget_high_u32(b); + unsafe { simd_cast(vabd_u32(c, d)) } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -299,7 +305,7 @@ pub fn vabs_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -308,7 +314,7 @@ pub fn vabsq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] @@ -321,7 +327,7 @@ pub fn vabs_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] @@ -334,7 +340,7 @@ pub fn vabsq_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] @@ -350,7 +356,7 @@ pub fn vabsd_s64(a: i64) -> i64 { } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -359,7 +365,7 @@ pub fn vaddd_s64(a: i64, b: i64) -> i64 { } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -368,7 +374,7 @@ pub fn vaddd_u64(a: u64, b: u64) -> u64 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -384,7 +390,7 @@ pub fn vaddlv_s16(a: int16x4_t) -> i32 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -400,7 +406,7 @@ pub fn vaddlvq_s16(a: int16x8_t) -> i32 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -416,7 +422,7 @@ pub fn vaddlvq_s32(a: int32x4_t) -> i64 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlp))] @@ -432,7 +438,7 @@ pub fn vaddlv_s32(a: int32x2_t) -> i64 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -448,7 +454,7 @@ pub fn vaddlv_s8(a: int8x8_t) -> i16 { } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] @@ -464,7 +470,7 @@ pub fn vaddlvq_s8(a: int8x16_t) -> i16 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -480,7 +486,7 @@ pub fn vaddlv_u16(a: uint16x4_t) -> u32 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -496,7 +502,7 @@ pub fn vaddlvq_u16(a: uint16x8_t) -> u32 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -512,7 +518,7 @@ pub fn vaddlvq_u32(a: uint32x4_t) -> u64 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlp))] @@ -528,7 +534,7 @@ pub fn vaddlv_u32(a: uint32x2_t) -> u64 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -544,7 +550,7 @@ pub fn vaddlv_u8(a: uint8x8_t) -> u16 { } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] @@ -560,7 +566,7 @@ pub fn vaddlvq_u8(a: uint8x16_t) -> u16 { } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] @@ -576,7 +582,7 @@ pub fn vaddv_f32(a: float32x2_t) -> f32 { } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] @@ -592,7 +598,7 @@ pub fn vaddvq_f32(a: float32x4_t) -> f32 { } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] @@ -608,7 +614,7 @@ pub fn vaddvq_f64(a: float64x2_t) -> f64 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -617,7 +623,7 @@ pub fn vaddv_s32(a: int32x2_t) -> i32 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -626,7 +632,7 @@ pub fn vaddv_s8(a: int8x8_t) -> i8 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -635,7 +641,7 @@ pub fn vaddvq_s8(a: int8x16_t) -> i8 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -644,7 +650,7 @@ pub fn vaddv_s16(a: int16x4_t) -> i16 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -653,7 +659,7 @@ pub fn vaddvq_s16(a: int16x8_t) -> i16 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -662,7 +668,7 @@ pub fn vaddvq_s32(a: int32x4_t) -> i32 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -671,7 +677,7 @@ pub fn vaddv_u32(a: uint32x2_t) -> u32 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -680,7 +686,7 @@ pub fn vaddv_u8(a: uint8x8_t) -> u8 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -689,7 +695,7 @@ pub fn vaddvq_u8(a: uint8x16_t) -> u8 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -698,7 +704,7 @@ pub fn vaddv_u16(a: uint16x4_t) -> u16 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -707,7 +713,7 @@ pub fn vaddvq_u16(a: uint16x8_t) -> u16 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] @@ -716,7 +722,7 @@ pub fn vaddvq_u32(a: uint32x4_t) -> u32 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -725,7 +731,7 @@ pub fn vaddvq_s64(a: int64x2_t) -> i64 { } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -734,7 +740,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -750,7 +756,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -766,7 +772,7 @@ pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -782,7 +788,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -798,7 +804,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -814,7 +820,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -830,7 +836,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -846,7 +852,7 @@ pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -862,7 +868,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -878,7 +884,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -894,7 +900,7 @@ pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -910,7 +916,7 @@ pub fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -926,7 +932,7 @@ pub fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -942,7 +948,7 @@ pub fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -958,7 +964,7 @@ pub fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -974,7 +980,7 @@ pub fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -990,7 +996,7 @@ pub fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -1006,7 +1012,7 @@ pub fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] @@ -1022,7 +1028,8 @@ pub fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -1039,8 +1046,33 @@ pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vcadd_rot270_f16(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v4f16" + )] + fn _vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcadd_rot270_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -1057,8 +1089,33 @@ pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { _vcaddq_rot270_f16(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v8f16" + )] + fn _vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcaddq_rot270_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1073,8 +1130,31 @@ pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vcadd_rot270_f32(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v2f32" + )] + fn _vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vcadd_rot270_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1089,8 +1169,31 @@ pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vcaddq_rot270_f32(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v4f32" + )] + fn _vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcaddq_rot270_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1105,8 +1208,31 @@ pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { _vcaddq_rot270_f64(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v2f64" + )] + fn _vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vcaddq_rot270_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -1123,8 +1249,33 @@ pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vcadd_rot90_f16(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v4f16" + )] + fn _vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcadd_rot90_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -1141,8 +1292,33 @@ pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { _vcaddq_rot90_f16(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v8f16" + )] + fn _vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcaddq_rot90_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1157,8 +1333,31 @@ pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vcadd_rot90_f32(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v2f32" + )] + fn _vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vcadd_rot90_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1173,8 +1372,31 @@ pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vcaddq_rot90_f32(a, b) } } #[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v4f32" + )] + fn _vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcaddq_rot90_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] @@ -1188,9 +1410,31 @@ pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } unsafe { _vcaddq_rot90_f64(a, b) } } +#[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v2f64" + )] + fn _vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vcaddq_rot90_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1206,7 +1450,7 @@ pub fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1222,7 +1466,7 @@ pub fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1238,7 +1482,7 @@ pub fn vcaged_f64(a: f64, b: f64) -> u64 { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1254,7 +1498,7 @@ pub fn vcages_f32(a: f32, b: f32) -> u32 { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(facge))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -1271,7 +1515,7 @@ pub fn vcageh_f16(a: f16, b: f16) -> u16 { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1287,7 +1531,7 @@ pub fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1303,7 +1547,7 @@ pub fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1319,7 +1563,7 @@ pub fn vcagtd_f64(a: f64, b: f64) -> u64 { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1335,7 +1579,7 @@ pub fn vcagts_f32(a: f32, b: f32) -> u32 { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagth_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(facgt))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -1352,7 +1596,7 @@ pub fn vcagth_f16(a: f16, b: f16) -> u16 { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1361,7 +1605,7 @@ pub fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1370,7 +1614,7 @@ pub fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1379,7 +1623,7 @@ pub fn vcaled_f64(a: f64, b: f64) -> u64 { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1388,7 +1632,7 @@ pub fn vcales_f32(a: f32, b: f32) -> u32 { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(facge))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -1398,7 +1642,7 @@ pub fn vcaleh_f16(a: f16, b: f16) -> u16 { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1407,7 +1651,7 @@ pub fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1416,7 +1660,7 @@ pub fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1425,7 +1669,7 @@ pub fn vcaltd_f64(a: f64, b: f64) -> u64 { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1434,7 +1678,7 @@ pub fn vcalts_f32(a: f32, b: f32) -> u32 { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalth_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(facgt))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -1444,7 +1688,7 @@ pub fn vcalth_f16(a: f16, b: f16) -> u16 { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1453,7 +1697,7 @@ pub fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1462,7 +1706,7 @@ pub fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1471,7 +1715,7 @@ pub fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1480,7 +1724,7 @@ pub fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1489,7 +1733,7 @@ pub fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1498,7 +1742,7 @@ pub fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1507,7 +1751,7 @@ pub fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1516,25 +1760,25 @@ pub fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vceqd_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vceq_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vceqs_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vceq_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Compare bitwise equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1543,7 +1787,7 @@ pub fn vceqd_s64(a: i64, b: i64) -> u64 { } #[doc = "Compare bitwise equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1552,17 +1796,17 @@ pub fn vceqd_u64(a: u64, b: u64) -> u64 { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqh_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vceq_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vceq_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -1573,7 +1817,7 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -1584,7 +1828,7 @@ pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1594,7 +1838,7 @@ pub fn vceqz_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1604,7 +1848,7 @@ pub fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1614,7 +1858,7 @@ pub fn vceqz_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1624,7 +1868,7 @@ pub fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1634,7 +1878,7 @@ pub fn vceqz_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1644,7 +1888,7 @@ pub fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1654,7 +1898,7 @@ pub fn vceqz_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1664,7 +1908,7 @@ pub fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1674,7 +1918,7 @@ pub fn vceqz_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1684,7 +1928,7 @@ pub fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1694,7 +1938,7 @@ pub fn vceqz_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1704,7 +1948,7 @@ pub fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1714,7 +1958,7 @@ pub fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1724,7 +1968,7 @@ pub fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1734,7 +1978,7 @@ pub fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1744,7 +1988,7 @@ pub fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1754,7 +1998,7 @@ pub fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1764,7 +2008,7 @@ pub fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1774,7 +2018,7 @@ pub fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1784,7 +2028,7 @@ pub fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1794,7 +2038,7 @@ pub fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1804,7 +2048,7 @@ pub fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1814,7 +2058,7 @@ pub fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1824,7 +2068,7 @@ pub fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1833,7 +2077,7 @@ pub fn vceqzd_s64(a: i64) -> u64 { } #[doc = "Compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1842,35 +2086,35 @@ pub fn vceqzd_u64(a: u64) -> u64 { } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqzh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vceqz_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vceqz_f16(vdup_n_f16(a))) } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vceqzs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vceqz_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vceqz_f32(vdup_n_f32(a))) } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vceqzd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vceqz_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vceqz_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1879,7 +2123,7 @@ pub fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1888,7 +2132,7 @@ pub fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1897,7 +2141,7 @@ pub fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1906,7 +2150,7 @@ pub fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1915,7 +2159,7 @@ pub fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1924,25 +2168,25 @@ pub fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcged_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vcge_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcges_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vcge_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1951,7 +2195,7 @@ pub fn vcged_s64(a: i64, b: i64) -> u64 { } #[doc = "Compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1960,17 +2204,17 @@ pub fn vcged_u64(a: u64, b: u64) -> u64 { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcgeh_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vcge_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vcge_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1980,7 +2224,7 @@ pub fn vcgez_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -1990,7 +2234,7 @@ pub fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2000,7 +2244,7 @@ pub fn vcgez_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2010,7 +2254,7 @@ pub fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2020,7 +2264,7 @@ pub fn vcgez_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2030,7 +2274,7 @@ pub fn vcgezq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2040,7 +2284,7 @@ pub fn vcgez_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2050,7 +2294,7 @@ pub fn vcgezq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2060,7 +2304,7 @@ pub fn vcgez_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2070,7 +2314,7 @@ pub fn vcgezq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2080,7 +2324,7 @@ pub fn vcgez_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2090,25 +2334,25 @@ pub fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgezd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vcgez_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vcgez_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgezs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vcgez_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vcgez_f32(vdup_n_f32(a))) } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2117,17 +2361,17 @@ pub fn vcgezd_s64(a: i64) -> u64 { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcgezh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vcgez_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vcgez_f16(vdup_n_f16(a))) } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2136,7 +2380,7 @@ pub fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2145,7 +2389,7 @@ pub fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2154,7 +2398,7 @@ pub fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2163,7 +2407,7 @@ pub fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2172,7 +2416,7 @@ pub fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2181,25 +2425,25 @@ pub fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgtd_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgts_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2208,7 +2452,7 @@ pub fn vcgtd_s64(a: i64, b: i64) -> u64 { } #[doc = "Compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2217,17 +2461,17 @@ pub fn vcgtd_u64(a: u64, b: u64) -> u64 { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgth_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcgth_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2237,7 +2481,7 @@ pub fn vcgtz_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2247,7 +2491,7 @@ pub fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2257,7 +2501,7 @@ pub fn vcgtz_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2267,7 +2511,7 @@ pub fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2277,7 +2521,7 @@ pub fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2287,7 +2531,7 @@ pub fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2297,7 +2541,7 @@ pub fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2307,7 +2551,7 @@ pub fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2317,7 +2561,7 @@ pub fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2327,7 +2571,7 @@ pub fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2337,7 +2581,7 @@ pub fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2347,25 +2591,25 @@ pub fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgtzd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vcgtz_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vcgtz_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcgtzs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vcgtz_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vcgtz_f32(vdup_n_f32(a))) } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2374,17 +2618,17 @@ pub fn vcgtzd_s64(a: i64) -> u64 { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcgtzh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vcgtz_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vcgtz_f16(vdup_n_f16(a))) } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2393,7 +2637,7 @@ pub fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2402,7 +2646,7 @@ pub fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2411,7 +2655,7 @@ pub fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2420,7 +2664,7 @@ pub fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2429,7 +2673,7 @@ pub fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2438,25 +2682,25 @@ pub fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcled_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vcle_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcles_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vcle_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2465,7 +2709,7 @@ pub fn vcled_u64(a: u64, b: u64) -> u64 { } #[doc = "Compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2474,17 +2718,17 @@ pub fn vcled_s64(a: i64, b: i64) -> u64 { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcleh_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vcle_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vcle_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2494,7 +2738,7 @@ pub fn vclez_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2504,7 +2748,7 @@ pub fn vclezq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2514,7 +2758,7 @@ pub fn vclez_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2524,7 +2768,7 @@ pub fn vclezq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2534,7 +2778,7 @@ pub fn vclez_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2544,7 +2788,7 @@ pub fn vclezq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2554,7 +2798,7 @@ pub fn vclez_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2564,7 +2808,7 @@ pub fn vclezq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2574,7 +2818,7 @@ pub fn vclez_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2584,7 +2828,7 @@ pub fn vclezq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2594,7 +2838,7 @@ pub fn vclez_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2604,25 +2848,25 @@ pub fn vclezq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vclezd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vclez_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vclez_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vclezs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vclez_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vclez_f32(vdup_n_f32(a))) } #[doc = "Compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2631,17 +2875,17 @@ pub fn vclezd_s64(a: i64) -> u64 { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vclezh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vclez_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vclez_f16(vdup_n_f16(a))) } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2650,7 +2894,7 @@ pub fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2659,7 +2903,7 @@ pub fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2668,7 +2912,7 @@ pub fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2677,7 +2921,7 @@ pub fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2686,7 +2930,7 @@ pub fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2695,7 +2939,7 @@ pub fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2704,7 +2948,7 @@ pub fn vcltd_u64(a: u64, b: u64) -> u64 { } #[doc = "Compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2713,35 +2957,35 @@ pub fn vcltd_s64(a: i64, b: i64) -> u64 { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclth_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vclth_f16(a: f16, b: f16) -> u16 { - unsafe { simd_extract!(vclt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } + vget_lane_u16::<0>(vclt_f16(vdup_n_f16(a), vdup_n_f16(b))) } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vclts_f32(a: f32, b: f32) -> u32 { - unsafe { simd_extract!(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } + vget_lane_u32::<0>(vclt_f32(vdup_n_f32(a), vdup_n_f32(b))) } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcltd_f64(a: f64, b: f64) -> u64 { - unsafe { simd_extract!(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } + vget_lane_u64::<0>(vclt_f64(vdup_n_f64(a), vdup_n_f64(b))) } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2751,7 +2995,7 @@ pub fn vcltz_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2761,7 +3005,7 @@ pub fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2771,7 +3015,7 @@ pub fn vcltz_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2781,7 +3025,7 @@ pub fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2791,7 +3035,7 @@ pub fn vcltz_s8(a: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2801,7 +3045,7 @@ pub fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2811,7 +3055,7 @@ pub fn vcltz_s16(a: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2821,7 +3065,7 @@ pub fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2831,7 +3075,7 @@ pub fn vcltz_s32(a: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2841,7 +3085,7 @@ pub fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2851,7 +3095,7 @@ pub fn vcltz_s64(a: int64x1_t) -> uint64x1_t { } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2861,25 +3105,25 @@ pub fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcltzd_f64(a: f64) -> u64 { - unsafe { simd_extract!(vcltz_f64(vdup_n_f64(a)), 0) } + vget_lane_u64::<0>(vcltz_f64(vdup_n_f64(a))) } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcltzs_f32(a: f32) -> u32 { - unsafe { simd_extract!(vcltz_f32(vdup_n_f32(a)), 0) } + vget_lane_u32::<0>(vcltz_f32(vdup_n_f32(a))) } #[doc = "Compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(asr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -2888,17 +3132,18 @@ pub fn vcltzd_s64(a: i64) -> u64 { } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcltzh_f16(a: f16) -> u16 { - unsafe { simd_extract!(vcltz_f16(vdup_n_f16(a)), 0) } + vget_lane_u16::<0>(vcltz_f16(vdup_n_f16(a))) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -2915,42 +3160,118 @@ pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t unsafe { _vcmla_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fcmla))] -pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { +pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vcmla.rot0.v8f16" + link_name = "llvm.aarch64.neon.vcmla.rot0.v4f16" )] - fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + fn _vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcmla_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vcmlaq_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fcmla))] -pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { +pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32" + link_name = "llvm.aarch64.neon.vcmla.rot0.v8f16" )] - fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { _vcmlaq_f16(a, b, c) } +} +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v8f16" + )] + fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcmlaq_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32" + )] + fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } unsafe { _vcmla_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32" + )] + fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float32x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float32x2_t = _vcmla_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -2965,8 +3286,32 @@ pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t unsafe { _vcmlaq_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v4f32" + )] + fn _vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcmlaq_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -2981,8 +3326,31 @@ pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t unsafe { _vcmlaq_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v2f64" + )] + fn _vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float64x2_t = _vcmlaq_f64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -2995,23 +3363,14 @@ pub fn vcmla_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdup_lane_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3024,27 +3383,14 @@ pub fn vcmlaq_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdupq_lane_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3055,14 +3401,14 @@ pub fn vcmla_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdup_lane_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3073,23 +3419,14 @@ pub fn vcmlaq_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdupq_lane_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3102,23 +3439,14 @@ pub fn vcmla_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdup_laneq_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3131,27 +3459,14 @@ pub fn vcmlaq_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdupq_laneq_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3162,14 +3477,14 @@ pub fn vcmla_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdup_laneq_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3180,23 +3495,15 @@ pub fn vcmlaq_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdupq_laneq_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3213,8 +3520,34 @@ pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float unsafe { _vcmla_rot180_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v4f16" + )] + fn _vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcmla_rot180_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3231,8 +3564,34 @@ pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa unsafe { _vcmlaq_rot180_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v8f16" + )] + fn _vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcmlaq_rot180_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3247,8 +3606,32 @@ pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float unsafe { _vcmla_rot180_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v2f32" + )] + fn _vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float32x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float32x2_t = _vcmla_rot180_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3263,8 +3646,32 @@ pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa unsafe { _vcmlaq_rot180_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v4f32" + )] + fn _vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcmlaq_rot180_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3279,8 +3686,31 @@ pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa unsafe { _vcmlaq_rot180_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v2f64" + )] + fn _vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float64x2_t = _vcmlaq_rot180_f64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3293,23 +3723,14 @@ pub fn vcmla_rot180_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot180_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdup_lane_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot180_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3322,27 +3743,14 @@ pub fn vcmlaq_rot180_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdupq_lane_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot180_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3353,14 +3761,14 @@ pub fn vcmla_rot180_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot180_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdup_lane_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot180_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3371,23 +3779,14 @@ pub fn vcmlaq_rot180_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdupq_lane_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot180_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3400,23 +3799,14 @@ pub fn vcmla_rot180_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot180_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdup_laneq_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot180_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3429,27 +3819,14 @@ pub fn vcmlaq_rot180_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdupq_laneq_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot180_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3460,14 +3837,14 @@ pub fn vcmla_rot180_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot180_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdup_laneq_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot180_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3478,23 +3855,15 @@ pub fn vcmlaq_rot180_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdupq_laneq_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot180_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3511,8 +3880,34 @@ pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float unsafe { _vcmla_rot270_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v4f16" + )] + fn _vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcmla_rot270_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3529,8 +3924,34 @@ pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa unsafe { _vcmlaq_rot270_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v8f16" + )] + fn _vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcmlaq_rot270_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3545,8 +3966,32 @@ pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float unsafe { _vcmla_rot270_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v2f32" + )] + fn _vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float32x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float32x2_t = _vcmla_rot270_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3561,8 +4006,32 @@ pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa unsafe { _vcmlaq_rot270_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v4f32" + )] + fn _vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcmlaq_rot270_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3577,8 +4046,31 @@ pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa unsafe { _vcmlaq_rot270_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v2f64" + )] + fn _vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float64x2_t = _vcmlaq_rot270_f64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3591,23 +4083,14 @@ pub fn vcmla_rot270_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot270_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdup_lane_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot270_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3620,27 +4103,14 @@ pub fn vcmlaq_rot270_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdupq_lane_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot270_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3651,14 +4121,14 @@ pub fn vcmla_rot270_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot270_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdup_lane_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot270_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3669,23 +4139,14 @@ pub fn vcmlaq_rot270_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdupq_lane_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot270_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3698,23 +4159,14 @@ pub fn vcmla_rot270_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot270_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdup_laneq_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot270_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3727,27 +4179,14 @@ pub fn vcmlaq_rot270_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdupq_laneq_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot270_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3758,14 +4197,14 @@ pub fn vcmla_rot270_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot270_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdup_laneq_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot270_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3776,23 +4215,15 @@ pub fn vcmlaq_rot270_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdupq_laneq_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot270_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3809,8 +4240,34 @@ pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float1 unsafe { _vcmla_rot90_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v4f16" + )] + fn _vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vcmla_rot90_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] @@ -3827,8 +4284,34 @@ pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float unsafe { _vcmlaq_rot90_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v8f16" + )] + fn _vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vcmlaq_rot90_f16(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3843,8 +4326,32 @@ pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 unsafe { _vcmla_rot90_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v2f32" + )] + fn _vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float32x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float32x2_t = _vcmla_rot90_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3859,8 +4366,32 @@ pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float unsafe { _vcmlaq_rot90_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v4f32" + )] + fn _vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vcmlaq_rot90_f32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] @@ -3875,8 +4406,31 @@ pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float unsafe { _vcmlaq_rot90_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v2f64" + )] + fn _vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: float64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: float64x2_t = _vcmlaq_rot90_f64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3889,23 +4443,14 @@ pub fn vcmla_rot90_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot90_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdup_lane_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot90_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3918,27 +4463,14 @@ pub fn vcmlaq_rot90_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f16(a, b, c) - } + let c = vreinterpret_u32_f16(c); + let c = vdupq_lane_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot90_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3949,14 +4481,14 @@ pub fn vcmla_rot90_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot90_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdup_lane_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot90_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3967,23 +4499,14 @@ pub fn vcmlaq_rot90_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f32(a, b, c) - } + let c = vreinterpret_u64_f32(c); + let c = vdupq_lane_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot90_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -3996,23 +4519,14 @@ pub fn vcmla_rot90_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot90_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdup_laneq_u32::(c); + let c = vreinterpret_f16_u32(c); + vcmla_rot90_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -4025,27 +4539,14 @@ pub fn vcmlaq_rot90_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f16(a, b, c) - } + let c = vreinterpretq_u32_f16(c); + let c = vdupq_laneq_u32::(c); + let c = vreinterpretq_f16_u32(c); + vcmlaq_rot90_f16(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -4056,14 +4557,14 @@ pub fn vcmla_rot90_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot90_f32(a, b, c) - } + let c = vreinterpretq_u64_f32(c); + let c = vdup_laneq_u64::(c); + let c = vreinterpret_f32_u64(c); + vcmla_rot90_f32(a, b, c) } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -4074,25 +4575,42 @@ pub fn vcmlaq_rot90_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); + let c = vreinterpretq_u64_f32(c); + let c = vdupq_laneq_u64::(c); + let c = vreinterpretq_f32_u64(c); + vcmlaq_rot90_f32(a, b, c) +} +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(mov))] +pub fn vcombine_f64(a: float64x1_t, b: float64x1_t) -> float64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } +} +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(mov))] +pub fn vcombine_f64(a: float64x1_t, b: float64x1_t) -> float64x2_t { unsafe { - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f32(a, b, c) + let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_f32( @@ -4101,105 +4619,76 @@ pub fn vcopy_lane_f32( ) -> float32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_f32::(vget_lane_f32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s8::(vget_lane_s8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s16::(vget_lane_s16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s32::(vget_lane_s32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u8::(vget_lane_u8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u16( @@ -4208,21 +4697,16 @@ pub fn vcopy_lane_u16( ) -> uint16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u16::(vget_lane_u16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u32( @@ -4231,43 +4715,31 @@ pub fn vcopy_lane_u32( ) -> uint32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u32::(vget_lane_u32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_p8::(vget_lane_p8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_p16( @@ -4276,21 +4748,76 @@ pub fn vcopy_lane_p16( ) -> poly16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_p16::(vget_lane_p16::(b), a) +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_lane_f64( + _a: float64x1_t, + b: float64x1_t, +) -> float64x1_t { + static_assert!(LANE1 == 0); + static_assert!(LANE2 == 0); + b +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_lane_s64( + _a: int64x1_t, + b: int64x1_t, +) -> int64x1_t { + static_assert!(LANE1 == 0); + static_assert!(LANE2 == 0); + b +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_lane_u64( + _a: uint64x1_t, + b: uint64x1_t, +) -> uint64x1_t { + static_assert!(LANE1 == 0); + static_assert!(LANE2 == 0); + b +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_lane_p64( + _a: poly64x1_t, + b: poly64x1_t, +) -> poly64x1_t { + static_assert!(LANE1 == 0); + static_assert!(LANE2 == 0); + b } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_f32( @@ -4299,46 +4826,31 @@ pub fn vcopy_laneq_f32( ) -> float32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_f32::(vgetq_lane_f32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s8(a: int8x8_t, b: int8x16_t) -> int8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s8::(vgetq_lane_s8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s16( @@ -4347,22 +4859,16 @@ pub fn vcopy_laneq_s16( ) -> int16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s16::(vgetq_lane_s16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s32( @@ -4371,20 +4877,16 @@ pub fn vcopy_laneq_s32( ) -> int32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_s32::(vgetq_lane_s32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u8( @@ -4393,27 +4895,16 @@ pub fn vcopy_laneq_u8( ) -> uint8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u8::(vgetq_lane_u8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u16( @@ -4422,22 +4913,16 @@ pub fn vcopy_laneq_u16( ) -> uint16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u16::(vgetq_lane_u16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u32( @@ -4446,20 +4931,16 @@ pub fn vcopy_laneq_u32( ) -> uint32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_u32::(vgetq_lane_u32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_p8( @@ -4468,27 +4949,16 @@ pub fn vcopy_laneq_p8( ) -> poly8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_p8::(vgetq_lane_p8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_p16( @@ -4497,20 +4967,71 @@ pub fn vcopy_laneq_p16( ) -> poly16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vset_lane_p16::(vgetq_lane_p16::(b), a) +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_laneq_f64( + _a: float64x1_t, + b: float64x2_t, +) -> float64x1_t { + static_assert!(LANE1 == 0); + static_assert_uimm_bits!(LANE2, 1); + unsafe { transmute(vgetq_lane_f64::(b)) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_laneq_s64( + _a: int64x1_t, + b: int64x2_t, +) -> int64x1_t { + static_assert!(LANE1 == 0); + static_assert_uimm_bits!(LANE2, 1); + unsafe { transmute(vgetq_lane_s64::(b)) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_laneq_u64( + _a: uint64x1_t, + b: uint64x2_t, +) -> uint64x1_t { + static_assert!(LANE1 == 0); + static_assert_uimm_bits!(LANE2, 1); + unsafe { transmute(vgetq_lane_u64::(b)) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopy_laneq_p64( + _a: poly64x1_t, + b: poly64x2_t, +) -> poly64x1_t { + static_assert!(LANE1 == 0); + static_assert_uimm_bits!(LANE2, 1); + unsafe { transmute(vgetq_lane_p64::(b)) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] @@ -4521,22 +5042,16 @@ pub fn vcopyq_lane_f32( ) -> float32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: float32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_f32::(vget_lane_f32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_f64( @@ -4545,20 +5060,17 @@ pub fn vcopyq_lane_f64( ) -> float64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: float64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: float64x2_t = vcombine_f64(b, b); + vsetq_lane_f64::(vgetq_lane_f64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s64( @@ -4567,20 +5079,17 @@ pub fn vcopyq_lane_s64( ) -> int64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: int64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: int64x2_t = vcombine_s64(b, b); + vsetq_lane_s64::(vgetq_lane_s64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u64( @@ -4589,20 +5098,38 @@ pub fn vcopyq_lane_u64( ) -> uint64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: uint64x2_t = vcombine_u64(b, b); + vsetq_lane_u64::(vgetq_lane_u64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopyq_lane_p64( + a: poly64x2_t, + b: poly64x1_t, +) -> poly64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert!(LANE2 == 0); + let b: poly64x2_t = vcombine_p64(b, b); + unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 1, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p64( @@ -4611,390 +5138,38 @@ pub fn vcopyq_lane_p64( ) -> poly64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: poly64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = vcombine_p64(b, b); + let ret_val: poly64x2_t = + simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s8(a: int8x16_t, b: int8x8_t) -> int8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: int8x16_t = - unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + let b: int8x16_t = vcombine_s8(b, b); + vsetq_lane_s8::(vgetq_lane_s8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s16( @@ -5003,26 +5178,17 @@ pub fn vcopyq_lane_s16( ) -> int16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: int16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: int16x8_t = vcombine_s16(b, b); + vsetq_lane_s16::(vgetq_lane_s16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s32( @@ -5031,22 +5197,17 @@ pub fn vcopyq_lane_s32( ) -> int32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: int32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: int32x4_t = vcombine_s32(b, b); + vsetq_lane_s32::(vgetq_lane_s32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u8( @@ -5055,371 +5216,17 @@ pub fn vcopyq_lane_u8( ) -> uint8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + let b: uint8x16_t = vcombine_u8(b, b); + vsetq_lane_u8::(vgetq_lane_u8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u16( @@ -5428,26 +5235,17 @@ pub fn vcopyq_lane_u16( ) -> uint16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: uint16x8_t = vcombine_u16(b, b); + vsetq_lane_u16::(vgetq_lane_u16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u32( @@ -5456,22 +5254,17 @@ pub fn vcopyq_lane_u32( ) -> uint32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: uint32x4_t = vcombine_u32(b, b); + vsetq_lane_u32::(vgetq_lane_u32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p8( @@ -5480,371 +5273,17 @@ pub fn vcopyq_lane_p8( ) -> poly8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: poly8x16_t = - unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + let b: poly8x16_t = vcombine_p8(b, b); + vsetq_lane_p8::(vgetq_lane_p8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p16( @@ -5853,26 +5292,17 @@ pub fn vcopyq_lane_p16( ) -> poly16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: poly16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + let b: poly16x8_t = vcombine_p16(b, b); + vsetq_lane_p16::(vgetq_lane_p16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_f32( @@ -5881,21 +5311,16 @@ pub fn vcopyq_laneq_f32( ) -> float32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_f32::(vgetq_lane_f32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_f64( @@ -5904,19 +5329,16 @@ pub fn vcopyq_laneq_f64( ) -> float64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_f64::(vgetq_lane_f64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s8( @@ -5925,369 +5347,16 @@ pub fn vcopyq_laneq_s8( ) -> int8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 4); - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + vsetq_lane_s8::(vgetq_lane_s8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s16( @@ -6296,25 +5365,16 @@ pub fn vcopyq_laneq_s16( ) -> int16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_s16::(vgetq_lane_s16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s32( @@ -6323,21 +5383,16 @@ pub fn vcopyq_laneq_s32( ) -> int32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_s32::(vgetq_lane_s32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s64( @@ -6346,19 +5401,16 @@ pub fn vcopyq_laneq_s64( ) -> int64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_s64::(vgetq_lane_s64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u8( @@ -6367,369 +5419,16 @@ pub fn vcopyq_laneq_u8( ) -> uint8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 4); - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + vsetq_lane_u8::(vgetq_lane_u8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u16( @@ -6738,25 +5437,16 @@ pub fn vcopyq_laneq_u16( ) -> uint16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_u16::(vgetq_lane_u16::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u32( @@ -6765,21 +5455,16 @@ pub fn vcopyq_laneq_u32( ) -> uint32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - unsafe { - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_u32::(vgetq_lane_u32::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u64( @@ -6788,19 +5473,16 @@ pub fn vcopyq_laneq_u64( ) -> uint64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_u64::(vgetq_lane_u64::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p8( @@ -6809,369 +5491,16 @@ pub fn vcopyq_laneq_p8( ) -> poly8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 4); - unsafe { - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } - } + vsetq_lane_p8::(vgetq_lane_p8::(b), a) } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p16( @@ -7180,25 +5509,36 @@ pub fn vcopyq_laneq_p16( ) -> poly16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - unsafe { - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } - } + vsetq_lane_p16::(vgetq_lane_p16::(b), a) +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopyq_laneq_p64( + a: poly64x2_t, + b: poly64x2_t, +) -> poly64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 1); + unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] +#[cfg_attr( + all(test, target_endian = "little"), + assert_instr(mov, LANE1 = 0, LANE2 = 0) +)] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p64( @@ -7208,16 +5548,16 @@ pub fn vcopyq_laneq_p64( static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); unsafe { - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = + simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7226,16 +5566,16 @@ pub fn vcreate_f64(a: u64) -> float64x1_t { } #[doc = "Floating-point convert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtn))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { unsafe { simd_cast(a) } } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7244,7 +5584,7 @@ pub fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7253,7 +5593,7 @@ pub fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7262,7 +5602,7 @@ pub fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7271,7 +5611,7 @@ pub fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7280,9 +5620,9 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { } #[doc = "Floating-point convert to lower precision"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { @@ -7290,9 +5630,9 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { } #[doc = "Floating-point convert to higher precision"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t { @@ -7300,28 +5640,25 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t { } #[doc = "Floating-point convert to lower precision narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { - unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) } + vcombine_f32(a, vcvt_f32_f64(b)) } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { - unsafe { - let b: float32x2_t = simd_shuffle!(a, a, [2, 3]); - simd_cast(b) - } + unsafe { simd_cast(vget_high_f32(a)) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7339,7 +5676,7 @@ pub fn vcvt_n_f64_s64(a: int64x1_t) -> float64x1_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7357,7 +5694,7 @@ pub fn vcvtq_n_f64_s64(a: int64x2_t) -> float64x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7375,7 +5712,7 @@ pub fn vcvt_n_f64_u64(a: uint64x1_t) -> float64x1_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7393,7 +5730,7 @@ pub fn vcvtq_n_f64_u64(a: uint64x2_t) -> float64x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7411,7 +5748,7 @@ pub fn vcvt_n_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7429,7 +5766,7 @@ pub fn vcvtq_n_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7447,7 +5784,7 @@ pub fn vcvt_n_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] @@ -7465,7 +5802,7 @@ pub fn vcvtq_n_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7481,7 +5818,7 @@ pub fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7497,7 +5834,7 @@ pub fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7513,7 +5850,7 @@ pub fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7529,7 +5866,7 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -7546,7 +5883,7 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -7563,7 +5900,7 @@ pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7579,7 +5916,7 @@ pub fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7595,7 +5932,7 @@ pub fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7611,7 +5948,7 @@ pub fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7627,7 +5964,7 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -7644,7 +5981,7 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -7661,7 +5998,7 @@ pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7677,7 +6014,7 @@ pub fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7693,7 +6030,7 @@ pub fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7709,7 +6046,7 @@ pub fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7725,17 +6062,24 @@ pub fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtah_s16_f16(a: f16) -> i16 { - vcvtah_s32_f16(a) as i16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtas.i16.f16" + )] + fn _vcvtah_s16_f16(a: f16) -> i16; + } + unsafe { _vcvtah_s16_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7752,7 +6096,7 @@ pub fn vcvtah_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7769,17 +6113,24 @@ pub fn vcvtah_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtah_u16_f16(a: f16) -> u16 { - vcvtah_u32_f16(a) as u16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtau.i16.f16" + )] + fn _vcvtah_u16_f16(a: f16) -> u16; + } + unsafe { _vcvtah_u16_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7796,7 +6147,7 @@ pub fn vcvtah_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7813,7 +6164,7 @@ pub fn vcvtah_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7829,7 +6180,7 @@ pub fn vcvtas_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7845,7 +6196,7 @@ pub fn vcvtad_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7861,7 +6212,7 @@ pub fn vcvtas_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7877,7 +6228,7 @@ pub fn vcvtad_u64_f64(a: f64) -> u64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7886,7 +6237,7 @@ pub fn vcvtd_f64_s64(a: i64) -> f64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -7895,7 +6246,7 @@ pub fn vcvts_f32_s32(a: i32) -> f32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7905,7 +6256,7 @@ pub fn vcvth_f16_s16(a: i16) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s32)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7915,7 +6266,7 @@ pub fn vcvth_f16_s32(a: i32) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s64)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7925,7 +6276,7 @@ pub fn vcvth_f16_s64(a: i64) -> f16 { } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7935,7 +6286,7 @@ pub fn vcvth_f16_u16(a: u16) -> f16 { } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u32)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7945,7 +6296,7 @@ pub fn vcvth_f16_u32(a: u32) -> f16 { } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u64)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -7955,7 +6306,7 @@ pub fn vcvth_f16_u64(a: u64) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -7967,7 +6318,7 @@ pub fn vcvth_n_f16_s16(a: i16) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -7986,7 +6337,7 @@ pub fn vcvth_n_f16_s32(a: i32) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8005,7 +6356,7 @@ pub fn vcvth_n_f16_s64(a: i64) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8017,7 +6368,7 @@ pub fn vcvth_n_f16_u16(a: u16) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8036,7 +6387,7 @@ pub fn vcvth_n_f16_u32(a: u32) -> f16 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8055,7 +6406,7 @@ pub fn vcvth_n_f16_u64(a: u64) -> f16 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8067,7 +6418,7 @@ pub fn vcvth_n_s16_f16(a: f16) -> i16 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8086,7 +6437,7 @@ pub fn vcvth_n_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8105,7 +6456,7 @@ pub fn vcvth_n_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8117,7 +6468,7 @@ pub fn vcvth_n_u16_f16(a: f16) -> u16 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8136,7 +6487,7 @@ pub fn vcvth_n_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -8155,7 +6506,7 @@ pub fn vcvth_n_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8165,7 +6516,7 @@ pub fn vcvth_s16_f16(a: f16) -> i16 { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8175,7 +6526,7 @@ pub fn vcvth_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8185,7 +6536,7 @@ pub fn vcvth_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8195,7 +6546,7 @@ pub fn vcvth_u16_f16(a: f16) -> u16 { } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8205,7 +6556,7 @@ pub fn vcvth_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8215,7 +6566,7 @@ pub fn vcvth_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8232,7 +6583,7 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8249,7 +6600,7 @@ pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8265,7 +6616,7 @@ pub fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8281,7 +6632,7 @@ pub fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8297,7 +6648,7 @@ pub fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8313,7 +6664,7 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8330,7 +6681,7 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8347,7 +6698,7 @@ pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8363,7 +6714,7 @@ pub fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8379,7 +6730,7 @@ pub fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8395,7 +6746,7 @@ pub fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8411,17 +6762,24 @@ pub fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmh_s16_f16(a: f16) -> i16 { - vcvtmh_s32_f16(a) as i16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtms.i16.f16" + )] + fn _vcvtmh_s16_f16(a: f16) -> i16; + } + unsafe { _vcvtmh_s16_f16(a) } } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8438,7 +6796,7 @@ pub fn vcvtmh_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8453,19 +6811,26 @@ pub fn vcvtmh_s64_f16(a: f16) -> i64 { } unsafe { _vcvtmh_s64_f16(a) } } -#[doc = "Floating-point convert to integer, rounding towards minus infinity"] +#[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmh_u16_f16(a: f16) -> u16 { - vcvtmh_u32_f16(a) as u16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtmu.i16.f16" + )] + fn _vcvtmh_u16_f16(a: f16) -> u16; + } + unsafe { _vcvtmh_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8482,7 +6847,7 @@ pub fn vcvtmh_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8499,7 +6864,7 @@ pub fn vcvtmh_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8515,7 +6880,7 @@ pub fn vcvtms_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8531,7 +6896,7 @@ pub fn vcvtmd_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8547,7 +6912,7 @@ pub fn vcvtms_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8563,7 +6928,7 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8580,7 +6945,7 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8597,7 +6962,7 @@ pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8613,7 +6978,7 @@ pub fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8629,7 +6994,7 @@ pub fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8645,7 +7010,7 @@ pub fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8661,7 +7026,7 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8678,7 +7043,7 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8695,7 +7060,7 @@ pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8711,7 +7076,7 @@ pub fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8727,7 +7092,7 @@ pub fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8743,7 +7108,7 @@ pub fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8759,17 +7124,24 @@ pub fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnh_s16_f16(a: f16) -> i16 { - vcvtnh_s32_f16(a) as i16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtns.i16.f16" + )] + fn _vcvtnh_s16_f16(a: f16) -> i16; + } + unsafe { _vcvtnh_s16_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8786,7 +7158,7 @@ pub fn vcvtnh_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8803,17 +7175,24 @@ pub fn vcvtnh_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnh_u16_f16(a: f16) -> u16 { - vcvtnh_u32_f16(a) as u16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtnu.i16.f16" + )] + fn _vcvtnh_u16_f16(a: f16) -> u16; + } + unsafe { _vcvtnh_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8830,7 +7209,7 @@ pub fn vcvtnh_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -8847,7 +7226,7 @@ pub fn vcvtnh_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8863,7 +7242,7 @@ pub fn vcvtns_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8879,7 +7258,7 @@ pub fn vcvtnd_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8895,7 +7274,7 @@ pub fn vcvtns_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8911,7 +7290,7 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8928,7 +7307,7 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -8945,7 +7324,7 @@ pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8961,7 +7340,7 @@ pub fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8977,7 +7356,7 @@ pub fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -8993,7 +7372,7 @@ pub fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9009,7 +7388,7 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -9026,7 +7405,7 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -9043,7 +7422,7 @@ pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9059,7 +7438,7 @@ pub fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9075,7 +7454,7 @@ pub fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9091,7 +7470,7 @@ pub fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9107,17 +7486,24 @@ pub fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtph_s16_f16(a: f16) -> i16 { - vcvtph_s32_f16(a) as i16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtps.i16.f16" + )] + fn _vcvtph_s16_f16(a: f16) -> i16; + } + unsafe { _vcvtph_s16_f16(a) } } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -9134,7 +7520,7 @@ pub fn vcvtph_s32_f16(a: f16) -> i32 { } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -9151,17 +7537,24 @@ pub fn vcvtph_s64_f16(a: f16) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtph_u16_f16(a: f16) -> u16 { - vcvtph_u32_f16(a) as u16 + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtpu.i16.f16" + )] + fn _vcvtph_u16_f16(a: f16) -> u16; + } + unsafe { _vcvtph_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -9178,7 +7571,7 @@ pub fn vcvtph_u32_f16(a: f16) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u64_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -9195,7 +7588,7 @@ pub fn vcvtph_u64_f16(a: f16) -> u64 { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9211,7 +7604,7 @@ pub fn vcvtps_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9227,7 +7620,7 @@ pub fn vcvtpd_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9243,7 +7636,7 @@ pub fn vcvtps_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9259,7 +7652,7 @@ pub fn vcvtpd_u64_f64(a: f64) -> u64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9268,7 +7661,7 @@ pub fn vcvts_f32_u32(a: u32) -> f32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9277,7 +7670,7 @@ pub fn vcvtd_f64_u64(a: u64) -> f64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9295,7 +7688,7 @@ pub fn vcvts_n_f32_s32(a: i32) -> f32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9313,7 +7706,7 @@ pub fn vcvtd_n_f64_s64(a: i64) -> f64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9331,7 +7724,7 @@ pub fn vcvts_n_f32_u32(a: u32) -> f32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9349,7 +7742,7 @@ pub fn vcvtd_n_f64_u64(a: u64) -> f64 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9367,7 +7760,7 @@ pub fn vcvts_n_s32_f32(a: f32) -> i32 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9385,7 +7778,7 @@ pub fn vcvtd_n_s64_f64(a: f64) -> i64 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9403,7 +7796,7 @@ pub fn vcvts_n_u32_f32(a: f32) -> u32 { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] @@ -9421,7 +7814,7 @@ pub fn vcvtd_n_u64_f64(a: f64) -> u64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9430,7 +7823,7 @@ pub fn vcvts_s32_f32(a: f32) -> i32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9439,7 +7832,7 @@ pub fn vcvtd_s64_f64(a: f64) -> i64 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9448,7 +7841,7 @@ pub fn vcvts_u32_f32(a: f32) -> u32 { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -9457,9 +7850,9 @@ pub fn vcvtd_u64_f64(a: f64) -> u64 { } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtxn))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { unsafe extern "unadjusted" { @@ -9473,25 +7866,25 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtxn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { - unsafe { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) } + vcombine_f32(a, vcvtx_f32_f64(b)) } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcvtxd_f32_f64(a: f64) -> f32 { - unsafe { simd_extract!(vcvtx_f32_f64(vdupq_n_f64(a)), 0) } + vget_lane_f32::<0>(vcvtx_f32_f64(vdupq_n_f64(a))) } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -9501,7 +7894,7 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -9511,7 +7904,7 @@ pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] @@ -9520,7 +7913,7 @@ pub fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] @@ -9529,7 +7922,7 @@ pub fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] @@ -9538,7 +7931,7 @@ pub fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] @@ -9547,7 +7940,7 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -9557,7 +7950,7 @@ pub fn vdivh_f16(a: f16, b: f16) -> f16 { } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] @@ -9568,7 +7961,7 @@ pub fn vdup_lane_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] @@ -9579,161 +7972,161 @@ pub fn vdup_lane_p64(a: poly64x1_t) -> poly64x1_t { } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdup_laneq_f64(a: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(N, 1); - unsafe { transmute::(simd_extract!(a, N as u32)) } + unsafe { transmute(vgetq_lane_f64::(a)) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdup_laneq_p64(a: poly64x2_t) -> poly64x1_t { static_assert_uimm_bits!(N, 1); - unsafe { transmute::(simd_extract!(a, N as u32)) } + unsafe { transmute(vgetq_lane_p64::(a)) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_lane_s8(a: int8x8_t) -> i8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vget_lane_s8::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_laneq_s16(a: int16x8_t) -> i16 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_s16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_lane_u8(a: uint8x8_t) -> u8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vget_lane_u8::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_laneq_u16(a: uint16x8_t) -> u16 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_u16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_lane_p8(a: poly8x8_t) -> p8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vget_lane_p8::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_laneq_p16(a: poly16x8_t) -> p16 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_p16::(a) } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_laneq_s8(a: int8x16_t) -> i8 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_s8::(a) } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_laneq_u8(a: uint8x16_t) -> u8 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_u8::(a) } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupb_laneq_p8(a: poly8x16_t) -> p8 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_p8::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_lane_f64(a: float64x1_t) -> f64 { static_assert!(N == 0); - unsafe { simd_extract!(a, N as u32) } + vget_lane_f64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_lane_s64(a: int64x1_t) -> i64 { static_assert!(N == 0); - unsafe { simd_extract!(a, N as u32) } + vget_lane_s64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_lane_u64(a: uint64x1_t) -> u64 { static_assert!(N == 0); - unsafe { simd_extract!(a, N as u32) } + vget_lane_u64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -9741,11 +8134,11 @@ pub fn vdupd_lane_u64(a: uint64x1_t) -> u64 { #[cfg(not(target_arch = "arm64ec"))] pub fn vduph_lane_f16(a: float16x4_t) -> f16 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vget_lane_f16::(a) } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] @@ -9753,11 +8146,12 @@ pub fn vduph_lane_f16(a: float16x4_t) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vduph_laneq_f16(a: float16x8_t) -> f16 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_f16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 0))] #[rustc_legacy_const_generics(1)] @@ -9767,8 +8161,24 @@ pub fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(dup, N = 0))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { + static_assert!(N == 0); + unsafe { + let ret_val: float64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 0))] #[rustc_legacy_const_generics(1)] @@ -9778,8 +8188,24 @@ pub fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(dup, N = 0))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { + static_assert!(N == 0); + unsafe { + let ret_val: poly64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 1))] #[rustc_legacy_const_generics(1)] @@ -9789,151 +8215,184 @@ pub fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { +pub fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] +#[cfg_attr(test, assert_instr(dup, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vdups_lane_f32(a: float32x2_t) -> f32 { +pub fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(dup, N = 1))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, N = 1))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vdups_lane_f32(a: float32x2_t) -> f32 { + static_assert_uimm_bits!(N, 1); + vget_lane_f32::(a) +} +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_laneq_f64(a: float64x2_t) -> f64 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_f64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_lane_s32(a: int32x2_t) -> i32 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vget_lane_s32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_laneq_s64(a: int64x2_t) -> i64 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_s64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_lane_u32(a: uint32x2_t) -> u32 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vget_lane_u32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdupd_laneq_u64(a: uint64x2_t) -> u64 { static_assert_uimm_bits!(N, 1); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_u64::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_laneq_f32(a: float32x4_t) -> f32 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_f32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_lane_s16(a: int16x4_t) -> i16 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vget_lane_s16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_laneq_s32(a: int32x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_s32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_lane_u16(a: uint16x4_t) -> u16 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vget_lane_u16::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vdups_laneq_u32(a: uint32x4_t) -> u32 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vgetq_lane_u32::(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vduph_lane_p16(a: poly16x4_t) -> p16 { static_assert_uimm_bits!(N, 2); - unsafe { simd_extract!(a, N as u32) } + vget_lane_p16::(a) } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -9949,7 +8408,7 @@ pub fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -9965,7 +8424,7 @@ pub fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -9981,7 +8440,7 @@ pub fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -9997,7 +8456,7 @@ pub fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -10013,7 +8472,7 @@ pub fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -10029,7 +8488,7 @@ pub fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -10045,7 +8504,7 @@ pub fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] @@ -10061,7 +8520,20 @@ pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(ext, N = 1))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ext, N = 1))] #[rustc_legacy_const_generics(2)] @@ -10069,16 +8541,28 @@ pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { pub fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(N, 1); unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(ext, N = 1))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ext, N = 1))] #[rustc_legacy_const_generics(2)] @@ -10086,16 +8570,15 @@ pub fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(N, 1); unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmadd))] @@ -10104,7 +8587,7 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] @@ -10116,11 +8599,11 @@ pub fn vfma_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } + vfma_f16(a, b, vdup_n_f16(vget_lane_f16::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] @@ -10132,11 +8615,11 @@ pub fn vfma_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } + vfma_f16(a, b, vdup_n_f16(vgetq_lane_f16::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] @@ -10148,11 +8631,11 @@ pub fn vfmaq_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } + vfmaq_f16(a, b, vdupq_n_f16(vget_lane_f16::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] @@ -10164,11 +8647,11 @@ pub fn vfmaq_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } + vfmaq_f16(a, b, vdupq_n_f16(vgetq_lane_f16::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10179,11 +8662,11 @@ pub fn vfma_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } + vfma_f32(a, b, vdup_n_f32(vget_lane_f32::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10194,11 +8677,11 @@ pub fn vfma_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } + vfma_f32(a, b, vdup_n_f32(vgetq_lane_f32::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10209,11 +8692,11 @@ pub fn vfmaq_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } + vfmaq_f32(a, b, vdupq_n_f32(vget_lane_f32::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10224,11 +8707,11 @@ pub fn vfmaq_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } + vfmaq_f32(a, b, vdupq_n_f32(vgetq_lane_f32::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10239,11 +8722,11 @@ pub fn vfmaq_laneq_f64( c: float64x2_t, ) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } + vfmaq_f64(a, b, vdupq_n_f64(vgetq_lane_f64::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10254,13 +8737,13 @@ pub fn vfma_lane_f64( c: float64x1_t, ) -> float64x1_t { static_assert!(LANE == 0); - unsafe { vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } + vfma_f64(a, b, vdup_n_f64(vget_lane_f64::(c))) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfma_laneq_f64( @@ -10269,11 +8752,11 @@ pub fn vfma_laneq_f64( c: float64x2_t, ) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } + vfma_f64(a, b, vdup_n_f64(vgetq_lane_f64::(c))) } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -10283,7 +8766,7 @@ pub fn vfma_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t { } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -10293,7 +8776,7 @@ pub fn vfmaq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t { } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmadd))] @@ -10302,21 +8785,19 @@ pub fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmad_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { static_assert!(LANE == 0); - unsafe { - let c: f64 = simd_extract!(c, LANE as u32); - fmaf64(b, c, a) - } + let c: f64 = vget_lane_f64::(c); + fmaf64(b, c, a) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmadd))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -10326,37 +8807,33 @@ pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 { } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"] -#[inline(always)] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[inline] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmah_lane_f16(a: f16, b: f16, v: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: f16 = simd_extract!(v, LANE as u32); - vfmah_f16(a, b, c) - } + let c: f16 = vget_lane_f16::(v); + vfmah_f16(a, b, c) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"] -#[inline(always)] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[inline] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmah_laneq_f16(a: f16, b: f16, v: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: f16 = simd_extract!(v, LANE as u32); - vfmah_f16(a, b, c) - } + let c: f16 = vgetq_lane_f16::(v); + vfmah_f16(a, b, c) } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmla))] @@ -10365,7 +8842,7 @@ pub fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10376,11 +8853,11 @@ pub fn vfmaq_lane_f64( c: float64x1_t, ) -> float64x2_t { static_assert!(LANE == 0); - unsafe { vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } + vfmaq_f64(a, b, vdupq_n_f64(vget_lane_f64::(c))) } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmla))] @@ -10389,49 +8866,44 @@ pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmas_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: f32 = simd_extract!(c, LANE as u32); - fmaf32(b, c, a) - } + let c: f32 = vget_lane_f32::(c); + fmaf32(b, c, a) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmas_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: f32 = simd_extract!(c, LANE as u32); - fmaf32(b, c, a) - } + let c: f32 = vgetq_lane_f32::(c); + fmaf32(b, c, a) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: f64 = simd_extract!(c, LANE as u32); - fmaf64(b, c, a) - } + let c: f64 = vgetq_lane_f64::(c); + fmaf64(b, c, a) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -10448,8 +8920,34 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3 unsafe { _vfmlal_high_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlal2))] +pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlal2.v2f32.v4f16" + )] + fn _vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; + } + unsafe { + let r: float32x2_t = simd_shuffle!(r, r, [1, 0]); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x2_t = _vfmlal_high_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -10465,9 +8963,34 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float } unsafe { _vfmlalq_high_f16(r, a, b) } } +#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlal2))] +pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlal2.v4f32.v8f16" + )] + fn _vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; + } + unsafe { + let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]); + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float32x4_t = _vfmlalq_high_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10480,11 +9003,11 @@ pub fn vfmlal_lane_high_f16( b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlal_high_f16(r, a, vdup_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10497,11 +9020,11 @@ pub fn vfmlal_laneq_high_f16( b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlal_high_f16(r, a, vdup_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10514,11 +9037,11 @@ pub fn vfmlalq_lane_high_f16( b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlalq_high_f16(r, a, vdupq_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10531,11 +9054,11 @@ pub fn vfmlalq_laneq_high_f16( b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlalq_high_f16(r, a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10548,11 +9071,11 @@ pub fn vfmlal_lane_low_f16( b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlal_low_f16(r, a, vdup_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10565,11 +9088,11 @@ pub fn vfmlal_laneq_low_f16( b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlal_low_f16(r, a, vdup_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10582,11 +9105,11 @@ pub fn vfmlalq_lane_low_f16( b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlalq_low_f16(r, a, vdupq_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10599,11 +9122,12 @@ pub fn vfmlalq_laneq_low_f16( b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlalq_low_f16(r, a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -10620,8 +9144,34 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32 unsafe { _vfmlal_low_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlal))] +pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlal.v2f32.v4f16" + )] + fn _vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; + } + unsafe { + let r: float32x2_t = simd_shuffle!(r, r, [1, 0]); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x2_t = _vfmlal_low_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -10637,9 +9187,35 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3 } unsafe { _vfmlalq_low_f16(r, a, b) } } +#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlal))] +pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlal.v4f32.v8f16" + )] + fn _vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; + } + unsafe { + let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]); + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float32x4_t = _vfmlalq_low_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -10656,8 +9232,34 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3 unsafe { _vfmlsl_high_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlsl2))] +pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlsl2.v2f32.v4f16" + )] + fn _vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; + } + unsafe { + let r: float32x2_t = simd_shuffle!(r, r, [1, 0]); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x2_t = _vfmlsl_high_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -10673,9 +9275,34 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float } unsafe { _vfmlslq_high_f16(r, a, b) } } +#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlsl2))] +pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlsl2.v4f32.v8f16" + )] + fn _vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; + } + unsafe { + let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]); + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float32x4_t = _vfmlslq_high_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10688,11 +9315,11 @@ pub fn vfmlsl_lane_high_f16( b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlsl_high_f16(r, a, vdup_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10705,11 +9332,11 @@ pub fn vfmlsl_laneq_high_f16( b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlsl_high_f16(r, a, vdup_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10722,11 +9349,11 @@ pub fn vfmlslq_lane_high_f16( b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlslq_high_f16(r, a, vdupq_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_high_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10739,11 +9366,11 @@ pub fn vfmlslq_laneq_high_f16( b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlslq_high_f16(r, a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10756,11 +9383,11 @@ pub fn vfmlsl_lane_low_f16( b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlsl_low_f16(r, a, vdup_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10773,11 +9400,11 @@ pub fn vfmlsl_laneq_low_f16( b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } + vfmlsl_low_f16(r, a, vdup_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10790,11 +9417,11 @@ pub fn vfmlslq_lane_low_f16( b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlslq_low_f16(r, a, vdupq_lane_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_low_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] @@ -10807,11 +9434,12 @@ pub fn vfmlslq_laneq_low_f16( b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } + vfmlslq_low_f16(r, a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -10828,8 +9456,34 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32 unsafe { _vfmlsl_low_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlsl))] +pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlsl.v2f32.v4f16" + )] + fn _vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; + } + unsafe { + let r: float32x2_t = simd_shuffle!(r, r, [1, 0]); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x2_t = _vfmlsl_low_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -10845,9 +9499,34 @@ pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3 } unsafe { _vfmlslq_low_f16(r, a, b) } } +#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmlsl))] +pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmlsl.v4f32.v8f16" + )] + fn _vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; + } + unsafe { + let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]); + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float32x4_t = _vfmlslq_low_f16(r, a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -10859,7 +9538,7 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] @@ -10871,11 +9550,11 @@ pub fn vfms_lane_f16( c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } + vfms_f16(a, b, vdup_n_f16(vget_lane_f16::(c))) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] @@ -10887,11 +9566,11 @@ pub fn vfms_laneq_f16( c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } + vfms_f16(a, b, vdup_n_f16(vgetq_lane_f16::(c))) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] @@ -10903,11 +9582,11 @@ pub fn vfmsq_lane_f16( c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } + vfmsq_f16(a, b, vdupq_n_f16(vget_lane_f16::(c))) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] @@ -10919,11 +9598,11 @@ pub fn vfmsq_laneq_f16( c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } + vfmsq_f16(a, b, vdupq_n_f16(vgetq_lane_f16::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10934,11 +9613,11 @@ pub fn vfms_lane_f32( c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } + vfms_f32(a, b, vdup_n_f32(vget_lane_f32::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10949,11 +9628,11 @@ pub fn vfms_laneq_f32( c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } + vfms_f32(a, b, vdup_n_f32(vgetq_lane_f32::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10964,11 +9643,11 @@ pub fn vfmsq_lane_f32( c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } + vfmsq_f32(a, b, vdupq_n_f32(vget_lane_f32::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10979,11 +9658,11 @@ pub fn vfmsq_laneq_f32( c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } + vfmsq_f32(a, b, vdupq_n_f32(vgetq_lane_f32::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -10994,11 +9673,11 @@ pub fn vfmsq_laneq_f64( c: float64x2_t, ) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } + vfmsq_f64(a, b, vdupq_n_f64(vgetq_lane_f64::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -11009,13 +9688,13 @@ pub fn vfms_lane_f64( c: float64x1_t, ) -> float64x1_t { static_assert!(LANE == 0); - unsafe { vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } + vfms_f64(a, b, vdup_n_f64(vget_lane_f64::(c))) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfms_laneq_f64( @@ -11024,11 +9703,11 @@ pub fn vfms_laneq_f64( c: float64x2_t, ) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } + vfms_f64(a, b, vdup_n_f64(vgetq_lane_f64::(c))) } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -11038,7 +9717,7 @@ pub fn vfms_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t { } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -11048,7 +9727,7 @@ pub fn vfmsq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t { } #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11057,7 +9736,7 @@ pub fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmsub))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -11067,37 +9746,33 @@ pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 { } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"] -#[inline(always)] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[inline] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsh_lane_f16(a: f16, b: f16, v: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: f16 = simd_extract!(v, LANE as u32); - vfmsh_f16(a, b, c) - } + let c: f16 = vget_lane_f16::(v); + vfmsh_f16(a, b, c) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"] -#[inline(always)] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[inline] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsh_laneq_f16(a: f16, b: f16, v: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: f16 = simd_extract!(v, LANE as u32); - vfmsh_f16(a, b, c) - } + let c: f16 = vgetq_lane_f16::(v); + vfmsh_f16(a, b, c) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11109,7 +9784,7 @@ pub fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] @@ -11120,11 +9795,11 @@ pub fn vfmsq_lane_f64( c: float64x1_t, ) -> float64x2_t { static_assert!(LANE == 0); - unsafe { vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } + vfmsq_f64(a, b, vdupq_n_f64(vget_lane_f64::(c))) } #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11133,9 +9808,9 @@ pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { @@ -11143,9 +9818,9 @@ pub fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { @@ -11153,9 +9828,9 @@ pub fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { @@ -11163,31 +9838,104 @@ pub fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { vfmad_laneq_f64::(a, -b, c) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr(test, assert_instr(ldr))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_high_f64(a: float64x2_t) -> float64x1_t { + unsafe { float64x1_t([simd_extract!(a, 1)]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_high_f64(a: float64x2_t) -> float64x1_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + float64x1_t([simd_extract!(a, 1)]) + } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_low_f64(a: float64x2_t) -> float64x1_t { + unsafe { float64x1_t([simd_extract!(a, 0)]) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_low_f64(a: float64x2_t) -> float64x1_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + float64x1_t([simd_extract!(a, 0)]) + } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +pub fn vgetq_lane_f64(a: float64x2_t) -> f64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(a, IMM5 as u32) } +} +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +pub fn vgetq_lane_f64(a: float64x2_t) -> f64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + simd_extract!(a, IMM5 as u32) + } +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr(test, assert_instr(ldr))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(ldr))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -11199,7 +9947,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11210,7 +9958,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11221,7 +9969,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11232,7 +9980,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11243,7 +9991,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11254,7 +10002,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11265,7 +10013,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11276,7 +10024,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11287,7 +10035,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11298,7 +10046,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11309,7 +10057,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11320,7 +10068,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11331,7 +10079,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11342,7 +10090,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11353,7 +10101,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11364,7 +10112,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11375,7 +10123,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11386,7 +10134,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11397,7 +10145,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11408,7 +10156,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11419,7 +10167,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11430,7 +10178,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11441,7 +10189,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11452,7 +10200,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11463,7 +10211,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11474,7 +10222,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11485,7 +10233,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld))] @@ -11496,7 +10244,7 @@ pub unsafe fn vld1_f64_x2(ptr: *const f64) -> float64x1x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld))] @@ -11507,7 +10255,7 @@ pub unsafe fn vld1_f64_x3(ptr: *const f64) -> float64x1x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld))] @@ -11518,7 +10266,7 @@ pub unsafe fn vld1_f64_x4(ptr: *const f64) -> float64x1x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld))] @@ -11529,7 +10277,7 @@ pub unsafe fn vld1q_f64_x2(ptr: *const f64) -> float64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld))] @@ -11540,7 +10288,7 @@ pub unsafe fn vld1q_f64_x3(ptr: *const f64) -> float64x2x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld))] @@ -11551,7 +10299,7 @@ pub unsafe fn vld1q_f64_x4(ptr: *const f64) -> float64x2x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] @@ -11569,7 +10317,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] @@ -11587,7 +10335,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] @@ -11605,7 +10353,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -11616,7 +10364,7 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11636,7 +10384,7 @@ pub unsafe fn vld2_lane_f64(a: *const f64, b: float64x1x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11656,7 +10404,7 @@ pub unsafe fn vld2_lane_s64(a: *const i64, b: int64x1x2_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11669,7 +10417,7 @@ pub unsafe fn vld2_lane_p64(a: *const p64, b: poly64x1x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11682,8 +10430,7 @@ pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] @@ -11691,52 +10438,21 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { transmute(vld2q_dup_s64(transmute(a))) } #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { - let mut ret_val: poly64x2x2_t = transmute(vld2q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { transmute(vld2q_dup_s64(transmute(a))) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { - let mut ret_val: uint64x2x2_t = transmute(vld2q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] @@ -11754,7 +10470,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] @@ -11772,7 +10488,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11793,7 +10509,7 @@ pub unsafe fn vld2q_lane_f64(a: *const f64, b: float64x2x2_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11813,7 +10529,7 @@ pub unsafe fn vld2q_lane_s8(a: *const i8, b: int8x16x2_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11833,7 +10549,7 @@ pub unsafe fn vld2q_lane_s64(a: *const i64, b: int64x2x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11846,7 +10562,7 @@ pub unsafe fn vld2q_lane_p64(a: *const p64, b: poly64x2x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11859,7 +10575,7 @@ pub unsafe fn vld2q_lane_u8(a: *const u8, b: uint8x16x2_t) -> u #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11872,7 +10588,7 @@ pub unsafe fn vld2q_lane_u64(a: *const u64, b: uint64x2x2_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -11885,8 +10601,7 @@ pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> p #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] @@ -11894,25 +10609,10 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { transmute(vld2q_s64(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { - let mut ret_val: poly64x2x2_t = transmute(vld2q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] @@ -11923,7 +10623,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] @@ -11941,7 +10641,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] @@ -11959,7 +10659,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] @@ -11977,7 +10677,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -11988,7 +10688,7 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12014,7 +10714,7 @@ pub unsafe fn vld3_lane_f64(a: *const f64, b: float64x1x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12027,7 +10727,7 @@ pub unsafe fn vld3_lane_p64(a: *const p64, b: poly64x1x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12053,7 +10753,7 @@ pub unsafe fn vld3_lane_s64(a: *const i64, b: int64x1x3_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12066,8 +10766,7 @@ pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] @@ -12075,90 +10774,43 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { transmute(vld3q_dup_s64(transmute(a))) } #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { - let mut ret_val: poly64x2x3_t = transmute(vld3q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { transmute(vld3q_dup_s64(transmute(a))) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { - let mut ret_val: uint64x2x3_t = transmute(vld3q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2f64.p0" - )] - fn _vld3q_f64(ptr: *const float64x2_t) -> float64x2x3_t; - } - _vld3q_f64(a as _) + crate::core_arch::macros::deinterleaving_load!(f64, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2i64.p0" - )] - fn _vld3q_s64(ptr: *const int64x2_t) -> int64x2x3_t; - } - _vld3q_s64(a as _) + crate::core_arch::macros::deinterleaving_load!(i64, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12184,7 +10836,7 @@ pub unsafe fn vld3q_lane_f64(a: *const f64, b: float64x2x3_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12197,13 +10849,13 @@ pub unsafe fn vld3q_lane_p64(a: *const p64, b: poly64x2x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> int8x16x3_t { - static_assert_uimm_bits!(LANE, 3); + static_assert_uimm_bits!(LANE, 4); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -12223,7 +10875,7 @@ pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12249,7 +10901,7 @@ pub unsafe fn vld3q_lane_s64(a: *const i64, b: int64x2x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12262,7 +10914,7 @@ pub unsafe fn vld3q_lane_u8(a: *const u8, b: uint8x16x3_t) -> u #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12275,7 +10927,7 @@ pub unsafe fn vld3q_lane_u64(a: *const u64, b: uint64x2x3_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12288,8 +10940,7 @@ pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> p #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] @@ -12297,26 +10948,10 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { transmute(vld3q_s64(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { - let mut ret_val: poly64x2x3_t = transmute(vld3q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] @@ -12327,7 +10962,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12345,7 +10980,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12363,7 +10998,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12381,7 +11016,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -12392,7 +11027,7 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12419,7 +11054,7 @@ pub unsafe fn vld4_lane_f64(a: *const f64, b: float64x1x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12446,7 +11081,7 @@ pub unsafe fn vld4_lane_s64(a: *const i64, b: int64x1x4_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12459,7 +11094,7 @@ pub unsafe fn vld4_lane_p64(a: *const p64, b: poly64x1x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12472,8 +11107,7 @@ pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12481,92 +11115,43 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { transmute(vld4q_dup_s64(transmute(a))) } #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { - let mut ret_val: poly64x2x4_t = transmute(vld4q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { transmute(vld4q_dup_s64(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { - let mut ret_val: uint64x2x4_t = transmute(vld4q_dup_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2f64.p0" - )] - fn _vld4q_f64(ptr: *const float64x2_t) -> float64x2x4_t; - } - _vld4q_f64(a as _) + crate::core_arch::macros::deinterleaving_load!(f64, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2i64.p0" - )] - fn _vld4q_s64(ptr: *const int64x2_t) -> int64x2x4_t; - } - _vld4q_s64(a as _) + crate::core_arch::macros::deinterleaving_load!(i64, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12593,13 +11178,13 @@ pub unsafe fn vld4q_lane_f64(a: *const f64, b: float64x2x4_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> int8x16x4_t { - static_assert_uimm_bits!(LANE, 3); + static_assert_uimm_bits!(LANE, 4); unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -12620,7 +11205,7 @@ pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12647,7 +11232,7 @@ pub unsafe fn vld4q_lane_s64(a: *const i64, b: int64x2x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12660,7 +11245,7 @@ pub unsafe fn vld4q_lane_p64(a: *const p64, b: poly64x2x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12673,7 +11258,7 @@ pub unsafe fn vld4q_lane_u8(a: *const u8, b: uint8x16x4_t) -> u #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12686,7 +11271,7 @@ pub unsafe fn vld4q_lane_u64(a: *const u64, b: uint64x2x4_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12699,8 +11284,7 @@ pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> p #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4))] @@ -12708,27 +11292,10 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { transmute(vld4q_s64(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { - let mut ret_val: poly64x2x4_t = transmute(vld4q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] @@ -12739,7 +11306,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12758,7 +11325,7 @@ pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12777,7 +11344,7 @@ pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] @@ -12791,7 +11358,7 @@ pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] @@ -12805,7 +11372,7 @@ pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] @@ -12819,7 +11386,7 @@ pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] @@ -12833,7 +11400,7 @@ pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] @@ -12847,7 +11414,7 @@ pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12860,7 +11427,7 @@ pub unsafe fn vluti2_lane_f16(a: float16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12873,7 +11440,7 @@ pub unsafe fn vluti2q_lane_f16(a: float16x8_t, b: uint8x8_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12886,7 +11453,7 @@ pub unsafe fn vluti2_lane_u8(a: uint8x8_t, b: uint8x8_t) -> ui #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12899,7 +11466,7 @@ pub unsafe fn vluti2q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12912,7 +11479,7 @@ pub unsafe fn vluti2_lane_u16(a: uint16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12925,7 +11492,7 @@ pub unsafe fn vluti2q_lane_u16(a: uint16x8_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12938,7 +11505,7 @@ pub unsafe fn vluti2_lane_p8(a: poly8x8_t, b: uint8x8_t) -> po #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12951,7 +11518,7 @@ pub unsafe fn vluti2q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12964,7 +11531,7 @@ pub unsafe fn vluti2_lane_p16(a: poly16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12977,7 +11544,7 @@ pub unsafe fn vluti2q_lane_p16(a: poly16x8_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -12997,7 +11564,7 @@ pub unsafe fn vluti2_lane_s8(a: int8x8_t, b: uint8x8_t) -> int8 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13017,7 +11584,7 @@ pub unsafe fn vluti2q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13037,7 +11604,7 @@ pub unsafe fn vluti2_lane_s16(a: int16x4_t, b: uint8x8_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13057,7 +11624,7 @@ pub unsafe fn vluti2q_lane_s16(a: int16x8_t, b: uint8x8_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13070,7 +11637,7 @@ pub unsafe fn vluti2_laneq_f16(a: float16x4_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13083,7 +11650,7 @@ pub unsafe fn vluti2q_laneq_f16(a: float16x8_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13096,7 +11663,7 @@ pub unsafe fn vluti2_laneq_u8(a: uint8x8_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13109,7 +11676,7 @@ pub unsafe fn vluti2q_laneq_u8(a: uint8x16_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13122,7 +11689,7 @@ pub unsafe fn vluti2_laneq_u16(a: uint16x4_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13135,7 +11702,7 @@ pub unsafe fn vluti2q_laneq_u16(a: uint16x8_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13148,7 +11715,7 @@ pub unsafe fn vluti2_laneq_p8(a: poly8x8_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13161,7 +11728,7 @@ pub unsafe fn vluti2q_laneq_p8(a: poly8x16_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13174,7 +11741,7 @@ pub unsafe fn vluti2_laneq_p16(a: poly16x4_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13187,7 +11754,7 @@ pub unsafe fn vluti2q_laneq_p16(a: poly16x8_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13207,7 +11774,7 @@ pub unsafe fn vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13227,7 +11794,7 @@ pub unsafe fn vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13247,7 +11814,7 @@ pub unsafe fn vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13267,7 +11834,7 @@ pub unsafe fn vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut,fp16")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13280,7 +11847,7 @@ pub unsafe fn vluti4q_lane_f16_x2(a: float16x8x2_t, b: uint8x8_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13293,7 +11860,7 @@ pub unsafe fn vluti4q_lane_u16_x2(a: uint16x8x2_t, b: uint8x8_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13306,7 +11873,7 @@ pub unsafe fn vluti4q_lane_p16_x2(a: poly16x8x2_t, b: uint8x8_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13326,7 +11893,7 @@ pub unsafe fn vluti4q_lane_s16_x2(a: int16x8x2_t, b: uint8x8_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13346,7 +11913,7 @@ pub unsafe fn vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13359,7 +11926,7 @@ pub unsafe fn vluti4q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> u #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13372,7 +11939,7 @@ pub unsafe fn vluti4q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> p #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut,fp16")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13388,7 +11955,7 @@ pub unsafe fn vluti4q_laneq_f16_x2( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13401,7 +11968,7 @@ pub unsafe fn vluti4q_laneq_u16_x2(a: uint16x8x2_t, b: uint8x16 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13414,7 +11981,7 @@ pub unsafe fn vluti4q_laneq_p16_x2(a: poly16x8x2_t, b: uint8x16 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13434,7 +12001,7 @@ pub unsafe fn vluti4q_laneq_s16_x2(a: int16x8x2_t, b: uint8x16_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13454,7 +12021,7 @@ pub unsafe fn vluti4q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13467,7 +12034,7 @@ pub unsafe fn vluti4q_laneq_u8(a: uint8x16_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13478,7 +12045,7 @@ pub unsafe fn vluti4q_laneq_p8(a: poly8x16_t, b: uint8x16_t) -> } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmax))] @@ -13494,7 +12061,7 @@ pub fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmax))] @@ -13510,7 +12077,7 @@ pub fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13527,7 +12094,7 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] @@ -13543,7 +12110,7 @@ pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] @@ -13559,7 +12126,7 @@ pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point Maximum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13576,7 +12143,7 @@ pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13593,7 +12160,7 @@ pub fn vmaxnmv_f16(a: float16x4_t) -> f16 { } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13610,7 +12177,7 @@ pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 { } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] @@ -13626,7 +12193,7 @@ pub fn vmaxnmv_f32(a: float32x2_t) -> f32 { } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] @@ -13642,7 +12209,7 @@ pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 { } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmv))] @@ -13658,7 +12225,7 @@ pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 { } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13675,7 +12242,7 @@ pub fn vmaxv_f16(a: float16x4_t) -> f16 { } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13692,7 +12259,7 @@ pub fn vmaxvq_f16(a: float16x8_t) -> f16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -13708,7 +12275,7 @@ pub fn vmaxv_f32(a: float32x2_t) -> f32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxv))] @@ -13724,7 +12291,7 @@ pub fn vmaxvq_f32(a: float32x4_t) -> f32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -13740,7 +12307,7 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13749,7 +12316,7 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13758,7 +12325,7 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13767,7 +12334,7 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13776,7 +12343,7 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] @@ -13785,7 +12352,7 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] @@ -13794,7 +12361,7 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13803,7 +12370,7 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13812,7 +12379,7 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13821,7 +12388,7 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13830,7 +12397,7 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] @@ -13839,7 +12406,7 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 { } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] @@ -13848,7 +12415,7 @@ pub fn vmaxvq_u32(a: uint32x4_t) -> u32 { } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmin))] @@ -13864,7 +12431,7 @@ pub fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmin))] @@ -13880,7 +12447,7 @@ pub fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13897,7 +12464,7 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] @@ -13913,7 +12480,7 @@ pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] @@ -13929,7 +12496,7 @@ pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point Minimum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13946,7 +12513,7 @@ pub fn vminnmh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13963,7 +12530,7 @@ pub fn vminnmv_f16(a: float16x4_t) -> f16 { } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -13980,7 +12547,7 @@ pub fn vminnmvq_f16(a: float16x8_t) -> f16 { } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -13996,7 +12563,7 @@ pub fn vminnmv_f32(a: float32x2_t) -> f32 { } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14012,7 +12579,7 @@ pub fn vminnmvq_f64(a: float64x2_t) -> f64 { } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmv))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14028,7 +12595,7 @@ pub fn vminnmvq_f32(a: float32x4_t) -> f32 { } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -14045,7 +12612,7 @@ pub fn vminv_f16(a: float16x4_t) -> f16 { } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -14062,7 +12629,7 @@ pub fn vminvq_f16(a: float16x8_t) -> f16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -14078,7 +12645,7 @@ pub fn vminv_f32(a: float32x2_t) -> f32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminv))] @@ -14094,7 +12661,7 @@ pub fn vminvq_f32(a: float32x4_t) -> f32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -14110,7 +12677,7 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14119,7 +12686,7 @@ pub fn vminv_s8(a: int8x8_t) -> i8 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14128,7 +12695,7 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14137,7 +12704,7 @@ pub fn vminv_s16(a: int16x4_t) -> i16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14146,7 +12713,7 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] @@ -14155,7 +12722,7 @@ pub fn vminv_s32(a: int32x2_t) -> i32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] @@ -14164,7 +12731,7 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14173,7 +12740,7 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14182,7 +12749,7 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14191,7 +12758,7 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14200,7 +12767,7 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] @@ -14209,7 +12776,7 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 { } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] @@ -14218,7 +12785,7 @@ pub fn vminvq_u32(a: uint32x4_t) -> u32 { } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14227,7 +12794,7 @@ pub fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14236,20 +12803,20 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } + vmlal_high_s16(a, b, vdupq_lane_s16::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_laneq_s16( @@ -14258,24 +12825,24 @@ pub fn vmlal_high_laneq_s16( c: int16x8_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } + vmlal_high_s16(a, b, vdupq_laneq_s16::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } + vmlal_high_s32(a, b, vdupq_lane_s32::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_laneq_s32( @@ -14284,13 +12851,13 @@ pub fn vmlal_high_laneq_s32( c: int32x4_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } + vmlal_high_s32(a, b, vdupq_laneq_s32::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_u16( @@ -14299,13 +12866,13 @@ pub fn vmlal_high_lane_u16( c: uint16x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } + vmlal_high_u16(a, b, vdupq_lane_u16::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_laneq_u16( @@ -14314,13 +12881,13 @@ pub fn vmlal_high_laneq_u16( c: uint16x8_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } + vmlal_high_u16(a, b, vdupq_laneq_u16::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_u32( @@ -14329,13 +12896,13 @@ pub fn vmlal_high_lane_u32( c: uint32x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } + vmlal_high_u32(a, b, vdupq_lane_u32::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_laneq_u32( @@ -14344,125 +12911,113 @@ pub fn vmlal_high_laneq_u32( c: uint32x4_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } + vmlal_high_u32(a, b, vdupq_laneq_u32::(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vmlal_high_s16(a, b, vdupq_n_s16(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vmlal_high_s32(a, b, vdupq_n_s32(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { vmlal_high_u16(a, b, vdupq_n_u16(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { vmlal_high_u32(a, b, vdupq_n_u32(c)) } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - unsafe { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlal_s8(a, b, c) - } + let b = vget_high_s8(b); + let c = vget_high_s8(c); + vmlal_s8(a, b, c) } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlal_s16(a, b, c) - } + let b = vget_high_s16(b); + let c = vget_high_s16(c); + vmlal_s16(a, b, c) } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlal_s32(a, b, c) - } + let b = vget_high_s32(b); + let c = vget_high_s32(c); + vmlal_s32(a, b, c) } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - unsafe { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlal_u8(a, b, c) - } + let b = vget_high_u8(b); + let c = vget_high_u8(c); + vmlal_u8(a, b, c) } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - unsafe { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlal_u16(a, b, c) - } + let b = vget_high_u16(b); + let c = vget_high_u16(c); + vmlal_u16(a, b, c) } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - unsafe { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlal_u32(a, b, c) - } + let b = vget_high_u32(b); + let c = vget_high_u32(c); + vmlal_u32(a, b, c) } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14471,7 +13026,7 @@ pub fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14480,20 +13035,20 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } + vmlsl_high_s16(a, b, vdupq_lane_s16::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_laneq_s16( @@ -14502,24 +13057,24 @@ pub fn vmlsl_high_laneq_s16( c: int16x8_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } + vmlsl_high_s16(a, b, vdupq_laneq_s16::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } + vmlsl_high_s32(a, b, vdupq_lane_s32::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_laneq_s32( @@ -14528,13 +13083,13 @@ pub fn vmlsl_high_laneq_s32( c: int32x4_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } + vmlsl_high_s32(a, b, vdupq_laneq_s32::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_u16( @@ -14543,13 +13098,13 @@ pub fn vmlsl_high_lane_u16( c: uint16x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } + vmlsl_high_u16(a, b, vdupq_lane_u16::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_laneq_u16( @@ -14558,13 +13113,13 @@ pub fn vmlsl_high_laneq_u16( c: uint16x8_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } + vmlsl_high_u16(a, b, vdupq_laneq_u16::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_u32( @@ -14573,13 +13128,13 @@ pub fn vmlsl_high_lane_u32( c: uint32x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } + vmlsl_high_u32(a, b, vdupq_lane_u32::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_laneq_u32( @@ -14588,269 +13143,227 @@ pub fn vmlsl_high_laneq_u32( c: uint32x4_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } + vmlsl_high_u32(a, b, vdupq_laneq_u32::(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vmlsl_high_s16(a, b, vdupq_n_s16(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vmlsl_high_s32(a, b, vdupq_n_s32(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { vmlsl_high_u16(a, b, vdupq_n_u16(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { vmlsl_high_u32(a, b, vdupq_n_u32(c)) } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - unsafe { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlsl_s8(a, b, c) - } + let b = vget_high_s8(b); + let c = vget_high_s8(c); + vmlsl_s8(a, b, c) } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlsl_s16(a, b, c) - } + let b = vget_high_s16(b); + let c = vget_high_s16(c); + vmlsl_s16(a, b, c) } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlsl_s32(a, b, c) - } + let b = vget_high_s32(b); + let c = vget_high_s32(c); + vmlsl_s32(a, b, c) } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - unsafe { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlsl_u8(a, b, c) - } + let b = vget_high_u8(b); + let c = vget_high_u8(c); + vmlsl_u8(a, b, c) } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - unsafe { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlsl_u16(a, b, c) - } + let b = vget_high_u16(b); + let c = vget_high_u16(c); + vmlsl_u16(a, b, c) } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - unsafe { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlsl_u32(a, b, c) - } + let b = vget_high_u32(b); + let c = vget_high_u32(c); + vmlsl_u32(a, b, c) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))] pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t { - unsafe { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vmovl_s8(a) - } + let a = vget_high_s8(a); + vmovl_s8(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))] pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t { - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vmovl_s16(a) - } + let a = vget_high_s16(a); + vmovl_s16(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))] pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t { - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - vmovl_s32(a) - } + let a = vget_high_s32(a); + vmovl_s32(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))] pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t { - unsafe { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vmovl_u8(a) - } + let a = vget_high_u8(a); + vmovl_u8(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))] pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t { - unsafe { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vmovl_u16(a) - } + let a = vget_high_u16(a); + vmovl_u16(a) } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))] pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t { - unsafe { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - vmovl_u32(a) - } + let a = vget_high_u32(a); + vmovl_u32(a) } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - unsafe { - let c: int8x8_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) - } + unsafe { vcombine_s8(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - unsafe { - let c: int16x4_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) - } + unsafe { vcombine_s16(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - unsafe { - let c: int32x2_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3]) - } + unsafe { vcombine_s32(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - unsafe { - let c: uint8x8_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) - } + unsafe { vcombine_u8(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - unsafe { - let c: uint16x4_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) - } + unsafe { vcombine_u16(a, simd_cast(b)) } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))] pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - unsafe { - let c: uint32x2_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3]) - } + unsafe { vcombine_u32(a, simd_cast(b)) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmul))] @@ -14859,7 +13372,7 @@ pub fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmul))] @@ -14868,18 +13381,18 @@ pub fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { static_assert!(LANE == 0); - unsafe { simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } + unsafe { simd_mul(a, transmute::(vget_lane_f64::(b))) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -14887,11 +13400,11 @@ pub fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64 #[cfg(not(target_arch = "arm64ec"))] pub fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + unsafe { simd_mul(a, vdup_laneq_f16::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -14899,22 +13412,22 @@ pub fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float1 #[cfg(not(target_arch = "arm64ec"))] pub fn vmulq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 8])) } + unsafe { simd_mul(a, vdupq_laneq_f16::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmul_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } + unsafe { simd_mul(a, transmute::(vgetq_lane_f64::(b))) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14923,7 +13436,7 @@ pub fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -14932,21 +13445,19 @@ pub fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmuld_lane_f64(a: f64, b: float64x1_t) -> f64 { static_assert!(LANE == 0); - unsafe { - let b: f64 = simd_extract!(b, LANE as u32); - a * b - } + let b: f64 = vget_lane_f64::(b); + a * b } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -14956,7 +13467,7 @@ pub fn vmulh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -14964,14 +13475,12 @@ pub fn vmulh_f16(a: f16, b: f16) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulh_lane_f16(a: f16, b: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: f16 = simd_extract!(b, LANE as u32); - a * b - } + let b: f16 = vget_lane_f16::(b); + a * b } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -14979,238 +13488,222 @@ pub fn vmulh_lane_f16(a: f16, b: float16x4_t) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulh_laneq_f16(a: f16, b: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - unsafe { - let b: f16 = simd_extract!(b, LANE as u32); - a * b - } + let b: f16 = vgetq_lane_f16::(b); + a * b } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } + vmull_high_s16(a, vdupq_lane_s16::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } + vmull_high_s16(a, vdupq_laneq_s16::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + vmull_high_s32(a, vdupq_lane_s32::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + vmull_high_s32(a, vdupq_laneq_s32::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } + vmull_high_u16(a, vdupq_lane_u16::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } + vmull_high_u16(a, vdupq_laneq_u16::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + vmull_high_u32(a, vdupq_lane_u32::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + vmull_high_u32(a, vdupq_laneq_u32::(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { vmull_high_s16(a, vdupq_n_s16(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { vmull_high_s32(a, vdupq_n_s32(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { vmull_high_u16(a, vdupq_n_u16(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { vmull_high_u32(a, vdupq_n_u32(b)) } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(pmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))] pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { - unsafe { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) } + vmull_p64(vgetq_lane_p64::<1>(a), vgetq_lane_p64::<1>(b)) } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(pmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))] pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { - unsafe { - let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: poly8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_p8(a, b) - } + let a = vget_high_p8(a); + let b = vget_high_p8(b); + vmull_p8(a, b) } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - unsafe { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_s8(a, b) - } + let a = vget_high_s8(a); + let b = vget_high_s8(b); + vmull_s8(a, b) } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vget_high_s16(b); + vmull_s16(a, b) } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))] pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - vmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vget_high_s32(b); + vmull_s32(a, b) } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - unsafe { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_u8(a, b) - } + let a = vget_high_u8(a); + let b = vget_high_u8(b); + vmull_u8(a, b) } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - unsafe { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vmull_u16(a, b) - } + let a = vget_high_u16(a); + let b = vget_high_u16(b); + vmull_u16(a, b) } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))] pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - unsafe { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - vmull_u32(a, b) - } + let a = vget_high_u32(a); + let b = vget_high_u32(b); + vmull_u32(a, b) } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(pmull))] @@ -15226,71 +13719,65 @@ pub fn vmull_p64(a: p64, b: p64) -> p128 { } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { static_assert!(LANE == 0); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 2])) } + unsafe { simd_mul(a, vdupq_lane_f64::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 2])) } + unsafe { simd_mul(a, vdupq_laneq_f64::(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmuls_lane_f32(a: f32, b: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - unsafe { - let b: f32 = simd_extract!(b, LANE as u32); - a * b - } + let b: f32 = vget_lane_f32::(b); + a * b } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmuls_laneq_f32(a: f32, b: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: f32 = simd_extract!(b, LANE as u32); - a * b - } + let b: f32 = vgetq_lane_f32::(b); + a * b } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - unsafe { - let b: f64 = simd_extract!(b, LANE as u32); - a * b - } + let b: f64 = vgetq_lane_f64::(b); + a * b } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -15307,7 +13794,7 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -15324,7 +13811,7 @@ pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15340,7 +13827,7 @@ pub fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15356,7 +13843,7 @@ pub fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15372,7 +13859,7 @@ pub fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15388,7 +13875,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -15396,11 +13883,11 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulx_f16(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + vmulx_f16(a, vdup_lane_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -15408,11 +13895,11 @@ pub fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float1 #[cfg(not(target_arch = "arm64ec"))] pub fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vmulx_f16(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + vmulx_f16(a, vdup_laneq_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -15420,11 +13907,11 @@ pub fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulxq_f16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } + vmulxq_f16(a, vdupq_lane_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -15432,88 +13919,88 @@ pub fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { vmulxq_f16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } + vmulxq_f16(a, vdupq_laneq_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32; 2])) } + vmulx_f32(a, vdup_lane_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32; 2])) } + vmulx_f32(a, vdup_laneq_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + vmulxq_f32(a, vdupq_lane_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } + vmulxq_f32(a, vdupq_laneq_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32; 2])) } + vmulxq_f64(a, vdupq_laneq_f64::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { static_assert!(LANE == 0); - unsafe { vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } + unsafe { vmulx_f64(a, transmute(vget_lane_f64::(b))) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } + unsafe { vmulx_f64(a, transmute(vgetq_lane_f64::(b))) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_n_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -15523,7 +14010,7 @@ pub fn vmulx_n_f16(a: float16x4_t, b: f16) -> float16x4_t { } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_n_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -15533,7 +14020,7 @@ pub fn vmulxq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15549,7 +14036,7 @@ pub fn vmulxd_f64(a: f64, b: f64) -> f64 { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] @@ -15565,51 +14052,51 @@ pub fn vmulxs_f32(a: f32, b: f32) -> f32 { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxd_lane_f64(a: f64, b: float64x1_t) -> f64 { static_assert!(LANE == 0); - unsafe { vmulxd_f64(a, simd_extract!(b, LANE as u32)) } + vmulxd_f64(a, vget_lane_f64::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxd_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulxd_f64(a, simd_extract!(b, LANE as u32)) } + vmulxd_f64(a, vgetq_lane_f64::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxs_lane_f32(a: f32, b: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulxs_f32(a, simd_extract!(b, LANE as u32)) } + vmulxs_f32(a, vget_lane_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxs_laneq_f32(a: f32, b: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulxs_f32(a, simd_extract!(b, LANE as u32)) } + vmulxs_f32(a, vgetq_lane_f32::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -15626,7 +14113,7 @@ pub fn vmulxh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_lane_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -15634,11 +14121,11 @@ pub fn vmulxh_f16(a: f16, b: f16) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxh_lane_f16(a: f16, b: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulxh_f16(a, simd_extract!(b, LANE as u32)) } + vmulxh_f16(a, vget_lane_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_laneq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] @@ -15646,22 +14133,22 @@ pub fn vmulxh_lane_f16(a: f16, b: float16x4_t) -> f16 { #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxh_laneq_f16(a: f16, b: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - unsafe { vmulxh_f16(a, simd_extract!(b, LANE as u32)) } + vmulxh_f16(a, vgetq_lane_f16::(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { static_assert!(LANE == 0); - unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32; 2])) } + vmulxq_f64(a, vdupq_lane_f64::(b)) } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fneg))] @@ -15670,7 +14157,7 @@ pub fn vneg_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fneg))] @@ -15679,7 +14166,7 @@ pub fn vnegq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] @@ -15688,7 +14175,7 @@ pub fn vneg_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] @@ -15697,7 +14184,7 @@ pub fn vnegq_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] @@ -15706,7 +14193,7 @@ pub fn vnegd_s64(a: i64) -> i64 { } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -15716,33 +14203,29 @@ pub fn vnegh_f16(a: f16) -> f16 { } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub fn vpaddd_f64(a: float64x2_t) -> f64 { - unsafe { - let a1: f64 = simd_extract!(a, 0); - let a2: f64 = simd_extract!(a, 1); - a1 + a2 - } + let a1: f64 = vgetq_lane_f64::<0>(a); + let a2: f64 = vgetq_lane_f64::<1>(a); + a1 + a2 } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub fn vpadds_f32(a: float32x2_t) -> f32 { - unsafe { - let a1: f32 = simd_extract!(a, 0); - let a2: f32 = simd_extract!(a, 1); - a1 + a2 - } + let a1: f32 = vget_lane_f32::<0>(a); + let a2: f32 = vget_lane_f32::<1>(a); + a1 + a2 } #[doc = "Add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15751,7 +14234,7 @@ pub fn vpaddd_s64(a: int64x2_t) -> i64 { } #[doc = "Add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15760,7 +14243,8 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 { } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -15773,11 +14257,30 @@ pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } } #[doc = "Floating-point add pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(faddp))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(faddp))] +pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + let ret_val: float16x8_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); @@ -15786,8 +14289,26 @@ pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + let ret_val: float32x4_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] @@ -15798,9 +14319,27 @@ pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_add(even, odd) } } +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + let ret_val: float64x2_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15812,8 +14351,32 @@ pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + let ret_val: int8x16_t = simd_add(even, odd); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15825,8 +14388,26 @@ pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } } #[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + let ret_val: int16x8_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15838,8 +14419,26 @@ pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } } #[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + let ret_val: int32x4_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15851,8 +14450,26 @@ pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } } #[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + let ret_val: int64x2_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15864,8 +14481,32 @@ pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + let ret_val: uint8x16_t = simd_add(even, odd); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15877,8 +14518,26 @@ pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } } #[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + let ret_val: uint16x8_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15890,8 +14549,26 @@ pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } } #[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + let ret_val: uint32x4_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] @@ -15902,9 +14579,27 @@ pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { simd_add(even, odd) } } +#[doc = "Add Pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(addp))] +pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + let ret_val: uint64x2_t = simd_add(even, odd); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -15920,8 +14615,32 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpmax_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v4f16" + )] + fn _vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpmax_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -15937,8 +14656,32 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { _vpmaxq_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v8f16" + )] + fn _vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vpmaxq_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -15954,8 +14697,32 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpmaxnm_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v4f16" + )] + fn _vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpmaxnm_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -15970,9 +14737,33 @@ pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } unsafe { _vpmaxnmq_f16(a, b) } } +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v8f16" + )] + fn _vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vpmaxnmq_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} #[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -15987,24 +14778,70 @@ pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vpmaxnm_f32(a, b) } } #[doc = "Floating-point Maximum Number Pairwise (vector)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnmp.v4f32" + link_name = "llvm.aarch64.neon.fmaxnmp.v2f32" )] - fn _vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + fn _vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpmaxnm_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v4f32" + )] + fn _vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } unsafe { _vpmaxnmq_f32(a, b) } } #[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v4f32" + )] + fn _vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vpmaxnmq_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16018,9 +14855,32 @@ pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } unsafe { _vpmaxnmq_f64(a, b) } } +#[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v2f64" + )] + fn _vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vpmaxnmq_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Floating-point maximum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16035,8 +14895,29 @@ pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { unsafe { _vpmaxnmqd_f64(a) } } #[doc = "Floating-point maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64" + )] + fn _vpmaxnmqd_f64(a: float64x2_t) -> f64; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + _vpmaxnmqd_f64(a) + } +} +#[doc = "Floating-point maximum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16050,9 +14931,30 @@ pub fn vpmaxnms_f32(a: float32x2_t) -> f32 { } unsafe { _vpmaxnms_f32(a) } } +#[doc = "Floating-point maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpmaxnms_f32(a: float32x2_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32" + )] + fn _vpmaxnms_f32(a: float32x2_t) -> f32; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + _vpmaxnms_f32(a) + } +} #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -16067,8 +14969,31 @@ pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vpmaxq_f32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v4f32" + )] + fn _vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vpmaxq_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -16083,8 +15008,31 @@ pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { _vpmaxq_f64(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v2f64" + )] + fn _vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vpmaxq_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] @@ -16099,8 +15047,37 @@ pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { _vpmaxq_s8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v16i8" + )] + fn _vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = _vpmaxq_s8(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] @@ -16115,8 +15092,31 @@ pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { _vpmaxq_s16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v8i16" + )] + fn _vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = _vpmaxq_s16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] @@ -16131,8 +15131,31 @@ pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { _vpmaxq_s32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v4i32" + )] + fn _vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = _vpmaxq_s32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] @@ -16147,8 +15170,37 @@ pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { _vpmaxq_u8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v16i8" + )] + fn _vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + } + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = _vpmaxq_u8(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] @@ -16163,8 +15215,31 @@ pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { _vpmaxq_u16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v8i16" + )] + fn _vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + } + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = _vpmaxq_u16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] @@ -16178,9 +15253,31 @@ pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } unsafe { _vpmaxq_u32(a, b) } } +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v4i32" + )] + fn _vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vpmaxq_u32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point maximum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -16196,7 +15293,7 @@ pub fn vpmaxqd_f64(a: float64x2_t) -> f64 { } #[doc = "Floating-point maximum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] @@ -16212,7 +15309,8 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 { } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -16228,13 +15326,37 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpmin_f16(a, b) } } #[doc = "Floating-point add pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminp))] -pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v4f16" + )] + fn _vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpmin_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16245,8 +15367,32 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { _vpminq_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v8f16" + )] + fn _vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vpminq_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -16262,8 +15408,32 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { _vpminnm_f16(a, b) } } #[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v4f16" + )] + fn _vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpminnm_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -16278,9 +15448,33 @@ pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } unsafe { _vpminnmq_f16(a, b) } } +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v8f16" + )] + fn _vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = _vpminnmq_f16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} #[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16295,8 +15489,31 @@ pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { _vpminnm_f32(a, b) } } #[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v2f32" + )] + fn _vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpminnm_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16311,8 +15528,31 @@ pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vpminnmq_f32(a, b) } } #[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v4f32" + )] + fn _vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vpminnmq_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16326,9 +15566,32 @@ pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } unsafe { _vpminnmq_f64(a, b) } } +#[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v2f64" + )] + fn _vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vpminnmq_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "Floating-point minimum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16343,8 +15606,29 @@ pub fn vpminnmqd_f64(a: float64x2_t) -> f64 { unsafe { _vpminnmqd_f64(a) } } #[doc = "Floating-point minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnmqd_f64(a: float64x2_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64" + )] + fn _vpminnmqd_f64(a: float64x2_t) -> f64; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + _vpminnmqd_f64(a) + } +} +#[doc = "Floating-point minimum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16358,9 +15642,30 @@ pub fn vpminnms_f32(a: float32x2_t) -> f32 { } unsafe { _vpminnms_f32(a) } } +#[doc = "Floating-point minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fminnmp))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vpminnms_f32(a: float32x2_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32" + )] + fn _vpminnms_f32(a: float32x2_t) -> f32; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + _vpminnms_f32(a) + } +} #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -16375,8 +15680,31 @@ pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { _vpminq_f32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v4f32" + )] + fn _vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = _vpminq_f32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -16391,8 +15719,31 @@ pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { _vpminq_f64(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v2f64" + )] + fn _vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = _vpminq_f64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] @@ -16407,8 +15758,37 @@ pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { _vpminq_s8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v16i8" + )] + fn _vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = _vpminq_s8(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] @@ -16423,8 +15803,31 @@ pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { _vpminq_s16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v8i16" + )] + fn _vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = _vpminq_s16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] @@ -16439,8 +15842,31 @@ pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { _vpminq_s32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v4i32" + )] + fn _vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = _vpminq_s32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] @@ -16455,8 +15881,37 @@ pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { _vpminq_u8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v16i8" + )] + fn _vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + } + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = _vpminq_u8(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] @@ -16471,8 +15926,31 @@ pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { _vpminq_u16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v8i16" + )] + fn _vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + } + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = _vpminq_u16(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] @@ -16486,9 +15964,32 @@ pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } unsafe { _vpminq_u32(a, b) } } +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v4i32" + )] + fn _vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vpminq_u32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Floating-point minimum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -16503,8 +16004,29 @@ pub fn vpminqd_f64(a: float64x2_t) -> f64 { unsafe { _vpminqd_f64(a) } } #[doc = "Floating-point minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpminqd_f64(a: float64x2_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminv.f64.v2f64" + )] + fn _vpminqd_f64(a: float64x2_t) -> f64; + } + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + _vpminqd_f64(a) + } +} +#[doc = "Floating-point minimum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] @@ -16518,9 +16040,29 @@ pub fn vpmins_f32(a: float32x2_t) -> f32 { } unsafe { _vpmins_f32(a) } } +#[doc = "Floating-point minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn vpmins_f32(a: float32x2_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminv.f32.v2f32" + )] + fn _vpmins_f32(a: float32x2_t) -> f32; + } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + _vpmins_f32(a) + } +} #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] @@ -16536,7 +16078,7 @@ pub fn vqabs_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] @@ -16552,25 +16094,25 @@ pub fn vqabsq_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] pub fn vqabsb_s8(a: i8) -> i8 { - unsafe { simd_extract!(vqabs_s8(vdup_n_s8(a)), 0) } + vget_lane_s8::<0>(vqabs_s8(vdup_n_s8(a))) } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] pub fn vqabsh_s16(a: i16) -> i16 { - unsafe { simd_extract!(vqabs_s16(vdup_n_s16(a)), 0) } + vget_lane_s16::<0>(vqabs_s16(vdup_n_s16(a))) } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] @@ -16586,7 +16128,7 @@ pub fn vqabss_s32(a: i32) -> i32 { } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] @@ -16602,51 +16144,51 @@ pub fn vqabsd_s64(a: i64) -> i64 { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] pub fn vqaddb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - unsafe { simd_extract!(vqadd_s8(a, b), 0) } + vget_lane_s8::<0>(vqadd_s8(a, b)) } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] pub fn vqaddh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqadd_s16(a, b), 0) } + vget_lane_s16::<0>(vqadd_s16(a, b)) } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] pub fn vqaddb_u8(a: u8, b: u8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: uint8x8_t = vdup_n_u8(b); - unsafe { simd_extract!(vqadd_u8(a, b), 0) } + vget_lane_u8::<0>(vqadd_u8(a, b)) } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] pub fn vqaddh_u16(a: u16, b: u16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: uint16x4_t = vdup_n_u16(b); - unsafe { simd_extract!(vqadd_u16(a, b), 0) } + vget_lane_u16::<0>(vqadd_u16(a, b)) } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] @@ -16662,7 +16204,7 @@ pub fn vqadds_s32(a: i32, b: i32) -> i32 { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] @@ -16678,7 +16220,7 @@ pub fn vqaddd_s64(a: i64, b: i64) -> i64 { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] @@ -16694,7 +16236,7 @@ pub fn vqadds_u32(a: u32, b: u32) -> u32 { } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] @@ -16710,9 +16252,9 @@ pub fn vqaddd_u64(a: u64, b: u64) -> u64 { } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { @@ -16721,9 +16263,9 @@ pub fn vqdmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { @@ -16732,9 +16274,9 @@ pub fn vqdmlal_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16 } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { @@ -16743,9 +16285,9 @@ pub fn vqdmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { @@ -16754,45 +16296,45 @@ pub fn vqdmlal_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32 } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vqaddq_s32(a, vqdmull_high_n_s16(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { vqaddq_s32(a, vqdmull_high_s16(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vqaddq_s64(a, vqdmull_high_n_s32(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { vqaddq_s64(a, vqdmull_high_s32(b, c)) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 2))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { @@ -16801,9 +16343,9 @@ pub fn vqdmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { @@ -16812,61 +16354,61 @@ pub fn vqdmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlalh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqdmlalh_s16(a, b, vget_lane_s16::(c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlalh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqdmlalh_s16(a, b, vgetq_lane_s16::(c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlals_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } + vqdmlals_s32(a, b, vget_lane_s32::(c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlals_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } + vqdmlals_s32(a, b, vgetq_lane_s32::(c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 { let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); - unsafe { vqadds_s32(a, simd_extract!(x, 0)) } + vqadds_s32(a, vgetq_lane_s32::<0>(x)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -16876,9 +16418,9 @@ pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 { } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { @@ -16887,9 +16429,9 @@ pub fn vqdmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { @@ -16898,9 +16440,9 @@ pub fn vqdmlsl_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16 } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { @@ -16909,9 +16451,9 @@ pub fn vqdmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { @@ -16920,45 +16462,45 @@ pub fn vqdmlsl_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32 } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vqsubq_s32(a, vqdmull_high_n_s16(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { vqsubq_s32(a, vqdmull_high_s16(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vqsubq_s64(a, vqdmull_high_n_s32(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { vqsubq_s64(a, vqdmull_high_s32(b, c)) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 2))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { @@ -16967,9 +16509,9 @@ pub fn vqdmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { @@ -16978,61 +16520,61 @@ pub fn vqdmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlslh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqdmlslh_s16(a, b, vget_lane_s16::(c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlslh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqdmlslh_s16(a, b, vgetq_lane_s16::(c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsls_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } + vqdmlsls_s32(a, b, vget_lane_s32::(c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsls_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } + vqdmlsls_s32(a, b, vgetq_lane_s32::(c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 { let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); - unsafe { vqsubs_s32(a, simd_extract!(x, 0)) } + vqsubs_s32(a, vgetq_lane_s32::<0>(x)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17042,336 +16584,300 @@ pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 { } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } + vqdmulh_s16(a, vdup_n_s16(vget_lane_s16::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } + vqdmulhq_s16(a, vdupq_n_s16(vget_lane_s16::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } + vqdmulh_s32(a, vdup_n_s32(vget_lane_s32::(b))) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } + vqdmulhq_s32(a, vdupq_n_s32(vget_lane_s32::(b))) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { static_assert_uimm_bits!(N, 2); - unsafe { - let b: i16 = simd_extract!(b, N as u32); - vqdmulhh_s16(a, b) - } + let b: i16 = vget_lane_s16::(b); + vqdmulhh_s16(a, b) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { static_assert_uimm_bits!(N, 3); - unsafe { - let b: i16 = simd_extract!(b, N as u32); - vqdmulhh_s16(a, b) - } + let b: i16 = vgetq_lane_s16::(b); + vqdmulhh_s16(a, b) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqdmulh_s16(a, b), 0) } + vget_lane_s16::<0>(vqdmulh_s16(a, b)) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); - unsafe { simd_extract!(vqdmulh_s32(a, b), 0) } + vget_lane_s32::<0>(vqdmulh_s32(a, b)) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { static_assert_uimm_bits!(N, 1); - unsafe { - let b: i32 = simd_extract!(b, N as u32); - vqdmulhs_s32(a, b) - } + let b: i32 = vget_lane_s32::(b); + vqdmulhs_s32(a, b) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - unsafe { - let b: i32 = simd_extract!(b, N as u32); - vqdmulhs_s32(a, b) - } + let b: i32 = vgetq_lane_s32::(b); + vqdmulhs_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vdup_lane_s16::(b); + vqdmull_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vdup_laneq_s32::(b); + vqdmull_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 1))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vdup_lane_s32::(b); + vqdmull_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 4))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vdup_laneq_s16::(b); + vqdmull_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = vdup_n_s16(b); - vqdmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vdup_n_s16(b); + vqdmull_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = vdup_n_s32(b); - vqdmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vdup_n_s32(b); + vqdmull_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vqdmull_s16(a, b) - } + let a = vget_high_s16(a); + let b = vget_high_s16(b); + vqdmull_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - vqdmull_s32(a, b) - } + let a = vget_high_s32(a); + let b = vget_high_s32(b); + vqdmull_s32(a, b) } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); - unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) - } + let b = vdup_laneq_s16::(b); + vqdmull_s16(a, b) } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) - } + let b = vdup_laneq_s32::(b); + vqdmull_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmullh_lane_s16(a: i16, b: int16x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - unsafe { - let b: i16 = simd_extract!(b, N as u32); - vqdmullh_s16(a, b) - } + let b: i16 = vget_lane_s16::(b); + vqdmullh_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulls_laneq_s32(a: i32, b: int32x4_t) -> i64 { static_assert_uimm_bits!(N, 2); - unsafe { - let b: i32 = simd_extract!(b, N as u32); - vqdmulls_s32(a, b) - } + let b: i32 = vgetq_lane_s32::(b); + vqdmulls_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmullh_laneq_s16(a: i16, b: int16x8_t) -> i32 { static_assert_uimm_bits!(N, 3); - unsafe { - let b: i16 = simd_extract!(b, N as u32); - vqdmullh_s16(a, b) - } + let b: i16 = vgetq_lane_s16::(b); + vqdmullh_s16(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmullh_s16(a: i16, b: i16) -> i32 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqdmull_s16(a, b), 0) } + vgetq_lane_s32::<0>(vqdmull_s16(a, b)) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmulls_lane_s32(a: i32, b: int32x2_t) -> i64 { static_assert_uimm_bits!(N, 1); - unsafe { - let b: i32 = simd_extract!(b, N as u32); - vqdmulls_s32(a, b) - } + let b: i32 = vget_lane_s32::(b); + vqdmulls_s32(a, b) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17387,73 +16893,61 @@ pub fn vqdmulls_s32(a: i32, b: i32) -> i64 { } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - unsafe { - simd_shuffle!( - a, - vqmovn_s16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vqmovn_s16(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - unsafe { simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vqmovn_s32(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - unsafe { simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) } + vcombine_s32(a, vqmovn_s64(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - unsafe { - simd_shuffle!( - a, - vqmovn_u16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqmovn_u16(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqmovn_u32(b)) } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqmovn_u64(b)) } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17469,7 +16963,7 @@ pub fn vqmovnd_s64(a: i64) -> i32 { } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -17485,103 +16979,97 @@ pub fn vqmovnd_u64(a: u64) -> u32 { } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovnh_s16(a: i16) -> i8 { - unsafe { simd_extract!(vqmovn_s16(vdupq_n_s16(a)), 0) } + vget_lane_s8::<0>(vqmovn_s16(vdupq_n_s16(a))) } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovns_s32(a: i32) -> i16 { - unsafe { simd_extract!(vqmovn_s32(vdupq_n_s32(a)), 0) } + vget_lane_s16::<0>(vqmovn_s32(vdupq_n_s32(a))) } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovnh_u16(a: u16) -> u8 { - unsafe { simd_extract!(vqmovn_u16(vdupq_n_u16(a)), 0) } + vget_lane_u8::<0>(vqmovn_u16(vdupq_n_u16(a))) } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovns_u32(a: u32) -> u16 { - unsafe { simd_extract!(vqmovn_u32(vdupq_n_u32(a)), 0) } + vget_lane_u16::<0>(vqmovn_u32(vdupq_n_u32(a))) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { - unsafe { - simd_shuffle!( - a, - vqmovun_s16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqmovun_s16(b)) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqmovun_s32(b)) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqmovun_s64(b)) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovunh_s16(a: i16) -> u8 { - unsafe { simd_extract!(vqmovun_s16(vdupq_n_s16(a)), 0) } + vget_lane_u8::<0>(vqmovun_s16(vdupq_n_s16(a))) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovuns_s32(a: i32) -> u16 { - unsafe { simd_extract!(vqmovun_s32(vdupq_n_s32(a)), 0) } + vget_lane_u16::<0>(vqmovun_s32(vdupq_n_s32(a))) } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqmovund_s64(a: i64) -> u32 { - unsafe { simd_extract!(vqmovun_s64(vdupq_n_s64(a)), 0) } + vget_lane_u32::<0>(vqmovun_s64(vdupq_n_s64(a))) } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] @@ -17597,7 +17085,7 @@ pub fn vqneg_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] @@ -17613,155 +17101,139 @@ pub fn vqnegq_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] pub fn vqnegb_s8(a: i8) -> i8 { - unsafe { simd_extract!(vqneg_s8(vdup_n_s8(a)), 0) } + vget_lane_s8::<0>(vqneg_s8(vdup_n_s8(a))) } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] pub fn vqnegh_s16(a: i16) -> i16 { - unsafe { simd_extract!(vqneg_s16(vdup_n_s16(a)), 0) } + vget_lane_s16::<0>(vqneg_s16(vdup_n_s16(a))) } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] pub fn vqnegs_s32(a: i32) -> i32 { - unsafe { simd_extract!(vqneg_s32(vdup_n_s32(a)), 0) } + vget_lane_s32::<0>(vqneg_s32(vdup_n_s32(a))) } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] pub fn vqnegd_s64(a: i64) -> i64 { - unsafe { simd_extract!(vqneg_s64(vdup_n_s64(a)), 0) } + vget_lane_s64::<0>(vqneg_s64(vdup_n_s64(a))) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlah_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); - vqrdmlah_s16(a, b, c) - } + let c = vdup_lane_s16::(c); + vqrdmlah_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlah_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]); - vqrdmlah_s32(a, b, c) - } + let c = vdup_lane_s32::(c); + vqrdmlah_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlah_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); - vqrdmlah_s16(a, b, c) - } + let c = vdup_laneq_s16::(c); + vqrdmlah_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlah_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]); - vqrdmlah_s32(a, b, c) - } + let c = vdup_laneq_s32::(c); + vqrdmlah_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]); - vqrdmlahq_s16(a, b, c) - } + let c = vdupq_lane_s16::(c); + vqrdmlahq_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); - vqrdmlahq_s32(a, b, c) - } + let c = vdupq_lane_s32::(c); + vqrdmlahq_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]); - vqrdmlahq_s16(a, b, c) - } + let c = vdupq_laneq_s16::(c); + vqrdmlahq_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); - vqrdmlahq_s32(a, b, c) - } + let c = vdupq_laneq_s32::(c); + vqrdmlahq_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -17777,7 +17249,7 @@ pub fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -17793,7 +17265,7 @@ pub fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -17809,7 +17281,7 @@ pub fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -17825,51 +17297,51 @@ pub fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlahh_s16(a, b, vget_lane_s16::(c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlahh_s16(a, b, vgetq_lane_s16::(c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlahs_s32(a, b, vget_lane_s32::(c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlahs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlahs_s32(a, b, vgetq_lane_s32::(c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -17877,11 +17349,11 @@ pub fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); let c: int16x4_t = vdup_n_s16(c); - unsafe { simd_extract!(vqrdmlah_s16(a, b, c), 0) } + vget_lane_s16::<0>(vqrdmlah_s16(a, b, c)) } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -17889,123 +17361,107 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); let c: int32x2_t = vdup_n_s32(c); - unsafe { simd_extract!(vqrdmlah_s32(a, b, c), 0) } + vget_lane_s32::<0>(vqrdmlah_s32(a, b, c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlsh_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); - vqrdmlsh_s16(a, b, c) - } + let c = vdup_lane_s16::(c); + vqrdmlsh_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlsh_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]); - vqrdmlsh_s32(a, b, c) - } + let c = vdup_lane_s32::(c); + vqrdmlsh_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlsh_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); - vqrdmlsh_s16(a, b, c) - } + let c = vdup_laneq_s16::(c); + vqrdmlsh_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlsh_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]); - vqrdmlsh_s32(a, b, c) - } + let c = vdup_laneq_s32::(c); + vqrdmlsh_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]); - vqrdmlshq_s16(a, b, c) - } + let c = vdupq_lane_s16::(c); + vqrdmlshq_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); - vqrdmlshq_s32(a, b, c) - } + let c = vdupq_lane_s32::(c); + vqrdmlshq_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]); - vqrdmlshq_s16(a, b, c) - } + let c = vdupq_laneq_s16::(c); + vqrdmlshq_s16(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); - vqrdmlshq_s32(a, b, c) - } + let c = vdupq_laneq_s32::(c); + vqrdmlshq_s32(a, b, c) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18021,7 +17477,7 @@ pub fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18037,7 +17493,7 @@ pub fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18053,7 +17509,7 @@ pub fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18069,51 +17525,51 @@ pub fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlshh_s16(a, b, vget_lane_s16::(c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlshh_s16(a, b, vgetq_lane_s16::(c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlshs_s32(a, b, vget_lane_s32::(c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] pub fn vqrdmlshs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } + vqrdmlshs_s32(a, b, vgetq_lane_s32::(c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18121,11 +17577,11 @@ pub fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); let c: int16x4_t = vdup_n_s16(c); - unsafe { simd_extract!(vqrdmlsh_s16(a, b, c), 0) } + vget_lane_s16::<0>(vqrdmlsh_s16(a, b, c)) } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] @@ -18133,117 +17589,117 @@ pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); let c: int32x2_t = vdup_n_s32(c); - unsafe { simd_extract!(vqrdmlsh_s32(a, b, c), 0) } + vget_lane_s32::<0>(vqrdmlsh_s32(a, b, c)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } + vqrdmulhh_s16(a, vget_lane_s16::(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - unsafe { vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } + vqrdmulhh_s16(a, vgetq_lane_s16::(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - unsafe { vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } + vqrdmulhs_s32(a, vget_lane_s32::(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - unsafe { vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } + vqrdmulhs_s32(a, vgetq_lane_s32::(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { - unsafe { simd_extract!(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) } + vget_lane_s16::<0>(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b))) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { - unsafe { simd_extract!(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) } + vget_lane_s32::<0>(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b))) } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshlb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - unsafe { simd_extract!(vqrshl_s8(a, b), 0) } + vget_lane_s8::<0>(vqrshl_s8(a, b)) } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshlh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqrshl_s16(a, b), 0) } + vget_lane_s16::<0>(vqrshl_s16(a, b)) } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshlb_u8(a: u8, b: i8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: int8x8_t = vdup_n_s8(b); - unsafe { simd_extract!(vqrshl_u8(a, b), 0) } + vget_lane_u8::<0>(vqrshl_u8(a, b)) } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshlh_u16(a: u16, b: i16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqrshl_u16(a, b), 0) } + vget_lane_u16::<0>(vqrshl_u16(a, b)) } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18259,7 +17715,7 @@ pub fn vqrshld_s64(a: i64, b: i64) -> i64 { } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18275,7 +17731,7 @@ pub fn vqrshls_s32(a: i32, b: i32) -> i32 { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18291,7 +17747,7 @@ pub fn vqrshls_u32(a: u32, b: i32) -> u32 { } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18307,85 +17763,73 @@ pub fn vqrshld_u64(a: u64, b: i64) -> u64 { } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqrshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vqrshrn_n_s16::(b)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vqrshrn_n_s32::(b)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqrshrn_n_s64::(b), [0, 1, 2, 3]) } + vcombine_s32(a, vqrshrn_n_s64::(b)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqrshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqrshrn_n_u16::(b)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqrshrn_n_u32::(b)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqrshrn_n_u64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqrshrn_n_u64::(b)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18393,11 +17837,11 @@ pub fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x pub fn vqrshrnd_n_u64(a: u64) -> u32 { static_assert!(N >= 1 && N <= 32); let a: uint64x2_t = vdupq_n_u64(a); - unsafe { simd_extract!(vqrshrn_n_u64::(a), 0) } + vget_lane_u32::<0>(vqrshrn_n_u64::(a)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18405,11 +17849,11 @@ pub fn vqrshrnd_n_u64(a: u64) -> u32 { pub fn vqrshrnh_n_u16(a: u16) -> u8 { static_assert!(N >= 1 && N <= 8); let a: uint16x8_t = vdupq_n_u16(a); - unsafe { simd_extract!(vqrshrn_n_u16::(a), 0) } + vget_lane_u8::<0>(vqrshrn_n_u16::(a)) } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18417,11 +17861,11 @@ pub fn vqrshrnh_n_u16(a: u16) -> u8 { pub fn vqrshrns_n_u32(a: u32) -> u16 { static_assert!(N >= 1 && N <= 16); let a: uint32x4_t = vdupq_n_u32(a); - unsafe { simd_extract!(vqrshrn_n_u32::(a), 0) } + vget_lane_u16::<0>(vqrshrn_n_u32::(a)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18429,11 +17873,11 @@ pub fn vqrshrns_n_u32(a: u32) -> u16 { pub fn vqrshrnh_n_s16(a: i16) -> i8 { static_assert!(N >= 1 && N <= 8); let a: int16x8_t = vdupq_n_s16(a); - unsafe { simd_extract!(vqrshrn_n_s16::(a), 0) } + vget_lane_s8::<0>(vqrshrn_n_s16::(a)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18441,11 +17885,11 @@ pub fn vqrshrnh_n_s16(a: i16) -> i8 { pub fn vqrshrns_n_s32(a: i32) -> i16 { static_assert!(N >= 1 && N <= 16); let a: int32x4_t = vdupq_n_s32(a); - unsafe { simd_extract!(vqrshrn_n_s32::(a), 0) } + vget_lane_s16::<0>(vqrshrn_n_s32::(a)) } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18453,50 +17897,44 @@ pub fn vqrshrns_n_s32(a: i32) -> i16 { pub fn vqrshrnd_n_s64(a: i64) -> i32 { static_assert!(N >= 1 && N <= 32); let a: int64x2_t = vdupq_n_s64(a); - unsafe { simd_extract!(vqrshrn_n_s64::(a), 0) } + vget_lane_s32::<0>(vqrshrn_n_s64::(a)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqrshrun_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqrshrun_n_s16::(b)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqrshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqrshrun_n_s32::(b)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqrshrun_n_s64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqrshrun_n_s64::(b)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18504,11 +17942,11 @@ pub fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x pub fn vqrshrund_n_s64(a: i64) -> u32 { static_assert!(N >= 1 && N <= 32); let a: int64x2_t = vdupq_n_s64(a); - unsafe { simd_extract!(vqrshrun_n_s64::(a), 0) } + vget_lane_u32::<0>(vqrshrun_n_s64::(a)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18516,11 +17954,11 @@ pub fn vqrshrund_n_s64(a: i64) -> u32 { pub fn vqrshrunh_n_s16(a: i16) -> u8 { static_assert!(N >= 1 && N <= 8); let a: int16x8_t = vdupq_n_s16(a); - unsafe { simd_extract!(vqrshrun_n_s16::(a), 0) } + vget_lane_u8::<0>(vqrshrun_n_s16::(a)) } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18528,159 +17966,159 @@ pub fn vqrshrunh_n_s16(a: i16) -> u8 { pub fn vqrshruns_n_s32(a: i32) -> u16 { static_assert!(N >= 1 && N <= 16); let a: int32x4_t = vdupq_n_s32(a); - unsafe { simd_extract!(vqrshrun_n_s32::(a), 0) } + vget_lane_u16::<0>(vqrshrun_n_s32::(a)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlb_n_s8(a: i8) -> i8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(vqshl_n_s8::(vdup_n_s8(a)), 0) } + vget_lane_s8::<0>(vqshl_n_s8::(vdup_n_s8(a))) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshld_n_s64(a: i64) -> i64 { static_assert_uimm_bits!(N, 6); - unsafe { simd_extract!(vqshl_n_s64::(vdup_n_s64(a)), 0) } + vget_lane_s64::<0>(vqshl_n_s64::(vdup_n_s64(a))) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlh_n_s16(a: i16) -> i16 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(vqshl_n_s16::(vdup_n_s16(a)), 0) } + vget_lane_s16::<0>(vqshl_n_s16::(vdup_n_s16(a))) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshls_n_s32(a: i32) -> i32 { static_assert_uimm_bits!(N, 5); - unsafe { simd_extract!(vqshl_n_s32::(vdup_n_s32(a)), 0) } + vget_lane_s32::<0>(vqshl_n_s32::(vdup_n_s32(a))) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlb_n_u8(a: u8) -> u8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(vqshl_n_u8::(vdup_n_u8(a)), 0) } + vget_lane_u8::<0>(vqshl_n_u8::(vdup_n_u8(a))) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshld_n_u64(a: u64) -> u64 { static_assert_uimm_bits!(N, 6); - unsafe { simd_extract!(vqshl_n_u64::(vdup_n_u64(a)), 0) } + vget_lane_u64::<0>(vqshl_n_u64::(vdup_n_u64(a))) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlh_n_u16(a: u16) -> u16 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(vqshl_n_u16::(vdup_n_u16(a)), 0) } + vget_lane_u16::<0>(vqshl_n_u16::(vdup_n_u16(a))) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshls_n_u32(a: u32) -> u32 { static_assert_uimm_bits!(N, 5); - unsafe { simd_extract!(vqshl_n_u32::(vdup_n_u32(a)), 0) } + vget_lane_u32::<0>(vqshl_n_u32::(vdup_n_u32(a))) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlb_s8(a: i8, b: i8) -> i8 { let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_s8::<0>(c) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlh_s16(a: i16, b: i16) -> i16 { let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_s16::<0>(c) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshls_s32(a: i32, b: i32) -> i32 { let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_s32::<0>(c) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlb_u8(a: u8, b: i8) -> u8 { let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_u8::<0>(c) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlh_u16(a: u16, b: i16) -> u16 { let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_u16::<0>(c) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshls_u32(a: u32, b: i32) -> u32 { let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b)); - unsafe { simd_extract!(c, 0) } + vget_lane_u32::<0>(c) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18696,7 +18134,7 @@ pub fn vqshld_s64(a: i64, b: i64) -> i64 { } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -18712,129 +18150,117 @@ pub fn vqshld_u64(a: u64, b: i64) -> u64 { } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlub_n_s8(a: i8) -> u8 { static_assert_uimm_bits!(N, 3); - unsafe { simd_extract!(vqshlu_n_s8::(vdup_n_s8(a)), 0) } + vget_lane_u8::<0>(vqshlu_n_s8::(vdup_n_s8(a))) } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlud_n_s64(a: i64) -> u64 { static_assert_uimm_bits!(N, 6); - unsafe { simd_extract!(vqshlu_n_s64::(vdup_n_s64(a)), 0) } + vget_lane_u64::<0>(vqshlu_n_s64::(vdup_n_s64(a))) } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshluh_n_s16(a: i16) -> u16 { static_assert_uimm_bits!(N, 4); - unsafe { simd_extract!(vqshlu_n_s16::(vdup_n_s16(a)), 0) } + vget_lane_u16::<0>(vqshlu_n_s16::(vdup_n_s16(a))) } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshlus_n_s32(a: i32) -> u32 { static_assert_uimm_bits!(N, 5); - unsafe { simd_extract!(vqshlu_n_s32::(vdup_n_s32(a)), 0) } + vget_lane_u32::<0>(vqshlu_n_s32::(vdup_n_s32(a))) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vqshrn_n_s16::(b)) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vqshrn_n_s32::(b)) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqshrn_n_s64::(b), [0, 1, 2, 3]) } + vcombine_s32(a, vqshrn_n_s64::(b)) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqshrn_n_u16::(b)) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqshrn_n_u32::(b)) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqshrn_n_u64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqshrn_n_u64::(b)) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18852,7 +18278,7 @@ pub fn vqshrnd_n_s64(a: i64) -> i32 { } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] @@ -18870,167 +18296,161 @@ pub fn vqshrnd_n_u64(a: u64) -> u32 { } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrnh_n_s16(a: i16) -> i8 { static_assert!(N >= 1 && N <= 8); - unsafe { simd_extract!(vqshrn_n_s16::(vdupq_n_s16(a)), 0) } + vget_lane_s8::<0>(vqshrn_n_s16::(vdupq_n_s16(a))) } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrns_n_s32(a: i32) -> i16 { static_assert!(N >= 1 && N <= 16); - unsafe { simd_extract!(vqshrn_n_s32::(vdupq_n_s32(a)), 0) } + vget_lane_s16::<0>(vqshrn_n_s32::(vdupq_n_s32(a))) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrnh_n_u16(a: u16) -> u8 { static_assert!(N >= 1 && N <= 8); - unsafe { simd_extract!(vqshrn_n_u16::(vdupq_n_u16(a)), 0) } + vget_lane_u8::<0>(vqshrn_n_u16::(vdupq_n_u16(a))) } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrns_n_u32(a: u32) -> u16 { static_assert!(N >= 1 && N <= 16); - unsafe { simd_extract!(vqshrn_n_u32::(vdupq_n_u32(a)), 0) } + vget_lane_u16::<0>(vqshrn_n_u32::(vdupq_n_u32(a))) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vqshrun_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vqshrun_n_s16::(b)) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vqshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vqshrun_n_s32::(b)) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vqshrun_n_s64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vqshrun_n_s64::(b)) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrund_n_s64(a: i64) -> u32 { static_assert!(N >= 1 && N <= 32); - unsafe { simd_extract!(vqshrun_n_s64::(vdupq_n_s64(a)), 0) } + vget_lane_u32::<0>(vqshrun_n_s64::(vdupq_n_s64(a))) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshrunh_n_s16(a: i16) -> u8 { static_assert!(N >= 1 && N <= 8); - unsafe { simd_extract!(vqshrun_n_s16::(vdupq_n_s16(a)), 0) } + vget_lane_u8::<0>(vqshrun_n_s16::(vdupq_n_s16(a))) } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqshruns_n_s32(a: i32) -> u16 { static_assert!(N >= 1 && N <= 16); - unsafe { simd_extract!(vqshrun_n_s32::(vdupq_n_s32(a)), 0) } + vget_lane_u16::<0>(vqshrun_n_s32::(vdupq_n_s32(a))) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] pub fn vqsubb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - unsafe { simd_extract!(vqsub_s8(a, b), 0) } + vget_lane_s8::<0>(vqsub_s8(a, b)) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] pub fn vqsubh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - unsafe { simd_extract!(vqsub_s16(a, b), 0) } + vget_lane_s16::<0>(vqsub_s16(a, b)) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] pub fn vqsubb_u8(a: u8, b: u8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: uint8x8_t = vdup_n_u8(b); - unsafe { simd_extract!(vqsub_u8(a, b), 0) } + vget_lane_u8::<0>(vqsub_u8(a, b)) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] pub fn vqsubh_u16(a: u16, b: u16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: uint16x4_t = vdup_n_u16(b); - unsafe { simd_extract!(vqsub_u16(a, b), 0) } + vget_lane_u16::<0>(vqsub_u16(a, b)) } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] @@ -19046,7 +18466,7 @@ pub fn vqsubs_s32(a: i32, b: i32) -> i32 { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] @@ -19062,7 +18482,7 @@ pub fn vqsubd_s64(a: i64, b: i64) -> i64 { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] @@ -19078,7 +18498,7 @@ pub fn vqsubs_u32(a: u32, b: u32) -> u32 { } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] @@ -19094,7 +18514,7 @@ pub fn vqsubd_u64(a: u64, b: u64) -> u64 { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19110,7 +18530,7 @@ fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19126,7 +18546,8 @@ fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19134,44 +18555,139 @@ pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t { vqtbl1(a, b) } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { - vqtbl1q(a, b) +pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbl1(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vqtbl1(transmute(a), b)) } +pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { + vqtbl1q(a, b) } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { transmute(vqtbl1q(transmute(a), b)) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] +pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbl1q(a, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vqtbl1(transmute(a), b)) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbl1(transmute(a), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vqtbl1q(transmute(a), b)) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = transmute(vqtbl1q(transmute(a), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl1(transmute(a), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbl1(transmute(a), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19179,8 +18695,29 @@ pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbl1q(transmute(a), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = transmute(vqtbl1q(transmute(a), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19196,7 +18733,7 @@ fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19212,7 +18749,8 @@ fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19220,8 +18758,34 @@ pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t { vqtbl2(a.0, a.1, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t { + let mut a: int8x16x2_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbl2(a.0, a.1, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19229,8 +18793,39 @@ pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t { vqtbl2q(a.0, a.1, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t { + let mut a: int8x16x2_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbl2q(a.0, a.1, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19238,8 +18833,34 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { + let mut a: uint8x16x2_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19247,8 +18868,39 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { + let mut a: uint8x16x2_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19256,8 +18908,34 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { + let mut a: poly8x16x2_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19265,8 +18943,38 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { + let mut a: poly8x16x2_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19282,7 +18990,7 @@ fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19298,7 +19006,8 @@ fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19306,8 +19015,39 @@ pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t { vqtbl3(a.0, a.1, a.2, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t { + let mut a: int8x16x3_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbl3(a.0, a.1, a.2, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19315,8 +19055,44 @@ pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { vqtbl3q(a.0, a.1, a.2, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { + let mut a: int8x16x3_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbl3q(a.0, a.1, a.2, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19324,8 +19100,40 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { + let mut a: uint8x16x3_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = + transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19333,17 +19141,86 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { +pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { + let mut a: uint8x16x3_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { + let mut a: poly8x16x3_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = + transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19351,8 +19228,44 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { + let mut a: poly8x16x3_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19374,7 +19287,7 @@ fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19396,7 +19309,8 @@ fn vqtbl4q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19404,8 +19318,44 @@ pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t { vqtbl4(a.0, a.1, a.2, a.3, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t { + let mut a: int8x16x4_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.3 = simd_shuffle!( + a.3, + a.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbl4(a.0, a.1, a.2, a.3, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19413,8 +19363,49 @@ pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t { vqtbl4q(a.0, a.1, a.2, a.3, b) } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t { + let mut a: int8x16x4_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.3 = simd_shuffle!( + a.3, + a.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbl4q(a.0, a.1, a.2, a.3, b); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19430,8 +19421,50 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { + let mut a: uint8x16x4_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.3 = simd_shuffle!( + a.3, + a.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19447,8 +19480,55 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { + let mut a: uint8x16x4_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.3 = simd_shuffle!( + a.3, + a.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = transmute(vqtbl4q( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19464,8 +19544,50 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { } } #[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { + let mut a: poly8x16x4_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.3 = simd_shuffle!( + a.3, + a.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19480,9 +19602,55 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { )) } } +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { + let mut a: poly8x16x4_t = a; + unsafe { + a.0 = simd_shuffle!( + a.0, + a.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.1 = simd_shuffle!( + a.1, + a.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.2 = simd_shuffle!( + a.2, + a.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + a.3 = simd_shuffle!( + a.3, + a.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = transmute(vqtbl4q( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19498,7 +19666,7 @@ fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19514,7 +19682,8 @@ fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19522,53 +19691,178 @@ pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { vqtbx1(a, b, c) } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { - vqtbx1q(a, b, c) +pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbx1(a, b, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) } +pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { + vqtbx1q(a, b, c) } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } +pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbx1q(a, b, c); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { +pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { - unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"] -#[inline(always)] +pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbx1(transmute(a), transmute(b), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = transmute(vqtbx1q(transmute(a), transmute(b), c)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbx1(transmute(a), transmute(b), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { + unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = transmute(vqtbx1q(transmute(a), transmute(b), c)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19584,7 +19878,7 @@ fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t { } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19600,7 +19894,8 @@ fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19608,8 +19903,35 @@ pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t { vqtbx2(a, b.0, b.1, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t { + let mut b: int8x16x2_t = b; + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbx2(a, b.0, b.1, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19617,8 +19939,41 @@ pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t { vqtbx2q(a, b.0, b.1, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t { + let mut b: int8x16x2_t = b; + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbx2q(a, b.0, b.1, c); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19626,8 +19981,35 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { + let mut b: uint8x16x2_t = b; + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19635,8 +20017,42 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { + let mut b: uint8x16x2_t = b; + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19644,8 +20060,35 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { + let mut b: poly8x16x2_t = b; + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19653,8 +20096,41 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { + let mut b: poly8x16x2_t = b; + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19671,7 +20147,7 @@ fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) - } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19693,7 +20169,8 @@ fn vqtbx3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19701,8 +20178,40 @@ pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t { vqtbx3(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t { + let mut b: int8x16x3_t = b; + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbx3(a, b.0, b.1, b.2, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19710,31 +20219,52 @@ pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { vqtbx3q(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { +pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { + let mut b: int8x16x3_t = b; unsafe { - transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )) + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbx3q(a, b.0, b.1, b.2, c); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { +pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { unsafe { - transmute(vqtbx3q( + transmute(vqtbx3( transmute(a), transmute(b.0), transmute(b.1), @@ -19744,29 +20274,50 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { +pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { + let mut b: uint8x16x3_t = b; unsafe { - transmute(vqtbx3( + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbx3( transmute(a), transmute(b.0), transmute(b.1), transmute(b.2), c, - )) + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { +pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbx3q( transmute(a), @@ -19778,13 +20329,172 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -fn vqtbx4( - a: int8x8_t, +pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { + let mut b: uint8x16x3_t = b; + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = transmute(vqtbx3q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vqtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { + let mut b: poly8x16x3_t = b; + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { + unsafe { + transmute(vqtbx3q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { + let mut b: poly8x16x3_t = b; + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = transmute(vqtbx3q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +fn vqtbx4( + a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, @@ -19809,7 +20519,7 @@ fn vqtbx4( } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19839,7 +20549,8 @@ fn vqtbx4q( } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19847,8 +20558,45 @@ pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t { vqtbx4(a, b.0, b.1, b.2, b.3, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t { + let mut b: int8x16x4_t = b; + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.3 = simd_shuffle!( + b.3, + b.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vqtbx4(a, b.0, b.1, b.2, b.3, c); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19856,8 +20604,51 @@ pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { vqtbx4q(a, b.0, b.1, b.2, b.3, c) } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { + let mut b: int8x16x4_t = b; + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.3 = simd_shuffle!( + b.3, + b.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = vqtbx4q(a, b.0, b.1, b.2, b.3, c); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19874,8 +20665,52 @@ pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { + let mut b: uint8x16x4_t = b; + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.3 = simd_shuffle!( + b.3, + b.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = transmute(vqtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19892,8 +20727,58 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { + let mut b: uint8x16x4_t = b; + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.3 = simd_shuffle!( + b.3, + b.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = transmute(vqtbx4q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19910,8 +20795,52 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { } } #[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { + let mut b: poly8x16x4_t = b; + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.3 = simd_shuffle!( + b.3, + b.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = transmute(vqtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19927,25 +20856,74 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { )) } } -#[doc = "Rotate and exclusive OR"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"] -#[inline(always)] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(rax1))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.rax1" - )] - fn _vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; - } - unsafe { _vrax1q_u64(a, b) } -} -#[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"] -#[inline(always)] +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(tbx))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { + let mut b: poly8x16x4_t = b; + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!( + b.0, + b.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.1 = simd_shuffle!( + b.1, + b.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.2 = simd_shuffle!( + b.2, + b.2, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + b.3 = simd_shuffle!( + b.3, + b.3, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = transmute(vqtbx4q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Rotate and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"] +#[inline] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(rax1))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.rax1" + )] + fn _vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; + } + unsafe { _vrax1q_u64(a, b) } +} +#[doc = "Reverse bit order"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -19954,7 +20932,7 @@ pub fn vrbit_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -19963,8 +20941,7 @@ pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -19972,23 +20949,8 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { unsafe { transmute(vrbit_s8(transmute(a))) } } #[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(rbit))] -pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vrbit_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -19996,28 +20958,8 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { unsafe { transmute(vrbitq_s8(transmute(a))) } } #[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(rbit))] -pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vrbitq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] @@ -20025,51 +20967,17 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { unsafe { transmute(vrbit_s8(transmute(a))) } } #[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(rbit))] -pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vrbit_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { unsafe { transmute(vrbitq_s8(transmute(a))) } } -#[doc = "Reverse bit order"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(rbit))] -pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(vrbitq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20085,7 +20993,7 @@ pub fn vrecpe_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20101,7 +21009,7 @@ pub fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20117,7 +21025,7 @@ pub fn vrecped_f64(a: f64) -> f64 { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20133,7 +21041,7 @@ pub fn vrecpes_f32(a: f32) -> f32 { } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(frecpe))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -20150,7 +21058,7 @@ pub fn vrecpeh_f16(a: f16) -> f16 { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20166,7 +21074,7 @@ pub fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20182,7 +21090,7 @@ pub fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20198,7 +21106,7 @@ pub fn vrecpsd_f64(a: f64, b: f64) -> f64 { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20214,7 +21122,7 @@ pub fn vrecpss_f32(a: f32, b: f32) -> f32 { } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(frecps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -20231,7 +21139,7 @@ pub fn vrecpsh_f16(a: f16, b: f16) -> f16 { } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20247,7 +21155,7 @@ pub fn vrecpxd_f64(a: f64) -> f64 { } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20263,7 +21171,7 @@ pub fn vrecpxs_f32(a: f32) -> f32 { } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(frecpx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -20280,1416 +21188,605 @@ pub fn vrecpxh_f16(a: f16) -> f16 { } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { +pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { +pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { +pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { +pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { - let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { +pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { +pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { +pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { +pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { +pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { +pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { +pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { +pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { +pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { +pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { +pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { +pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { +pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { +pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { +pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { +pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { +pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { +pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { +pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { +pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { +pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { +pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { +pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { +pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { +pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { +pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { +pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { +pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { +pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { +pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { +pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { +pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] @@ -21705,7 +21802,7 @@ pub fn vrnd32x_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] @@ -21721,7 +21818,7 @@ pub fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] @@ -21737,7 +21834,7 @@ pub fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] @@ -21749,11 +21846,11 @@ pub fn vrnd32x_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd32x_f64(a: f64) -> f64; } - unsafe { transmute(_vrnd32x_f64(simd_extract!(a, 0))) } + unsafe { transmute(_vrnd32x_f64(vget_lane_f64::<0>(a))) } } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] @@ -21769,7 +21866,7 @@ pub fn vrnd32z_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] @@ -21785,7 +21882,7 @@ pub fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] @@ -21801,7 +21898,7 @@ pub fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] @@ -21813,11 +21910,11 @@ pub fn vrnd32z_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd32z_f64(a: f64) -> f64; } - unsafe { transmute(_vrnd32z_f64(simd_extract!(a, 0))) } + unsafe { transmute(_vrnd32z_f64(vget_lane_f64::<0>(a))) } } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] @@ -21833,7 +21930,7 @@ pub fn vrnd64x_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] @@ -21849,7 +21946,7 @@ pub fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] @@ -21865,7 +21962,7 @@ pub fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] @@ -21877,11 +21974,11 @@ pub fn vrnd64x_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd64x_f64(a: f64) -> f64; } - unsafe { transmute(_vrnd64x_f64(simd_extract!(a, 0))) } + unsafe { transmute(_vrnd64x_f64(vget_lane_f64::<0>(a))) } } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] @@ -21897,7 +21994,7 @@ pub fn vrnd64z_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] @@ -21913,7 +22010,7 @@ pub fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] @@ -21929,7 +22026,7 @@ pub fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] @@ -21941,11 +22038,11 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd64z_f64(a: f64) -> f64; } - unsafe { transmute(_vrnd64z_f64(simd_extract!(a, 0))) } + unsafe { transmute(_vrnd64z_f64(vget_lane_f64::<0>(a))) } } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -21955,7 +22052,7 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -21965,7 +22062,7 @@ pub fn vrndq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] @@ -21974,7 +22071,7 @@ pub fn vrnd_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] @@ -21983,7 +22080,7 @@ pub fn vrndq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] @@ -21992,7 +22089,7 @@ pub fn vrnd_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] @@ -22001,7 +22098,7 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22011,7 +22108,7 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22021,7 +22118,7 @@ pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] @@ -22030,7 +22127,7 @@ pub fn vrnda_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] @@ -22039,7 +22136,7 @@ pub fn vrndaq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] @@ -22048,7 +22145,7 @@ pub fn vrnda_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] @@ -22057,7 +22154,7 @@ pub fn vrndaq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndah_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -22067,7 +22164,7 @@ pub fn vrndah_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -22077,7 +22174,7 @@ pub fn vrndh_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22094,7 +22191,7 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22111,7 +22208,7 @@ pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] @@ -22127,7 +22224,7 @@ pub fn vrndi_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] @@ -22143,7 +22240,7 @@ pub fn vrndiq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] @@ -22159,7 +22256,7 @@ pub fn vrndi_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] @@ -22175,7 +22272,7 @@ pub fn vrndiq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndih_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -22192,7 +22289,7 @@ pub fn vrndih_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22202,7 +22299,7 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22212,7 +22309,7 @@ pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] @@ -22221,7 +22318,7 @@ pub fn vrndm_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] @@ -22230,7 +22327,7 @@ pub fn vrndmq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] @@ -22239,7 +22336,7 @@ pub fn vrndm_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] @@ -22248,7 +22345,7 @@ pub fn vrndmq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -22258,7 +22355,7 @@ pub fn vrndmh_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] @@ -22274,7 +22371,7 @@ pub fn vrndn_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] @@ -22290,7 +22387,7 @@ pub fn vrndnq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -22307,7 +22404,7 @@ pub fn vrndnh_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] @@ -22323,7 +22420,7 @@ pub fn vrndns_f32(a: f32) -> f32 { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22333,7 +22430,7 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22343,7 +22440,7 @@ pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] @@ -22352,7 +22449,7 @@ pub fn vrndp_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] @@ -22361,7 +22458,7 @@ pub fn vrndpq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] @@ -22370,7 +22467,7 @@ pub fn vrndp_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] @@ -22379,7 +22476,7 @@ pub fn vrndpq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndph_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -22389,7 +22486,7 @@ pub fn vrndph_f16(a: f16) -> f16 { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22399,7 +22496,7 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] @@ -22409,7 +22506,7 @@ pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] @@ -22418,7 +22515,7 @@ pub fn vrndx_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] @@ -22427,7 +22524,7 @@ pub fn vrndxq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] @@ -22436,7 +22533,7 @@ pub fn vrndx_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] @@ -22445,7 +22542,7 @@ pub fn vrndxq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -22455,7 +22552,7 @@ pub fn vrndxh_f16(a: f16) -> f16 { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22471,7 +22568,7 @@ pub fn vrshld_s64(a: i64, b: i64) -> i64 { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22487,7 +22584,7 @@ pub fn vrshld_u64(a: u64, b: i64) -> u64 { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshr, N = 2))] #[rustc_legacy_const_generics(1)] @@ -22498,7 +22595,7 @@ pub fn vrshrd_n_s64(a: i64) -> i64 { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshr, N = 2))] #[rustc_legacy_const_generics(1)] @@ -22509,85 +22606,73 @@ pub fn vrshrd_n_u64(a: u64) -> u64 { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vrshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vrshrn_n_s16::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vrshrn_n_s32::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vrshrn_n_s64::(b), [0, 1, 2, 3]) } + vcombine_s32(a, vrshrn_n_s64::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vrshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vrshrn_n_u16::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vrshrn_n_u32::(b)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vrshrn_n_u64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vrshrn_n_u64::(b)) } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22603,7 +22688,7 @@ pub fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22619,7 +22704,7 @@ pub fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22635,7 +22720,7 @@ pub fn vrsqrted_f64(a: f64) -> f64 { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22651,7 +22736,7 @@ pub fn vrsqrtes_f32(a: f32) -> f32 { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(frsqrte))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -22668,7 +22753,7 @@ pub fn vrsqrteh_f16(a: f16) -> f16 { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22684,7 +22769,7 @@ pub fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22700,7 +22785,7 @@ pub fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22716,7 +22801,7 @@ pub fn vrsqrtsd_f64(a: f64, b: f64) -> f64 { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -22732,7 +22817,7 @@ pub fn vrsqrtss_f32(a: f32, b: f32) -> f32 { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(frsqrts))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] @@ -22749,7 +22834,7 @@ pub fn vrsqrtsh_f16(a: f16, b: f16) -> f16 { } #[doc = "Signed rounding shift right and accumulate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshr, N = 2))] #[rustc_legacy_const_generics(2)] @@ -22761,7 +22846,7 @@ pub fn vrsrad_n_s64(a: i64, b: i64) -> i64 { } #[doc = "Unsigned rounding shift right and accumulate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshr, N = 2))] #[rustc_legacy_const_generics(2)] @@ -22773,139 +22858,127 @@ pub fn vrsrad_n_u64(a: u64, b: u64) -> u64 { } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let x: int8x8_t = vrsubhn_s16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_s8(a, vrsubhn_s16(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let x: int16x4_t = vrsubhn_s32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vrsubhn_s32(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let x: int32x2_t = vrsubhn_s64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_s32(a, vrsubhn_s64(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let x: uint8x8_t = vrsubhn_u16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_u8(a, vrsubhn_u16(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let x: uint16x4_t = vrsubhn_u32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vrsubhn_u32(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "little")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let x: uint32x2_t = vrsubhn_u64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_u32(a, vrsubhn_u64(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let x: int8x8_t = vrsubhn_s16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_s8(a, vrsubhn_s16(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let x: int16x4_t = vrsubhn_s32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vrsubhn_s32(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let x: int32x2_t = vrsubhn_s64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_s32(a, vrsubhn_s64(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let x: uint8x8_t = vrsubhn_u16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } + vcombine_u8(a, vrsubhn_u16(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let x: uint16x4_t = vrsubhn_u32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vrsubhn_u32(b, c)) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_endian = "big")] #[cfg_attr(test, assert_instr(rsubhn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let x: uint32x2_t = vrsubhn_u64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } + vcombine_u32(a, vrsubhn_u64(b, c)) } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -22921,7 +22994,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -22937,7 +23010,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -22953,7 +23026,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -22969,7 +23042,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"] -#[inline(always)] +#[inline] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] @@ -22985,7 +23058,7 @@ pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -22996,7 +23069,8 @@ pub fn vset_lane_f64(a: f64, b: float64x1_t) -> float64x1_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -23005,9 +23079,26 @@ pub fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); unsafe { simd_insert!(b, LANE as u32, a) } } +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(nop, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "SHA512 hash update part 2"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512h2))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] @@ -23021,9 +23112,33 @@ pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t } unsafe { _vsha512h2q_u64(a, b, c) } } +#[doc = "SHA512 hash update part 2"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512h2))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512h2" + )] + fn _vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; + } + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: uint64x2_t = _vsha512h2q_u64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "SHA512 hash update part 1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512h))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] @@ -23037,25 +23152,89 @@ pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t } unsafe { _vsha512hq_u64(a, b, c) } } +#[doc = "SHA512 hash update part 1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512h))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512h" + )] + fn _vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; + } + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: uint64x2_t = _vsha512hq_u64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "SHA512 schedule update 0"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512su0))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512su0" + )] + fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; + } + unsafe { _vsha512su0q_u64(a, b) } +} #[doc = "SHA512 schedule update 0"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512su0))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512su0" + )] + fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; + } + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = _vsha512su0q_u64(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "SHA512 schedule update 1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512su1))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.crypto.sha512su0" + link_name = "llvm.aarch64.crypto.sha512su1" )] - fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; + fn _vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - unsafe { _vsha512su0q_u64(a, b) } + unsafe { _vsha512su1q_u64(a, b, c) } } #[doc = "SHA512 schedule update 1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512su1))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] @@ -23067,11 +23246,17 @@ pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_ )] fn _vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - unsafe { _vsha512su1q_u64(a, b, c) } + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]); + let ret_val: uint64x2_t = _vsha512su1q_u64(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23080,7 +23265,7 @@ pub fn vshld_s64(a: i64, b: i64) -> i64 { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ushl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23089,169 +23274,145 @@ pub fn vshld_u64(a: u64, b: i64) -> u64 { } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_s8(a: int8x16_t) -> int16x8_t { static_assert!(N >= 0 && N <= 8); - unsafe { - let b: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vshll_n_s8::(b) - } + let b = vget_high_s8(a); + vshll_n_s8::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_s16(a: int16x8_t) -> int32x4_t { static_assert!(N >= 0 && N <= 16); - unsafe { - let b: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vshll_n_s16::(b) - } + let b = vget_high_s16(a); + vshll_n_s16::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_s32(a: int32x4_t) -> int64x2_t { static_assert!(N >= 0 && N <= 32); - unsafe { - let b: int32x2_t = simd_shuffle!(a, a, [2, 3]); - vshll_n_s32::(b) - } + let b = vget_high_s32(a); + vshll_n_s32::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_u8(a: uint8x16_t) -> uint16x8_t { static_assert!(N >= 0 && N <= 8); - unsafe { - let b: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vshll_n_u8::(b) - } + let b: uint8x8_t = vget_high_u8(a); + vshll_n_u8::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_u16(a: uint16x8_t) -> uint32x4_t { static_assert!(N >= 0 && N <= 16); - unsafe { - let b: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vshll_n_u16::(b) - } + let b: uint16x4_t = vget_high_u16(a); + vshll_n_u16::(b) } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshll_high_n_u32(a: uint32x4_t) -> uint64x2_t { static_assert!(N >= 0 && N <= 32); - unsafe { - let b: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - vshll_n_u32::(b) - } + let b: uint32x2_t = vget_high_u32(a); + vshll_n_u32::(b) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_s8(a, vshrn_n_s16::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_s16(a, vshrn_n_s32::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vshrn_n_s64::(b), [0, 1, 2, 3]) } + vcombine_s32(a, vshrn_n_s64::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe { - simd_shuffle!( - a, - vshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) - } + vcombine_u8(a, vshrn_n_u16::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe { simd_shuffle!(a, vshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } + vcombine_u16(a, vshrn_n_u32::(b)) } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe { simd_shuffle!(a, vshrn_n_u64::(b), [0, 1, 2, 3]) } + vcombine_u32(a, vshrn_n_u64::(b)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23269,7 +23430,7 @@ pub fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23287,7 +23448,7 @@ pub fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23305,7 +23466,7 @@ pub fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23323,7 +23484,7 @@ pub fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23341,7 +23502,7 @@ pub fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23359,7 +23520,7 @@ pub fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23377,7 +23538,7 @@ pub fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23395,7 +23556,7 @@ pub fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23406,7 +23567,7 @@ pub fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23417,7 +23578,7 @@ pub fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23428,7 +23589,7 @@ pub fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23439,7 +23600,7 @@ pub fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23450,7 +23611,7 @@ pub fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23461,7 +23622,7 @@ pub fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23472,7 +23633,7 @@ pub fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23483,7 +23644,7 @@ pub fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23494,7 +23655,7 @@ pub fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23505,7 +23666,7 @@ pub fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23516,7 +23677,7 @@ pub fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23527,7 +23688,7 @@ pub fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23538,7 +23699,7 @@ pub fn vsli_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23549,7 +23710,7 @@ pub fn vsliq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { } #[doc = "Shift left and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] @@ -23560,7 +23721,7 @@ pub fn vslid_n_s64(a: i64, b: i64) -> i64 { } #[doc = "Shift left and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] @@ -23571,7 +23732,8 @@ pub fn vslid_n_u64(a: u64, b: u64) -> u64 { } #[doc = "SM3PARTW1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3partw1))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -23585,9 +23747,33 @@ pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_ } unsafe { _vsm3partw1q_u32(a, b, c) } } +#[doc = "SM3PARTW1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3partw1))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3partw1" + )] + fn _vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3partw1q_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3PARTW2"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3partw2))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -23601,9 +23787,33 @@ pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_ } unsafe { _vsm3partw2q_u32(a, b, c) } } +#[doc = "SM3PARTW2"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3partw2))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3partw2" + )] + fn _vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3partw2q_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3SS1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3ss1))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -23617,9 +23827,33 @@ pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } unsafe { _vsm3ss1q_u32(a, b, c) } } +#[doc = "SM3SS1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3ss1))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3ss1" + )] + fn _vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3ss1q_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3TT1A"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))] #[rustc_legacy_const_generics(3)] @@ -23635,9 +23869,35 @@ pub fn vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_ } unsafe { _vsm3tt1aq_u32(a, b, c, IMM2 as i64) } } +#[doc = "SM3TT1A"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(IMM2, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3tt1a" + )] + fn _vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3tt1aq_u32(a, b, c, IMM2 as i64); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3TT1B"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))] #[rustc_legacy_const_generics(3)] @@ -23653,9 +23913,35 @@ pub fn vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_ } unsafe { _vsm3tt1bq_u32(a, b, c, IMM2 as i64) } } +#[doc = "SM3TT1B"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(IMM2, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3tt1b" + )] + fn _vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3tt1bq_u32(a, b, c, IMM2 as i64); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3TT2A"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))] #[rustc_legacy_const_generics(3)] @@ -23671,9 +23957,35 @@ pub fn vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_ } unsafe { _vsm3tt2aq_u32(a, b, c, IMM2 as i64) } } +#[doc = "SM3TT2A"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(IMM2, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3tt2a" + )] + fn _vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3tt2aq_u32(a, b, c, IMM2 as i64); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM3TT2B"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))] #[rustc_legacy_const_generics(3)] @@ -23689,9 +24001,35 @@ pub fn vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_ } unsafe { _vsm3tt2bq_u32(a, b, c, IMM2 as i64) } } +#[doc = "SM3TT2B"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(IMM2, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3tt2b" + )] + fn _vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm3tt2bq_u32(a, b, c, IMM2 as i64); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM4 key"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm4ekey))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -23705,9 +24043,32 @@ pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } unsafe { _vsm4ekeyq_u32(a, b) } } +#[doc = "SM4 key"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm4ekey))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm4ekey" + )] + fn _vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm4ekeyq_u32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SM4 encode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm4e))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] @@ -23721,9 +24082,31 @@ pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } unsafe { _vsm4eq_u32(a, b) } } +#[doc = "SM4 encode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm4e))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm4e" + )] + fn _vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsm4eq_u32(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -23739,7 +24122,7 @@ pub fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -23755,7 +24138,7 @@ pub fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -23771,7 +24154,7 @@ pub fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -23787,7 +24170,7 @@ pub fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -23803,7 +24186,7 @@ pub fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -23819,7 +24202,7 @@ pub fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -23835,7 +24218,7 @@ pub fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] @@ -23851,25 +24234,25 @@ pub fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsqaddb_u8(a: u8, b: i8) -> u8 { - unsafe { simd_extract!(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)), 0) } + vget_lane_u8::<0>(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b))) } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsqaddh_u16(a: u16, b: i16) -> u16 { - unsafe { simd_extract!(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)), 0) } + vget_lane_u16::<0>(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b))) } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23885,7 +24268,7 @@ pub fn vsqaddd_u64(a: u64, b: i64) -> u64 { } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23901,7 +24284,7 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -23911,7 +24294,7 @@ pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] @@ -23921,7 +24304,7 @@ pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23930,7 +24313,7 @@ pub fn vsqrt_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23939,7 +24322,7 @@ pub fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23948,7 +24331,7 @@ pub fn vsqrt_f64(a: float64x1_t) -> float64x1_t { } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23957,7 +24340,7 @@ pub fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrth_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -23967,7 +24350,7 @@ pub fn vsqrth_f16(a: f16) -> f16 { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23978,7 +24361,7 @@ pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -23989,7 +24372,7 @@ pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24000,7 +24383,7 @@ pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24011,7 +24394,7 @@ pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24022,7 +24405,7 @@ pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24033,7 +24416,7 @@ pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24044,7 +24427,7 @@ pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24055,7 +24438,7 @@ pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24066,7 +24449,7 @@ pub fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24077,7 +24460,7 @@ pub fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24088,7 +24471,7 @@ pub fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24099,7 +24482,7 @@ pub fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24110,7 +24493,7 @@ pub fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24121,7 +24504,7 @@ pub fn vsriq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24132,7 +24515,7 @@ pub fn vsri_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24143,7 +24526,7 @@ pub fn vsriq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24154,7 +24537,7 @@ pub fn vsri_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24165,7 +24548,7 @@ pub fn vsriq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24176,7 +24559,7 @@ pub fn vsri_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24187,7 +24570,7 @@ pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24198,7 +24581,7 @@ pub fn vsri_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] @@ -24209,7 +24592,7 @@ pub fn vsriq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { } #[doc = "Shift right and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] @@ -24220,7 +24603,7 @@ pub fn vsrid_n_s64(a: i64, b: i64) -> i64 { } #[doc = "Shift right and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] @@ -24233,7 +24616,7 @@ pub fn vsrid_n_u64(a: u64, b: u64) -> u64 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24246,7 +24629,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24259,7 +24642,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24271,7 +24654,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24283,7 +24666,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24295,7 +24678,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24307,7 +24690,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24319,7 +24702,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24331,7 +24714,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24343,7 +24726,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24355,7 +24738,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24367,7 +24750,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24379,7 +24762,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24391,7 +24774,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24403,7 +24786,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24415,7 +24798,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24427,7 +24810,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24439,7 +24822,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24451,7 +24834,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24463,7 +24846,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24475,7 +24858,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24487,7 +24870,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24499,7 +24882,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24511,7 +24894,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24523,7 +24906,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24535,7 +24918,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24547,7 +24930,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24559,7 +24942,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] @@ -24571,7 +24954,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24589,7 +24972,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24607,7 +24990,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24625,7 +25008,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24643,7 +25026,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24667,7 +25050,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24691,7 +25074,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24704,7 +25087,7 @@ pub unsafe fn vst1_lane_f64(a: *mut f64, b: float64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24717,7 +25100,7 @@ pub unsafe fn vst1q_lane_f64(a: *mut f64, b: float64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(stp))] @@ -24728,7 +25111,7 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24748,7 +25131,7 @@ pub unsafe fn vst2_lane_f64(a: *mut f64, b: float64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24768,7 +25151,7 @@ pub unsafe fn vst2_lane_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24781,7 +25164,7 @@ pub unsafe fn vst2_lane_p64(a: *mut p64, b: poly64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24794,7 +25177,7 @@ pub unsafe fn vst2_lane_u64(a: *mut u64, b: uint64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] @@ -24805,7 +25188,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] @@ -24816,7 +25199,7 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24836,7 +25219,7 @@ pub unsafe fn vst2q_lane_f64(a: *mut f64, b: float64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24856,7 +25239,7 @@ pub unsafe fn vst2q_lane_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24876,7 +25259,7 @@ pub unsafe fn vst2q_lane_s64(a: *mut i64, b: int64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24889,7 +25272,7 @@ pub unsafe fn vst2q_lane_p64(a: *mut p64, b: poly64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24902,7 +25285,7 @@ pub unsafe fn vst2q_lane_u8(a: *mut u8, b: uint8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24915,7 +25298,7 @@ pub unsafe fn vst2q_lane_u64(a: *mut u64, b: uint64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24928,7 +25311,7 @@ pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24939,7 +25322,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] @@ -24950,7 +25333,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -24961,7 +25344,7 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -24981,7 +25364,7 @@ pub unsafe fn vst3_lane_f64(a: *mut f64, b: float64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25001,7 +25384,7 @@ pub unsafe fn vst3_lane_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -25014,7 +25397,7 @@ pub unsafe fn vst3_lane_p64(a: *mut p64, b: poly64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -25027,7 +25410,7 @@ pub unsafe fn vst3_lane_u64(a: *mut u64, b: uint64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] @@ -25038,7 +25421,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] @@ -25049,7 +25432,7 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25069,7 +25452,7 @@ pub unsafe fn vst3q_lane_f64(a: *mut f64, b: float64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25089,7 +25472,7 @@ pub unsafe fn vst3q_lane_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25109,7 +25492,7 @@ pub unsafe fn vst3q_lane_s64(a: *mut i64, b: int64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -25122,7 +25505,7 @@ pub unsafe fn vst3q_lane_p64(a: *mut p64, b: poly64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -25135,7 +25518,7 @@ pub unsafe fn vst3q_lane_u8(a: *mut u8, b: uint8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -25148,7 +25531,7 @@ pub unsafe fn vst3q_lane_u64(a: *mut u64, b: uint64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -25161,7 +25544,7 @@ pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3))] @@ -25172,7 +25555,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] @@ -25183,7 +25566,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] @@ -25194,7 +25577,7 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25221,7 +25604,7 @@ pub unsafe fn vst4_lane_f64(a: *mut f64, b: float64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25248,7 +25631,7 @@ pub unsafe fn vst4_lane_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -25261,7 +25644,7 @@ pub unsafe fn vst4_lane_p64(a: *mut p64, b: poly64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -25274,7 +25657,7 @@ pub unsafe fn vst4_lane_u64(a: *mut u64, b: uint64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] @@ -25285,7 +25668,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] @@ -25296,7 +25679,7 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25323,7 +25706,7 @@ pub unsafe fn vst4q_lane_f64(a: *mut f64, b: float64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25350,7 +25733,7 @@ pub unsafe fn vst4q_lane_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -25377,7 +25760,7 @@ pub unsafe fn vst4q_lane_s64(a: *mut i64, b: int64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -25390,7 +25773,7 @@ pub unsafe fn vst4q_lane_p64(a: *mut p64, b: poly64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -25403,7 +25786,7 @@ pub unsafe fn vst4q_lane_u8(a: *mut u8, b: uint8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -25416,7 +25799,7 @@ pub unsafe fn vst4q_lane_u64(a: *mut u64, b: uint64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -25429,7 +25812,7 @@ pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4))] @@ -25440,7 +25823,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] @@ -25449,111 +25832,123 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { +pub unsafe fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { +pub unsafe fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { +pub unsafe fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { +pub unsafe fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { +pub unsafe fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { +pub unsafe fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { +pub unsafe fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { static_assert!(LANE == 0); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; - unsafe { - let lane: i64 = simd_extract!(val, LANE as u32); - (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) - } + let lane: i64 = vget_lane_s64::(val); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"] -#[inline(always)] +#[doc = "## Safety"] +#[doc = " * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."] +#[inline] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { +pub unsafe fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { static_assert_uimm_bits!(LANE, 1); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; - unsafe { - let lane: i64 = simd_extract!(val, LANE as u32); - (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) - } + let lane: i64 = vgetq_lane_s64::(val); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fsub))] @@ -25562,7 +25957,7 @@ pub fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fsub))] @@ -25571,7 +25966,7 @@ pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sub))] @@ -25580,7 +25975,7 @@ pub fn vsubd_s64(a: i64, b: i64) -> i64 { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sub))] @@ -25589,7 +25984,7 @@ pub fn vsubd_u64(a: u64, b: u64) -> u64 { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubh_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] @@ -25599,169 +25994,145 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 { } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))] pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { unsafe { - let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: int16x8_t = simd_cast(c); - let e: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: int16x8_t = simd_cast(e); - simd_sub(d, f) + let c: int16x8_t = simd_cast(vget_high_s8(a)); + let d: int16x8_t = simd_cast(vget_high_s8(b)); + simd_sub(c, d) } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))] pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { unsafe { - let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: int32x4_t = simd_cast(c); - let e: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let f: int32x4_t = simd_cast(e); - simd_sub(d, f) + let c: int32x4_t = simd_cast(vget_high_s16(a)); + let d: int32x4_t = simd_cast(vget_high_s16(b)); + simd_sub(c, d) } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))] pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { unsafe { - let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: int64x2_t = simd_cast(c); - let e: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let f: int64x2_t = simd_cast(e); - simd_sub(d, f) + let c: int64x2_t = simd_cast(vget_high_s32(a)); + let d: int64x2_t = simd_cast(vget_high_s32(b)); + simd_sub(c, d) } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))] pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { unsafe { - let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: uint16x8_t = simd_cast(c); - let e: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: uint16x8_t = simd_cast(e); - simd_sub(d, f) + let c: uint16x8_t = simd_cast(vget_high_u8(a)); + let d: uint16x8_t = simd_cast(vget_high_u8(b)); + simd_sub(c, d) } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))] pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { unsafe { - let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: uint32x4_t = simd_cast(c); - let e: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let f: uint32x4_t = simd_cast(e); - simd_sub(d, f) + let c: uint32x4_t = simd_cast(vget_high_u16(a)); + let d: uint32x4_t = simd_cast(vget_high_u16(b)); + simd_sub(c, d) } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubl2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))] pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { unsafe { - let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: uint64x2_t = simd_cast(c); - let e: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let f: uint64x2_t = simd_cast(e); - simd_sub(d, f) + let c: uint64x2_t = simd_cast(vget_high_u32(a)); + let d: uint64x2_t = simd_cast(vget_high_u32(b)); + simd_sub(c, d) } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))] pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { - unsafe { - let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_s8(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))] pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { - unsafe { - let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_s16(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ssubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))] pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { - unsafe { - let c: int32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_s32(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))] pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { - unsafe { - let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_u8(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))] pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { - unsafe { - let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_u16(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(usubw2))] +#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))] pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { - unsafe { - let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_sub(a, simd_cast(c)) - } + let c = vget_high_u32(b); + unsafe { simd_sub(a, simd_cast(c)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25774,7 +26145,7 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25783,7 +26154,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25792,34 +26163,34 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { - unsafe { vqtbl1(transmute(vcombine_s8(a.0, a.1)), transmute(b)) } + vqtbl1_s8(vcombine_s8(a.0, a.1), vreinterpret_u8_s8(b)) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)) } + vqtbl1_u8(vcombine_u8(a.0, a.1), b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)) } + vqtbl1_p8(vcombine_p8(a.0, a.1), b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25828,11 +26199,11 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { vcombine_s8(a.0, a.1), vcombine_s8(a.2, unsafe { crate::mem::zeroed() }), ); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) } + vqtbl2_s8(x, vreinterpret_u8_s8(b)) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25841,11 +26212,11 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { vcombine_u8(a.0, a.1), vcombine_u8(a.2, unsafe { crate::mem::zeroed() }), ); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } + vqtbl2_u8(x, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25854,41 +26225,41 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { vcombine_p8(a.0, a.1), vcombine_p8(a.2, unsafe { crate::mem::zeroed() }), ); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } + vqtbl2_p8(x, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { let x = int8x16x2_t(vcombine_s8(a.0, a.1), vcombine_s8(a.2, a.3)); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) } + vqtbl2_s8(x, vreinterpret_u8_s8(b)) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3)); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } + vqtbl2_u8(x, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); - unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } + vqtbl2_p8(x, b) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25896,18 +26267,18 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { unsafe { simd_select( simd_lt::(c, transmute(i8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_s8(b, crate::mem::zeroed())), - transmute(c), - )), + vqtbx1_s8( + a, + vcombine_s8(b, crate::mem::zeroed()), + vreinterpret_u8_s8(c), + ), a, ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25915,18 +26286,14 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { unsafe { simd_select( simd_lt::(c, transmute(u8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_u8(b, crate::mem::zeroed())), - c, - )), + vqtbx1_u8(a, vcombine_u8(b, crate::mem::zeroed()), c), a, ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25934,45 +26301,59 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { unsafe { simd_select( simd_lt::(c, transmute(u8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_p8(b, crate::mem::zeroed())), - c, - )), + vqtbx1_p8(a, vcombine_p8(b, crate::mem::zeroed()), c), a, ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { - unsafe { vqtbx1(transmute(a), transmute(vcombine_s8(b.0, b.1)), transmute(c)) } + unsafe { + simd_select( + simd_lt::(c, transmute(i8x8::splat(16))), + vqtbx1_s8(a, vcombine_s8(b.0, b.1), vreinterpret_u8_s8(c)), + a, + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)) } + unsafe { + simd_select( + simd_lt::(c, transmute(u8x8::splat(16))), + vqtbx1_u8(a, vcombine_u8(b.0, b.1), c), + a, + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)) } + unsafe { + simd_select( + simd_lt::(c, transmute(u8x8::splat(16))), + vqtbx1_p8(a, vcombine_p8(b.0, b.1), c), + a, + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25982,21 +26363,16 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { vcombine_s8(b.2, unsafe { crate::mem::zeroed() }), ); unsafe { - transmute(simd_select( - simd_lt::(transmute(c), transmute(i8x8::splat(24))), - transmute(vqtbx2( - transmute(a), - transmute(x.0), - transmute(x.1), - transmute(c), - )), + simd_select( + simd_lt::(c, transmute(i8x8::splat(24))), + vqtbx2_s8(a, x, vreinterpret_u8_s8(c)), a, - )) + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26006,16 +26382,16 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { vcombine_u8(b.2, unsafe { crate::mem::zeroed() }), ); unsafe { - transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), + simd_select( + simd_lt::(c, transmute(u8x8::splat(24))), + vqtbx2_u8(a, x, c), a, - )) + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26025,168 +26401,416 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { vcombine_p8(b.2, unsafe { crate::mem::zeroed() }), ); unsafe { - transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), + simd_select( + simd_lt::(c, transmute(u8x8::splat(24))), + vqtbx2_p8(a, x, c), a, - )) + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { + let x = int8x16x2_t(vcombine_s8(b.0, b.1), vcombine_s8(b.2, b.3)); unsafe { - vqtbx2( - transmute(a), - transmute(vcombine_s8(b.0, b.1)), - transmute(vcombine_s8(b.2, b.3)), - transmute(c), + simd_select( + simd_lt::(c, transmute(i8x8::splat(32))), + vqtbx2_s8(a, x, vreinterpret_u8_s8(c)), + a, ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { + let x = uint8x16x2_t(vcombine_u8(b.0, b.1), vcombine_u8(b.2, b.3)); unsafe { - transmute(vqtbx2( - transmute(a), - transmute(vcombine_u8(b.0, b.1)), - transmute(vcombine_u8(b.2, b.3)), - c, - )) + simd_select( + simd_lt::(c, transmute(u8x8::splat(32))), + vqtbx2_u8(a, x, c), + a, + ) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { + let x = poly8x16x2_t(vcombine_p8(b.0, b.1), vcombine_p8(b.2, b.3)); unsafe { - transmute(vqtbx2( - transmute(a), - transmute(vcombine_p8(b.0, b.1)), - transmute(vcombine_p8(b.2, b.3)), - c, - )) + simd_select( + simd_lt::(c, transmute(u8x8::splat(32))), + vqtbx2_p8(a, x, c), + a, + ) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -26197,47 +26821,167 @@ pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -26248,47 +26992,167 @@ pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -26299,130 +27163,450 @@ pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn1) +)] +pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -26433,98 +27617,338 @@ pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { - simd_shuffle!( + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -26535,26 +27959,98 @@ pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(trn2) +)] +pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26567,7 +28063,7 @@ pub fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26580,7 +28076,7 @@ pub fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26593,7 +28089,7 @@ pub fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26606,7 +28102,7 @@ pub fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26619,7 +28115,7 @@ pub fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26632,7 +28128,7 @@ pub fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Compare bitwise test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26641,7 +28137,7 @@ pub fn vtstd_s64(a: i64, b: i64) -> u64 { } #[doc = "Compare bitwise test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26650,7 +28146,7 @@ pub fn vtstd_u64(a: u64, b: u64) -> u64 { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -26666,7 +28162,7 @@ pub fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -26682,7 +28178,7 @@ pub fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -26698,7 +28194,7 @@ pub fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -26714,7 +28210,7 @@ pub fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -26730,7 +28226,7 @@ pub fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -26746,7 +28242,7 @@ pub fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -26762,7 +28258,7 @@ pub fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t { } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] @@ -26778,25 +28274,25 @@ pub fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t { } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vuqaddb_s8(a: i8, b: u8) -> i8 { - unsafe { simd_extract!(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)), 0) } + vget_lane_s8::<0>(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b))) } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vuqaddh_s16(a: i16, b: u16) -> i16 { - unsafe { simd_extract!(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)), 0) } + vget_lane_s16::<0>(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b))) } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26812,7 +28308,7 @@ pub fn vuqaddd_s64(a: i64, b: u64) -> i64 { } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26828,111 +28324,359 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 { } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -26943,47 +28687,167 @@ pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } +} +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -26994,47 +28858,167 @@ pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -27045,130 +29029,450 @@ pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp1) +)] +pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -27179,47 +29483,167 @@ pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -27230,47 +29654,167 @@ pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -27281,26 +29825,98 @@ pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(uzp2) +)] +pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} #[doc = "Exclusive OR and rotate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vxarq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(xar, IMM6 = 0))] #[rustc_legacy_const_generics(2)] @@ -27318,135 +29934,437 @@ pub fn vxarq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { - simd_shuffle!( + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -27457,65 +30375,229 @@ pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -27526,94 +30608,326 @@ pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip1) +)] +pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,fp16")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } +} +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_shuffle!(a, b, [1, 3]) } +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { + let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe { simd_shuffle!( @@ -27624,65 +30938,229 @@ pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!( @@ -27693,65 +31171,229 @@ pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe { simd_shuffle!( @@ -27762,29 +31404,123 @@ pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { unsafe { simd_shuffle!(a, b, [1, 3]) } } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr( + all(test, not(target_env = "msvc"), target_endian = "little"), + assert_instr(zip2) +)] +pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} diff --git a/stdarch/crates/core_arch/src/aarch64/neon/mod.rs b/stdarch/crates/core_arch/src/aarch64/neon/mod.rs index 2fbd2255aa0fd..c66702814cfb2 100644 --- a/stdarch/crates/core_arch/src/aarch64/neon/mod.rs +++ b/stdarch/crates/core_arch/src/aarch64/neon/mod.rs @@ -12,7 +12,6 @@ pub use self::generated::*; use crate::{ core_arch::{arm_shared::*, simd::*}, - hint::unreachable_unchecked, intrinsics::{simd::*, *}, mem::transmute, }; @@ -94,117 +93,6 @@ macro_rules! shift_right_and_insert { pub(crate) use shift_right_and_insert; -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_lane_s64(_a: int64x1_t, b: int64x1_t) -> int64x1_t { - static_assert!(N1 == 0); - static_assert!(N2 == 0); - b -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_lane_u64(_a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - static_assert!(N1 == 0); - static_assert!(N2 == 0); - b -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_lane_p64(_a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { - static_assert!(N1 == 0); - static_assert!(N2 == 0); - b -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_lane_f64( - _a: float64x1_t, - b: float64x1_t, -) -> float64x1_t { - static_assert!(N1 == 0); - static_assert!(N2 == 0); - b -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_laneq_s64( - _a: int64x1_t, - b: int64x2_t, -) -> int64x1_t { - static_assert!(LANE1 == 0); - static_assert_uimm_bits!(LANE2, 1); - unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_laneq_u64( - _a: uint64x1_t, - b: uint64x2_t, -) -> uint64x1_t { - static_assert!(LANE1 == 0); - static_assert_uimm_bits!(LANE2, 1); - unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_laneq_p64( - _a: poly64x1_t, - b: poly64x2_t, -) -> poly64x1_t { - static_assert!(LANE1 == 0); - static_assert_uimm_bits!(LANE2, 1); - unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcopy_laneq_f64( - _a: float64x1_t, - b: float64x2_t, -) -> float64x1_t { - static_assert!(LANE1 == 0); - static_assert_uimm_bits!(LANE2, 1); - unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } -} - /// Load multiple single-element structures to one, two, three, or four registers #[inline] #[target_feature(enable = "neon")] @@ -443,42 +331,6 @@ pub fn vmovq_n_f64(value: f64) -> float64x2_t { vdupq_n_f64(value) } -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vget_high_f64(a: float64x2_t) -> float64x1_t { - unsafe { float64x1_t([simd_extract!(a, 1)]) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ext))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { - unsafe { transmute(u64x1::new(simd_extract!(a, 1))) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vget_low_f64(a: float64x2_t) -> float64x1_t { - unsafe { float64x1_t([simd_extract!(a, 0)]) } -} - -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { - unsafe { transmute(u64x1::new(simd_extract!(a, 0))) } -} - /// Duplicate vector element to vector or scalar #[inline] #[target_feature(enable = "neon")] @@ -493,29 +345,6 @@ pub fn vget_lane_f64(v: float64x1_t) -> f64 { unsafe { simd_extract!(v, IMM5 as u32) } } -/// Duplicate vector element to vector or scalar -#[inline] -#[target_feature(enable = "neon")] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, IMM5 = 0) -)] -pub fn vgetq_lane_f64(v: float64x2_t) -> f64 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } -} - -/// Vector combine -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vcombine_f64(low: float64x1_t, high: float64x1_t) -> float64x2_t { - unsafe { simd_shuffle!(low, high, [0, 1]) } -} - /// Shift left #[inline] #[target_feature(enable = "neon")] @@ -781,38 +610,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vget_high_f64() { - let a = f64x2::new(1.0, 2.0); - let e = f64x1::new(2.0); - let r = f64x1::from(vget_high_f64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_p64() { - let a = u64x2::new(1, 2); - let e = u64x1::new(2); - let r = u64x1::from(vget_high_p64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_f64() { - let a = f64x2::new(1.0, 2.0); - let e = f64x1::new(1.0); - let r = f64x1::from(vget_low_f64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_p64() { - let a = u64x2::new(1, 2); - let e = u64x1::new(1); - let r = u64x1::from(vget_low_p64(a.into())); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] fn test_vget_lane_f64() { let v = f64x1::new(1.0); @@ -820,15 +617,6 @@ mod tests { assert_eq!(r, 1.0); } - #[simd_test(enable = "neon")] - fn test_vgetq_lane_f64() { - let v = f64x2::new(0.0, 1.0); - let r = vgetq_lane_f64::<1>(v.into()); - assert_eq!(r, 1.0); - let r = vgetq_lane_f64::<0>(v.into()); - assert_eq!(r, 0.0); - } - #[simd_test(enable = "neon")] fn test_vcopy_lane_s64() { let a = i64x1::new(1); @@ -865,42 +653,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vcopy_laneq_s64() { - let a = i64x1::new(1); - let b = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r = i64x1::from(vcopy_laneq_s64::<0, 1>(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vcopy_laneq_u64() { - let a = u64x1::new(1); - let b = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r = u64x1::from(vcopy_laneq_u64::<0, 1>(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vcopy_laneq_p64() { - let a = u64x1::new(1); - let b = u64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r = u64x1::from(vcopy_laneq_p64::<0, 1>(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vcopy_laneq_f64() { - let a = f64x1::from_array([1.]); - let b = f64x2::from_array([0., 0.5]); - let e = f64x1::from_array([0.5]); - let r = f64x1::from(vcopy_laneq_f64::<0, 1>(a.into(), b.into())); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] fn test_vbsl_f64() { let a = u64x1::new(0x8000000000000000); @@ -1022,8 +774,12 @@ mod tests { ($elem_ty:ty, $len:expr, $vec_ty:ty, $store:expr, $load:expr) => { let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); let a: $vec_ty = transmute(vals); - let mut tmp = [0 as $elem_ty; $len]; + let mut tmp = core::mem::MaybeUninit::<[$elem_ty; $len]>::uninit(); $store(tmp.as_mut_ptr().cast(), a); + + // With Miri this will check that all elements were initialized. + let tmp = tmp.assume_init(); + let r: $vec_ty = $load(tmp.as_ptr().cast()); let out: [$elem_ty; $len] = transmute(r); assert_eq!(out, vals); @@ -1033,6 +789,7 @@ mod tests { macro_rules! wide_store_load_roundtrip_fp16 { ($( $name:ident $args:tt);* $(;)?) => { $( + #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics #[simd_test(enable = "neon,fp16")] #[cfg(not(target_arch = "arm64ec"))] unsafe fn $name() { @@ -1051,13 +808,13 @@ mod tests { test_vld1q_f16_x3(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3); test_vld1q_f16_x4(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4); - test_vld2_f16_x2(f16, 8, float16x4x2_t, vst2_f16, vld2_f16); - test_vld2_f16_x3(f16, 12, float16x4x3_t, vst3_f16, vld3_f16); - test_vld2_f16_x4(f16, 16, float16x4x4_t, vst4_f16, vld4_f16); + test_vld2_f16(f16, 8, float16x4x2_t, vst2_f16, vld2_f16); + test_vld3_f16(f16, 12, float16x4x3_t, vst3_f16, vld3_f16); + test_vld4_f16(f16, 16, float16x4x4_t, vst4_f16, vld4_f16); - test_vld2q_f16_x2(f16, 16, float16x8x2_t, vst2q_f16, vld2q_f16); - test_vld3q_f16_x3(f16, 24, float16x8x3_t, vst3q_f16, vld3q_f16); - test_vld4q_f16_x4(f16, 32, float16x8x4_t, vst4q_f16, vld4q_f16); + test_vld2q_f16(f16, 16, float16x8x2_t, vst2q_f16, vld2q_f16); + test_vld3q_f16(f16, 24, float16x8x3_t, vst3q_f16, vld3q_f16); + test_vld4q_f16(f16, 32, float16x8x4_t, vst4q_f16, vld4q_f16); } macro_rules! wide_store_load_roundtrip_aes { @@ -1191,101 +948,149 @@ mod tests { } wide_store_load_roundtrip_neon! { - test_vld2_f32_x2(f32, 4, float32x2x2_t, vst2_f32, vld2_f32); - test_vld2_f32_x3(f32, 6, float32x2x3_t, vst3_f32, vld3_f32); - test_vld2_f32_x4(f32, 8, float32x2x4_t, vst4_f32, vld4_f32); + test_vld2_f32(f32, 4, float32x2x2_t, vst2_f32, vld2_f32); + test_vld3_f32(f32, 6, float32x2x3_t, vst3_f32, vld3_f32); + test_vld4_f32(f32, 8, float32x2x4_t, vst4_f32, vld4_f32); + + test_vld2q_f32(f32, 8, float32x4x2_t, vst2q_f32, vld2q_f32); + test_vld3q_f32(f32, 12, float32x4x3_t, vst3q_f32, vld3q_f32); + test_vld4q_f32(f32, 16, float32x4x4_t, vst4q_f32, vld4q_f32); - test_vld2q_f32_x2(f32, 8, float32x4x2_t, vst2q_f32, vld2q_f32); - test_vld3q_f32_x3(f32, 12, float32x4x3_t, vst3q_f32, vld3q_f32); - test_vld4q_f32_x4(f32, 16, float32x4x4_t, vst4q_f32, vld4q_f32); + test_vld2_f64(f64, 2, float64x1x2_t, vst2_f64, vld2_f64); + test_vld3_f64(f64, 3, float64x1x3_t, vst3_f64, vld3_f64); + test_vld4_f64(f64, 4, float64x1x4_t, vst4_f64, vld4_f64); - test_vld2_f64_x2(f64, 2, float64x1x2_t, vst2_f64, vld2_f64); - test_vld2_f64_x3(f64, 3, float64x1x3_t, vst3_f64, vld3_f64); - test_vld2_f64_x4(f64, 4, float64x1x4_t, vst4_f64, vld4_f64); + test_vld2q_f64(f64, 4, float64x2x2_t, vst2q_f64, vld2q_f64); + test_vld3q_f64(f64, 6, float64x2x3_t, vst3q_f64, vld3q_f64); + test_vld4q_f64(f64, 8, float64x2x4_t, vst4q_f64, vld4q_f64); - test_vld2q_f64_x2(f64, 4, float64x2x2_t, vst2q_f64, vld2q_f64); - test_vld3q_f64_x3(f64, 6, float64x2x3_t, vst3q_f64, vld3q_f64); - test_vld4q_f64_x4(f64, 8, float64x2x4_t, vst4q_f64, vld4q_f64); + test_vld2_s8(i8, 16, int8x8x2_t, vst2_s8, vld2_s8); + test_vld3_s8(i8, 24, int8x8x3_t, vst3_s8, vld3_s8); + test_vld4_s8(i8, 32, int8x8x4_t, vst4_s8, vld4_s8); - test_vld2_s8_x2(i8, 16, int8x8x2_t, vst2_s8, vld2_s8); - test_vld2_s8_x3(i8, 24, int8x8x3_t, vst3_s8, vld3_s8); - test_vld2_s8_x4(i8, 32, int8x8x4_t, vst4_s8, vld4_s8); + test_vld2q_s8(i8, 32, int8x16x2_t, vst2q_s8, vld2q_s8); + test_vld3q_s8(i8, 48, int8x16x3_t, vst3q_s8, vld3q_s8); + test_vld4q_s8(i8, 64, int8x16x4_t, vst4q_s8, vld4q_s8); - test_vld2q_s8_x2(i8, 32, int8x16x2_t, vst2q_s8, vld2q_s8); - test_vld3q_s8_x3(i8, 48, int8x16x3_t, vst3q_s8, vld3q_s8); - test_vld4q_s8_x4(i8, 64, int8x16x4_t, vst4q_s8, vld4q_s8); + test_vld2_s16(i16, 8, int16x4x2_t, vst2_s16, vld2_s16); + test_vld3_s16(i16, 12, int16x4x3_t, vst3_s16, vld3_s16); + test_vld4_s16(i16, 16, int16x4x4_t, vst4_s16, vld4_s16); - test_vld2_s16_x2(i16, 8, int16x4x2_t, vst2_s16, vld2_s16); - test_vld2_s16_x3(i16, 12, int16x4x3_t, vst3_s16, vld3_s16); - test_vld2_s16_x4(i16, 16, int16x4x4_t, vst4_s16, vld4_s16); + test_vld2q_s16(i16, 16, int16x8x2_t, vst2q_s16, vld2q_s16); + test_vld3q_s16(i16, 24, int16x8x3_t, vst3q_s16, vld3q_s16); + test_vld4q_s16(i16, 32, int16x8x4_t, vst4q_s16, vld4q_s16); - test_vld2q_s16_x2(i16, 16, int16x8x2_t, vst2q_s16, vld2q_s16); - test_vld3q_s16_x3(i16, 24, int16x8x3_t, vst3q_s16, vld3q_s16); - test_vld4q_s16_x4(i16, 32, int16x8x4_t, vst4q_s16, vld4q_s16); + test_vld2_s32(i32, 4, int32x2x2_t, vst2_s32, vld2_s32); + test_vld3_s32(i32, 6, int32x2x3_t, vst3_s32, vld3_s32); + test_vld4_s32(i32, 8, int32x2x4_t, vst4_s32, vld4_s32); - test_vld2_s32_x2(i32, 4, int32x2x2_t, vst2_s32, vld2_s32); - test_vld2_s32_x3(i32, 6, int32x2x3_t, vst3_s32, vld3_s32); - test_vld2_s32_x4(i32, 8, int32x2x4_t, vst4_s32, vld4_s32); + test_vld2q_s32(i32, 8, int32x4x2_t, vst2q_s32, vld2q_s32); + test_vld3q_s32(i32, 12, int32x4x3_t, vst3q_s32, vld3q_s32); + test_vld4q_s32(i32, 16, int32x4x4_t, vst4q_s32, vld4q_s32); - test_vld2q_s32_x2(i32, 8, int32x4x2_t, vst2q_s32, vld2q_s32); - test_vld3q_s32_x3(i32, 12, int32x4x3_t, vst3q_s32, vld3q_s32); - test_vld4q_s32_x4(i32, 16, int32x4x4_t, vst4q_s32, vld4q_s32); + test_vld2_s64(i64, 2, int64x1x2_t, vst2_s64, vld2_s64); + test_vld3_s64(i64, 3, int64x1x3_t, vst3_s64, vld3_s64); + test_vld4_s64(i64, 4, int64x1x4_t, vst4_s64, vld4_s64); - test_vld2_s64_x2(i64, 2, int64x1x2_t, vst2_s64, vld2_s64); - test_vld2_s64_x3(i64, 3, int64x1x3_t, vst3_s64, vld3_s64); - test_vld2_s64_x4(i64, 4, int64x1x4_t, vst4_s64, vld4_s64); + test_vld2q_s64(i64, 4, int64x2x2_t, vst2q_s64, vld2q_s64); + test_vld3q_s64(i64, 6, int64x2x3_t, vst3q_s64, vld3q_s64); + test_vld4q_s64(i64, 8, int64x2x4_t, vst4q_s64, vld4q_s64); - test_vld2q_s64_x2(i64, 4, int64x2x2_t, vst2q_s64, vld2q_s64); - test_vld3q_s64_x3(i64, 6, int64x2x3_t, vst3q_s64, vld3q_s64); - test_vld4q_s64_x4(i64, 8, int64x2x4_t, vst4q_s64, vld4q_s64); + test_vld2_u8(u8, 16, uint8x8x2_t, vst2_u8, vld2_u8); + test_vld3_u8(u8, 24, uint8x8x3_t, vst3_u8, vld3_u8); + test_vld4_u8(u8, 32, uint8x8x4_t, vst4_u8, vld4_u8); - test_vld2_u8_x2(u8, 16, uint8x8x2_t, vst2_u8, vld2_u8); - test_vld2_u8_x3(u8, 24, uint8x8x3_t, vst3_u8, vld3_u8); - test_vld2_u8_x4(u8, 32, uint8x8x4_t, vst4_u8, vld4_u8); + test_vld2q_u8(u8, 32, uint8x16x2_t, vst2q_u8, vld2q_u8); + test_vld3q_u8(u8, 48, uint8x16x3_t, vst3q_u8, vld3q_u8); + test_vld4q_u8(u8, 64, uint8x16x4_t, vst4q_u8, vld4q_u8); - test_vld2q_u8_x2(u8, 32, uint8x16x2_t, vst2q_u8, vld2q_u8); - test_vld3q_u8_x3(u8, 48, uint8x16x3_t, vst3q_u8, vld3q_u8); - test_vld4q_u8_x4(u8, 64, uint8x16x4_t, vst4q_u8, vld4q_u8); + test_vld2_u16(u16, 8, uint16x4x2_t, vst2_u16, vld2_u16); + test_vld3_u16(u16, 12, uint16x4x3_t, vst3_u16, vld3_u16); + test_vld4_u16(u16, 16, uint16x4x4_t, vst4_u16, vld4_u16); - test_vld2_u16_x2(u16, 8, uint16x4x2_t, vst2_u16, vld2_u16); - test_vld2_u16_x3(u16, 12, uint16x4x3_t, vst3_u16, vld3_u16); - test_vld2_u16_x4(u16, 16, uint16x4x4_t, vst4_u16, vld4_u16); + test_vld2q_u16(u16, 16, uint16x8x2_t, vst2q_u16, vld2q_u16); + test_vld3q_u16(u16, 24, uint16x8x3_t, vst3q_u16, vld3q_u16); + test_vld4q_u16(u16, 32, uint16x8x4_t, vst4q_u16, vld4q_u16); - test_vld2q_u16_x2(u16, 16, uint16x8x2_t, vst2q_u16, vld2q_u16); - test_vld3q_u16_x3(u16, 24, uint16x8x3_t, vst3q_u16, vld3q_u16); - test_vld4q_u16_x4(u16, 32, uint16x8x4_t, vst4q_u16, vld4q_u16); + test_vld2_u32(u32, 4, uint32x2x2_t, vst2_u32, vld2_u32); + test_vld3_u32(u32, 6, uint32x2x3_t, vst3_u32, vld3_u32); + test_vld4_u32(u32, 8, uint32x2x4_t, vst4_u32, vld4_u32); - test_vld2_u32_x2(u32, 4, uint32x2x2_t, vst2_u32, vld2_u32); - test_vld2_u32_x3(u32, 6, uint32x2x3_t, vst3_u32, vld3_u32); - test_vld2_u32_x4(u32, 8, uint32x2x4_t, vst4_u32, vld4_u32); + test_vld2q_u32(u32, 8, uint32x4x2_t, vst2q_u32, vld2q_u32); + test_vld3q_u32(u32, 12, uint32x4x3_t, vst3q_u32, vld3q_u32); + test_vld4q_u32(u32, 16, uint32x4x4_t, vst4q_u32, vld4q_u32); - test_vld2q_u32_x2(u32, 8, uint32x4x2_t, vst2q_u32, vld2q_u32); - test_vld3q_u32_x3(u32, 12, uint32x4x3_t, vst3q_u32, vld3q_u32); - test_vld4q_u32_x4(u32, 16, uint32x4x4_t, vst4q_u32, vld4q_u32); + test_vld2_u64(u64, 2, uint64x1x2_t, vst2_u64, vld2_u64); + test_vld3_u64(u64, 3, uint64x1x3_t, vst3_u64, vld3_u64); + test_vld4_u64(u64, 4, uint64x1x4_t, vst4_u64, vld4_u64); - test_vld2_u64_x2(u64, 2, uint64x1x2_t, vst2_u64, vld2_u64); - test_vld2_u64_x3(u64, 3, uint64x1x3_t, vst3_u64, vld3_u64); - test_vld2_u64_x4(u64, 4, uint64x1x4_t, vst4_u64, vld4_u64); + test_vld2q_u64(u64, 4, uint64x2x2_t, vst2q_u64, vld2q_u64); + test_vld3q_u64(u64, 6, uint64x2x3_t, vst3q_u64, vld3q_u64); + test_vld4q_u64(u64, 8, uint64x2x4_t, vst4q_u64, vld4q_u64); - test_vld2q_u64_x2(u64, 4, uint64x2x2_t, vst2q_u64, vld2q_u64); - test_vld3q_u64_x3(u64, 6, uint64x2x3_t, vst3q_u64, vld3q_u64); - test_vld4q_u64_x4(u64, 8, uint64x2x4_t, vst4q_u64, vld4q_u64); + test_vld2_p8(p8, 16, poly8x8x2_t, vst2_p8, vld2_p8); + test_vld3_p8(p8, 24, poly8x8x3_t, vst3_p8, vld3_p8); + test_vld4_p8(p8, 32, poly8x8x4_t, vst4_p8, vld4_p8); - test_vld2_p8_x2(p8, 16, poly8x8x2_t, vst2_p8, vld2_p8); - test_vld2_p8_x3(p8, 24, poly8x8x3_t, vst3_p8, vld3_p8); - test_vld2_p8_x4(p8, 32, poly8x8x4_t, vst4_p8, vld4_p8); + test_vld2q_p8(p8, 32, poly8x16x2_t, vst2q_p8, vld2q_p8); + test_vld3q_p8(p8, 48, poly8x16x3_t, vst3q_p8, vld3q_p8); + test_vld4q_p8(p8, 64, poly8x16x4_t, vst4q_p8, vld4q_p8); - test_vld2q_p8_x2(p8, 32, poly8x16x2_t, vst2q_p8, vld2q_p8); - test_vld3q_p8_x3(p8, 48, poly8x16x3_t, vst3q_p8, vld3q_p8); - test_vld4q_p8_x4(p8, 64, poly8x16x4_t, vst4q_p8, vld4q_p8); + test_vld2_p16(p16, 8, poly16x4x2_t, vst2_p16, vld2_p16); + test_vld3_p16(p16, 12, poly16x4x3_t, vst3_p16, vld3_p16); + test_vld4_p16(p16, 16, poly16x4x4_t, vst4_p16, vld4_p16); - test_vld2_p16_x2(p16, 8, poly16x4x2_t, vst2_p16, vld2_p16); - test_vld2_p16_x3(p16, 12, poly16x4x3_t, vst3_p16, vld3_p16); - test_vld2_p16_x4(p16, 16, poly16x4x4_t, vst4_p16, vld4_p16); + test_vld2q_p16(p16, 16, poly16x8x2_t, vst2q_p16, vld2q_p16); + test_vld3q_p16(p16, 24, poly16x8x3_t, vst3q_p16, vld3q_p16); + test_vld4q_p16(p16, 32, poly16x8x4_t, vst4q_p16, vld4q_p16); + } + + macro_rules! lane_wide_store_load_roundtrip { + ($elem_ty:ty, $len:expr, $idx:expr, $vec_ty:ty, $store:ident, $load:ident) => { + let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); + let a: $vec_ty = transmute(vals); + let mut tmp = [0 as $elem_ty; 4]; + $store::<$idx>(tmp.as_mut_ptr().cast(), a); + let r: $vec_ty = $load::<$idx>(tmp.as_ptr().cast(), a); + let out: [$elem_ty; $len] = transmute(r); + assert_eq!(out, vals); + }; + } + + macro_rules! lane_wide_store_load_roundtrip_neon { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics + #[simd_test(enable = "neon")] + unsafe fn $name() { + lane_wide_store_load_roundtrip! $args; + } + )* + }; + } - test_vld2q_p16_x2(p16, 16, poly16x8x2_t, vst2q_p16, vld2q_p16); - test_vld3q_p16_x3(p16, 24, poly16x8x3_t, vst3q_p16, vld3q_p16); - test_vld4q_p16_x4(p16, 32, poly16x8x4_t, vst4q_p16, vld4q_p16); + lane_wide_store_load_roundtrip_neon! { + test_vld2q_lane_s8(i8, 32, 15, int8x16x2_t, vst2q_lane_s8, vld2q_lane_s8); + test_vld3q_lane_s8(i8, 48, 15, int8x16x3_t, vst3q_lane_s8, vld3q_lane_s8); + test_vld4q_lane_s8(i8, 64, 15, int8x16x4_t, vst4q_lane_s8, vld4q_lane_s8); + + test_vld2q_lane_u8(u8, 32, 15, uint8x16x2_t, vst2q_lane_u8, vld2q_lane_u8); + test_vld3q_lane_u8(u8, 48, 15, uint8x16x3_t, vst3q_lane_u8, vld3q_lane_u8); + test_vld4q_lane_u8(u8, 64, 15, uint8x16x4_t, vst4q_lane_u8, vld4q_lane_u8); + + test_vld2_lane_s64(i64, 2, 0, int64x1x2_t, vst2_lane_s64, vld2_lane_s64); + test_vld3_lane_s64(i64, 3, 0, int64x1x3_t, vst3_lane_s64, vld3_lane_s64); + test_vld4_lane_s64(i64, 4, 0, int64x1x4_t, vst4_lane_s64, vld4_lane_s64); + test_vld2q_lane_s64(i64, 4, 1, int64x2x2_t, vst2q_lane_s64, vld2q_lane_s64); + test_vld3q_lane_s64(i64, 6, 1, int64x2x3_t, vst3q_lane_s64, vld3q_lane_s64); + test_vld4q_lane_s64(i64, 8, 1, int64x2x4_t, vst4q_lane_s64, vld4q_lane_s64); + + test_vld2_lane_u64(u64, 2, 0, uint64x1x2_t, vst2_lane_u64, vld2_lane_u64); + test_vld3_lane_u64(u64, 3, 0, uint64x1x3_t, vst3_lane_u64, vld3_lane_u64); + test_vld4_lane_u64(u64, 4, 0, uint64x1x4_t, vst4_lane_u64, vld4_lane_u64); + test_vld2q_lane_u64(u64, 4, 1, uint64x2x2_t, vst2q_lane_u64, vld2q_lane_u64); + test_vld3q_lane_u64(u64, 6, 1, uint64x2x3_t, vst3q_lane_u64, vld3q_lane_u64); + test_vld4q_lane_u64(u64, 8, 1, uint64x2x4_t, vst4q_lane_u64, vld4q_lane_u64); } } diff --git a/stdarch/crates/core_arch/src/aarch64/sve/generated.rs b/stdarch/crates/core_arch/src/aarch64/sve/generated.rs new file mode 100644 index 0000000000000..6c6a2476a43fd --- /dev/null +++ b/stdarch/crates/core_arch/src/aarch64/sve/generated.rs @@ -0,0 +1,44957 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(improper_ctypes)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use super::*; +use crate::core_arch::arch::aarch64::*; + +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabd.nxv4f32")] + fn _svabd_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svabd_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svabd_f32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svabd_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabd.nxv2f64")] + fn _svabd_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svabd_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svabd_f64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svabd_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv16i8")] + fn _svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svabd_s8_m(pg, op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svabd_s8_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svabd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv8i16")] + fn _svabd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svabd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svabd_s16_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svabd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv4i32")] + fn _svabd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svabd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svabd_s32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svabd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv2i64")] + fn _svabd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svabd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svabd_s64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svabd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv16i8")] + fn _svabd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svabd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svabd_u8_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svabd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv8i16")] + fn _svabd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svabd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svabd_u16_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svabd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv4i32")] + fn _svabd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svabd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svabd_u32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svabd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv2i64")] + fn _svabd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svabd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svabd_u64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svabd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabs.nxv4f32")] + fn _svabs_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svabs_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svabs_f32_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svabs_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabs.nxv2f64")] + fn _svabs_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svabs_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svabs_f64_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svabs_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv16i8")] + fn _svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svabs_s8_m(inactive, pg, op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svabs_s8_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svabs_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv8i16")] + fn _svabs_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svabs_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svabs_s16_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svabs_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv4i32")] + fn _svabs_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svabs_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svabs_s32_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svabs_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv2i64")] + fn _svabs_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svabs_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svabs_s64_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svabs_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facge.nxv4f32")] + fn _svacge_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svacge_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacge_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facge.nxv2f64")] + fn _svacge_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svacge_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacge_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facgt.nxv4f32")] + fn _svacgt_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svacgt_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacgt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facgt.nxv2f64")] + fn _svacgt_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svacgt_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacgt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svacge_f32(pg, op2, op1) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacle_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svacge_f64(pg, op2, op1) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacle_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svacgt_f32(pg, op2, op1) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svaclt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svacgt_f64(pg, op2, op1) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svaclt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadd.nxv4f32")] + fn _svadd_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svadd_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svadd_f32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svadd_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadd.nxv2f64")] + fn _svadd_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svadd_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svadd_f64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svadd_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv16i8")] + fn _svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svadd_s8_m(pg, op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svadd_s8_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv8i16")] + fn _svadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svadd_s16_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv4i32")] + fn _svadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svadd_s32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv2i64")] + fn _svadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svadd_s64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svadd_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svadd_u8_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svadd_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svadd_u16_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svadd_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svadd_u32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svadd_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svadd_u64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add reduction (strictly-ordered)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadda))] +pub fn svadda_f32(pg: svbool_t, initial: f32, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadda.nxv4f32")] + fn _svadda_f32(pg: svbool4_t, initial: f32, op: svfloat32_t) -> f32; + } + unsafe { _svadda_f32(pg.sve_into(), initial, op) } +} +#[doc = "Add reduction (strictly-ordered)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadda))] +pub fn svadda_f64(pg: svbool_t, initial: f64, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadda.nxv2f64")] + fn _svadda_f64(pg: svbool2_t, initial: f64, op: svfloat64_t) -> f64; + } + unsafe { _svadda_f64(pg.sve_into(), initial, op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddv))] +pub fn svaddv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddv.nxv4f32")] + fn _svaddv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svaddv_f32(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddv))] +pub fn svaddv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddv.nxv2f64")] + fn _svaddv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svaddv_f64(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv2i64")] + fn _svaddv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svaddv_s64(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv2i64")] + fn _svaddv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svaddv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s8(pg: svbool_t, op: svint8_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv16i8")] + fn _svaddv_s8(pg: svbool_t, op: svint8_t) -> i64; + } + unsafe { _svaddv_s8(pg, op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s16(pg: svbool_t, op: svint16_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv8i16")] + fn _svaddv_s16(pg: svbool8_t, op: svint16_t) -> i64; + } + unsafe { _svaddv_s16(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s32(pg: svbool_t, op: svint32_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv4i32")] + fn _svaddv_s32(pg: svbool4_t, op: svint32_t) -> i64; + } + unsafe { _svaddv_s32(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u8(pg: svbool_t, op: svuint8_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv16i8")] + fn _svaddv_u8(pg: svbool_t, op: svint8_t) -> i64; + } + unsafe { _svaddv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u16(pg: svbool_t, op: svuint16_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv8i16")] + fn _svaddv_u16(pg: svbool8_t, op: svint16_t) -> i64; + } + unsafe { _svaddv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u32(pg: svbool_t, op: svuint32_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv4i32")] + fn _svaddv_u32(pg: svbool4_t, op: svint32_t) -> i64; + } + unsafe { _svaddv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[s32]offset)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u32base_s32offset(bases: svuint32_t, offsets: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrb.nxv4i32")] + fn _svadrb_u32base_s32offset(bases: svint32_t, offsets: svint32_t) -> svint32_t; + } + unsafe { _svadrb_u32base_s32offset(bases.as_signed(), offsets).as_unsigned() } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[s32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrh.nxv4i32")] + fn _svadrh_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrh_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[s32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrw.nxv4i32")] + fn _svadrw_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrw_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[s32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrd.nxv4i32")] + fn _svadrd_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrd_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[u32]offset)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u32base_u32offset(bases: svuint32_t, offsets: svuint32_t) -> svuint32_t { + unsafe { svadrb_u32base_s32offset(bases, offsets.as_signed()) } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[u32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrh_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[u32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrw_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[u32]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrd_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[s64]offset)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u64base_s64offset(bases: svuint64_t, offsets: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrb.nxv2i64")] + fn _svadrb_u64base_s64offset(bases: svint64_t, offsets: svint64_t) -> svint64_t; + } + unsafe { _svadrb_u64base_s64offset(bases.as_signed(), offsets).as_unsigned() } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[s64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrh.nxv2i64")] + fn _svadrh_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrh_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[s64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrw.nxv2i64")] + fn _svadrw_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrw_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[s64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrd.nxv2i64")] + fn _svadrd_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrd_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[u64]offset)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u64base_u64offset(bases: svuint64_t, offsets: svuint64_t) -> svuint64_t { + unsafe { svadrb_u64base_s64offset(bases, offsets.as_signed()) } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[u64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrh_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[u64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrw_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[u64]index)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrd_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.z.nvx16i1")] + fn _svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svand_b_z(pg, op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv16i8")] + fn _svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svand_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svand_s8_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svand_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv8i16")] + fn _svand_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svand_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svand_s16_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svand_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv4i32")] + fn _svand_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svand_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svand_s32_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svand_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv2i64")] + fn _svand_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svand_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svand_s64_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svand_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svand_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svand_u8_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svand_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svand_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svand_u16_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svand_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svand_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svand_u32_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svand_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svand_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svand_u64_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svand_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv16i8")] + fn _svandv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svandv_s8(pg, op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv8i16")] + fn _svandv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svandv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv4i32")] + fn _svandv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svandv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv2i64")] + fn _svandv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svandv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svandv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svandv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svandv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svandv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv16i8")] + fn _svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svasr_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svasr_s8_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svasr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv8i16")] + fn _svasr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svasr_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svasr_s16_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svasr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv4i32")] + fn _svasr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svasr_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svasr_s32_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svasr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv2i64")] + fn _svasr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svasr_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svasr_s64_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svasr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv16i8" + )] + fn _svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svasr_wide_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svasr_wide_s8_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svasr_wide_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv8i16" + )] + fn _svasr_wide_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svasr_wide_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svasr_wide_s16_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svasr_wide_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv4i32" + )] + fn _svasr_wide_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svasr_wide_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svasr_wide_s32_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svasr_wide_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_m(pg: svbool_t, op1: svint8_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv16i8")] + fn _svasrd_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svasrd_n_s8_m(pg, op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_x(pg: svbool_t, op1: svint8_t) -> svint8_t { + svasrd_n_s8_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_z(pg: svbool_t, op1: svint8_t) -> svint8_t { + svasrd_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_m(pg: svbool_t, op1: svint16_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv8i16")] + fn _svasrd_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svasrd_n_s16_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_x(pg: svbool_t, op1: svint16_t) -> svint16_t { + svasrd_n_s16_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_z(pg: svbool_t, op1: svint16_t) -> svint16_t { + svasrd_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_m(pg: svbool_t, op1: svint32_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv4i32")] + fn _svasrd_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svasrd_n_s32_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_x(pg: svbool_t, op1: svint32_t) -> svint32_t { + svasrd_n_s32_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_z(pg: svbool_t, op1: svint32_t) -> svint32_t { + svasrd_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_m(pg: svbool_t, op1: svint64_t) -> svint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv2i64")] + fn _svasrd_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svasrd_n_s64_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_x(pg: svbool_t, op1: svint64_t) -> svint64_t { + svasrd_n_s64_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_z(pg: svbool_t, op1: svint64_t) -> svint64_t { + svasrd_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.z.nvx16i1")] + fn _svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbic_b_z(pg, op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv16i8")] + fn _svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbic_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svbic_s8_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svbic_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv8i16")] + fn _svbic_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbic_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svbic_s16_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svbic_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv4i32")] + fn _svbic_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbic_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svbic_s32_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svbic_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv2i64")] + fn _svbic_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbic_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svbic_s64_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svbic_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svbic_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svbic_u8_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svbic_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svbic_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svbic_u16_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svbic_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svbic_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svbic_u32_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svbic_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svbic_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svbic_u64_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svbic_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Break after first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brka))] +pub fn svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brka.nxv16i1")] + fn _svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrka_b_m(inactive, pg, op) } +} +#[doc = "Break after first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brka))] +pub fn svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brka.z.nxv16i1")] + fn _svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrka_b_z(pg, op) } +} +#[doc = "Break before first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkb))] +pub fn svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkb.nxv16i1")] + fn _svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrkb_b_m(inactive, pg, op) } +} +#[doc = "Break before first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkb))] +pub fn svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkb.z.nxv16i1")] + fn _svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrkb_b_z(pg, op) } +} +#[doc = "Propagate break to next partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkn[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkn))] +pub fn svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkn.z.nxv16i1")] + fn _svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkn_b_z(pg, op1, op2) } +} +#[doc = "Break after first true condition, propagating from previous partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpa[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkpa))] +pub fn svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.brkpa.z.nxv16i1" + )] + fn _svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkpa_b_z(pg, op1, op2) } +} +#[doc = "Break before first true condition, propagating from previous partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpb[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkpb))] +pub fn svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.brkpb.z.nxv16i1" + )] + fn _svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkpb_b_z(pg, op1, op2) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcadd.nxv4f32")] + fn _svcadd_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcadd_f32_m(pg.sve_into(), op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + svcadd_f32_m::(pg, op1, op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + svcadd_f32_m::(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcadd.nxv2f64")] + fn _svcadd_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + imm_rotation: i32, + ) -> svfloat64_t; + } + unsafe { _svcadd_f64_m(pg.sve_into(), op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + svcadd_f64_m::(pg, op1, op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + svcadd_f64_m::(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv4f32")] + fn _svclasta_f32(pg: svbool4_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t; + } + unsafe { _svclasta_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv2f64")] + fn _svclasta_f64(pg: svbool2_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t; + } + unsafe { _svclasta_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv16i8")] + fn _svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t; + } + unsafe { _svclasta_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv8i16")] + fn _svclasta_s16(pg: svbool8_t, fallback: svint16_t, data: svint16_t) -> svint16_t; + } + unsafe { _svclasta_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv4i32")] + fn _svclasta_s32(pg: svbool4_t, fallback: svint32_t, data: svint32_t) -> svint32_t; + } + unsafe { _svclasta_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv2i64")] + fn _svclasta_s64(pg: svbool2_t, fallback: svint64_t, data: svint64_t) -> svint64_t; + } + unsafe { _svclasta_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint8_t { + unsafe { svclasta_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svuint16_t { + unsafe { svclasta_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svuint32_t { + unsafe { svclasta_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svuint64_t { + unsafe { svclasta_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv4f32" + )] + fn _svclasta_n_f32(pg: svbool4_t, fallback: f32, data: svfloat32_t) -> f32; + } + unsafe { _svclasta_n_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv2f64" + )] + fn _svclasta_n_f64(pg: svbool2_t, fallback: f64, data: svfloat64_t) -> f64; + } + unsafe { _svclasta_n_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv16i8" + )] + fn _svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8; + } + unsafe { _svclasta_n_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv8i16" + )] + fn _svclasta_n_s16(pg: svbool8_t, fallback: i16, data: svint16_t) -> i16; + } + unsafe { _svclasta_n_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv4i32" + )] + fn _svclasta_n_s32(pg: svbool4_t, fallback: i32, data: svint32_t) -> i32; + } + unsafe { _svclasta_n_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv2i64" + )] + fn _svclasta_n_s64(pg: svbool2_t, fallback: i64, data: svint64_t) -> i64; + } + unsafe { _svclasta_n_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 { + unsafe { svclasta_n_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 { + unsafe { svclasta_n_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 { + unsafe { svclasta_n_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 { + unsafe { svclasta_n_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv4f32")] + fn _svclastb_f32(pg: svbool4_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t; + } + unsafe { _svclastb_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv2f64")] + fn _svclastb_f64(pg: svbool2_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t; + } + unsafe { _svclastb_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv16i8")] + fn _svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t; + } + unsafe { _svclastb_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv8i16")] + fn _svclastb_s16(pg: svbool8_t, fallback: svint16_t, data: svint16_t) -> svint16_t; + } + unsafe { _svclastb_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv4i32")] + fn _svclastb_s32(pg: svbool4_t, fallback: svint32_t, data: svint32_t) -> svint32_t; + } + unsafe { _svclastb_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv2i64")] + fn _svclastb_s64(pg: svbool2_t, fallback: svint64_t, data: svint64_t) -> svint64_t; + } + unsafe { _svclastb_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint8_t { + unsafe { svclastb_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svuint16_t { + unsafe { svclastb_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svuint32_t { + unsafe { svclastb_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svuint64_t { + unsafe { svclastb_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv4f32" + )] + fn _svclastb_n_f32(pg: svbool4_t, fallback: f32, data: svfloat32_t) -> f32; + } + unsafe { _svclastb_n_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv2f64" + )] + fn _svclastb_n_f64(pg: svbool2_t, fallback: f64, data: svfloat64_t) -> f64; + } + unsafe { _svclastb_n_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv16i8" + )] + fn _svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8; + } + unsafe { _svclastb_n_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv8i16" + )] + fn _svclastb_n_s16(pg: svbool8_t, fallback: i16, data: svint16_t) -> i16; + } + unsafe { _svclastb_n_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv4i32" + )] + fn _svclastb_n_s32(pg: svbool4_t, fallback: i32, data: svint32_t) -> i32; + } + unsafe { _svclastb_n_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv2i64" + )] + fn _svclastb_n_s64(pg: svbool2_t, fallback: i64, data: svint64_t) -> i64; + } + unsafe { _svclastb_n_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 { + unsafe { svclastb_n_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 { + unsafe { svclastb_n_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 { + unsafe { svclastb_n_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 { + unsafe { svclastb_n_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv16i8")] + fn _svcls_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcls_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svcls_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svcls_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv8i16")] + fn _svcls_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcls_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svcls_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svcls_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv4i32")] + fn _svcls_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcls_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svcls_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svcls_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv2i64")] + fn _svcls_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcls_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svcls_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svcls_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv16i8")] + fn _svclz_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svclz_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svclz_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svclz_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv8i16")] + fn _svclz_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svclz_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svclz_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svclz_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv4i32")] + fn _svclz_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svclz_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svclz_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svclz_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv2i64")] + fn _svclz_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svclz_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svclz_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svclz_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svclz_s8_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svclz_u8_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svclz_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svclz_s16_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svclz_u16_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svclz_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svclz_s32_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svclz_u32_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svclz_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svclz_s64_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svclz_u64_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svclz_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmla.nxv4f32")] + fn _svcmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcmla_f32_m(pg.sve_into(), op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svcmla_f32_m::(pg, op1, op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svcmla_f32_m::(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmla.nxv2f64")] + fn _svcmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + imm_rotation: i32, + ) -> svfloat64_t; + } + unsafe { _svcmla_f64_m(pg.sve_into(), op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svcmla_f64_m::(pg, op1, op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svcmla_f64_m::(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fcmla.lane.x.nxv4f32" + )] + fn _svcmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcmla_lane_f32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpeq.nxv4f32")] + fn _svcmpeq_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpeq_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpeq_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpeq.nxv2f64")] + fn _svcmpeq_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpeq_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpeq_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv16i8")] + fn _svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpeq_s8(pg, op1, op2) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpeq_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv8i16")] + fn _svcmpeq_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpeq_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpeq_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv4i32")] + fn _svcmpeq_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpeq_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpeq_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv2i64")] + fn _svcmpeq_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpeq_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpeq_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svcmpeq_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpeq_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svcmpeq_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpeq_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe { svcmpeq_s32(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpeq_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe { svcmpeq_s64(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpeq_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv16i8" + )] + fn _svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpeq_wide_s8(pg, op1, op2) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpeq_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv8i16" + )] + fn _svcmpeq_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpeq_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpeq_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv4i32" + )] + fn _svcmpeq_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpeq_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpeq_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpge.nxv4f32")] + fn _svcmpge_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpge_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpge_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpge.nxv2f64")] + fn _svcmpge_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpge_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpge_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv16i8")] + fn _svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpge_s8(pg, op1, op2) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpge_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv8i16")] + fn _svcmpge_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpge_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpge_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv4i32")] + fn _svcmpge_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpge_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpge_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv2i64")] + fn _svcmpge_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpge_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpge_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv16i8")] + fn _svcmpge_u8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpge_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpge_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv8i16")] + fn _svcmpge_u16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpge_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpge_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv4i32")] + fn _svcmpge_u32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpge_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpge_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv2i64")] + fn _svcmpge_u64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpge_u64(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpge_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv16i8" + )] + fn _svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpge_wide_s8(pg, op1, op2) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpge_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv8i16" + )] + fn _svcmpge_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpge_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpge_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv4i32" + )] + fn _svcmpge_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpge_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpge_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv16i8" + )] + fn _svcmpge_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpge_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmpge_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv8i16" + )] + fn _svcmpge_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpge_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmpge_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv4i32" + )] + fn _svcmpge_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpge_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmpge_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpgt.nxv4f32")] + fn _svcmpgt_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpgt_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpgt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpgt.nxv2f64")] + fn _svcmpgt_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpgt_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpgt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv16i8")] + fn _svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpgt_s8(pg, op1, op2) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpgt_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv8i16")] + fn _svcmpgt_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpgt_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpgt_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv4i32")] + fn _svcmpgt_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpgt_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpgt_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv2i64")] + fn _svcmpgt_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpgt_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpgt_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv16i8")] + fn _svcmpgt_u8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpgt_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpgt_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv8i16")] + fn _svcmpgt_u16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpgt_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpgt_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv4i32")] + fn _svcmpgt_u32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpgt_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpgt_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv2i64")] + fn _svcmpgt_u64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpgt_u64(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpgt_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv16i8" + )] + fn _svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpgt_wide_s8(pg, op1, op2) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpgt_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv8i16" + )] + fn _svcmpgt_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpgt_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpgt_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv4i32" + )] + fn _svcmpgt_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpgt_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpgt_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv16i8" + )] + fn _svcmpgt_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpgt_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmpgt_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv8i16" + )] + fn _svcmpgt_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpgt_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmpgt_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv4i32" + )] + fn _svcmpgt_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpgt_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmpgt_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svcmpge_f32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmple_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svcmpge_f64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmple_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + svcmpge_s8(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmple_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + svcmpge_s16(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmple_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + svcmpge_s32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmple_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + svcmpge_s64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmple_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + svcmpge_u8(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmple_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + svcmpge_u16(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmple_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + svcmpge_u32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmple_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + svcmpge_u64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmple_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv16i8" + )] + fn _svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmple_wide_s8(pg, op1, op2) } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmple_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv8i16" + )] + fn _svcmple_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmple_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmple_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv4i32" + )] + fn _svcmple_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmple_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmple_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv16i8" + )] + fn _svcmple_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmple_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmple_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv8i16" + )] + fn _svcmple_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmple_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmple_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv4i32" + )] + fn _svcmple_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmple_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmple_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svcmpgt_f32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmplt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svcmpgt_f64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmplt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + svcmpgt_s8(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmplt_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + svcmpgt_s16(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmplt_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + svcmpgt_s32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmplt_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + svcmpgt_s64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmplt_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + svcmpgt_u8(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmplt_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + svcmpgt_u16(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmplt_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + svcmpgt_u32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmplt_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + svcmpgt_u64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmplt_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv16i8" + )] + fn _svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmplt_wide_s8(pg, op1, op2) } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmplt_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv8i16" + )] + fn _svcmplt_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmplt_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmplt_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv4i32" + )] + fn _svcmplt_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmplt_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmplt_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv16i8" + )] + fn _svcmplt_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmplt_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmplt_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv8i16" + )] + fn _svcmplt_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmplt_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmplt_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv4i32" + )] + fn _svcmplt_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmplt_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmplt_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpne.nxv4f32")] + fn _svcmpne_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpne_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpne_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpne.nxv2f64")] + fn _svcmpne_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpne_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpne_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv16i8")] + fn _svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpne_s8(pg, op1, op2) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpne_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv8i16")] + fn _svcmpne_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpne_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpne_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv4i32")] + fn _svcmpne_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpne_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpne_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv2i64")] + fn _svcmpne_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpne_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpne_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svcmpne_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpne_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svcmpne_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpne_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe { svcmpne_s32(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpne_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe { svcmpne_s64(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpne_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv16i8" + )] + fn _svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpne_wide_s8(pg, op1, op2) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpne_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv8i16" + )] + fn _svcmpne_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpne_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpne_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv4i32" + )] + fn _svcmpne_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpne_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpne_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpuo.nxv4f32")] + fn _svcmpuo_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpuo_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpuo_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpuo.nxv2f64")] + fn _svcmpuo_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpuo_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpuo_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv16i8")] + fn _svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcnot_s8_m(inactive, pg, op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svcnot_s8_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svcnot_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv8i16")] + fn _svcnot_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcnot_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svcnot_s16_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svcnot_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv4i32")] + fn _svcnot_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcnot_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svcnot_s32_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svcnot_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv2i64")] + fn _svcnot_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcnot_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svcnot_s64_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svcnot_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svcnot_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnot_u8_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnot_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svcnot_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnot_u16_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnot_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcnot_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnot_u32_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnot_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcnot_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnot_u64_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnot_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv4f32")] + fn _svcnt_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcnt_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe { svcnt_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + svcnt_f32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv2f64")] + fn _svcnt_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcnt_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe { svcnt_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + svcnt_f64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv16i8")] + fn _svcnt_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcnt_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svcnt_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svcnt_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv8i16")] + fn _svcnt_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcnt_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svcnt_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svcnt_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv4i32")] + fn _svcnt_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcnt_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svcnt_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svcnt_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv2i64")] + fn _svcnt_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcnt_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svcnt_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svcnt_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svcnt_s8_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnt_u8_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnt_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svcnt_s16_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnt_u16_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnt_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcnt_s32_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnt_u32_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnt_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcnt_s64_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnt_u64_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnt_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count the number of 8-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svcntb() -> u64 { + svcntb_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 16-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svcnth() -> u64 { + svcnth_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 32-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svcntw() -> u64 { + svcntw_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 64-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svcntd() -> u64 { + svcntd_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 8-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb_pat)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (rdvl , PATTERN = { svpattern :: SV_ALL }))] +# [cfg_attr (test , assert_instr (cntb , PATTERN = { svpattern :: SV_MUL4 }))] +pub fn svcntb_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntb")] + fn _svcntb_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntb_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 16-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth_pat)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cnth , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcnth_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnth")] + fn _svcnth_pat(pattern: svpattern) -> i64; + } + unsafe { _svcnth_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 32-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw_pat)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cntw , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcntw_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntw")] + fn _svcntw_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntw_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 64-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd_pat)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cntd , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcntd_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntd")] + fn _svcntd_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntd_pat(PATTERN).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b8(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv16i1")] + fn _svcntp_b8(pg: svbool_t, op: svbool_t) -> i64; + } + unsafe { _svcntp_b8(pg, op).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b16(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv8i1")] + fn _svcntp_b16(pg: svbool8_t, op: svbool8_t) -> i64; + } + unsafe { _svcntp_b16(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b32(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv4i1")] + fn _svcntp_b32(pg: svbool4_t, op: svbool4_t) -> i64; + } + unsafe { _svcntp_b32(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b64(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv2i1")] + fn _svcntp_b64(pg: svbool2_t, op: svbool2_t) -> i64; + } + unsafe { _svcntp_b64(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_f32(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv4f32" + )] + fn _svcompact_f32(pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svcompact_f32(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_f64(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv2f64" + )] + fn _svcompact_f64(pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svcompact_f64(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_s32(pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv4i32" + )] + fn _svcompact_s32(pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcompact_s32(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_s64(pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv2i64" + )] + fn _svcompact_s64(pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcompact_s64(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_u32(pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcompact_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_u64(pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcompact_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_f32(x0: svfloat32_t, x1: svfloat32_t) -> svfloat32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_f64(x0: svfloat64_t, x1: svfloat64_t) -> svfloat64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s8(x0: svint8_t, x1: svint8_t) -> svint8x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s16(x0: svint16_t, x1: svint16_t) -> svint16x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s32(x0: svint32_t, x1: svint32_t) -> svint32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s64(x0: svint64_t, x1: svint64_t) -> svint64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u8(x0: svuint8_t, x1: svuint8_t) -> svuint8x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u16(x0: svuint16_t, x1: svuint16_t) -> svuint16x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u32(x0: svuint32_t, x1: svuint32_t) -> svuint32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u64(x0: svuint64_t, x1: svuint64_t) -> svuint64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_f32(x0: svfloat32_t, x1: svfloat32_t, x2: svfloat32_t) -> svfloat32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_f64(x0: svfloat64_t, x1: svfloat64_t, x2: svfloat64_t) -> svfloat64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t) -> svint8x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t) -> svint16x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t) -> svint32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t) -> svint64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t) -> svuint8x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u16(x0: svuint16_t, x1: svuint16_t, x2: svuint16_t) -> svuint16x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u32(x0: svuint32_t, x1: svuint32_t, x2: svuint32_t) -> svuint32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u64(x0: svuint64_t, x1: svuint64_t, x2: svuint64_t) -> svuint64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_f32( + x0: svfloat32_t, + x1: svfloat32_t, + x2: svfloat32_t, + x3: svfloat32_t, +) -> svfloat32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_f64( + x0: svfloat64_t, + x1: svfloat64_t, + x2: svfloat64_t, + x3: svfloat64_t, +) -> svfloat64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t, x3: svint8_t) -> svint8x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t, x3: svint16_t) -> svint16x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t, x3: svint32_t) -> svint32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t, x3: svint64_t) -> svint64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t, x3: svuint8_t) -> svuint8x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u16( + x0: svuint16_t, + x1: svuint16_t, + x2: svuint16_t, + x3: svuint16_t, +) -> svuint16x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u32( + x0: svuint32_t, + x1: svuint32_t, + x2: svuint32_t, + x3: svuint32_t, +) -> svuint32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u64( + x0: svuint64_t, + x1: svuint64_t, + x2: svuint64_t, + x3: svuint64_t, +) -> svuint64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvt.f32f64")] + fn _svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe { svcvt_f32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvt_f32_f64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvt.f64f32")] + fn _svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe { svcvt_f64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + svcvt_f64_f32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool_t, op: svint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i32")] + fn _svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_x(pg: svbool_t, op: svint32_t) -> svfloat32_t { + unsafe { svcvt_f32_s32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_z(pg: svbool_t, op: svint32_t) -> svfloat32_t { + svcvt_f32_s32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool_t, op: svint64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i64")] + fn _svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_x(pg: svbool_t, op: svint64_t) -> svfloat32_t { + unsafe { svcvt_f32_s64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_z(pg: svbool_t, op: svint64_t) -> svfloat32_t { + svcvt_f32_s64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool_t, op: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f32i32")] + fn _svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_u32_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat32_t { + unsafe { svcvt_f32_u32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat32_t { + svcvt_f32_u32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool_t, op: svuint64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f32i64")] + fn _svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_u64_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat32_t { + unsafe { svcvt_f32_u64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat32_t { + svcvt_f32_u64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool_t, op: svint32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f64i32")] + fn _svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool2_t, op: svint32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_x(pg: svbool_t, op: svint32_t) -> svfloat64_t { + unsafe { svcvt_f64_s32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_z(pg: svbool_t, op: svint32_t) -> svfloat64_t { + svcvt_f64_s32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool_t, op: svint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f64i64")] + fn _svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_x(pg: svbool_t, op: svint64_t) -> svfloat64_t { + unsafe { svcvt_f64_s64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_z(pg: svbool_t, op: svint64_t) -> svfloat64_t { + svcvt_f64_s64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool_t, op: svuint32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f64i32")] + fn _svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool2_t, op: svint32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_u32_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat64_t { + unsafe { svcvt_f64_u32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat64_t { + svcvt_f64_u32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool_t, op: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f64i64")] + fn _svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_u64_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat64_t { + unsafe { svcvt_f64_u64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat64_t { + svcvt_f64_u64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f32")] + fn _svcvt_s32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcvt_s32_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe { svcvt_s32_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t { + svcvt_s32_f32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_m(inactive: svint32_t, pg: svbool_t, op: svfloat64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f64")] + fn _svcvt_s32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t; + } + unsafe { _svcvt_s32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_x(pg: svbool_t, op: svfloat64_t) -> svint32_t { + unsafe { svcvt_s32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_z(pg: svbool_t, op: svfloat64_t) -> svint32_t { + svcvt_s32_f64_m(svdup_n_s32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_m(inactive: svint64_t, pg: svbool_t, op: svfloat32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f32")] + fn _svcvt_s64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t; + } + unsafe { _svcvt_s64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_x(pg: svbool_t, op: svfloat32_t) -> svint64_t { + unsafe { svcvt_s64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_z(pg: svbool_t, op: svfloat32_t) -> svint64_t { + svcvt_s64_f32_m(svdup_n_s64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f64")] + fn _svcvt_s64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcvt_s64_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe { svcvt_s64_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t { + svcvt_s64_f64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i32f32")] + fn _svcvt_u32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcvt_u32_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe { svcvt_u32_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + svcvt_u32_f32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_m(inactive: svuint32_t, pg: svbool_t, op: svfloat64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i32f64")] + fn _svcvt_u32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t; + } + unsafe { _svcvt_u32_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint32_t { + unsafe { svcvt_u32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint32_t { + svcvt_u32_f64_m(svdup_n_u32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_m(inactive: svuint64_t, pg: svbool_t, op: svfloat32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i64f32")] + fn _svcvt_u64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t; + } + unsafe { _svcvt_u64_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint64_t { + unsafe { svcvt_u64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint64_t { + svcvt_u64_f32_m(svdup_n_u64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i64f64")] + fn _svcvt_u64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcvt_u64_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe { svcvt_u64_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + svcvt_u64_f64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdiv.nxv4f32")] + fn _svdiv_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svdiv_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdiv_f32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdiv_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdiv.nxv2f64")] + fn _svdiv_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svdiv_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdiv_f64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdiv_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdiv.nxv4i32")] + fn _svdiv_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdiv_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdiv_s32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdiv_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdiv.nxv2i64")] + fn _svdiv_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdiv_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdiv_s64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdiv_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udiv.nxv4i32")] + fn _svdiv_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdiv_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdiv_u32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdiv_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udiv.nxv2i64")] + fn _svdiv_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdiv_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdiv_u64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdiv_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdivr.nxv4f32")] + fn _svdivr_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svdivr_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdivr_f32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdivr_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdivr.nxv2f64")] + fn _svdivr_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svdivr_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdivr_f64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdivr_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdivr.nxv4i32")] + fn _svdivr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdivr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdivr_s32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdivr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdivr.nxv2i64")] + fn _svdivr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdivr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdivr_s64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdivr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udivr.nxv4i32")] + fn _svdivr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdivr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdivr_u32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdivr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udivr.nxv2i64")] + fn _svdivr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdivr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdivr_u64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdivr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))] +pub fn svdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sdot.lane.nxv4i32" + )] + fn _svdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svdot_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))] +pub fn svdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sdot.lane.nxv2i64" + )] + fn _svdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + ) -> svint64_t; + } + unsafe { _svdot_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))] +pub fn svdot_lane_u32( + op1: svuint32_t, + op2: svuint8_t, + op3: svuint8_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.udot.lane.nxv4i32" + )] + fn _svdot_lane_u32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { + _svdot_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX).as_unsigned() + } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))] +pub fn svdot_lane_u64( + op1: svuint64_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.udot.lane.nxv2i64" + )] + fn _svdot_lane_u64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + ) -> svint64_t; + } + unsafe { + _svdot_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX).as_unsigned() + } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdot.nxv4i32")] + fn _svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svdot_s32(op1, op2, op3) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_n_s32(op1: svint32_t, op2: svint8_t, op3: i8) -> svint32_t { + svdot_s32(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdot.nxv2i64")] + fn _svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t; + } + unsafe { _svdot_s64(op1, op2, op3) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_n_s64(op1: svint64_t, op2: svint16_t, op3: i16) -> svint64_t { + svdot_s64(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udot.nxv4i32")] + fn _svdot_u32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svdot_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_n_u32(op1: svuint32_t, op2: svuint8_t, op3: u8) -> svuint32_t { + svdot_u32(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_u64(op1: svuint64_t, op2: svuint16_t, op3: svuint16_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udot.nxv2i64")] + fn _svdot_u64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t; + } + unsafe { _svdot_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_n_u64(op1: svuint64_t, op2: svuint16_t, op3: u16) -> svuint64_t { + svdot_u64(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_f32(data: svfloat32_t, index: u32) -> svfloat32_t { + svtbl_f32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t { + svtbl_f64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s8(data: svint8_t, index: u8) -> svint8_t { + svtbl_s8(data, svdup_n_u8(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s16(data: svint16_t, index: u16) -> svint16_t { + svtbl_s16(data, svdup_n_u16(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s32(data: svint32_t, index: u32) -> svint32_t { + svtbl_s32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s64(data: svint64_t, index: u64) -> svint64_t { + svtbl_s64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u8(data: svuint8_t, index: u8) -> svuint8_t { + svtbl_u8(data, svdup_n_u8(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u16(data: svuint16_t, index: u16) -> svuint16_t { + svtbl_u16(data, svdup_n_u16(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u32(data: svuint32_t, index: u32) -> svuint32_t { + svtbl_u32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u64(data: svuint64_t, index: u64) -> svuint64_t { + svtbl_u64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b8(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv16i1")] + fn _svdup_n_b8(op: bool) -> svbool_t; + } + unsafe { _svdup_n_b8(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b16(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv8i1")] + fn _svdup_n_b16(op: bool) -> svbool8_t; + } + unsafe { _svdup_n_b16(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b32(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i1")] + fn _svdup_n_b32(op: bool) -> svbool4_t; + } + unsafe { _svdup_n_b32(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b64(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2i1")] + fn _svdup_n_b64(op: bool) -> svbool2_t; + } + unsafe { _svdup_n_b64(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32(op: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4f32")] + fn _svdup_n_f32(op: f32) -> svfloat32_t; + } + unsafe { _svdup_n_f32(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64(op: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2f64")] + fn _svdup_n_f64(op: f64) -> svfloat64_t; + } + unsafe { _svdup_n_f64(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8(op: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv16i8")] + fn _svdup_n_s8(op: i8) -> svint8_t; + } + unsafe { _svdup_n_s8(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16(op: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv8i16")] + fn _svdup_n_s16(op: i16) -> svint16_t; + } + unsafe { _svdup_n_s16(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32(op: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i32")] + fn _svdup_n_s32(op: i32) -> svint32_t; + } + unsafe { _svdup_n_s32(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64(op: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2i64")] + fn _svdup_n_s64(op: i64) -> svint64_t; + } + unsafe { _svdup_n_s64(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8(op: u8) -> svuint8_t { + unsafe { svdup_n_s8(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16(op: u16) -> svuint16_t { + unsafe { svdup_n_s16(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32(op: u32) -> svuint32_t { + unsafe { svdup_n_s32(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64(op: u64) -> svuint64_t { + unsafe { svdup_n_s64(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_m(inactive: svfloat32_t, pg: svbool_t, op: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv4f32")] + fn _svdup_n_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: f32) -> svfloat32_t; + } + unsafe { _svdup_n_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_x(pg: svbool_t, op: f32) -> svfloat32_t { + svdup_n_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_z(pg: svbool_t, op: f32) -> svfloat32_t { + svdup_n_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_m(inactive: svfloat64_t, pg: svbool_t, op: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv2f64")] + fn _svdup_n_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: f64) -> svfloat64_t; + } + unsafe { _svdup_n_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_x(pg: svbool_t, op: f64) -> svfloat64_t { + svdup_n_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_z(pg: svbool_t, op: f64) -> svfloat64_t { + svdup_n_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv16i8")] + fn _svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t; + } + unsafe { _svdup_n_s8_m(inactive, pg, op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_x(pg: svbool_t, op: i8) -> svint8_t { + svdup_n_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_z(pg: svbool_t, op: i8) -> svint8_t { + svdup_n_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_m(inactive: svint16_t, pg: svbool_t, op: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv8i16")] + fn _svdup_n_s16_m(inactive: svint16_t, pg: svbool8_t, op: i16) -> svint16_t; + } + unsafe { _svdup_n_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_x(pg: svbool_t, op: i16) -> svint16_t { + svdup_n_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_z(pg: svbool_t, op: i16) -> svint16_t { + svdup_n_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_m(inactive: svint32_t, pg: svbool_t, op: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv4i32")] + fn _svdup_n_s32_m(inactive: svint32_t, pg: svbool4_t, op: i32) -> svint32_t; + } + unsafe { _svdup_n_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_x(pg: svbool_t, op: i32) -> svint32_t { + svdup_n_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_z(pg: svbool_t, op: i32) -> svint32_t { + svdup_n_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_m(inactive: svint64_t, pg: svbool_t, op: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv2i64")] + fn _svdup_n_s64_m(inactive: svint64_t, pg: svbool2_t, op: i64) -> svint64_t; + } + unsafe { _svdup_n_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_x(pg: svbool_t, op: i64) -> svint64_t { + svdup_n_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_z(pg: svbool_t, op: i64) -> svint64_t { + svdup_n_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_m(inactive: svuint8_t, pg: svbool_t, op: u8) -> svuint8_t { + unsafe { svdup_n_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_x(pg: svbool_t, op: u8) -> svuint8_t { + svdup_n_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_z(pg: svbool_t, op: u8) -> svuint8_t { + svdup_n_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_m(inactive: svuint16_t, pg: svbool_t, op: u16) -> svuint16_t { + unsafe { svdup_n_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_x(pg: svbool_t, op: u16) -> svuint16_t { + svdup_n_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_z(pg: svbool_t, op: u16) -> svuint16_t { + svdup_n_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_m(inactive: svuint32_t, pg: svbool_t, op: u32) -> svuint32_t { + unsafe { svdup_n_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_x(pg: svbool_t, op: u32) -> svuint32_t { + svdup_n_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_z(pg: svbool_t, op: u32) -> svuint32_t { + svdup_n_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_m(inactive: svuint64_t, pg: svbool_t, op: u64) -> svuint64_t { + unsafe { svdup_n_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_x(pg: svbool_t, op: u64) -> svuint64_t { + svdup_n_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_z(pg: svbool_t, op: u64) -> svuint64_t { + svdup_n_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_f32(data: svfloat32_t, index: u64) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv4f32" + )] + fn _svdupq_lane_f32(data: svfloat32_t, index: i64) -> svfloat32_t; + } + unsafe { _svdupq_lane_f32(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv2f64" + )] + fn _svdupq_lane_f64(data: svfloat64_t, index: i64) -> svfloat64_t; + } + unsafe { _svdupq_lane_f64(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s8(data: svint8_t, index: u64) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv16i8" + )] + fn _svdupq_lane_s8(data: svint8_t, index: i64) -> svint8_t; + } + unsafe { _svdupq_lane_s8(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s16(data: svint16_t, index: u64) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv8i16" + )] + fn _svdupq_lane_s16(data: svint16_t, index: i64) -> svint16_t; + } + unsafe { _svdupq_lane_s16(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s32(data: svint32_t, index: u64) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv4i32" + )] + fn _svdupq_lane_s32(data: svint32_t, index: i64) -> svint32_t; + } + unsafe { _svdupq_lane_s32(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s64(data: svint64_t, index: u64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv2i64" + )] + fn _svdupq_lane_s64(data: svint64_t, index: i64) -> svint64_t; + } + unsafe { _svdupq_lane_s64(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u8(data: svuint8_t, index: u64) -> svuint8_t { + unsafe { svdupq_lane_s8(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u16(data: svuint16_t, index: u64) -> svuint16_t { + unsafe { svdupq_lane_s16(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u32(data: svuint32_t, index: u64) -> svuint32_t { + unsafe { svdupq_lane_s32(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u64(data: svuint64_t, index: u64) -> svuint64_t { + unsafe { svdupq_lane_s64(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b16( + x0: bool, + x1: bool, + x2: bool, + x3: bool, + x4: bool, + x5: bool, + x6: bool, + x7: bool, +) -> svbool_t { + let op1 = svdupq_n_s16( + x0 as i16, x1 as i16, x2 as i16, x3 as i16, x4 as i16, x5 as i16, x6 as i16, x7 as i16, + ); + svcmpne_wide_s16(svptrue_b16(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b32(x0: bool, x1: bool, x2: bool, x3: bool) -> svbool_t { + let op1 = svdupq_n_s32(x0 as i32, x1 as i32, x2 as i32, x3 as i32); + svcmpne_wide_s32(svptrue_b32(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b64(x0: bool, x1: bool) -> svbool_t { + let op1 = svdupq_n_s64(x0 as i64, x1 as i64); + svcmpne_s64(svptrue_b64(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b8( + x0: bool, + x1: bool, + x2: bool, + x3: bool, + x4: bool, + x5: bool, + x6: bool, + x7: bool, + x8: bool, + x9: bool, + x10: bool, + x11: bool, + x12: bool, + x13: bool, + x14: bool, + x15: bool, +) -> svbool_t { + let op1 = svdupq_n_s8( + x0 as i8, x1 as i8, x2 as i8, x3 as i8, x4 as i8, x5 as i8, x6 as i8, x7 as i8, x8 as i8, + x9 as i8, x10 as i8, x11 as i8, x12 as i8, x13 as i8, x14 as i8, x15 as i8, + ); + svcmpne_wide_s8(svptrue_b8(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_f32(x0: f32, x1: f32, x2: f32, x3: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv4f32.v4f32" + )] + fn _svdupq_n_f32(op0: svfloat32_t, op1: float32x4_t, idx: i64) -> svfloat32_t; + } + unsafe { + let op = _svdupq_n_f32(svundef_f32(), crate::mem::transmute([x0, x1, x2, x3]), 0); + svdupq_lane_f32(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s32(x0: i32, x1: i32, x2: i32, x3: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv4i32.v4i32" + )] + fn _svdupq_n_s32(op0: svint32_t, op1: int32x4_t, idx: i64) -> svint32_t; + } + unsafe { + let op = _svdupq_n_s32(svundef_s32(), crate::mem::transmute([x0, x1, x2, x3]), 0); + svdupq_lane_s32(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u32(x0: u32, x1: u32, x2: u32, x3: u32) -> svuint32_t { + unsafe { + svdupq_n_s32( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_f64(x0: f64, x1: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv2f64.v2f64" + )] + fn _svdupq_n_f64(op0: svfloat64_t, op1: float64x2_t, idx: i64) -> svfloat64_t; + } + unsafe { + let op = _svdupq_n_f64(svundef_f64(), crate::mem::transmute([x0, x1]), 0); + svdupq_lane_f64(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s64(x0: i64, x1: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv2i64.v2i64" + )] + fn _svdupq_n_s64(op0: svint64_t, op1: int64x2_t, idx: i64) -> svint64_t; + } + unsafe { + let op = _svdupq_n_s64(svundef_s64(), crate::mem::transmute([x0, x1]), 0); + svdupq_lane_s64(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u64(x0: u64, x1: u64) -> svuint64_t { + unsafe { svdupq_n_s64(x0.as_signed(), x1.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s16( + x0: i16, + x1: i16, + x2: i16, + x3: i16, + x4: i16, + x5: i16, + x6: i16, + x7: i16, +) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv8i16.v8i16" + )] + fn _svdupq_n_s16(op0: svint16_t, op1: int16x8_t, idx: i64) -> svint16_t; + } + unsafe { + let op = _svdupq_n_s16( + svundef_s16(), + crate::mem::transmute([x0, x1, x2, x3, x4, x5, x6, x7]), + 0, + ); + svdupq_lane_s16(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u16( + x0: u16, + x1: u16, + x2: u16, + x3: u16, + x4: u16, + x5: u16, + x6: u16, + x7: u16, +) -> svuint16_t { + unsafe { + svdupq_n_s16( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + x4.as_signed(), + x5.as_signed(), + x6.as_signed(), + x7.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s8( + x0: i8, + x1: i8, + x2: i8, + x3: i8, + x4: i8, + x5: i8, + x6: i8, + x7: i8, + x8: i8, + x9: i8, + x10: i8, + x11: i8, + x12: i8, + x13: i8, + x14: i8, + x15: i8, +) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.vector.insert.nxv16i8.v16i8" + )] + fn _svdupq_n_s8(op0: svint8_t, op1: int8x16_t, idx: i64) -> svint8_t; + } + unsafe { + let op = _svdupq_n_s8( + svundef_s8(), + crate::mem::transmute([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, + ]), + 0, + ); + svdupq_lane_s8(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u8( + x0: u8, + x1: u8, + x2: u8, + x3: u8, + x4: u8, + x5: u8, + x6: u8, + x7: u8, + x8: u8, + x9: u8, + x10: u8, + x11: u8, + x12: u8, + x13: u8, + x14: u8, + x15: u8, +) -> svuint8_t { + unsafe { + svdupq_n_s8( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + x4.as_signed(), + x5.as_signed(), + x6.as_signed(), + x7.as_signed(), + x8.as_signed(), + x9.as_signed(), + x10.as_signed(), + x11.as_signed(), + x12.as_signed(), + x13.as_signed(), + x14.as_signed(), + x15.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.z.nvx16i1")] + fn _sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _sveor_b_z(pg, op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv16i8")] + fn _sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveor_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + sveor_s8_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + sveor_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv8i16")] + fn _sveor_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveor_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + sveor_s16_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + sveor_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv4i32")] + fn _sveor_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveor_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + sveor_s32_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + sveor_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv2i64")] + fn _sveor_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveor_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + sveor_s64_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + sveor_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveor_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + sveor_u8_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + sveor_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveor_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + sveor_u16_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + sveor_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveor_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + sveor_u32_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + sveor_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveor_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + sveor_u64_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + sveor_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv16i8")] + fn _sveorv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _sveorv_s8(pg, op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv8i16")] + fn _sveorv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _sveorv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv4i32")] + fn _sveorv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _sveorv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv2i64")] + fn _sveorv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _sveorv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { sveorv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { sveorv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { sveorv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { sveorv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Floating-point exponential accelerator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fexpa))] +pub fn svexpa_f32(op: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fexpa.x.nxv4f32 " + )] + fn _svexpa_f32(op: svint32_t) -> svfloat32_t; + } + unsafe { _svexpa_f32(op.as_signed()) } +} +#[doc = "Floating-point exponential accelerator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fexpa))] +pub fn svexpa_f64(op: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fexpa.x.nxv2f64 " + )] + fn _svexpa_f64(op: svint64_t) -> svfloat64_t; + } + unsafe { _svexpa_f64(op.as_signed()) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv4f32")] + fn _svext_f32(op1: svfloat32_t, op2: svfloat32_t, imm3: i32) -> svfloat32_t; + } + unsafe { _svext_f32(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv2f64")] + fn _svext_f64(op1: svfloat64_t, op2: svfloat64_t, imm3: i32) -> svfloat64_t; + } + unsafe { _svext_f64(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 0..=255); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv16i8")] + fn _svext_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svext_s8(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 0..=127); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv8i16")] + fn _svext_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svext_s16(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv4i32")] + fn _svext_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svext_s32(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv2i64")] + fn _svext_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svext_s64(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 0..=255); + unsafe { svext_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 0..=127); + unsafe { svext_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 0..=63); + unsafe { svext_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 0..=31); + unsafe { svext_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv8i16")] + fn _svextb_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svextb_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svextb_s16_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svextb_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv4i32")] + fn _svextb_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svextb_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svextb_s32_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svextb_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxth.nxv4i32")] + fn _svexth_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svexth_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svexth_s32_m(op, pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svexth_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv2i64")] + fn _svextb_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextb_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svextb_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svextb_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxth.nxv2i64")] + fn _svexth_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svexth_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svexth_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svexth_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtw.nxv2i64")] + fn _svextw_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextw_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svextw_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svextw_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv8i16")] + fn _svextb_u16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svextb_u16_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svextb_u16_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svextb_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv4i32")] + fn _svextb_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svextb_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svextb_u32_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svextb_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxth.nxv4i32")] + fn _svexth_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svexth_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svexth_u32_m(op, pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svexth_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv2i64")] + fn _svextb_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextb_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextb_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextb_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxth.nxv2i64")] + fn _svexth_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svexth_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svexth_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svexth_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtw.nxv2i64")] + fn _svextw_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextw_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextw_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextw_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_f32(tuple: svfloat32x2_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_f64(tuple: svfloat64x2_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s8(tuple: svint8x2_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s16(tuple: svint16x2_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s32(tuple: svint32x2_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s64(tuple: svint64x2_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u8(tuple: svuint8x2_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u16(tuple: svuint16x2_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u32(tuple: svuint32x2_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u64(tuple: svuint64x2_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_f32(tuple: svfloat32x3_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_f64(tuple: svfloat64x3_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s8(tuple: svint8x3_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s16(tuple: svint16x3_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s32(tuple: svint32x3_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s64(tuple: svint64x3_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u8(tuple: svuint8x3_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u16(tuple: svuint16x3_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u32(tuple: svuint32x3_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u64(tuple: svuint64x3_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_f32(tuple: svfloat32x4_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_f64(tuple: svfloat64x4_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s8(tuple: svint8x4_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s16(tuple: svint16x4_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s32(tuple: svint32x4_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s64(tuple: svint64x4_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u8(tuple: svuint8x4_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u16(tuple: svuint16x4_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u32(tuple: svuint32x4_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u64(tuple: svuint64x4_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s8(base: i8, step: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv16i8")] + fn _svindex_s8(base: i8, step: i8) -> svint8_t; + } + unsafe { _svindex_s8(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s16(base: i16, step: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv8i16")] + fn _svindex_s16(base: i16, step: i16) -> svint16_t; + } + unsafe { _svindex_s16(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s32(base: i32, step: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv4i32")] + fn _svindex_s32(base: i32, step: i32) -> svint32_t; + } + unsafe { _svindex_s32(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s64(base: i64, step: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv2i64")] + fn _svindex_s64(base: i64, step: i64) -> svint64_t; + } + unsafe { _svindex_s64(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u8(base: u8, step: u8) -> svuint8_t { + unsafe { svindex_s8(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u16(base: u16, step: u16) -> svuint16_t { + unsafe { svindex_s16(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u32(base: u32, step: u32) -> svuint32_t { + unsafe { svindex_s32(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u64(base: u64, step: u64) -> svuint64_t { + unsafe { svindex_s64(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv4f32")] + fn _svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t; + } + unsafe { _svinsr_n_f32(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv2f64")] + fn _svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t; + } + unsafe { _svinsr_n_f64(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv16i8")] + fn _svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t; + } + unsafe { _svinsr_n_s8(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv8i16")] + fn _svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t; + } + unsafe { _svinsr_n_s16(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv4i32")] + fn _svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t; + } + unsafe { _svinsr_n_s32(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv2i64")] + fn _svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t; + } + unsafe { _svinsr_n_s64(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + unsafe { svinsr_n_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + unsafe { svinsr_n_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + unsafe { svinsr_n_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + unsafe { svinsr_n_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv4f32")] + fn _svlasta_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svlasta_f32(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv2f64")] + fn _svlasta_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svlasta_f64(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv16i8")] + fn _svlasta_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svlasta_s8(pg, op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv8i16")] + fn _svlasta_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svlasta_s16(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv4i32")] + fn _svlasta_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svlasta_s32(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv2i64")] + fn _svlasta_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svlasta_s64(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svlasta_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svlasta_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svlasta_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svlasta_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv4f32")] + fn _svlastb_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svlastb_f32(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv2f64")] + fn _svlastb_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svlastb_f64(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv16i8")] + fn _svlastb_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svlastb_s8(pg, op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv8i16")] + fn _svlastb_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svlastb_s16(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv4i32")] + fn _svlastb_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svlastb_s32(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv2i64")] + fn _svlastb_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svlastb_s64(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svlastb_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svlastb_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svlastb_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svlastb_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4f32")] + fn _svld1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2f64")] + fn _svld1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv16i8")] + fn _svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1_s8(pg, base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i16")] + fn _svld1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i32")] + fn _svld1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i64")] + fn _svld1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_f32( + pg: svbool_t, + base: *const f32, + indices: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4f32" + )] + fn _svld1_gather_s32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_s32index_f32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_s32( + pg: svbool_t, + base: *const i32, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i32" + )] + fn _svld1_gather_s32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svld1_gather_s32index_s32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_u32( + pg: svbool_t, + base: *const u32, + indices: svint32_t, +) -> svuint32_t { + svld1_gather_s32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2f64" + )] + fn _svld1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svld1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i64" + )] + fn _svld1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svld1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svld1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_f32( + pg: svbool_t, + base: *const f32, + indices: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4f32" + )] + fn _svld1_gather_u32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_u32index_f32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_s32( + pg: svbool_t, + base: *const i32, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i32" + )] + fn _svld1_gather_u32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svld1_gather_u32index_s32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_u32( + pg: svbool_t, + base: *const u32, + indices: svuint32_t, +) -> svuint32_t { + svld1_gather_u32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svld1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svld1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svld1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32" + )] + fn _svld1_gather_s32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_s32offset_f32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32" + )] + fn _svld1_gather_s32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svld1_gather_s32offset_s32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svint32_t, +) -> svuint32_t { + svld1_gather_s32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2f64" + )] + fn _svld1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svld1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i64" + )] + fn _svld1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svld1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svld1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32" + )] + fn _svld1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32" + )] + fn _svld1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svld1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svld1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svld1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svld1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svld1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svld1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svld1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svld1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svld1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svld1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svld1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svld1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svld1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svld1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svld1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svld1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svld1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svld1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svld1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svld1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svld1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svld1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svld1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svld1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svld1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svld1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svld1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv4f32")] + fn _svld1ro_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1ro_f32(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv2f64")] + fn _svld1ro_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1ro_f64(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rob))] +pub unsafe fn svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv16i8")] + fn _svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1ro_s8(pg, base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1roh))] +pub unsafe fn svld1ro_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv8i16")] + fn _svld1ro_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1ro_s16(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv4i32")] + fn _svld1ro_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1ro_s32(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv2i64")] + fn _svld1ro_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1ro_s64(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rob))] +pub unsafe fn svld1ro_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1ro_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1roh))] +pub unsafe fn svld1ro_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1ro_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1ro_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1ro_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv4f32")] + fn _svld1rq_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1rq_f32(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv2f64")] + fn _svld1rq_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1rq_f64(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqb))] +pub unsafe fn svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv16i8")] + fn _svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1rq_s8(pg, base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqh))] +pub unsafe fn svld1rq_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv8i16")] + fn _svld1rq_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1rq_s16(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv4i32")] + fn _svld1rq_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1rq_s32(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv2i64")] + fn _svld1rq_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1rq_s64(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqb))] +pub unsafe fn svld1rq_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1rq_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqh))] +pub unsafe fn svld1rq_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1rq_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1rq_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1rq_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8" + )] + fn _svld1sb_gather_s32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_s32offset_s32(pg.sve_into(), base, offsets)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16" + )] + fn _svld1sh_gather_s32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s32offset_s32(pg.sve_into(), base, offsets)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svuint32_t { + svld1sb_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svuint32_t { + svld1sh_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i8" + )] + fn _svld1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i16" + )] + fn _svld1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i32" + )] + fn _svld1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8" + )] + fn _svld1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16" + )] + fn _svld1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svld1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svld1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svld1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svld1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svld1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svld1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svld1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i8")] + fn _svld1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i8")] + fn _svld1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i16")] + fn _svld1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i8")] + fn _svld1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i16")] + fn _svld1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i32")] + fn _svld1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svld1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svld1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svld1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svld1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svld1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svld1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svld1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svld1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svld1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svld1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svld1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svld1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svld1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svld1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svld1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svld1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svld1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svld1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32index_s32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16" + )] + fn _svld1sh_gather_s32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s32index_s32(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32index_u32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svuint32_t { + svld1sh_gather_s32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i16" + )] + fn _svld1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i32" + )] + fn _svld1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svld1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svld1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32index_s32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16" + )] + fn _svld1sh_gather_u32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32index_s32( + pg.sve_into(), + base, + indices.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32index_u32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svuint32_t { + svld1sh_gather_u32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svld1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svld1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svld1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svld1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svint32_t { + svld1ub_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svint32_t { + svld1uh_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8" + )] + fn _svld1ub_gather_s32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16" + )] + fn _svld1uh_gather_s32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i8" + )] + fn _svld1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i16" + )] + fn _svld1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i32" + )] + fn _svld1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svld1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svld1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8" + )] + fn _svld1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16" + )] + fn _svld1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svld1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svld1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svld1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svld1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svld1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svld1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i8")] + fn _svld1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i8")] + fn _svld1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i16")] + fn _svld1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i8")] + fn _svld1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i16")] + fn _svld1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i32")] + fn _svld1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svld1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svld1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svld1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svld1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svld1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svld1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svld1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svld1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svld1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svld1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svld1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svld1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svld1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svld1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svld1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svld1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svld1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svld1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32index_s32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svint32_t { + svld1uh_gather_s32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32index_u32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16" + )] + fn _svld1uh_gather_s32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s32index_u32(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svld1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svld1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i16" + )] + fn _svld1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i32" + )] + fn _svld1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32index_s32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svint32_t { + svld1uh_gather_u32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32index_u32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16" + )] + fn _svld1uh_gather_u32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32index_u32(pg.sve_into(), base.as_signed(), indices.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svld1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svld1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svld1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svld1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_f32(pg: svbool_t, base: *const f32) -> svfloat32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv4f32" + )] + fn _svld2_f32(pg: svbool4_t, base: *const f32) -> svfloat32x2_t; + } + _svld2_f32(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_f64(pg: svbool_t, base: *const f64) -> svfloat64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv2f64" + )] + fn _svld2_f64(pg: svbool2_t, base: *const f64) -> svfloat64x2_t; + } + _svld2_f64(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv16i8" + )] + fn _svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t; + } + _svld2_s8(pg, base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_s16(pg: svbool_t, base: *const i16) -> svint16x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv8i16" + )] + fn _svld2_s16(pg: svbool8_t, base: *const i16) -> svint16x2_t; + } + _svld2_s16(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_s32(pg: svbool_t, base: *const i32) -> svint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv4i32" + )] + fn _svld2_s32(pg: svbool4_t, base: *const i32) -> svint32x2_t; + } + _svld2_s32(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_s64(pg: svbool_t, base: *const i64) -> svint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv2i64" + )] + fn _svld2_s64(pg: svbool2_t, base: *const i64) -> svint64x2_t; + } + _svld2_s64(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_u8(pg: svbool_t, base: *const u8) -> svuint8x2_t { + svld2_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_u16(pg: svbool_t, base: *const u16) -> svuint16x2_t { + svld2_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_u32(pg: svbool_t, base: *const u32) -> svuint32x2_t { + svld2_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_u64(pg: svbool_t, base: *const u64) -> svuint64x2_t { + svld2_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x2_t { + svld2_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x2_t { + svld2_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x2_t { + svld2_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x2_t { + svld2_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x2_t { + svld2_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x2_t { + svld2_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x2_t { + svld2_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x2_t { + svld2_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x2_t { + svld2_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x2_t { + svld2_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_f32(pg: svbool_t, base: *const f32) -> svfloat32x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv4f32" + )] + fn _svld3_f32(pg: svbool4_t, base: *const f32) -> svfloat32x3_t; + } + _svld3_f32(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_f64(pg: svbool_t, base: *const f64) -> svfloat64x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv2f64" + )] + fn _svld3_f64(pg: svbool2_t, base: *const f64) -> svfloat64x3_t; + } + _svld3_f64(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv16i8" + )] + fn _svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t; + } + _svld3_s8(pg, base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_s16(pg: svbool_t, base: *const i16) -> svint16x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv8i16" + )] + fn _svld3_s16(pg: svbool8_t, base: *const i16) -> svint16x3_t; + } + _svld3_s16(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_s32(pg: svbool_t, base: *const i32) -> svint32x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv4i32" + )] + fn _svld3_s32(pg: svbool4_t, base: *const i32) -> svint32x3_t; + } + _svld3_s32(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_s64(pg: svbool_t, base: *const i64) -> svint64x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv2i64" + )] + fn _svld3_s64(pg: svbool2_t, base: *const i64) -> svint64x3_t; + } + _svld3_s64(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_u8(pg: svbool_t, base: *const u8) -> svuint8x3_t { + svld3_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_u16(pg: svbool_t, base: *const u16) -> svuint16x3_t { + svld3_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_u32(pg: svbool_t, base: *const u32) -> svuint32x3_t { + svld3_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_u64(pg: svbool_t, base: *const u64) -> svuint64x3_t { + svld3_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x3_t { + svld3_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x3_t { + svld3_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x3_t { + svld3_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x3_t { + svld3_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x3_t { + svld3_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x3_t { + svld3_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x3_t { + svld3_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x3_t { + svld3_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x3_t { + svld3_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x3_t { + svld3_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_f32(pg: svbool_t, base: *const f32) -> svfloat32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv4f32" + )] + fn _svld4_f32(pg: svbool4_t, base: *const f32) -> svfloat32x4_t; + } + _svld4_f32(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_f64(pg: svbool_t, base: *const f64) -> svfloat64x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv2f64" + )] + fn _svld4_f64(pg: svbool2_t, base: *const f64) -> svfloat64x4_t; + } + _svld4_f64(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv16i8" + )] + fn _svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t; + } + _svld4_s8(pg, base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_s16(pg: svbool_t, base: *const i16) -> svint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv8i16" + )] + fn _svld4_s16(pg: svbool8_t, base: *const i16) -> svint16x4_t; + } + _svld4_s16(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_s32(pg: svbool_t, base: *const i32) -> svint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv4i32" + )] + fn _svld4_s32(pg: svbool4_t, base: *const i32) -> svint32x4_t; + } + _svld4_s32(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_s64(pg: svbool_t, base: *const i64) -> svint64x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv2i64" + )] + fn _svld4_s64(pg: svbool2_t, base: *const i64) -> svint64x4_t; + } + _svld4_s64(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_u8(pg: svbool_t, base: *const u8) -> svuint8x4_t { + svld4_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_u16(pg: svbool_t, base: *const u16) -> svuint16x4_t { + svld4_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_u32(pg: svbool_t, base: *const u32) -> svuint32x4_t { + svld4_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_u64(pg: svbool_t, base: *const u64) -> svuint64x4_t { + svld4_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x4_t { + svld4_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x4_t { + svld4_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x4_t { + svld4_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x4_t { + svld4_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x4_t { + svld4_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x4_t { + svld4_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x4_t { + svld4_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x4_t { + svld4_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x4_t { + svld4_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x4_t { + svld4_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4f32")] + fn _svldff1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldff1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2f64")] + fn _svldff1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldff1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv16i8")] + fn _svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldff1_s8(pg, base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i16")] + fn _svldff1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldff1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i32")] + fn _svldff1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldff1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i64")] + fn _svldff1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldff1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldff1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldff1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldff1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldff1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_f32( + pg: svbool_t, + base: *const f32, + indices: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4f32" + )] + fn _svldff1_gather_s32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_s32index_f32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_s32( + pg: svbool_t, + base: *const i32, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32" + )] + fn _svldff1_gather_s32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_s32index_s32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_u32( + pg: svbool_t, + base: *const u32, + indices: svint32_t, +) -> svuint32_t { + svldff1_gather_s32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2f64" + )] + fn _svldff1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svldff1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i64" + )] + fn _svldff1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svldff1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svldff1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_f32( + pg: svbool_t, + base: *const f32, + indices: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4f32" + )] + fn _svldff1_gather_u32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_u32index_f32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_s32( + pg: svbool_t, + base: *const i32, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i32" + )] + fn _svldff1_gather_u32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_u32index_s32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_u32( + pg: svbool_t, + base: *const u32, + indices: svuint32_t, +) -> svuint32_t { + svldff1_gather_u32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svldff1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svldff1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svldff1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4f32" + )] + fn _svldff1_gather_s32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_s32offset_f32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i32" + )] + fn _svldff1_gather_s32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_s32offset_s32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svint32_t, +) -> svuint32_t { + svldff1_gather_s32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2f64" + )] + fn _svldff1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svldff1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i64" + )] + fn _svldff1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svldff1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svldff1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4f32" + )] + fn _svldff1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i32" + )] + fn _svldff1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svldff1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svldff1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svldff1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svldff1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svldff1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svldff1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svldff1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svldff1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svldff1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svldff1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svldff1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svldff1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svldff1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svldff1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svldff1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svldff1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldff1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldff1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldff1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldff1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldff1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldff1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldff1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldff1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldff1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldff1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8" + )] + fn _svldff1sb_gather_s32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_s32offset_s32( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16" + )] + fn _svldff1sh_gather_s32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s32offset_s32( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svuint32_t { + svldff1sb_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svuint32_t { + svldff1sh_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i8" + )] + fn _svldff1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i16" + )] + fn _svldff1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i32" + )] + fn _svldff1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8" + )] + fn _svldff1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16" + )] + fn _svldff1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svldff1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svldff1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldff1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldff1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldff1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldff1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldff1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i8")] + fn _svldff1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i8")] + fn _svldff1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i16")] + fn _svldff1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i8")] + fn _svldff1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i16")] + fn _svldff1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i32")] + fn _svldff1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svldff1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svldff1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svldff1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svldff1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svldff1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svldff1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svldff1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svldff1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svldff1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svldff1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svldff1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svldff1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svldff1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svldff1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svldff1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svldff1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svldff1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svldff1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32index_s32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16" + )] + fn _svldff1sh_gather_s32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s32index_s32(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32index_u32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svuint32_t { + svldff1sh_gather_s32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i16" + )] + fn _svldff1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i32" + )] + fn _svldff1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32index_s32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16" + )] + fn _svldff1sh_gather_u32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32index_s32( + pg.sve_into(), + base, + indices.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32index_u32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svuint32_t { + svldff1sh_gather_u32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svint32_t { + svldff1ub_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svint32_t { + svldff1uh_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8" + )] + fn _svldff1ub_gather_s32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16" + )] + fn _svldff1uh_gather_s32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i8" + )] + fn _svldff1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i16" + )] + fn _svldff1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i32" + )] + fn _svldff1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svldff1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svldff1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8" + )] + fn _svldff1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16" + )] + fn _svldff1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldff1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldff1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldff1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldff1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldff1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldff1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i8")] + fn _svldff1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i8")] + fn _svldff1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i16")] + fn _svldff1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i8")] + fn _svldff1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i16")] + fn _svldff1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i32")] + fn _svldff1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svldff1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svldff1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svldff1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svldff1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svldff1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svldff1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svldff1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svldff1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svldff1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svldff1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svldff1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svldff1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svldff1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svldff1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svldff1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svldff1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svldff1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svldff1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32index_s32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svint32_t { + svldff1uh_gather_s32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32index_u32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16" + )] + fn _svldff1uh_gather_s32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s32index_u32(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i16" + )] + fn _svldff1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i32" + )] + fn _svldff1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32index_s32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svint32_t { + svldff1uh_gather_u32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32index_u32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16" + )] + fn _svldff1uh_gather_u32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32index_u32(pg.sve_into(), base.as_signed(), indices.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4f32")] + fn _svldnf1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldnf1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2f64")] + fn _svldnf1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldnf1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv16i8")] + fn _svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldnf1_s8(pg, base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i16")] + fn _svldnf1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldnf1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i32")] + fn _svldnf1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldnf1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i64")] + fn _svldnf1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldnf1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldnf1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldnf1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldnf1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldnf1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldnf1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldnf1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldnf1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldnf1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldnf1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldnf1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldnf1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldnf1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldnf1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldnf1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i8")] + fn _svldnf1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i8")] + fn _svldnf1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i16")] + fn _svldnf1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnf1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i8")] + fn _svldnf1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i16")] + fn _svldnf1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnf1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i32")] + fn _svldnf1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnf1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svldnf1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svldnf1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svldnf1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svldnf1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svldnf1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svldnf1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svldnf1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svldnf1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svldnf1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svldnf1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svldnf1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svldnf1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svldnf1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svldnf1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svldnf1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svldnf1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svldnf1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svldnf1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i8")] + fn _svldnf1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i8")] + fn _svldnf1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i16")] + fn _svldnf1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i8")] + fn _svldnf1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i16")] + fn _svldnf1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i32")] + fn _svldnf1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svldnf1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svldnf1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svldnf1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svldnf1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svldnf1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svldnf1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svldnf1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svldnf1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svldnf1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svldnf1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svldnf1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svldnf1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svldnf1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svldnf1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svldnf1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svldnf1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svldnf1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svldnf1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv4f32")] + fn _svldnt1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldnt1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv2f64")] + fn _svldnt1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldnt1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv16i8")] + fn _svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldnt1_s8(pg, base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv8i16")] + fn _svldnt1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldnt1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv4i32")] + fn _svldnt1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldnt1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv2i64")] + fn _svldnt1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldnt1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldnt1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldnt1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldnt1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldnt1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldnt1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldnt1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldnt1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldnt1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldnt1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldnt1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldnt1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldnt1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldnt1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldnt1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_f32(_op: svfloat32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_f64(_op: svfloat64_t) -> u64 { + svcntd() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svlen_s8(_op: svint8_t) -> u64 { + svcntb() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svlen_s16(_op: svint16_t) -> u64 { + svcnth() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_s32(_op: svint32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_s64(_op: svint64_t) -> u64 { + svcntd() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svlen_u8(_op: svuint8_t) -> u64 { + svcntb() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svlen_u16(_op: svuint16_t) -> u64 { + svcnth() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_u32(_op: svuint32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_u64(_op: svuint64_t) -> u64 { + svcntd() +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv16i8")] + fn _svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svlsl_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svlsl_s8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svlsl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv8i16")] + fn _svlsl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svlsl_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svlsl_s16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svlsl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv4i32")] + fn _svlsl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svlsl_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svlsl_s32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svlsl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv2i64")] + fn _svlsl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svlsl_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svlsl_s64_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svlsl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svlsl_s8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsl_u8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svlsl_s16_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsl_u16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svlsl_s32_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsl_u32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svlsl_s64_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsl_u64_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv16i8" + )] + fn _svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svlsl_wide_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svlsl_wide_s8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svlsl_wide_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv8i16" + )] + fn _svlsl_wide_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svlsl_wide_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svlsl_wide_s16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svlsl_wide_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv4i32" + )] + fn _svlsl_wide_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svlsl_wide_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svlsl_wide_s32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svlsl_wide_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + unsafe { svlsl_wide_s8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsl_wide_u8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsl_wide_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + unsafe { svlsl_wide_s16_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsl_wide_u16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsl_wide_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + unsafe { svlsl_wide_s32_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsl_wide_u32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsl_wide_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv16i8")] + fn _svlsr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svlsr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsr_u8_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv8i16")] + fn _svlsr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svlsr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsr_u16_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv4i32")] + fn _svlsr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svlsr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsr_u32_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv2i64")] + fn _svlsr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svlsr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsr_u64_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv16i8" + )] + fn _svlsr_wide_u8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svlsr_wide_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsr_wide_u8_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsr_wide_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv8i16" + )] + fn _svlsr_wide_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svlsr_wide_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsr_wide_u16_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsr_wide_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv4i32" + )] + fn _svlsr_wide_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svlsr_wide_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsr_wide_u32_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsr_wide_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmad.nxv4f32")] + fn _svmad_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmad_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmad_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmad_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmad.nxv2f64")] + fn _svmad_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmad_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmad_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmad_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv16i8")] + fn _svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmad_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmad_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmad_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv8i16")] + fn _svmad_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmad_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmad_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmad_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv4i32")] + fn _svmad_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmad_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmad_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmad_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv2i64")] + fn _svmad_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmad_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmad_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmad_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmad_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmad_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmad_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmad_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmad_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmad_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmad_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmad_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmad_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmad_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmad_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmad_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmax.nxv4f32")] + fn _svmax_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmax_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmax_f32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmax_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmax.nxv2f64")] + fn _svmax_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmax_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmax_f64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmax_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv16i8")] + fn _svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmax_s8_m(pg, op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmax_s8_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmax_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv8i16")] + fn _svmax_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmax_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmax_s16_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmax_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv4i32")] + fn _svmax_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmax_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmax_s32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmax_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv2i64")] + fn _svmax_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmax_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmax_s64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmax_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv16i8")] + fn _svmax_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmax_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmax_u8_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmax_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv8i16")] + fn _svmax_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmax_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmax_u16_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmax_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv4i32")] + fn _svmax_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmax_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmax_u32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmax_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv2i64")] + fn _svmax_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmax_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmax_u64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmax_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxnm.nxv4f32")] + fn _svmaxnm_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxnm_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnm_f32_m(pg, op1, op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnm_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxnm.nxv2f64")] + fn _svmaxnm_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxnm_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnm_f64_m(pg, op1, op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnm_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmv))] +pub fn svmaxnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmv.nxv4f32" + )] + fn _svmaxnmv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svmaxnmv_f32(pg.sve_into(), op) } +} +#[doc = "Maximum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmv))] +pub fn svmaxnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmv.nxv2f64" + )] + fn _svmaxnmv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svmaxnmv_f64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxv))] +pub fn svmaxv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxv.nxv4f32")] + fn _svmaxv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svmaxv_f32(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxv))] +pub fn svmaxv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxv.nxv2f64")] + fn _svmaxv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svmaxv_f64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv16i8")] + fn _svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svmaxv_s8(pg, op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv8i16")] + fn _svmaxv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svmaxv_s16(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv4i32")] + fn _svmaxv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svmaxv_s32(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv2i64")] + fn _svmaxv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svmaxv_s64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv16i8")] + fn _svmaxv_u8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svmaxv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv8i16")] + fn _svmaxv_u16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svmaxv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv4i32")] + fn _svmaxv_u32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svmaxv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv2i64")] + fn _svmaxv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svmaxv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmin.nxv4f32")] + fn _svmin_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmin_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmin_f32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmin_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmin.nxv2f64")] + fn _svmin_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmin_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmin_f64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmin_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv16i8")] + fn _svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmin_s8_m(pg, op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmin_s8_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmin_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv8i16")] + fn _svmin_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmin_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmin_s16_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmin_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv4i32")] + fn _svmin_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmin_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmin_s32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmin_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv2i64")] + fn _svmin_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmin_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmin_s64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmin_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv16i8")] + fn _svmin_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmin_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmin_u8_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmin_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv8i16")] + fn _svmin_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmin_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmin_u16_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmin_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv4i32")] + fn _svmin_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmin_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmin_u32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmin_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv2i64")] + fn _svmin_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmin_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmin_u64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmin_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminnm.nxv4f32")] + fn _svminnm_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminnm_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnm_f32_m(pg, op1, op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnm_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminnm.nxv2f64")] + fn _svminnm_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminnm_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnm_f64_m(pg, op1, op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnm_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmv))] +pub fn svminnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmv.nxv4f32" + )] + fn _svminnmv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svminnmv_f32(pg.sve_into(), op) } +} +#[doc = "Minimum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmv))] +pub fn svminnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmv.nxv2f64" + )] + fn _svminnmv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svminnmv_f64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminv))] +pub fn svminv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminv.nxv4f32")] + fn _svminv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svminv_f32(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminv))] +pub fn svminv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminv.nxv2f64")] + fn _svminv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svminv_f64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv16i8")] + fn _svminv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svminv_s8(pg, op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv8i16")] + fn _svminv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svminv_s16(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv4i32")] + fn _svminv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svminv_s32(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv2i64")] + fn _svminv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svminv_s64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv16i8")] + fn _svminv_u8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svminv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv8i16")] + fn _svminv_u16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svminv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv4i32")] + fn _svminv_u32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svminv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv2i64")] + fn _svminv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svminv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmla.nxv4f32")] + fn _svmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmla_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmla_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmla_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmla.nxv2f64")] + fn _svmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmla_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmla_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmla_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv16i8")] + fn _svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmla_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmla_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmla_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv8i16")] + fn _svmla_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmla_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmla_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmla_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv4i32")] + fn _svmla_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmla_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmla_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmla_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv2i64")] + fn _svmla_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmla_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmla_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmla_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmla_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmla_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmla_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmla_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmla_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmla_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmla_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmla_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmla_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmla_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmla_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmla_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))] +pub fn svmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmla.lane.nxv4f32" + )] + fn _svmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + IMM_INDEX: i32, + ) -> svfloat32_t; + } + unsafe { _svmla_lane_f32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))] +pub fn svmla_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmla.lane.nxv2f64" + )] + fn _svmla_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + IMM_INDEX: i32, + ) -> svfloat64_t; + } + unsafe { _svmla_lane_f64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmls.nxv4f32")] + fn _svmls_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmls_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmls_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmls_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmls.nxv2f64")] + fn _svmls_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmls_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmls_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmls_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv16i8")] + fn _svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmls_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmls_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmls_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv8i16")] + fn _svmls_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmls_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmls_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmls_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv4i32")] + fn _svmls_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmls_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmls_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmls_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv2i64")] + fn _svmls_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmls_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmls_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmls_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmls_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmls_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmls_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmls_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmls_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmls_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmls_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmls_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmls_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmls_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmls_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmls_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))] +pub fn svmls_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmls.lane.nxv4f32" + )] + fn _svmls_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + IMM_INDEX: i32, + ) -> svfloat32_t; + } + unsafe { _svmls_lane_f32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))] +pub fn svmls_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmls.lane.nxv2f64" + )] + fn _svmls_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + IMM_INDEX: i32, + ) -> svfloat64_t; + } + unsafe { _svmls_lane_f64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f32])"] +#[inline] +#[target_feature(enable = "sve,f32mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmmla))] +pub fn svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmmla.nxv4f32")] + fn _svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmmla_f32(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmmla))] +pub fn svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmmla.nxv2f64")] + fn _svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmmla_f64(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smmla))] +pub fn svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smmla.nxv4i32")] + fn _svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svmmla_s32(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_u32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ummla))] +pub fn svmmla_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ummla.nxv4i32")] + fn _svmmla_u32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svmmla_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmov[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svmov_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + svand_b_z(pg, op, op) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmsb.nxv4f32")] + fn _svmsb_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmsb_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmsb_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmsb_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmsb.nxv2f64")] + fn _svmsb_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmsb_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmsb_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmsb_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv16i8")] + fn _svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmsb_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmsb_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmsb_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv8i16")] + fn _svmsb_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmsb_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmsb_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmsb_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv4i32")] + fn _svmsb_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmsb_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmsb_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmsb_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv2i64")] + fn _svmsb_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmsb_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmsb_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmsb_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmsb_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmsb_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmsb_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmsb_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmsb_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmsb_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmsb_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmsb_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmsb_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmsb_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmsb_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmsb_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmul.nxv4f32")] + fn _svmul_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmul_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmul_f32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmul_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmul.nxv2f64")] + fn _svmul_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmul_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmul_f64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmul_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv16i8")] + fn _svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmul_s8_m(pg, op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmul_s8_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmul_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv8i16")] + fn _svmul_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmul_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmul_s16_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmul_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv4i32")] + fn _svmul_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmul_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmul_s32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmul_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv2i64")] + fn _svmul_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmul_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmul_s64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmul_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svmul_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmul_u8_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmul_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svmul_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmul_u16_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmul_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svmul_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmul_u32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmul_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svmul_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmul_u64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmul_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv16i8")] + fn _svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmulh_s8_m(pg, op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmulh_s8_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmulh_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv8i16")] + fn _svmulh_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmulh_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmulh_s16_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmulh_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv4i32")] + fn _svmulh_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmulh_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmulh_s32_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmulh_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv2i64")] + fn _svmulh_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmulh_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmulh_s64_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmulh_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv16i8")] + fn _svmulh_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmulh_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmulh_u8_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmulh_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv8i16")] + fn _svmulh_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmulh_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmulh_u16_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmulh_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv4i32")] + fn _svmulh_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmulh_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmulh_u32_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmulh_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv2i64")] + fn _svmulh_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmulh_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmulh_u64_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmulh_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmulx.nxv4f32")] + fn _svmulx_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmulx_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmulx_f32_m(pg, op1, op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmulx_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmulx.nxv2f64")] + fn _svmulx_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmulx_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmulx_f64_m(pg, op1, op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmulx_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Bitwise NAND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnand[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nand))] +pub fn svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nand.z.nxv16i1")] + fn _svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svnand_b_z(pg, op1, op2) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fneg.nxv4f32")] + fn _svneg_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svneg_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svneg_f32_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svneg_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fneg.nxv2f64")] + fn _svneg_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svneg_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svneg_f64_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svneg_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv16i8")] + fn _svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svneg_s8_m(inactive, pg, op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svneg_s8_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svneg_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv8i16")] + fn _svneg_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svneg_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svneg_s16_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svneg_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv4i32")] + fn _svneg_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svneg_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svneg_s32_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svneg_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv2i64")] + fn _svneg_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svneg_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svneg_s64_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svneg_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmad.nxv4f32")] + fn _svnmad_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmad_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmad_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmad_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmad.nxv2f64")] + fn _svnmad_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmad_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmad_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmad_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmla.nxv4f32")] + fn _svnmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmla_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmla_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmla_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmla.nxv2f64")] + fn _svnmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmla_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmla_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmla_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmls.nxv4f32")] + fn _svnmls_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmls_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmls_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmls_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmls.nxv2f64")] + fn _svnmls_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmls_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmls_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmls_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmsb.nxv4f32")] + fn _svnmsb_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmsb_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmsb_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmsb_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmsb.nxv2f64")] + fn _svnmsb_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmsb_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmsb_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmsb_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Bitwise NOR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnor[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nor))] +pub fn svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nor.z.nxv16i1")] + fn _svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svnor_b_z(pg, op1, op2) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + sveor_b_z(pg, op, pg) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv16i8")] + fn _svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svnot_s8_m(inactive, pg, op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svnot_s8_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svnot_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv8i16")] + fn _svnot_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svnot_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svnot_s16_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svnot_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv4i32")] + fn _svnot_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svnot_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svnot_s32_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svnot_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv2i64")] + fn _svnot_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svnot_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svnot_s64_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svnot_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svnot_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svnot_u8_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svnot_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svnot_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svnot_u16_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svnot_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svnot_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svnot_u32_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svnot_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svnot_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svnot_u64_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svnot_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Bitwise inclusive OR, inverting second argument"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorn[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orn))] +pub fn svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orn.z.nvx16i1")] + fn _svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svorn_b_z(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_b]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.z.nvx16i1")] + fn _svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svorr_b_z(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv16i8")] + fn _svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svorr_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svorr_s8_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svorr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv8i16")] + fn _svorr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svorr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svorr_s16_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svorr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv4i32")] + fn _svorr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svorr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svorr_s32_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svorr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv2i64")] + fn _svorr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svorr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svorr_s64_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svorr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svorr_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svorr_u8_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svorr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svorr_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svorr_u16_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svorr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svorr_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svorr_u32_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svorr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svorr_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svorr_u64_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svorr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv16i8")] + fn _svorv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svorv_s8(pg, op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv8i16")] + fn _svorv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svorv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv4i32")] + fn _svorv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svorv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv2i64")] + fn _svorv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svorv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svorv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svorv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svorv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svorv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Set all predicate elements to false"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfalse[_b])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svpfalse_b() -> svbool_t { + svdupq_n_b8( + false, false, false, false, false, false, false, false, false, false, false, false, false, + false, false, false, + ) +} +#[doc = "Set the first active predicate element to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfirst[_b])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pfirst))] +pub fn svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pfirst.nxv16i1")] + fn _svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svpfirst_b(pg, op) } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv16i1")] + fn _svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svpnext_b8(pg, op) } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b16(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv8i1")] + fn _svpnext_b16(pg: svbool8_t, op: svbool8_t) -> svbool8_t; + } + unsafe { _svpnext_b16(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b32(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv4i1")] + fn _svpnext_b32(pg: svbool4_t, op: svbool4_t) -> svbool4_t; + } + unsafe { _svpnext_b32(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b64(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv2i1")] + fn _svpnext_b64(pg: svbool2_t, op: svbool2_t) -> svbool2_t; + } + unsafe { _svpnext_b64(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv16i1")] + fn _svprfb(pg: svbool_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfb(pg, base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv8i1")] + fn _svprfh(pg: svbool8_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfh(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv4i1")] + fn _svprfw(pg: svbool4_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfw(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv2i1")] + fn _svprfd(pg: svbool2_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfd(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s32]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_s32offset( + pg: svbool_t, + base: *const T, + offsets: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.sxtw.index.nxv4i32" + )] + fn _svprfb_gather_s32offset( + pg: svbool4_t, + base: *const crate::ffi::c_void, + offsets: svint32_t, + op: svprfop, + ); + } + _svprfb_gather_s32offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets, + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.sxtw.index.nxv4i32" + )] + fn _svprfh_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfh_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.sxtw.index.nxv4i32" + )] + fn _svprfw_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfw_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.sxtw.index.nxv4i32" + )] + fn _svprfd_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfd_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s64]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_s64offset( + pg: svbool_t, + base: *const T, + offsets: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.index.nxv2i64" + )] + fn _svprfb_gather_s64offset( + pg: svbool2_t, + base: *const crate::ffi::c_void, + offsets: svint64_t, + op: svprfop, + ); + } + _svprfb_gather_s64offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets, + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.index.nxv2i64" + )] + fn _svprfh_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfh_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.index.nxv2i64" + )] + fn _svprfw_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfw_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.index.nxv2i64" + )] + fn _svprfd_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfd_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u32]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_u32offset( + pg: svbool_t, + base: *const T, + offsets: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.uxtw.index.nxv4i32" + )] + fn _svprfb_gather_u32offset( + pg: svbool4_t, + base: *const crate::ffi::c_void, + offsets: svint32_t, + op: svprfop, + ); + } + _svprfb_gather_u32offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets.as_signed(), + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.uxtw.index.nxv4i32" + )] + fn _svprfh_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfh_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.uxtw.index.nxv4i32" + )] + fn _svprfw_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfw_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.uxtw.index.nxv4i32" + )] + fn _svprfd_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfd_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u64]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_u64offset( + pg: svbool_t, + base: *const T, + offsets: svuint64_t, +) { + svprfb_gather_s64offset::(pg, base, offsets.as_signed()) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfh_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfw_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfd_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32" + )] + fn _svprfb_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfb_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32" + )] + fn _svprfh_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfh_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32" + )] + fn _svprfw_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfw_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32" + )] + fn _svprfd_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfd_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64" + )] + fn _svprfb_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfb_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv2i64" + )] + fn _svprfh_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfh_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv2i64" + )] + fn _svprfw_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfw_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64" + )] + fn _svprfd_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfd_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u32base]_offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u32base_offset( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32" + )] + fn _svprfb_gather_u32base_offset(pg: svbool4_t, bases: svint32_t, offset: i64, op: svprfop); + } + _svprfb_gather_u32base_offset(pg.sve_into(), bases.as_signed(), offset, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32" + )] + fn _svprfh_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfh_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(1), OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32" + )] + fn _svprfw_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfw_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(2), OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32" + )] + fn _svprfd_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfd_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(3), OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u64base]_offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u64base_offset( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64" + )] + fn _svprfb_gather_u64base_offset(pg: svbool2_t, bases: svint64_t, offset: i64, op: svprfop); + } + _svprfb_gather_u64base_offset(pg.sve_into(), bases.as_signed(), offset, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv2i64" + )] + fn _svprfh_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfh_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(1), OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv2i64" + )] + fn _svprfw_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfw_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(2), OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64" + )] + fn _svprfd_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfd_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(3), OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfb::(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfh::(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfw::(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfd::(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Test whether any active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_any)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_any(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.any.nxv16i1" + )] + fn _svptest_any(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_any(pg, op) } +} +#[doc = "Test whether first active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_first)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_first(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.first.nxv16i1" + )] + fn _svptest_first(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_first(pg, op) } +} +#[doc = "Test whether last active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_last)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_last(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.last.nxv16i1" + )] + fn _svptest_last(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_last(pg, op) } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b8() -> svbool_t { + svptrue_pat_b8::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b16() -> svbool_t { + svptrue_pat_b16::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b32() -> svbool_t { + svptrue_pat_b32::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b64() -> svbool_t { + svptrue_pat_b64::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b8() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv16i1")] + fn _svptrue_pat_b8(pattern: svpattern) -> svbool_t; + } + unsafe { _svptrue_pat_b8(PATTERN) } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b16() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv8i1")] + fn _svptrue_pat_b16(pattern: svpattern) -> svbool8_t; + } + unsafe { _svptrue_pat_b16(PATTERN).sve_into() } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b32() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv4i1")] + fn _svptrue_pat_b32(pattern: svpattern) -> svbool4_t; + } + unsafe { _svptrue_pat_b32(PATTERN).sve_into() } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b64() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv2i1")] + fn _svptrue_pat_b64(pattern: svpattern) -> svbool2_t; + } + unsafe { _svptrue_pat_b64(PATTERN).sve_into() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv16i8" + )] + fn _svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_s8(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv8i16" + )] + fn _svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_s16(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv4i32" + )] + fn _svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_s32(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv2i64" + )] + fn _svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_s64(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv16i8" + )] + fn _svqadd_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv8i16" + )] + fn _svqadd_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv4i32" + )] + fn _svqadd_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv2i64" + )] + fn _svqadd_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_s32(op: i32) -> i32 { + svqdecb_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_s32(op: i32) -> i32 { + svqdech_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_s32(op: i32) -> i32 { + svqdecw_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_s32(op: i32) -> i32 { + svqdecd_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_s64(op: i64) -> i64 { + svqdecb_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_s64(op: i64) -> i64 { + svqdech_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_s64(op: i64) -> i64 { + svqdecw_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_s64(op: i64) -> i64 { + svqdecd_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_u32(op: u32) -> u32 { + svqdecb_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_u32(op: u32) -> u32 { + svqdech_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_u32(op: u32) -> u32 { + svqdecw_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_u32(op: u32) -> u32 { + svqdecd_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_u64(op: u64) -> u64 { + svqdecb_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_u64(op: u64) -> u64 { + svqdech_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_u64(op: u64) -> u64 { + svqdecw_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_u64(op: u64) -> u64 { + svqdecd_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecb.n32")] + fn _svqdecb_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecb_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.n32")] + fn _svqdech_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdech_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.n32")] + fn _svqdecw_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecw_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.n32")] + fn _svqdecd_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecd_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecb.n64")] + fn _svqdecb_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecb_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.n64")] + fn _svqdech_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdech_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.n64")] + fn _svqdecw_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecw_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.n64")] + fn _svqdecd_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecd_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecb.n32")] + fn _svqdecb_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecb_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.n32")] + fn _svqdech_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdech_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.n32")] + fn _svqdecw_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecw_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.n32")] + fn _svqdecd_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecd_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecb.n64")] + fn _svqdecb_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecb_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.n64")] + fn _svqdech_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdech_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.n64")] + fn _svqdecw_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecw_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.n64")] + fn _svqdecd_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecd_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_s16( + op: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.nxv8i16")] + fn _svqdech_pat_s16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqdech_pat_s16(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_s32( + op: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.nxv4i32")] + fn _svqdecw_pat_s32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqdecw_pat_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_s64( + op: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.nxv2i64")] + fn _svqdecd_pat_s64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqdecd_pat_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_u16( + op: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.nxv8i16")] + fn _svqdech_pat_u16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqdech_pat_u16(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_u32( + op: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.nxv4i32")] + fn _svqdecw_pat_u32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqdecw_pat_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_u64( + op: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.nxv2i64")] + fn _svqdecd_pat_u64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqdecd_pat_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_s16(op: svint16_t) -> svint16_t { + svqdech_pat_s16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_s32(op: svint32_t) -> svint32_t { + svqdecw_pat_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_s64(op: svint64_t) -> svint64_t { + svqdecd_pat_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_u16(op: svuint16_t) -> svuint16_t { + svqdech_pat_u16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_u32(op: svuint32_t) -> svuint32_t { + svqdecw_pat_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_u64(op: svuint64_t) -> svuint64_t { + svqdecd_pat_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv16i1" + )] + fn _svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqdecp_n_s32_b8(op, pg) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b16(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv8i1" + )] + fn _svqdecp_n_s32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqdecp_n_s32_b16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b32(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv4i1" + )] + fn _svqdecp_n_s32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqdecp_n_s32_b32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b64(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv2i1" + )] + fn _svqdecp_n_s32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqdecp_n_s32_b64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv16i1" + )] + fn _svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqdecp_n_s64_b8(op, pg) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b16(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv8i1" + )] + fn _svqdecp_n_s64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqdecp_n_s64_b16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b32(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv4i1" + )] + fn _svqdecp_n_s64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqdecp_n_s64_b32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b64(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv2i1" + )] + fn _svqdecp_n_s64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqdecp_n_s64_b64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b8(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv16i1" + )] + fn _svqdecp_n_u32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqdecp_n_u32_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b16(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv8i1" + )] + fn _svqdecp_n_u32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqdecp_n_u32_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b32(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv4i1" + )] + fn _svqdecp_n_u32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqdecp_n_u32_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b64(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv2i1" + )] + fn _svqdecp_n_u32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqdecp_n_u32_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b8(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv16i1" + )] + fn _svqdecp_n_u64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqdecp_n_u64_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b16(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv8i1" + )] + fn _svqdecp_n_u64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqdecp_n_u64_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b32(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv4i1" + )] + fn _svqdecp_n_u64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqdecp_n_u64_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b64(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv2i1" + )] + fn _svqdecp_n_u64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqdecp_n_u64_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s16(op: svint16_t, pg: svbool_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv8i16")] + fn _svqdecp_s16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqdecp_s16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s32(op: svint32_t, pg: svbool_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv4i32")] + fn _svqdecp_s32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqdecp_s32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s64(op: svint64_t, pg: svbool_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv2i64")] + fn _svqdecp_s64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqdecp_s64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv8i16")] + fn _svqdecp_u16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqdecp_u16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv4i32")] + fn _svqdecp_u32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqdecp_u32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv2i64")] + fn _svqdecp_u64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqdecp_u64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_s32(op: i32) -> i32 { + svqincb_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_s32(op: i32) -> i32 { + svqinch_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_s32(op: i32) -> i32 { + svqincw_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_s32(op: i32) -> i32 { + svqincd_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_s64(op: i64) -> i64 { + svqincb_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_s64(op: i64) -> i64 { + svqinch_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_s64(op: i64) -> i64 { + svqincw_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_s64(op: i64) -> i64 { + svqincd_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_u32(op: u32) -> u32 { + svqincb_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_u32(op: u32) -> u32 { + svqinch_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_u32(op: u32) -> u32 { + svqincw_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_u32(op: u32) -> u32 { + svqincd_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_u64(op: u64) -> u64 { + svqincb_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_u64(op: u64) -> u64 { + svqinch_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_u64(op: u64) -> u64 { + svqincw_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_u64(op: u64) -> u64 { + svqincd_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincb.n32")] + fn _svqincb_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincb_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.n32")] + fn _svqinch_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqinch_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.n32")] + fn _svqincw_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincw_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.n32")] + fn _svqincd_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincd_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincb.n64")] + fn _svqincb_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincb_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.n64")] + fn _svqinch_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqinch_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.n64")] + fn _svqincw_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincw_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.n64")] + fn _svqincd_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincd_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincb.n32")] + fn _svqincb_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincb_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.n32")] + fn _svqinch_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqinch_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.n32")] + fn _svqincw_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincw_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.n32")] + fn _svqincd_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincd_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincb.n64")] + fn _svqincb_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincb_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.n64")] + fn _svqinch_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqinch_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.n64")] + fn _svqincw_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincw_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.n64")] + fn _svqincd_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincd_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_s16( + op: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.nxv8i16")] + fn _svqinch_pat_s16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqinch_pat_s16(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_s32( + op: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.nxv4i32")] + fn _svqincw_pat_s32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqincw_pat_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_s64( + op: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.nxv2i64")] + fn _svqincd_pat_s64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqincd_pat_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_u16( + op: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.nxv8i16")] + fn _svqinch_pat_u16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqinch_pat_u16(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_u32( + op: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.nxv4i32")] + fn _svqincw_pat_u32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqincw_pat_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_u64( + op: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.nxv2i64")] + fn _svqincd_pat_u64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqincd_pat_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_s16(op: svint16_t) -> svint16_t { + svqinch_pat_s16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_s32(op: svint32_t) -> svint32_t { + svqincw_pat_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_s64(op: svint64_t) -> svint64_t { + svqincd_pat_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_u16(op: svuint16_t) -> svuint16_t { + svqinch_pat_u16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_u32(op: svuint32_t) -> svuint32_t { + svqincw_pat_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_u64(op: svuint64_t) -> svuint64_t { + svqincd_pat_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv16i1" + )] + fn _svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqincp_n_s32_b8(op, pg) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b16(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv8i1" + )] + fn _svqincp_n_s32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqincp_n_s32_b16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b32(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv4i1" + )] + fn _svqincp_n_s32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqincp_n_s32_b32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b64(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv2i1" + )] + fn _svqincp_n_s32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqincp_n_s32_b64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv16i1" + )] + fn _svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqincp_n_s64_b8(op, pg) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b16(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv8i1" + )] + fn _svqincp_n_s64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqincp_n_s64_b16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b32(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv4i1" + )] + fn _svqincp_n_s64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqincp_n_s64_b32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b64(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv2i1" + )] + fn _svqincp_n_s64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqincp_n_s64_b64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b8(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv16i1" + )] + fn _svqincp_n_u32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqincp_n_u32_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b16(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv8i1" + )] + fn _svqincp_n_u32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqincp_n_u32_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b32(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv4i1" + )] + fn _svqincp_n_u32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqincp_n_u32_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b64(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv2i1" + )] + fn _svqincp_n_u32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqincp_n_u32_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b8(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv16i1" + )] + fn _svqincp_n_u64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqincp_n_u64_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b16(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv8i1" + )] + fn _svqincp_n_u64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqincp_n_u64_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b32(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv4i1" + )] + fn _svqincp_n_u64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqincp_n_u64_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b64(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv2i1" + )] + fn _svqincp_n_u64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqincp_n_u64_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s16(op: svint16_t, pg: svbool_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv8i16")] + fn _svqincp_s16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqincp_s16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s32(op: svint32_t, pg: svbool_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv4i32")] + fn _svqincp_s32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqincp_s32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s64(op: svint64_t, pg: svbool_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv2i64")] + fn _svqincp_s64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqincp_s64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv8i16")] + fn _svqincp_u16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqincp_u16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv4i32")] + fn _svqincp_u32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqincp_u32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv2i64")] + fn _svqincp_u64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqincp_u64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv16i8" + )] + fn _svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_s8(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv8i16" + )] + fn _svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_s16(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv4i32" + )] + fn _svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_s32(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv2i64" + )] + fn _svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_s64(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv16i8" + )] + fn _svqsub_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv8i16" + )] + fn _svqsub_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv4i32" + )] + fn _svqsub_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv2i64" + )] + fn _svqsub_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv16i8")] + fn _svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svrbit_s8_m(inactive, pg, op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svrbit_s8_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svrbit_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv8i16")] + fn _svrbit_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svrbit_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svrbit_s16_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svrbit_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv4i32")] + fn _svrbit_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrbit_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrbit_s32_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrbit_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv2i64")] + fn _svrbit_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrbit_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrbit_s64_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrbit_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svrbit_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svrbit_u8_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svrbit_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svrbit_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrbit_u16_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrbit_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrbit_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrbit_u32_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrbit_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrbit_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrbit_u64_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrbit_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Read FFR, returning predicate of succesfully loaded elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdffr))] +pub fn svrdffr() -> svbool_t { + svrdffr_z(svptrue_b8()) +} +#[doc = "Read FFR, returning predicate of succesfully loaded elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdffr))] +pub fn svrdffr_z(pg: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rdffr.z")] + fn _svrdffr_z(pg: svbool_t) -> svbool_t; + } + unsafe { _svrdffr_z(pg) } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpe))] +pub fn svrecpe_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpe.x.nxv4f32" + )] + fn _svrecpe_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecpe_f32(op) } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpe))] +pub fn svrecpe_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpe.x.nxv2f64" + )] + fn _svrecpe_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecpe_f64(op) } +} +#[doc = "Reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecps))] +pub fn svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecps.x.nxv4f32" + )] + fn _svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecps_f32(op1, op2) } +} +#[doc = "Reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecps))] +pub fn svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecps.x.nxv2f64" + )] + fn _svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecps_f64(op1, op2) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpx.x.nxv4f32" + )] + fn _svrecpx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecpx_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrecpx_f32_m(op, pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrecpx_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpx.x.nxv2f64" + )] + fn _svrecpx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecpx_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrecpx_f64_m(op, pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrecpx_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_f32(op: svfloat32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_f64(op: svfloat64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s8(op: svint8_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s16(op: svint16_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s32(op: svint32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s64(op: svint64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u8(op: svuint8_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u16(op: svuint16_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u32(op: svuint32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u64(op: svuint64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_f32(op: svfloat32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_f64(op: svfloat64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s8(op: svint8_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s16(op: svint16_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s32(op: svint32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s64(op: svint64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u8(op: svuint8_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u16(op: svuint16_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u32(op: svuint32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u64(op: svuint64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_f32(op: svfloat32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_f64(op: svfloat64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s8(op: svint8_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s16(op: svint16_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s32(op: svint32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s64(op: svint64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u8(op: svuint8_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u16(op: svuint16_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u32(op: svuint32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u64(op: svuint64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_f32(op: svfloat32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_f64(op: svfloat64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s8(op: svint8_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s16(op: svint16_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s32(op: svint32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s64(op: svint64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u8(op: svuint8_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u16(op: svuint16_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u32(op: svuint32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u64(op: svuint64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_f32(op: svfloat32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_f64(op: svfloat64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s8(op: svint8_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s16(op: svint16_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s32(op: svint32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s64(op: svint64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u8(op: svuint8_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u16(op: svuint16_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u32(op: svuint32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u64(op: svuint64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_f32(op: svfloat32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_f64(op: svfloat64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s8(op: svint8_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s16(op: svint16_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s32(op: svint32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s64(op: svint64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u8(op: svuint8_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u16(op: svuint16_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u32(op: svuint32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u64(op: svuint64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_f32(op: svfloat32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_f64(op: svfloat64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s8(op: svint8_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s16(op: svint16_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s32(op: svint32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s64(op: svint64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u8(op: svuint8_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u16(op: svuint16_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u32(op: svuint32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u64(op: svuint64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_f32(op: svfloat32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_f64(op: svfloat64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s8(op: svint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s16(op: svint16_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s32(op: svint32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s64(op: svint64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u8(op: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u16(op: svuint16_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u32(op: svuint32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u64(op: svuint64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_f32(op: svfloat32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_f64(op: svfloat64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s8(op: svint8_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s16(op: svint16_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s32(op: svint32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s64(op: svint64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u8(op: svuint8_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u16(op: svuint16_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u32(op: svuint32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u64(op: svuint64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_f32(op: svfloat32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_f64(op: svfloat64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s8(op: svint8_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s16(op: svint16_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s32(op: svint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s64(op: svint64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u8(op: svuint8_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u16(op: svuint16_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u32(op: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u64(op: svuint64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b8(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv16i1")] + fn _svrev_b8(op: svbool_t) -> svbool_t; + } + unsafe { _svrev_b8(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b16(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv8i1")] + fn _svrev_b16(op: svbool8_t) -> svbool8_t; + } + unsafe { _svrev_b16(op.sve_into()).sve_into() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b32(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4i1")] + fn _svrev_b32(op: svbool4_t) -> svbool4_t; + } + unsafe { _svrev_b32(op.sve_into()).sve_into() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b64(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2i1")] + fn _svrev_b64(op: svbool2_t) -> svbool2_t; + } + unsafe { _svrev_b64(op.sve_into()).sve_into() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4f32")] + fn _svrev_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrev_f32(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2f64")] + fn _svrev_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrev_f64(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s8(op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv16i8")] + fn _svrev_s8(op: svint8_t) -> svint8_t; + } + unsafe { _svrev_s8(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s16(op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv8i16")] + fn _svrev_s16(op: svint16_t) -> svint16_t; + } + unsafe { _svrev_s16(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s32(op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv4i32")] + fn _svrev_s32(op: svint32_t) -> svint32_t; + } + unsafe { _svrev_s32(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s64(op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.vector.reverse.nxv2i64")] + fn _svrev_s64(op: svint64_t) -> svint64_t; + } + unsafe { _svrev_s64(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u8(op: svuint8_t) -> svuint8_t { + unsafe { svrev_s8(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u16(op: svuint16_t) -> svuint16_t { + unsafe { svrev_s16(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u32(op: svuint32_t) -> svuint32_t { + unsafe { svrev_s32(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u64(op: svuint64_t) -> svuint64_t { + unsafe { svrev_s64(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv8i16")] + fn _svrevb_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svrevb_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svrevb_s16_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svrevb_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv4i32")] + fn _svrevb_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrevb_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevb_s32_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevb_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv2i64")] + fn _svrevb_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevb_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevb_s64_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevb_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svrevb_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrevb_u16_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrevb_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrevb_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevb_u32_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevb_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevb_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevb_u64_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevb_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revh.nxv4i32")] + fn _svrevh_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrevh_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevh_s32_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevh_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revh.nxv2i64")] + fn _svrevh_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevh_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevh_s64_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevh_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrevh_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevh_u32_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevh_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevh_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevh_u64_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevh_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revw.nxv2i64")] + fn _svrevw_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevw_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevw_s64_m(op, pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevw_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevw_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevw_u64_m(op, pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevw_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinta.nxv4f32")] + fn _svrinta_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrinta_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinta_f32_m(op, pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinta_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinta.nxv2f64")] + fn _svrinta_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrinta_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinta_f64_m(op, pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinta_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinti.nxv4f32")] + fn _svrinti_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrinti_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinti_f32_m(op, pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinti_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinti.nxv2f64")] + fn _svrinti_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrinti_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinti_f64_m(op, pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinti_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintm.nxv4f32")] + fn _svrintm_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintm_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintm_f32_m(op, pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintm_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintm.nxv2f64")] + fn _svrintm_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintm_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintm_f64_m(op, pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintm_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintn.nxv4f32")] + fn _svrintn_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintn_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintn_f32_m(op, pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintn_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintn.nxv2f64")] + fn _svrintn_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintn_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintn_f64_m(op, pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintn_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintp.nxv4f32")] + fn _svrintp_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintp_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintp_f32_m(op, pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintp_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintp.nxv2f64")] + fn _svrintp_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintp_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintp_f64_m(op, pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintp_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintx.nxv4f32")] + fn _svrintx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintx_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintx_f32_m(op, pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintx_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintx.nxv2f64")] + fn _svrintx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintx_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintx_f64_m(op, pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintx_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintz.nxv4f32")] + fn _svrintz_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintz_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintz_f32_m(op, pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintz_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintz.nxv2f64")] + fn _svrintz_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintz_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintz_f64_m(op, pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintz_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrte))] +pub fn svrsqrte_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrte.x.nxv4f32" + )] + fn _svrsqrte_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrsqrte_f32(op) } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrte))] +pub fn svrsqrte_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrte.x.nxv2f64" + )] + fn _svrsqrte_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrsqrte_f64(op) } +} +#[doc = "Reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrts))] +pub fn svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrts.x.nxv4f32" + )] + fn _svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrsqrts_f32(op1, op2) } +} +#[doc = "Reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrts))] +pub fn svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrts.x.nxv2f64" + )] + fn _svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrsqrts_f64(op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fscale.nxv4f32")] + fn _svscale_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svscale_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + svscale_f32_m(pg, op1, op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + svscale_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fscale.nxv2f64")] + fn _svscale_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svscale_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + svscale_f64_m(pg, op1, op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + svscale_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_b])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_b(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe { simd_select(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe { simd_select::(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { simd_select::(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_f32(tuple: svfloat32x2_t, x: svfloat32_t) -> svfloat32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_f64(tuple: svfloat64x2_t, x: svfloat64_t) -> svfloat64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s8(tuple: svint8x2_t, x: svint8_t) -> svint8x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s16(tuple: svint16x2_t, x: svint16_t) -> svint16x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s32(tuple: svint32x2_t, x: svint32_t) -> svint32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s64(tuple: svint64x2_t, x: svint64_t) -> svint64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u8(tuple: svuint8x2_t, x: svuint8_t) -> svuint8x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u16(tuple: svuint16x2_t, x: svuint16_t) -> svuint16x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u32(tuple: svuint32x2_t, x: svuint32_t) -> svuint32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u64(tuple: svuint64x2_t, x: svuint64_t) -> svuint64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_f32(tuple: svfloat32x3_t, x: svfloat32_t) -> svfloat32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_f64(tuple: svfloat64x3_t, x: svfloat64_t) -> svfloat64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s8(tuple: svint8x3_t, x: svint8_t) -> svint8x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s16(tuple: svint16x3_t, x: svint16_t) -> svint16x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s32(tuple: svint32x3_t, x: svint32_t) -> svint32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s64(tuple: svint64x3_t, x: svint64_t) -> svint64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u8(tuple: svuint8x3_t, x: svuint8_t) -> svuint8x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u16(tuple: svuint16x3_t, x: svuint16_t) -> svuint16x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u32(tuple: svuint32x3_t, x: svuint32_t) -> svuint32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u64(tuple: svuint64x3_t, x: svuint64_t) -> svuint64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_f32(tuple: svfloat32x4_t, x: svfloat32_t) -> svfloat32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_f64(tuple: svfloat64x4_t, x: svfloat64_t) -> svfloat64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s8(tuple: svint8x4_t, x: svint8_t) -> svint8x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s16(tuple: svint16x4_t, x: svint16_t) -> svint16x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s32(tuple: svint32x4_t, x: svint32_t) -> svint32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s64(tuple: svint64x4_t, x: svint64_t) -> svint64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u8(tuple: svuint8x4_t, x: svuint8_t) -> svuint8x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u16(tuple: svuint16x4_t, x: svuint16_t) -> svuint16x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u32(tuple: svuint32x4_t, x: svuint32_t) -> svuint32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u64(tuple: svuint64x4_t, x: svuint64_t) -> svuint64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Initialize the first-fault register to all-true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsetffr)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(setffr))] +pub fn svsetffr() { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.setffr")] + fn _svsetffr(); + } + unsafe { _svsetffr() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv4f32")] + fn _svsplice_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsplice_f32(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv2f64")] + fn _svsplice_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsplice_f64(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv16i8")] + fn _svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsplice_s8(pg, op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv8i16")] + fn _svsplice_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsplice_s16(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv4i32")] + fn _svsplice_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsplice_s32(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv2i64")] + fn _svsplice_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsplice_s64(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsplice_s8(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsplice_s16(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsplice_s32(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsplice_s64(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsqrt.nxv4f32")] + fn _svsqrt_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsqrt_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svsqrt_f32_m(op, pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svsqrt_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsqrt.nxv2f64")] + fn _svsqrt_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsqrt_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svsqrt_f64_m(op, pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svsqrt_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4f32")] + fn _svst1_f32(data: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svst1_f32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2f64")] + fn _svst1_f64(data: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svst1_f64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv16i8")] + fn _svst1_s8(data: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst1_s8(data, pg, base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv8i16")] + fn _svst1_s16(data: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svst1_s16(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i32")] + fn _svst1_s32(data: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svst1_s32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i64")] + fn _svst1_s64(data: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svst1_s64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) { + svst1_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) { + svst1_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) { + svst1_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) { + svst1_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_f32( + pg: svbool_t, + base: *mut f32, + indices: svint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32" + )] + fn _svst1_scatter_s32index_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + indices: svint32_t, + ); + } + _svst1_scatter_s32index_f32(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_s32( + pg: svbool_t, + base: *mut i32, + indices: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32" + )] + fn _svst1_scatter_s32index_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + indices: svint32_t, + ); + } + _svst1_scatter_s32index_s32(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_u32( + pg: svbool_t, + base: *mut u32, + indices: svint32_t, + data: svuint32_t, +) { + svst1_scatter_s32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2f64" + )] + fn _svst1_scatter_s64index_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + indices: svint64_t, + ); + } + _svst1_scatter_s64index_f64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i64" + )] + fn _svst1_scatter_s64index_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + indices: svint64_t, + ); + } + _svst1_scatter_s64index_s64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svint64_t, + data: svuint64_t, +) { + svst1_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_f32( + pg: svbool_t, + base: *mut f32, + indices: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32" + )] + fn _svst1_scatter_u32index_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + indices: svint32_t, + ); + } + _svst1_scatter_u32index_f32(data, pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_s32( + pg: svbool_t, + base: *mut i32, + indices: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32" + )] + fn _svst1_scatter_u32index_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + indices: svint32_t, + ); + } + _svst1_scatter_u32index_s32(data, pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_u32( + pg: svbool_t, + base: *mut u32, + indices: svuint32_t, + data: svuint32_t, +) { + svst1_scatter_u32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svuint64_t, + data: svfloat64_t, +) { + svst1_scatter_s64index_f64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svuint64_t, + data: svint64_t, +) { + svst1_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svuint64_t, + data: svuint64_t, +) { + svst1_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4f32" + )] + fn _svst1_scatter_s32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svst1_scatter_s32offset_f32(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i32" + )] + fn _svst1_scatter_s32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svst1_scatter_s32offset_s32(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svint32_t, + data: svuint32_t, +) { + svst1_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2f64" + )] + fn _svst1_scatter_s64offset_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + offsets: svint64_t, + ); + } + _svst1_scatter_s64offset_f64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i64" + )] + fn _svst1_scatter_s64offset_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + offsets: svint64_t, + ); + } + _svst1_scatter_s64offset_s64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svint64_t, + data: svuint64_t, +) { + svst1_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4f32" + )] + fn _svst1_scatter_u32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svst1_scatter_u32offset_f32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i32" + )] + fn _svst1_scatter_u32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svst1_scatter_u32offset_s32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svuint64_t, + data: svfloat64_t, +) { + svst1_scatter_s64offset_f64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svuint64_t, + data: svint64_t, +) { + svst1_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: svfloat32_t) { + svst1_scatter_u32base_offset_f32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: svfloat64_t) { + svst1_scatter_u64base_offset_f64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svfloat32_t, +) { + svst1_scatter_u32base_offset_f32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svst1_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svst1_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svfloat64_t, +) { + svst1_scatter_u64base_offset_f64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svst1_scatter_u32base_offset_f32( + data: svfloat32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1_scatter_u32base_offset_f32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svst1_scatter_u32base_offset_s32( + data: svint32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1_scatter_u32base_offset_s32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svst1_scatter_u64base_offset_f64( + data: svfloat64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1_scatter_u64base_offset_f64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svst1_scatter_u64base_offset_s64( + data: svint64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1_scatter_u64base_offset_s64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32_t) { + svst1_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64_t) { + svst1_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8_t) { + svst1_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16_t) { + svst1_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32_t) { + svst1_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64_t) { + svst1_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8_t) { + svst1_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16_t) { + svst1_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32_t) { + svst1_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64_t) { + svst1_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s16(pg: svbool_t, base: *mut i8, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv8i8")] + fn _svst1b_s16(data: nxv8i8, pg: svbool8_t, ptr: *mut i8); + } + _svst1b_s16( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s32(pg: svbool_t, base: *mut i8, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i8")] + fn _svst1b_s32(data: nxv4i8, pg: svbool4_t, ptr: *mut i8); + } + _svst1b_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_s32(pg: svbool_t, base: *mut i16, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i16")] + fn _svst1h_s32(data: nxv4i16, pg: svbool4_t, ptr: *mut i16); + } + _svst1h_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s64(pg: svbool_t, base: *mut i8, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i8")] + fn _svst1b_s64(data: nxv2i8, pg: svbool2_t, ptr: *mut i8); + } + _svst1b_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_s64(pg: svbool_t, base: *mut i16, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i16")] + fn _svst1h_s64(data: nxv2i16, pg: svbool2_t, ptr: *mut i16); + } + _svst1h_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_s64(pg: svbool_t, base: *mut i32, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i32")] + fn _svst1w_s64(data: nxv2i32, pg: svbool2_t, ptr: *mut i32); + } + _svst1w_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u16(pg: svbool_t, base: *mut u8, data: svuint16_t) { + svst1b_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u32(pg: svbool_t, base: *mut u8, data: svuint32_t) { + svst1b_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_u32(pg: svbool_t, base: *mut u16, data: svuint32_t) { + svst1h_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u64(pg: svbool_t, base: *mut u8, data: svuint64_t) { + svst1b_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_u64(pg: svbool_t, base: *mut u16, data: svuint64_t) { + svst1h_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_u64(pg: svbool_t, base: *mut u32, data: svuint64_t) { + svst1w_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i8" + )] + fn _svst1b_scatter_s32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svst1b_scatter_s32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i16" + )] + fn _svst1h_scatter_s32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svst1h_scatter_s32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svint32_t, + data: svuint32_t, +) { + svst1b_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svint32_t, + data: svuint32_t, +) { + svst1h_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i8" + )] + fn _svst1b_scatter_s64offset_s64( + data: nxv2i8, + pg: svbool2_t, + base: *mut i8, + offsets: svint64_t, + ); + } + _svst1b_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i16" + )] + fn _svst1h_scatter_s64offset_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + offsets: svint64_t, + ); + } + _svst1h_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i32" + )] + fn _svst1w_scatter_s64offset_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + offsets: svint64_t, + ); + } + _svst1w_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svint64_t, + data: svuint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i8" + )] + fn _svst1b_scatter_u32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svst1b_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i16" + )] + fn _svst1h_scatter_u32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svst1h_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1b_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1h_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svuint64_t, + data: svint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svuint64_t, + data: svint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svuint64_t, + data: svint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svst1b_scatter_u32base_offset_s32( + data: nxv4i8, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1b_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svst1h_scatter_u32base_offset_s32( + data: nxv4i16, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1h_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1b_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1h_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svst1b_scatter_u64base_offset_s64( + data: nxv2i8, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1b_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svst1h_scatter_u64base_offset_s64( + data: nxv2i16, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1h_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svst1w_scatter_u64base_offset_s64( + data: nxv2i32, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1w_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1b_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1h_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1w_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1b_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1h_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1b_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1h_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1b_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1h_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1w_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1b_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1h_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1w_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s16(pg: svbool_t, base: *mut i8, vnum: i64, data: svint16_t) { + svst1b_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s32(pg: svbool_t, base: *mut i8, vnum: i64, data: svint32_t) { + svst1b_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_s32(pg: svbool_t, base: *mut i16, vnum: i64, data: svint32_t) { + svst1h_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s64(pg: svbool_t, base: *mut i8, vnum: i64, data: svint64_t) { + svst1b_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_s64(pg: svbool_t, base: *mut i16, vnum: i64, data: svint64_t) { + svst1h_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_vnum_s64(pg: svbool_t, base: *mut i32, vnum: i64, data: svint64_t) { + svst1w_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u16(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint16_t) { + svst1b_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u32(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint32_t) { + svst1b_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_u32(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint32_t) { + svst1h_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u64(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint64_t) { + svst1b_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_u64(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint64_t) { + svst1h_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_vnum_u64(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint64_t) { + svst1w_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32index_s32( + pg: svbool_t, + base: *mut i16, + indices: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16" + )] + fn _svst1h_scatter_s32index_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + indices: svint32_t, + ); + } + _svst1h_scatter_s32index_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32index_u32( + pg: svbool_t, + base: *mut u16, + indices: svint32_t, + data: svuint32_t, +) { + svst1h_scatter_s32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i16" + )] + fn _svst1h_scatter_s64index_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + indices: svint64_t, + ); + } + _svst1h_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i32" + )] + fn _svst1w_scatter_s64index_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + indices: svint64_t, + ); + } + _svst1w_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32index_s32( + pg: svbool_t, + base: *mut i16, + indices: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16" + )] + fn _svst1h_scatter_u32index_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + indices: svint32_t, + ); + } + _svst1h_scatter_u32index_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32index_u32( + pg: svbool_t, + base: *mut u16, + indices: svuint32_t, + data: svuint32_t, +) { + svst1h_scatter_u32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svuint64_t, + data: svint64_t, +) { + svst1h_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svuint64_t, + data: svint64_t, +) { + svst1w_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svuint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svuint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svst1h_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svst1h_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1h_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1w_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1h_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1w_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_f32(pg: svbool_t, base: *mut f32, data: svfloat32x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv4f32")] + fn _svst2_f32(data0: svfloat32_t, data1: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svst2_f32( + svget2_f32::<0>(data), + svget2_f32::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_f64(pg: svbool_t, base: *mut f64, data: svfloat64x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv2f64")] + fn _svst2_f64(data0: svfloat64_t, data1: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svst2_f64( + svget2_f64::<0>(data), + svget2_f64::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_s8(pg: svbool_t, base: *mut i8, data: svint8x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv16i8")] + fn _svst2_s8(data0: svint8_t, data1: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst2_s8(svget2_s8::<0>(data), svget2_s8::<1>(data), pg, base) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_s16(pg: svbool_t, base: *mut i16, data: svint16x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv8i16")] + fn _svst2_s16(data0: svint16_t, data1: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svst2_s16( + svget2_s16::<0>(data), + svget2_s16::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_s32(pg: svbool_t, base: *mut i32, data: svint32x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv4i32")] + fn _svst2_s32(data0: svint32_t, data1: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svst2_s32( + svget2_s32::<0>(data), + svget2_s32::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_s64(pg: svbool_t, base: *mut i64, data: svint64x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv2i64")] + fn _svst2_s64(data0: svint64_t, data1: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svst2_s64( + svget2_s64::<0>(data), + svget2_s64::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_u8(pg: svbool_t, base: *mut u8, data: svuint8x2_t) { + svst2_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_u16(pg: svbool_t, base: *mut u16, data: svuint16x2_t) { + svst2_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_u32(pg: svbool_t, base: *mut u32, data: svuint32x2_t) { + svst2_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_u64(pg: svbool_t, base: *mut u64, data: svuint64x2_t) { + svst2_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x2_t) { + svst2_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x2_t) { + svst2_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x2_t) { + svst2_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x2_t) { + svst2_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x2_t) { + svst2_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x2_t) { + svst2_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x2_t) { + svst2_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x2_t) { + svst2_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x2_t) { + svst2_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x2_t) { + svst2_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_f32(pg: svbool_t, base: *mut f32, data: svfloat32x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv4f32")] + fn _svst3_f32( + data0: svfloat32_t, + data1: svfloat32_t, + data2: svfloat32_t, + pg: svbool4_t, + ptr: *mut f32, + ); + } + _svst3_f32( + svget3_f32::<0>(data), + svget3_f32::<1>(data), + svget3_f32::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_f64(pg: svbool_t, base: *mut f64, data: svfloat64x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv2f64")] + fn _svst3_f64( + data0: svfloat64_t, + data1: svfloat64_t, + data2: svfloat64_t, + pg: svbool2_t, + ptr: *mut f64, + ); + } + _svst3_f64( + svget3_f64::<0>(data), + svget3_f64::<1>(data), + svget3_f64::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_s8(pg: svbool_t, base: *mut i8, data: svint8x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv16i8")] + fn _svst3_s8(data0: svint8_t, data1: svint8_t, data2: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst3_s8( + svget3_s8::<0>(data), + svget3_s8::<1>(data), + svget3_s8::<2>(data), + pg, + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_s16(pg: svbool_t, base: *mut i16, data: svint16x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv8i16")] + fn _svst3_s16( + data0: svint16_t, + data1: svint16_t, + data2: svint16_t, + pg: svbool8_t, + ptr: *mut i16, + ); + } + _svst3_s16( + svget3_s16::<0>(data), + svget3_s16::<1>(data), + svget3_s16::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_s32(pg: svbool_t, base: *mut i32, data: svint32x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv4i32")] + fn _svst3_s32( + data0: svint32_t, + data1: svint32_t, + data2: svint32_t, + pg: svbool4_t, + ptr: *mut i32, + ); + } + _svst3_s32( + svget3_s32::<0>(data), + svget3_s32::<1>(data), + svget3_s32::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_s64(pg: svbool_t, base: *mut i64, data: svint64x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv2i64")] + fn _svst3_s64( + data0: svint64_t, + data1: svint64_t, + data2: svint64_t, + pg: svbool2_t, + ptr: *mut i64, + ); + } + _svst3_s64( + svget3_s64::<0>(data), + svget3_s64::<1>(data), + svget3_s64::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_u8(pg: svbool_t, base: *mut u8, data: svuint8x3_t) { + svst3_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_u16(pg: svbool_t, base: *mut u16, data: svuint16x3_t) { + svst3_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_u32(pg: svbool_t, base: *mut u32, data: svuint32x3_t) { + svst3_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_u64(pg: svbool_t, base: *mut u64, data: svuint64x3_t) { + svst3_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x3_t) { + svst3_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x3_t) { + svst3_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x3_t) { + svst3_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x3_t) { + svst3_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x3_t) { + svst3_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x3_t) { + svst3_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x3_t) { + svst3_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x3_t) { + svst3_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x3_t) { + svst3_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x3_t) { + svst3_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_f32(pg: svbool_t, base: *mut f32, data: svfloat32x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv4f32")] + fn _svst4_f32( + data0: svfloat32_t, + data1: svfloat32_t, + data2: svfloat32_t, + data3: svfloat32_t, + pg: svbool4_t, + ptr: *mut f32, + ); + } + _svst4_f32( + svget4_f32::<0>(data), + svget4_f32::<1>(data), + svget4_f32::<2>(data), + svget4_f32::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_f64(pg: svbool_t, base: *mut f64, data: svfloat64x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv2f64")] + fn _svst4_f64( + data0: svfloat64_t, + data1: svfloat64_t, + data2: svfloat64_t, + data3: svfloat64_t, + pg: svbool2_t, + ptr: *mut f64, + ); + } + _svst4_f64( + svget4_f64::<0>(data), + svget4_f64::<1>(data), + svget4_f64::<2>(data), + svget4_f64::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_s8(pg: svbool_t, base: *mut i8, data: svint8x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv16i8")] + fn _svst4_s8( + data0: svint8_t, + data1: svint8_t, + data2: svint8_t, + data3: svint8_t, + pg: svbool_t, + ptr: *mut i8, + ); + } + _svst4_s8( + svget4_s8::<0>(data), + svget4_s8::<1>(data), + svget4_s8::<2>(data), + svget4_s8::<3>(data), + pg, + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_s16(pg: svbool_t, base: *mut i16, data: svint16x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv8i16")] + fn _svst4_s16( + data0: svint16_t, + data1: svint16_t, + data2: svint16_t, + data3: svint16_t, + pg: svbool8_t, + ptr: *mut i16, + ); + } + _svst4_s16( + svget4_s16::<0>(data), + svget4_s16::<1>(data), + svget4_s16::<2>(data), + svget4_s16::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_s32(pg: svbool_t, base: *mut i32, data: svint32x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv4i32")] + fn _svst4_s32( + data0: svint32_t, + data1: svint32_t, + data2: svint32_t, + data3: svint32_t, + pg: svbool4_t, + ptr: *mut i32, + ); + } + _svst4_s32( + svget4_s32::<0>(data), + svget4_s32::<1>(data), + svget4_s32::<2>(data), + svget4_s32::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_s64(pg: svbool_t, base: *mut i64, data: svint64x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv2i64")] + fn _svst4_s64( + data0: svint64_t, + data1: svint64_t, + data2: svint64_t, + data3: svint64_t, + pg: svbool2_t, + ptr: *mut i64, + ); + } + _svst4_s64( + svget4_s64::<0>(data), + svget4_s64::<1>(data), + svget4_s64::<2>(data), + svget4_s64::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_u8(pg: svbool_t, base: *mut u8, data: svuint8x4_t) { + svst4_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_u16(pg: svbool_t, base: *mut u16, data: svuint16x4_t) { + svst4_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_u32(pg: svbool_t, base: *mut u32, data: svuint32x4_t) { + svst4_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_u64(pg: svbool_t, base: *mut u64, data: svuint64x4_t) { + svst4_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x4_t) { + svst4_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x4_t) { + svst4_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x4_t) { + svst4_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x4_t) { + svst4_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x4_t) { + svst4_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x4_t) { + svst4_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x4_t) { + svst4_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x4_t) { + svst4_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x4_t) { + svst4_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x4_t) { + svst4_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv4f32")] + fn _svstnt1_f32(data: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svstnt1_f32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv2f64")] + fn _svstnt1_f64(data: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svstnt1_f64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv16i8")] + fn _svstnt1_s8(data: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svstnt1_s8(data, pg, base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv8i16")] + fn _svstnt1_s16(data: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svstnt1_s16(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv4i32")] + fn _svstnt1_s32(data: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svstnt1_s32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv2i64")] + fn _svstnt1_s64(data: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svstnt1_s64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) { + svstnt1_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) { + svstnt1_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) { + svstnt1_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) { + svstnt1_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32_t) { + svstnt1_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64_t) { + svstnt1_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8_t) { + svstnt1_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16_t) { + svstnt1_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32_t) { + svstnt1_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64_t) { + svstnt1_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8_t) { + svstnt1_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16_t) { + svstnt1_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32_t) { + svstnt1_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64_t) { + svstnt1_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsub.nxv4f32")] + fn _svsub_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsub_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsub_f32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsub_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsub.nxv2f64")] + fn _svsub_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsub_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsub_f64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsub_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv16i8")] + fn _svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsub_s8_m(pg, op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsub_s8_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv8i16")] + fn _svsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsub_s16_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv4i32")] + fn _svsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsub_s32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv2i64")] + fn _svsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsub_s64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsub_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsub_u8_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsub_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsub_u16_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsub_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsub_u32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsub_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsub_u64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsubr.nxv4f32")] + fn _svsubr_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsubr_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsubr_f32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsubr_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsubr.nxv2f64")] + fn _svsubr_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsubr_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsubr_f64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsubr_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv16i8")] + fn _svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsubr_s8_m(pg, op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsubr_s8_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv8i16")] + fn _svsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsubr_s16_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv4i32")] + fn _svsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsubr_s32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv2i64")] + fn _svsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsubr_s64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsubr_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsubr_u8_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsubr_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsubr_u16_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsubr_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsubr_u32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsubr_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsubr_u64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sudot, IMM_INDEX = 0))] +pub fn svsudot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svuint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sudot.lane.nxv4i32" + )] + fn _svsudot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svsudot_lane_s32(op1, op2, op3.as_signed(), IMM_INDEX) } +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svsudot_s32(op1: svint32_t, op2: svint8_t, op3: svuint8_t) -> svint32_t { + svusdot_s32(op1, op3, op2) +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svsudot_n_s32(op1: svint32_t, op2: svint8_t, op3: u8) -> svint32_t { + svsudot_s32(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_f32(data: svfloat32_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv4f32")] + fn _svtbl_f32(data: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { _svtbl_f32(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_f64(data: svfloat64_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv2f64")] + fn _svtbl_f64(data: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { _svtbl_f64(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s8(data: svint8_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv16i8")] + fn _svtbl_s8(data: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { _svtbl_s8(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s16(data: svint16_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv8i16")] + fn _svtbl_s16(data: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { _svtbl_s16(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s32(data: svint32_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv4i32")] + fn _svtbl_s32(data: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svtbl_s32(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s64(data: svint64_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv2i64")] + fn _svtbl_s64(data: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svtbl_s64(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u8(data: svuint8_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbl_s8(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u16(data: svuint16_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbl_s16(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u32(data: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbl_s32(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u64(data: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbl_s64(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Trigonometric multiply-add coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))] +pub fn svtmad_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftmad.x.nxv4f32" + )] + fn _svtmad_f32(op1: svfloat32_t, op2: svfloat32_t, imm3: i32) -> svfloat32_t; + } + unsafe { _svtmad_f32(op1, op2, IMM3) } +} +#[doc = "Trigonometric multiply-add coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))] +pub fn svtmad_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftmad.x.nxv2f64" + )] + fn _svtmad_f64(op1: svfloat64_t, op2: svfloat64_t, imm3: i32) -> svfloat64_t; + } + unsafe { _svtmad_f64(op1, op2, IMM3) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i1")] + fn _svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn1_b8(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i1")] + fn _svtrn1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svtrn1_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i1")] + fn _svtrn1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svtrn1_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i1")] + fn _svtrn1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svtrn1_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4f32")] + fn _svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn1_f32(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2f64")] + fn _svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn1_f64(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i8")] + fn _svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn1_s8(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i16")] + fn _svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn1_s16(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i32")] + fn _svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn1_s32(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i64")] + fn _svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn1_s64(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv4f32")] + fn _svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn1q_f32(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv2f64")] + fn _svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn1q_f64(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv16i8")] + fn _svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn1q_s8(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv8i16")] + fn _svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn1q_s16(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv4i32")] + fn _svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn1q_s32(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv2i64")] + fn _svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn1q_s64(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i1")] + fn _svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn2_b8(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i1")] + fn _svtrn2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svtrn2_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i1")] + fn _svtrn2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svtrn2_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i1")] + fn _svtrn2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svtrn2_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4f32")] + fn _svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn2_f32(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2f64")] + fn _svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn2_f64(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i8")] + fn _svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn2_s8(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i16")] + fn _svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn2_s16(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i32")] + fn _svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn2_s32(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i64")] + fn _svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn2_s64(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv4f32")] + fn _svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn2q_f32(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv2f64")] + fn _svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn2q_f64(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv16i8")] + fn _svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn2q_s8(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv8i16")] + fn _svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn2q_s16(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv4i32")] + fn _svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn2q_s32(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv2i64")] + fn _svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn2q_s64(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Trigonometric starting value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftsmul))] +pub fn svtsmul_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftsmul.x.nxv4f32" + )] + fn _svtsmul_f32(op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svtsmul_f32(op1, op2.as_signed()) } +} +#[doc = "Trigonometric starting value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftsmul))] +pub fn svtsmul_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftsmul.x.nxv2f64" + )] + fn _svtsmul_f64(op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svtsmul_f64(op1, op2.as_signed()) } +} +#[doc = "Trigonometric select coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftssel))] +pub fn svtssel_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftssel.x.nxv4f32" + )] + fn _svtssel_f32(op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svtssel_f32(op1, op2.as_signed()) } +} +#[doc = "Trigonometric select coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftssel))] +pub fn svtssel_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftssel.x.nxv2f64" + )] + fn _svtssel_f64(op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svtssel_f64(op1, op2.as_signed()) } +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_f32() -> svfloat32x2_t { + svcreate2_f32(svdup_n_f32(0f32), svdup_n_f32(0f32)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_f64() -> svfloat64x2_t { + svcreate2_f64(svdup_n_f64(0f64), svdup_n_f64(0f64)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s8() -> svint8x2_t { + svcreate2_s8(svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s16() -> svint16x2_t { + svcreate2_s16(svdup_n_s16(0), svdup_n_s16(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s32() -> svint32x2_t { + svcreate2_s32(svdup_n_s32(0), svdup_n_s32(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s64() -> svint64x2_t { + svcreate2_s64(svdup_n_s64(0), svdup_n_s64(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u8() -> svuint8x2_t { + svcreate2_u8(svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u16() -> svuint16x2_t { + svcreate2_u16(svdup_n_u16(0), svdup_n_u16(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u32() -> svuint32x2_t { + svcreate2_u32(svdup_n_u32(0), svdup_n_u32(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u64() -> svuint64x2_t { + svcreate2_u64(svdup_n_u64(0), svdup_n_u64(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_f32() -> svfloat32x3_t { + svcreate3_f32(svdup_n_f32(0f32), svdup_n_f32(0f32), svdup_n_f32(0f32)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_f64() -> svfloat64x3_t { + svcreate3_f64(svdup_n_f64(0f64), svdup_n_f64(0f64), svdup_n_f64(0f64)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s8() -> svint8x3_t { + svcreate3_s8(svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s16() -> svint16x3_t { + svcreate3_s16(svdup_n_s16(0), svdup_n_s16(0), svdup_n_s16(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s32() -> svint32x3_t { + svcreate3_s32(svdup_n_s32(0), svdup_n_s32(0), svdup_n_s32(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s64() -> svint64x3_t { + svcreate3_s64(svdup_n_s64(0), svdup_n_s64(0), svdup_n_s64(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u8() -> svuint8x3_t { + svcreate3_u8(svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u16() -> svuint16x3_t { + svcreate3_u16(svdup_n_u16(0), svdup_n_u16(0), svdup_n_u16(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u32() -> svuint32x3_t { + svcreate3_u32(svdup_n_u32(0), svdup_n_u32(0), svdup_n_u32(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u64() -> svuint64x3_t { + svcreate3_u64(svdup_n_u64(0), svdup_n_u64(0), svdup_n_u64(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_f32() -> svfloat32x4_t { + svcreate4_f32( + svdup_n_f32(0f32), + svdup_n_f32(0f32), + svdup_n_f32(0f32), + svdup_n_f32(0f32), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_f64() -> svfloat64x4_t { + svcreate4_f64( + svdup_n_f64(0f64), + svdup_n_f64(0f64), + svdup_n_f64(0f64), + svdup_n_f64(0f64), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s8() -> svint8x4_t { + svcreate4_s8(svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s16() -> svint16x4_t { + svcreate4_s16( + svdup_n_s16(0), + svdup_n_s16(0), + svdup_n_s16(0), + svdup_n_s16(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s32() -> svint32x4_t { + svcreate4_s32( + svdup_n_s32(0), + svdup_n_s32(0), + svdup_n_s32(0), + svdup_n_s32(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s64() -> svint64x4_t { + svcreate4_s64( + svdup_n_s64(0), + svdup_n_s64(0), + svdup_n_s64(0), + svdup_n_s64(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u8() -> svuint8x4_t { + svcreate4_u8(svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u16() -> svuint16x4_t { + svcreate4_u16( + svdup_n_u16(0), + svdup_n_u16(0), + svdup_n_u16(0), + svdup_n_u16(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u32() -> svuint32x4_t { + svcreate4_u32( + svdup_n_u32(0), + svdup_n_u32(0), + svdup_n_u32(0), + svdup_n_u32(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u64() -> svuint64x4_t { + svcreate4_u64( + svdup_n_u64(0), + svdup_n_u64(0), + svdup_n_u64(0), + svdup_n_u64(0), + ) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_f32() -> svfloat32_t { + svdup_n_f32(0f32) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_f64() -> svfloat64_t { + svdup_n_f64(0f64) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s8() -> svint8_t { + svdup_n_s8(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s16() -> svint16_t { + svdup_n_s16(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s32() -> svint32_t { + svdup_n_s32(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s64() -> svint64_t { + svdup_n_s64(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u8() -> svuint8_t { + svdup_n_u8(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u16() -> svuint16_t { + svdup_n_u16(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u32() -> svuint32_t { + svdup_n_u32(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u64() -> svuint64_t { + svdup_n_u64(0) +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot, IMM_INDEX = 0))] +pub fn svusdot_lane_s32( + op1: svint32_t, + op2: svuint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.usdot.lane.nxv4i32" + )] + fn _svusdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svusdot_lane_s32(op1, op2.as_signed(), op3, IMM_INDEX) } +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svusdot_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usdot.nxv4i32")] + fn _svusdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svusdot_s32(op1, op2.as_signed(), op3) } +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svusdot_n_s32(op1: svint32_t, op2: svuint8_t, op3: i8) -> svint32_t { + svusdot_s32(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Matrix multiply-accumulate (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusmmla[_s32])"] +#[inline] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usmmla))] +pub fn svusmmla_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usmmla.nxv4i32")] + fn _svusmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svusmmla_s32(op1, op2.as_signed(), op3) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i1")] + fn _svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp1_b8(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv8i1")] + fn _svuzp1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svuzp1_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4i1")] + fn _svuzp1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svuzp1_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2i1")] + fn _svuzp1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svuzp1_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4f32")] + fn _svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp1_f32(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2f64")] + fn _svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp1_f64(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i8")] + fn _svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp1_s8(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv8i16")] + fn _svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp1_s16(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4i32")] + fn _svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp1_s32(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2i64")] + fn _svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp1_s64(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv4f32")] + fn _svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp1q_f32(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv2f64")] + fn _svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp1q_f64(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv16i8")] + fn _svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp1q_s8(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv8i16")] + fn _svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp1q_s16(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv4i32")] + fn _svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp1q_s32(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv2i64")] + fn _svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp1q_s64(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i1")] + fn _svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp2_b8(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv8i1")] + fn _svuzp2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svuzp2_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4i1")] + fn _svuzp2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svuzp2_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2i1")] + fn _svuzp2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svuzp2_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4f32")] + fn _svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp2_f32(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2f64")] + fn _svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp2_f64(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i8")] + fn _svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp2_s8(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv8i16")] + fn _svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp2_s16(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4i32")] + fn _svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp2_s32(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2i64")] + fn _svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp2_s64(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv4f32")] + fn _svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp2q_f32(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv2f64")] + fn _svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp2q_f64(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv16i8")] + fn _svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp2q_s8(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv8i16")] + fn _svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp2q_s16(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv4i32")] + fn _svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp2q_s32(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv2i64")] + fn _svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp2q_s64(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv16i1.i32" + )] + fn _svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilele_b8_s32(op1, op2) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv8i1.i32" + )] + fn _svwhilele_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilele_b16_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv4i1.i32" + )] + fn _svwhilele_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilele_b32_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv2i1.i32" + )] + fn _svwhilele_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilele_b64_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv16i1.i64" + )] + fn _svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilele_b8_s64(op1, op2) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv8i1.i64" + )] + fn _svwhilele_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilele_b16_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv4i1.i64" + )] + fn _svwhilele_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilele_b32_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv2i1.i64" + )] + fn _svwhilele_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilele_b64_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv16i1.i32" + )] + fn _svwhilele_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilele_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv8i1.i32" + )] + fn _svwhilele_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilele_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv4i1.i32" + )] + fn _svwhilele_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilele_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv2i1.i32" + )] + fn _svwhilele_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilele_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv16i1.i64" + )] + fn _svwhilele_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilele_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv8i1.i64" + )] + fn _svwhilele_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilele_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv4i1.i64" + )] + fn _svwhilele_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilele_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv2i1.i64" + )] + fn _svwhilele_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilele_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv16i1.i32" + )] + fn _svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilelt_b8_s32(op1, op2) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv8i1.i32" + )] + fn _svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilelt_b16_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv4i1.i32" + )] + fn _svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilelt_b32_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv2i1.i32" + )] + fn _svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilelt_b64_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv16i1.i64" + )] + fn _svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilelt_b8_s64(op1, op2) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv8i1.i64" + )] + fn _svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilelt_b16_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv4i1.i64" + )] + fn _svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilelt_b32_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv2i1.i64" + )] + fn _svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilelt_b64_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv16i1.i32" + )] + fn _svwhilelt_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilelt_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv8i1.i32" + )] + fn _svwhilelt_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilelt_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv4i1.i32" + )] + fn _svwhilelt_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilelt_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv2i1.i32" + )] + fn _svwhilelt_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilelt_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv16i1.i64" + )] + fn _svwhilelt_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilelt_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv8i1.i64" + )] + fn _svwhilelt_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilelt_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv4i1.i64" + )] + fn _svwhilelt_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilelt_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv2i1.i64" + )] + fn _svwhilelt_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilelt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Write to the first-fault register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwrffr)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(wrffr))] +pub fn svwrffr(op: svbool_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.wrffr")] + fn _svwrffr(op: svbool_t); + } + unsafe { _svwrffr(op) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i1")] + fn _svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip1_b8(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv8i1")] + fn _svzip1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svzip1_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4i1")] + fn _svzip1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svzip1_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2i1")] + fn _svzip1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svzip1_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4f32")] + fn _svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip1_f32(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2f64")] + fn _svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip1_f64(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i8")] + fn _svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip1_s8(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv8i16")] + fn _svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip1_s16(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4i32")] + fn _svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip1_s32(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2i64")] + fn _svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip1_s64(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv4f32")] + fn _svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip1q_f32(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv2f64")] + fn _svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip1q_f64(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv16i8")] + fn _svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip1q_s8(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv8i16")] + fn _svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip1q_s16(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv4i32")] + fn _svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip1q_s32(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv2i64")] + fn _svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip1q_s64(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b8)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i1")] + fn _svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip2_b8(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b16)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv8i1")] + fn _svzip2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svzip2_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b32)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4i1")] + fn _svzip2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svzip2_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b64)"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2i1")] + fn _svzip2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svzip2_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4f32")] + fn _svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip2_f32(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2f64")] + fn _svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip2_f64(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i8")] + fn _svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip2_s8(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv8i16")] + fn _svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip2_s16(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4i32")] + fn _svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip2_s32(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2i64")] + fn _svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip2_s64(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u8])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u16])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u32])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u64])"] +#[inline] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv4f32")] + fn _svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip2q_f32(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv2f64")] + fn _svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip2q_f64(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv16i8")] + fn _svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip2q_s8(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv8i16")] + fn _svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip2q_s16(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv4i32")] + fn _svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip2q_s32(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv2i64")] + fn _svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip2q_s64(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u8])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u16])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u32])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u64])"] +#[inline] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} diff --git a/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs b/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs new file mode 100644 index 0000000000000..3007ba4ee6597 --- /dev/null +++ b/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs @@ -0,0 +1,11235 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate +// this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(unused)] +use super::*; +use std::boxed::Box; +use std::convert::{TryFrom, TryInto}; +use std::sync::LazyLock; +use std::vec::Vec; +use stdarch_test::simd_test; +static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as f32) + .collect::>() + .try_into() + .expect("f32 data incorrectly initialised") +}); +static F64_DATA: LazyLock<[f64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as f64) + .collect::>() + .try_into() + .expect("f64 data incorrectly initialised") +}); +static I8_DATA: LazyLock<[i8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| ((i + 128) % 256 - 128) as i8) + .collect::>() + .try_into() + .expect("i8 data incorrectly initialised") +}); +static I16_DATA: LazyLock<[i16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as i16) + .collect::>() + .try_into() + .expect("i16 data incorrectly initialised") +}); +static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as i32) + .collect::>() + .try_into() + .expect("i32 data incorrectly initialised") +}); +static I64_DATA: LazyLock<[i64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as i64) + .collect::>() + .try_into() + .expect("i64 data incorrectly initialised") +}); +static U8_DATA: LazyLock<[u8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| i as u8) + .collect::>() + .try_into() + .expect("u8 data incorrectly initialised") +}); +static U16_DATA: LazyLock<[u16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as u16) + .collect::>() + .try_into() + .expect("u16 data incorrectly initialised") +}); +static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as u32) + .collect::>() + .try_into() + .expect("u32 data incorrectly initialised") +}); +static U64_DATA: LazyLock<[u64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as u64) + .collect::>() + .try_into() + .expect("u64 data incorrectly initialised") +}); +#[target_feature(enable = "sve")] +fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_f32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_f64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_s8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_s16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_s32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_s64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_u8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_u16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_u32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_u64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_f32_with_svst1_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svst1_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_f64_with_svst1_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svst1_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s8_with_svst1_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s16_with_svst1_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s32_with_svst1_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s64_with_svst1_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u8_with_svst1_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u16_with_svst1_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u32_with_svst1_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u64_with_svst1_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_f32_with_svst1_scatter_s32index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_f32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_s32index_f32(svptrue_b32(), storage.as_ptr() as *const f32, indices); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_s32_with_svst1_scatter_s32index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_s32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_s32index_s32(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_u32_with_svst1_scatter_s32index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_u32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_s32index_u32(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_f64_with_svst1_scatter_s64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_s64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_s64_with_svst1_scatter_s64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_s64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_u64_with_svst1_scatter_s64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_s64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_f32_with_svst1_scatter_u32index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_f32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32index_f32(svptrue_b32(), storage.as_ptr() as *const f32, indices); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_s32_with_svst1_scatter_u32index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_s32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32index_s32(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_u32_with_svst1_scatter_u32index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_u32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32index_u32(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_f64_with_svst1_scatter_u64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_s64_with_svst1_scatter_u64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_u64_with_svst1_scatter_u64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_f32_with_svst1_scatter_s32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_s32_with_svst1_scatter_s32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_u32_with_svst1_scatter_s32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_f64_with_svst1_scatter_s64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_s64_with_svst1_scatter_s64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_u64_with_svst1_scatter_s64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_f32_with_svst1_scatter_u32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_s32_with_svst1_scatter_u32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_u32_with_svst1_scatter_u32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_f64_with_svst1_scatter_u64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_s64_with_svst1_scatter_u64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_u64_with_svst1_scatter_u64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_f64_with_svst1_scatter_u64base_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_f64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_f64(svptrue_b64(), bases); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_s64_with_svst1_scatter_u64base_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_s64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_s64(svptrue_b64(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_u64_with_svst1_scatter_u64base_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_u64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_u64(svptrue_b64(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_f32_with_svst1_scatter_u32base_index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_s32_with_svst1_scatter_u32base_index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_u32_with_svst1_scatter_u32base_index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_f64_with_svst1_scatter_u64base_index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_s64_with_svst1_scatter_u64base_index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_u64_with_svst1_scatter_u64base_index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_f32_with_svst1_scatter_u32base_offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_s32_with_svst1_scatter_u32base_offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_u32_with_svst1_scatter_u32base_offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_f64_with_svst1_scatter_u64base_offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_s64_with_svst1_scatter_u64base_offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_u64_with_svst1_scatter_u64base_offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_f32_with_svst1_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svst1_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_f64_with_svst1_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svst1_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s8_with_svst1_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s16_with_svst1_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s32_with_svst1_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s64_with_svst1_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u8_with_svst1_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u16_with_svst1_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u32_with_svst1_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u64_with_svst1_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_f32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_f32 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_f32(svptrue_b32(), F32_DATA.as_ptr()); + assert_vector_matches_f32( + loaded, + svtrn1q_f32( + svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32), + svdupq_n_f32(4usize as f32, 5usize as f32, 6usize as f32, 7usize as f32), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_f64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_f64 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_f64(svptrue_b64(), F64_DATA.as_ptr()); + assert_vector_matches_f64( + loaded, + svtrn1q_f64( + svdupq_n_f64(0usize as f64, 1usize as f64), + svdupq_n_f64(2usize as f64, 3usize as f64), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s8() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s8 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_s8(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i8( + loaded, + svtrn1q_s8( + svdupq_n_s8( + 0usize as i8, + 1usize as i8, + 2usize as i8, + 3usize as i8, + 4usize as i8, + 5usize as i8, + 6usize as i8, + 7usize as i8, + 8usize as i8, + 9usize as i8, + 10usize as i8, + 11usize as i8, + 12usize as i8, + 13usize as i8, + 14usize as i8, + 15usize as i8, + ), + svdupq_n_s8( + 16usize as i8, + 17usize as i8, + 18usize as i8, + 19usize as i8, + 20usize as i8, + 21usize as i8, + 22usize as i8, + 23usize as i8, + 24usize as i8, + 25usize as i8, + 26usize as i8, + 27usize as i8, + 28usize as i8, + 29usize as i8, + 30usize as i8, + 31usize as i8, + ), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s16() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s16 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_s16(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svtrn1q_s16( + svdupq_n_s16( + 0usize as i16, + 1usize as i16, + 2usize as i16, + 3usize as i16, + 4usize as i16, + 5usize as i16, + 6usize as i16, + 7usize as i16, + ), + svdupq_n_s16( + 8usize as i16, + 9usize as i16, + 10usize as i16, + 11usize as i16, + 12usize as i16, + 13usize as i16, + 14usize as i16, + 15usize as i16, + ), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s32 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_s32(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svtrn1q_s32( + svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32), + svdupq_n_s32(4usize as i32, 5usize as i32, 6usize as i32, 7usize as i32), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s64 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_s64(svptrue_b64(), I64_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svtrn1q_s64( + svdupq_n_s64(0usize as i64, 1usize as i64), + svdupq_n_s64(2usize as i64, 3usize as i64), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u8() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u8 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_u8(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u8( + loaded, + svtrn1q_u8( + svdupq_n_u8( + 0usize as u8, + 1usize as u8, + 2usize as u8, + 3usize as u8, + 4usize as u8, + 5usize as u8, + 6usize as u8, + 7usize as u8, + 8usize as u8, + 9usize as u8, + 10usize as u8, + 11usize as u8, + 12usize as u8, + 13usize as u8, + 14usize as u8, + 15usize as u8, + ), + svdupq_n_u8( + 16usize as u8, + 17usize as u8, + 18usize as u8, + 19usize as u8, + 20usize as u8, + 21usize as u8, + 22usize as u8, + 23usize as u8, + 24usize as u8, + 25usize as u8, + 26usize as u8, + 27usize as u8, + 28usize as u8, + 29usize as u8, + 30usize as u8, + 31usize as u8, + ), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u16() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u16 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_u16(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svtrn1q_u16( + svdupq_n_u16( + 0usize as u16, + 1usize as u16, + 2usize as u16, + 3usize as u16, + 4usize as u16, + 5usize as u16, + 6usize as u16, + 7usize as u16, + ), + svdupq_n_u16( + 8usize as u16, + 9usize as u16, + 10usize as u16, + 11usize as u16, + 12usize as u16, + 13usize as u16, + 14usize as u16, + 15usize as u16, + ), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u32 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_u32(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svtrn1q_u32( + svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32), + svdupq_n_u32(4usize as u32, 5usize as u32, 6usize as u32, 7usize as u32), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u64 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_u64(svptrue_b64(), U64_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svtrn1q_u64( + svdupq_n_u64(0usize as u64, 1usize as u64), + svdupq_n_u64(2usize as u64, 3usize as u64), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_f32() { + svsetffr(); + let loaded = svld1rq_f32(svptrue_b32(), F32_DATA.as_ptr()); + assert_vector_matches_f32( + loaded, + svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_f64() { + svsetffr(); + let loaded = svld1rq_f64(svptrue_b64(), F64_DATA.as_ptr()); + assert_vector_matches_f64(loaded, svdupq_n_f64(0usize as f64, 1usize as f64)); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s8() { + svsetffr(); + let loaded = svld1rq_s8(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i8( + loaded, + svdupq_n_s8( + 0usize as i8, + 1usize as i8, + 2usize as i8, + 3usize as i8, + 4usize as i8, + 5usize as i8, + 6usize as i8, + 7usize as i8, + 8usize as i8, + 9usize as i8, + 10usize as i8, + 11usize as i8, + 12usize as i8, + 13usize as i8, + 14usize as i8, + 15usize as i8, + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s16() { + svsetffr(); + let loaded = svld1rq_s16(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svdupq_n_s16( + 0usize as i16, + 1usize as i16, + 2usize as i16, + 3usize as i16, + 4usize as i16, + 5usize as i16, + 6usize as i16, + 7usize as i16, + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s32() { + svsetffr(); + let loaded = svld1rq_s32(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s64() { + svsetffr(); + let loaded = svld1rq_s64(svptrue_b64(), I64_DATA.as_ptr()); + assert_vector_matches_i64(loaded, svdupq_n_s64(0usize as i64, 1usize as i64)); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u8() { + svsetffr(); + let loaded = svld1rq_u8(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u8( + loaded, + svdupq_n_u8( + 0usize as u8, + 1usize as u8, + 2usize as u8, + 3usize as u8, + 4usize as u8, + 5usize as u8, + 6usize as u8, + 7usize as u8, + 8usize as u8, + 9usize as u8, + 10usize as u8, + 11usize as u8, + 12usize as u8, + 13usize as u8, + 14usize as u8, + 15usize as u8, + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u16() { + svsetffr(); + let loaded = svld1rq_u16(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svdupq_n_u16( + 0usize as u16, + 1usize as u16, + 2usize as u16, + 3usize as u16, + 4usize as u16, + 5usize as u16, + 6usize as u16, + 7usize as u16, + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u32() { + svsetffr(); + let loaded = svld1rq_u32(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u64() { + svsetffr(); + let loaded = svld1rq_u64(svptrue_b64(), U64_DATA.as_ptr()); + assert_vector_matches_u64(loaded, svdupq_n_u64(0usize as u64, 1usize as u64)); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_offset_s64_with_svst1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_offset_u64_with_svst1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_offset_u64_with_svst1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_offset_u64_with_svst1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_s64_with_svst1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_s64_with_svst1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_s64_with_svst1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_u64_with_svst1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_u64_with_svst1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_u64_with_svst1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s16_with_svst1b_s16() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s16(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s32_with_svst1b_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s32(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_s32_with_svst1h_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_s32(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s64_with_svst1b_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s64(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_s64_with_svst1h_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_s64(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_s64_with_svst1w_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_s64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_s64(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u16_with_svst1b_u16() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u16(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u32_with_svst1b_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u32(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_u32_with_svst1h_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_u32(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u64_with_svst1b_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u64(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_u64_with_svst1h_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_u64(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_u64_with_svst1w_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_u64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1sw_u64(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s16_with_svst1b_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s16(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s32_with_svst1b_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s32(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_s32_with_svst1h_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_vnum_s32(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s64_with_svst1b_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s64(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_s64_with_svst1h_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_vnum_s64(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_vnum_s64_with_svst1w_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_s64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_vnum_s64(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u16_with_svst1b_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u16(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u32_with_svst1b_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u32(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_u32_with_svst1h_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_vnum_u32(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u64_with_svst1b_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u64(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_u64_with_svst1h_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_vnum_u64(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_vnum_u64_with_svst1w_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_u64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1sw_vnum_u64(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32index_s32_with_svst1h_scatter_s32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32index_s32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32index_u32_with_svst1h_scatter_s32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32index_u32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64index_s64_with_svst1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64index_s64_with_svst1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64index_u64_with_svst1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64index_u64_with_svst1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32index_s32_with_svst1h_scatter_u32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32index_s32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32index_u32_with_svst1h_scatter_u32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32index_u32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64index_s64_with_svst1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64index_s64_with_svst1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64index_u64_with_svst1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64index_u64_with_svst1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_index_s32_with_svst1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_index_u32_with_svst1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_index_s64_with_svst1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_index_s64_with_svst1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_index_u64_with_svst1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_index_u64_with_svst1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_offset_s64_with_svst1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_offset_u64_with_svst1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_offset_u64_with_svst1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_offset_u64_with_svst1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_s64_with_svst1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_s64_with_svst1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_s64_with_svst1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_u64_with_svst1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_u64_with_svst1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_u64_with_svst1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s16_with_svst1b_s16() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s16(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s32_with_svst1b_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s32(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_s32_with_svst1h_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_s32(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s64_with_svst1b_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s64(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_s64_with_svst1h_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_s64(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_s64_with_svst1w_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_s64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_s64(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u16_with_svst1b_u16() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u16(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u32_with_svst1b_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u32(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_u32_with_svst1h_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_u32(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u64_with_svst1b_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u64(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_u64_with_svst1h_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_u64(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_u64_with_svst1w_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_u64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1uw_u64(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s16_with_svst1b_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s16(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s32_with_svst1b_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s32(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_s32_with_svst1h_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_vnum_s32(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s64_with_svst1b_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s64(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_s64_with_svst1h_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_vnum_s64(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_vnum_s64_with_svst1w_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_s64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_vnum_s64(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u16_with_svst1b_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u16(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u32_with_svst1b_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u32(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_u32_with_svst1h_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_vnum_u32(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u64_with_svst1b_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u64(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_u64_with_svst1h_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_vnum_u64(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_vnum_u64_with_svst1w_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_u64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1uw_vnum_u64(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32index_s32_with_svst1h_scatter_s32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32index_s32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32index_u32_with_svst1h_scatter_s32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32index_u32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64index_s64_with_svst1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64index_s64_with_svst1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64index_u64_with_svst1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64index_u64_with_svst1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32index_s32_with_svst1h_scatter_u32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32index_s32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32index_u32_with_svst1h_scatter_u32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32index_u32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64index_s64_with_svst1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64index_s64_with_svst1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64index_u64_with_svst1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64index_u64_with_svst1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_index_s32_with_svst1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_index_u32_with_svst1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_index_s64_with_svst1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_index_s64_with_svst1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_index_u64_with_svst1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_index_u64_with_svst1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_f32_with_svst2_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate2_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + svst2_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld2_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + svget2_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget2_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_f64_with_svst2_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate2_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + svst2_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld2_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + svget2_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget2_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s8_with_svst2_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate2_s8( + svindex_s8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld2_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + svget2_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget2_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s16_with_svst2_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate2_s16( + svindex_s16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld2_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + svget2_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget2_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s32_with_svst2_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate2_s32( + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld2_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + svget2_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget2_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s64_with_svst2_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate2_s64( + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld2_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + svget2_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget2_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u8_with_svst2_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate2_u8( + svindex_u8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld2_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + svget2_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget2_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u16_with_svst2_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate2_u16( + svindex_u16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld2_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + svget2_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget2_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u32_with_svst2_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate2_u32( + svindex_u32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld2_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + svget2_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget2_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u64_with_svst2_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate2_u64( + svindex_u64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld2_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + svget2_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget2_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_f32_with_svst2_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate2_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + svst2_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld2_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + svget2_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget2_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_f64_with_svst2_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate2_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + svst2_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld2_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + svget2_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget2_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s8_with_svst2_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate2_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld2_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + svget2_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget2_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s16_with_svst2_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate2_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld2_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + svget2_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget2_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s32_with_svst2_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate2_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld2_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + svget2_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget2_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s64_with_svst2_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate2_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld2_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + svget2_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget2_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u8_with_svst2_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate2_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld2_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + svget2_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget2_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u16_with_svst2_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate2_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld2_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + svget2_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget2_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u32_with_svst2_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate2_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld2_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + svget2_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget2_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u64_with_svst2_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate2_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld2_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + svget2_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget2_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_f32_with_svst3_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate3_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + svst3_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld3_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + svget3_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget3_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget3_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_f64_with_svst3_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate3_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + svst3_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld3_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + svget3_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget3_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget3_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s8_with_svst3_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate3_s8( + svindex_s8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld3_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + svget3_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget3_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget3_s8::<{ 2usize as i32 }>(loaded), + svindex_s8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s16_with_svst3_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate3_s16( + svindex_s16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld3_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + svget3_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget3_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget3_s16::<{ 2usize as i32 }>(loaded), + svindex_s16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s32_with_svst3_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate3_s32( + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld3_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + svget3_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget3_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget3_s32::<{ 2usize as i32 }>(loaded), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s64_with_svst3_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate3_s64( + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld3_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + svget3_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget3_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget3_s64::<{ 2usize as i32 }>(loaded), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u8_with_svst3_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate3_u8( + svindex_u8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld3_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + svget3_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget3_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget3_u8::<{ 2usize as i32 }>(loaded), + svindex_u8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u16_with_svst3_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate3_u16( + svindex_u16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld3_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + svget3_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget3_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget3_u16::<{ 2usize as i32 }>(loaded), + svindex_u16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u32_with_svst3_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate3_u32( + svindex_u32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld3_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + svget3_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget3_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget3_u32::<{ 2usize as i32 }>(loaded), + svindex_u32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u64_with_svst3_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate3_u64( + svindex_u64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld3_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + svget3_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget3_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget3_u64::<{ 2usize as i32 }>(loaded), + svindex_u64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_f32_with_svst3_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate3_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + svst3_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld3_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + svget3_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget3_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget3_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_f64_with_svst3_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate3_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + svst3_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld3_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + svget3_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget3_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget3_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s8_with_svst3_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate3_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld3_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + svget3_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget3_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget3_s8::<{ 2usize as i32 }>(loaded), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s16_with_svst3_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate3_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld3_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + svget3_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget3_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget3_s16::<{ 2usize as i32 }>(loaded), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s32_with_svst3_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate3_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld3_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + svget3_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget3_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget3_s32::<{ 2usize as i32 }>(loaded), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s64_with_svst3_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate3_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld3_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + svget3_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget3_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget3_s64::<{ 2usize as i32 }>(loaded), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u8_with_svst3_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate3_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld3_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + svget3_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget3_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget3_u8::<{ 2usize as i32 }>(loaded), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u16_with_svst3_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate3_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld3_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + svget3_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget3_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget3_u16::<{ 2usize as i32 }>(loaded), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u32_with_svst3_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate3_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld3_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + svget3_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget3_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget3_u32::<{ 2usize as i32 }>(loaded), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u64_with_svst3_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate3_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld3_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + svget3_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget3_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget3_u64::<{ 2usize as i32 }>(loaded), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_f32_with_svst4_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate4_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + svst4_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld4_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + svget4_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 3usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_f64_with_svst4_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate4_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + svst4_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld4_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + svget4_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 3usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s8_with_svst4_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate4_s8( + svindex_s8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld4_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + svget4_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget4_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget4_s8::<{ 2usize as i32 }>(loaded), + svindex_s8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget4_s8::<{ 3usize as i32 }>(loaded), + svindex_s8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s16_with_svst4_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate4_s16( + svindex_s16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld4_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + svget4_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget4_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget4_s16::<{ 2usize as i32 }>(loaded), + svindex_s16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget4_s16::<{ 3usize as i32 }>(loaded), + svindex_s16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s32_with_svst4_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate4_s32( + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld4_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + svget4_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget4_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget4_s32::<{ 2usize as i32 }>(loaded), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget4_s32::<{ 3usize as i32 }>(loaded), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s64_with_svst4_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate4_s64( + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld4_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + svget4_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget4_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget4_s64::<{ 2usize as i32 }>(loaded), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget4_s64::<{ 3usize as i32 }>(loaded), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u8_with_svst4_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate4_u8( + svindex_u8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld4_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + svget4_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget4_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget4_u8::<{ 2usize as i32 }>(loaded), + svindex_u8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget4_u8::<{ 3usize as i32 }>(loaded), + svindex_u8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u16_with_svst4_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate4_u16( + svindex_u16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld4_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + svget4_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget4_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget4_u16::<{ 2usize as i32 }>(loaded), + svindex_u16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget4_u16::<{ 3usize as i32 }>(loaded), + svindex_u16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u32_with_svst4_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate4_u32( + svindex_u32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld4_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + svget4_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget4_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget4_u32::<{ 2usize as i32 }>(loaded), + svindex_u32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget4_u32::<{ 3usize as i32 }>(loaded), + svindex_u32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u64_with_svst4_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate4_u64( + svindex_u64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld4_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + svget4_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget4_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget4_u64::<{ 2usize as i32 }>(loaded), + svindex_u64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget4_u64::<{ 3usize as i32 }>(loaded), + svindex_u64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_f32_with_svst4_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate4_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + svst4_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld4_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + svget4_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 3usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_f64_with_svst4_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate4_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + svst4_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld4_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + svget4_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 3usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s8_with_svst4_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate4_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld4_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + svget4_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget4_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget4_s8::<{ 2usize as i32 }>(loaded), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget4_s8::<{ 3usize as i32 }>(loaded), + svindex_s8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s16_with_svst4_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate4_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld4_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + svget4_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget4_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget4_s16::<{ 2usize as i32 }>(loaded), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget4_s16::<{ 3usize as i32 }>(loaded), + svindex_s16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s32_with_svst4_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate4_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld4_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + svget4_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget4_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget4_s32::<{ 2usize as i32 }>(loaded), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget4_s32::<{ 3usize as i32 }>(loaded), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s64_with_svst4_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate4_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld4_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + svget4_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget4_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget4_s64::<{ 2usize as i32 }>(loaded), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget4_s64::<{ 3usize as i32 }>(loaded), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u8_with_svst4_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate4_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld4_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + svget4_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget4_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget4_u8::<{ 2usize as i32 }>(loaded), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget4_u8::<{ 3usize as i32 }>(loaded), + svindex_u8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u16_with_svst4_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate4_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld4_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + svget4_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget4_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget4_u16::<{ 2usize as i32 }>(loaded), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget4_u16::<{ 3usize as i32 }>(loaded), + svindex_u16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u32_with_svst4_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate4_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld4_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + svget4_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget4_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget4_u32::<{ 2usize as i32 }>(loaded), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget4_u32::<{ 3usize as i32 }>(loaded), + svindex_u32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u64_with_svst4_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate4_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld4_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + svget4_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget4_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget4_u64::<{ 2usize as i32 }>(loaded), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget4_u64::<{ 3usize as i32 }>(loaded), + svindex_u64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_f32() { + svsetffr(); + let _ = svld1_f32(svptrue_b32(), F32_DATA.as_ptr()); + let loaded = svldff1_f32(svptrue_b32(), F32_DATA.as_ptr()); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_f64() { + svsetffr(); + let _ = svld1_f64(svptrue_b64(), F64_DATA.as_ptr()); + let loaded = svldff1_f64(svptrue_b64(), F64_DATA.as_ptr()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s8() { + svsetffr(); + let _ = svld1_s8(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1_s8(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s16() { + svsetffr(); + let _ = svld1_s16(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1_s16(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s32() { + svsetffr(); + let _ = svld1_s32(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldff1_s32(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s64() { + svsetffr(); + let _ = svld1_s64(svptrue_b64(), I64_DATA.as_ptr()); + let loaded = svldff1_s64(svptrue_b64(), I64_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u8() { + svsetffr(); + let _ = svld1_u8(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1_u8(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u16() { + svsetffr(); + let _ = svld1_u16(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1_u16(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u32() { + svsetffr(); + let _ = svld1_u32(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldff1_u32(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u64() { + svsetffr(); + let _ = svld1_u64(svptrue_b64(), U64_DATA.as_ptr()); + let loaded = svldff1_u64(svptrue_b64(), U64_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32index_f32() { + let indices = svindex_s32(0, 1); + svsetffr(); + let _ = svld1_gather_s32index_f32(svptrue_b32(), F32_DATA.as_ptr(), indices); + let loaded = svldff1_gather_s32index_f32(svptrue_b32(), F32_DATA.as_ptr(), indices); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32index_s32() { + let indices = svindex_s32(0, 1); + svsetffr(); + let _ = svld1_gather_s32index_s32(svptrue_b32(), I32_DATA.as_ptr(), indices); + let loaded = svldff1_gather_s32index_s32(svptrue_b32(), I32_DATA.as_ptr(), indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32index_u32() { + let indices = svindex_s32(0, 1); + svsetffr(); + let _ = svld1_gather_s32index_u32(svptrue_b32(), U32_DATA.as_ptr(), indices); + let loaded = svldff1_gather_s32index_u32(svptrue_b32(), U32_DATA.as_ptr(), indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64index_f64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1_gather_s64index_f64(svptrue_b64(), F64_DATA.as_ptr(), indices); + let loaded = svldff1_gather_s64index_f64(svptrue_b64(), F64_DATA.as_ptr(), indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1_gather_s64index_s64(svptrue_b64(), I64_DATA.as_ptr(), indices); + let loaded = svldff1_gather_s64index_s64(svptrue_b64(), I64_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1_gather_s64index_u64(svptrue_b64(), U64_DATA.as_ptr(), indices); + let loaded = svldff1_gather_s64index_u64(svptrue_b64(), U64_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32index_f32() { + let indices = svindex_u32(0, 1); + svsetffr(); + let _ = svld1_gather_u32index_f32(svptrue_b32(), F32_DATA.as_ptr(), indices); + let loaded = svldff1_gather_u32index_f32(svptrue_b32(), F32_DATA.as_ptr(), indices); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32index_s32() { + let indices = svindex_u32(0, 1); + svsetffr(); + let _ = svld1_gather_u32index_s32(svptrue_b32(), I32_DATA.as_ptr(), indices); + let loaded = svldff1_gather_u32index_s32(svptrue_b32(), I32_DATA.as_ptr(), indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32index_u32() { + let indices = svindex_u32(0, 1); + svsetffr(); + let _ = svld1_gather_u32index_u32(svptrue_b32(), U32_DATA.as_ptr(), indices); + let loaded = svldff1_gather_u32index_u32(svptrue_b32(), U32_DATA.as_ptr(), indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64index_f64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1_gather_u64index_f64(svptrue_b64(), F64_DATA.as_ptr(), indices); + let loaded = svldff1_gather_u64index_f64(svptrue_b64(), F64_DATA.as_ptr(), indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1_gather_u64index_s64(svptrue_b64(), I64_DATA.as_ptr(), indices); + let loaded = svldff1_gather_u64index_s64(svptrue_b64(), I64_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1_gather_u64index_u64(svptrue_b64(), U64_DATA.as_ptr(), indices); + let loaded = svldff1_gather_u64index_u64(svptrue_b64(), U64_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32offset_f32() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_s32offset_f32(svptrue_b32(), F32_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_s32offset_f32(svptrue_b32(), F32_DATA.as_ptr(), offsets); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32offset_s32() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_s32offset_s32(svptrue_b32(), I32_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_s32offset_s32(svptrue_b32(), I32_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s32offset_u32() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_s32offset_u32(svptrue_b32(), U32_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_s32offset_u32(svptrue_b32(), U32_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64offset_f64() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_s64offset_f64(svptrue_b64(), F64_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_s64offset_f64(svptrue_b64(), F64_DATA.as_ptr(), offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64offset_s64() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_s64offset_s64(svptrue_b64(), I64_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_s64offset_s64(svptrue_b64(), I64_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_s64offset_u64() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_s64offset_u64(svptrue_b64(), U64_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_s64offset_u64(svptrue_b64(), U64_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32offset_f32() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32offset_f32(svptrue_b32(), F32_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_u32offset_f32(svptrue_b32(), F32_DATA.as_ptr(), offsets); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32offset_s32() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32offset_s32(svptrue_b32(), I32_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_u32offset_s32(svptrue_b32(), I32_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32offset_u32() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32offset_u32(svptrue_b32(), U32_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_u32offset_u32(svptrue_b32(), U32_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64offset_f64() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u64offset_f64(svptrue_b64(), F64_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_u64offset_f64(svptrue_b64(), F64_DATA.as_ptr(), offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64offset_s64() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u64offset_s64(svptrue_b64(), I64_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_u64offset_s64(svptrue_b64(), I64_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64offset_u64() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u64offset_u64(svptrue_b64(), U64_DATA.as_ptr(), offsets); + let loaded = svldff1_gather_u64offset_u64(svptrue_b64(), U64_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_f64() { + let bases = svdup_n_u64(F64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_f64(svptrue_b64(), bases); + let loaded = svldff1_gather_u64base_f64(svptrue_b64(), bases); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_s64() { + let bases = svdup_n_u64(I64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_s64(svptrue_b64(), bases); + let loaded = svldff1_gather_u64base_s64(svptrue_b64(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_u64() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_u64(svptrue_b64(), bases); + let loaded = svldff1_gather_u64base_u64(svptrue_b64(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_index_f32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_index_f32( + svptrue_b32(), + bases, + F32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let loaded = svldff1_gather_u32base_index_f32( + svptrue_b32(), + bases, + F32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_index_s32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_index_s32( + svptrue_b32(), + bases, + I32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let loaded = svldff1_gather_u32base_index_s32( + svptrue_b32(), + bases, + I32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_index_u32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_index_u32( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + let loaded = svldff1_gather_u32base_index_u32( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_index_f64() { + let bases = svdup_n_u64(F64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + let loaded = svldff1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_index_s64() { + let bases = svdup_n_u64(I64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + let loaded = svldff1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_index_u64() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + let loaded = svldff1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_offset_f32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + F32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let loaded = svldff1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + F32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + I32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let loaded = svldff1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + I32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + let loaded = svldff1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_offset_f64() { + let bases = svdup_n_u64(F64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let loaded = svldff1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_offset_s64() { + let bases = svdup_n_u64(I64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let loaded = svldff1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_gather_u64base_offset_u64() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let _ = svld1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + let loaded = svldff1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_f32() { + svsetffr(); + let _ = svld1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_f64() { + svsetffr(); + let _ = svld1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s8() { + svsetffr(); + let _ = svld1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntb() as usize; + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s16() { + svsetffr(); + let _ = svld1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s32() { + svsetffr(); + let _ = svld1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s64() { + svsetffr(); + let _ = svld1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u8() { + svsetffr(); + let _ = svld1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntb() as usize; + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u16() { + svsetffr(); + let _ = svld1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u32() { + svsetffr(); + let _ = svld1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u64() { + svsetffr(); + let _ = svld1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_s32offset_s32() { + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_s32offset_s32(svptrue_b8(), I8_DATA.as_ptr(), offsets); + let loaded = svldff1sb_gather_s32offset_s32(svptrue_b8(), I8_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s32offset_s32() { + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_s32offset_s32(svptrue_b16(), I16_DATA.as_ptr(), offsets); + let loaded = svldff1sh_gather_s32offset_s32(svptrue_b16(), I16_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_s32offset_u32() { + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_s32offset_u32(svptrue_b8(), I8_DATA.as_ptr(), offsets); + let loaded = svldff1sb_gather_s32offset_u32(svptrue_b8(), I8_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s32offset_u32() { + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_s32offset_u32(svptrue_b16(), I16_DATA.as_ptr(), offsets); + let loaded = svldff1sh_gather_s32offset_u32(svptrue_b16(), I16_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_s64offset_s64() { + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_s64offset_s64(svptrue_b8(), I8_DATA.as_ptr(), offsets); + let loaded = svldff1sb_gather_s64offset_s64(svptrue_b8(), I8_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s64offset_s64() { + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_s64offset_s64(svptrue_b16(), I16_DATA.as_ptr(), offsets); + let loaded = svldff1sh_gather_s64offset_s64(svptrue_b16(), I16_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_s64offset_s64() { + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sw_gather_s64offset_s64(svptrue_b32(), I32_DATA.as_ptr(), offsets); + let loaded = svldff1sw_gather_s64offset_s64(svptrue_b32(), I32_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_s64offset_u64() { + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_s64offset_u64(svptrue_b8(), I8_DATA.as_ptr(), offsets); + let loaded = svldff1sb_gather_s64offset_u64(svptrue_b8(), I8_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s64offset_u64() { + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_s64offset_u64(svptrue_b16(), I16_DATA.as_ptr(), offsets); + let loaded = svldff1sh_gather_s64offset_u64(svptrue_b16(), I16_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_s64offset_u64() { + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sw_gather_s64offset_u64(svptrue_b32(), I32_DATA.as_ptr(), offsets); + let loaded = svldff1sw_gather_s64offset_u64(svptrue_b32(), I32_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u32offset_s32() { + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_u32offset_s32(svptrue_b8(), I8_DATA.as_ptr(), offsets); + let loaded = svldff1sb_gather_u32offset_s32(svptrue_b8(), I8_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32offset_s32() { + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32offset_s32(svptrue_b16(), I16_DATA.as_ptr(), offsets); + let loaded = svldff1sh_gather_u32offset_s32(svptrue_b16(), I16_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u32offset_u32() { + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_u32offset_u32(svptrue_b8(), I8_DATA.as_ptr(), offsets); + let loaded = svldff1sb_gather_u32offset_u32(svptrue_b8(), I8_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32offset_u32() { + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32offset_u32(svptrue_b16(), I16_DATA.as_ptr(), offsets); + let loaded = svldff1sh_gather_u32offset_u32(svptrue_b16(), I16_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64offset_s64() { + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_u64offset_s64(svptrue_b8(), I8_DATA.as_ptr(), offsets); + let loaded = svldff1sb_gather_u64offset_s64(svptrue_b8(), I8_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64offset_s64() { + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u64offset_s64(svptrue_b16(), I16_DATA.as_ptr(), offsets); + let loaded = svldff1sh_gather_u64offset_s64(svptrue_b16(), I16_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64offset_s64() { + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sw_gather_u64offset_s64(svptrue_b32(), I32_DATA.as_ptr(), offsets); + let loaded = svldff1sw_gather_u64offset_s64(svptrue_b32(), I32_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64offset_u64() { + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_u64offset_u64(svptrue_b8(), I8_DATA.as_ptr(), offsets); + let loaded = svldff1sb_gather_u64offset_u64(svptrue_b8(), I8_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64offset_u64() { + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u64offset_u64(svptrue_b16(), I16_DATA.as_ptr(), offsets); + let loaded = svldff1sh_gather_u64offset_u64(svptrue_b16(), I16_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64offset_u64() { + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sw_gather_u64offset_u64(svptrue_b32(), I32_DATA.as_ptr(), offsets); + let loaded = svldff1sw_gather_u64offset_u64(svptrue_b32(), I32_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + I8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let loaded = svldff1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + I8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let loaded = svldff1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + I8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let loaded = svldff1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + I8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let loaded = svldff1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64base_offset_s64() { + let bases = svdup_n_u64(I8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let loaded = svldff1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_offset_s64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let loaded = + svldff1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_offset_s64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let loaded = + svldff1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64base_offset_u64() { + let bases = svdup_n_u64(I8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let loaded = svldff1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_offset_u64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let loaded = + svldff1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_offset_u64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let loaded = + svldff1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64base_s64() { + let bases = svdup_n_u64(I8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1sb_gather_u64base_s64(svptrue_b8(), bases); + let loaded = svldff1sb_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_s64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_s64(svptrue_b16(), bases); + let loaded = svldff1sh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_s64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_s64(svptrue_b32(), bases); + let loaded = svldff1sw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_gather_u64base_u64() { + let bases = svdup_n_u64(I8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1sb_gather_u64base_u64(svptrue_b8(), bases); + let loaded = svldff1sb_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_u64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_u64(svptrue_b16(), bases); + let loaded = svldff1sh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_u64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_u64(svptrue_b32(), bases); + let loaded = svldff1sw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s16() { + svsetffr(); + let _ = svld1sb_s16(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_s16(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s32() { + svsetffr(); + let _ = svld1sb_s32(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_s32(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_s32() { + svsetffr(); + let _ = svld1sh_s32(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1sh_s32(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s64() { + svsetffr(); + let _ = svld1sb_s64(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_s64(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_s64() { + svsetffr(); + let _ = svld1sh_s64(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1sh_s64(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_s64() { + svsetffr(); + let _ = svld1sw_s64(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldff1sw_s64(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u16() { + svsetffr(); + let _ = svld1sb_u16(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_u16(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u32() { + svsetffr(); + let _ = svld1sb_u32(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_u32(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_u32() { + svsetffr(); + let _ = svld1sh_u32(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1sh_u32(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u64() { + svsetffr(); + let _ = svld1sb_u64(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_u64(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_u64() { + svsetffr(); + let _ = svld1sh_u64(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1sh_u64(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_u64() { + svsetffr(); + let _ = svld1sw_u64(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldff1sw_u64(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s16() { + svsetffr(); + let _ = svld1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s32() { + svsetffr(); + let _ = svld1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_s32() { + svsetffr(); + let _ = svld1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s64() { + svsetffr(); + let _ = svld1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_s64() { + svsetffr(); + let _ = svld1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_vnum_s64() { + svsetffr(); + let _ = svld1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldff1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u16() { + svsetffr(); + let _ = svld1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u32() { + svsetffr(); + let _ = svld1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_u32() { + svsetffr(); + let _ = svld1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u64() { + svsetffr(); + let _ = svld1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_u64() { + svsetffr(); + let _ = svld1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_vnum_u64() { + svsetffr(); + let _ = svld1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldff1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s32index_s32() { + let indices = svindex_s32(0, 1); + svsetffr(); + let _ = svld1sh_gather_s32index_s32(svptrue_b16(), I16_DATA.as_ptr(), indices); + let loaded = svldff1sh_gather_s32index_s32(svptrue_b16(), I16_DATA.as_ptr(), indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s32index_u32() { + let indices = svindex_s32(0, 1); + svsetffr(); + let _ = svld1sh_gather_s32index_u32(svptrue_b16(), I16_DATA.as_ptr(), indices); + let loaded = svldff1sh_gather_s32index_u32(svptrue_b16(), I16_DATA.as_ptr(), indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1sh_gather_s64index_s64(svptrue_b16(), I16_DATA.as_ptr(), indices); + let loaded = svldff1sh_gather_s64index_s64(svptrue_b16(), I16_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1sw_gather_s64index_s64(svptrue_b32(), I32_DATA.as_ptr(), indices); + let loaded = svldff1sw_gather_s64index_s64(svptrue_b32(), I32_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1sh_gather_s64index_u64(svptrue_b16(), I16_DATA.as_ptr(), indices); + let loaded = svldff1sh_gather_s64index_u64(svptrue_b16(), I16_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1sw_gather_s64index_u64(svptrue_b32(), I32_DATA.as_ptr(), indices); + let loaded = svldff1sw_gather_s64index_u64(svptrue_b32(), I32_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32index_s32() { + let indices = svindex_u32(0, 1); + svsetffr(); + let _ = svld1sh_gather_u32index_s32(svptrue_b16(), I16_DATA.as_ptr(), indices); + let loaded = svldff1sh_gather_u32index_s32(svptrue_b16(), I16_DATA.as_ptr(), indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32index_u32() { + let indices = svindex_u32(0, 1); + svsetffr(); + let _ = svld1sh_gather_u32index_u32(svptrue_b16(), I16_DATA.as_ptr(), indices); + let loaded = svldff1sh_gather_u32index_u32(svptrue_b16(), I16_DATA.as_ptr(), indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1sh_gather_u64index_s64(svptrue_b16(), I16_DATA.as_ptr(), indices); + let loaded = svldff1sh_gather_u64index_s64(svptrue_b16(), I16_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1sw_gather_u64index_s64(svptrue_b32(), I32_DATA.as_ptr(), indices); + let loaded = svldff1sw_gather_u64index_s64(svptrue_b32(), I32_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1sh_gather_u64index_u64(svptrue_b16(), I16_DATA.as_ptr(), indices); + let loaded = svldff1sh_gather_u64index_u64(svptrue_b16(), I16_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1sw_gather_u64index_u64(svptrue_b32(), I32_DATA.as_ptr(), indices); + let loaded = svldff1sw_gather_u64index_u64(svptrue_b32(), I32_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32base_index_s32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let loaded = svldff1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u32base_index_u32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let loaded = svldff1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + I16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_index_s64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let loaded = svldff1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_index_s64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let loaded = svldff1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_gather_u64base_index_u64() { + let bases = svdup_n_u64(I16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let loaded = svldff1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_gather_u64base_index_u64() { + let bases = svdup_n_u64(I32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let loaded = svldff1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_s32offset_s32() { + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_s32offset_s32(svptrue_b8(), U8_DATA.as_ptr(), offsets); + let loaded = svldff1ub_gather_s32offset_s32(svptrue_b8(), U8_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s32offset_s32() { + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_s32offset_s32(svptrue_b16(), U16_DATA.as_ptr(), offsets); + let loaded = svldff1uh_gather_s32offset_s32(svptrue_b16(), U16_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_s32offset_u32() { + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_s32offset_u32(svptrue_b8(), U8_DATA.as_ptr(), offsets); + let loaded = svldff1ub_gather_s32offset_u32(svptrue_b8(), U8_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s32offset_u32() { + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_s32offset_u32(svptrue_b16(), U16_DATA.as_ptr(), offsets); + let loaded = svldff1uh_gather_s32offset_u32(svptrue_b16(), U16_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_s64offset_s64() { + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_s64offset_s64(svptrue_b8(), U8_DATA.as_ptr(), offsets); + let loaded = svldff1ub_gather_s64offset_s64(svptrue_b8(), U8_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s64offset_s64() { + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_s64offset_s64(svptrue_b16(), U16_DATA.as_ptr(), offsets); + let loaded = svldff1uh_gather_s64offset_s64(svptrue_b16(), U16_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_s64offset_s64() { + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uw_gather_s64offset_s64(svptrue_b32(), U32_DATA.as_ptr(), offsets); + let loaded = svldff1uw_gather_s64offset_s64(svptrue_b32(), U32_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_s64offset_u64() { + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_s64offset_u64(svptrue_b8(), U8_DATA.as_ptr(), offsets); + let loaded = svldff1ub_gather_s64offset_u64(svptrue_b8(), U8_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s64offset_u64() { + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_s64offset_u64(svptrue_b16(), U16_DATA.as_ptr(), offsets); + let loaded = svldff1uh_gather_s64offset_u64(svptrue_b16(), U16_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_s64offset_u64() { + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uw_gather_s64offset_u64(svptrue_b32(), U32_DATA.as_ptr(), offsets); + let loaded = svldff1uw_gather_s64offset_u64(svptrue_b32(), U32_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u32offset_s32() { + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_u32offset_s32(svptrue_b8(), U8_DATA.as_ptr(), offsets); + let loaded = svldff1ub_gather_u32offset_s32(svptrue_b8(), U8_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32offset_s32() { + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32offset_s32(svptrue_b16(), U16_DATA.as_ptr(), offsets); + let loaded = svldff1uh_gather_u32offset_s32(svptrue_b16(), U16_DATA.as_ptr(), offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u32offset_u32() { + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_u32offset_u32(svptrue_b8(), U8_DATA.as_ptr(), offsets); + let loaded = svldff1ub_gather_u32offset_u32(svptrue_b8(), U8_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32offset_u32() { + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32offset_u32(svptrue_b16(), U16_DATA.as_ptr(), offsets); + let loaded = svldff1uh_gather_u32offset_u32(svptrue_b16(), U16_DATA.as_ptr(), offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64offset_s64() { + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_u64offset_s64(svptrue_b8(), U8_DATA.as_ptr(), offsets); + let loaded = svldff1ub_gather_u64offset_s64(svptrue_b8(), U8_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64offset_s64() { + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u64offset_s64(svptrue_b16(), U16_DATA.as_ptr(), offsets); + let loaded = svldff1uh_gather_u64offset_s64(svptrue_b16(), U16_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64offset_s64() { + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uw_gather_u64offset_s64(svptrue_b32(), U32_DATA.as_ptr(), offsets); + let loaded = svldff1uw_gather_u64offset_s64(svptrue_b32(), U32_DATA.as_ptr(), offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64offset_u64() { + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_u64offset_u64(svptrue_b8(), U8_DATA.as_ptr(), offsets); + let loaded = svldff1ub_gather_u64offset_u64(svptrue_b8(), U8_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64offset_u64() { + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u64offset_u64(svptrue_b16(), U16_DATA.as_ptr(), offsets); + let loaded = svldff1uh_gather_u64offset_u64(svptrue_b16(), U16_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64offset_u64() { + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uw_gather_u64offset_u64(svptrue_b32(), U32_DATA.as_ptr(), offsets); + let loaded = svldff1uw_gather_u64offset_u64(svptrue_b32(), U32_DATA.as_ptr(), offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + U8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let loaded = svldff1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + U8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32base_offset_s32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let loaded = svldff1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svsetffr(); + let _ = svld1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + U8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + let loaded = svldff1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + U8_DATA.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32base_offset_u32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + let loaded = svldff1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64base_offset_s64() { + let bases = svdup_n_u64(U8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let loaded = svldff1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_offset_s64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let loaded = + svldff1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_offset_s64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let loaded = + svldff1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64base_offset_u64() { + let bases = svdup_n_u64(U8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + let loaded = svldff1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_offset_u64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + let loaded = + svldff1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_offset_u64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + let loaded = + svldff1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64base_s64() { + let bases = svdup_n_u64(U8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1ub_gather_u64base_s64(svptrue_b8(), bases); + let loaded = svldff1ub_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_s64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_s64(svptrue_b16(), bases); + let loaded = svldff1uh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_s64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_s64(svptrue_b32(), bases); + let loaded = svldff1uw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_gather_u64base_u64() { + let bases = svdup_n_u64(U8_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svsetffr(); + let _ = svld1ub_gather_u64base_u64(svptrue_b8(), bases); + let loaded = svldff1ub_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_u64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_u64(svptrue_b16(), bases); + let loaded = svldff1uh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_u64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_u64(svptrue_b32(), bases); + let loaded = svldff1uw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s16() { + svsetffr(); + let _ = svld1ub_s16(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_s16(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s32() { + svsetffr(); + let _ = svld1ub_s32(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_s32(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_s32() { + svsetffr(); + let _ = svld1uh_s32(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1uh_s32(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s64() { + svsetffr(); + let _ = svld1ub_s64(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_s64(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_s64() { + svsetffr(); + let _ = svld1uh_s64(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1uh_s64(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_s64() { + svsetffr(); + let _ = svld1uw_s64(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldff1uw_s64(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u16() { + svsetffr(); + let _ = svld1ub_u16(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_u16(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u32() { + svsetffr(); + let _ = svld1ub_u32(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_u32(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_u32() { + svsetffr(); + let _ = svld1uh_u32(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1uh_u32(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u64() { + svsetffr(); + let _ = svld1ub_u64(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_u64(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_u64() { + svsetffr(); + let _ = svld1uh_u64(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1uh_u64(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_u64() { + svsetffr(); + let _ = svld1uw_u64(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldff1uw_u64(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s16() { + svsetffr(); + let _ = svld1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s32() { + svsetffr(); + let _ = svld1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_s32() { + svsetffr(); + let _ = svld1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s64() { + svsetffr(); + let _ = svld1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_s64() { + svsetffr(); + let _ = svld1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_vnum_s64() { + svsetffr(); + let _ = svld1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldff1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u16() { + svsetffr(); + let _ = svld1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u32() { + svsetffr(); + let _ = svld1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_u32() { + svsetffr(); + let _ = svld1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u64() { + svsetffr(); + let _ = svld1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_u64() { + svsetffr(); + let _ = svld1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_vnum_u64() { + svsetffr(); + let _ = svld1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldff1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s32index_s32() { + let indices = svindex_s32(0, 1); + svsetffr(); + let _ = svld1uh_gather_s32index_s32(svptrue_b16(), U16_DATA.as_ptr(), indices); + let loaded = svldff1uh_gather_s32index_s32(svptrue_b16(), U16_DATA.as_ptr(), indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s32index_u32() { + let indices = svindex_s32(0, 1); + svsetffr(); + let _ = svld1uh_gather_s32index_u32(svptrue_b16(), U16_DATA.as_ptr(), indices); + let loaded = svldff1uh_gather_s32index_u32(svptrue_b16(), U16_DATA.as_ptr(), indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1uh_gather_s64index_s64(svptrue_b16(), U16_DATA.as_ptr(), indices); + let loaded = svldff1uh_gather_s64index_s64(svptrue_b16(), U16_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_s64index_s64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1uw_gather_s64index_s64(svptrue_b32(), U32_DATA.as_ptr(), indices); + let loaded = svldff1uw_gather_s64index_s64(svptrue_b32(), U32_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1uh_gather_s64index_u64(svptrue_b16(), U16_DATA.as_ptr(), indices); + let loaded = svldff1uh_gather_s64index_u64(svptrue_b16(), U16_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_s64index_u64() { + let indices = svindex_s64(0, 1); + svsetffr(); + let _ = svld1uw_gather_s64index_u64(svptrue_b32(), U32_DATA.as_ptr(), indices); + let loaded = svldff1uw_gather_s64index_u64(svptrue_b32(), U32_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32index_s32() { + let indices = svindex_u32(0, 1); + svsetffr(); + let _ = svld1uh_gather_u32index_s32(svptrue_b16(), U16_DATA.as_ptr(), indices); + let loaded = svldff1uh_gather_u32index_s32(svptrue_b16(), U16_DATA.as_ptr(), indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32index_u32() { + let indices = svindex_u32(0, 1); + svsetffr(); + let _ = svld1uh_gather_u32index_u32(svptrue_b16(), U16_DATA.as_ptr(), indices); + let loaded = svldff1uh_gather_u32index_u32(svptrue_b16(), U16_DATA.as_ptr(), indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1uh_gather_u64index_s64(svptrue_b16(), U16_DATA.as_ptr(), indices); + let loaded = svldff1uh_gather_u64index_s64(svptrue_b16(), U16_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64index_s64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1uw_gather_u64index_s64(svptrue_b32(), U32_DATA.as_ptr(), indices); + let loaded = svldff1uw_gather_u64index_s64(svptrue_b32(), U32_DATA.as_ptr(), indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1uh_gather_u64index_u64(svptrue_b16(), U16_DATA.as_ptr(), indices); + let loaded = svldff1uh_gather_u64index_u64(svptrue_b16(), U16_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64index_u64() { + let indices = svindex_u64(0, 1); + svsetffr(); + let _ = svld1uw_gather_u64index_u64(svptrue_b32(), U32_DATA.as_ptr(), indices); + let loaded = svldff1uw_gather_u64index_u64(svptrue_b32(), U32_DATA.as_ptr(), indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32base_index_s32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let loaded = svldff1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u32base_index_u32() { + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svsetffr(); + let _ = svld1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + let loaded = svldff1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + U16_DATA.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_index_s64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + let loaded = svldff1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_index_s64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + let loaded = svldff1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_gather_u64base_index_u64() { + let bases = svdup_n_u64(U16_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svsetffr(); + let _ = svld1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + let loaded = svldff1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_gather_u64base_index_u64() { + let bases = svdup_n_u64(U32_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svsetffr(); + let _ = svld1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + let loaded = svldff1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_f32() { + svsetffr(); + let _ = svld1_f32(svptrue_b32(), F32_DATA.as_ptr()); + let loaded = svldnf1_f32(svptrue_b32(), F32_DATA.as_ptr()); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_f64() { + svsetffr(); + let _ = svld1_f64(svptrue_b64(), F64_DATA.as_ptr()); + let loaded = svldnf1_f64(svptrue_b64(), F64_DATA.as_ptr()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s8() { + svsetffr(); + let _ = svld1_s8(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1_s8(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s16() { + svsetffr(); + let _ = svld1_s16(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1_s16(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s32() { + svsetffr(); + let _ = svld1_s32(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldnf1_s32(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s64() { + svsetffr(); + let _ = svld1_s64(svptrue_b64(), I64_DATA.as_ptr()); + let loaded = svldnf1_s64(svptrue_b64(), I64_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u8() { + svsetffr(); + let _ = svld1_u8(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1_u8(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u16() { + svsetffr(); + let _ = svld1_u16(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1_u16(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u32() { + svsetffr(); + let _ = svld1_u32(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldnf1_u32(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u64() { + svsetffr(); + let _ = svld1_u64(svptrue_b64(), U64_DATA.as_ptr()); + let loaded = svldnf1_u64(svptrue_b64(), U64_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_f32() { + svsetffr(); + let _ = svld1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_f64() { + svsetffr(); + let _ = svld1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s8() { + svsetffr(); + let _ = svld1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntb() as usize; + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s16() { + svsetffr(); + let _ = svld1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s32() { + svsetffr(); + let _ = svld1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s64() { + svsetffr(); + let _ = svld1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u8() { + svsetffr(); + let _ = svld1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntb() as usize; + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u16() { + svsetffr(); + let _ = svld1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u32() { + svsetffr(); + let _ = svld1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u64() { + svsetffr(); + let _ = svld1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s16() { + svsetffr(); + let _ = svld1sb_s16(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_s16(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s32() { + svsetffr(); + let _ = svld1sb_s32(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_s32(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_s32() { + svsetffr(); + let _ = svld1sh_s32(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1sh_s32(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s64() { + svsetffr(); + let _ = svld1sb_s64(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_s64(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_s64() { + svsetffr(); + let _ = svld1sh_s64(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1sh_s64(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_s64() { + svsetffr(); + let _ = svld1sw_s64(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldnf1sw_s64(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u16() { + svsetffr(); + let _ = svld1sb_u16(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_u16(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u32() { + svsetffr(); + let _ = svld1sb_u32(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_u32(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_u32() { + svsetffr(); + let _ = svld1sh_u32(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1sh_u32(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u64() { + svsetffr(); + let _ = svld1sb_u64(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_u64(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_u64() { + svsetffr(); + let _ = svld1sh_u64(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1sh_u64(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_u64() { + svsetffr(); + let _ = svld1sw_u64(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldnf1sw_u64(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s16() { + svsetffr(); + let _ = svld1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s32() { + svsetffr(); + let _ = svld1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_s32() { + svsetffr(); + let _ = svld1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s64() { + svsetffr(); + let _ = svld1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_s64() { + svsetffr(); + let _ = svld1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_vnum_s64() { + svsetffr(); + let _ = svld1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldnf1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u16() { + svsetffr(); + let _ = svld1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u32() { + svsetffr(); + let _ = svld1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_u32() { + svsetffr(); + let _ = svld1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u64() { + svsetffr(); + let _ = svld1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_u64() { + svsetffr(); + let _ = svld1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_vnum_u64() { + svsetffr(); + let _ = svld1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldnf1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s16() { + svsetffr(); + let _ = svld1ub_s16(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_s16(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s32() { + svsetffr(); + let _ = svld1ub_s32(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_s32(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_s32() { + svsetffr(); + let _ = svld1uh_s32(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1uh_s32(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s64() { + svsetffr(); + let _ = svld1ub_s64(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_s64(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_s64() { + svsetffr(); + let _ = svld1uh_s64(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1uh_s64(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_s64() { + svsetffr(); + let _ = svld1uw_s64(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldnf1uw_s64(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u16() { + svsetffr(); + let _ = svld1ub_u16(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_u16(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u32() { + svsetffr(); + let _ = svld1ub_u32(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_u32(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_u32() { + svsetffr(); + let _ = svld1uh_u32(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1uh_u32(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u64() { + svsetffr(); + let _ = svld1ub_u64(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_u64(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_u64() { + svsetffr(); + let _ = svld1uh_u64(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1uh_u64(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_u64() { + svsetffr(); + let _ = svld1uw_u64(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldnf1uw_u64(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s16() { + svsetffr(); + let _ = svld1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s32() { + svsetffr(); + let _ = svld1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_s32() { + svsetffr(); + let _ = svld1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s64() { + svsetffr(); + let _ = svld1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_s64() { + svsetffr(); + let _ = svld1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_vnum_s64() { + svsetffr(); + let _ = svld1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldnf1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u16() { + svsetffr(); + let _ = svld1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u32() { + svsetffr(); + let _ = svld1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_u32() { + svsetffr(); + let _ = svld1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u64() { + svsetffr(); + let _ = svld1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_u64() { + svsetffr(); + let _ = svld1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_vnum_u64() { + svsetffr(); + let _ = svld1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldnf1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_f32_with_svstnt1_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svstnt1_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_f64_with_svstnt1_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svstnt1_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s8_with_svstnt1_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s16_with_svstnt1_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s32_with_svstnt1_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s64_with_svstnt1_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u8_with_svstnt1_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svldnt1_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u16_with_svstnt1_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svldnt1_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u32_with_svstnt1_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u64_with_svstnt1_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_f32_with_svstnt1_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svstnt1_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_f64_with_svstnt1_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svstnt1_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s8_with_svstnt1_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s16_with_svstnt1_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s32_with_svstnt1_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s64_with_svstnt1_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u8_with_svstnt1_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svldnt1_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u16_with_svstnt1_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svldnt1_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u32_with_svstnt1_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u64_with_svstnt1_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb() { + svsetffr(); + let loaded = svprfb::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b8(), I64_DATA.as_ptr()); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh() { + svsetffr(); + let loaded = svprfh::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b16(), I64_DATA.as_ptr()); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw() { + svsetffr(); + let loaded = svprfw::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), I64_DATA.as_ptr()); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd() { + svsetffr(); + let loaded = svprfd::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), I64_DATA.as_ptr()); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_s32offset() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_s32offset::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + offsets, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_s32index() { + let indices = svindex_s32(0, 1); + svsetffr(); + let loaded = svprfh_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_s32index() { + let indices = svindex_s32(0, 1); + svsetffr(); + let loaded = svprfw_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_s32index() { + let indices = svindex_s32(0, 1); + svsetffr(); + let loaded = svprfd_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_s64offset() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_s64offset::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + offsets, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_s64index() { + let indices = svindex_s64(0, 1); + svsetffr(); + let loaded = svprfh_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_s64index() { + let indices = svindex_s64(0, 1); + svsetffr(); + let loaded = svprfw_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_s64index() { + let indices = svindex_s64(0, 1); + svsetffr(); + let loaded = svprfd_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u32offset() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_u32offset::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + offsets, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u32index() { + let indices = svindex_u32(0, 1); + svsetffr(); + let loaded = svprfh_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u32index() { + let indices = svindex_u32(0, 1); + svsetffr(); + let loaded = svprfw_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u32index() { + let indices = svindex_u32(0, 1); + svsetffr(); + let loaded = svprfd_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64offset() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_u64offset::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + offsets, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64index() { + let indices = svindex_u64(0, 1); + svsetffr(); + let loaded = svprfh_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64index() { + let indices = svindex_u64(0, 1); + svsetffr(); + let loaded = svprfw_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64index() { + let indices = svindex_u64(0, 1); + svsetffr(); + let loaded = svprfd_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfb_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfh_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfw_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfd_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u32base_offset() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_u32base_offset::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 + 4u32 as i64, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfh_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfw_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfd_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64base_offset() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfb_gather_u64base_offset::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 8u32.try_into().unwrap(), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfh_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfw_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfd_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_vnum() { + svsetffr(); + let loaded = svprfb_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b8(), I64_DATA.as_ptr(), 1); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_vnum() { + svsetffr(); + let loaded = svprfh_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b16(), I64_DATA.as_ptr(), 1); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_vnum() { + svsetffr(); + let loaded = svprfw_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), I64_DATA.as_ptr(), 1); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_vnum() { + svsetffr(); + let loaded = svprfd_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), I64_DATA.as_ptr(), 1); +} +#[simd_test(enable = "sve")] +unsafe fn test_ffr() { + svsetffr(); + let ffr = svrdffr(); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0)); + let pred = svdupq_n_b8( + true, false, true, false, true, false, true, false, true, false, true, false, true, false, + true, false, + ); + svwrffr(pred); + let ffr = svrdffr_z(svptrue_b8()); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1)); +} diff --git a/stdarch/crates/core_arch/src/aarch64/sve/mod.rs b/stdarch/crates/core_arch/src/aarch64/sve/mod.rs new file mode 100644 index 0000000000000..04a92359a0228 --- /dev/null +++ b/stdarch/crates/core_arch/src/aarch64/sve/mod.rs @@ -0,0 +1,382 @@ +//! SVE intrinsics + +#![allow(non_camel_case_types)] + +// `generated.rs` has a `super::*` and this import is for that +use crate::intrinsics::{simd::*, *}; + +#[rustfmt::skip] +mod generated; +#[rustfmt::skip] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::generated::*; + +use crate::{marker::ConstParamTy, mem::transmute}; + +pub(super) trait AsUnsigned { + type Unsigned; + unsafe fn as_unsigned(self) -> Self::Unsigned; +} + +pub(super) trait AsSigned { + type Signed; + unsafe fn as_signed(self) -> Self::Signed; +} + +/// Same as `Into` but with into being unsafe so that it can have the required `target_feature` +pub(super) trait SveInto: Sized { + unsafe fn sve_into(self) -> T; +} + +macro_rules! impl_sve_type { + ($(($v:vis, $elem_type:ty, $name:ident, $elt:literal))*) => ($( + #[doc = concat!("Scalable vector of type ", stringify!($elem_type))] + #[derive(Clone, Copy, Debug)] + #[rustc_scalable_vector($elt)] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($elem_type); + )*) +} + +macro_rules! impl_sve_tuple_type { + ($(($v:vis, $vec_type:ty, $elt:tt, $name:ident))*) => ($( + impl_sve_tuple_type!(@ ($v, $vec_type, $elt, $name)); + )*); + (@ ($v:vis, $vec_type:ty, 2, $name:ident)) => ( + #[doc = concat!("Two-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy, Debug)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type); + ); + (@ ($v:vis, $vec_type:ty, 3, $name:ident)) => ( + #[doc = concat!("Three-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy, Debug)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type, $vec_type); + ); + (@ ($v:vis, $vec_type:ty, 4, $name:ident)) => ( + #[doc = concat!("Four-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy, Debug)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type, $vec_type, $vec_type); + ); +} + +macro_rules! impl_sign_conversions_sv { + ($(($signed:ty, $unsigned:ty))*) => ($( + impl AsUnsigned for $signed { + type Unsigned = $unsigned; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_unsigned(self) -> $unsigned { + transmute_unchecked(self) + } + } + + impl AsSigned for $unsigned { + type Signed = $signed; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_signed(self) -> $signed { + transmute_unchecked(self) + } + } + )*) +} + +macro_rules! impl_sign_conversions { + ($(($signed:ty, $unsigned:ty))*) => ($( + impl AsUnsigned for $signed { + type Unsigned = $unsigned; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_unsigned(self) -> $unsigned { + transmute(self) + } + } + + impl AsSigned for $unsigned { + type Signed = $signed; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_signed(self) -> $signed { + transmute(self) + } + } + )*) +} + +/// LLVM requires the predicate lane count to be the same as the lane count +/// it's working with. However the ACLE only defines one bool type and the +/// instruction set doesn't have this distinction. As a result we have to +/// create these internal types so we can match the LLVM signature. Each of +/// these internal types can be converted to the public `svbool_t` type and +/// the `svbool_t` type can be converted into these. +macro_rules! impl_internal_sve_predicate { + ($(($name:ident, $elt:literal))*) => ($( + impl_sve_type! { + (pub(super), bool, $name, $elt) + } + + impl SveInto for $name { + #[inline] + #[target_feature(enable = "sve")] + unsafe fn sve_into(self) -> svbool_t { + #[allow(improper_ctypes)] + unsafe extern "C" { + #[cfg_attr( + target_arch = "aarch64", + link_name = concat!("llvm.aarch64.sve.convert.to.svbool.nxv", $elt, "i1") + )] + fn convert_to_svbool(b: $name) -> svbool_t; + } + unsafe { convert_to_svbool(self) } + } + } + + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + impl SveInto<$name> for svbool_t { + #[inline] + #[target_feature(enable = "sve")] + unsafe fn sve_into(self) -> $name { + #[allow(improper_ctypes)] + unsafe extern "C" { + #[cfg_attr( + target_arch = "aarch64", + link_name = concat!("llvm.aarch64.sve.convert.from.svbool.nxv", $elt, "i1") + )] + fn convert_from_svbool(b: svbool_t) -> $name; + } + unsafe { convert_from_svbool(self) } + } + } + )*) +} + +impl_sve_type! { + (pub, bool, svbool_t, 16) + + (pub, i8, svint8_t, 16) + (pub, u8, svuint8_t, 16) + + (pub, i16, svint16_t, 8) + (pub, u16, svuint16_t, 8) + (pub, f32, svfloat32_t, 4) + (pub, i32, svint32_t, 4) + (pub, u32, svuint32_t, 4) + (pub, f64, svfloat64_t, 2) + (pub, i64, svint64_t, 2) + (pub, u64, svuint64_t, 2) + + // Internal types: + (pub(super), i8, nxv2i8, 2) + (pub(super), i8, nxv4i8, 4) + (pub(super), i8, nxv8i8, 8) + + (pub(super), i16, nxv2i16, 2) + (pub(super), i16, nxv4i16, 4) + + (pub(super), i32, nxv2i32, 2) + + (pub(super), u8, nxv2u8, 2) + (pub(super), u8, nxv4u8, 4) + (pub(super), u8, nxv8u8, 8) + + (pub(super), u16, nxv2u16, 2) + (pub(super), u16, nxv4u16, 4) + + (pub(super), u32, nxv2u32, 2) +} + +impl_sve_tuple_type! { + (pub, svint8_t, 2, svint8x2_t) + (pub, svuint8_t, 2, svuint8x2_t) + (pub, svint16_t, 2, svint16x2_t) + (pub, svuint16_t, 2, svuint16x2_t) + (pub, svfloat32_t, 2, svfloat32x2_t) + (pub, svint32_t, 2, svint32x2_t) + (pub, svuint32_t, 2, svuint32x2_t) + (pub, svfloat64_t, 2, svfloat64x2_t) + (pub, svint64_t, 2, svint64x2_t) + (pub, svuint64_t, 2, svuint64x2_t) + + (pub, svint8_t, 3, svint8x3_t) + (pub, svuint8_t, 3, svuint8x3_t) + (pub, svint16_t, 3, svint16x3_t) + (pub, svuint16_t, 3, svuint16x3_t) + (pub, svfloat32_t, 3, svfloat32x3_t) + (pub, svint32_t, 3, svint32x3_t) + (pub, svuint32_t, 3, svuint32x3_t) + (pub, svfloat64_t, 3, svfloat64x3_t) + (pub, svint64_t, 3, svint64x3_t) + (pub, svuint64_t, 3, svuint64x3_t) + + (pub, svint8_t, 4, svint8x4_t) + (pub, svuint8_t, 4, svuint8x4_t) + (pub, svint16_t, 4, svint16x4_t) + (pub, svuint16_t, 4, svuint16x4_t) + (pub, svfloat32_t, 4, svfloat32x4_t) + (pub, svint32_t, 4, svint32x4_t) + (pub, svuint32_t, 4, svuint32x4_t) + (pub, svfloat64_t, 4, svfloat64x4_t) + (pub, svint64_t, 4, svint64x4_t) + (pub, svuint64_t, 4, svuint64x4_t) +} + +impl_sign_conversions! { + (i8, u8) + (i16, u16) + (i32, u32) + (i64, u64) + (*const i8, *const u8) + (*const i16, *const u16) + (*const i32, *const u32) + (*const i64, *const u64) + (*mut i8, *mut u8) + (*mut i16, *mut u16) + (*mut i32, *mut u32) + (*mut i64, *mut u64) +} + +impl_sign_conversions_sv! { + (svint8_t, svuint8_t) + (svint16_t, svuint16_t) + (svint32_t, svuint32_t) + (svint64_t, svuint64_t) + + (svint8x2_t, svuint8x2_t) + (svint16x2_t, svuint16x2_t) + (svint32x2_t, svuint32x2_t) + (svint64x2_t, svuint64x2_t) + + (svint8x3_t, svuint8x3_t) + (svint16x3_t, svuint16x3_t) + (svint32x3_t, svuint32x3_t) + (svint64x3_t, svuint64x3_t) + + (svint8x4_t, svuint8x4_t) + (svint16x4_t, svuint16x4_t) + (svint32x4_t, svuint32x4_t) + (svint64x4_t, svuint64x4_t) + + // Internal types: + (nxv2i8, nxv2u8) + (nxv4i8, nxv4u8) + (nxv8i8, nxv8u8) + + (nxv2i16, nxv2u16) + (nxv4i16, nxv4u16) + + (nxv2i32, nxv2u32) +} + +impl_internal_sve_predicate! { + (svbool2_t, 2) + (svbool4_t, 4) + (svbool8_t, 8) +} + +/// Patterns returned by a `PTRUE` +#[repr(i32)] +#[allow(non_camel_case_types)] +#[derive(Clone, Copy, Debug, PartialEq, Eq, ConstParamTy)] +#[non_exhaustive] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub enum svpattern { + /// Activate the largest power-of-two number of elements that is less than the vector length + SV_POW2 = 0, + /// Activate the first element + SV_VL1 = 1, + /// Activate the first two elements + SV_VL2 = 2, + /// Activate the first three elements + SV_VL3 = 3, + /// Activate the first four elements + SV_VL4 = 4, + /// Activate the first five elements + SV_VL5 = 5, + /// Activate the first six elements + SV_VL6 = 6, + /// Activate the first seven elements + SV_VL7 = 7, + /// Activate the first eight elements + SV_VL8 = 8, + /// Activate the first sixteen elements + SV_VL16 = 9, + /// Activate the first thirty-two elements + SV_VL32 = 10, + /// Activate the first sixty-four elements + SV_VL64 = 11, + /// Activate the first one-hundred-and-twenty-eight elements + SV_VL128 = 12, + /// Activate the first two-hundred-and-fifty-six elements + SV_VL256 = 13, + /// Activate the largest multiple-of-four number of elements that is less than the vector length + SV_MUL4 = 29, + /// Activate the largest multiple-of-three number of elements that is less than the vector + /// length + SV_MUL3 = 30, + /// Activate all elements + SV_ALL = 31, +} + +/// Addressing mode for prefetch intrinsics - allows the specification of the expected access +/// kind (read or write), the cache level to load the data, the data retention policy +/// (temporal or streaming) +#[repr(i32)] +#[allow(non_camel_case_types)] +#[derive(Clone, Copy, Debug, PartialEq, Eq, ConstParamTy)] +#[non_exhaustive] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub enum svprfop { + /// Temporal fetch of the addressed location for reading to the L1 cache (i.e. allocate in + /// cache normally) + SV_PLDL1KEEP = 0, + /// Streaming fetch of the addressed location for reading to the L1 cache (i.e. memory only + /// used once) + SV_PLDL1STRM = 1, + /// Temporal fetch of the addressed location for reading to the L2 cache (i.e. allocate in + /// cache normally) + SV_PLDL2KEEP = 2, + /// Streaming fetch of the addressed location for reading to the L2 cache (i.e. memory only + /// used once) + SV_PLDL2STRM = 3, + /// Temporal fetch of the addressed location for reading to the L3 cache (i.e. allocate in + /// cache normally) + SV_PLDL3KEEP = 4, + /// Streaming fetch of the addressed location for reading to the L3 cache (i.e. memory only + /// used once) + SV_PLDL3STRM = 5, + /// Temporal fetch of the addressed location for writing to the L1 cache (i.e. allocate in + /// cache normally) + SV_PSTL1KEEP = 8, + /// Temporal fetch of the addressed location for writing to the L1 cache (i.e. memory only + /// used once) + SV_PSTL1STRM = 9, + /// Temporal fetch of the addressed location for writing to the L2 cache (i.e. allocate in + /// cache normally) + SV_PSTL2KEEP = 10, + /// Temporal fetch of the addressed location for writing to the L2 cache (i.e. memory only + /// used once) + SV_PSTL2STRM = 11, + /// Temporal fetch of the addressed location for writing to the L3 cache (i.e. allocate in + /// cache normally) + SV_PSTL3KEEP = 12, + /// Temporal fetch of the addressed location for writing to the L3 cache (i.e. memory only + /// used once) + SV_PSTL3STRM = 13, +} + +// FIXME(arm-maintainers): On MSVC targets, it seemed like spurious corruption of the FFR was being +// observed non-deterministically on CI. Disabling these tests out of caution on that platform until +// it is investigated. +#[cfg(all(test, not(target_env = "msvc")))] +#[path = "ld_st_tests_aarch64.rs"] +mod ld_st_tests; diff --git a/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs b/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs new file mode 100644 index 0000000000000..e11c20e5dd07d --- /dev/null +++ b/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs @@ -0,0 +1,23881 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(improper_ctypes)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use super::*; + +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv16i8")] + fn _svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svaba_s8(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svaba_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv8i16")] + fn _svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svaba_s16(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svaba_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv4i32")] + fn _svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svaba_s32(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svaba_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv2i64")] + fn _svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svaba_s64(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svaba_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv16i8")] + fn _svaba_u8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svaba_u8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svaba_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv8i16")] + fn _svaba_u16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svaba_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svaba_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv4i32")] + fn _svaba_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svaba_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svaba_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv2i64")] + fn _svaba_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svaba_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svaba_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv8i16")] + fn _svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalb_s16(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svabalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv4i32")] + fn _svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalb_s32(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svabalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv2i64")] + fn _svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalb_s64(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svabalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv8i16")] + fn _svabalb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svabalb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv4i32")] + fn _svabalb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svabalb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv2i64")] + fn _svabalb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svabalb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv8i16")] + fn _svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalt_s16(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svabalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv4i32")] + fn _svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalt_s32(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svabalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv2i64")] + fn _svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalt_s64(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svabalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv8i16")] + fn _svabalt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svabalt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv4i32")] + fn _svabalt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svabalt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv2i64")] + fn _svabalt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svabalt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv8i16")] + fn _svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlb_s16(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svabdlb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv4i32")] + fn _svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlb_s32(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svabdlb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv2i64")] + fn _svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlb_s64(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svabdlb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv8i16")] + fn _svabdlb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svabdlb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv4i32")] + fn _svabdlb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svabdlb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv2i64")] + fn _svabdlb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svabdlb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv8i16")] + fn _svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlt_s16(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svabdlt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv4i32")] + fn _svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlt_s32(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svabdlt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv2i64")] + fn _svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlt_s64(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svabdlt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv8i16")] + fn _svabdlt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svabdlt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv4i32")] + fn _svabdlt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svabdlt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv2i64")] + fn _svabdlt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svabdlt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv8i16")] + fn _svadalp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svadalp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + svadalp_s16_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_z(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + svadalp_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv4i32")] + fn _svadalp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svadalp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + svadalp_s32_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_z(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + svadalp_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv2i64")] + fn _svadalp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svadalp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + svadalp_s64_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_z(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + svadalp_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv8i16")] + fn _svadalp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svadalp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + svadalp_u16_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + svadalp_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv4i32")] + fn _svadalp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svadalp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + svadalp_u32_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + svadalp_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv2i64")] + fn _svadalp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svadalp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + svadalp_u64_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + svadalp_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclb.nxv4i32")] + fn _svadclb_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svadclb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svadclb_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclb.nxv2i64")] + fn _svadclb_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svadclb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svadclb_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclt.nxv4i32")] + fn _svadclt_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svadclt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svadclt_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclt.nxv2i64")] + fn _svadclt_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svadclt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svadclt_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv8i16")] + fn _svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svaddhnb_s16(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svaddhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv4i32")] + fn _svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svaddhnb_s32(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svaddhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv2i64")] + fn _svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svaddhnb_s64(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svaddhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svaddhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svaddhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svaddhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svaddhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svaddhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svaddhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv8i16")] + fn _svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svaddhnt_s16(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svaddhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv4i32")] + fn _svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svaddhnt_s32(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svaddhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv2i64")] + fn _svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svaddhnt_s64(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svaddhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svaddhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svaddhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svaddhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svaddhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svaddhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svaddhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv8i16")] + fn _svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlb_s16(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv4i32")] + fn _svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlb_s32(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv2i64")] + fn _svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlb_s64(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv8i16")] + fn _svaddlb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svaddlb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv4i32")] + fn _svaddlb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svaddlb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv2i64")] + fn _svaddlb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svaddlb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv8i16" + )] + fn _svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlbt_s16(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlbt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv4i32" + )] + fn _svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlbt_s32(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlbt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv2i64" + )] + fn _svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlbt_s64(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlbt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv8i16")] + fn _svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlt_s16(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv4i32")] + fn _svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlt_s32(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv2i64")] + fn _svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlt_s64(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv8i16")] + fn _svaddlt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svaddlt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv4i32")] + fn _svaddlt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svaddlt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv2i64")] + fn _svaddlt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svaddlt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddp.nxv4f32")] + fn _svaddp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svaddp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svaddp_f32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddp.nxv2f64")] + fn _svaddp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svaddp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svaddp_f64_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv16i8")] + fn _svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaddp_s8_m(pg, op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svaddp_s8_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv8i16")] + fn _svaddp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svaddp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svaddp_s16_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv4i32")] + fn _svaddp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svaddp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svaddp_s32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv2i64")] + fn _svaddp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svaddp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svaddp_s64_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svaddp_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svaddp_u8_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svaddp_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svaddp_u16_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svaddp_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svaddp_u32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svaddp_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svaddp_u64_m(pg, op1, op2) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv8i16")] + fn _svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwb_s16(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svaddwb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv4i32")] + fn _svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwb_s32(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svaddwb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv2i64")] + fn _svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwb_s64(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svaddwb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv8i16")] + fn _svaddwb_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svaddwb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv4i32")] + fn _svaddwb_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svaddwb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv2i64")] + fn _svaddwb_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svaddwb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv8i16")] + fn _svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwt_s16(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svaddwt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv4i32")] + fn _svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwt_s32(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svaddwt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv2i64")] + fn _svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwt_s64(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svaddwt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv8i16")] + fn _svaddwt_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svaddwt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv4i32")] + fn _svaddwt_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svaddwt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv2i64")] + fn _svaddwt_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svaddwt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "AES single round decryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesd[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesd))] +pub fn svaesd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesd")] + fn _svaesd_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaesd_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "AES single round encryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaese[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aese))] +pub fn svaese_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aese")] + fn _svaese_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaese_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "AES inverse mix columns"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesimc[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesimc))] +pub fn svaesimc_u8(op: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesimc")] + fn _svaesimc_u8(op: svint8_t) -> svint8_t; + } + unsafe { _svaesimc_u8(op.as_signed()).as_unsigned() } +} +#[doc = "AES mix columns"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesmc[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesmc))] +pub fn svaesmc_u8(op: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesmc")] + fn _svaesmc_u8(op: svint8_t) -> svint8_t; + } + unsafe { _svaesmc_u8(op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv16i8")] + fn _svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbcax_s8(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbcax_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv8i16")] + fn _svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbcax_s16(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbcax_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv4i32")] + fn _svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbcax_s32(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbcax_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv2i64")] + fn _svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbcax_s64(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbcax_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbcax_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbcax_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbcax_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbcax_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbcax_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbcax_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbcax_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbcax_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv16i8")] + fn _svbdep_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbdep_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbdep_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv8i16")] + fn _svbdep_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbdep_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbdep_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv4i32")] + fn _svbdep_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbdep_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbdep_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv2i64")] + fn _svbdep_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbdep_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbdep_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv16i8")] + fn _svbext_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbext_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbext_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv8i16")] + fn _svbext_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbext_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbext_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv4i32")] + fn _svbext_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbext_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbext_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv2i64")] + fn _svbext_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbext_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbext_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv16i8")] + fn _svbgrp_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbgrp_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbgrp_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv8i16")] + fn _svbgrp_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbgrp_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbgrp_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv4i32")] + fn _svbgrp_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbgrp_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbgrp_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv2i64")] + fn _svbgrp_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbgrp_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbgrp_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv16i8")] + fn _svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl1n_s8(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl1n_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv8i16")] + fn _svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl1n_s16(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl1n_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv4i32")] + fn _svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl1n_s32(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl1n_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv2i64")] + fn _svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl1n_s64(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl1n_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl1n_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl1n_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl1n_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl1n_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl1n_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl1n_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl1n_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl1n_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv16i8")] + fn _svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl2n_s8(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl2n_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv8i16")] + fn _svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl2n_s16(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl2n_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv4i32")] + fn _svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl2n_s32(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl2n_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv2i64")] + fn _svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl2n_s64(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl2n_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl2n_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl2n_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl2n_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl2n_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl2n_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl2n_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl2n_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl2n_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv16i8")] + fn _svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl_s8(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv8i16")] + fn _svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl_s16(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv4i32")] + fn _svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl_s32(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv2i64")] + fn _svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl_s64(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv16i8")] + fn _svcadd_s8(op1: svint8_t, op2: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svcadd_s8(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv8i16")] + fn _svcadd_s16(op1: svint16_t, op2: svint16_t, imm_rotation: i32) -> svint16_t; + } + unsafe { _svcadd_s16(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv4i32")] + fn _svcadd_s32(op1: svint32_t, op2: svint32_t, imm_rotation: i32) -> svint32_t; + } + unsafe { _svcadd_s32(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv2i64")] + fn _svcadd_s64(op1: svint64_t, op2: svint64_t, imm_rotation: i32) -> svint64_t; + } + unsafe { _svcadd_s64(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cdot.lane.nxv4i32" + )] + fn _svcdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcdot_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cdot.lane.nxv2i64" + )] + fn _svcdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcdot_lane_s64(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))] +pub fn svcdot_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cdot.nxv4i32")] + fn _svcdot_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcdot_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))] +pub fn svcdot_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cdot.nxv2i64")] + fn _svcdot_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcdot_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmla.lane.x.nxv8i16" + )] + fn _svcmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svcmla_lane_s16(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmla.lane.x.nxv4i32" + )] + fn _svcmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcmla_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_lane_s16::( + op1.as_signed(), + op2.as_signed(), + op3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_lane_s32::( + op1.as_signed(), + op2.as_signed(), + op3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv16i8")] + fn _svcmla_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svcmla_s8(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv8i16")] + fn _svcmla_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svcmla_s16(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv4i32")] + fn _svcmla_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcmla_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv2i64")] + fn _svcmla_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcmla_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u8( + op1: svuint8_t, + op2: svuint8_t, + op3: svuint8_t, +) -> svuint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s8::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Up convert long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtlt))] +pub fn svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtlt.f64f32")] + fn _svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat32_t) + -> svfloat64_t; + } + unsafe { _svcvtlt_f64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Up convert long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtlt))] +pub fn svcvtlt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe { svcvtlt_f64_f32_m(crate::intrinsics::transmute_unchecked(op), pg, op) } +} +#[doc = "Down convert and narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtnt))] +pub fn svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtnt.f32f64")] + fn _svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtnt_f32_f64_m(even, pg.sve_into(), op) } +} +#[doc = "Down convert and narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtnt))] +pub fn svcvtnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtnt_f32_f64_m(even, pg, op) +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtx.f32f64")] + fn _svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtx_f32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe { svcvtx_f32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtx_f32_f64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Down convert, rounding to odd (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtxnt))] +pub fn svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtxnt.f32f64")] + fn _svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtxnt_f32_f64_m(even, pg.sve_into(), op) } +} +#[doc = "Down convert, rounding to odd (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtxnt))] +pub fn svcvtxnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtxnt_f32_f64_m(even, pg, op) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv16i8")] + fn _sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _sveor3_s8(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + sveor3_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv8i16")] + fn _sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _sveor3_s16(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + sveor3_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv4i32")] + fn _sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _sveor3_s32(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + sveor3_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv2i64")] + fn _sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _sveor3_s64(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + sveor3_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { sveor3_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + sveor3_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { sveor3_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + sveor3_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { sveor3_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + sveor3_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { sveor3_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + sveor3_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv16i8")] + fn _sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveorbt_s8(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s8(odd: svint8_t, op1: svint8_t, op2: i8) -> svint8_t { + sveorbt_s8(odd, op1, svdup_n_s8(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv8i16")] + fn _sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveorbt_s16(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s16(odd: svint16_t, op1: svint16_t, op2: i16) -> svint16_t { + sveorbt_s16(odd, op1, svdup_n_s16(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv4i32")] + fn _sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveorbt_s32(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s32(odd: svint32_t, op1: svint32_t, op2: i32) -> svint32_t { + sveorbt_s32(odd, op1, svdup_n_s32(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv2i64")] + fn _sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveorbt_s64(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s64(odd: svint64_t, op1: svint64_t, op2: i64) -> svint64_t { + sveorbt_s64(odd, op1, svdup_n_s64(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u8(odd: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveorbt_s8(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u8(odd: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveorbt_u8(odd, op1, svdup_n_u8(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u16(odd: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveorbt_s16(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u16(odd: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveorbt_u16(odd, op1, svdup_n_u16(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u32(odd: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveorbt_s32(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u32(odd: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveorbt_u32(odd, op1, svdup_n_u32(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u64(odd: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveorbt_s64(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u64(odd: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveorbt_u64(odd, op1, svdup_n_u64(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv16i8")] + fn _sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveortb_s8(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s8(even: svint8_t, op1: svint8_t, op2: i8) -> svint8_t { + sveortb_s8(even, op1, svdup_n_s8(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv8i16")] + fn _sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveortb_s16(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s16(even: svint16_t, op1: svint16_t, op2: i16) -> svint16_t { + sveortb_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv4i32")] + fn _sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveortb_s32(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s32(even: svint32_t, op1: svint32_t, op2: i32) -> svint32_t { + sveortb_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv2i64")] + fn _sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveortb_s64(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s64(even: svint64_t, op1: svint64_t, op2: i64) -> svint64_t { + sveortb_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u8(even: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveortb_s8(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u8(even: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveortb_u8(even, op1, svdup_n_u8(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u16(even: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveortb_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u16(even: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveortb_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u32(even: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveortb_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u32(even: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveortb_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u64(even: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveortb_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u64(even: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveortb_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv16i8")] + fn _svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhadd_s8_m(pg, op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhadd_s8_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv8i16")] + fn _svhadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhadd_s16_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv4i32")] + fn _svhadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhadd_s32_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv2i64")] + fn _svhadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhadd_s64_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv16i8")] + fn _svhadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhadd_u8_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv8i16")] + fn _svhadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhadd_u16_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv4i32")] + fn _svhadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhadd_u32_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv2i64")] + fn _svhadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhadd_u64_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histcnt.nxv4i32" + )] + fn _svhistcnt_s32_z(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhistcnt_s32_z(pg.sve_into(), op1, op2).as_unsigned() } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histcnt.nxv2i64" + )] + fn _svhistcnt_s64_z(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhistcnt_s64_z(pg.sve_into(), op1, op2).as_unsigned() } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svhistcnt_s32_z(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svhistcnt_s64_z(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Count matching elements in 128-bit segments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histseg))] +pub fn svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histseg.nxv16i8" + )] + fn _svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhistseg_s8(op1, op2).as_unsigned() } +} +#[doc = "Count matching elements in 128-bit segments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histseg))] +pub fn svhistseg_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svhistseg_s8(op1.as_signed(), op2.as_signed()) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv16i8")] + fn _svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsub_s8_m(pg, op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsub_s8_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv8i16")] + fn _svhsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsub_s16_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv4i32")] + fn _svhsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsub_s32_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv2i64")] + fn _svhsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsub_s64_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv16i8")] + fn _svhsub_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsub_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsub_u8_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv8i16")] + fn _svhsub_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsub_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsub_u16_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv4i32")] + fn _svhsub_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsub_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsub_u32_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv2i64")] + fn _svhsub_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsub_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsub_u64_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv16i8")] + fn _svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsubr_s8_m(pg, op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsubr_s8_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv8i16")] + fn _svhsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsubr_s16_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv4i32")] + fn _svhsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsubr_s32_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv2i64")] + fn _svhsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsubr_s64_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv16i8")] + fn _svhsubr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsubr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsubr_u8_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv8i16")] + fn _svhsubr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsubr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsubr_u16_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv4i32")] + fn _svhsubr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsubr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsubr_u32_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv2i64")] + fn _svhsubr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsubr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsubr_u64_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2f64" + )] + fn _svldnt1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svldnt1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i64" + )] + fn _svldnt1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svldnt1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svldnt1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svldnt1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svldnt1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svldnt1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2f64" + )] + fn _svldnt1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svldnt1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i64" + )] + fn _svldnt1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svldnt1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svldnt1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4f32" + )] + fn _svldnt1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldnt1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i32" + )] + fn _svldnt1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldnt1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svldnt1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svldnt1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svldnt1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svldnt1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svldnt1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svldnt1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svldnt1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svldnt1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svldnt1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svldnt1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svldnt1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svldnt1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svldnt1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svldnt1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i8" + )] + fn _svldnt1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i16" + )] + fn _svldnt1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i32" + )] + fn _svldnt1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8" + )] + fn _svldnt1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16" + )] + fn _svldnt1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldnt1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldnt1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldnt1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldnt1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldnt1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i16" + )] + fn _svldnt1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i32" + )] + fn _svldnt1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i8" + )] + fn _svldnt1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i16" + )] + fn _svldnt1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i32" + )] + fn _svldnt1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svldnt1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svldnt1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8" + )] + fn _svldnt1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16" + )] + fn _svldnt1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldnt1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldnt1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldnt1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldnt1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldnt1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldnt1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i16" + )] + fn _svldnt1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i32" + )] + fn _svldnt1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.flogb.nxv4f32")] + fn _svlogb_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svlogb_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe { svlogb_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t { + svlogb_f32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.flogb.nxv2f64")] + fn _svlogb_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svlogb_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe { svlogb_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t { + svlogb_f64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.match.nxv16i8")] + fn _svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svmatch_s8(pg, op1, op2) } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.match.nxv8i16")] + fn _svmatch_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svmatch_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svmatch_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svmatch_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmp.nxv4f32" + )] + fn _svmaxnmp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxnmp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnmp_f32_m(pg, op1, op2) +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmp.nxv2f64" + )] + fn _svmaxnmp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxnmp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnmp_f64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxp.nxv4f32")] + fn _svmaxp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxp_f32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxp.nxv2f64")] + fn _svmaxp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxp_f64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv16i8")] + fn _svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmaxp_s8_m(pg, op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmaxp_s8_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv8i16")] + fn _svmaxp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmaxp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmaxp_s16_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv4i32")] + fn _svmaxp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmaxp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmaxp_s32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv2i64")] + fn _svmaxp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmaxp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmaxp_s64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv16i8")] + fn _svmaxp_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmaxp_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmaxp_u8_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv8i16")] + fn _svmaxp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmaxp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmaxp_u16_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv4i32")] + fn _svmaxp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmaxp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmaxp_u32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv2i64")] + fn _svmaxp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmaxp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmaxp_u64_m(pg, op1, op2) +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmp.nxv4f32" + )] + fn _svminnmp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminnmp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnmp_f32_m(pg, op1, op2) +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmp.nxv2f64" + )] + fn _svminnmp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminnmp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnmp_f64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminp.nxv4f32")] + fn _svminp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminp_f32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminp.nxv2f64")] + fn _svminp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminp_f64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv16i8")] + fn _svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svminp_s8_m(pg, op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svminp_s8_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv8i16")] + fn _svminp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svminp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svminp_s16_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv4i32")] + fn _svminp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svminp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svminp_s32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv2i64")] + fn _svminp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svminp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svminp_s64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv16i8")] + fn _svminp_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svminp_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svminp_u8_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv8i16")] + fn _svminp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svminp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svminp_u16_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv4i32")] + fn _svminp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svminp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svminp_u32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv2i64")] + fn _svminp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svminp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svminp_u64_m(pg, op1, op2) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv8i16" + )] + fn _svmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svmla_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv4i32" + )] + fn _svmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmla_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv2i64" + )] + fn _svmla_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmla_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { + svmla_lane_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { + svmla_lane_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { + svmla_lane_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalb.lane.nxv4i32" + )] + fn _svmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlalb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalb.lane.nxv2i64" + )] + fn _svmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlalb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalb.lane.nxv4i32" + )] + fn _svmlalb_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlalb_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalb.lane.nxv2i64" + )] + fn _svmlalb_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlalb_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv8i16")] + fn _svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalb_s16(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv4i32")] + fn _svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalb_s32(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv2i64")] + fn _svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalb_s64(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv8i16")] + fn _svmlalb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlalb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv4i32")] + fn _svmlalb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlalb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv2i64")] + fn _svmlalb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlalb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalt.lane.nxv4i32" + )] + fn _svmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlalt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalt.lane.nxv2i64" + )] + fn _svmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlalt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalt.lane.nxv4i32" + )] + fn _svmlalt_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlalt_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalt.lane.nxv2i64" + )] + fn _svmlalt_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlalt_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv8i16")] + fn _svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalt_s16(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv4i32")] + fn _svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalt_s32(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv2i64")] + fn _svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalt_s64(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv8i16")] + fn _svmlalt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlalt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv4i32")] + fn _svmlalt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlalt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv2i64")] + fn _svmlalt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlalt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv8i16" + )] + fn _svmls_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svmls_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv4i32" + )] + fn _svmls_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmls_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv2i64" + )] + fn _svmls_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmls_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { + svmls_lane_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { + svmls_lane_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { + svmls_lane_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslb.lane.nxv4i32" + )] + fn _svmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlslb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslb.lane.nxv2i64" + )] + fn _svmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlslb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslb.lane.nxv4i32" + )] + fn _svmlslb_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlslb_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslb.lane.nxv2i64" + )] + fn _svmlslb_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlslb_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv8i16")] + fn _svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslb_s16(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlslb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv4i32")] + fn _svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslb_s32(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlslb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv2i64")] + fn _svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslb_s64(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlslb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv8i16")] + fn _svmlslb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlslb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv4i32")] + fn _svmlslb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlslb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv2i64")] + fn _svmlslb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlslb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslt.lane.nxv4i32" + )] + fn _svmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlslt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslt.lane.nxv2i64" + )] + fn _svmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlslt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslt.lane.nxv4i32" + )] + fn _svmlslt_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlslt_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslt.lane.nxv2i64" + )] + fn _svmlslt_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlslt_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv8i16")] + fn _svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslt_s16(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlslt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv4i32")] + fn _svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslt_s32(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlslt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv2i64")] + fn _svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslt_s64(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlslt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv8i16")] + fn _svmlslt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlslt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv4i32")] + fn _svmlslt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlslt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv2i64")] + fn _svmlslt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlslt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s16(op: svint8_t) -> svint16_t { + svshllb_n_s16::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s32(op: svint16_t) -> svint32_t { + svshllb_n_s32::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s64(op: svint32_t) -> svint64_t { + svshllb_n_s64::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u16(op: svuint8_t) -> svuint16_t { + svshllb_n_u16::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u32(op: svuint16_t) -> svuint32_t { + svshllb_n_u32::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u64(op: svuint32_t) -> svuint64_t { + svshllb_n_u64::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s16(op: svint8_t) -> svint16_t { + svshllt_n_s16::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s32(op: svint16_t) -> svint32_t { + svshllt_n_s32::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s64(op: svint32_t) -> svint64_t { + svshllt_n_s64::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u16(op: svuint8_t) -> svuint16_t { + svshllt_n_u16::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u32(op: svuint16_t) -> svuint32_t { + svshllt_n_u32::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u64(op: svuint32_t) -> svuint64_t { + svshllt_n_u64::<0>(op) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))] +pub fn svmul_lane_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmul.lane.nxv4f32" + )] + fn _svmul_lane_f32(op1: svfloat32_t, op2: svfloat32_t, imm_index: i32) -> svfloat32_t; + } + unsafe { _svmul_lane_f32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))] +pub fn svmul_lane_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmul.lane.nxv2f64" + )] + fn _svmul_lane_f64(op1: svfloat64_t, op2: svfloat64_t, imm_index: i32) -> svfloat64_t; + } + unsafe { _svmul_lane_f64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv8i16" + )] + fn _svmul_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svmul_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv4i32" + )] + fn _svmul_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmul_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv2i64" + )] + fn _svmul_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmul_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { svmul_lane_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { svmul_lane_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { svmul_lane_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullb.lane.nxv4i32" + )] + fn _svmullb_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullb_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullb.lane.nxv2i64" + )] + fn _svmullb_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullb_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullb.lane.nxv4i32" + )] + fn _svmullb_lane_u32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullb_lane_u32(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullb.lane.nxv2i64" + )] + fn _svmullb_lane_u64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullb_lane_u64(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv8i16")] + fn _svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullb_s16(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svmullb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv4i32")] + fn _svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullb_s32(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svmullb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv2i64")] + fn _svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullb_s64(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svmullb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv8i16")] + fn _svmullb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svmullb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv4i32")] + fn _svmullb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svmullb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv2i64")] + fn _svmullb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svmullb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullt.lane.nxv4i32" + )] + fn _svmullt_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullt_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullt.lane.nxv2i64" + )] + fn _svmullt_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullt_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullt.lane.nxv4i32" + )] + fn _svmullt_lane_u32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullt_lane_u32(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullt.lane.nxv2i64" + )] + fn _svmullt_lane_u64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullt_lane_u64(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv8i16")] + fn _svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullt_s16(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svmullt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv4i32")] + fn _svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullt_s32(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svmullt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv2i64")] + fn _svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullt_s64(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svmullt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv8i16")] + fn _svmullt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svmullt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv4i32")] + fn _svmullt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svmullt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv2i64")] + fn _svmullt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svmullt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv16i8")] + fn _svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svnbsl_s8(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svnbsl_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv8i16")] + fn _svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svnbsl_s16(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svnbsl_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv4i32")] + fn _svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svnbsl_s32(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svnbsl_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv2i64")] + fn _svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svnbsl_s64(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svnbsl_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svnbsl_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svnbsl_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svnbsl_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svnbsl_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svnbsl_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svnbsl_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svnbsl_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svnbsl_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nmatch.nxv16i8")] + fn _svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svnmatch_s8(pg, op1, op2) } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nmatch.nxv8i16")] + fn _svnmatch_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svnmatch_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svnmatch_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svnmatch_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmul))] +pub fn svpmul_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pmul.nxv16i8")] + fn _svpmul_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmul_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmul))] +pub fn svpmul_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmul_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv16i8" + )] + fn _svpmullb_pair_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmullb_pair_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmullb_pair_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv4i32" + )] + fn _svpmullb_pair_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svpmullb_pair_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svpmullb_pair_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv2i64" + )] + fn _svpmullb_pair_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svpmullb_pair_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svpmullb_pair_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullb_pair_u8(op1, op2)) } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svpmullb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullb_pair_u32(op1, op2)) } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svpmullb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv16i8" + )] + fn _svpmullt_pair_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmullt_pair_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmullt_pair_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv4i32" + )] + fn _svpmullt_pair_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svpmullt_pair_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svpmullt_pair_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv2i64" + )] + fn _svpmullt_pair_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svpmullt_pair_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svpmullt_pair_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullt_pair_u8(op1, op2)) } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svpmullt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullt_pair_u32(op1, op2)) } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svpmullt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv16i8")] + fn _svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svqabs_s8_m(inactive, pg, op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svqabs_s8_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svqabs_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv8i16")] + fn _svqabs_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svqabs_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svqabs_s16_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svqabs_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv4i32")] + fn _svqabs_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svqabs_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svqabs_s32_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svqabs_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv2i64")] + fn _svqabs_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svqabs_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svqabs_s64_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svqabs_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv16i8")] + fn _svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_s8_m(pg, op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqadd_s8_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv8i16")] + fn _svqadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqadd_s16_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv4i32")] + fn _svqadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqadd_s32_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv2i64")] + fn _svqadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqadd_s64_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv16i8")] + fn _svqadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqadd_u8_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv8i16")] + fn _svqadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqadd_u16_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv4i32")] + fn _svqadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqadd_u32_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv2i64")] + fn _svqadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqadd_u64_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv16i8" + )] + fn _svqcadd_s8(op1: svint8_t, op2: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svqcadd_s8(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv8i16" + )] + fn _svqcadd_s16(op1: svint16_t, op2: svint16_t, imm_rotation: i32) -> svint16_t; + } + unsafe { _svqcadd_s16(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv4i32" + )] + fn _svqcadd_s32(op1: svint32_t, op2: svint32_t, imm_rotation: i32) -> svint32_t; + } + unsafe { _svqcadd_s32(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv2i64" + )] + fn _svqcadd_s64(op1: svint64_t, op2: svint64_t, imm_rotation: i32) -> svint64_t; + } + unsafe { _svqcadd_s64(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))] +pub fn svqdmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.lane.nxv4i32" + )] + fn _svqdmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlalb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))] +pub fn svqdmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.lane.nxv2i64" + )] + fn _svqdmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlalb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv8i16" + )] + fn _svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalb_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv4i32" + )] + fn _svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalb_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv2i64" + )] + fn _svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalb_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv8i16" + )] + fn _svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalbt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalbt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv4i32" + )] + fn _svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalbt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalbt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv2i64" + )] + fn _svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalbt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalbt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))] +pub fn svqdmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.lane.nxv4i32" + )] + fn _svqdmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlalt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))] +pub fn svqdmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.lane.nxv2i64" + )] + fn _svqdmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlalt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv8i16" + )] + fn _svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv4i32" + )] + fn _svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv2i64" + )] + fn _svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))] +pub fn svqdmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.lane.nxv4i32" + )] + fn _svqdmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlslb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))] +pub fn svqdmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.lane.nxv2i64" + )] + fn _svqdmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlslb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv8i16" + )] + fn _svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslb_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv4i32" + )] + fn _svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslb_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv2i64" + )] + fn _svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslb_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv8i16" + )] + fn _svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslbt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslbt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv4i32" + )] + fn _svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslbt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslbt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv2i64" + )] + fn _svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslbt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslbt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))] +pub fn svqdmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.lane.nxv4i32" + )] + fn _svqdmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlslt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))] +pub fn svqdmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.lane.nxv2i64" + )] + fn _svqdmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlslt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv8i16" + )] + fn _svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv4i32" + )] + fn _svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv2i64" + )] + fn _svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv8i16" + )] + fn _svqdmulh_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svqdmulh_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv4i32" + )] + fn _svqdmulh_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmulh_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv2i64" + )] + fn _svqdmulh_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmulh_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv16i8" + )] + fn _svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqdmulh_s8(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqdmulh_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv8i16" + )] + fn _svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqdmulh_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqdmulh_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv4i32" + )] + fn _svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqdmulh_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqdmulh_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv2i64" + )] + fn _svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqdmulh_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqdmulh_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))] +pub fn svqdmullb_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.lane.nxv4i32" + )] + fn _svqdmullb_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmullb_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))] +pub fn svqdmullb_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.lane.nxv2i64" + )] + fn _svqdmullb_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmullb_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv8i16" + )] + fn _svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svqdmullb_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svqdmullb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv4i32" + )] + fn _svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svqdmullb_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svqdmullb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv2i64" + )] + fn _svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svqdmullb_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svqdmullb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))] +pub fn svqdmullt_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.lane.nxv4i32" + )] + fn _svqdmullt_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmullt_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))] +pub fn svqdmullt_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.lane.nxv2i64" + )] + fn _svqdmullt_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmullt_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv8i16" + )] + fn _svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svqdmullt_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svqdmullt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv4i32" + )] + fn _svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svqdmullt_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svqdmullt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv2i64" + )] + fn _svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svqdmullt_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svqdmullt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv16i8")] + fn _svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svqneg_s8_m(inactive, pg, op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svqneg_s8_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svqneg_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv8i16")] + fn _svqneg_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svqneg_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svqneg_s16_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svqneg_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv4i32")] + fn _svqneg_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svqneg_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svqneg_s32_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svqneg_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv2i64")] + fn _svqneg_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svqneg_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svqneg_s64_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svqneg_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svqrdcmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16" + )] + fn _svqrdcmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svqrdcmlah_lane_s16(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svqrdcmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32" + )] + fn _svqrdcmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svqrdcmlah_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s8( + op1: svint8_t, + op2: svint8_t, + op3: svint8_t, +) -> svint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv16i8" + )] + fn _svqrdcmlah_s8( + op1: svint8_t, + op2: svint8_t, + op3: svint8_t, + imm_rotation: i32, + ) -> svint8_t; + } + unsafe { _svqrdcmlah_s8(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv8i16" + )] + fn _svqrdcmlah_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svqrdcmlah_s16(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv4i32" + )] + fn _svqrdcmlah_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svqrdcmlah_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv2i64" + )] + fn _svqrdcmlah_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svqrdcmlah_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv8i16" + )] + fn _svqrdmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svqrdmlah_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv4i32" + )] + fn _svqrdmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqrdmlah_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv2i64" + )] + fn _svqrdmlah_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqrdmlah_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv16i8" + )] + fn _svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svqrdmlah_s8(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svqrdmlah_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv8i16" + )] + fn _svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svqrdmlah_s16(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svqrdmlah_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv4i32" + )] + fn _svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svqrdmlah_s32(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svqrdmlah_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv2i64" + )] + fn _svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svqrdmlah_s64(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svqrdmlah_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16" + )] + fn _svqrdmlsh_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svqrdmlsh_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32" + )] + fn _svqrdmlsh_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqrdmlsh_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64" + )] + fn _svqrdmlsh_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqrdmlsh_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv16i8" + )] + fn _svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svqrdmlsh_s8(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svqrdmlsh_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv8i16" + )] + fn _svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svqrdmlsh_s16(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svqrdmlsh_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv4i32" + )] + fn _svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svqrdmlsh_s32(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svqrdmlsh_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv2i64" + )] + fn _svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svqrdmlsh_s64(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svqrdmlsh_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv8i16" + )] + fn _svqrdmulh_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svqrdmulh_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv4i32" + )] + fn _svqrdmulh_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqrdmulh_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv2i64" + )] + fn _svqrdmulh_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqrdmulh_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv16i8" + )] + fn _svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrdmulh_s8(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqrdmulh_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv8i16" + )] + fn _svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrdmulh_s16(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqrdmulh_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv4i32" + )] + fn _svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrdmulh_s32(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqrdmulh_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv2i64" + )] + fn _svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrdmulh_s64(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqrdmulh_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv16i8")] + fn _svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrshl_s8_m(pg, op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqrshl_s8_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqrshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv8i16")] + fn _svqrshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqrshl_s16_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqrshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv4i32")] + fn _svqrshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqrshl_s32_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqrshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv2i64")] + fn _svqrshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqrshl_s64_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqrshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv16i8")] + fn _svqrshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqrshl_u8_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqrshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv8i16")] + fn _svqrshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqrshl_u16_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqrshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv4i32")] + fn _svqrshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqrshl_u32_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqrshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv2i64")] + fn _svqrshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqrshl_u64_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqrshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv8i16" + )] + fn _svqrshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnb_n_s16(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv4i32" + )] + fn _svqrshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnb_n_s32(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv2i64" + )] + fn _svqrshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnb_n_s64(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv8i16" + )] + fn _svqrshrnb_n_u16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv4i32" + )] + fn _svqrshrnb_n_u32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv2i64" + )] + fn _svqrshrnb_n_u64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv8i16" + )] + fn _svqrshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv4i32" + )] + fn _svqrshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv2i64" + )] + fn _svqrshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv8i16" + )] + fn _svqrshrnt_n_u16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnt_n_u16(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv4i32" + )] + fn _svqrshrnt_n_u32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnt_n_u32(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv2i64" + )] + fn _svqrshrnt_n_u64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnt_n_u64(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s16(op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv8i16" + )] + fn _svqrshrunb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrunb_n_s16(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s32(op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv4i32" + )] + fn _svqrshrunb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrunb_n_s32(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s64(op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv2i64" + )] + fn _svqrshrunb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrunb_n_s64(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s16(even: svuint8_t, op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv8i16" + )] + fn _svqrshrunt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrunt_n_s16(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s32(even: svuint16_t, op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv4i32" + )] + fn _svqrshrunt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrunt_n_s32(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s64(even: svuint32_t, op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv2i64" + )] + fn _svqrshrunt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrunt_n_s64(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv16i8")] + fn _svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqshl_s8_m(pg, op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqshl_s8_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv8i16")] + fn _svqshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqshl_s16_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv4i32")] + fn _svqshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqshl_s32_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv2i64")] + fn _svqshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqshl_s64_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv16i8")] + fn _svqshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqshl_u8_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv8i16")] + fn _svqshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqshl_u16_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv4i32")] + fn _svqshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqshl_u32_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv2i64")] + fn _svqshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqshl_u64_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_m(pg: svbool_t, op1: svint8_t) -> svuint8_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv16i8")] + fn _svqshlu_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshlu_n_s8_m(pg, op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_x(pg: svbool_t, op1: svint8_t) -> svuint8_t { + svqshlu_n_s8_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_z(pg: svbool_t, op1: svint8_t) -> svuint8_t { + svqshlu_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_m(pg: svbool_t, op1: svint16_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv8i16")] + fn _svqshlu_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshlu_n_s16_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_x(pg: svbool_t, op1: svint16_t) -> svuint16_t { + svqshlu_n_s16_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_z(pg: svbool_t, op1: svint16_t) -> svuint16_t { + svqshlu_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_m(pg: svbool_t, op1: svint32_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv4i32")] + fn _svqshlu_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshlu_n_s32_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_x(pg: svbool_t, op1: svint32_t) -> svuint32_t { + svqshlu_n_s32_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_z(pg: svbool_t, op1: svint32_t) -> svuint32_t { + svqshlu_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_m(pg: svbool_t, op1: svint64_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv2i64")] + fn _svqshlu_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svqshlu_n_s64_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_x(pg: svbool_t, op1: svint64_t) -> svuint64_t { + svqshlu_n_s64_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_z(pg: svbool_t, op1: svint64_t) -> svuint64_t { + svqshlu_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv8i16" + )] + fn _svqshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnb_n_s16(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv4i32" + )] + fn _svqshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnb_n_s32(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv2i64" + )] + fn _svqshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnb_n_s64(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv8i16" + )] + fn _svqshrnb_n_u16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv4i32" + )] + fn _svqshrnb_n_u32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv2i64" + )] + fn _svqshrnb_n_u64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv8i16" + )] + fn _svqshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv4i32" + )] + fn _svqshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv2i64" + )] + fn _svqshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv8i16" + )] + fn _svqshrnt_n_u16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnt_n_u16(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv4i32" + )] + fn _svqshrnt_n_u32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnt_n_u32(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv2i64" + )] + fn _svqshrnt_n_u64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnt_n_u64(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s16(op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv8i16" + )] + fn _svqshrunb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrunb_n_s16(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s32(op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv4i32" + )] + fn _svqshrunb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrunb_n_s32(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s64(op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv2i64" + )] + fn _svqshrunb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrunb_n_s64(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s16(even: svuint8_t, op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv8i16" + )] + fn _svqshrunt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrunt_n_s16(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s32(even: svuint16_t, op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv4i32" + )] + fn _svqshrunt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrunt_n_s32(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s64(even: svuint32_t, op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv2i64" + )] + fn _svqshrunt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrunt_n_s64(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv16i8")] + fn _svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_s8_m(pg, op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsub_s8_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv8i16")] + fn _svqsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsub_s16_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv4i32")] + fn _svqsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsub_s32_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv2i64")] + fn _svqsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsub_s64_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv16i8")] + fn _svqsub_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsub_u8_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv8i16")] + fn _svqsub_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsub_u16_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv4i32")] + fn _svqsub_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsub_u32_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv2i64")] + fn _svqsub_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsub_u64_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv16i8")] + fn _svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsubr_s8_m(pg, op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsubr_s8_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv8i16")] + fn _svqsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsubr_s16_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv4i32")] + fn _svqsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsubr_s32_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv2i64")] + fn _svqsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsubr_s64_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv16i8")] + fn _svqsubr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsubr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsubr_u8_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv8i16")] + fn _svqsubr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsubr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsubr_u16_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv4i32")] + fn _svqsubr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsubr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsubr_u32_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv2i64")] + fn _svqsubr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsubr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsubr_u64_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s16(op: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv8i16")] + fn _svqxtnb_s16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnb_s16(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s32(op: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv4i32")] + fn _svqxtnb_s32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnb_s32(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s64(op: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv2i64")] + fn _svqxtnb_s64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnb_s64(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u16(op: svuint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv8i16")] + fn _svqxtnb_u16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnb_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u32(op: svuint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv4i32")] + fn _svqxtnb_u32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnb_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u64(op: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv2i64")] + fn _svqxtnb_u64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnb_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv8i16")] + fn _svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnt_s16(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv4i32")] + fn _svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnt_s32(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv2i64")] + fn _svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnt_s64(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u16(even: svuint8_t, op: svuint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv8i16")] + fn _svqxtnt_u16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnt_u16(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u32(even: svuint16_t, op: svuint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv4i32")] + fn _svqxtnt_u32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnt_u32(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u64(even: svuint32_t, op: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv2i64")] + fn _svqxtnt_u64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnt_u64(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s16(op: svint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv8i16" + )] + fn _svqxtunb_s16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtunb_s16(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s32(op: svint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv4i32" + )] + fn _svqxtunb_s32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtunb_s32(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s64(op: svint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv2i64" + )] + fn _svqxtunb_s64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtunb_s64(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s16(even: svuint8_t, op: svint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv8i16" + )] + fn _svqxtunt_s16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtunt_s16(even.as_signed(), op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s32(even: svuint16_t, op: svint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv4i32" + )] + fn _svqxtunt_s32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtunt_s32(even.as_signed(), op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s64(even: svuint32_t, op: svint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv2i64" + )] + fn _svqxtunt_s64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtunt_s64(even.as_signed(), op).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv8i16" + )] + fn _svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svraddhnb_s16(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svraddhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv4i32" + )] + fn _svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svraddhnb_s32(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svraddhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv2i64" + )] + fn _svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svraddhnb_s64(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svraddhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svraddhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svraddhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svraddhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svraddhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svraddhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svraddhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv8i16" + )] + fn _svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svraddhnt_s16(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svraddhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv4i32" + )] + fn _svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svraddhnt_s32(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svraddhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv2i64" + )] + fn _svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svraddhnt_s64(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svraddhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svraddhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svraddhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svraddhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svraddhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svraddhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svraddhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise rotate left by 1 and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-sha3")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rax1))] +pub fn svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rax1")] + fn _svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrax1_s64(op1, op2) } +} +#[doc = "Bitwise rotate left by 1 and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-sha3")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rax1))] +pub fn svrax1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svrax1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urecpe.nxv4i32")] + fn _svrecpe_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrecpe_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrecpe_u32_m(op, pg, op) +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrecpe_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv16i8")] + fn _svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrhadd_s8_m(pg, op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrhadd_s8_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrhadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv8i16")] + fn _svrhadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrhadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrhadd_s16_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrhadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv4i32")] + fn _svrhadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrhadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrhadd_s32_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrhadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv2i64")] + fn _svrhadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrhadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrhadd_s64_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrhadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv16i8")] + fn _svrhadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrhadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svrhadd_u8_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svrhadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv8i16")] + fn _svrhadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrhadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svrhadd_u16_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svrhadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv4i32")] + fn _svrhadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrhadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svrhadd_u32_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svrhadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv2i64")] + fn _svrhadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrhadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svrhadd_u64_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svrhadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv16i8")] + fn _svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrshl_s8_m(pg, op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrshl_s8_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv8i16")] + fn _svrshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrshl_s16_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv4i32")] + fn _svrshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrshl_s32_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv2i64")] + fn _svrshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrshl_s64_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv16i8")] + fn _svrshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svrshl_u8_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svrshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv8i16")] + fn _svrshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svrshl_u16_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svrshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv4i32")] + fn _svrshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svrshl_u32_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svrshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv2i64")] + fn _svrshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svrshl_u64_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svrshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_m(pg: svbool_t, op1: svint8_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv16i8")] + fn _svrshr_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshr_n_s8_m(pg, op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_x(pg: svbool_t, op1: svint8_t) -> svint8_t { + svrshr_n_s8_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_z(pg: svbool_t, op1: svint8_t) -> svint8_t { + svrshr_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_m(pg: svbool_t, op1: svint16_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv8i16")] + fn _svrshr_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshr_n_s16_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_x(pg: svbool_t, op1: svint16_t) -> svint16_t { + svrshr_n_s16_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_z(pg: svbool_t, op1: svint16_t) -> svint16_t { + svrshr_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_m(pg: svbool_t, op1: svint32_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv4i32")] + fn _svrshr_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshr_n_s32_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_x(pg: svbool_t, op1: svint32_t) -> svint32_t { + svrshr_n_s32_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_z(pg: svbool_t, op1: svint32_t) -> svint32_t { + svrshr_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_m(pg: svbool_t, op1: svint64_t) -> svint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv2i64")] + fn _svrshr_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svrshr_n_s64_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_x(pg: svbool_t, op1: svint64_t) -> svint64_t { + svrshr_n_s64_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_z(pg: svbool_t, op1: svint64_t) -> svint64_t { + svrshr_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_m(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv16i8")] + fn _svrshr_n_u8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshr_n_u8_m(pg, op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_x(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + svrshr_n_u8_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_z(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + svrshr_n_u8_m::(pg, svsel_u8(pg, op1, svdup_n_u8(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_m(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv8i16")] + fn _svrshr_n_u16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshr_n_u16_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_x(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + svrshr_n_u16_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_z(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + svrshr_n_u16_m::(pg, svsel_u16(pg, op1, svdup_n_u16(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_m(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv4i32")] + fn _svrshr_n_u32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshr_n_u32_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_x(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + svrshr_n_u32_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_z(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + svrshr_n_u32_m::(pg, svsel_u32(pg, op1, svdup_n_u32(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_m(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv2i64")] + fn _svrshr_n_u64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svrshr_n_u64_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_x(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + svrshr_n_u64_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_z(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + svrshr_n_u64_m::(pg, svsel_u64(pg, op1, svdup_n_u64(0))) +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv8i16")] + fn _svrshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshrnb_n_s16(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv4i32")] + fn _svrshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshrnb_n_s32(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv2i64")] + fn _svrshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshrnb_n_s64(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svrshrnb_n_s16::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svrshrnb_n_s32::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svrshrnb_n_s64::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv8i16")] + fn _svrshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv4i32")] + fn _svrshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv2i64")] + fn _svrshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svrshrnt_n_s16::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svrshrnt_n_s32::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svrshrnt_n_s64::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ursqrte.nxv4i32" + )] + fn _svrsqrte_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrsqrte_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrsqrte_u32_m(op, pg, op) +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrsqrte_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv16i8")] + fn _svrsra_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svrsra_n_s8(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv8i16")] + fn _svrsra_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svrsra_n_s16(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv4i32")] + fn _svrsra_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svrsra_n_s32(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv2i64")] + fn _svrsra_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svrsra_n_s64(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv16i8")] + fn _svrsra_n_u8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svrsra_n_u8(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv8i16")] + fn _svrsra_n_u16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svrsra_n_u16(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv4i32")] + fn _svrsra_n_u32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svrsra_n_u32(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv2i64")] + fn _svrsra_n_u64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svrsra_n_u64(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv8i16" + )] + fn _svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svrsubhnb_s16(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svrsubhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv4i32" + )] + fn _svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svrsubhnb_s32(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svrsubhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv2i64" + )] + fn _svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svrsubhnb_s64(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svrsubhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svrsubhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svrsubhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svrsubhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svrsubhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svrsubhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svrsubhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv8i16" + )] + fn _svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svrsubhnt_s16(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svrsubhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv4i32" + )] + fn _svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svrsubhnt_s32(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svrsubhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv2i64" + )] + fn _svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svrsubhnt_s64(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svrsubhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svrsubhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svrsubhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svrsubhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svrsubhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svrsubhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svrsubhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclb.nxv4i32")] + fn _svsbclb_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svsbclb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svsbclb_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclb.nxv2i64")] + fn _svsbclb_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svsbclb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svsbclb_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclt.nxv4i32")] + fn _svsbclt_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svsbclt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svsbclt_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclt.nxv2i64")] + fn _svsbclt_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svsbclt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svsbclt_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s16(op1: svint8_t) -> svint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv8i16")] + fn _svshllb_n_s16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllb_n_s16(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s32(op1: svint16_t) -> svint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv4i32")] + fn _svshllb_n_s32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllb_n_s32(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s64(op1: svint32_t) -> svint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv2i64")] + fn _svshllb_n_s64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllb_n_s64(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u16(op1: svuint8_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv8i16")] + fn _svshllb_n_u16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u32(op1: svuint16_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv4i32")] + fn _svshllb_n_u32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u64(op1: svuint32_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv2i64")] + fn _svshllb_n_u64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s16(op1: svint8_t) -> svint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv8i16")] + fn _svshllt_n_s16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllt_n_s16(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s32(op1: svint16_t) -> svint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv4i32")] + fn _svshllt_n_s32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllt_n_s32(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s64(op1: svint32_t) -> svint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv2i64")] + fn _svshllt_n_s64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllt_n_s64(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u16(op1: svuint8_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv8i16")] + fn _svshllt_n_u16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllt_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u32(op1: svuint16_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv4i32")] + fn _svshllt_n_u32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllt_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u64(op1: svuint32_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv2i64")] + fn _svshllt_n_u64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllt_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv8i16")] + fn _svshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svshrnb_n_s16(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv4i32")] + fn _svshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svshrnb_n_s32(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv2i64")] + fn _svshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svshrnb_n_s64(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svshrnb_n_s16::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svshrnb_n_s32::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svshrnb_n_s64::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv8i16")] + fn _svshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv4i32")] + fn _svshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv2i64")] + fn _svshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svshrnt_n_s16::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svshrnt_n_s32::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svshrnt_n_s64::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv16i8")] + fn _svsli_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsli_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv8i16")] + fn _svsli_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsli_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv4i32")] + fn _svsli_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsli_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv2i64")] + fn _svsli_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsli_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 0..=7); + unsafe { svsli_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 0..=15); + unsafe { svsli_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 0..=31); + unsafe { svsli_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 0..=63); + unsafe { svsli_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "SM4 encryption and decryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4e[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-sm4")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sm4e))] +pub fn svsm4e_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sm4e")] + fn _svsm4e_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsm4e_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "SM4 key updates"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4ekey[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2,sve2-sm4")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sm4ekey))] +pub fn svsm4ekey_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sm4ekey")] + fn _svsm4ekey_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsm4ekey_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv16i8")] + fn _svsqadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsqadd_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svsqadd_u8_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svsqadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv8i16")] + fn _svsqadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsqadd_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svsqadd_u16_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svsqadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv4i32")] + fn _svsqadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsqadd_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svsqadd_u32_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svsqadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv2i64")] + fn _svsqadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsqadd_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svsqadd_u64_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svsqadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv16i8")] + fn _svsra_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsra_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv8i16")] + fn _svsra_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsra_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv4i32")] + fn _svsra_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsra_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv2i64")] + fn _svsra_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsra_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv16i8")] + fn _svsra_n_u8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsra_n_u8(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv8i16")] + fn _svsra_n_u16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsra_n_u16(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv4i32")] + fn _svsra_n_u32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsra_n_u32(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv2i64")] + fn _svsra_n_u64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsra_n_u64(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv16i8")] + fn _svsri_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsri_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv8i16")] + fn _svsri_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsri_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv4i32")] + fn _svsri_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsri_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv2i64")] + fn _svsri_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsri_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe { svsri_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe { svsri_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe { svsri_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe { svsri_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2f64" + )] + fn _svstnt1_scatter_s64index_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + indices: svint64_t, + ); + } + _svstnt1_scatter_s64index_f64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i64" + )] + fn _svstnt1_scatter_s64index_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + indices: svint64_t, + ); + } + _svstnt1_scatter_s64index_s64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svuint64_t, + data: svfloat64_t, +) { + svstnt1_scatter_s64index_f64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2f64" + )] + fn _svstnt1_scatter_s64offset_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + offsets: svint64_t, + ); + } + _svstnt1_scatter_s64offset_f64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i64" + )] + fn _svstnt1_scatter_s64offset_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + offsets: svint64_t, + ); + } + _svstnt1_scatter_s64offset_s64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4f32" + )] + fn _svstnt1_scatter_u32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svstnt1_scatter_u32offset_f32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i32" + )] + fn _svstnt1_scatter_u32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svstnt1_scatter_u32offset_s32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svuint64_t, + data: svfloat64_t, +) { + svstnt1_scatter_s64offset_f64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: svfloat32_t) { + svstnt1_scatter_u32base_offset_f32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: svfloat64_t) { + svstnt1_scatter_u64base_offset_f64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svfloat32_t, +) { + svstnt1_scatter_u32base_offset_f32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svstnt1_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svstnt1_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svfloat64_t, +) { + svstnt1_scatter_u64base_offset_f64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svstnt1_scatter_u32base_offset_f32( + data: svfloat32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1_scatter_u32base_offset_f32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svstnt1_scatter_u32base_offset_s32( + data: svint32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1_scatter_u32base_offset_s32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svstnt1_scatter_u64base_offset_f64( + data: svfloat64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1_scatter_u64base_offset_f64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svstnt1_scatter_u64base_offset_s64( + data: svint64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1_scatter_u64base_offset_s64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i8" + )] + fn _svstnt1b_scatter_s64offset_s64( + data: nxv2i8, + pg: svbool2_t, + base: *mut i8, + offsets: svint64_t, + ); + } + _svstnt1b_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i16" + )] + fn _svstnt1h_scatter_s64offset_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + offsets: svint64_t, + ); + } + _svstnt1h_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i32" + )] + fn _svstnt1w_scatter_s64offset_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + offsets: svint64_t, + ); + } + _svstnt1w_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i8" + )] + fn _svstnt1b_scatter_u32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svstnt1b_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i16" + )] + fn _svstnt1h_scatter_u32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svstnt1h_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1b_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1h_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svstnt1b_scatter_u32base_offset_s32( + data: nxv4i8, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1b_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svstnt1h_scatter_u32base_offset_s32( + data: nxv4i16, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1h_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1b_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svstnt1b_scatter_u64base_offset_s64( + data: nxv2i8, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1b_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svstnt1h_scatter_u64base_offset_s64( + data: nxv2i16, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1h_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svstnt1w_scatter_u64base_offset_s64( + data: nxv2i32, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1w_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1b_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1b_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1b_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1h_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1b_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1b_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1h_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1w_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i16" + )] + fn _svstnt1h_scatter_s64index_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + indices: svint64_t, + ); + } + _svstnt1h_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i32" + )] + fn _svstnt1w_scatter_s64index_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + indices: svint64_t, + ); + } + _svstnt1w_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svstnt1h_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1h_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1w_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv8i16")] + fn _svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svsubhnb_s16(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svsubhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv4i32")] + fn _svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svsubhnb_s32(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svsubhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv2i64")] + fn _svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svsubhnb_s64(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svsubhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svsubhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svsubhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svsubhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svsubhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svsubhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svsubhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv8i16")] + fn _svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svsubhnt_s16(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svsubhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv4i32")] + fn _svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svsubhnt_s32(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svsubhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv2i64")] + fn _svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svsubhnt_s64(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svsubhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svsubhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svsubhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svsubhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svsubhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svsubhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svsubhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv8i16")] + fn _svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublb_s16(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv4i32")] + fn _svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublb_s32(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv2i64")] + fn _svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublb_s64(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv8i16")] + fn _svsublb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svsublb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv4i32")] + fn _svsublb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svsublb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv2i64")] + fn _svsublb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svsublb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv8i16" + )] + fn _svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublbt_s16(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublbt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv4i32" + )] + fn _svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublbt_s32(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublbt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv2i64" + )] + fn _svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublbt_s64(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublbt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv8i16")] + fn _svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublt_s16(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv4i32")] + fn _svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublt_s32(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv2i64")] + fn _svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublt_s64(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv8i16")] + fn _svsublt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svsublt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv4i32")] + fn _svsublt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svsublt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv2i64")] + fn _svsublt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svsublt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv8i16" + )] + fn _svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubltb_s16(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsubltb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv4i32" + )] + fn _svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubltb_s32(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsubltb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv2i64" + )] + fn _svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubltb_s64(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsubltb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv8i16")] + fn _svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwb_s16(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svsubwb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv4i32")] + fn _svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwb_s32(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svsubwb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv2i64")] + fn _svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwb_s64(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svsubwb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv8i16")] + fn _svsubwb_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svsubwb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv4i32")] + fn _svsubwb_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svsubwb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv2i64")] + fn _svsubwb_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svsubwb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv8i16")] + fn _svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwt_s16(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svsubwt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv4i32")] + fn _svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwt_s32(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svsubwt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv2i64")] + fn _svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwt_s64(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svsubwt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv8i16")] + fn _svsubwt_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svsubwt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv4i32")] + fn _svsubwt_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svsubwt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv2i64")] + fn _svsubwt_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svsubwt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_f32(data: svfloat32x2_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv4f32")] + fn _svtbl2_f32(data0: svfloat32_t, data1: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { + _svtbl2_f32( + svget2_f32::<0>(data), + svget2_f32::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_f64(data: svfloat64x2_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv2f64")] + fn _svtbl2_f64(data0: svfloat64_t, data1: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { + _svtbl2_f64( + svget2_f64::<0>(data), + svget2_f64::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s8(data: svint8x2_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv16i8")] + fn _svtbl2_s8(data0: svint8_t, data1: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { + _svtbl2_s8( + svget2_s8::<0>(data), + svget2_s8::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s16(data: svint16x2_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv8i16")] + fn _svtbl2_s16(data0: svint16_t, data1: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { + _svtbl2_s16( + svget2_s16::<0>(data), + svget2_s16::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s32(data: svint32x2_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv4i32")] + fn _svtbl2_s32(data0: svint32_t, data1: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { + _svtbl2_s32( + svget2_s32::<0>(data), + svget2_s32::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s64(data: svint64x2_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv2i64")] + fn _svtbl2_s64(data0: svint64_t, data1: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { + _svtbl2_s64( + svget2_s64::<0>(data), + svget2_s64::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u8(data: svuint8x2_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbl2_s8(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u16(data: svuint16x2_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbl2_s16(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u32(data: svuint32x2_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbl2_s32(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u64(data: svuint64x2_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbl2_s64(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv4f32")] + fn _svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { _svtbx_f32(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv2f64")] + fn _svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { _svtbx_f64(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv16i8")] + fn _svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { _svtbx_s8(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv8i16")] + fn _svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { _svtbx_s16(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv4i32")] + fn _svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svtbx_s32(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv2i64")] + fn _svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svtbx_s64(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u8(fallback: svuint8_t, data: svuint8_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbx_s8(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u16(fallback: svuint16_t, data: svuint16_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbx_s16(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u32(fallback: svuint32_t, data: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbx_s32(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u64(fallback: svuint64_t, data: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbx_s64(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_b])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(punpkhi))] +pub fn svunpkhi_b(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.punpkhi.nxv16i1" + )] + fn _svunpkhi_b(op: svbool_t) -> svbool8_t; + } + unsafe { _svunpkhi_b(op).sve_into() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s16(op: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv8i16" + )] + fn _svunpkhi_s16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpkhi_s16(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s32(op: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv4i32" + )] + fn _svunpkhi_s32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpkhi_s32(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s64(op: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv2i64" + )] + fn _svunpkhi_s64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpkhi_s64(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u16(op: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv8i16" + )] + fn _svunpkhi_u16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpkhi_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u32(op: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv4i32" + )] + fn _svunpkhi_u32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpkhi_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u64(op: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv2i64" + )] + fn _svunpkhi_u64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpkhi_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_b])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(punpklo))] +pub fn svunpklo_b(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.punpklo.nxv16i1" + )] + fn _svunpklo_b(op: svbool_t) -> svbool8_t; + } + unsafe { _svunpklo_b(op).sve_into() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s16(op: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv8i16" + )] + fn _svunpklo_s16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpklo_s16(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s32(op: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv4i32" + )] + fn _svunpklo_s32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpklo_s32(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s64(op: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv2i64" + )] + fn _svunpklo_s64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpklo_s64(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u16(op: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv8i16" + )] + fn _svunpklo_u16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpklo_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u32(op: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv4i32" + )] + fn _svunpklo_u32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpklo_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u64(op: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv2i64" + )] + fn _svunpklo_u64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpklo_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv16i8")] + fn _svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuqadd_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svuqadd_s8_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svuqadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv8i16")] + fn _svuqadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuqadd_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svuqadd_s16_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svuqadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv4i32")] + fn _svuqadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuqadd_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svuqadd_s32_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svuqadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv2i64")] + fn _svuqadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuqadd_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_m)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svuqadd_s64_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_x)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svuqadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_z)"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv16i1.i32" + )] + fn _svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilege_b8_s32(op1, op2) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv8i1.i32" + )] + fn _svwhilege_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilege_b16_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv4i1.i32" + )] + fn _svwhilege_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilege_b32_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv2i1.i32" + )] + fn _svwhilege_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilege_b64_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv16i1.i64" + )] + fn _svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilege_b8_s64(op1, op2) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv8i1.i64" + )] + fn _svwhilege_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilege_b16_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv4i1.i64" + )] + fn _svwhilege_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilege_b32_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv2i1.i64" + )] + fn _svwhilege_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilege_b64_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv16i1.i32" + )] + fn _svwhilege_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilege_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv8i1.i32" + )] + fn _svwhilege_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilege_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv4i1.i32" + )] + fn _svwhilege_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilege_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv2i1.i32" + )] + fn _svwhilege_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilege_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv16i1.i64" + )] + fn _svwhilege_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilege_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv8i1.i64" + )] + fn _svwhilege_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilege_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv4i1.i64" + )] + fn _svwhilege_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilege_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv2i1.i64" + )] + fn _svwhilege_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilege_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv16i1.i32" + )] + fn _svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilegt_b8_s32(op1, op2) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv8i1.i32" + )] + fn _svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilegt_b16_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv4i1.i32" + )] + fn _svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilegt_b32_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv2i1.i32" + )] + fn _svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilegt_b64_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv16i1.i64" + )] + fn _svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilegt_b8_s64(op1, op2) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv8i1.i64" + )] + fn _svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilegt_b16_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv4i1.i64" + )] + fn _svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilegt_b32_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv2i1.i64" + )] + fn _svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilegt_b64_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv16i1.i32" + )] + fn _svwhilegt_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilegt_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv8i1.i32" + )] + fn _svwhilegt_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilegt_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv4i1.i32" + )] + fn _svwhilegt_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilegt_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv2i1.i32" + )] + fn _svwhilegt_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilegt_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv16i1.i64" + )] + fn _svwhilegt_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilegt_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv8i1.i64" + )] + fn _svwhilegt_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilegt_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv4i1.i64" + )] + fn _svwhilegt_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilegt_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv2i1.i64" + )] + fn _svwhilegt_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilegt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_8ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.b.nxv16i1.p0" + )] + fn _svwhilerw_8ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool_t; + } + _svwhilerw_8ptr(op1, op2) +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_16ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.h.nxv8i1.p0" + )] + fn _svwhilerw_16ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool8_t; + } + _svwhilerw_16ptr(op1, op2).sve_into() +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_32ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.s.nxv4i1.p0" + )] + fn _svwhilerw_32ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool4_t; + } + _svwhilerw_32ptr(op1, op2).sve_into() +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_64ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.d.nxv2i1.p0" + )] + fn _svwhilerw_64ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool2_t; + } + _svwhilerw_64ptr(op1, op2).sve_into() +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_f32(op1: *const f32, op2: *const f32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_f64(op1: *const f64, op2: *const f64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s8(op1: *const i8, op2: *const i8) -> svbool_t { + svwhilerw_8ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s16(op1: *const i16, op2: *const i16) -> svbool_t { + svwhilerw_16ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s32(op1: *const i32, op2: *const i32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s64(op1: *const i64, op2: *const i64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u8(op1: *const u8, op2: *const u8) -> svbool_t { + svwhilerw_8ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u16(op1: *const u16, op2: *const u16) -> svbool_t { + svwhilerw_16ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u32(op1: *const u32, op2: *const u32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u64(op1: *const u64, op2: *const u64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_8ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.b.nxv16i1.p0" + )] + fn _svwhilewr_8ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool_t; + } + _svwhilewr_8ptr(op1, op2) +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_16ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.h.nxv8i1.p0" + )] + fn _svwhilewr_16ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool8_t; + } + _svwhilewr_16ptr(op1, op2).sve_into() +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_32ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.s.nxv4i1.p0" + )] + fn _svwhilewr_32ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool4_t; + } + _svwhilewr_32ptr(op1, op2).sve_into() +} +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_64ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.d.nxv2i1.p0" + )] + fn _svwhilewr_64ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool2_t; + } + _svwhilewr_64ptr(op1, op2).sve_into() +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_f32(op1: *const f32, op2: *const f32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_f64(op1: *const f64, op2: *const f64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s8(op1: *const i8, op2: *const i8) -> svbool_t { + svwhilewr_8ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s16(op1: *const i16, op2: *const i16) -> svbool_t { + svwhilewr_16ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s32(op1: *const i32, op2: *const i32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s64(op1: *const i64, op2: *const i64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u8(op1: *const u8, op2: *const u8) -> svbool_t { + svwhilewr_8ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u16(op1: *const u16, op2: *const u16) -> svbool_t { + svwhilewr_16ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u32(op1: *const u32, op2: *const u32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u64(op1: *const u64, op2: *const u64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv16i8")] + fn _svxar_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svxar_n_s8(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv8i16")] + fn _svxar_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svxar_n_s16(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv4i32")] + fn _svxar_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svxar_n_s32(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv2i64")] + fn _svxar_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svxar_n_s64(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u8])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe { svxar_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u16])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe { svxar_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u32])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe { svxar_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u64])"] +#[inline] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe { svxar_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} diff --git a/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs b/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs new file mode 100644 index 0000000000000..2ec3ad6a5d04c --- /dev/null +++ b/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs @@ -0,0 +1,2482 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate +// this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(unused)] +use super::*; +use std::boxed::Box; +use std::convert::{TryFrom, TryInto}; +use std::sync::LazyLock; +use std::vec::Vec; +use stdarch_test::simd_test; +static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as f32) + .collect::>() + .try_into() + .expect("f32 data incorrectly initialised") +}); +static F64_DATA: LazyLock<[f64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as f64) + .collect::>() + .try_into() + .expect("f64 data incorrectly initialised") +}); +static I8_DATA: LazyLock<[i8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| ((i + 128) % 256 - 128) as i8) + .collect::>() + .try_into() + .expect("i8 data incorrectly initialised") +}); +static I16_DATA: LazyLock<[i16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as i16) + .collect::>() + .try_into() + .expect("i16 data incorrectly initialised") +}); +static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as i32) + .collect::>() + .try_into() + .expect("i32 data incorrectly initialised") +}); +static I64_DATA: LazyLock<[i64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as i64) + .collect::>() + .try_into() + .expect("i64 data incorrectly initialised") +}); +static U8_DATA: LazyLock<[u8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| i as u8) + .collect::>() + .try_into() + .expect("u8 data incorrectly initialised") +}); +static U16_DATA: LazyLock<[u16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as u16) + .collect::>() + .try_into() + .expect("u16 data incorrectly initialised") +}); +static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as u32) + .collect::>() + .try_into() + .expect("u32 data incorrectly initialised") +}); +static U64_DATA: LazyLock<[u64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as u64) + .collect::>() + .try_into() + .expect("u64 data incorrectly initialised") +}); +#[target_feature(enable = "sve")] +fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_f32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_f64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_s8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_s16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_s32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_s64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_u8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_u16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_u32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_u64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_f64_with_svstnt1_scatter_s64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_s64_with_svstnt1_scatter_s64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_u64_with_svstnt1_scatter_s64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_f64_with_svstnt1_scatter_u64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_s64_with_svstnt1_scatter_u64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_u64_with_svstnt1_scatter_u64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_f64_with_svstnt1_scatter_s64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_s64_with_svstnt1_scatter_s64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_u64_with_svstnt1_scatter_s64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_f32_with_svstnt1_scatter_u32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_s32_with_svstnt1_scatter_u32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_u32_with_svstnt1_scatter_u32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_f64_with_svstnt1_scatter_u64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_s64_with_svstnt1_scatter_u64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_u64_with_svstnt1_scatter_u64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_f64_with_svstnt1_scatter_u64base_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_f64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_f64(svptrue_b64(), bases); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_s64_with_svstnt1_scatter_u64base_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_s64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_s64(svptrue_b64(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_u64_with_svstnt1_scatter_u64base_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_u64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_u64(svptrue_b64(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_f32_with_svstnt1_scatter_u32base_index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_s32_with_svstnt1_scatter_u32base_index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_u32_with_svstnt1_scatter_u32base_index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_f64_with_svstnt1_scatter_u64base_index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_s64_with_svstnt1_scatter_u64base_index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_u64_with_svstnt1_scatter_u64base_index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_f32_with_svstnt1_scatter_u32base_offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_s32_with_svstnt1_scatter_u32base_offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_u32_with_svstnt1_scatter_u32base_offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_f64_with_svstnt1_scatter_u64base_offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_s64_with_svstnt1_scatter_u64base_offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_u64_with_svstnt1_scatter_u64base_offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_s64offset_s64_with_svstnt1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64offset_s64_with_svstnt1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64offset_s64_with_svstnt1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_s64offset_u64_with_svstnt1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64offset_u64_with_svstnt1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64offset_u64_with_svstnt1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32offset_s32_with_svstnt1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32offset_s32_with_svstnt1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32offset_u32_with_svstnt1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32offset_u32_with_svstnt1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64offset_s64_with_svstnt1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64offset_s64_with_svstnt1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64offset_s64_with_svstnt1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64offset_u64_with_svstnt1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64offset_u64_with_svstnt1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64offset_u64_with_svstnt1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32base_offset_s32_with_svstnt1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_offset_s32_with_svstnt1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32base_offset_u32_with_svstnt1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_offset_u32_with_svstnt1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_offset_s64_with_svstnt1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_offset_s64_with_svstnt1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_offset_s64_with_svstnt1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_offset_u64_with_svstnt1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_offset_u64_with_svstnt1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_offset_u64_with_svstnt1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_s64_with_svstnt1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_s64_with_svstnt1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_s64_with_svstnt1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_u64_with_svstnt1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_u64_with_svstnt1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_u64_with_svstnt1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64index_s64_with_svstnt1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64index_s64_with_svstnt1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64index_u64_with_svstnt1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64index_u64_with_svstnt1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64index_s64_with_svstnt1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64index_s64_with_svstnt1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64index_u64_with_svstnt1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64index_u64_with_svstnt1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_index_s32_with_svstnt1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_index_u32_with_svstnt1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_index_s64_with_svstnt1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_index_s64_with_svstnt1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_index_u64_with_svstnt1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_index_u64_with_svstnt1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_s64offset_s64_with_svstnt1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64offset_s64_with_svstnt1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64offset_s64_with_svstnt1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_s64offset_u64_with_svstnt1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64offset_u64_with_svstnt1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64offset_u64_with_svstnt1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32offset_s32_with_svstnt1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32offset_s32_with_svstnt1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32offset_u32_with_svstnt1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32offset_u32_with_svstnt1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64offset_s64_with_svstnt1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64offset_s64_with_svstnt1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64offset_s64_with_svstnt1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64offset_u64_with_svstnt1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64offset_u64_with_svstnt1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64offset_u64_with_svstnt1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32base_offset_s32_with_svstnt1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_offset_s32_with_svstnt1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32base_offset_u32_with_svstnt1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_offset_u32_with_svstnt1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_offset_s64_with_svstnt1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_offset_s64_with_svstnt1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_offset_s64_with_svstnt1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_offset_u64_with_svstnt1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_offset_u64_with_svstnt1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_offset_u64_with_svstnt1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_s64_with_svstnt1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_s64_with_svstnt1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_s64_with_svstnt1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_u64_with_svstnt1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_u64_with_svstnt1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_u64_with_svstnt1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64index_s64_with_svstnt1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64index_s64_with_svstnt1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64index_u64_with_svstnt1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64index_u64_with_svstnt1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64index_s64_with_svstnt1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64index_s64_with_svstnt1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64index_u64_with_svstnt1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64index_u64_with_svstnt1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_index_s32_with_svstnt1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_index_u32_with_svstnt1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_index_s64_with_svstnt1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_index_s64_with_svstnt1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_index_u64_with_svstnt1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_index_u64_with_svstnt1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} diff --git a/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs b/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs new file mode 100644 index 0000000000000..acf9070214571 --- /dev/null +++ b/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs @@ -0,0 +1,17 @@ +//! SVE2 intrinsics + +#![allow(non_camel_case_types)] + +// `generated.rs` has a `super::*` and this import is for that +use super::sve::*; +use crate::intrinsics::*; + +#[rustfmt::skip] +mod generated; +#[rustfmt::skip] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::generated::*; + +#[cfg(test)] +#[path = "ld_st_tests_aarch64.rs"] +mod ld_st_tests; diff --git a/stdarch/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md b/stdarch/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md new file mode 100644 index 0000000000000..1bc8899d33e0a --- /dev/null +++ b/stdarch/crates/core_arch/src/amdgpu/intrinsic_is_convergent.md @@ -0,0 +1,6 @@ +This intrinsic does not behave like a normal function call; it is a "[convergent]" operation and as such has non-standard control-flow effects which need special treatment by the language. +Rust currently does not properly support convergent operations. +This operation is hence provided on a best-effort basis. +Using it may result in incorrect code under some circumstances. + +[convergent]: https://llvm.org/docs/ConvergentOperations.html diff --git a/stdarch/crates/core_arch/src/amdgpu/mod.rs b/stdarch/crates/core_arch/src/amdgpu/mod.rs index 40274e4d794fd..374f582696947 100644 --- a/stdarch/crates/core_arch/src/amdgpu/mod.rs +++ b/stdarch/crates/core_arch/src/amdgpu/mod.rs @@ -244,6 +244,8 @@ pub fn wavefrontsize() -> u32 { /// Synchronize all wavefronts in a workgroup. /// /// Each wavefronts in a workgroup waits at the barrier until all wavefronts in the workgroup arrive at a barrier. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn s_barrier() { @@ -253,6 +255,8 @@ pub fn s_barrier() { /// Signal a specific barrier type. /// /// Only for non-named barriers. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn s_barrier_signal() { @@ -265,6 +269,8 @@ pub unsafe fn s_barrier_signal() { /// Provides access to the s_barrier_signal_first instruction; /// additionally ensures that the result value is valid even when /// the intrinsic is used from a wavefront that is not running in a workgroup. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn s_barrier_signal_isfirst() -> bool { @@ -274,6 +280,8 @@ pub unsafe fn s_barrier_signal_isfirst() -> bool { /// Wait for a specific barrier type. /// /// Only for non-named barriers. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn s_barrier_wait() { @@ -283,6 +291,8 @@ pub unsafe fn s_barrier_wait() { /// Get the state of a specific barrier type. /// /// The `barrier_type` argument must be uniform, otherwise behavior is undefined. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn s_get_barrier_state() -> u32 { @@ -292,6 +302,8 @@ pub unsafe fn s_get_barrier_state() -> u32 { /// A barrier for only the threads within the current wavefront. /// /// Does not result in an instruction but restricts the compiler. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_barrier() { @@ -315,6 +327,8 @@ pub fn wave_barrier() { /// - 0x0100: All DS read instructions may be scheduled across `sched_barrier`. /// - 0x0200: All DS write instructions may be scheduled across `sched_barrier`. /// - 0x0400: All Transcendental (e.g. V_EXP) instructions may be scheduled across `sched_barrier`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn sched_barrier() { @@ -345,6 +359,8 @@ pub unsafe fn sched_barrier() { /// // 5 MFMA /// sched_group_barrier::<8, 5, 0>() /// ``` +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn sched_group_barrier() { @@ -366,6 +382,8 @@ pub fn s_sleep() { /// Stop execution of the kernel. /// /// This usually signals an error state. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn s_sethalt() -> ! { @@ -407,6 +425,8 @@ pub fn mbcnt_hi(value: u32, init: u32) -> u32 { /// Returns a bitfield (`u32` or `u64`) containing the result of its i1 argument /// in all active lanes, and zero in all inactive lanes. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn ballot(b: bool) -> u64 { @@ -419,6 +439,8 @@ pub fn ballot(b: bool) -> u64 { /// While [`ballot`] converts a `bool` to a mask, `inverse_ballot` converts a mask back to a `bool`. /// This means `inverse_ballot(ballot(b)) == b`. /// The inverse of `ballot(inverse_ballot(value)) ~= value` is not always true as inactive lanes are set to zero by `ballot`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn inverse_ballot(value: u64) -> bool { @@ -433,6 +455,8 @@ pub fn inverse_ballot(value: u64) -> bool { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_umin(value: u32) -> u32 { @@ -447,6 +471,8 @@ pub fn wave_reduce_umin(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_min(value: i32) -> i32 { @@ -462,6 +488,8 @@ pub fn wave_reduce_min(value: i32) -> i32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_umax(value: u32) -> u32 { @@ -476,6 +504,8 @@ pub fn wave_reduce_umax(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_max(value: i32) -> i32 { @@ -491,6 +521,8 @@ pub fn wave_reduce_max(value: i32) -> i32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_add(value: u32) -> u32 { @@ -506,6 +538,8 @@ pub fn wave_reduce_add(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_and(value: u32) -> u32 { @@ -520,6 +554,8 @@ pub fn wave_reduce_and(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_or(value: u32) -> u32 { @@ -534,6 +570,8 @@ pub fn wave_reduce_or(value: u32) -> u32 { /// - 2: DPP /// /// If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn wave_reduce_xor(value: u32) -> u32 { @@ -544,12 +582,16 @@ pub fn wave_reduce_xor(value: u32) -> u32 { // The following intrinsics can have multiple sizes /// Get `value` from the first active lane in the wavefront. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn readfirstlane_u32(value: u32) -> u32 { llvm_readfirstlane_u32(value) } /// Get `value` from the first active lane in the wavefront. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn readfirstlane_u64(value: u64) -> u64 { @@ -559,6 +601,8 @@ pub fn readfirstlane_u64(value: u64) -> u64 { /// /// The lane argument must be uniform across the currently active threads /// of the current wavefront. Otherwise, the result is undefined. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn readlane_u32(value: u32, lane: u32) -> u32 { @@ -568,6 +612,8 @@ pub unsafe fn readlane_u32(value: u32, lane: u32) -> u32 { /// /// The lane argument must be uniform across the currently active threads /// of the current wavefront. Otherwise, the result is undefined. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn readlane_u64(value: u64, lane: u32) -> u64 { @@ -582,6 +628,8 @@ pub unsafe fn readlane_u64(value: u64, lane: u32) -> u64 { /// /// `value` is the value returned by `lane`. /// `default` is the value returned by all lanes other than `lane`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn writelane_u32(value: u32, lane: u32, default: u32) -> u32 { @@ -596,6 +644,8 @@ pub unsafe fn writelane_u32(value: u32, lane: u32, default: u32) -> u32 { /// /// `value` is the value returned by `lane`. /// `default` is the value returned by all lanes other than `lane`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn writelane_u64(value: u64, lane: u32, default: u64) -> u64 { @@ -605,6 +655,8 @@ pub unsafe fn writelane_u64(value: u64, lane: u32, default: u64) -> u64 { /// Stop execution of the wavefront. /// /// This usually signals the end of a successful execution. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub fn endpgm() -> ! { @@ -621,6 +673,8 @@ pub fn endpgm() -> ! { /// v_mov_b32 /// v_mov_b32 /// ``` +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn update_dpp< @@ -651,6 +705,8 @@ pub fn s_memrealtime() -> u64 { /// /// Reading from inactive lanes returns `0`. /// In case multiple values get written to the same `lane`, the value from the source lane with the higher index is taken. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn ds_permute(lane: u32, value: u32) -> u32 { @@ -661,6 +717,8 @@ pub unsafe fn ds_permute(lane: u32, value: u32) -> u32 { /// Returns the `value` given to `ds_permute` by lane `lane`. /// /// Reading from inactive lanes returns `0`. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn ds_bpermute(lane: u32, value: u32) -> u32 { @@ -680,6 +738,8 @@ pub unsafe fn perm(src0: u32, src1: u32, selector: u32) -> u32 { /// /// The third and fourth inputs must be uniform across the current wavefront. /// These are combined into a single 64-bit value representing lane selects used to swizzle within each row. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane16_u32( @@ -696,6 +756,8 @@ pub unsafe fn permlane16_u32( /// /// The third and fourth inputs must be uniform across the current wavefront. /// These are combined into a single 64-bit value representing lane selects used to swizzle within each row. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlanex16_u32( @@ -718,6 +780,8 @@ pub fn s_get_waveid_in_workgroup() -> u32 { /// Swap `value` between upper and lower 32 lanes in a wavefront. /// /// Does nothing for wave32. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane64_u32(value: u32) -> u32 { @@ -728,6 +792,8 @@ pub unsafe fn permlane64_u32(value: u32) -> u32 { /// Performs arbitrary gather-style operation within a row (16 contiguous lanes) of the second input operand. /// /// In contrast to [`permlane16_u32`], allows each lane to specify its own gather lane. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane16_var( @@ -742,6 +808,8 @@ pub unsafe fn permlane16_var( /// Performs arbitrary gather-style operation across two rows (16 contiguous lanes) of the second input operand. /// /// In contrast to [`permlanex16_u32`], allows each lane to specify its own gather lane. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlanex16_var( @@ -766,6 +834,8 @@ pub fn wave_id() -> u32 { /// Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes). /// Returns a pair for the swapped registers. /// The first element of the return corresponds to the swapped element of the first argument. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane16_swap( @@ -782,6 +852,8 @@ pub unsafe fn permlane16_swap( /// Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes). /// Returns a pair for the swapped registers. /// The first element of the return corresponds to the swapped element of the first argument. +/// +#[doc = include_str!("intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_amdgpu", issue = "149988")] pub unsafe fn permlane32_swap( diff --git a/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 4a846e2877462..5284a3c44af49 100644 --- a/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -14,7 +14,7 @@ use super::*; #[doc = "CRC32 single round checksum for bytes (8 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32b))] @@ -39,7 +39,7 @@ pub fn __crc32b(crc: u32, data: u8) -> u32 { } #[doc = "CRC32-C single round checksum for bytes (8 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32cb))] @@ -64,7 +64,7 @@ pub fn __crc32cb(crc: u32, data: u8) -> u32 { } #[doc = "CRC32-C single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg(target_arch = "arm")] #[cfg_attr(test, assert_instr(crc32cw))] @@ -83,7 +83,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 { } #[doc = "CRC32-C single round checksum for bytes (16 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32ch))] @@ -108,7 +108,7 @@ pub fn __crc32ch(crc: u32, data: u16) -> u32 { } #[doc = "CRC32-C single round checksum for bytes (32 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32cw))] @@ -133,7 +133,7 @@ pub fn __crc32cw(crc: u32, data: u32) -> u32 { } #[doc = "CRC32 single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg(target_arch = "arm")] #[cfg_attr(test, assert_instr(crc32w))] @@ -152,7 +152,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 { } #[doc = "CRC32 single round checksum for bytes (16 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32h))] @@ -177,7 +177,7 @@ pub fn __crc32h(crc: u32, data: u16) -> u32 { } #[doc = "CRC32 single round checksum for bytes (32 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"] -#[inline(always)] +#[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(crc32w))] @@ -202,7 +202,7 @@ pub fn __crc32w(crc: u32, data: u32) -> u32 { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -220,7 +220,7 @@ fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -238,7 +238,7 @@ fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -256,7 +256,7 @@ fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -274,7 +274,7 @@ fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -292,7 +292,7 @@ fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -310,7 +310,7 @@ fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -328,7 +328,7 @@ fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -346,7 +346,7 @@ fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -364,7 +364,7 @@ fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -382,7 +382,7 @@ fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -400,7 +400,7 @@ fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -418,7 +418,7 @@ fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))] @@ -439,7 +439,7 @@ pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))] @@ -460,7 +460,7 @@ pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))] @@ -481,7 +481,7 @@ pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))] @@ -502,7 +502,7 @@ pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))] @@ -523,7 +523,7 @@ pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { } #[doc = "Absolute difference and accumulate (64-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))] @@ -544,7 +544,7 @@ pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))] @@ -569,7 +569,7 @@ pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))] @@ -594,7 +594,7 @@ pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))] @@ -619,7 +619,7 @@ pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))] @@ -641,7 +641,7 @@ pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))] @@ -663,7 +663,7 @@ pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))] @@ -685,7 +685,7 @@ pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))] @@ -706,7 +706,7 @@ pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))] @@ -727,7 +727,7 @@ pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))] @@ -748,7 +748,7 @@ pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))] @@ -769,7 +769,7 @@ pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))] @@ -790,7 +790,7 @@ pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Absolute difference and accumulate (128-bit)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))] @@ -811,7 +811,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))] #[cfg_attr( @@ -841,7 +841,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))] #[cfg_attr( @@ -871,7 +871,7 @@ pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))] @@ -900,7 +900,7 @@ pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))] @@ -929,7 +929,7 @@ pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))] @@ -958,7 +958,7 @@ pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))] @@ -987,7 +987,7 @@ pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))] @@ -1016,7 +1016,7 @@ pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))] @@ -1045,7 +1045,7 @@ pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))] @@ -1074,7 +1074,7 @@ pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))] @@ -1103,7 +1103,7 @@ pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))] @@ -1132,7 +1132,7 @@ pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))] @@ -1161,7 +1161,7 @@ pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))] @@ -1190,7 +1190,7 @@ pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))] @@ -1219,7 +1219,7 @@ pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))] @@ -1248,7 +1248,7 @@ pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))] @@ -1277,7 +1277,7 @@ pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))] @@ -1301,7 +1301,7 @@ pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))] @@ -1325,7 +1325,7 @@ pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))] @@ -1349,7 +1349,7 @@ pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))] @@ -1370,7 +1370,7 @@ pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))] @@ -1391,7 +1391,7 @@ pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))] @@ -1412,7 +1412,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] #[cfg_attr( @@ -1434,7 +1434,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] #[cfg_attr( @@ -1456,7 +1456,7 @@ pub fn vabsq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1477,7 +1477,7 @@ pub fn vabs_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1498,7 +1498,7 @@ pub fn vabsq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1523,7 +1523,7 @@ pub fn vabs_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1548,7 +1548,7 @@ pub fn vabsq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1573,7 +1573,7 @@ pub fn vabs_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1598,7 +1598,7 @@ pub fn vabsq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1623,7 +1623,7 @@ pub fn vabs_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1648,7 +1648,7 @@ pub fn vabsq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] #[cfg_attr( @@ -1659,11 +1659,11 @@ pub fn vabsq_s32(a: int32x4_t) -> int32x4_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub fn vabsh_f16(a: f16) -> f16 { - unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) } + vget_lane_f16::<0>(vabs_f16(vdup_n_f16(a))) } #[doc = "Floating-point Add (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] #[cfg_attr( @@ -1685,7 +1685,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Floating-point Add (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] #[cfg_attr( @@ -1707,7 +1707,7 @@ pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1728,7 +1728,7 @@ pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1749,7 +1749,7 @@ pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1770,7 +1770,7 @@ pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1791,7 +1791,7 @@ pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1812,7 +1812,7 @@ pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1833,7 +1833,7 @@ pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1854,7 +1854,7 @@ pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1875,7 +1875,7 @@ pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1896,7 +1896,7 @@ pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1917,7 +1917,7 @@ pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1938,7 +1938,7 @@ pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1959,7 +1959,7 @@ pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -1980,7 +1980,7 @@ pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -2001,7 +2001,7 @@ pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -2022,7 +2022,7 @@ pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Vector add."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))] @@ -2043,7 +2043,7 @@ pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2064,7 +2064,7 @@ pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2085,7 +2085,7 @@ pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2106,7 +2106,7 @@ pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2127,7 +2127,7 @@ pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2148,7 +2148,7 @@ pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2169,7 +2169,7 @@ pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] #[cfg_attr( @@ -2184,12 +2184,16 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 { } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2203,17 +2207,21 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 { pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + vcombine_s8(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2227,17 +2235,21 @@ pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t { pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7]) + vcombine_s16(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2251,17 +2263,21 @@ pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t { pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))); - simd_shuffle!(r, x, [0, 1, 2, 3]) + vcombine_s32(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2275,17 +2291,21 @@ pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t { pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + vcombine_u8(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2299,17 +2319,21 @@ pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7]) + vcombine_u16(r, x) } } #[doc = "Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(addhn2) )] #[cfg_attr( @@ -2323,12 +2347,12 @@ pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_ pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t { unsafe { let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))); - simd_shuffle!(r, x, [0, 1, 2, 3]) + vcombine_u32(r, x) } } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2349,7 +2373,7 @@ pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2370,7 +2394,7 @@ pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2391,7 +2415,7 @@ pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2412,7 +2436,7 @@ pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2433,7 +2457,7 @@ pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { } #[doc = "Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))] @@ -2454,12 +2478,16 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddl2) )] #[cfg_attr( @@ -2471,9 +2499,9 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + let a: int16x4_t = vget_high_s16(a); + let b: int16x4_t = vget_high_s16(b); unsafe { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); let a: int32x4_t = simd_cast(a); let b: int32x4_t = simd_cast(b); simd_add(a, b) @@ -2481,12 +2509,16 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddl2) )] #[cfg_attr( @@ -2498,9 +2530,9 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + let a: int32x2_t = vget_high_s32(a); + let b: int32x2_t = vget_high_s32(b); unsafe { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); let a: int64x2_t = simd_cast(a); let b: int64x2_t = simd_cast(b); simd_add(a, b) @@ -2508,12 +2540,16 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddl2) )] #[cfg_attr( @@ -2525,9 +2561,9 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + let a: int8x8_t = vget_high_s8(a); + let b: int8x8_t = vget_high_s8(b); unsafe { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); let a: int16x8_t = simd_cast(a); let b: int16x8_t = simd_cast(b); simd_add(a, b) @@ -2535,12 +2571,16 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddl2) )] #[cfg_attr( @@ -2552,9 +2592,9 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + let a: uint16x4_t = vget_high_u16(a); + let b: uint16x4_t = vget_high_u16(b); unsafe { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); let a: uint32x4_t = simd_cast(a); let b: uint32x4_t = simd_cast(b); simd_add(a, b) @@ -2562,12 +2602,16 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddl2) )] #[cfg_attr( @@ -2579,9 +2623,9 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + let a: uint32x2_t = vget_high_u32(a); + let b: uint32x2_t = vget_high_u32(b); unsafe { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); let a: uint64x2_t = simd_cast(a); let b: uint64x2_t = simd_cast(b); simd_add(a, b) @@ -2589,12 +2633,16 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { } #[doc = "Signed Add Long (vector, high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddl2) )] #[cfg_attr( @@ -2606,9 +2654,9 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { + let a: uint8x8_t = vget_high_u8(a); + let b: uint8x8_t = vget_high_u8(b); unsafe { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); let a: uint16x8_t = simd_cast(a); let b: uint16x8_t = simd_cast(b); simd_add(a, b) @@ -2616,7 +2664,7 @@ pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2641,7 +2689,7 @@ pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2666,7 +2714,7 @@ pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2691,7 +2739,7 @@ pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2716,7 +2764,7 @@ pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2741,7 +2789,7 @@ pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { } #[doc = "Add Long (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))] @@ -2766,7 +2814,7 @@ pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -2787,12 +2835,16 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 { } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddw2) )] #[cfg_attr( @@ -2804,20 +2856,24 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { + let b = vget_high_s16(b); unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); let b: int32x4_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddw2) )] #[cfg_attr( @@ -2829,20 +2885,24 @@ pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { + let b = vget_high_s32(b); unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); let b: int64x2_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(saddw2) )] #[cfg_attr( @@ -2854,20 +2914,24 @@ pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { + let b = vget_high_s8(b); unsafe { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); let b: int16x8_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddw2) )] #[cfg_attr( @@ -2879,20 +2943,24 @@ pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { + let b = vget_high_u16(b); unsafe { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); let b: uint32x4_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddw2) )] #[cfg_attr( @@ -2904,20 +2972,24 @@ pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { + let b = vget_high_u32(b); unsafe { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); let b: uint64x2_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), assert_instr(uaddw2) )] #[cfg_attr( @@ -2929,15 +3001,15 @@ pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { + let b = vget_high_u8(b); unsafe { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); let b: uint16x8_t = simd_cast(b); simd_add(a, b) } } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -2961,7 +3033,7 @@ pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -2985,7 +3057,7 @@ pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -3009,7 +3081,7 @@ pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -3033,7 +3105,7 @@ pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -3057,7 +3129,7 @@ pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { } #[doc = "Add Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))] @@ -3081,7 +3153,8 @@ pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { } #[doc = "AES single round encryption."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(aesd))] @@ -3105,8 +3178,52 @@ pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { unsafe { _vaesdq_u8(data, key) } } #[doc = "AES single round encryption."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(aesd))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.aesd" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")] + fn _vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t; + } + unsafe { + let data: uint8x16_t = simd_shuffle!( + data, + data, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let key: uint8x16_t = simd_shuffle!( + key, + key, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let ret_val: uint8x16_t = _vaesdq_u8(data, key); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} +#[doc = "AES single round encryption."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(aese))] @@ -3129,9 +3246,53 @@ pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { } unsafe { _vaeseq_u8(data, key) } } +#[doc = "AES single round encryption."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(aese))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.aese" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")] + fn _vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t; + } + unsafe { + let data: uint8x16_t = simd_shuffle!( + data, + data, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let key: uint8x16_t = simd_shuffle!( + key, + key, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let ret_val: uint8x16_t = _vaeseq_u8(data, key); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} #[doc = "AES inverse mix columns."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(aesimc))] @@ -3154,9 +3315,48 @@ pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t { } unsafe { _vaesimcq_u8(data) } } +#[doc = "AES inverse mix columns."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(aesimc))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.aesimc" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")] + fn _vaesimcq_u8(data: uint8x16_t) -> uint8x16_t; + } + unsafe { + let data: uint8x16_t = simd_shuffle!( + data, + data, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let ret_val: uint8x16_t = _vaesimcq_u8(data); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} #[doc = "AES mix columns."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(aesmc))] @@ -3179,9 +3379,47 @@ pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t { } unsafe { _vaesmcq_u8(data) } } +#[doc = "AES mix columns."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(aesmc))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.aesmc" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")] + fn _vaesmcq_u8(data: uint8x16_t) -> uint8x16_t; + } + unsafe { + let data: uint8x16_t = simd_shuffle!( + data, + data, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + let ret_val: uint8x16_t = _vaesmcq_u8(data); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } +} #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3202,7 +3440,7 @@ pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3223,7 +3461,7 @@ pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3244,7 +3482,7 @@ pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3265,7 +3503,7 @@ pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3286,7 +3524,7 @@ pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3307,7 +3545,7 @@ pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3328,7 +3566,7 @@ pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3349,7 +3587,7 @@ pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3370,7 +3608,7 @@ pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3391,7 +3629,7 @@ pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3412,7 +3650,7 @@ pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3433,7 +3671,7 @@ pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3454,7 +3692,7 @@ pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3475,7 +3713,7 @@ pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3496,7 +3734,7 @@ pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] @@ -3517,7 +3755,7 @@ pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3539,7 +3777,7 @@ pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3561,7 +3799,7 @@ pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3583,7 +3821,7 @@ pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3605,7 +3843,7 @@ pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3627,7 +3865,7 @@ pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3649,7 +3887,7 @@ pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3671,7 +3909,7 @@ pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3693,7 +3931,7 @@ pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3715,7 +3953,7 @@ pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3737,7 +3975,7 @@ pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3759,7 +3997,7 @@ pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3781,7 +4019,7 @@ pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3803,7 +4041,7 @@ pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3825,7 +4063,7 @@ pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3847,7 +4085,7 @@ pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Vector bitwise bit clear."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))] @@ -3869,7 +4107,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -3897,7 +4135,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -3925,7 +4163,7 @@ pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -3952,7 +4190,7 @@ pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -3979,7 +4217,7 @@ pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4006,7 +4244,7 @@ pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4033,7 +4271,7 @@ pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4060,7 +4298,7 @@ pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4087,7 +4325,7 @@ pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4114,7 +4352,7 @@ pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4141,7 +4379,7 @@ pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4168,7 +4406,7 @@ pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4195,7 +4433,7 @@ pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4222,7 +4460,7 @@ pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4249,7 +4487,7 @@ pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4276,7 +4514,7 @@ pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4303,7 +4541,7 @@ pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4330,7 +4568,7 @@ pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4357,7 +4595,7 @@ pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4384,7 +4622,7 @@ pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4411,7 +4649,7 @@ pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4438,7 +4676,7 @@ pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4465,7 +4703,7 @@ pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4492,7 +4730,7 @@ pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { } #[doc = "Bitwise Select."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))] @@ -4519,7 +4757,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] #[cfg_attr( @@ -4549,7 +4787,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] #[cfg_attr( @@ -4579,7 +4817,7 @@ pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] @@ -4608,7 +4846,7 @@ pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] @@ -4637,7 +4875,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] #[cfg_attr( @@ -4667,7 +4905,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] #[cfg_attr( @@ -4697,7 +4935,7 @@ pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] @@ -4726,7 +4964,7 @@ pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] @@ -4755,7 +4993,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] #[cfg_attr( @@ -4777,7 +5015,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] #[cfg_attr( @@ -4799,7 +5037,7 @@ pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] @@ -4820,7 +5058,7 @@ pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] @@ -4841,7 +5079,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] #[cfg_attr( @@ -4863,7 +5101,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] #[cfg_attr( @@ -4885,7 +5123,7 @@ pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] @@ -4906,7 +5144,7 @@ pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] @@ -4927,7 +5165,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))] #[cfg_attr( @@ -4949,7 +5187,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))] #[cfg_attr( @@ -4971,7 +5209,7 @@ pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))] @@ -4992,7 +5230,7 @@ pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))] @@ -5013,7 +5251,7 @@ pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5034,7 +5272,7 @@ pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5055,7 +5293,7 @@ pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] @@ -5076,7 +5314,7 @@ pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] @@ -5097,7 +5335,7 @@ pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] @@ -5118,7 +5356,7 @@ pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] @@ -5139,7 +5377,7 @@ pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5160,7 +5398,7 @@ pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5181,7 +5419,7 @@ pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] @@ -5202,7 +5440,7 @@ pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] @@ -5223,7 +5461,7 @@ pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] @@ -5244,7 +5482,7 @@ pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] @@ -5265,7 +5503,7 @@ pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5286,7 +5524,7 @@ pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] @@ -5307,7 +5545,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -5329,7 +5567,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -5351,7 +5589,7 @@ pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] @@ -5372,7 +5610,7 @@ pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] @@ -5393,7 +5631,7 @@ pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] @@ -5414,7 +5652,7 @@ pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] @@ -5435,7 +5673,7 @@ pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] @@ -5456,7 +5694,7 @@ pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] @@ -5477,7 +5715,7 @@ pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] @@ -5498,7 +5736,7 @@ pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] @@ -5519,7 +5757,7 @@ pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] @@ -5540,7 +5778,7 @@ pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] @@ -5561,7 +5799,7 @@ pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] @@ -5582,7 +5820,7 @@ pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] @@ -5603,7 +5841,7 @@ pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] @@ -5624,7 +5862,7 @@ pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] @@ -5645,7 +5883,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -5668,7 +5906,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -5691,7 +5929,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -5713,7 +5951,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -5735,7 +5973,7 @@ pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] @@ -5756,7 +5994,7 @@ pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] @@ -5777,7 +6015,7 @@ pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] @@ -5798,7 +6036,7 @@ pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] @@ -5819,7 +6057,7 @@ pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] @@ -5840,7 +6078,7 @@ pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] @@ -5861,7 +6099,7 @@ pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] @@ -5882,7 +6120,7 @@ pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] @@ -5903,7 +6141,7 @@ pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] @@ -5924,7 +6162,7 @@ pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] @@ -5945,7 +6183,7 @@ pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] @@ -5966,7 +6204,7 @@ pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] @@ -5987,7 +6225,7 @@ pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] @@ -6008,7 +6246,7 @@ pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] @@ -6029,7 +6267,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -6052,7 +6290,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -6075,7 +6313,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -6097,7 +6335,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] #[cfg_attr( @@ -6119,7 +6357,7 @@ pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] @@ -6140,7 +6378,7 @@ pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] @@ -6161,7 +6399,7 @@ pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] @@ -6182,7 +6420,7 @@ pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] @@ -6203,7 +6441,7 @@ pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] @@ -6224,7 +6462,7 @@ pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] @@ -6245,7 +6483,7 @@ pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] @@ -6266,7 +6504,7 @@ pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] @@ -6287,7 +6525,7 @@ pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] @@ -6308,7 +6546,7 @@ pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] @@ -6329,7 +6567,7 @@ pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] @@ -6350,7 +6588,7 @@ pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] @@ -6371,7 +6609,7 @@ pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] @@ -6392,7 +6630,7 @@ pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] @@ -6413,7 +6651,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))] #[cfg_attr( @@ -6436,7 +6674,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))] #[cfg_attr( @@ -6459,7 +6697,7 @@ pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))] @@ -6488,7 +6726,7 @@ pub fn vcls_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))] @@ -6517,7 +6755,7 @@ pub fn vclsq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))] @@ -6546,7 +6784,7 @@ pub fn vcls_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))] @@ -6575,7 +6813,7 @@ pub fn vclsq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))] @@ -6604,7 +6842,7 @@ pub fn vcls_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))] @@ -6633,7 +6871,7 @@ pub fn vclsq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6654,7 +6892,7 @@ pub fn vcls_u8(a: uint8x8_t) -> int8x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6675,7 +6913,7 @@ pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6696,7 +6934,7 @@ pub fn vcls_u16(a: uint16x4_t) -> int16x4_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6717,7 +6955,7 @@ pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6738,7 +6976,7 @@ pub fn vcls_u32(a: uint32x2_t) -> int32x2_t { } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] @@ -6759,7 +6997,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -6781,7 +7019,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] #[cfg_attr( @@ -6803,7 +7041,7 @@ pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] @@ -6824,7 +7062,7 @@ pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] @@ -6845,7 +7083,7 @@ pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] @@ -6866,7 +7104,7 @@ pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] @@ -6887,7 +7125,7 @@ pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] @@ -6908,7 +7146,7 @@ pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] @@ -6929,7 +7167,7 @@ pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] @@ -6950,7 +7188,7 @@ pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] @@ -6971,7 +7209,7 @@ pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] @@ -6992,7 +7230,7 @@ pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] @@ -7013,7 +7251,7 @@ pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] @@ -7034,7 +7272,7 @@ pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] @@ -7055,7 +7293,7 @@ pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] @@ -7076,7 +7314,7 @@ pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] @@ -7097,7 +7335,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))] #[cfg_attr( @@ -7120,7 +7358,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))] #[cfg_attr( @@ -7143,7 +7381,7 @@ pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] @@ -7164,7 +7402,7 @@ pub fn vclz_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] @@ -7185,7 +7423,7 @@ pub fn vclzq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] @@ -7206,7 +7444,7 @@ pub fn vclz_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] @@ -7227,7 +7465,7 @@ pub fn vclzq_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] @@ -7248,7 +7486,7 @@ pub fn vclz_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] @@ -7269,8 +7507,7 @@ pub fn vclzq_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] @@ -7290,35 +7527,8 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t { unsafe { transmute(vclz_s16(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] @@ -7338,35 +7548,8 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { unsafe { transmute(vclzq_s16(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] @@ -7386,35 +7569,8 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t { unsafe { transmute(vclz_s32(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a))); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] @@ -7434,35 +7590,8 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { unsafe { transmute(vclzq_s32(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] @@ -7482,35 +7611,8 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t { unsafe { transmute(vclz_s8(transmute(a))) } } #[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] @@ -7529,40 +7631,9 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t { pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { unsafe { transmute(vclzq_s8(transmute(a))) } } -#[doc = "Count leading zero bits"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(clz) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7583,7 +7654,7 @@ pub fn vcnt_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7604,8 +7675,7 @@ pub fn vcntq_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7625,9 +7695,8 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { unsafe { transmute(vcnt_s8(transmute(a))) } } #[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7643,17 +7712,12 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vcntq_s8(transmute(a))) } } #[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7669,13 +7733,12 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { - unsafe { transmute(vcntq_s8(transmute(a))) } +pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { transmute(vcnt_s8(transmute(a))) } } #[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] @@ -7691,77 +7754,61 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { transmute(vcntq_s8(transmute(a))) } } -#[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cnt) -)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { - unsafe { transmute(vcnt_s8(transmute(a))) } +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } -#[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cnt) -)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { unsafe { - let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a))); + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cnt) -)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -7770,20 +7817,16 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { - unsafe { transmute(vcntq_s8(transmute(a))) } +pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } -#[doc = "Population count per byte."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cnt) -)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -7792,40 +7835,36 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { unsafe { - let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7837,12 +7876,23 @@ pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } +pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = + simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7854,12 +7904,13 @@ pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7872,11 +7923,17 @@ pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7892,8 +7949,32 @@ pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t { unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } #[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7909,8 +7990,9 @@ pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { unsafe { simd_shuffle!(a, b, [0, 1]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7922,12 +8004,16 @@ pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { + unsafe { + let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7939,12 +8025,13 @@ pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7956,12 +8043,23 @@ pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } +pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7973,12 +8071,13 @@ pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { - unsafe { simd_shuffle!(a, b, [0, 1]) } +pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -7990,12 +8089,18 @@ pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8007,12 +8112,13 @@ pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { - unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } #[doc = "Join two smaller vectors into a single larger vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8024,71 +8130,60 @@ pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { - unsafe { simd_shuffle!(a, b, [0, 1]) } +pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vcreate_f16(a: u64) -> float16x4_t { - unsafe { transmute(a) } +pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vcreate_f16(a: u64) -> float16x4_t { +pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8097,20 +8192,16 @@ pub fn vcreate_f16(a: u64) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_f32(a: u64) -> float32x2_t { - unsafe { transmute(a) } +pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8119,23 +8210,26 @@ pub fn vcreate_f32(a: u64) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_f32(a: u64) -> float32x2_t { +pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8144,20 +8238,16 @@ pub fn vcreate_f32(a: u64) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s8(a: u64) -> int8x8_t { - unsafe { transmute(a) } +pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8166,23 +8256,21 @@ pub fn vcreate_s8(a: u64) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s8(a: u64) -> int8x8_t { +pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { unsafe { - let ret_val: int8x8_t = transmute(a); + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8191,20 +8279,16 @@ pub fn vcreate_s8(a: u64) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s16(a: u64) -> int16x4_t { - unsafe { transmute(a) } +pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } } -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] -#[inline(always)] +#[doc = "Join two smaller vectors into a single larger vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -8213,16 +8297,15 @@ pub fn vcreate_s16(a: u64) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s16(a: u64) -> int16x4_t { +pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8230,21 +8313,22 @@ pub fn vcreate_s16(a: u64) -> int16x4_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s32(a: u64) -> int32x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vcreate_f16(a: u64) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8260,15 +8344,12 @@ pub fn vcreate_s32(a: u64) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s32(a: u64) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vcreate_f32(a: u64) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8284,13 +8365,12 @@ pub fn vcreate_s32(a: u64) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_s64(a: u64) -> int64x1_t { +pub fn vcreate_s8(a: u64) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8306,13 +8386,12 @@ pub fn vcreate_s64(a: u64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u8(a: u64) -> uint8x8_t { +pub fn vcreate_s16(a: u64) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8328,16 +8407,12 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u8(a: u64) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vcreate_s32(a: u64) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8353,13 +8428,12 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u16(a: u64) -> uint16x4_t { +pub fn vcreate_s64(a: u64) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8375,16 +8449,12 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u16(a: u64) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vcreate_u8(a: u64) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8400,13 +8470,12 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vcreate_u32(a: u64) -> uint32x2_t { +pub fn vcreate_u16(a: u64) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8423,14 +8492,11 @@ pub fn vcreate_u32(a: u64) -> uint32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vcreate_u32(a: u64) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8451,8 +8517,7 @@ pub fn vcreate_u64(a: u64) -> uint64x1_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8472,34 +8537,8 @@ pub fn vcreate_p8(a: u64) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vcreate_p8(a: u64) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8519,33 +8558,8 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vcreate_p16(a: u64) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -8566,7 +8580,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t { } #[doc = "Floating-point convert to lower precision narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8589,7 +8603,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -8611,7 +8625,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -8633,7 +8647,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -8655,7 +8669,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -8677,7 +8691,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t { } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8700,7 +8714,7 @@ pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8721,7 +8735,7 @@ pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8742,7 +8756,7 @@ pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8763,7 +8777,7 @@ pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -8784,7 +8798,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -8819,7 +8833,7 @@ pub fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -8854,7 +8868,7 @@ pub fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -8889,7 +8903,7 @@ pub fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -8924,7 +8938,7 @@ pub fn vcvtq_n_f16_u16(a: uint16x8_t) -> float16x8_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -8943,7 +8957,7 @@ pub fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -8962,7 +8976,7 @@ pub fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(scvtf, N = 2))] @@ -8981,7 +8995,7 @@ pub fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(scvtf, N = 2))] @@ -9000,7 +9014,7 @@ pub fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9019,7 +9033,7 @@ pub fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9038,7 +9052,7 @@ pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] @@ -9057,7 +9071,7 @@ pub fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] @@ -9076,7 +9090,7 @@ pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -9111,7 +9125,7 @@ pub fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -9146,7 +9160,7 @@ pub fn vcvtq_n_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9165,7 +9179,7 @@ pub fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9184,7 +9198,7 @@ pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] @@ -9203,7 +9217,7 @@ pub fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] @@ -9222,7 +9236,7 @@ pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -9257,7 +9271,7 @@ pub fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] #[cfg_attr( @@ -9292,7 +9306,7 @@ pub fn vcvtq_n_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9311,7 +9325,7 @@ pub fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] @@ -9330,7 +9344,7 @@ pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] @@ -9349,7 +9363,7 @@ pub fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] @@ -9368,7 +9382,7 @@ pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -9390,7 +9404,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -9412,7 +9426,7 @@ pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -9441,7 +9455,7 @@ pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t { } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -9470,7 +9484,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -9492,7 +9506,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] #[cfg_attr( @@ -9514,7 +9528,7 @@ pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -9543,7 +9557,7 @@ pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t { } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -9572,8 +9586,7 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] @@ -9592,77 +9605,13 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { )] pub fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vdot_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vdotq_lane_s32(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: int32x2_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, transmute(c)) - } + let c = vreinterpret_s32_s8(c); + let c = vdup_lane_s32::(c); + vdot_s32(a, b, vreinterpret_s8_s32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] @@ -9681,50 +9630,13 @@ pub fn vdotq_lane_s32(a: int32x4_t, b: int8x16_t, c: int8x8_t) )] pub fn vdotq_lane_s32(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: int8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x2_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(udot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, transmute(c)) - } + let c = vreinterpret_s32_s8(c); + let c = vdupq_lane_s32::(c); + vdotq_s32(a, b, vreinterpretq_s8_s32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] @@ -9743,20 +9655,13 @@ pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) )] pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + let c = vreinterpret_u32_u8(c); + let c = vdup_lane_u32::(c); + vdot_u32(a, b, vreinterpret_u8_u32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] @@ -9775,51 +9680,13 @@ pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) )] pub fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(udot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_dotprod", issue = "117224") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } + let c = vreinterpret_u32_u8(c); + let c = vdupq_lane_u32::(c); + vdotq_u32(a, b, vreinterpretq_u8_u32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] @@ -9831,42 +9698,13 @@ pub fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_ #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vdot_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + let c = vreinterpretq_s32_s8(c); + let c = vdup_laneq_s32::(c); + vdot_s32(a, b, vreinterpret_s8_s32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] @@ -9878,45 +9716,13 @@ pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sdot, LANE = 0) -)] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: int8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } + let c = vreinterpretq_s32_s8(c); + let c = vdupq_laneq_s32::(c); + vdotq_s32(a, b, vreinterpretq_s8_s32(c)) } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] @@ -9928,16 +9734,13 @@ pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, transmute(c)) - } + let c = vreinterpretq_u32_u8(c); + let c = vdup_laneq_u32::(c); + vdot_u32(a, b, vreinterpret_u8_u32(c)) } #[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] @@ -9947,72 +9750,46 @@ pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_ )] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { +pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } + let c = vreinterpretq_u32_u8(c); + let c = vdupq_laneq_u32::(c); + vdotq_u32(a, b, vreinterpretq_u8_u32(c)) } -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] -#[inline(always)] +#[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] +#[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(udot, LANE = 0) + assert_instr(sdot) )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, transmute(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(udot, LANE = 0) + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8" + )] + fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; } + unsafe { _vdot_s32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] @@ -10037,11 +9814,18 @@ pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { )] fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; } - unsafe { _vdot_s32(a, b, c) } + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int32x2_t = _vdot_s32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] @@ -10069,8 +9853,47 @@ pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { unsafe { _vdotq_s32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8" + )] + fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; + } + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int32x4_t = _vdotq_s32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] @@ -10098,8 +9921,45 @@ pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { unsafe { _vdot_u32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.udot.v2i32.v8i8" + )] + fn _vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t; + } + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint32x2_t = _vdot_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] @@ -10126,9 +9986,48 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { } unsafe { _vdotq_u32(a, b, c) } } +#[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.udot.v4i32.v16i8" + )] + fn _vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t; + } + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: uint8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint32x4_t = _vdotq_u32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] @@ -10152,8 +10051,9 @@ pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] @@ -10172,59 +10072,74 @@ pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { +pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 1) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 1) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] @@ -10241,13 +10156,14 @@ pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(N, 1); unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] @@ -10264,13 +10180,18 @@ pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { +pub fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] @@ -10287,13 +10208,14 @@ pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { +pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] @@ -10310,19 +10232,24 @@ pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { +pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10333,19 +10260,20 @@ pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32; 4]) } +pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10356,19 +10284,24 @@ pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32; 4]) } +pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10379,19 +10312,20 @@ pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32; 4]) } +pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10402,19 +10336,24 @@ pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10425,19 +10364,20 @@ pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10448,19 +10388,24 @@ pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10471,19 +10416,20 @@ pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 1) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10494,19 +10440,24 @@ pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10517,19 +10468,20 @@ pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10540,19 +10492,24 @@ pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 16]) } +pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10563,19 +10520,20 @@ pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 16]) } +pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10586,19 +10544,24 @@ pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 16]) } +pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 0) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10609,19 +10572,20 @@ pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { - static_assert!(N == 0); - a +pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 0) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10632,66 +10596,73 @@ pub fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { - static_assert!(N == 0); - a +pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 4]) } +pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 4) + assert_instr(dup, N = 2) )] #[rustc_legacy_const_generics(1)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2) @@ -10705,16 +10676,17 @@ pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { +pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2) @@ -10728,16 +10700,21 @@ pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { +pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2) @@ -10751,16 +10728,17 @@ pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { +pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2) @@ -10774,19 +10752,24 @@ pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { +pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10797,19 +10780,20 @@ pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } +pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 2) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10820,16 +10804,21 @@ pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } +pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10843,16 +10832,17 @@ pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { +pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 4]) } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10866,16 +10856,21 @@ pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { +pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 4]) } + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10889,16 +10884,17 @@ pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { +pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 4]) } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10912,16 +10908,21 @@ pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { +pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10935,16 +10936,17 @@ pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { +pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4) @@ -10958,19 +10960,28 @@ pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -10981,19 +10992,20 @@ pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11004,19 +11016,28 @@ pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11027,19 +11048,20 @@ pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shuffle!(a, a, [N as u32; 8]) } +pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11050,19 +11072,27 @@ pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shuffle!(a, a, [N as u32; 16]) } +pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(nop, N = 0) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11073,19 +11103,19 @@ pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shuffle!(a, a, [N as u32; 16]) } +pub fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { + static_assert!(N == 0); + a } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 8) + assert_instr(nop, N = 0) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11096,119 +11126,134 @@ pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 4); - unsafe { simd_shuffle!(a, a, [N as u32; 16]) } +pub fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { + static_assert!(N == 0); + a } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 1) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { - static_assert_uimm_bits!(N, 1); - unsafe { transmute::(simd_extract!(a, N as u32)) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 1) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 1); - unsafe { transmute::(simd_extract!(a, N as u32)) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Create a new vector with all lanes set to a value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vdup_n_f16(a: f16) -> float16x4_t { - float16x4_t::splat(a) -} -#[doc = "Create a new vector with all lanes set to a value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub fn vdupq_n_f16(a: f16) -> float16x8_t { - float16x8_t::splat(a) +pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_f32(value: f32) -> float32x2_t { - float32x2_t::splat(value) +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11217,19 +11262,22 @@ pub fn vdup_n_f32(value: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_p16(value: p16) -> poly16x4_t { - poly16x4_t::splat(value) +pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11238,19 +11286,26 @@ pub fn vdup_n_p16(value: p16) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_p8(value: p8) -> poly8x8_t { - poly8x8_t::splat(value) +pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11259,19 +11314,22 @@ pub fn vdup_n_p8(value: p8) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_s16(value: i16) -> int16x4_t { - int16x4_t::splat(value) +pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11280,19 +11338,26 @@ pub fn vdup_n_s16(value: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_s32(value: i32) -> int32x2_t { - int32x2_t::splat(value) +pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmov) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11301,19 +11366,22 @@ pub fn vdup_n_s32(value: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_s64(value: i64) -> int64x1_t { - int64x1_t::splat(value) +pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11322,19 +11390,26 @@ pub fn vdup_n_s64(value: i64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_s8(value: i8) -> int8x8_t { - int8x8_t::splat(value) +pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11343,19 +11418,22 @@ pub fn vdup_n_s8(value: i8) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_u16(value: u16) -> uint16x4_t { - uint16x4_t::splat(value) +pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11364,19 +11442,26 @@ pub fn vdup_n_u16(value: u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_u32(value: u32) -> uint32x2_t { - uint32x2_t::splat(value) +pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmov) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11385,19 +11470,22 @@ pub fn vdup_n_u32(value: u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_u64(value: u64) -> uint64x1_t { - uint64x1_t::splat(value) +pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11406,19 +11494,26 @@ pub fn vdup_n_u64(value: u64) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdup_n_u8(value: u8) -> uint8x8_t { - uint8x8_t::splat(value) +pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11427,19 +11522,22 @@ pub fn vdup_n_u8(value: u8) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_f32(value: f32) -> float32x4_t { - float32x4_t::splat(value) +pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11448,19 +11546,26 @@ pub fn vdupq_n_f32(value: f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_p16(value: p16) -> poly16x8_t { - poly16x8_t::splat(value) +pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11469,19 +11574,22 @@ pub fn vdupq_n_p16(value: p16) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_p8(value: p8) -> poly8x16_t { - poly8x16_t::splat(value) +pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11490,19 +11598,26 @@ pub fn vdupq_n_p8(value: p8) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_s16(value: i16) -> int16x8_t { - int16x8_t::splat(value) +pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11511,19 +11626,22 @@ pub fn vdupq_n_s16(value: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_s32(value: i32) -> int32x4_t { - int32x4_t::splat(value) +pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11532,19 +11650,26 @@ pub fn vdupq_n_s32(value: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_s64(value: i64) -> int64x2_t { - int64x2_t::splat(value) +pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11553,19 +11678,22 @@ pub fn vdupq_n_s64(value: i64) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_s8(value: i8) -> int8x16_t { - int8x16_t::splat(value) +pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11574,19 +11702,26 @@ pub fn vdupq_n_s8(value: i8) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_u16(value: u16) -> uint16x8_t { - uint16x8_t::splat(value) +pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [N as u32; 4]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11595,19 +11730,22 @@ pub fn vdupq_n_u16(value: u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_u32(value: u32) -> uint32x4_t { - uint32x4_t::splat(value) +pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11616,19 +11754,26 @@ pub fn vdupq_n_u32(value: u32) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_u64(value: u64) -> uint64x2_t { - uint64x2_t::splat(value) +pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11637,19 +11782,22 @@ pub fn vdupq_n_u64(value: u64) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_n_u8(value: u8) -> uint8x16_t { - uint8x16_t::splat(value) +pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11658,19 +11806,26 @@ pub fn vdupq_n_u8(value: u8) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -fn vdup_n_f32_vfp4(value: f32) -> float32x2_t { - float32x2_t::splat(value) +pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) + assert_instr(dup, N = 4) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11679,18 +11834,20 @@ fn vdup_n_f32_vfp4(value: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { - float32x4_t::splat(value) +pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 0) + assert_instr(dup, N = 4) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11701,19 +11858,24 @@ fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { - static_assert!(N == 0); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 0) + assert_instr(dup, N = 8) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11724,19 +11886,20 @@ pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { - static_assert!(N == 0); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 1) + assert_instr(dup, N = 8) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11747,19 +11910,25 @@ pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Set all vector lanes to the same value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup, N = 1) + assert_instr(dup, N = 8) )] #[rustc_legacy_const_generics(1)] #[cfg_attr( @@ -11770,20 +11939,22 @@ pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } +pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11792,19 +11963,27 @@ pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11813,19 +11992,22 @@ pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11834,19 +12016,27 @@ pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [N as u32; 8]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11855,19 +12045,22 @@ pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11876,19 +12069,31 @@ pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11897,19 +12102,22 @@ pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11918,19 +12126,31 @@ pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11939,19 +12159,22 @@ pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup, N = 8) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11960,19 +12183,30 @@ pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_xor(a, b) } +pub fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!(a, a, [N as u32; 16]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(nop, N = 1) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -11981,19 +12215,21 @@ pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { + static_assert_uimm_bits!(N, 1); + unsafe { transmute(vgetq_lane_s64::(a)) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(nop, N = 1) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12002,39 +12238,51 @@ pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_xor(a, b) } +pub fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 1); + unsafe { transmute(vgetq_lane_u64::(a)) } } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"] -#[inline(always)] +#[doc = "Create a new vector with all lanes set to a value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(dup) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdup_n_f16(a: f16) -> float16x4_t { + float16x4_t::splat(a) +} +#[doc = "Create a new vector with all lanes set to a value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup) )] -pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_xor(a, b) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vdupq_n_f16(a: f16) -> float16x8_t { + float16x8_t::splat(a) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12044,18 +12292,18 @@ pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_f32(value: f32) -> float32x2_t { + float32x2_t::splat(value) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12065,18 +12313,18 @@ pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_p16(value: p16) -> poly16x4_t { + poly16x4_t::splat(value) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12086,18 +12334,18 @@ pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_p8(value: p8) -> poly8x8_t { + poly8x8_t::splat(value) } -#[doc = "Vector bitwise exclusive or (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(eor) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -12107,52 +12355,40 @@ pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { simd_xor(a, b) } +pub fn vdup_n_s16(value: i16) -> int16x4_t { + int16x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_s32(value: i32) -> int32x2_t { + int32x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(fmov) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12161,27 +12397,19 @@ pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_s64(value: i64) -> int64x1_t { + int64x1_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12190,27 +12418,19 @@ pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_s8(value: i8) -> int8x8_t { + int8x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12219,29 +12439,19 @@ pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_u16(value: u16) -> uint16x4_t { + uint16x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 0) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12250,23 +12460,19 @@ pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { - static_assert!(N == 0); - a +pub fn vdup_n_u32(value: u32) -> uint32x2_t { + uint32x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, N = 0) + assert_instr(fmov) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12275,21 +12481,19 @@ pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t { - static_assert!(N == 0); - a +pub fn vdup_n_u64(value: u64) -> uint64x1_t { + uint64x1_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12298,33 +12502,19 @@ pub unsafe fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdup_n_u8(value: u8) -> uint8x8_t { + uint8x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12333,33 +12523,19 @@ pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_f32(value: f32) -> float32x4_t { + float32x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12368,33 +12544,19 @@ pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_p16(value: p16) -> poly16x8_t { + poly16x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12403,33 +12565,19 @@ pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_p8(value: p8) -> poly8x16_t { + poly8x16_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12438,33 +12586,19 @@ pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_s16(value: i16) -> int16x8_t { + int16x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12473,69 +12607,40 @@ pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_s32(value: i32) -> int32x4_t { + int32x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 7) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - static_assert_uimm_bits!(N, 3); - unsafe { - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_s64(value: i64) -> int64x2_t { + int64x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12544,29 +12649,19 @@ pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_s8(value: i8) -> int8x16_t { + int8x16_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12575,29 +12670,19 @@ pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_u16(value: u16) -> uint16x8_t { + uint16x8_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12606,29 +12691,19 @@ pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_u32(value: u32) -> uint32x4_t { + uint32x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12637,29 +12712,19 @@ pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_u64(value: u64) -> uint64x2_t { + uint64x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12668,29 +12733,19 @@ pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_n_u8(value: u8) -> uint8x16_t { + uint8x16_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 3) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12699,29 +12754,19 @@ pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } - } +fn vdup_n_f32_vfp4(value: f32) -> float32x2_t { + float32x2_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(dup) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12730,27 +12775,21 @@ pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { + float32x4_t::splat(value) } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 1) + assert_instr(dup, N = 0) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12759,27 +12798,22 @@ pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { + static_assert!(N == 0); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 15) + assert_instr(dup, N = 0) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12788,101 +12822,25 @@ pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 4); +pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { + static_assert!(N == 0); unsafe { - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), - } + let ret_val: int64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 15) + assert_instr(dup, N = 0) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12891,101 +12849,22 @@ pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 4); - unsafe { - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), - } - } +pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { + static_assert!(N == 0); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Extract vector from pair of vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext, N = 15) + assert_instr(dup, N = 0) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -12994,144 +12873,77 @@ pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 4); +pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { + static_assert!(N == 0); unsafe { - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), - } + let ret_val: uint64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(dup, N = 1) )] -#[target_feature(enable = "neon,fp16")] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { - unsafe { simd_fma(b, c, a) } +pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(dup, N = 1) )] -#[target_feature(enable = "neon,fp16")] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { - unsafe { simd_fma(b, c, a) } +pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(dup, N = 1) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13140,19 +12952,22 @@ pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - unsafe { simd_fma(b, c, a) } +pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } -#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"] -#[inline(always)] +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(dup, N = 1) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13161,18 +12976,23 @@ pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - unsafe { simd_fma(b, c, a) } +pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13182,18 +13002,18 @@ pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vfma_f32(a, b, vdup_n_f32_vfp4(c)) +pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmla) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13203,70 +13023,60 @@ pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vfmaq_f32(a, b, vdupq_n_f32_vfp4(c)) +pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { - unsafe { - let b: float16x4_t = simd_neg(b); - vfma_f16(a, b, c) - } +pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { - unsafe { - let b: float16x8_t = simd_neg(b); - vfmaq_f16(a, b, c) - } +pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13276,21 +13086,18 @@ pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - unsafe { - let b: float32x2_t = simd_neg(b); - vfma_f32(a, b, c) - } +pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13300,21 +13107,18 @@ pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - unsafe { - let b: float32x4_t = simd_neg(b); - vfmaq_f32(a, b, c) - } +pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13324,18 +13128,18 @@ pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vfms_f32(a, b, vdup_n_f32_vfp4(c)) +pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmls) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13345,56 +13149,60 @@ pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vfmsq_f32(a, b, vdupq_n_f32_vfp4(c)) +pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { - unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(test, assert_instr(nop))] -pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13404,18 +13212,18 @@ pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { - unsafe { simd_shuffle!(a, a, [2, 3]) } +pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13425,18 +13233,18 @@ pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { - unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13446,18 +13254,18 @@ pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13467,18 +13275,18 @@ pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_s16(a: int16x8_t) -> int16x4_t { - unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13488,18 +13296,18 @@ pub fn vget_high_s16(a: int16x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_s32(a: int32x4_t) -> int32x2_t { - unsafe { simd_shuffle!(a, a, [2, 3]) } +pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"] -#[inline(always)] +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(eor) )] #[cfg_attr( not(target_arch = "arm"), @@ -13509,61 +13317,77 @@ pub fn vget_high_s32(a: int32x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_s8(a: int8x16_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_xor(a, b) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 3) )] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 3) )] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { - unsafe { simd_shuffle!(a, a, [2, 3]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13572,19 +13396,22 @@ pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13593,19 +13420,27 @@ pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { - unsafe { int64x1_t([simd_extract!(a, 1)]) } +pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ext) + assert_instr(ext, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13614,52 +13449,22 @@ pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { - unsafe { uint64x1_t([simd_extract!(a, 1)]) } -} -#[doc = "Duplicate vector element to scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) -)] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vget_lane_f16(a: float16x4_t) -> f16 { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_extract!(a, LANE as u32) } +pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop, LANE = 0) + assert_instr(ext, N = 1) )] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_extract!(a, LANE as u32) } -} -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13668,17 +13473,27 @@ pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_f32(v: float32x2_t) -> f32 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13687,17 +13502,22 @@ pub fn vget_lane_f32(v: float32x2_t) -> f32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_p16(v: poly16x4_t) -> p16 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13706,17 +13526,28 @@ pub fn vget_lane_p16(v: poly16x4_t) -> p16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_p8(v: poly8x8_t) -> p8 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, N = 0) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13725,17 +13556,23 @@ pub fn vget_lane_p8(v: poly8x8_t) -> p8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_s16(v: int16x4_t) -> i16 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { + static_assert!(N == 0); + a } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, N = 0) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13744,17 +13581,22 @@ pub fn vget_lane_s16(v: int16x4_t) -> i16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_s32(v: int32x2_t) -> i32 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub unsafe fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t { + static_assert!(N == 0); + a } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13763,17 +13605,37 @@ pub fn vget_lane_s32(v: int32x2_t) -> i32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_s8(v: int8x8_t) -> i8 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13782,17 +13644,40 @@ pub fn vget_lane_s8(v: int8x8_t) -> i8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_u16(v: uint16x4_t) -> u16 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13801,17 +13686,37 @@ pub fn vget_lane_u16(v: uint16x4_t) -> u16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_u32(v: uint32x2_t) -> u32 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13820,17 +13725,40 @@ pub fn vget_lane_u32(v: uint32x2_t) -> u32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_u8(v: uint8x8_t) -> u8 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13839,17 +13767,37 @@ pub fn vget_lane_u8(v: uint8x8_t) -> u8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13858,17 +13806,40 @@ pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13877,17 +13848,37 @@ pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13896,17 +13887,40 @@ pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { - static_assert_uimm_bits!(IMM5, 4); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13915,17 +13929,37 @@ pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_s16(v: int16x8_t) -> i16 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13934,17 +13968,40 @@ pub fn vgetq_lane_s16(v: int16x8_t) -> i16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_s32(v: int32x4_t) -> i32 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13953,17 +14010,37 @@ pub fn vgetq_lane_s32(v: int32x4_t) -> i32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { - static_assert_uimm_bits!(IMM5, 1); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -13972,55 +14049,123 @@ pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_s8(v: int8x16_t) -> i8 { - static_assert_uimm_bits!(IMM5, 4); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_u16(v: uint16x8_t) -> u16 { - static_assert_uimm_bits!(IMM5, 3); - unsafe { simd_extract!(v, IMM5 as u32) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(N, 3); + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7 + ] + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14029,17 +14174,22 @@ pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { - static_assert_uimm_bits!(IMM5, 2); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14048,17 +14198,28 @@ pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { - static_assert_uimm_bits!(IMM5, 4); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14067,17 +14228,22 @@ pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_p64(v: poly64x1_t) -> p64 { - static_assert!(IMM5 == 0); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14086,17 +14252,28 @@ pub fn vget_lane_p64(v: poly64x1_t) -> p64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_s64(v: int64x1_t) -> i64 { - static_assert!(IMM5 == 0); - unsafe { simd_extract!(v, IMM5 as u32) } +pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Move vector element to general-purpose register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14105,16 +14282,22 @@ pub fn vget_lane_s64(v: int64x1_t) -> i64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_lane_u64(v: uint64x1_t) -> u64 { - static_assert!(IMM5 == 0); - unsafe { simd_extract!(v, 0) } +pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14123,15 +14306,28 @@ pub fn vget_lane_u64(v: uint64x1_t) -> u64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { - unsafe { simd_shuffle!(a, a, [0, 1]) } +pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14140,15 +14336,22 @@ pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14157,15 +14360,28 @@ pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14174,15 +14390,22 @@ pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14191,15 +14414,28 @@ pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { - unsafe { simd_shuffle!(a, a, [0, 1]) } +pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14208,15 +14444,22 @@ pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14225,15 +14468,28 @@ pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = + simd_shuffle!(a, b, [N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14242,15 +14498,22 @@ pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { - unsafe { simd_shuffle!(a, a, [0, 1]) } +pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14259,15 +14522,27 @@ pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14276,15 +14551,22 @@ pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { - unsafe { int64x1_t([simd_extract!(a, 0)]) } +pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) } } -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14293,19 +14575,27 @@ pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { - unsafe { uint64x1_t([simd_extract!(a, 0)]) } +pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14314,27 +14604,45 @@ pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")] - fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; +pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ) } - unsafe { _vhadd_s8(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14343,27 +14651,54 @@ pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")] - fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; +pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } - unsafe { _vhaddq_s8(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14372,27 +14707,45 @@ pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")] - fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; +pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ) } - unsafe { _vhadd_s16(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14401,27 +14754,54 @@ pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")] - fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; +pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } - unsafe { _vhaddq_s16(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14430,27 +14810,45 @@ pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")] - fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; +pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ) } - unsafe { _vhadd_s32(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"] -#[inline(always)] +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shadd) + assert_instr(ext, N = 15) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -14459,84 +14857,95 @@ pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shadd.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")] - fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; +pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_shuffle!( + a, + b, + [ + N as u32, + N as u32 + 1, + N as u32 + 2, + N as u32 + 3, + N as u32 + 4, + N as u32 + 5, + N as u32 + 6, + N as u32 + 7, + N as u32 + 8, + N as u32 + 9, + N as u32 + 10, + N as u32 + 11, + N as u32 + 12, + N as u32 + 13, + N as u32 + 14, + N as u32 + 15 + ] + ); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } - unsafe { _vhaddq_s32(a, b) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] +#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")] - fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } - unsafe { _vhadd_u8(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe { simd_fma(b, c, a) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] +#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")] - fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; - } - unsafe { _vhaddq_u8(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe { simd_fma(b, c, a) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] #[cfg_attr( not(target_arch = "arm"), @@ -14546,26 +14955,18 @@ pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")] - fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } - unsafe { _vhadd_u16(a, b) } +pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { simd_fma(b, c, a) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] #[cfg_attr( not(target_arch = "arm"), @@ -14575,26 +14976,18 @@ pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")] - fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; - } - unsafe { _vhaddq_u16(a, b) } +pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { simd_fma(b, c, a) } } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] #[cfg_attr( not(target_arch = "arm"), @@ -14604,26 +14997,18 @@ pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")] - fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } - unsafe { _vhadd_u32(a, b) } +pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vfma_f32(a, b, vdup_n_f32_vfp4(c)) } -#[doc = "Halving add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhadd) + assert_instr(fmla) )] #[cfg_attr( not(target_arch = "arm"), @@ -14633,84 +15018,70 @@ pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhadd.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")] - fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } - unsafe { _vhaddq_u32(a, b) } +pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vfmaq_f32(a, b, vdupq_n_f32_vfp4(c)) } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")] - fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; +#[cfg(not(target_arch = "arm64ec"))] +pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe { + let b: float16x4_t = simd_neg(b); + vfma_f16(a, b, c) } - unsafe { _vhsub_s16(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")] - fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; +#[cfg(not(target_arch = "arm64ec"))] +pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe { + let b: float16x8_t = simd_neg(b); + vfmaq_f16(a, b, c) } - unsafe { _vhsubq_s16(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"] -#[inline(always)] +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] #[cfg_attr( not(target_arch = "arm"), @@ -14720,26 +15091,21 @@ pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")] - fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; +pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { + let b: float32x2_t = simd_neg(b); + vfma_f32(a, b, c) } - unsafe { _vhsub_s32(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"] -#[inline(always)] +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] #[cfg_attr( not(target_arch = "arm"), @@ -14749,26 +15115,21 @@ pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")] - fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; +pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { + let b: float32x4_t = simd_neg(b); + vfmaq_f32(a, b, c) } - unsafe { _vhsubq_s32(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] #[cfg_attr( not(target_arch = "arm"), @@ -14778,26 +15139,18 @@ pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")] - fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vhsub_s8(a, b) } +pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vfms_f32(a, b, vdup_n_f32_vfp4(c)) } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"] -#[inline(always)] +#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(shsub) + assert_instr(fmls) )] #[cfg_attr( not(target_arch = "arm"), @@ -14807,84 +15160,107 @@ pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.shsub.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")] - fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } - unsafe { _vhsubq_s8(a, b) } +pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vfmsq_f32(a, b, vdupq_n_f32_vfp4(c)) } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } +} +#[doc = "Duplicate vector element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")] - fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vhsub_u8(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } +} +#[doc = "Duplicate vector element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")] - fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; +#[cfg(not(target_arch = "arm64ec"))] +#[cfg_attr(test, assert_instr(nop))] +pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vhsubq_u8(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -14894,26 +15270,19 @@ pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")] - fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } - unsafe { _vhsub_u16(a, b) } +pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -14923,26 +15292,23 @@ pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")] - fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; +pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [2, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } - unsafe { _vhsubq_u16(a, b) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -14952,26 +15318,19 @@ pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")] - fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } - unsafe { _vhsub_u32(a, b) } +pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } -#[doc = "Signed halving subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uhsub) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -14981,66 +15340,45 @@ pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uhsub.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")] - fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; +pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vhsubq_u32(a, b) } } -#[doc = "Load one single-element structure and replicate to all lanes of one register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t { - let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0))); - simd_shuffle!(x, x, [0, 0, 0, 0]) -} -#[doc = "Load one single-element structure and replicate to all lanes of one register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t { - let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0))); - simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0]) +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15050,20 +15388,24 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t { - transmute(f32x2::splat(*ptr)) +pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15073,20 +15415,19 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t { - transmute(u16x4::splat(*ptr)) +pub fn vget_high_s16(a: int16x8_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15096,20 +15437,23 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t { - transmute(u8x8::splat(*ptr)) +pub fn vget_high_s16(a: int16x8_t) -> int16x4_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15119,20 +15463,19 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t { - transmute(i16x4::splat(*ptr)) +pub fn vget_high_s32(a: int32x4_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15142,20 +15485,23 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t { - transmute(i32x2::splat(*ptr)) +pub fn vget_high_s32(a: int32x4_t) -> int32x2_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [2, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15165,20 +15511,19 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t { - transmute(i8x8::splat(*ptr)) +pub fn vget_high_s8(a: int8x16_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15188,20 +15533,24 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t { - transmute(u16x4::splat(*ptr)) +pub fn vget_high_s8(a: int8x16_t) -> int8x8_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15211,20 +15560,19 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t { - transmute(u32x2::splat(*ptr)) +pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15234,20 +15582,23 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t { - transmute(u8x8::splat(*ptr)) +pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15257,20 +15608,19 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { - transmute(f32x4::splat(*ptr)) +pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15280,20 +15630,23 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t { - transmute(u16x8::splat(*ptr)) +pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15303,20 +15656,19 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t { - transmute(u8x16::splat(*ptr)) +pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15326,20 +15678,24 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t { - transmute(i16x8::splat(*ptr)) +pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15349,20 +15705,19 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t { - transmute(i32x4::splat(*ptr)) +pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { transmute(u64x1::new(simd_extract!(a, 1))) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15372,20 +15727,22 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t { - transmute(i64x2::splat(*ptr)) +pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + transmute(u64x1::new(simd_extract!(a, 1))) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15395,20 +15752,19 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t { - transmute(i8x16::splat(*ptr)) +pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { + unsafe { int64x1_t([simd_extract!(a, 1)]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15418,20 +15774,22 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t { - transmute(u16x8::splat(*ptr)) +pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + int64x1_t([simd_extract!(a, 1)]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15441,20 +15799,19 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t { - transmute(u32x4::splat(*ptr)) +pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { uint64x1_t([simd_extract!(a, 1)]) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(ext) )] #[cfg_attr( not(target_arch = "arm"), @@ -15464,44 +15821,102 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t { - transmute(u64x2::splat(*ptr)) +pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + uint64x1_t([simd_extract!(a, 1)]) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vget_lane_f16(a: float16x4_t) -> f16 { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_extract!(a, LANE as u32) } +} +#[doc = "Duplicate vector element to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vget_lane_f16(a: float16x4_t) -> f16 { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + simd_extract!(a, LANE as u32) + } +} +#[doc = "Duplicate vector element to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) )] -pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { - transmute(u8x16::splat(*ptr)) +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_extract!(a, LANE as u32) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] +#[doc = "Duplicate vector element to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { + static_assert_uimm_bits!(LANE, 3); + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(a, LANE as u32) + } +} +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15510,30 +15925,18 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t { - let x: poly64x1_t; - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { - x = crate::core_arch::aarch64::vld1_p64(ptr); - } - #[cfg(target_arch = "arm")] - { - x = crate::core_arch::arm::vld1_p64(ptr); - }; - x +pub fn vget_lane_f32(v: float32x2_t) -> f32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15542,30 +15945,21 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t { - let x: int64x1_t; - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { - x = crate::core_arch::aarch64::vld1_s64(ptr); - } - #[cfg(target_arch = "arm")] - { - x = crate::core_arch::arm::vld1_s64(ptr); - }; - x +pub fn vget_lane_f32(v: float32x2_t) -> f32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: float32x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15574,407 +15968,84 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t { - let x: uint64x1_t; - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { - x = crate::core_arch::aarch64::vld1_u64(ptr); - } - #[cfg(target_arch = "arm")] - { - x = crate::core_arch::arm::vld1_u64(ptr); - }; - x -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { - transmute(vld1_v4f16( - ptr as *const i8, - crate::mem::align_of::() as i32, - )) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { - let ret_val: float16x4_t = transmute(vld1_v4f16( - ptr as *const i8, - crate::mem::align_of::() as i32, - )); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { - transmute(vld1q_v8f16( - ptr as *const i8, - crate::mem::align_of::() as i32, - )) +pub fn vget_lane_p16(v: poly16x4_t) -> p16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { - let ret_val: float16x8_t = transmute(vld1q_v8f16( - ptr as *const i8, - crate::mem::align_of::() as i32, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { - crate::ptr::read_unaligned(a.cast()) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_p16(v: poly16x4_t) -> p16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: poly16x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { - crate::ptr::read_unaligned(a.cast()) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_p8(v: poly8x8_t) -> p8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { - crate::ptr::read_unaligned(a.cast()) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t { - crate::ptr::read_unaligned(a.cast()) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v2f32::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] -pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v4f32::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v8i8::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v16i8::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v4i16::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v8i16::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v2i32::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] -pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v4i32::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v1i64::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] -pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v2i64::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v8i8::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v16i8::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1_v4i16::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v8i16::(ptr as *const i8)) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,aes")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] -pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - transmute(vld1q_v2i64::(ptr as *const i8)) +pub fn vget_lane_p8(v: poly8x8_t) -> p8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: poly8x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -15983,21 +16054,18 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_s16(v: int16x4_t) -> i16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16006,21 +16074,21 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_s16(v: int16x4_t) -> i16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: int16x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16029,21 +16097,18 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_s32(v: int32x2_t) -> i32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16052,21 +16117,21 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_s32(v: int32x2_t) -> i32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: int32x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16075,21 +16140,18 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_s8(v: int8x8_t) -> i8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16098,62 +16160,21 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { - crate::ptr::read_unaligned(a.cast()) -} -#[doc = "Load one single-element structure to one lane of one register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1_lane_f16(ptr: *const f16, src: float16x4_t) -> float16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) -} -#[doc = "Load one single-element structure to one lane of one register"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld1q_lane_f16(ptr: *const f16, src: float16x8_t) -> float16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_s8(v: int8x8_t) -> i8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: int8x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16162,23 +16183,18 @@ pub unsafe fn vld1q_lane_f16(ptr: *const f16, src: float16x8_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_f32(ptr: *const f32, src: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u16(v: uint16x4_t) -> u16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16187,23 +16203,21 @@ pub unsafe fn vld1_lane_f32(ptr: *const f32, src: float32x2_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_p16(ptr: *const p16, src: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u16(v: uint16x4_t) -> u16 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: uint16x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16212,23 +16226,18 @@ pub unsafe fn vld1_lane_p16(ptr: *const p16, src: poly16x4_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_p8(ptr: *const p8, src: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u32(v: uint32x2_t) -> u32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16237,23 +16246,21 @@ pub unsafe fn vld1_lane_p8(ptr: *const p8, src: poly8x8_t) -> p target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_s16(ptr: *const i16, src: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u32(v: uint32x2_t) -> u32 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: uint32x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16262,23 +16269,18 @@ pub unsafe fn vld1_lane_s16(ptr: *const i16, src: int16x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_s32(ptr: *const i32, src: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u8(v: uint8x8_t) -> u8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr, LANE = 0) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16287,23 +16289,21 @@ pub unsafe fn vld1_lane_s32(ptr: *const i32, src: int32x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { - static_assert!(LANE == 0); - simd_insert!(src, LANE as u32, *ptr) +pub fn vget_lane_u8(v: uint8x8_t) -> u8 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: uint8x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16312,23 +16312,18 @@ pub unsafe fn vld1_lane_s64(ptr: *const i64, src: int64x1_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_s8(ptr: *const i8, src: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16337,23 +16332,21 @@ pub unsafe fn vld1_lane_s8(ptr: *const i8, src: int8x8_t) -> in target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_u16(ptr: *const u16, src: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: float32x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16362,23 +16355,18 @@ pub unsafe fn vld1_lane_u16(ptr: *const u16, src: uint16x4_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_u32(ptr: *const u32, src: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr, LANE = 0) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16387,23 +16375,21 @@ pub unsafe fn vld1_lane_u32(ptr: *const u32, src: uint32x2_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { - static_assert!(LANE == 0); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: poly16x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16412,23 +16398,18 @@ pub unsafe fn vld1_lane_u64(ptr: *const u64, src: uint64x1_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_u8(ptr: *const u8, src: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16437,23 +16418,21 @@ pub unsafe fn vld1_lane_u8(ptr: *const u8, src: uint8x8_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_f32(ptr: *const f32, src: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: poly64x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16462,23 +16441,18 @@ pub unsafe fn vld1q_lane_f32(ptr: *const f32, src: float32x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_p16(ptr: *const p16, src: poly16x8_t) -> poly16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 15) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16487,23 +16461,22 @@ pub unsafe fn vld1q_lane_p16(ptr: *const p16, src: poly16x8_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_p8(ptr: *const p8, src: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { + let v: poly8x16_t = + simd_shuffle!(v, v, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16512,23 +16485,18 @@ pub unsafe fn vld1q_lane_p8(ptr: *const p8, src: poly8x16_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_s16(ptr: *const i16, src: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s16(v: int16x8_t) -> i16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16537,23 +16505,21 @@ pub unsafe fn vld1q_lane_s16(ptr: *const i16, src: int16x8_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_s32(ptr: *const i32, src: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s16(v: int16x8_t) -> i16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: int16x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16562,23 +16528,18 @@ pub unsafe fn vld1q_lane_s32(ptr: *const i32, src: int32x4_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s32(v: int32x4_t) -> i32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 15) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16587,23 +16548,21 @@ pub unsafe fn vld1q_lane_s64(ptr: *const i64, src: int64x2_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_s8(ptr: *const i8, src: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s32(v: int32x4_t) -> i32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: int32x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 7) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16612,23 +16571,18 @@ pub unsafe fn vld1q_lane_s8(ptr: *const i8, src: int8x16_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_u16(ptr: *const u16, src: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 3) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16637,23 +16591,21 @@ pub unsafe fn vld1q_lane_u16(ptr: *const u16, src: uint16x8_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_u32(ptr: *const u32, src: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { + static_assert_uimm_bits!(IMM5, 1); + unsafe { + let v: int64x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16662,23 +16614,18 @@ pub unsafe fn vld1q_lane_u32(ptr: *const u32, src: uint32x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_s8(v: int8x16_t) -> i8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 15) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16687,23 +16634,22 @@ pub unsafe fn vld1q_lane_u64(ptr: *const u64, src: uint64x2_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(src, LANE as u32, *ptr) -} -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] +pub fn vgetq_lane_s8(v: int8x16_t) -> i8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { + let v: int8x16_t = + simd_shuffle!(v, v, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } +} +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ldr, LANE = 0) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16712,23 +16658,18 @@ pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { - static_assert!(LANE == 0); - simd_insert!(src, LANE as u32, *ptr) +pub fn vgetq_lane_u16(v: uint16x8_t) -> u16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load one single-element structure to one lane of one register."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1, LANE = 1) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16737,40 +16678,21 @@ pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(src, LANE as u32, *ptr) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,aes")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { - let a: *const i8 = ptr as *const i8; - let b: i32 = crate::mem::align_of::() as i32; - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")] - fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t; +pub fn vgetq_lane_u16(v: uint16x8_t) -> u16 { + static_assert_uimm_bits!(IMM5, 3); + unsafe { + let v: uint16x8_t = simd_shuffle!(v, v, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) } - transmute(_vld1_v1i64(a, b)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16779,21 +16701,18 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16802,21 +16721,21 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: uint32x4_t = simd_shuffle!(v, v, [3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16825,21 +16744,18 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 1))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16848,21 +16764,21 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { + static_assert_uimm_bits!(IMM5, 2); + unsafe { + let v: uint64x2_t = simd_shuffle!(v, v, [1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16871,21 +16787,18 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 2))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -16894,125 +16807,21 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { - crate::ptr::read_unaligned(a.cast()) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1_v8i8::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] -pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1q_v16i8::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1_v4i16::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] -pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1q_v8i16::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1_v2i32::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] -pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1q_v4i32::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] -pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1_v1i64::(ptr as *const i8) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] -pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { - const ALIGN: i32 = crate::mem::align_of::() as i32; - vld1q_v2i64::(ptr as *const i8) +pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { + static_assert_uimm_bits!(IMM5, 4); + unsafe { + let v: uint8x16_t = + simd_shuffle!(v, v, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + simd_extract!(v, IMM5 as u32) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17021,21 +16830,17 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_p64(v: poly64x1_t) -> p64 { + static_assert!(IMM5 == 0); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17044,21 +16849,17 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_s64(v: int64x1_t) -> i64 { + static_assert!(IMM5 == 0); + unsafe { simd_extract!(v, IMM5 as u32) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Move vector element to general-purpose register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop, IMM5 = 0))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17067,21 +16868,17 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_lane_u64(v: uint64x1_t) -> u64 { + static_assert!(IMM5 == 0); + unsafe { simd_extract!(v, 0) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17090,21 +16887,16 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17113,21 +16905,20 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17136,21 +16927,16 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17159,21 +16945,20 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17182,21 +16967,16 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17205,21 +16985,21 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17228,21 +17008,16 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17251,21 +17026,20 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17274,21 +17048,16 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17297,21 +17066,20 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17320,21 +17088,16 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17343,21 +17106,21 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17366,21 +17129,16 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17389,21 +17147,20 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17412,21 +17169,16 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17435,21 +17187,20 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [0, 1]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17458,21 +17209,16 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17481,21 +17227,21 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17504,21 +17250,16 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { transmute(u64x1::new(simd_extract!(a, 0))) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17527,21 +17268,19 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { + let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); + transmute(u64x1::new(simd_extract!(a, 0))) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17550,21 +17289,16 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { + unsafe { int64x1_t([simd_extract!(a, 0)]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17573,21 +17307,19 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { + unsafe { + let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); + int64x1_t([simd_extract!(a, 0)]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17596,21 +17328,16 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { uint64x1_t([simd_extract!(a, 0)]) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) -)] +#[cfg_attr(test, assert_instr(nop))] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -17619,20 +17346,21 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { + let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); + uint64x1_t([simd_extract!(a, 0)]) + } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17642,20 +17370,26 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")] + fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vhadd_s8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17665,20 +17399,26 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")] + fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { _vhaddq_s8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17688,20 +17428,26 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")] + fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vhadd_s16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17711,20 +17457,26 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")] + fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { _vhaddq_s16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17734,20 +17486,26 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")] + fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vhadd_s32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17757,20 +17515,26 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")] + fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { _vhaddq_s32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17780,20 +17544,26 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")] + fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { _vhadd_u8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17803,20 +17573,26 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")] + fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + } + unsafe { _vhaddq_u8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17826,20 +17602,26 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")] + fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { _vhadd_u16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17849,20 +17631,26 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")] + fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + } + unsafe { _vhaddq_u16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17872,20 +17660,26 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")] + fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { _vhadd_u32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(uhadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -17895,20 +17689,26 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")] + fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { _vhaddq_u32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -17918,20 +17718,26 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")] + fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vhsub_s16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -17941,20 +17747,26 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")] + fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { _vhsubq_s16(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -17964,20 +17776,26 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")] + fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vhsub_s32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -17987,20 +17805,26 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")] + fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { _vhsubq_s32(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18010,20 +17834,26 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")] + fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vhsub_s8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(shsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18033,20 +17863,26 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")] + fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + unsafe { _vhsubq_s8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(uhsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18056,20 +17892,26 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")] + fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { _vhsub_u8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(uhsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -18079,20 +17921,182 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { - crate::ptr::read_unaligned(a.cast()) +pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")] + fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + } + unsafe { _vhsubq_u8(a, b) } } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")] + fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { _vhsub_u16(a, b) } +} +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")] + fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + } + unsafe { _vhsubq_u16(a, b) } +} +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")] + fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { _vhsub_u32(a, b) } +} +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")] + fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + } + unsafe { _vhsubq_u32(a, b) } +} +#[doc = "Load one single-element structure and replicate to all lanes of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) +)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t { + let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0))); + simd_shuffle!(x, x, [0, 0, 0, 0]) +} +#[doc = "Load one single-element structure and replicate to all lanes of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t { + let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0))); + simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0]) +} +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18102,20 +18106,20 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t { + transmute(f32x2::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18125,20 +18129,20 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t { + transmute(u16x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18148,20 +18152,20 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t { + transmute(u8x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18171,20 +18175,20 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t { + transmute(i16x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18194,20 +18198,20 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t { + transmute(i32x2::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18217,20 +18221,20 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t { + transmute(i8x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18240,20 +18244,20 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t { + transmute(u16x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18263,20 +18267,20 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t { + transmute(u32x2::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18286,20 +18290,20 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t { + transmute(u8x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18309,20 +18313,20 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { + transmute(f32x4::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18332,20 +18336,20 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t { + transmute(u16x8::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18355,20 +18359,20 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t { + transmute(u8x16::splat(*ptr)) } -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld) + assert_instr(ld1r) )] #[cfg_attr( not(target_arch = "arm"), @@ -18378,568 +18382,614 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { - crate::ptr::read_unaligned(a.cast()) +pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t { + transmute(i16x8::splat(*ptr)) } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v1i64(a: *const i8) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")] - fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t; - } - _vld1_v1i64(a, ALIGN) +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t { + transmute(i32x4::splat(*ptr)) } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v2f32(a: *const i8) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")] - fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t; - } - _vld1_v2f32(a, ALIGN) +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t { + transmute(i64x2::splat(*ptr)) } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v2i32(a: *const i8) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")] - fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t; - } - _vld1_v2i32(a, ALIGN) +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t { + transmute(i8x16::splat(*ptr)) } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v4i16(a: *const i8) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")] - fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t; - } - _vld1_v4i16(a, ALIGN) +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t { + transmute(u16x8::splat(*ptr)) } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1_v8i8(a: *const i8) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")] - fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t; - } - _vld1_v8i8(a, ALIGN) +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t { + transmute(u32x4::splat(*ptr)) } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v16i8(a: *const i8) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")] - fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t; - } - _vld1q_v16i8(a, ALIGN) +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t { + transmute(u64x2::splat(*ptr)) } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v2i64(a: *const i8) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")] - fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t; - } - _vld1q_v2i64(a, ALIGN) +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { + transmute(u8x16::splat(*ptr)) } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v4f32(a: *const i8) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")] - fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t; +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ldr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t { + let x: poly64x1_t; + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + { + x = crate::core_arch::aarch64::vld1_p64(ptr); } - _vld1q_v4f32(a, ALIGN) + #[cfg(target_arch = "arm")] + { + x = crate::core_arch::arm::vld1_p64(ptr); + }; + x } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v4i32(a: *const i8) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")] - fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t; +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ldr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t { + let x: int64x1_t; + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + { + x = crate::core_arch::aarch64::vld1_s64(ptr); } - _vld1q_v4i32(a, ALIGN) + #[cfg(target_arch = "arm")] + { + x = crate::core_arch::arm::vld1_s64(ptr); + }; + x } -#[inline(always)] -#[rustc_legacy_const_generics(1)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vld1q_v8i16(a: *const i8) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")] - fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t; +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ldr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t { + let x: uint64x1_t; + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + { + x = crate::core_arch::aarch64::vld1_u64(ptr); } - _vld1q_v8i16(a, ALIGN) + #[cfg(target_arch = "arm")] + { + x = crate::core_arch::arm::vld1_u64(ptr); + }; + x } -#[inline(always)] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")] - fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t; - } - _vld1_v4f16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { + transmute(vld1_v4f16( + ptr as *const i8, + crate::mem::align_of::() as i32, + )) } -#[inline(always)] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")] - fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t; - } - _vld1q_v8f16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { + transmute(vld1q_v8f16( + ptr as *const i8, + crate::mem::align_of::() as i32, + )) } -#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(ld) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) )] -pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t { - let x = vld1q_lane_p64::<0>(ptr, transmute(u64x2::splat(0))); - simd_shuffle!(x, x, [0, 0]) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0")] - fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t; - } - _vld2_dup_f16(a as _, 2) +pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0")] - fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t; - } - _vld2q_dup_f16(a as _, 2) +pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v4f16.p0" - )] - fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t; - } - _vld2_dup_f16(a as _) +pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v8f16.p0" - )] - fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t; - } - _vld2q_dup_f16(a as _) +pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")] - fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t; - } - _vld2_dup_f32(a as *const i8, 4) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v2f32::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")] - fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t; - } - _vld2q_dup_f32(a as *const i8, 4) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v4f32::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")] - fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t; - } - _vld2_dup_s8(a as *const i8, 1) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v8i8::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")] - fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t; - } - _vld2q_dup_s8(a as *const i8, 1) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v16i8::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")] - fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t; - } - _vld2_dup_s16(a as *const i8, 2) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v4i16::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")] - fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t; - } - _vld2q_dup_s16(a as *const i8, 2) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v8i16::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")] - fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t; - } - _vld2_dup_s32(a as *const i8, 4) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v2i32::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")] - fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t; - } - _vld2q_dup_s32(a as *const i8, 4) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v4i32::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v2f32.p0" - )] - fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t; - } - _vld2_dup_f32(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v1i64::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v4f32.p0" - )] - fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t; - } - _vld2q_dup_f32(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] +pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v2i64::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v8i8.p0" - )] - fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t; - } - _vld2_dup_s8(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v8i8::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v16i8.p0" - )] - fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t; - } - _vld2q_dup_s8(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v16i8::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v4i16.p0" - )] - fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t; - } - _vld2_dup_s16(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1_v4i16::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v8i16.p0" - )] - fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t; - } - _vld2q_dup_s16(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v8i16::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v2i32.p0" - )] - fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t; - } - _vld2_dup_s32(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,aes")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] +pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + transmute(vld1q_v2i64::(ptr as *const i8)) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v4i32.p0" - )] - fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t; - } - _vld2q_dup_s32(a as _) -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18949,55 +18999,20 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { - transmute(vld2_dup_s64(transmute(a))) -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")] - fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t; - } - _vld2_dup_s64(a as *const i8, 8) -} -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2r))] -pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2r.v1i64.p0" - )] - fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t; - } - _vld2_dup_s64(a as _) +pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19007,21 +19022,20 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { - transmute(vld2_dup_s64(transmute(a))) +pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19031,21 +19045,20 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { - transmute(vld2_dup_s8(transmute(a))) +pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19055,24 +19068,20 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { - let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19082,21 +19091,20 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { - transmute(vld2q_dup_s8(transmute(a))) +pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19106,60 +19114,61 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { - let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] +#[doc = "Load one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(ld1, LANE = 0) )] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1_lane_f16(ptr: *const f16, src: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) +} +#[doc = "Load one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 0) )] -pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { - transmute(vld2_dup_s16(transmute(a))) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld1q_lane_f16(ptr: *const f16, src: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 1) )] #[cfg_attr( not(target_arch = "arm"), @@ -19169,24 +19178,22 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { - let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_lane_f32(ptr: *const f32, src: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19196,21 +19203,22 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { - transmute(vld2q_dup_s16(transmute(a))) +pub unsafe fn vld1_lane_p16(ptr: *const p16, src: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19220,24 +19228,22 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { - let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_lane_p8(ptr: *const p8, src: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19247,21 +19253,22 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { - transmute(vld2_dup_s32(transmute(a))) +pub unsafe fn vld1_lane_s16(ptr: *const i16, src: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 1) )] #[cfg_attr( not(target_arch = "arm"), @@ -19271,24 +19278,22 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { - let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val +pub unsafe fn vld1_lane_s32(ptr: *const i32, src: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ldr, LANE = 0) )] #[cfg_attr( not(target_arch = "arm"), @@ -19298,21 +19303,22 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { - transmute(vld2q_dup_s32(transmute(a))) +pub unsafe fn vld1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { + static_assert!(LANE == 0); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19322,24 +19328,22 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { - let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_lane_s8(ptr: *const i8, src: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19349,21 +19353,22 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { - transmute(vld2_dup_s8(transmute(a))) +pub unsafe fn vld1_lane_u16(ptr: *const u16, src: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 1) )] #[cfg_attr( not(target_arch = "arm"), @@ -19373,24 +19378,22 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { - let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_lane_u32(ptr: *const u32, src: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ldr, LANE = 0) )] #[cfg_attr( not(target_arch = "arm"), @@ -19400,21 +19403,22 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { - transmute(vld2q_dup_s8(transmute(a))) +pub unsafe fn vld1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { + static_assert!(LANE == 0); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19424,36 +19428,22 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { - let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_lane_u8(ptr: *const u8, src: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 3) )] #[cfg_attr( not(target_arch = "arm"), @@ -19463,21 +19453,22 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { - transmute(vld2_dup_s16(transmute(a))) +pub unsafe fn vld1q_lane_f32(ptr: *const f32, src: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19487,24 +19478,22 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { - let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_lane_p16(ptr: *const p16, src: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 15) )] #[cfg_attr( not(target_arch = "arm"), @@ -19514,21 +19503,22 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { - transmute(vld2q_dup_s16(transmute(a))) +pub unsafe fn vld1q_lane_p8(ptr: *const p8, src: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2r) + assert_instr(ld1, LANE = 7) )] #[cfg_attr( not(target_arch = "arm"), @@ -19538,812 +19528,599 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { - let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_lane_s16(ptr: *const i16, src: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0")] - fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t; - } - _vld2_f16(a as _, 2) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_s32(ptr: *const i32, src: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0")] - fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t; - } - _vld2q_f16(a as _, 2) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld1, LANE = 15) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v4f16.p0" - )] - fn _vld2_f16(ptr: *const f16) -> float16x4x2_t; - } - _vld2_f16(a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_s8(ptr: *const i8, src: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld1, LANE = 7) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v8f16.p0" - )] - fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t; - } - _vld2q_f16(a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")] - fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t; - } - _vld2_f32(a as *const i8, 4) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_u16(ptr: *const u16, src: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")] - fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t; - } - _vld2q_f32(a as *const i8, 4) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_u32(ptr: *const u32, src: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")] - fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t; - } - _vld2_s8(a as *const i8, 1) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")] - fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t; - } - _vld2q_s8(a as *const i8, 1) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 15) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")] - fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t; - } - _vld2_s16(a as *const i8, 2) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ldr, LANE = 0) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { + static_assert!(LANE == 0); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] +#[doc = "Load one single-element structure to one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")] - fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t; - } - _vld2q_s16(a as *const i8, 2) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1, LANE = 1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(src, LANE as u32, *ptr) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] #[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,aes")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { + let a: *const i8 = ptr as *const i8; + let b: i32 = crate::mem::align_of::() as i32; unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")] - fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")] + fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t; } - _vld2_s32(a as *const i8, 4) + transmute(_vld1_v1i64(a, b)) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld2))] -pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")] - fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t; - } - _vld2q_s32(a as *const i8, 4) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v2f32.p0" - )] - fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t; - } - _vld2_f32(a as _) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v4f32.p0" - )] - fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t; - } - _vld2q_f32(a as _) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v8i8.p0" - )] - fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t; - } - _vld2_s8(a as _) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v16i8.p0" - )] - fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t; - } - _vld2q_s8(a as _) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v4i16.p0" - )] - fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t; - } - _vld2_s16(a as _) +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v8i16.p0" - )] - fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t; - } - _vld2q_s16(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1_v8i8::(ptr as *const i8) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v2i32.p0" - )] - fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t; - } - _vld2_s32(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))] +pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1q_v16i8::(ptr as *const i8) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v4i32.p0" - )] - fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t; - } - _vld2q_s32(a as _) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1_v4i16::(ptr as *const i8) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))] +pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1q_v8i16::(ptr as *const i8) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> float16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")] - fn _vld2_lane_f16( - ptr: *const f16, - a: float16x4_t, - b: float16x4_t, - n: i32, - size: i32, - ) -> float16x4x2_t; - } - _vld2_lane_f16(a as _, b.0, b.1, LANE, 2) +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1_v2i32::(ptr as *const i8) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))] +pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1q_v4i32::(ptr as *const i8) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) -> float16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")] - fn _vld2q_lane_f16( - ptr: *const f16, - a: float16x8_t, - b: float16x8_t, - n: i32, - size: i32, - ) -> float16x8x2_t; - } - _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2) +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1_v1i64::(ptr as *const i8) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] +pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { + const ALIGN: i32 = crate::mem::align_of::() as i32; + vld1q_v2i64::(ptr as *const i8) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> float16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0" - )] - fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16) - -> float16x4x2_t; - } - _vld2_lane_f16(b.0, b.1, LANE as i64, a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) -> float16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0" - )] - fn _vld2q_lane_f16( - a: float16x8_t, - b: float16x8_t, - n: i64, - ptr: *const f16, - ) -> float16x8x2_t; - } - _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0" - )] - fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t; - } - _vld2_lane_f32(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0" - )] - fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8) - -> float32x4x2_t; - } - _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0" - )] - fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t; - } - _vld2_lane_s8(b.0, b.1, LANE as i64, a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0" - )] - fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t; - } - _vld2_lane_s16(b.0, b.1, LANE as i64, a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0" - )] - fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t; - } - _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0" - )] - fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t; - } - _vld2_lane_s32(b.0, b.1, LANE as i64, a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0" - )] - fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t; - } - _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")] - fn _vld2_lane_f32( - ptr: *const i8, - a: float32x2_t, - b: float32x2_t, - n: i32, - size: i32, - ) -> float32x2x2_t; - } - _vld2_lane_f32(a as _, b.0, b.1, LANE, 4) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")] - fn _vld2q_lane_f32( - ptr: *const i8, - a: float32x4_t, - b: float32x4_t, - n: i32, - size: i32, - ) -> float32x4x2_t; - } - _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")] - fn _vld2q_lane_s16( - ptr: *const i8, - a: int16x8_t, - b: int16x8_t, - n: i32, - size: i32, - ) -> int16x8x2_t; - } - _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")] - fn _vld2q_lane_s32( - ptr: *const i8, - a: int32x4_t, - b: int32x4_t, - n: i32, - size: i32, - ) -> int32x4x2_t; - } - _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")] - fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32) - -> int8x8x2_t; - } - _vld2_lane_s8(a as _, b.0, b.1, LANE, 1) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")] - fn _vld2_lane_s16( - ptr: *const i8, - a: int16x4_t, - b: int16x4_t, - n: i32, - size: i32, - ) -> int16x4x2_t; - } - _vld2_lane_s16(a as _, b.0, b.1, LANE, 2) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")] - fn _vld2_lane_s32( - ptr: *const i8, - a: int32x2_t, - b: int32x2_t, - n: i32, - size: i32, - ) -> int32x2x2_t; - } - _vld2_lane_s32(a as _, b.0, b.1, LANE, 4) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -20352,23 +20129,21 @@ pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> i target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -20377,23 +20152,21 @@ pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uin target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld2_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -20402,23 +20175,21 @@ pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -20427,23 +20198,21 @@ pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld2_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -20452,23 +20221,21 @@ pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld2q_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -20477,23 +20244,21 @@ pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -20502,23 +20267,21 @@ pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> pol target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld2_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2, LANE = 0) + assert_instr(ld) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -20527,21 +20290,20 @@ pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20551,55 +20313,20 @@ pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { - transmute(vld2_s64(transmute(a))) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")] - fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t; - } - _vld2_s64(a as *const i8, 8) -} -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v1i64.p0" - )] - fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t; - } - _vld2_s64(a as _) +pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20609,20 +20336,20 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { - transmute(vld2_s64(transmute(a))) +pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20632,20 +20359,20 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { - transmute(vld2_s8(transmute(a))) +pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20655,20 +20382,20 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { - transmute(vld2q_s8(transmute(a))) +pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20678,20 +20405,20 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { - transmute(vld2_s16(transmute(a))) +pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20701,20 +20428,20 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { - transmute(vld2q_s16(transmute(a))) +pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20724,20 +20451,20 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { - transmute(vld2_s32(transmute(a))) +pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20747,20 +20474,20 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { - transmute(vld2q_s32(transmute(a))) +pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20770,20 +20497,20 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { - transmute(vld2_s8(transmute(a))) +pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20793,20 +20520,20 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { - transmute(vld2q_s8(transmute(a))) +pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20816,20 +20543,20 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { - transmute(vld2_s16(transmute(a))) +pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -20839,405 +20566,20 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { - transmute(vld2q_s16(transmute(a))) -} -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0")] - fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t; - } - _vld3_dup_f16(a as _, 2) +pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0")] - fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t; - } - _vld3q_dup_f16(a as _, 2) -} -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v4f16.p0" - )] - fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t; - } - _vld3_dup_f16(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v8f16.p0" - )] - fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t; - } - _vld3q_dup_f16(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v2f32.p0" - )] - fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t; - } - _vld3_dup_f32(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v4f32.p0" - )] - fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t; - } - _vld3q_dup_f32(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v8i8.p0" - )] - fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t; - } - _vld3_dup_s8(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v16i8.p0" - )] - fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t; - } - _vld3q_dup_s8(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v4i16.p0" - )] - fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t; - } - _vld3_dup_s16(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v8i16.p0" - )] - fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t; - } - _vld3q_dup_s16(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v2i32.p0" - )] - fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t; - } - _vld3_dup_s32(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v4i32.p0" - )] - fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t; - } - _vld3q_dup_s32(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3r))] -pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3r.v1i64.p0" - )] - fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t; - } - _vld3_dup_s64(a as _) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")] - fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t; - } - _vld3_dup_f32(a as *const i8, 4) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")] - fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t; - } - _vld3q_dup_f32(a as *const i8, 4) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")] - fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t; - } - _vld3_dup_s8(a as *const i8, 1) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")] - fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t; - } - _vld3q_dup_s8(a as *const i8, 1) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")] - fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t; - } - _vld3_dup_s16(a as *const i8, 2) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")] - fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t; - } - _vld3q_dup_s16(a as *const i8, 2) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")] - fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t; - } - _vld3_dup_s32(a as *const i8, 4) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")] - fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t; - } - _vld3q_dup_s32(a as *const i8, 4) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21247,36 +20589,20 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { - transmute(vld3_dup_s64(transmute(a))) -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")] - fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t; - } - _vld3_dup_s64(a as *const i8, 8) +pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21286,21 +20612,20 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { - transmute(vld3_dup_s64(transmute(a))) +pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21310,21 +20635,20 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { - transmute(vld3_dup_s8(transmute(a))) +pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21334,25 +20658,20 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { - let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21362,21 +20681,20 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { - transmute(vld3q_dup_s8(transmute(a))) +pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21386,43 +20704,20 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { - let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21432,21 +20727,20 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { - transmute(vld3_dup_s16(transmute(a))) +pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21456,25 +20750,20 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { - let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] +pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21484,21 +20773,20 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { - transmute(vld3q_dup_s16(transmute(a))) +pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21508,25 +20796,20 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { - let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21536,21 +20819,20 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { - transmute(vld3_dup_s32(transmute(a))) +pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21560,25 +20842,20 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { - let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val +pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21588,21 +20865,20 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { - transmute(vld3q_dup_s32(transmute(a))) +pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21612,25 +20888,20 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { - let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21640,21 +20911,20 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { - transmute(vld3_dup_s8(transmute(a))) +pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21664,25 +20934,20 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { - let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21692,21 +20957,20 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { - transmute(vld3q_dup_s8(transmute(a))) +pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21716,43 +20980,20 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { - let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21762,21 +21003,20 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { - transmute(vld3_dup_s16(transmute(a))) +pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21786,25 +21026,20 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { - let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21814,21 +21049,20 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { - transmute(vld3q_dup_s16(transmute(a))) +pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3r) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -21838,804 +21072,891 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { - let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0")] - fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t; - } - _vld3_f16(a as _, 2) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0")] - fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t; - } - _vld3q_f16(a as _, 2) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { - crate::core_arch::macros::deinterleaving_load!(f16, 4, 3, a) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld) )] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { - crate::core_arch::macros::deinterleaving_load!(f16, 8, 3, a) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { - crate::core_arch::macros::deinterleaving_load!(f32, 2, 3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { - crate::core_arch::macros::deinterleaving_load!(f32, 4, 3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { - crate::core_arch::macros::deinterleaving_load!(i8, 8, 3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { - crate::core_arch::macros::deinterleaving_load!(i8, 16, 3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { - crate::core_arch::macros::deinterleaving_load!(i16, 4, 3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { - crate::core_arch::macros::deinterleaving_load!(i16, 8, 3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { - crate::core_arch::macros::deinterleaving_load!(i32, 2, 3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { - crate::core_arch::macros::deinterleaving_load!(i32, 4, 3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")] - fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t; - } - _vld3_f32(a as *const i8, 4) +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { + crate::ptr::read_unaligned(a.cast()) +} +#[inline] +#[rustc_legacy_const_generics(1)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { +unsafe fn vld1_v1i64(a: *const i8) -> int64x1_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")] - fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")] + fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t; } - _vld3q_f32(a as *const i8, 4) + _vld1_v1i64(a, ALIGN) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[rustc_legacy_const_generics(1)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { +unsafe fn vld1_v2f32(a: *const i8) -> float32x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")] - fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")] + fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t; } - _vld3_s8(a as *const i8, 1) + _vld1_v2f32(a, ALIGN) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[rustc_legacy_const_generics(1)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { +unsafe fn vld1_v2i32(a: *const i8) -> int32x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")] - fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")] + fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t; } - _vld3q_s8(a as *const i8, 1) + _vld1_v2i32(a, ALIGN) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[rustc_legacy_const_generics(1)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { +unsafe fn vld1_v4i16(a: *const i8) -> int16x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")] - fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")] + fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t; } - _vld3_s16(a as *const i8, 2) + _vld1_v4i16(a, ALIGN) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[rustc_legacy_const_generics(1)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { +unsafe fn vld1_v8i8(a: *const i8) -> int8x8_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")] - fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")] + fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t; } - _vld3q_s16(a as *const i8, 2) + _vld1_v8i8(a, ALIGN) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[rustc_legacy_const_generics(1)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { +unsafe fn vld1q_v16i8(a: *const i8) -> int8x16_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")] - fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")] + fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t; } - _vld3_s32(a as *const i8, 4) + _vld1q_v16i8(a, ALIGN) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[rustc_legacy_const_generics(1)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld3))] -pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { +unsafe fn vld1q_v2i64(a: *const i8) -> int64x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")] - fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")] + fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t; } - _vld3q_s32(a as *const i8, 4) + _vld1q_v2i64(a, ALIGN) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1q_v4f32(a: *const i8) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")] + fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t; + } + _vld1q_v4f32(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1q_v4i32(a: *const i8) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")] + fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t; + } + _vld1q_v4i32(a, ALIGN) +} +#[inline] +#[rustc_legacy_const_generics(1)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", ALIGN = 0))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +unsafe fn vld1q_v8i16(a: *const i8) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")] + fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t; + } + _vld1q_v8i16(a, ALIGN) +} +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg(not(target_arch = "arm64ec"))] +unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")] + fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t; + } + _vld1_v4f16(a, b) +} +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg(not(target_arch = "arm64ec"))] +unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")] + fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t; + } + _vld1q_v8f16(a, b) +} +#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t { + let x = vld1q_lane_p64::<0>(ptr, transmute(u64x2::splat(0))); + simd_shuffle!(x, x, [0, 0]) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> float16x4x3_t { - static_assert_uimm_bits!(LANE, 2); +pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")] - fn _vld3_lane_f16( - ptr: *const f16, - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - n: i32, - size: i32, - ) -> float16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0")] + fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t; } - _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2) + _vld2_dup_f16(a as _, 2) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) -> float16x8x3_t { - static_assert_uimm_bits!(LANE, 3); +pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")] - fn _vld3q_lane_f16( - ptr: *const f16, - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - n: i32, - size: i32, - ) -> float16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0")] + fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t; } - _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2) + _vld2q_dup_f16(a as _, 2) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld2r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> float16x4x3_t { - static_assert_uimm_bits!(LANE, 2); +pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0" + link_name = "llvm.aarch64.neon.ld2r.v4f16.p0" )] - fn _vld3_lane_f16( - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - n: i64, - ptr: *const f16, - ) -> float16x4x3_t; + fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t; } - _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _) + _vld2_dup_f16(a as _) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld2r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) -> float16x8x3_t { - static_assert_uimm_bits!(LANE, 3); +pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0" + link_name = "llvm.aarch64.neon.ld2r.v8f16.p0" )] - fn _vld3q_lane_f16( - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - n: i64, - ptr: *const f16, - ) -> float16x8x3_t; + fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t; } - _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _) + _vld2q_dup_f16(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { - static_assert_uimm_bits!(LANE, 1); +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0" - )] - fn _vld3_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - n: i64, - ptr: *const i8, - ) -> float32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")] + fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t; } - _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) + _vld2_dup_f32(a as *const i8, 4) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { - static_assert_uimm_bits!(LANE, 2); +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0" - )] - fn _vld3q_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - n: i64, - ptr: *const i8, - ) -> float32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")] + fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t; } - _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) + _vld2q_dup_f32(a as *const i8, 4) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { - static_assert_uimm_bits!(LANE, 1); +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")] - fn _vld3_lane_f32( - ptr: *const i8, - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - n: i32, - size: i32, - ) -> float32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")] + fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t; } - _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) + _vld2_dup_s8(a as *const i8, 1) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { - static_assert_uimm_bits!(LANE, 3); +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0" - )] - fn _vld3_lane_s8( - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - n: i64, - ptr: *const i8, - ) -> int8x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")] + fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t; } - _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) + _vld2q_dup_s8(a as *const i8, 1) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { - static_assert_uimm_bits!(LANE, 2); +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0" - )] - fn _vld3_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - n: i64, - ptr: *const i8, - ) -> int16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")] + fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t; } - _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) + _vld2_dup_s16(a as *const i8, 2) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { - static_assert_uimm_bits!(LANE, 4); +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0" - )] - fn _vld3q_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - n: i64, - ptr: *const i8, - ) -> int16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")] + fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t; } - _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) + _vld2q_dup_s16(a as *const i8, 2) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")] + fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t; + } + _vld2_dup_s32(a as *const i8, 4) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")] + fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t; + } + _vld2q_dup_s32(a as *const i8, 4) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { - static_assert_uimm_bits!(LANE, 1); +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0" + link_name = "llvm.aarch64.neon.ld2r.v2f32.p0" )] - fn _vld3_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - n: i64, - ptr: *const i8, - ) -> int32x2x3_t; + fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t; } - _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) + _vld2_dup_f32(a as _) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { - static_assert_uimm_bits!(LANE, 2); +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0" + link_name = "llvm.aarch64.neon.ld2r.v4f32.p0" )] - fn _vld3q_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - n: i64, - ptr: *const i8, - ) -> int32x4x3_t; + fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t; } - _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) + _vld2q_dup_f32(a as _) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { - static_assert_uimm_bits!(LANE, 3); +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")] - fn _vld3_lane_s8( - ptr: *const i8, - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - n: i32, - size: i32, - ) -> int8x8x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v8i8.p0" + )] + fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t; } - _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1) + _vld2_dup_s8(a as _) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { - static_assert_uimm_bits!(LANE, 2); +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")] - fn _vld3_lane_s16( - ptr: *const i8, - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - n: i32, - size: i32, - ) -> int16x4x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v16i8.p0" + )] + fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t; } - _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) + _vld2q_dup_s8(a as _) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { - static_assert_uimm_bits!(LANE, 3); +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")] - fn _vld3q_lane_s16( - ptr: *const i8, - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - n: i32, - size: i32, - ) -> int16x8x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4i16.p0" + )] + fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t; } - _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) + _vld2_dup_s16(a as _) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { - static_assert_uimm_bits!(LANE, 1); +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")] - fn _vld3_lane_s32( - ptr: *const i8, - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - n: i32, - size: i32, - ) -> int32x2x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v8i16.p0" + )] + fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t; } - _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) + _vld2q_dup_s16(a as _) } -#[doc = "Load multiple 3-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { - static_assert_uimm_bits!(LANE, 2); +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")] - fn _vld3q_lane_s32( - ptr: *const i8, - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - n: i32, - size: i32, - ) -> int32x4x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v2i32.p0" + )] + fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t; } - _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) + _vld2_dup_s32(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3_lane_s8::(transmute(a), transmute(b))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4i32.p0" + )] + fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t; + } + _vld2q_dup_s32(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld2r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22644,48 +21965,56 @@ pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uin target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { + transmute(vld2_dup_s64(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")] + fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t; + } + _vld2_dup_s64(a as *const i8, 8) +} +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3q_lane_s16::(transmute(a), transmute(b))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v1i64.p0" + )] + fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t; + } + _vld2_dup_s64(a as _) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld2r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22694,23 +22023,21 @@ pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld3_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { + transmute(vld2_dup_s64(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld2r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22719,23 +22046,21 @@ pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3q_lane_s32::(transmute(a), transmute(b))) +pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { + transmute(vld2_dup_s8(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld2r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22744,23 +22069,21 @@ pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { + transmute(vld2q_dup_s8(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld2r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22769,23 +22092,21 @@ pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> pol target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { + transmute(vld2_dup_s16(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3, LANE = 0) + assert_instr(ld2r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -22794,21 +22115,20 @@ pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3q_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { + transmute(vld2q_dup_s16(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22818,48 +22138,20 @@ pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { - transmute(vld3_s64(transmute(a))) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { - crate::ptr::read_unaligned(a.cast()) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")] - fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t; - } - _vld3_s64(a as *const i8, 8) +pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { + transmute(vld2_dup_s32(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22869,20 +22161,20 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { - transmute(vld3_s64(transmute(a))) +pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { + transmute(vld2q_dup_s32(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22892,20 +22184,20 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { - transmute(vld3_s8(transmute(a))) +pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { + transmute(vld2_dup_s8(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22915,20 +22207,20 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { - transmute(vld3q_s8(transmute(a))) +pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { + transmute(vld2q_dup_s8(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22938,20 +22230,20 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { - transmute(vld3_s16(transmute(a))) +pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { + transmute(vld2_dup_s16(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) + assert_instr(ld2r) )] #[cfg_attr( not(target_arch = "arm"), @@ -22961,604 +22253,809 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { - transmute(vld3q_s16(transmute(a))) +pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { + transmute(vld2q_dup_s16(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { - transmute(vld3_s32(transmute(a))) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { - transmute(vld3q_s32(transmute(a))) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { - transmute(vld3_s8(transmute(a))) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { - transmute(vld3q_s8(transmute(a))) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { - transmute(vld3_s16(transmute(a))) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { - transmute(vld3q_s16(transmute(a))) -} -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")] - fn _vld3q_lane_f32( - ptr: *const i8, - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - n: i32, - size: i32, - ) -> float32x4x3_t; - } - _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) -} -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { +pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0")] - fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0")] + fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t; } - _vld4_dup_f16(a as _, 2) + _vld2_f16(a as _, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { +pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0")] - fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0")] + fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t; } - _vld4q_dup_f16(a as _, 2) + _vld2q_f16(a as _, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { +pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v4f16.p0" + link_name = "llvm.aarch64.neon.ld2.v4f16.p0" )] - fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t; + fn _vld2_f16(ptr: *const f16) -> float16x4x2_t; } - _vld4_dup_f16(a as _) + _vld2_f16(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { +pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v8f16.p0" + link_name = "llvm.aarch64.neon.ld2.v8f16.p0" )] - fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t; + fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t; } - _vld4q_dup_f16(a as _) + _vld2q_f16(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")] - fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")] + fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t; } - _vld4_dup_f32(a as *const i8, 4) + _vld2_f32(a as *const i8, 4) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")] - fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")] + fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t; } - _vld4q_dup_f32(a as *const i8, 4) + _vld2q_f32(a as *const i8, 4) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")] - fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")] + fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t; } - _vld4_dup_s8(a as *const i8, 1) + _vld2_s8(a as *const i8, 1) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")] - fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")] + fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t; } - _vld4q_dup_s8(a as *const i8, 1) + _vld2q_s8(a as *const i8, 1) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")] - fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")] + fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t; } - _vld4_dup_s16(a as *const i8, 2) + _vld2_s16(a as *const i8, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")] - fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")] + fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t; } - _vld4q_dup_s16(a as *const i8, 2) + _vld2q_s16(a as *const i8, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")] - fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")] + fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t; } - _vld4_dup_s32(a as *const i8, 4) + _vld2_s32(a as *const i8, 4) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")] - fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")] + fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t; } - _vld4q_dup_s32(a as *const i8, 4) + _vld2q_s32(a as *const i8, 4) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v2f32.p0.p0" + link_name = "llvm.aarch64.neon.ld2.v2f32.p0" )] - fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t; + fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t; } - _vld4_dup_f32(a as _) + _vld2_f32(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v4f32.p0.p0" + link_name = "llvm.aarch64.neon.ld2.v4f32.p0" )] - fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t; + fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t; } - _vld4q_dup_f32(a as _) + _vld2q_f32(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v8i8.p0.p0" + link_name = "llvm.aarch64.neon.ld2.v8i8.p0" )] - fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t; + fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t; } - _vld4_dup_s8(a as _) + _vld2_s8(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v16i8.p0.p0" + link_name = "llvm.aarch64.neon.ld2.v16i8.p0" )] - fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t; + fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t; } - _vld4q_dup_s8(a as _) + _vld2q_s8(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v4i16.p0.p0" + link_name = "llvm.aarch64.neon.ld2.v4i16.p0" )] - fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t; + fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t; } - _vld4_dup_s16(a as _) + _vld2_s16(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v8i16.p0.p0" + link_name = "llvm.aarch64.neon.ld2.v8i16.p0" )] - fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t; + fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t; } - _vld4q_dup_s16(a as _) + _vld2q_s16(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v2i32.p0.p0" + link_name = "llvm.aarch64.neon.ld2.v2i32.p0" )] - fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t; + fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t; } - _vld4_dup_s32(a as _) + _vld2_s32(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v4i32.p0.p0" + link_name = "llvm.aarch64.neon.ld2.v4i32.p0" )] - fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t; + fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t; } - _vld4q_dup_s32(a as _) + _vld2q_s32(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> float16x4x2_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4r.v1i64.p0.p0" - )] - fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")] + fn _vld2_lane_f16( + ptr: *const f16, + a: float16x4_t, + b: float16x4_t, + n: i32, + size: i32, + ) -> float16x4x2_t; } - _vld4_dup_s64(a as _) + _vld2_lane_f16(a as _, b.0, b.1, LANE, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { - transmute(vld4_dup_s64(transmute(a))) -} -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] -#[doc = "## Safety"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) -> float16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")] + fn _vld2q_lane_f16( + ptr: *const f16, + a: float16x8_t, + b: float16x8_t, + n: i32, + size: i32, + ) -> float16x8x2_t; + } + _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> float16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0" + )] + fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16) + -> float16x4x2_t; + } + _vld2_lane_f16(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) -> float16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0" + )] + fn _vld2q_lane_f16( + a: float16x8_t, + b: float16x8_t, + n: i64, + ptr: *const f16, + ) -> float16x8x2_t; + } + _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0" + )] + fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t; + } + _vld2_lane_f32(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0" + )] + fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8) + -> float32x4x2_t; + } + _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0" + )] + fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t; + } + _vld2_lane_s8(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0" + )] + fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t; + } + _vld2_lane_s16(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0" + )] + fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t; + } + _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0" + )] + fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t; + } + _vld2_lane_s32(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0" + )] + fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t; + } + _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] +#[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")] + fn _vld2_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x2_t; + } + _vld2_lane_f32(a as _, b.0, b.1, LANE, 4) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { +pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")] - fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")] + fn _vld2q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x2_t; } - _vld4_dup_s64(a as *const i8, 8) + _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")] + fn _vld2q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x2_t; + } + _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")] + fn _vld2q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x2_t; + } + _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")] + fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32) + -> int8x8x2_t; + } + _vld2_lane_s8(a as _, b.0, b.1, LANE, 1) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")] + fn _vld2_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x2_t; + } + _vld2_lane_s16(a as _, b.0, b.1, LANE, 2) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")] + fn _vld2_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x2_t; + } + _vld2_lane_s32(a as _, b.0, b.1, LANE, 4) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23567,22 +23064,23 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { - transmute(vld4_dup_s64(transmute(a))) +pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23591,22 +23089,23 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { - transmute(vld4_dup_s8(transmute(a))) +pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23615,27 +23114,23 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { - let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23644,22 +23139,23 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { - transmute(vld4q_dup_s8(transmute(a))) +pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld2_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23668,51 +23164,23 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { - let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2q_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23721,22 +23189,23 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { - transmute(vld4_dup_s16(transmute(a))) +pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23745,27 +23214,23 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { - let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -23774,21 +23239,21 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { - transmute(vld4q_dup_s16(transmute(a))) +pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -23798,50 +23263,55 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { - let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { + transmute(vld2_s64(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")] + fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t; + } + _vld2_s64(a as *const i8, 8) +} +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { - transmute(vld4_dup_s32(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v1i64.p0" + )] + fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t; + } + _vld2_s64(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -23851,26 +23321,20 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { - let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val +pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { + transmute(vld2_s64(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23880,21 +23344,20 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { - transmute(vld4q_dup_s32(transmute(a))) +pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { + transmute(vld2_s8(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23904,26 +23367,20 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { - let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { + transmute(vld2q_s8(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23933,21 +23390,20 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { - transmute(vld4_dup_s8(transmute(a))) +pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { + transmute(vld2_s16(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23957,26 +23413,20 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { - let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { + transmute(vld2q_s16(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -23986,21 +23436,20 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { - transmute(vld4q_dup_s8(transmute(a))) +pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { + transmute(vld2_s32(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -24010,50 +23459,20 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { - let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { + transmute(vld2q_s32(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -24063,21 +23482,20 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { - transmute(vld4_dup_s16(transmute(a))) +pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { + transmute(vld2_s8(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -24087,26 +23505,20 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { - let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { + transmute(vld2q_s8(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -24116,21 +23528,20 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { - transmute(vld4q_dup_s16(transmute(a))) +pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { + transmute(vld2_s16(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4r) + assert_instr(ld2) )] #[cfg_attr( not(target_arch = "arm"), @@ -24140,817 +23551,652 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { - let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { + transmute(vld2q_s16(transmute(a))) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { +pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0")] - fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0")] + fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t; } - _vld4_f16(a as _, 2) + _vld3_dup_f16(a as _, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { +pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0")] - fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0")] + fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t; } - _vld4q_f16(a as _, 2) + _vld3q_dup_f16(a as _, 2) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld3r) )] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { - crate::core_arch::macros::deinterleaving_load!(f16, 4, 4, a) +pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v4f16.p0" + )] + fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t; + } + _vld3_dup_f16(a as _) } -#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld3r) )] -#[target_feature(enable = "neon,fp16")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { - crate::core_arch::macros::deinterleaving_load!(f16, 8, 4, a) +pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v8f16.p0" + )] + fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t; + } + _vld3q_dup_f16(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { - crate::core_arch::macros::deinterleaving_load!(f32, 2, 4, a) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v2f32.p0" + )] + fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t; + } + _vld3_dup_f32(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { - crate::core_arch::macros::deinterleaving_load!(f32, 4, 4, a) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v4f32.p0" + )] + fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t; + } + _vld3q_dup_f32(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { - crate::core_arch::macros::deinterleaving_load!(i8, 8, 4, a) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v8i8.p0" + )] + fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t; + } + _vld3_dup_s8(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { - crate::core_arch::macros::deinterleaving_load!(i8, 16, 4, a) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v16i8.p0" + )] + fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t; + } + _vld3q_dup_s8(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { - crate::core_arch::macros::deinterleaving_load!(i16, 4, 4, a) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v4i16.p0" + )] + fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t; + } + _vld3_dup_s16(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { - crate::core_arch::macros::deinterleaving_load!(i16, 8, 4, a) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v8i16.p0" + )] + fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t; + } + _vld3q_dup_s16(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { - crate::core_arch::macros::deinterleaving_load!(i32, 2, 4, a) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v2i32.p0" + )] + fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t; + } + _vld3_dup_s32(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { - crate::core_arch::macros::deinterleaving_load!(i32, 4, 4, a) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v4i32.p0" + )] + fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t; + } + _vld3q_dup_s32(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")] - fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v1i64.p0" + )] + fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t; } - _vld4_f32(a as *const i8, 4) + _vld3_dup_s64(a as _) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")] - fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")] + fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t; } - _vld4q_f32(a as *const i8, 4) + _vld3_dup_f32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")] - fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")] + fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t; } - _vld4_s8(a as *const i8, 1) + _vld3q_dup_f32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")] - fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")] + fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t; } - _vld4q_s8(a as *const i8, 1) + _vld3_dup_s8(a as *const i8, 1) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")] - fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")] + fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t; } - _vld4_s16(a as *const i8, 2) + _vld3q_dup_s8(a as *const i8, 1) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")] - fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")] + fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t; } - _vld4q_s16(a as *const i8, 2) + _vld3_dup_s16(a as *const i8, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")] - fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")] + fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t; } - _vld4_s32(a as *const i8, 4) + _vld3q_dup_s16(a as *const i8, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vld4))] -pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")] - fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")] + fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t; } - _vld4q_s32(a as *const i8, 4) + _vld3_dup_s32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> float16x4x4_t { - static_assert_uimm_bits!(LANE, 2); +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")] - fn _vld4_lane_f16( - ptr: *const f16, - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - d: float16x4_t, - n: i32, - size: i32, - ) -> float16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")] + fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t; } - _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vld3q_dup_s32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { + transmute(vld3_dup_s64(transmute(a))) +} +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg(target_arch = "arm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) -> float16x8x4_t { - static_assert_uimm_bits!(LANE, 3); +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")] - fn _vld4q_lane_f16( - ptr: *const f16, - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - d: float16x8_t, - n: i32, - size: i32, - ) -> float16x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")] + fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t; } - _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vld3_dup_s64(a as *const i8, 8) } -#[doc = "Load multiple 4-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(not(target_arch = "arm"))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> float16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0" - )] - fn _vld4_lane_f16( - a: float16x4_t, - b: float16x4_t, - c: float16x4_t, - d: float16x4_t, - n: i64, - ptr: *const f16, - ) -> float16x4x4_t; - } - _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { + transmute(vld3_dup_s64(transmute(a))) } -#[doc = "Load multiple 4-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(not(target_arch = "arm"))] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) -> float16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0" - )] - fn _vld4q_lane_f16( - a: float16x8_t, - b: float16x8_t, - c: float16x8_t, - d: float16x8_t, - n: i64, - ptr: *const f16, - ) -> float16x8x4_t; - } - _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { + transmute(vld3_dup_s8(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0" - )] - fn _vld4_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - d: float32x2_t, - n: i64, - ptr: *const i8, - ) -> float32x2x4_t; - } - _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { + transmute(vld3q_dup_s8(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0" - )] - fn _vld4q_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - d: float32x4_t, - n: i64, - ptr: *const i8, - ) -> float32x4x4_t; - } - _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { + transmute(vld3_dup_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0" - )] - fn _vld4_lane_s8( - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - d: int8x8_t, - n: i64, - ptr: *const i8, - ) -> int8x8x4_t; - } - _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { + transmute(vld3q_dup_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0" - )] - fn _vld4_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - d: int16x4_t, - n: i64, - ptr: *const i8, - ) -> int16x4x4_t; - } - _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { + transmute(vld3_dup_s32(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0" - )] - fn _vld4q_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - d: int16x8_t, - n: i64, - ptr: *const i8, - ) -> int16x8x4_t; - } - _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { + transmute(vld3q_dup_s32(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0" - )] - fn _vld4_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - d: int32x2_t, - n: i64, - ptr: *const i8, - ) -> int32x2x4_t; - } - _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { + transmute(vld3_dup_s8(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0" - )] - fn _vld4q_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - d: int32x4_t, - n: i64, - ptr: *const i8, - ) -> int32x4x4_t; - } - _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { + transmute(vld3q_dup_s8(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")] - fn _vld4_lane_f32( - ptr: *const i8, - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - d: float32x2_t, - n: i32, - size: i32, - ) -> float32x2x4_t; - } - _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")] - fn _vld4q_lane_f32( - ptr: *const i8, - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - d: float32x4_t, - n: i32, - size: i32, - ) -> float32x4x4_t; - } - _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")] - fn _vld4_lane_s8( - ptr: *const i8, - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - d: int8x8_t, - n: i32, - size: i32, - ) -> int8x8x4_t; - } - _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")] - fn _vld4_lane_s16( - ptr: *const i8, - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - d: int16x4_t, - n: i32, - size: i32, - ) -> int16x4x4_t; - } - _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")] - fn _vld4q_lane_s16( - ptr: *const i8, - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - d: int16x8_t, - n: i32, - size: i32, - ) -> int16x8x4_t; - } - _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")] - fn _vld4_lane_s32( - ptr: *const i8, - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - d: int32x2_t, - n: i32, - size: i32, - ) -> int32x2x4_t; - } - _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")] - fn _vld4q_lane_s32( - ptr: *const i8, - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - d: int32x4_t, - n: i32, - size: i32, - ) -> int32x4x4_t; - } - _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24959,23 +24205,21 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { + transmute(vld3_dup_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) + assert_instr(ld3r) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -24984,663 +24228,775 @@ pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uin target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4_lane_s16::(transmute(a), transmute(b))) +pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { + transmute(vld3q_dup_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4q_lane_s16::(transmute(a), transmute(b))) +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0")] + fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t; + } + _vld3_f16(a as _, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld4_lane_s32::(transmute(a), transmute(b))) +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0")] + fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t; + } + _vld3q_f16(a as _, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld3) )] -pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4q_lane_s32::(transmute(a), transmute(b))) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { + crate::core_arch::macros::deinterleaving_load!(f16, 4, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] +#[doc = "Load single 3-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld3) )] -pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4_lane_s8::(transmute(a), transmute(b))) +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { + crate::core_arch::macros::deinterleaving_load!(f16, 8, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4_lane_s16::(transmute(a), transmute(b))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { + crate::core_arch::macros::deinterleaving_load!(f32, 2, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4q_lane_s16::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { - transmute(vld4_s64(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { + crate::core_arch::macros::deinterleaving_load!(f32, 4, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - crate::ptr::read_unaligned(a.cast()) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { + crate::core_arch::macros::deinterleaving_load!(i8, 8, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")] - fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t; - } - _vld4_s64(a as *const i8, 8) +#[inline] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { + crate::core_arch::macros::deinterleaving_load!(i8, 16, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { - transmute(vld4_s64(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { + crate::core_arch::macros::deinterleaving_load!(i16, 4, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { - transmute(vld4_s8(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { + crate::core_arch::macros::deinterleaving_load!(i16, 8, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { - transmute(vld4q_s8(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { + crate::core_arch::macros::deinterleaving_load!(i32, 2, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { - transmute(vld4_s16(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { + crate::core_arch::macros::deinterleaving_load!(i32, 4, 3, a) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { - transmute(vld4q_s16(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")] + fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t; + } + _vld3_f32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { - transmute(vld4_s32(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")] + fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t; + } + _vld3q_f32(a as *const i8, 4) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { - transmute(vld4q_s32(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")] + fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t; + } + _vld3_s8(a as *const i8, 1) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { - transmute(vld4_s8(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")] + fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t; + } + _vld3q_s8(a as *const i8, 1) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { - transmute(vld4q_s8(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")] + fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t; + } + _vld3_s16(a as *const i8, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { - transmute(vld4_s16(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")] + fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t; + } + _vld3q_s16(a as *const i8, 2) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { - transmute(vld4q_s16(transmute(a))) +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")] + fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t; + } + _vld3_s32(a as *const i8, 4) } -#[doc = "Store SIMD&FP register (immediate offset)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vldrq_p128(a: *const p128) -> p128 { - *a +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")] + fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t; + } + _vld3q_s32(a as *const i8, 4) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> float16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")] + fn _vld3_lane_f16( + ptr: *const f16, + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + n: i32, + size: i32, + ) -> float16x4x3_t; + } + _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) -> float16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")] + fn _vld3q_lane_f16( + ptr: *const f16, + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + n: i32, + size: i32, + ) -> float16x8x3_t; + } + _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmax) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> float16x4x3_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmax.v4f16" + link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0" )] - fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + fn _vld3_lane_f16( + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + n: i64, + ptr: *const f16, + ) -> float16x4x3_t; } - unsafe { _vmax_f16(a, b) } + _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmax) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) -> float16x8x3_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmax.v8f16" + link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0" )] - fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + fn _vld3q_lane_f16( + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + n: i64, + ptr: *const f16, + ) -> float16x8x3_t; } - unsafe { _vmaxq_f16(a, b) } + _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmax) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { + static_assert_uimm_bits!(LANE, 1); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmax.v2f32" + link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0" )] - fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + fn _vld3_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + n: i64, + ptr: *const i8, + ) -> float32x2x3_t; } - unsafe { _vmax_f32(a, b) } + _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmax) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmax.v4f32" + link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0" )] - fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + fn _vld3q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + n: i64, + ptr: *const i8, + ) -> float32x4x3_t; } - unsafe { _vmaxq_f32(a, b) } + _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { - let mask: int8x8_t = simd_ge(a, b); - simd_select(mask, a, b) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")] + fn _vld3_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x3_t; } + _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { - let mask: int8x16_t = simd_ge(a, b); - simd_select(mask, a, b) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0" + )] + fn _vld3_lane_s8( + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + n: i64, + ptr: *const i8, + ) -> int8x8x3_t; } + _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0" + )] + fn _vld3_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + n: i64, + ptr: *const i8, + ) -> int16x4x3_t; + } + _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { + static_assert_uimm_bits!(LANE, 4); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0" + )] + fn _vld3q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + n: i64, + ptr: *const i8, + ) -> int16x8x3_t; + } + _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0" + )] + fn _vld3_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + n: i64, + ptr: *const i8, + ) -> int32x2x3_t; + } + _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0" + )] + fn _vld3q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + n: i64, + ptr: *const i8, + ) -> int32x4x3_t; + } + _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")] + fn _vld3_lane_s8( + ptr: *const i8, + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + n: i32, + size: i32, + ) -> int8x8x3_t; + } + _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")] + fn _vld3_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x3_t; + } + _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")] + fn _vld3q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x3_t; + } + _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")] + fn _vld3_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x3_t; + } + _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) +} +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")] + fn _vld3q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x3_t; + } + _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) +} +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25649,22 +25005,23 @@ pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { - let mask: int16x4_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25673,22 +25030,23 @@ pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { - let mask: int16x8_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25697,22 +25055,23 @@ pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { - let mask: int32x2_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smax) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25721,22 +25080,23 @@ pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { - let mask: int32x4_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld3_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25745,22 +25105,23 @@ pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { - let mask: uint8x8_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3q_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25769,22 +25130,23 @@ pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { - let mask: uint8x16_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25793,22 +25155,23 @@ pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { - let mask: uint16x4_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(ld3, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -25817,21 +25180,21 @@ pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { - let mask: uint16x8_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -25841,21 +25204,48 @@ pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { - let mask: uint32x2_t = simd_ge(a, b); - simd_select(mask, a, b) +pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { + transmute(vld3_s64(transmute(a))) +} +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")] + fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t; } + _vld3_s64(a as *const i8, 8) } -#[doc = "Maximum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umax) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -25865,281 +25255,66 @@ pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { - let mask: uint32x4_t = simd_ge(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { + transmute(vld3_s64(transmute(a))) } -#[doc = "Floating-point Maximum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxnm) + assert_instr(ld3) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v4f16" - )] - fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; - } - unsafe { _vmaxnm_f16(a, b) } +pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { + transmute(vld3_s8(transmute(a))) } -#[doc = "Floating-point Maximum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxnm) + assert_instr(ld3) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v8f16" - )] - fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; - } - unsafe { _vmaxnmq_f16(a, b) } -} -#[doc = "Floating-point Maximum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxnm) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v2f32" - )] - fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vmaxnm_f32(a, b) } -} -#[doc = "Floating-point Maximum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxnm) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v4f32" - )] - fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - unsafe { _vmaxnmq_f32(a, b) } -} -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmin) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmin.v4f16" - )] - fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; - } - unsafe { _vmin_f16(a, b) } -} -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmin) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmin.v8f16" - )] - fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; - } - unsafe { _vminq_f16(a, b) } -} -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmin) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmin.v2f32" - )] - fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vmin_f32(a, b) } -} -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmin) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmin.v4f32" - )] - fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - unsafe { _vminq_f32(a, b) } -} -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { - let mask: int8x8_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { + transmute(vld3q_s8(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26149,21 +25324,20 @@ pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { - let mask: int8x16_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { + transmute(vld3_s16(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26173,21 +25347,20 @@ pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { - let mask: int16x4_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { + transmute(vld3q_s16(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26197,21 +25370,20 @@ pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { - let mask: int16x8_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { + transmute(vld3_s32(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26221,21 +25393,20 @@ pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { - let mask: int32x2_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { + transmute(vld3q_s32(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smin) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26245,21 +25416,20 @@ pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { - let mask: int32x4_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { + transmute(vld3_s8(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26269,21 +25439,20 @@ pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { - let mask: uint8x8_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { + transmute(vld3q_s8(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26293,21 +25462,20 @@ pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { - let mask: uint8x16_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { + transmute(vld3_s16(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"] -#[inline(always)] +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) + assert_instr(ld3) )] #[cfg_attr( not(target_arch = "arm"), @@ -26317,182 +25485,426 @@ pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { - let mask: uint16x4_t = simd_le(a, b); - simd_select(mask, a, b) - } +pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { + transmute(vld3q_s16(transmute(a))) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { - let mask: uint16x8_t = simd_le(a, b); - simd_select(mask, a, b) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")] + fn _vld3q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x3_t; } + _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { - let mask: uint32x2_t = simd_le(a, b); - simd_select(mask, a, b) +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0")] + fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t; } + _vld4_dup_f16(a as _, 2) } -#[doc = "Minimum (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umin) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { - let mask: uint32x4_t = simd_le(a, b); - simd_select(mask, a, b) +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0")] + fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t; } + _vld4q_dup_f16(a as _, 2) } -#[doc = "Floating-point Minimum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminnm) + assert_instr(ld4r) )] #[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v4f16" + link_name = "llvm.aarch64.neon.ld4r.v4f16.p0" )] - fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t; } - unsafe { _vminnm_f16(a, b) } + _vld4_dup_f16(a as _) } -#[doc = "Floating-point Minimum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminnm) + assert_instr(ld4r) )] #[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] -pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v8f16" + link_name = "llvm.aarch64.neon.ld4r.v8f16.p0" )] - fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t; } - unsafe { _vminnmq_f16(a, b) } + _vld4q_dup_f16(a as _) } -#[doc = "Floating-point Minimum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminnm) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")] + fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t; + } + _vld4_dup_f32(a as *const i8, 4) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")] + fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t; + } + _vld4q_dup_f32(a as *const i8, 4) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")] + fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t; + } + _vld4_dup_s8(a as *const i8, 1) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")] + fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t; + } + _vld4q_dup_s8(a as *const i8, 1) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")] + fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t; + } + _vld4_dup_s16(a as *const i8, 2) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")] + fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t; + } + _vld4q_dup_s16(a as *const i8, 2) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")] + fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t; + } + _vld4_dup_s32(a as *const i8, 4) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")] + fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t; + } + _vld4q_dup_s32(a as *const i8, 4) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v2f32" + link_name = "llvm.aarch64.neon.ld4r.v2f32.p0.p0" )] - fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t; } - unsafe { _vminnm_f32(a, b) } + _vld4_dup_f32(a as _) } -#[doc = "Floating-point Minimum Number (vector)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v4f32.p0.p0" + )] + fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t; + } + _vld4q_dup_f32(a as _) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v8i8.p0.p0" + )] + fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t; + } + _vld4_dup_s8(a as _) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v16i8.p0.p0" + )] + fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t; + } + _vld4q_dup_s8(a as _) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v4i16.p0.p0" + )] + fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t; + } + _vld4_dup_s16(a as _) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v8i16.p0.p0" + )] + fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t; + } + _vld4q_dup_s16(a as _) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v2i32.p0.p0" + )] + fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t; + } + _vld4_dup_s32(a as _) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v4i32.p0.p0" + )] + fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t; + } + _vld4q_dup_s32(a as _) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v1i64.p0.p0" + )] + fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t; + } + _vld4_dup_s64(a as _) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminnm) + assert_instr(ld4r) )] #[cfg_attr( not(target_arch = "arm"), @@ -26502,26 +25914,36 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { + transmute(vld4_dup_s64(transmute(a))) +} +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(nop))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v4f32" - )] - fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")] + fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t; } - unsafe { _vminnmq_f32(a, b) } + _vld4_dup_s64(a as *const i8, 8) } -#[doc = "Floating-point multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) + assert_instr(ld4r) )] #[cfg_attr( not(target_arch = "arm"), @@ -26531,18 +25953,20 @@ pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - unsafe { simd_add(a, simd_mul(b, c)) } +pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { + transmute(vld4_dup_s64(transmute(a))) } -#[doc = "Floating-point multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) + assert_instr(ld4r) )] #[cfg_attr( not(target_arch = "arm"), @@ -26552,20 +25976,21 @@ pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - unsafe { simd_add(a, simd_mul(b, c)) } +pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { + transmute(vld4_dup_s8(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26574,25 +25999,21 @@ pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, -) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { + transmute(vld4q_dup_s8(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26601,25 +26022,21 @@ pub fn vmla_lane_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_laneq_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x4_t, -) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { + transmute(vld4_dup_s16(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26628,31 +26045,21 @@ pub fn vmla_laneq_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x2_t, -) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlaq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { + transmute(vld4q_dup_s16(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26661,31 +26068,21 @@ pub fn vmlaq_lane_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_laneq_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, -) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlaq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { + transmute(vld4_dup_s32(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26694,27 +26091,21 @@ pub fn vmlaq_laneq_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmla_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { + transmute(vld4q_dup_s32(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26723,27 +26114,21 @@ pub fn vmla_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmla_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { + transmute(vld4_dup_s8(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26752,27 +26137,21 @@ pub fn vmla_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmla_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { + transmute(vld4q_dup_s8(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26781,27 +26160,21 @@ pub fn vmla_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmla_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmla_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { + transmute(vld4_dup_s16(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"] -#[inline(always)] +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) + assert_instr(ld4r) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -26810,5260 +26183,812 @@ pub fn vmla_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmlaq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlaq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } +pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { + transmute(vld4q_dup_s16(transmute(a))) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlaq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0")] + fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t; } + _vld4_f16(a as _, 2) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlaq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0")] + fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t; } + _vld4q_f16(a as _, 2) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld4) )] -pub fn vmlaq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlaq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { + crate::core_arch::macros::deinterleaving_load!(f16, 4, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[doc = "Load single 4-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld4) )] -pub fn vmla_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { + crate::core_arch::macros::deinterleaving_load!(f16, 8, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { + crate::core_arch::macros::deinterleaving_load!(f32, 2, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { + crate::core_arch::macros::deinterleaving_load!(f32, 4, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { + crate::core_arch::macros::deinterleaving_load!(i8, 8, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlaq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { + crate::core_arch::macros::deinterleaving_load!(i8, 16, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlaq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { + crate::core_arch::macros::deinterleaving_load!(i16, 4, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlaq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { + crate::core_arch::macros::deinterleaving_load!(i16, 8, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlaq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { + crate::core_arch::macros::deinterleaving_load!(i32, 2, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vmla_f32(a, b, vdup_n_f32(c)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { + crate::core_arch::macros::deinterleaving_load!(i32, 4, 4, a) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vmlaq_f32(a, b, vdupq_n_f32(c)) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")] + fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t; + } + _vld4_f32(a as *const i8, 4) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { - vmla_s16(a, b, vdup_n_s16(c)) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")] + fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t; + } + _vld4q_f32(a as *const i8, 4) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { - vmlaq_s16(a, b, vdupq_n_s16(c)) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")] + fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t; + } + _vld4_s8(a as *const i8, 1) } -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { - vmla_u16(a, b, vdup_n_u16(c)) -} -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { - vmlaq_u16(a, b, vdupq_n_u16(c)) -} -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { - vmla_s32(a, b, vdup_n_s32(c)) -} -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { - vmlaq_s32(a, b, vdupq_n_s32(c)) -} -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { - vmla_u32(a, b, vdup_n_u32(c)) -} -#[doc = "Vector multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { - vmlaq_u32(a, b, vdupq_n_u32(c)) -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Multiply-add to accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mla) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - unsafe { simd_add(a, simd_mul(b, c)) } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlal_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlal_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { - vmlal_s16(a, b, vdup_n_s16(c)) -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { - vmlal_s32(a, b, vdup_n_s32(c)) -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { - vmlal_u16(a, b, vdup_n_u16(c)) -} -#[doc = "Vector widening multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { - vmlal_u32(a, b, vdup_n_u32(c)) -} -#[doc = "Signed multiply-add long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { - unsafe { simd_add(a, vmull_s8(b, c)) } -} -#[doc = "Signed multiply-add long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - unsafe { simd_add(a, vmull_s16(b, c)) } -} -#[doc = "Signed multiply-add long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - unsafe { simd_add(a, vmull_s32(b, c)) } -} -#[doc = "Unsigned multiply-add long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { - unsafe { simd_add(a, vmull_u8(b, c)) } -} -#[doc = "Unsigned multiply-add long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - unsafe { simd_add(a, vmull_u16(b, c)) } -} -#[doc = "Unsigned multiply-add long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlal) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - unsafe { simd_add(a, vmull_u32(b, c)) } -} -#[doc = "Floating-point multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Floating-point multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, -) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_laneq_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x4_t, -) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x2_t, -) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_laneq_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, -) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmls_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmls_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmls_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmls_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vmls_f32(a, b, vdup_n_f32(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vmlsq_f32(a, b, vdupq_n_f32(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { - vmls_s16(a, b, vdup_n_s16(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { - vmlsq_s16(a, b, vdupq_n_s16(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { - vmls_u16(a, b, vdup_n_u16(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { - vmlsq_u16(a, b, vdupq_n_u16(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { - vmls_s32(a, b, vdup_n_s32(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { - vmlsq_s32(a, b, vdupq_n_s32(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { - vmls_u32(a, b, vdup_n_u32(c)) -} -#[doc = "Vector multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { - vmlsq_u32(a, b, vdupq_n_u32(c)) -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Multiply-subtract from accumulator"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mls) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - unsafe { simd_sub(a, simd_mul(b, c)) } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsl_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsl_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl, LANE = 1) -)] -#[rustc_legacy_const_generics(3)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { - vmlsl_s16(a, b, vdup_n_s16(c)) -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { - vmlsl_s32(a, b, vdup_n_s32(c)) -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { - vmlsl_u16(a, b, vdup_n_u16(c)) -} -#[doc = "Vector widening multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { - vmlsl_u32(a, b, vdup_n_u32(c)) -} -#[doc = "Signed multiply-subtract long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { - unsafe { simd_sub(a, vmull_s8(b, c)) } -} -#[doc = "Signed multiply-subtract long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - unsafe { simd_sub(a, vmull_s16(b, c)) } -} -#[doc = "Signed multiply-subtract long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - unsafe { simd_sub(a, vmull_s32(b, c)) } -} -#[doc = "Unsigned multiply-subtract long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { - unsafe { simd_sub(a, vmull_u8(b, c)) } -} -#[doc = "Unsigned multiply-subtract long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - unsafe { simd_sub(a, vmull_u16(b, c)) } -} -#[doc = "Unsigned multiply-subtract long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umlsl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - unsafe { simd_sub(a, vmull_u32(b, c)) } -} -#[doc = "8-bit integer matrix multiply-accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smmla) -)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smmla.v4i32.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.smmla.v4i32.v16i8")] - fn _vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; - } - unsafe { _vmmlaq_s32(a, b, c) } -} -#[doc = "8-bit integer matrix multiply-accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ummla) -)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ummla.v4i32.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.ummla.v4i32.v16i8")] - fn _vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t; - } - unsafe { _vmmlaq_u32(a, b, c) } -} -#[doc = "Duplicate element to vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmov_n_f16(a: f16) -> float16x4_t { - vdup_n_f16(a) -} -#[doc = "Duplicate element to vector"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmovq_n_f16(a: f16) -> float16x8_t { - vdupq_n_f16(a) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_f32(value: f32) -> float32x2_t { - vdup_n_f32(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_p16(value: p16) -> poly16x4_t { - vdup_n_p16(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_p8(value: p8) -> poly8x8_t { - vdup_n_p8(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_s16(value: i16) -> int16x4_t { - vdup_n_s16(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_s32(value: i32) -> int32x2_t { - vdup_n_s32(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmov) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_s64(value: i64) -> int64x1_t { - vdup_n_s64(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_s8(value: i8) -> int8x8_t { - vdup_n_s8(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_u16(value: u16) -> uint16x4_t { - vdup_n_u16(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_u32(value: u32) -> uint32x2_t { - vdup_n_u32(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmov) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_u64(value: u64) -> uint64x1_t { - vdup_n_u64(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmov_n_u8(value: u8) -> uint8x8_t { - vdup_n_u8(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_f32(value: f32) -> float32x4_t { - vdupq_n_f32(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_p16(value: p16) -> poly16x8_t { - vdupq_n_p16(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_p8(value: p8) -> poly8x16_t { - vdupq_n_p8(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_s16(value: i16) -> int16x8_t { - vdupq_n_s16(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_s32(value: i32) -> int32x4_t { - vdupq_n_s32(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_s64(value: i64) -> int64x2_t { - vdupq_n_s64(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_s8(value: i8) -> int8x16_t { - vdupq_n_s8(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_u16(value: u16) -> uint16x8_t { - vdupq_n_u16(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_u32(value: u32) -> uint32x4_t { - vdupq_n_u32(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_u64(value: u64) -> uint64x2_t { - vdupq_n_u64(value) -} -#[doc = "Duplicate vector element to vector or scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(dup) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovq_n_u8(value: u8) -> uint8x16_t { - vdupq_n_u8(value) -} -#[doc = "Vector long move."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sxtl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovl_s16(a: int16x4_t) -> int32x4_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector long move."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sxtl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovl_s32(a: int32x2_t) -> int64x2_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector long move."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sxtl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovl_s8(a: int8x8_t) -> int16x8_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector long move."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uxtl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector long move."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uxtl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector long move."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uxtl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector narrow integer."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(xtn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovn_s16(a: int16x8_t) -> int8x8_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector narrow integer."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(xtn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovn_s32(a: int32x4_t) -> int16x4_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector narrow integer."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(xtn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovn_s64(a: int64x2_t) -> int32x2_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector narrow integer."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(xtn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector narrow integer."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(xtn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t { - unsafe { simd_cast(a) } -} -#[doc = "Vector narrow integer."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(xtn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { - unsafe { simd_cast(a) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmulq_lane_f16(a: float16x8_t, v: float16x4_t) -> float16x8_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!( - v, - v, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } -} -#[doc = "Floating-point multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -} -#[doc = "Floating-point multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -} -#[doc = "Floating-point multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Floating-point multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")] + fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t; } + _vld4q_s8(a as *const i8, 1) } -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")] + fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t; } + _vld4_s16(a as *const i8, 2) } -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")] + fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t; } + _vld4q_s16(a as *const i8, 2) } -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")] + fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t; } + _vld4_s32(a as *const i8, 4) } -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")] + fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t; } + _vld4q_s32(a as *const i8, 4) } -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t { - unsafe { simd_mul(a, vdup_n_f16(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { - unsafe { simd_mul(a, vdupq_n_f16(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { - unsafe { simd_mul(a, vdup_n_f32(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { - unsafe { simd_mul(a, vdupq_n_f32(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { - unsafe { simd_mul(a, vdup_n_s16(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { - unsafe { simd_mul(a, vdupq_n_s16(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { - unsafe { simd_mul(a, vdup_n_s32(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { - unsafe { simd_mul(a, vdupq_n_s32(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { - unsafe { simd_mul(a, vdup_n_u16(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { - unsafe { simd_mul(a, vdupq_n_u16(b)) } -} -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { - unsafe { simd_mul(a, vdup_n_u32(b)) } +#[doc = "Load multiple 4-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> float16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")] + fn _vld4_lane_f16( + ptr: *const f16, + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + d: float16x4_t, + n: i32, + size: i32, + ) -> float16x4x4_t; + } + _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } -#[doc = "Vector multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { - unsafe { simd_mul(a, vdupq_n_u32(b)) } +#[doc = "Load multiple 4-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) -> float16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")] + fn _vld4q_lane_f16( + ptr: *const f16, + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + d: float16x8_t, + n: i32, + size: i32, + ) -> float16x8x4_t; + } + _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } -#[doc = "Polynomial multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[doc = "Load multiple 4-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(pmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld4, LANE = 0) )] -pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> float16x4x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.pmul.v8i8" + link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0" )] - fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t; + fn _vld4_lane_f16( + a: float16x4_t, + b: float16x4_t, + c: float16x4_t, + d: float16x4_t, + n: i64, + ptr: *const f16, + ) -> float16x4x4_t; } - unsafe { _vmul_p8(a, b) } + _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Polynomial multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[doc = "Load multiple 4-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(not(target_arch = "arm"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(pmul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(ld4, LANE = 0) )] -pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) -> float16x8x4_t { + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.pmul.v16i8" + link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0" )] - fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t; + fn _vld4q_lane_f16( + a: float16x8_t, + b: float16x8_t, + c: float16x8_t, + d: float16x8_t, + n: i64, + ptr: *const f16, + ) -> float16x8x4_t; } - unsafe { _vmulq_p8(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_mul(a, b) } -} -#[doc = "Multiply"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mul) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { simd_mul(a, b) } + _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Vector long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull, LANE = 1) -)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_s16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0" + )] + fn _vld4_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i64, + ptr: *const i8, + ) -> float32x2x4_t; } + _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Vector long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull, LANE = 1) -)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - vmull_s16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0" + )] + fn _vld4q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i64, + ptr: *const i8, + ) -> float32x4x4_t; } + _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Vector long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull, LANE = 1) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull, LANE = 1) -)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0" + )] + fn _vld4_lane_s8( + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + n: i64, + ptr: *const i8, + ) -> int8x8x4_t; + } + _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Vector long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull, LANE = 1) -)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_u16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0" + )] + fn _vld4_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i64, + ptr: *const i8, + ) -> int16x4x4_t; } + _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Vector long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull, LANE = 1) -)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmull_u16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0" + )] + fn _vld4q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i64, + ptr: *const i8, + ) -> int16x8x4_t; } + _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Vector long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull, LANE = 1) -)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0" + )] + fn _vld4_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i64, + ptr: *const i8, + ) -> int32x2x4_t; + } + _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Vector long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull, LANE = 1) -)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -} -#[doc = "Vector long multiply with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { - vmull_s16(a, vdup_n_s16(b)) + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0" + )] + fn _vld4q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i64, + ptr: *const i8, + ) -> int32x4x4_t; + } + _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -#[doc = "Vector long multiply with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { - vmull_s32(a, vdup_n_s32(b)) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")] + fn _vld4_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x4_t; + } + _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -#[doc = "Vector long multiply with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { - vmull_u16(a, vdup_n_u16(b)) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")] + fn _vld4q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x4_t; + } + _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -#[doc = "Vector long multiply with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { - vmull_u32(a, vdup_n_u32(b)) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")] + fn _vld4_lane_s8( + ptr: *const i8, + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + n: i32, + size: i32, + ) -> int8x8x4_t; + } + _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) } -#[doc = "Polynomial multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(pmull) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.pmull.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i16")] - fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")] + fn _vld4_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x4_t; } - unsafe { _vmull_p8(a, b) } + _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } -#[doc = "Signed multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - unsafe { simd_mul(simd_cast(a), simd_cast(b)) } +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")] + fn _vld4q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x4_t; + } + _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } -#[doc = "Signed multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - unsafe { simd_mul(simd_cast(a), simd_cast(b)) } +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")] + fn _vld4_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x4_t; + } + _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -#[doc = "Signed multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smull) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - unsafe { simd_mul(simd_cast(a), simd_cast(b)) } +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")] + fn _vld4q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x4_t; + } + _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -#[doc = "Unsigned multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -32072,19 +26997,23 @@ pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - unsafe { simd_mul(simd_cast(a), simd_cast(b)) } +pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Unsigned multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -32093,19 +27022,23 @@ pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - unsafe { simd_mul(simd_cast(a), simd_cast(b)) } +pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Unsigned multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umull) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -32114,19 +27047,23 @@ pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - unsafe { simd_mul(simd_cast(a), simd_cast(b)) } +pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -32135,20 +27072,23 @@ pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t { - let b = poly8x8_t::splat(255); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld4_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -32157,20 +27097,23 @@ pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvn_s16(a: int16x4_t) -> int16x4_t { - let b = int16x4_t::splat(-1); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4q_lane_s32::(transmute(a), transmute(b))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -32179,20 +27122,23 @@ pub fn vmvn_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvn_s32(a: int32x2_t) -> int32x2_t { - let b = int32x2_t::splat(-1); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4_lane_s8::(transmute(a), transmute(b))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -32201,20 +27147,23 @@ pub fn vmvn_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvn_s8(a: int8x8_t) -> int8x8_t { - let b = int8x8_t::splat(-1); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -32223,19 +27172,21 @@ pub fn vmvn_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t { - let b = uint16x4_t::splat(65_535); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -32245,19 +27196,48 @@ pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t { - let b = uint32x2_t::splat(4_294_967_295); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { + transmute(vld4_s64(transmute(a))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")] + fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t; + } + _vld4_s64(a as *const i8, 8) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -32267,19 +27247,20 @@ pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t { - let b = uint8x8_t::splat(255); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { + transmute(vld4_s64(transmute(a))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32289,19 +27270,20 @@ pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t { - let b = poly8x16_t::splat(255); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { + transmute(vld4_s8(transmute(a))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32311,19 +27293,20 @@ pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t { - let b = int16x8_t::splat(-1); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { + transmute(vld4q_s8(transmute(a))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32333,19 +27316,20 @@ pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t { - let b = int32x4_t::splat(-1); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { + transmute(vld4_s16(transmute(a))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32355,19 +27339,20 @@ pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t { - let b = int8x16_t::splat(-1); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { + transmute(vld4q_s16(transmute(a))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32377,19 +27362,20 @@ pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t { - let b = uint16x8_t::splat(65_535); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { + transmute(vld4_s32(transmute(a))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32399,19 +27385,20 @@ pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t { - let b = uint32x4_t::splat(4_294_967_295); - unsafe { simd_xor(a, b) } +pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { + transmute(vld4q_s32(transmute(a))) } -#[doc = "Vector bitwise not."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(mvn) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32421,63 +27408,20 @@ pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { - let b = uint8x16_t::splat(255); - unsafe { simd_xor(a, b) } -} -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fneg) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vneg_f16(a: float16x4_t) -> float16x4_t { - unsafe { simd_neg(a) } -} -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fneg) -)] -#[target_feature(enable = "neon,fp16")] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vnegq_f16(a: float16x8_t) -> float16x8_t { - unsafe { simd_neg(a) } +pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { + transmute(vld4_s8(transmute(a))) } -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fneg) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32487,18 +27431,20 @@ pub fn vnegq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vneg_f32(a: float32x2_t) -> float32x2_t { - unsafe { simd_neg(a) } +pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { + transmute(vld4q_s8(transmute(a))) } -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fneg) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32508,18 +27454,20 @@ pub fn vneg_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vnegq_f32(a: float32x4_t) -> float32x4_t { - unsafe { simd_neg(a) } +pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { + transmute(vld4_s16(transmute(a))) } -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"] -#[inline(always)] +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(neg) + assert_instr(ld4) )] #[cfg_attr( not(target_arch = "arm"), @@ -32529,18 +27477,20 @@ pub fn vnegq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vneg_s8(a: int8x8_t) -> int8x8_t { - unsafe { simd_neg(a) } +pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { + transmute(vld4q_s16(transmute(a))) } -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"] -#[inline(always)] +#[doc = "Store SIMD&FP register (immediate offset)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(neg) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -32550,60 +27500,78 @@ pub fn vneg_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vnegq_s8(a: int8x16_t) -> int8x16_t { - unsafe { simd_neg(a) } +pub unsafe fn vldrq_p128(a: *const p128) -> p128 { + *a } -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(neg) + assert_instr(fmax) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vneg_s16(a: int16x4_t) -> int16x4_t { - unsafe { simd_neg(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmax.v4f16" + )] + fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vmax_f16(a, b) } } -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(neg) + assert_instr(fmax) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vnegq_s16(a: int16x8_t) -> int16x8_t { - unsafe { simd_neg(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmax.v8f16" + )] + fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vmaxq_f16(a, b) } } -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(neg) + assert_instr(fmax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32613,18 +27581,26 @@ pub fn vnegq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vneg_s32(a: int32x2_t) -> int32x2_t { - unsafe { simd_neg(a) } +pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmax.v2f32" + )] + fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vmax_f32(a, b) } } -#[doc = "Negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(neg) + assert_instr(fmax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32634,18 +27610,26 @@ pub fn vneg_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vnegq_s32(a: int32x4_t) -> int32x4_t { - unsafe { simd_neg(a) } +pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmax.v4f32" + )] + fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vmaxq_f32(a, b) } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32655,19 +27639,21 @@ pub fn vnegq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - let c = int16x4_t::splat(-1); - unsafe { simd_or(simd_xor(b, c), a) } +pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let mask: int8x8_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32677,19 +27663,21 @@ pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - let c = int32x2_t::splat(-1); - unsafe { simd_or(simd_xor(b, c), a) } +pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let mask: int8x16_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32699,19 +27687,21 @@ pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - let c = int64x1_t::splat(-1); - unsafe { simd_or(simd_xor(b, c), a) } +pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let mask: int16x4_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32721,19 +27711,21 @@ pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - let c = int8x8_t::splat(-1); - unsafe { simd_or(simd_xor(b, c), a) } +pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let mask: int16x8_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32743,19 +27735,21 @@ pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - let c = int16x8_t::splat(-1); - unsafe { simd_or(simd_xor(b, c), a) } +pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let mask: int32x2_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(smax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32765,19 +27759,21 @@ pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - let c = int32x4_t::splat(-1); - unsafe { simd_or(simd_xor(b, c), a) } +pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let mask: int32x4_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32787,19 +27783,21 @@ pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - let c = int64x2_t::splat(-1); - unsafe { simd_or(simd_xor(b, c), a) } +pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let mask: uint8x8_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32809,19 +27807,21 @@ pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - let c = int8x16_t::splat(-1); - unsafe { simd_or(simd_xor(b, c), a) } +pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let mask: uint8x16_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32831,19 +27831,21 @@ pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - let c = int16x4_t::splat(-1); - unsafe { simd_or(simd_xor(b, transmute(c)), a) } +pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let mask: uint16x4_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32853,19 +27855,21 @@ pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - let c = int32x2_t::splat(-1); - unsafe { simd_or(simd_xor(b, transmute(c)), a) } +pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let mask: uint16x8_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32875,19 +27879,21 @@ pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - let c = int64x1_t::splat(-1); - unsafe { simd_or(simd_xor(b, transmute(c)), a) } +pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let mask: uint32x2_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"] -#[inline(always)] +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(umax) )] #[cfg_attr( not(target_arch = "arm"), @@ -32897,63 +27903,81 @@ pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - let c = int8x8_t::splat(-1); - unsafe { simd_or(simd_xor(b, transmute(c)), a) } +pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let mask: uint32x4_t = simd_ge(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(fmaxnm) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - let c = int16x8_t::splat(-1); - unsafe { simd_or(simd_xor(b, transmute(c)), a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v4f16" + )] + fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vmaxnm_f16(a, b) } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(fmaxnm) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - let c = int32x4_t::splat(-1); - unsafe { simd_or(simd_xor(b, transmute(c)), a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v8f16" + )] + fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vmaxnmq_f16(a, b) } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"] -#[inline(always)] +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(fmaxnm) )] #[cfg_attr( not(target_arch = "arm"), @@ -32963,19 +27987,26 @@ pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - let c = int64x2_t::splat(-1); - unsafe { simd_or(simd_xor(b, transmute(c)), a) } +pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v2f32" + )] + fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vmaxnm_f32(a, b) } } -#[doc = "Vector bitwise inclusive OR NOT"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"] -#[inline(always)] +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orn) + assert_instr(fmaxnm) )] #[cfg_attr( not(target_arch = "arm"), @@ -32985,61 +28016,86 @@ pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - let c = int8x16_t::splat(-1); - unsafe { simd_or(simd_xor(b, transmute(c)), a) } +pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v4f32" + )] + fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vmaxnmq_f32(a, b) } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(fmin) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_or(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v4f16" + )] + fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vmin_f16(a, b) } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(fmin) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { simd_or(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v8f16" + )] + fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vminq_f16(a, b) } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(fmin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33049,18 +28105,26 @@ pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_or(a, b) } +pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v2f32" + )] + fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vmin_f32(a, b) } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(fmin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33070,18 +28134,26 @@ pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_or(a, b) } +pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v4f32" + )] + fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vminq_f32(a, b) } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(smin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33091,18 +28163,21 @@ pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { simd_or(a, b) } +pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { + let mask: int8x8_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(smin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33112,18 +28187,21 @@ pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_or(a, b) } +pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + let mask: int8x16_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(smin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33133,18 +28211,21 @@ pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe { simd_or(a, b) } +pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { + let mask: int16x4_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(smin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33154,18 +28235,21 @@ pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe { simd_or(a, b) } +pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { + let mask: int16x8_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(smin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33175,18 +28259,21 @@ pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_or(a, b) } +pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { + let mask: int32x2_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(smin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33196,18 +28283,21 @@ pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { simd_or(a, b) } +pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { + let mask: int32x4_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(umin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33217,18 +28307,21 @@ pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_or(a, b) } +pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let mask: uint8x8_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(umin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33238,18 +28331,21 @@ pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_or(a, b) } +pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let mask: uint8x16_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(umin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33259,18 +28355,21 @@ pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { simd_or(a, b) } +pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let mask: uint16x4_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(umin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33280,18 +28379,21 @@ pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_or(a, b) } +pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let mask: uint16x8_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(umin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33301,18 +28403,21 @@ pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - unsafe { simd_or(a, b) } +pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let mask: uint32x2_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Vector bitwise or (immediate, inclusive)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"] -#[inline(always)] +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(orr) + assert_instr(umin) )] #[cfg_attr( not(target_arch = "arm"), @@ -33322,78 +28427,81 @@ pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { simd_or(a, b) } +pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let mask: uint32x4_t = simd_le(a, b); + simd_select(mask, a, b) + } } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))] +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sadalp) + assert_instr(fminnm) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { - let x: int16x4_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadal_s8(a, b); +#[cfg(not(target_arch = "arm64ec"))] +pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v4f16" + )] + fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddl_s8(b), a); - }; - x + unsafe { _vminnm_f16(a, b) } } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))] +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sadalp) + assert_instr(fminnm) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { - let x: int16x8_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadalq_s8(a, b); +#[cfg(not(target_arch = "arm64ec"))] +pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v8f16" + )] + fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddlq_s8(b), a); - }; - x + unsafe { _vminnmq_f16(a, b) } } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"] -#[inline(always)] +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sadalp) + assert_instr(fminnm) )] #[cfg_attr( not(target_arch = "arm"), @@ -33403,27 +28511,26 @@ pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { - let x: int32x2_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadal_s16(a, b); +pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v2f32" + )] + fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddl_s16(b), a); - }; - x + unsafe { _vminnm_f32(a, b) } } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"] -#[inline(always)] +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sadalp) + assert_instr(fminnm) )] #[cfg_attr( not(target_arch = "arm"), @@ -33433,27 +28540,26 @@ pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { - let x: int32x4_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadalq_s16(a, b); +pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v4f32" + )] + fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddlq_s16(b), a); - }; - x + unsafe { _vminnmq_f32(a, b) } } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"] -#[inline(always)] +#[doc = "Floating-point multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sadalp) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -33463,27 +28569,18 @@ pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { - let x: int64x1_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadal_s32(a, b); - } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddl_s32(b), a); - }; - x +pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"] -#[inline(always)] +#[doc = "Floating-point multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sadalp) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -33493,28 +28590,20 @@ pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { - let x: int64x2_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadalq_s32(a, b); - } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddlq_s32(b), a); - }; - x +pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uadalp) + assert_instr(fmul, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33523,28 +28612,25 @@ pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { - let x: uint16x4_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadal_u8(a, b); - } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddl_u8(b), a); - }; - x +pub fn vmla_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_f32(a, b, vdup_lane_f32::(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uadalp) + assert_instr(fmul, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33553,28 +28639,25 @@ pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { - let x: uint16x8_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadalq_u8(a, b); - } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddlq_u8(b), a); - }; - x +pub fn vmla_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_f32(a, b, vdup_laneq_f32::(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uadalp) + assert_instr(fmul, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33583,28 +28666,25 @@ pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { - let x: uint32x2_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadal_u16(a, b); - } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddl_u16(b), a); - }; - x +pub fn vmlaq_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlaq_f32(a, b, vdupq_lane_f32::(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uadalp) + assert_instr(fmul, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33613,28 +28693,25 @@ pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { - let x: uint32x4_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadalq_u16(a, b); - } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddlq_u16(b), a); - }; - x +pub fn vmlaq_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_f32(a, b, vdupq_laneq_f32::(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uadalp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33643,28 +28720,21 @@ pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { - let x: uint64x1_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadal_u32(a, b); - } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddl_u32(b), a); - }; - x +pub fn vmla_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmla_s16(a, b, vdup_lane_s16::(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uadalp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33673,58 +28743,44 @@ pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { - let x: uint64x2_t; - #[cfg(target_arch = "arm")] - { - x = priv_vpadalq_u32(a, b); - } - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - unsafe { - x = simd_add(vpaddlq_u32(b), a); - }; - x +pub fn vmla_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmla_u16(a, b, vdup_lane_u16::(c)) } -#[doc = "Floating-point add pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(faddp) + assert_instr(mla, LANE = 1) )] -#[target_feature(enable = "neon,fp16")] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v4f16" - )] - fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; - } - unsafe { _vpadd_f16(a, b) } +pub fn vmla_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmla_s16(a, b, vdup_laneq_s16::(c)) } -#[doc = "Floating-point add pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(faddp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33733,27 +28789,21 @@ pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v2f32" - )] - fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vpadd_f32(a, b) } +pub fn vmla_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmla_u16(a, b, vdup_laneq_u16::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33762,27 +28812,21 @@ pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")] - fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vpadd_s8(a, b) } +pub fn vmlaq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_s16(a, b, vdupq_lane_s16::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33791,27 +28835,21 @@ pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")] - fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vpadd_s16(a, b) } +pub fn vmlaq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_u16(a, b, vdupq_lane_u16::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33820,28 +28858,21 @@ pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")] - fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vpadd_s32(a, b) } +pub fn vmlaq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlaq_s16(a, b, vdupq_laneq_s16::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33850,20 +28881,21 @@ pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) } +pub fn vmlaq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlaq_u16(a, b, vdupq_laneq_u16::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33872,25 +28904,21 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vmla_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_s32(a, b, vdup_lane_s32::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33898,21 +28926,22 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) } +)] +pub fn vmla_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_u32(a, b, vdup_lane_u32::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33921,25 +28950,21 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint16x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vmla_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_s32(a, b, vdup_laneq_s32::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33948,20 +28973,21 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) } +pub fn vmla_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_u32(a, b, vdup_laneq_u32::(c)) } -#[doc = "Add pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(addp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33970,24 +28996,21 @@ pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint32x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vmlaq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlaq_s32(a, b, vdupq_lane_s32::(c)) } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(saddlp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -33996,27 +29019,21 @@ pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.saddlp.v4i16.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i16.v8i8")] - fn _vpaddl_s8(a: int8x8_t) -> int16x4_t; - } - unsafe { _vpaddl_s8(a) } +pub fn vmlaq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlaq_u32(a, b, vdupq_lane_u32::(c)) } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(saddlp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34025,27 +29042,21 @@ pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.saddlp.v8i16.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v8i16.v16i8")] - fn _vpaddlq_s8(a: int8x16_t) -> int16x8_t; - } - unsafe { _vpaddlq_s8(a) } +pub fn vmlaq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_s32(a, b, vdupq_laneq_s32::(c)) } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(saddlp) + assert_instr(mla, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34054,26 +29065,19 @@ pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.saddlp.v2i32.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i32.v4i16")] - fn _vpaddl_s16(a: int16x4_t) -> int32x2_t; - } - unsafe { _vpaddl_s16(a) } +pub fn vmlaq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_u32(a, b, vdupq_laneq_u32::(c)) } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(saddlp) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -34083,26 +29087,18 @@ pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.saddlp.v4i32.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i32.v8i16")] - fn _vpaddlq_s16(a: int16x8_t) -> int32x4_t; - } - unsafe { _vpaddlq_s16(a) } +pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vmla_f32(a, b, vdup_n_f32(c)) } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(saddlp) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -34112,26 +29108,18 @@ pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.saddlp.v1i64.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v1i64.v2i32")] - fn _vpaddl_s32(a: int32x2_t) -> int64x1_t; - } - unsafe { _vpaddl_s32(a) } +pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vmlaq_f32(a, b, vdupq_n_f32(c)) } -#[doc = "Signed Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(saddlp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34141,26 +29129,18 @@ pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.saddlp.v2i64.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i64.v4i32")] - fn _vpaddlq_s32(a: int32x4_t) -> int64x2_t; - } - unsafe { _vpaddlq_s32(a) } +pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { + vmla_s16(a, b, vdup_n_s16(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uaddlp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34170,26 +29150,18 @@ pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uaddlp.v4i16.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i16.v8i8")] - fn _vpaddl_u8(a: uint8x8_t) -> uint16x4_t; - } - unsafe { _vpaddl_u8(a) } +pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { + vmlaq_s16(a, b, vdupq_n_s16(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uaddlp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34199,26 +29171,18 @@ pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uaddlp.v8i16.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v8i16.v16i8")] - fn _vpaddlq_u8(a: uint8x16_t) -> uint16x8_t; - } - unsafe { _vpaddlq_u8(a) } +pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { + vmla_u16(a, b, vdup_n_u16(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uaddlp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34228,26 +29192,18 @@ pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uaddlp.v2i32.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i32.v4i16")] - fn _vpaddl_u16(a: uint16x4_t) -> uint32x2_t; - } - unsafe { _vpaddl_u16(a) } +pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { + vmlaq_u16(a, b, vdupq_n_u16(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uaddlp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34257,26 +29213,18 @@ pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uaddlp.v4i32.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i32.v8i16")] - fn _vpaddlq_u16(a: uint16x8_t) -> uint32x4_t; - } - unsafe { _vpaddlq_u16(a) } +pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { + vmla_s32(a, b, vdup_n_s32(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uaddlp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34286,26 +29234,18 @@ pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uaddlp.v1i64.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v1i64.v2i32")] - fn _vpaddl_u32(a: uint32x2_t) -> uint64x1_t; - } - unsafe { _vpaddl_u32(a) } +pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { + vmlaq_s32(a, b, vdupq_n_s32(c)) } -#[doc = "Unsigned Add and Accumulate Long Pairwise."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uaddlp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34315,26 +29255,18 @@ pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uaddlp.v2i64.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i64.v4i32")] - fn _vpaddlq_u32(a: uint32x4_t) -> uint64x2_t; - } - unsafe { _vpaddlq_u32(a) } +pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { + vmla_u32(a, b, vdup_n_u32(c)) } -#[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"] -#[inline(always)] +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fmaxp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34344,26 +29276,18 @@ pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxp.v2f32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")] - fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vpmax_f32(a, b) } +pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { + vmlaq_u32(a, b, vdupq_n_u32(c)) } -#[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smaxp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34373,26 +29297,18 @@ pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxp.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")] - fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vpmax_s8(a, b) } +pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smaxp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34402,26 +29318,18 @@ pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxp.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")] - fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vpmax_s16(a, b) } +pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(smaxp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34431,26 +29339,18 @@ pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxp.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")] - fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vpmax_s32(a, b) } +pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umaxp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34460,26 +29360,18 @@ pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxp.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")] - fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } - unsafe { _vpmax_u8(a, b) } +pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umaxp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34489,26 +29381,18 @@ pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxp.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")] - fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } - unsafe { _vpmax_u16(a, b) } +pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding maximum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(umaxp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34518,26 +29402,18 @@ pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxp.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")] - fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } - unsafe { _vpmax_u32(a, b) } +pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fminp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34547,26 +29423,18 @@ pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminp.v2f32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")] - fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vpmin_f32(a, b) } +pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sminp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34576,26 +29444,18 @@ pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminp.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")] - fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vpmin_s8(a, b) } +pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sminp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34605,26 +29465,18 @@ pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminp.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")] - fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vpmin_s16(a, b) } +pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sminp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34632,28 +29484,20 @@ pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] #[cfg_attr( target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminp.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")] - fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vpmin_s32(a, b) } + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uminp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34663,26 +29507,18 @@ pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminp.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")] - fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } - unsafe { _vpmin_u8(a, b) } +pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"] -#[inline(always)] +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uminp) + assert_instr(mla) )] #[cfg_attr( not(target_arch = "arm"), @@ -34692,27 +29528,20 @@ pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminp.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")] - fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } - unsafe { _vpmin_u16(a, b) } +pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } -#[doc = "Folding minimum of adjacent pairs"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uminp) + assert_instr(smlal, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34721,27 +29550,21 @@ pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminp.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")] - fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } - unsafe { _vpmin_u32(a, b) } +pub fn vmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_s16(a, b, vdup_lane_s16::(c)) } -#[doc = "Signed saturating Absolute value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqabs) + assert_instr(smlal, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34750,27 +29573,21 @@ pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqabs_s8(a: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqabs.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")] - fn _vqabs_s8(a: int8x8_t) -> int8x8_t; - } - unsafe { _vqabs_s8(a) } +pub fn vmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlal_s16(a, b, vdup_laneq_s16::(c)) } -#[doc = "Signed saturating Absolute value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqabs) + assert_instr(smlal, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34779,27 +29596,21 @@ pub fn vqabs_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqabs.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")] - fn _vqabsq_s8(a: int8x16_t) -> int8x16_t; - } - unsafe { _vqabsq_s8(a) } +pub fn vmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlal_s32(a, b, vdup_lane_s32::(c)) } -#[doc = "Signed saturating Absolute value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqabs) + assert_instr(smlal, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34808,27 +29619,21 @@ pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqabs_s16(a: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqabs.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")] - fn _vqabs_s16(a: int16x4_t) -> int16x4_t; - } - unsafe { _vqabs_s16(a) } +pub fn vmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_s32(a, b, vdup_laneq_s32::(c)) } -#[doc = "Signed saturating Absolute value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqabs) + assert_instr(umlal, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34837,27 +29642,21 @@ pub fn vqabs_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqabs.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")] - fn _vqabsq_s16(a: int16x8_t) -> int16x8_t; - } - unsafe { _vqabsq_s16(a) } +pub fn vmlal_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_u16(a, b, vdup_lane_u16::(c)) } -#[doc = "Signed saturating Absolute value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqabs) + assert_instr(umlal, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34866,27 +29665,21 @@ pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqabs_s32(a: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqabs.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")] - fn _vqabs_s32(a: int32x2_t) -> int32x2_t; - } - unsafe { _vqabs_s32(a) } +pub fn vmlal_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlal_u16(a, b, vdup_laneq_u16::(c)) } -#[doc = "Signed saturating Absolute value"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqabs) + assert_instr(umlal, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34895,27 +29688,21 @@ pub fn vqabs_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqabs.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")] - fn _vqabsq_s32(a: int32x4_t) -> int32x4_t; - } - unsafe { _vqabsq_s32(a) } +pub fn vmlal_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlal_u32(a, b, vdup_lane_u32::(c)) } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqadd) + assert_instr(umlal, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -34924,18 +29711,19 @@ pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_u32(a, b, vdup_laneq_u32::(c)) } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqadd) + assert_instr(smlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -34945,18 +29733,18 @@ pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { + vmlal_s16(a, b, vdup_n_s16(c)) } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqadd) + assert_instr(smlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -34966,18 +29754,18 @@ pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { + vmlal_s32(a, b, vdup_n_s32(c)) } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqadd) + assert_instr(umlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -34987,18 +29775,18 @@ pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { + vmlal_u16(a, b, vdup_n_u16(c)) } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"] -#[inline(always)] +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqadd) + assert_instr(umlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -35008,18 +29796,18 @@ pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { + vmlal_u32(a, b, vdup_n_u32(c)) } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"] -#[inline(always)] +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqadd) + assert_instr(smlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -35029,18 +29817,18 @@ pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { + unsafe { simd_add(a, vmull_s8(b, c)) } } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"] -#[inline(always)] +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqadd) + assert_instr(smlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -35050,18 +29838,18 @@ pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + unsafe { simd_add(a, vmull_s16(b, c)) } } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"] -#[inline(always)] +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqadd) + assert_instr(smlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -35071,18 +29859,18 @@ pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + unsafe { simd_add(a, vmull_s32(b, c)) } } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"] -#[inline(always)] +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqadd) + assert_instr(umlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -35092,18 +29880,18 @@ pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { + unsafe { simd_add(a, vmull_u8(b, c)) } } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"] -#[inline(always)] +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqadd) + assert_instr(umlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -35113,18 +29901,18 @@ pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + unsafe { simd_add(a, vmull_u16(b, c)) } } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"] -#[inline(always)] +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqadd) + assert_instr(umlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -35134,18 +29922,18 @@ pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + unsafe { simd_add(a, vmull_u32(b, c)) } } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"] -#[inline(always)] +#[doc = "Floating-point multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqadd) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -35155,18 +29943,18 @@ pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"] -#[inline(always)] +#[doc = "Floating-point multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqadd) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -35176,19 +29964,20 @@ pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqadd) + assert_instr(fmul, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35197,19 +29986,25 @@ pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmls_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmls_f32(a, b, vdup_lane_f32::(c)) } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqadd) + assert_instr(fmul, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35218,19 +30013,25 @@ pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmls_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmls_f32(a, b, vdup_laneq_f32::(c)) } -#[doc = "Saturating add"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqadd) + assert_instr(fmul, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35239,18 +30040,23 @@ pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { simd_saturating_add(a, b) } +pub fn vmlsq_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlsq_f32(a, b, vdupq_lane_f32::(c)) } -#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlal, N = 2) + assert_instr(fmul, LANE = 1) )] #[rustc_legacy_const_generics(3)] #[cfg_attr( @@ -35261,19 +30067,23 @@ pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - vqaddq_s32(a, vqdmull_lane_s16::(b, c)) +pub fn vmlsq_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_f32(a, b, vdupq_laneq_f32::(c)) } -#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlal, N = 1) + assert_instr(mls, LANE = 1) )] #[rustc_legacy_const_generics(3)] #[cfg_attr( @@ -35284,20 +30094,21 @@ pub fn vqdmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - vqaddq_s64(a, vqdmull_lane_s32::(b, c)) +pub fn vmls_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmls_s16(a, b, vdup_lane_s16::(c)) } -#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlal) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35306,19 +30117,21 @@ pub fn vqdmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { - vqaddq_s32(a, vqdmull_n_s16(b, c)) +pub fn vmls_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmls_u16(a, b, vdup_lane_u16::(c)) } -#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlal) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35327,19 +30140,21 @@ pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { - vqaddq_s64(a, vqdmull_n_s32(b, c)) +pub fn vmls_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmls_s16(a, b, vdup_laneq_s16::(c)) } -#[doc = "Signed saturating doubling multiply-add long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlal) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35348,19 +30163,21 @@ pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - vqaddq_s32(a, vqdmull_s16(b, c)) +pub fn vmls_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmls_u16(a, b, vdup_laneq_u16::(c)) } -#[doc = "Signed saturating doubling multiply-add long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlal) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35369,18 +30186,19 @@ pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - vqaddq_s64(a, vqdmull_s32(b, c)) +pub fn vmlsq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_s16(a, b, vdupq_lane_s16::(c)) } -#[doc = "Vector widening saturating doubling multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlsl, N = 2) + assert_instr(mls, LANE = 1) )] #[rustc_legacy_const_generics(3)] #[cfg_attr( @@ -35391,19 +30209,19 @@ pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - vqsubq_s32(a, vqdmull_lane_s16::(b, c)) +pub fn vmlsq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_u16(a, b, vdupq_lane_u16::(c)) } -#[doc = "Vector widening saturating doubling multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlsl, N = 1) + assert_instr(mls, LANE = 1) )] #[rustc_legacy_const_generics(3)] #[cfg_attr( @@ -35414,20 +30232,21 @@ pub fn vqdmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - vqsubq_s64(a, vqdmull_lane_s32::(b, c)) +pub fn vmlsq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlsq_s16(a, b, vdupq_laneq_s16::(c)) } -#[doc = "Vector widening saturating doubling multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlsl) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35436,19 +30255,21 @@ pub fn vqdmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { - vqsubq_s32(a, vqdmull_n_s16(b, c)) +pub fn vmlsq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlsq_u16(a, b, vdupq_laneq_u16::(c)) } -#[doc = "Vector widening saturating doubling multiply subtract with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlsl) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35457,19 +30278,21 @@ pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { - vqsubq_s64(a, vqdmull_n_s32(b, c)) +pub fn vmls_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmls_s32(a, b, vdup_lane_s32::(c)) } -#[doc = "Signed saturating doubling multiply-subtract long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlsl) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35478,19 +30301,21 @@ pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - vqsubq_s32(a, vqdmull_s16(b, c)) +pub fn vmls_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmls_u32(a, b, vdup_lane_u32::(c)) } -#[doc = "Signed saturating doubling multiply-subtract long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmlsl) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35499,20 +30324,21 @@ pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - vqsubq_s64(a, vqdmull_s32(b, c)) +pub fn vmls_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmls_s32(a, b, vdup_laneq_s32::(c)) } -#[doc = "Vector saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh, LANE = 0) + assert_instr(mls, LANE = 1) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35521,21 +30347,21 @@ pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } +pub fn vmls_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmls_u32(a, b, vdup_laneq_u32::(c)) } -#[doc = "Vector saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh, LANE = 0) + assert_instr(mls, LANE = 1) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35544,21 +30370,21 @@ pub fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } +pub fn vmlsq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlsq_s32(a, b, vdupq_lane_s32::(c)) } -#[doc = "Vector saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh, LANE = 0) + assert_instr(mls, LANE = 1) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35567,21 +30393,21 @@ pub fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } +pub fn vmlsq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlsq_u32(a, b, vdupq_lane_u32::(c)) } -#[doc = "Vector saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh, LANE = 0) + assert_instr(mls, LANE = 1) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35590,20 +30416,21 @@ pub fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vmlsq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } + vmlsq_s32(a, b, vdupq_laneq_s32::(c)) } -#[doc = "Vector saturating doubling multiply high with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh) + assert_instr(mls, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35612,19 +30439,19 @@ pub fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { - let b: int16x4_t = vdup_n_s16(b); - vqdmulh_s16(a, b) +pub fn vmlsq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_u32(a, b, vdupq_laneq_u32::(c)) } -#[doc = "Vector saturating doubling multiply high with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -35634,19 +30461,18 @@ pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { - let b: int16x8_t = vdupq_n_s16(b); - vqdmulhq_s16(a, b) +pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vmls_f32(a, b, vdup_n_f32(c)) } -#[doc = "Vector saturating doubling multiply high with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -35656,19 +30482,18 @@ pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { - let b: int32x2_t = vdup_n_s32(b); - vqdmulh_s32(a, b) +pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vmlsq_f32(a, b, vdupq_n_f32(c)) } -#[doc = "Vector saturating doubling multiply high with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35678,19 +30503,18 @@ pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { - let b: int32x4_t = vdupq_n_s32(b); - vqdmulhq_s32(a, b) +pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { + vmls_s16(a, b, vdup_n_s16(c)) } -#[doc = "Signed saturating doubling multiply returning high half"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35700,26 +30524,18 @@ pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqdmulh.v4i16" - )] - fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vqdmulh_s16(a, b) } +pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { + vmlsq_s16(a, b, vdupq_n_s16(c)) } -#[doc = "Signed saturating doubling multiply returning high half"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35729,26 +30545,18 @@ pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqdmulh.v8i16" - )] - fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } - unsafe { _vqdmulhq_s16(a, b) } +pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { + vmls_u16(a, b, vdup_n_u16(c)) } -#[doc = "Signed saturating doubling multiply returning high half"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35758,26 +30566,18 @@ pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqdmulh.v2i32" - )] - fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vqdmulh_s32(a, b) } +pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { + vmlsq_u16(a, b, vdupq_n_u16(c)) } -#[doc = "Signed saturating doubling multiply returning high half"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmulh) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35787,28 +30587,19 @@ pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqdmulh.v4i32" - )] - fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vqdmulhq_s32(a, b) } +pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { + vmls_s32(a, b, vdup_n_s32(c)) } -#[doc = "Vector saturating doubling long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmull, N = 2) + assert_instr(mls) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35817,24 +30608,19 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [N as u32; 4]); - vqdmull_s16(a, b) - } +pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { + vmlsq_s32(a, b, vdupq_n_s32(c)) } -#[doc = "Vector saturating doubling long multiply by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmull, N = 1) + assert_instr(mls) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -35843,22 +30629,18 @@ pub fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [N as u32; 2]); - vqdmull_s32(a, b) - } +pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { + vmls_u32(a, b, vdup_n_u32(c)) } -#[doc = "Vector saturating doubling long multiply with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"] -#[inline(always)] +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmull) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35868,18 +30650,18 @@ pub fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { - vqdmull_s16(a, vdup_n_s16(b)) +pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { + vmlsq_u32(a, b, vdupq_n_u32(c)) } -#[doc = "Vector saturating doubling long multiply with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmull) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35889,18 +30671,18 @@ pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { - vqdmull_s32(a, vdup_n_s32(b)) +pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating doubling multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmull) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35910,26 +30692,18 @@ pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqdmull.v4i32" - )] - fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; - } - unsafe { _vqdmull_s16(a, b) } +pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating doubling multiply long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqdmull) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35939,26 +30713,18 @@ pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqdmull.v2i64" - )] - fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; - } - unsafe { _vqdmull_s32(a, b) } +pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating extract narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqxtn) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35968,26 +30734,18 @@ pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqxtn.v8i8" - )] - fn _vqmovn_s16(a: int16x8_t) -> int8x8_t; - } - unsafe { _vqmovn_s16(a) } +pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating extract narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqxtn) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -35997,26 +30755,18 @@ pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqxtn.v4i16" - )] - fn _vqmovn_s32(a: int32x4_t) -> int16x4_t; - } - unsafe { _vqmovn_s32(a) } +pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating extract narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqxtn) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -36026,26 +30776,18 @@ pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqxtn.v2i32" - )] - fn _vqmovn_s64(a: int64x2_t) -> int32x2_t; - } - unsafe { _vqmovn_s64(a) } +pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Unsigned saturating extract narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqxtn) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -36055,26 +30797,18 @@ pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqxtn.v8i8" - )] - fn _vqmovn_u16(a: uint16x8_t) -> uint8x8_t; - } - unsafe { _vqmovn_u16(a) } +pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Unsigned saturating extract narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqxtn) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -36084,26 +30818,18 @@ pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqxtn.v4i16" - )] - fn _vqmovn_u32(a: uint32x4_t) -> uint16x4_t; - } - unsafe { _vqmovn_u32(a) } +pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Unsigned saturating extract narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqxtn) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -36113,26 +30839,18 @@ pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqxtn.v2i32" - )] - fn _vqmovn_u64(a: uint64x2_t) -> uint32x2_t; - } - unsafe { _vqmovn_u64(a) } +pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating extract unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqxtun) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -36142,26 +30860,18 @@ pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqxtun.v8i8" - )] - fn _vqmovun_s16(a: int16x8_t) -> uint8x8_t; - } - unsafe { _vqmovun_s16(a) } +pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating extract unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqxtun) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -36171,26 +30881,18 @@ pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqxtun.v4i16" - )] - fn _vqmovun_s32(a: int32x4_t) -> uint16x4_t; - } - unsafe { _vqmovun_s32(a) } +pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating extract unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"] -#[inline(always)] +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqxtun) + assert_instr(mls) )] #[cfg_attr( not(target_arch = "arm"), @@ -36200,27 +30902,20 @@ pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqxtun.v2i32" - )] - fn _vqmovun_s64(a: int64x2_t) -> uint32x2_t; - } - unsafe { _vqmovun_s64(a) } +pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } -#[doc = "Signed saturating negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqneg) + assert_instr(smlsl, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36229,27 +30924,21 @@ pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqneg_s8(a: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqneg.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")] - fn _vqneg_s8(a: int8x8_t) -> int8x8_t; - } - unsafe { _vqneg_s8(a) } +pub fn vmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_s16(a, b, vdup_lane_s16::(c)) } -#[doc = "Signed saturating negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqneg) + assert_instr(smlsl, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36258,27 +30947,21 @@ pub fn vqneg_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqneg.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")] - fn _vqnegq_s8(a: int8x16_t) -> int8x16_t; - } - unsafe { _vqnegq_s8(a) } +pub fn vmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlsl_s16(a, b, vdup_laneq_s16::(c)) } -#[doc = "Signed saturating negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqneg) + assert_instr(smlsl, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36287,27 +30970,21 @@ pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqneg_s16(a: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqneg.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")] - fn _vqneg_s16(a: int16x4_t) -> int16x4_t; - } - unsafe { _vqneg_s16(a) } +pub fn vmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlsl_s32(a, b, vdup_lane_s32::(c)) } -#[doc = "Signed saturating negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqneg) + assert_instr(smlsl, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36316,27 +30993,21 @@ pub fn vqneg_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqneg.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")] - fn _vqnegq_s16(a: int16x8_t) -> int16x8_t; - } - unsafe { _vqnegq_s16(a) } +pub fn vmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_s32(a, b, vdup_laneq_s32::(c)) } -#[doc = "Signed saturating negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqneg) + assert_instr(umlsl, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36345,27 +31016,21 @@ pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqneg_s32(a: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqneg.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")] - fn _vqneg_s32(a: int32x2_t) -> int32x2_t; - } - unsafe { _vqneg_s32(a) } +pub fn vmlsl_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_u16(a, b, vdup_lane_u16::(c)) } -#[doc = "Signed saturating negate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqneg) + assert_instr(umlsl, LANE = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36374,28 +31039,21 @@ pub fn vqneg_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqneg.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")] - fn _vqnegq_s32(a: int32x4_t) -> int32x4_t; - } - unsafe { _vqnegq_s32(a) } +pub fn vmlsl_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlsl_u16(a, b, vdup_laneq_u16::(c)) } -#[doc = "Vector rounding saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh, LANE = 1) + assert_instr(umlsl, LANE = 1) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36404,25 +31062,21 @@ pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: int16x4_t = - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulh_s16(a, b) - } +pub fn vmlsl_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlsl_u32(a, b, vdup_lane_u32::(c)) } -#[doc = "Vector rounding saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh, LANE = 1) + assert_instr(umlsl, LANE = 1) )] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36431,24 +31085,20 @@ pub fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); - vqrdmulh_s32(a, b) - } +pub fn vmlsl_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_u32(a, b, vdup_laneq_u32::(c)) } -#[doc = "Vector rounding saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh, LANE = 1) + assert_instr(smlsl) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36457,25 +31107,19 @@ pub fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - let b: int16x4_t = - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulh_s16(a, b) - } +pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { + vmlsl_s16(a, b, vdup_n_s16(c)) } -#[doc = "Vector rounding saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh, LANE = 1) + assert_instr(smlsl) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36484,24 +31128,19 @@ pub fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); - vqrdmulh_s32(a, b) - } +pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { + vmlsl_s32(a, b, vdup_n_s32(c)) } -#[doc = "Vector rounding saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh, LANE = 1) + assert_instr(umlsl) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36510,37 +31149,19 @@ pub fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: int16x8_t = simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmulhq_s16(a, b) - } +pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { + vmlsl_u16(a, b, vdup_n_u16(c)) } -#[doc = "Vector rounding saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"] -#[inline(always)] +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh, LANE = 1) + assert_instr(umlsl) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36549,25 +31170,19 @@ pub fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { - let b: int32x4_t = - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s32(a, b) - } +pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { + vmlsl_u32(a, b, vdup_n_u32(c)) } -#[doc = "Vector rounding saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"] -#[inline(always)] +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh, LANE = 1) + assert_instr(smlsl) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36576,37 +31191,19 @@ pub fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { - let b: int16x8_t = simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmulhq_s16(a, b) - } +pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { + unsafe { simd_sub(a, vmull_s8(b, c)) } } -#[doc = "Vector rounding saturating doubling multiply high by scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"] -#[inline(always)] +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh, LANE = 1) + assert_instr(smlsl) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -36615,23 +31212,18 @@ pub fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let b: int32x4_t = - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s32(a, b) - } +pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + unsafe { simd_sub(a, vmull_s16(b, c)) } } -#[doc = "Vector saturating rounding doubling multiply high with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"] -#[inline(always)] +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh) + assert_instr(smlsl) )] #[cfg_attr( not(target_arch = "arm"), @@ -36641,18 +31233,18 @@ pub fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { - vqrdmulh_s16(a, vdup_n_s16(b)) +pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + unsafe { simd_sub(a, vmull_s32(b, c)) } } -#[doc = "Vector saturating rounding doubling multiply high with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"] -#[inline(always)] +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh) + assert_instr(umlsl) )] #[cfg_attr( not(target_arch = "arm"), @@ -36662,18 +31254,18 @@ pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { - vqrdmulhq_s16(a, vdupq_n_s16(b)) +pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { + unsafe { simd_sub(a, vmull_u8(b, c)) } } -#[doc = "Vector saturating rounding doubling multiply high with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"] -#[inline(always)] +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh) + assert_instr(umlsl) )] #[cfg_attr( not(target_arch = "arm"), @@ -36683,18 +31275,18 @@ pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { - vqrdmulh_s32(a, vdup_n_s32(b)) +pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + unsafe { simd_sub(a, vmull_u16(b, c)) } } -#[doc = "Vector saturating rounding doubling multiply high with scalar"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"] -#[inline(always)] +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh) + assert_instr(umlsl) )] #[cfg_attr( not(target_arch = "arm"), @@ -36704,105 +31296,108 @@ pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { - vqrdmulhq_s32(a, vdupq_n_s32(b)) +pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + unsafe { simd_sub(a, vmull_u32(b, c)) } } -#[doc = "Signed saturating rounding doubling multiply returning high half"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[doc = "8-bit integer matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh) + assert_instr(smmla) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + unstable(feature = "stdarch_neon_i8mm", issue = "117223") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrdmulh.v4i16" + link_name = "llvm.aarch64.neon.smmla.v4i32.v16i8" )] - fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.smmla.v4i32.v16i8")] + fn _vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; } - unsafe { _vqrdmulh_s16(a, b) } + unsafe { _vmmlaq_s32(a, b, c) } } -#[doc = "Signed saturating rounding doubling multiply returning high half"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[doc = "8-bit integer matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh) + assert_instr(ummla) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + unstable(feature = "stdarch_neon_i8mm", issue = "117223") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrdmulh.v8i16" + link_name = "llvm.aarch64.neon.ummla.v4i32.v16i8" )] - fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.ummla.v4i32.v16i8")] + fn _vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t; } - unsafe { _vqrdmulhq_s16(a, b) } + unsafe { _vmmlaq_u32(a, b, c) } } -#[doc = "Signed saturating rounding doubling multiply returning high half"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"] -#[inline(always)] +#[doc = "Duplicate element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + assert_instr(dup) )] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmov_n_f16(a: f16) -> float16x4_t { + vdup_n_f16(a) +} +#[doc = "Duplicate element to vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup) )] -pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrdmulh.v2i32" - )] - fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vqrdmulh_s32(a, b) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmovq_n_f16(a: f16) -> float16x8_t { + vdupq_n_f16(a) } -#[doc = "Signed saturating rounding doubling multiply returning high half"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrdmulh) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -36812,26 +31407,18 @@ pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrdmulh.v4i32" - )] - fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vqrdmulhq_s32(a, b) } +pub fn vmov_n_f32(value: f32) -> float32x2_t { + vdup_n_f32(value) } -#[doc = "Signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -36841,26 +31428,18 @@ pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshl.v8i8" - )] - fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vqrshl_s8(a, b) } +pub fn vmov_n_p16(value: p16) -> poly16x4_t { + vdup_n_p16(value) } -#[doc = "Signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -36870,26 +31449,18 @@ pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshl.v16i8" - )] - fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } - unsafe { _vqrshlq_s8(a, b) } +pub fn vmov_n_p8(value: p8) -> poly8x8_t { + vdup_n_p8(value) } -#[doc = "Signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -36899,26 +31470,18 @@ pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshl.v4i16" - )] - fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vqrshl_s16(a, b) } +pub fn vmov_n_s16(value: i16) -> int16x4_t { + vdup_n_s16(value) } -#[doc = "Signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -36928,26 +31491,18 @@ pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshl.v8i16" - )] - fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } - unsafe { _vqrshlq_s16(a, b) } +pub fn vmov_n_s32(value: i32) -> int32x2_t { + vdup_n_s32(value) } -#[doc = "Signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrshl) + assert_instr(fmov) )] #[cfg_attr( not(target_arch = "arm"), @@ -36955,28 +31510,20 @@ pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] #[cfg_attr( target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshl.v2i32" - )] - fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vqrshl_s32(a, b) } + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmov_n_s64(value: i64) -> int64x1_t { + vdup_n_s64(value) } -#[doc = "Signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -36986,26 +31533,18 @@ pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshl.v4i32" - )] - fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vqrshlq_s32(a, b) } +pub fn vmov_n_s8(value: i8) -> int8x8_t { + vdup_n_s8(value) } -#[doc = "Signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37015,26 +31554,18 @@ pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshl.v1i64" - )] - fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; - } - unsafe { _vqrshl_s64(a, b) } +pub fn vmov_n_u16(value: u16) -> uint16x4_t { + vdup_n_u16(value) } -#[doc = "Signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37044,26 +31575,18 @@ pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshl.v2i64" - )] - fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; - } - unsafe { _vqrshlq_s64(a, b) } +pub fn vmov_n_u32(value: u32) -> uint32x2_t { + vdup_n_u32(value) } -#[doc = "Unsigned signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqrshl) + assert_instr(fmov) )] #[cfg_attr( not(target_arch = "arm"), @@ -37073,26 +31596,18 @@ pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshl.v8i8" - )] - fn _vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; - } - unsafe { _vqrshl_u8(a, b) } +pub fn vmov_n_u64(value: u64) -> uint64x1_t { + vdup_n_u64(value) } -#[doc = "Unsigned signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37102,26 +31617,18 @@ pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshl.v16i8" - )] - fn _vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; - } - unsafe { _vqrshlq_u8(a, b) } +pub fn vmov_n_u8(value: u8) -> uint8x8_t { + vdup_n_u8(value) } -#[doc = "Unsigned signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37131,26 +31638,18 @@ pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshl.v4i16" - )] - fn _vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; - } - unsafe { _vqrshl_u16(a, b) } +pub fn vmovq_n_f32(value: f32) -> float32x4_t { + vdupq_n_f32(value) } -#[doc = "Unsigned signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37160,26 +31659,18 @@ pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshl.v8i16" - )] - fn _vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; - } - unsafe { _vqrshlq_u16(a, b) } +pub fn vmovq_n_p16(value: p16) -> poly16x8_t { + vdupq_n_p16(value) } -#[doc = "Unsigned signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37189,26 +31680,18 @@ pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshl.v2i32" - )] - fn _vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; - } - unsafe { _vqrshl_u32(a, b) } +pub fn vmovq_n_p8(value: p8) -> poly8x16_t { + vdupq_n_p8(value) } -#[doc = "Unsigned signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37218,26 +31701,18 @@ pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshl.v4i32" - )] - fn _vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; - } - unsafe { _vqrshlq_u32(a, b) } +pub fn vmovq_n_s16(value: i16) -> int16x8_t { + vdupq_n_s16(value) } -#[doc = "Unsigned signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37247,26 +31722,18 @@ pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshl.v1i64" - )] - fn _vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; - } - unsafe { _vqrshl_u64(a, b) } +pub fn vmovq_n_s32(value: i32) -> int32x4_t { + vdupq_n_s32(value) } -#[doc = "Unsigned signed saturating rounding shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqrshl) + assert_instr(dup) )] #[cfg_attr( not(target_arch = "arm"), @@ -37276,343 +31743,61 @@ pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshl.v2i64" - )] - fn _vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; - } - unsafe { _vqrshlq_u64(a, b) } -} -#[doc = "Signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")] - fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; - } - unsafe { _vqrshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } -} -#[doc = "Signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")] - fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; - } - unsafe { _vqrshrn_n_s32(a, const { int32x4_t([-N; 4]) }) } -} -#[doc = "Signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")] - fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; - } - unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } -} -#[doc = "Signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshrn.v8i8" - )] - fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; - } - unsafe { _vqrshrn_n_s16(a, N) } -} -#[doc = "Signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshrn.v4i16" - )] - fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; - } - unsafe { _vqrshrn_n_s32(a, N) } -} -#[doc = "Signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshrn.v2i32" - )] - fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; - } - unsafe { _vqrshrn_n_s64(a, N) } -} -#[doc = "Unsigned signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")] - fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; - } - unsafe { _vqrshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) } -} -#[doc = "Unsigned signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")] - fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; - } - unsafe { _vqrshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) } -} -#[doc = "Unsigned signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")] - fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; - } - unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) } -} -#[doc = "Unsigned signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshrn.v8i8" - )] - fn _vqrshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t; - } - unsafe { _vqrshrn_n_u16(a, N) } -} -#[doc = "Unsigned signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshrn.v4i16" - )] - fn _vqrshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t; - } - unsafe { _vqrshrn_n_u32(a, N) } -} -#[doc = "Unsigned signed saturating rounded shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqrshrn.v2i32" - )] - fn _vqrshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t; - } - unsafe { _vqrshrn_n_u64(a, N) } -} -#[doc = "Signed saturating rounded shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")] - fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t; - } - unsafe { _vqrshrun_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } -} -#[doc = "Signed saturating rounded shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")] - fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t; - } - unsafe { _vqrshrun_n_s32(a, const { int32x4_t([-N; 4]) }) } -} -#[doc = "Signed saturating rounded shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")] - fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t; - } - unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } -} -#[doc = "Signed saturating rounded shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshrun.v8i8" - )] - fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t; - } - unsafe { _vqrshrun_n_s16(a, N) } +pub fn vmovq_n_s64(value: i64) -> int64x2_t { + vdupq_n_s64(value) } -#[doc = "Signed saturating rounded shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshrun.v4i16" - )] - fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t; - } - unsafe { _vqrshrun_n_s32(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmovq_n_s8(value: i8) -> int8x16_t { + vdupq_n_s8(value) } -#[doc = "Signed saturating rounded shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqrshrun.v2i32" - )] - fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t; - } - unsafe { _vqrshrun_n_s64(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmovq_n_u16(value: u16) -> uint16x8_t { + vdupq_n_u16(value) } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl, N = 2) + assert_instr(dup) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37621,21 +31806,19 @@ pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - vqshl_s8(a, vdup_n_s8(N as _)) +pub fn vmovq_n_u32(value: u32) -> uint32x4_t { + vdupq_n_u32(value) } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl, N = 2) + assert_instr(dup) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37644,21 +31827,19 @@ pub fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 3); - vqshlq_s8(a, vdupq_n_s8(N as _)) +pub fn vmovq_n_u64(value: u64) -> uint64x2_t { + vdupq_n_u64(value) } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"] -#[inline(always)] +#[doc = "Duplicate vector element to vector or scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl, N = 2) + assert_instr(dup) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37667,21 +31848,19 @@ pub fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 4); - vqshl_s16(a, vdup_n_s16(N as _)) +pub fn vmovq_n_u8(value: u8) -> uint8x16_t { + vdupq_n_u8(value) } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"] -#[inline(always)] +#[doc = "Vector long move."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl, N = 2) + assert_instr(sxtl) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37690,21 +31869,19 @@ pub fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 4); - vqshlq_s16(a, vdupq_n_s16(N as _)) +pub fn vmovl_s16(a: int16x4_t) -> int32x4_t { + unsafe { simd_cast(a) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"] -#[inline(always)] +#[doc = "Vector long move."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl, N = 2) + assert_instr(sxtl) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37713,21 +31890,19 @@ pub fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 5); - vqshl_s32(a, vdup_n_s32(N as _)) +pub fn vmovl_s32(a: int32x2_t) -> int64x2_t { + unsafe { simd_cast(a) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"] -#[inline(always)] +#[doc = "Vector long move."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl, N = 2) + assert_instr(sxtl) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37736,21 +31911,19 @@ pub fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 5); - vqshlq_s32(a, vdupq_n_s32(N as _)) +pub fn vmovl_s8(a: int8x8_t) -> int16x8_t { + unsafe { simd_cast(a) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"] -#[inline(always)] +#[doc = "Vector long move."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl, N = 2) + assert_instr(uxtl) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37759,21 +31932,19 @@ pub fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { - static_assert_uimm_bits!(N, 6); - vqshl_s64(a, vdup_n_s64(N as _)) +pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t { + unsafe { simd_cast(a) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"] -#[inline(always)] +#[doc = "Vector long move."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl, N = 2) + assert_instr(uxtl) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37782,21 +31953,19 @@ pub fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 6); - vqshlq_s64(a, vdupq_n_s64(N as _)) +pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t { + unsafe { simd_cast(a) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"] -#[inline(always)] +#[doc = "Vector long move."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl, N = 2) + assert_instr(uxtl) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37805,21 +31974,19 @@ pub fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - vqshl_u8(a, vdup_n_s8(N as _)) +pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t { + unsafe { simd_cast(a) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"] -#[inline(always)] +#[doc = "Vector narrow integer."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl, N = 2) + assert_instr(xtn) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37828,21 +31995,19 @@ pub fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - vqshlq_u8(a, vdupq_n_s8(N as _)) +pub fn vmovn_s16(a: int16x8_t) -> int8x8_t { + unsafe { simd_cast(a) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"] -#[inline(always)] +#[doc = "Vector narrow integer."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl, N = 2) + assert_instr(xtn) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37851,21 +32016,19 @@ pub fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - vqshl_u16(a, vdup_n_s16(N as _)) +pub fn vmovn_s32(a: int32x4_t) -> int16x4_t { + unsafe { simd_cast(a) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"] -#[inline(always)] +#[doc = "Vector narrow integer."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl, N = 2) + assert_instr(xtn) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37874,21 +32037,19 @@ pub fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - vqshlq_u16(a, vdupq_n_s16(N as _)) +pub fn vmovn_s64(a: int64x2_t) -> int32x2_t { + unsafe { simd_cast(a) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"] -#[inline(always)] +#[doc = "Vector narrow integer."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl, N = 2) + assert_instr(xtn) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37897,21 +32058,19 @@ pub fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 5); - vqshl_u32(a, vdup_n_s32(N as _)) +pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t { + unsafe { simd_cast(a) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"] -#[inline(always)] +#[doc = "Vector narrow integer."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl, N = 2) + assert_instr(xtn) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37920,21 +32079,19 @@ pub fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 5); - vqshlq_u32(a, vdupq_n_s32(N as _)) +pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t { + unsafe { simd_cast(a) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"] -#[inline(always)] +#[doc = "Vector narrow integer."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl, N = 2) + assert_instr(xtn) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37943,21 +32100,63 @@ pub fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 6); - vqshl_u64(a, vdup_n_s64(N as _)) +pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { + unsafe { simd_cast(a) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_mul(a, b) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_mul(a, b) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl, N = 2) + assert_instr(fmul) )] -#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -37966,19 +32165,18 @@ pub fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 6); - vqshlq_u64(a, vdupq_n_s64(N as _)) +pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_mul(a, b) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl) + assert_instr(fmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -37988,27 +32186,68 @@ pub fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshl.v8i8" - )] - fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vqshl_s8(a, b) } +pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_mul(a, b) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdup_lane_f16::(v)) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmulq_lane_f16(a: float16x8_t, v: float16x4_t) -> float16x8_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdupq_lane_f16::(v)) } +} +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl) + assert_instr(fmul, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38017,27 +32256,21 @@ pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshl.v16i8" - )] - fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } - unsafe { _vqshlq_s8(a, b) } +pub fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_mul(a, vdup_lane_f32::(b)) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"] -#[inline(always)] +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl) + assert_instr(fmul, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38046,27 +32279,21 @@ pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshl.v4i16" - )] - fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } - unsafe { _vqshl_s16(a, b) } +pub fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdup_laneq_f32::(b)) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"] -#[inline(always)] +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl) + assert_instr(fmul, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38075,27 +32302,21 @@ pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshl.v8i16" - )] - fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } - unsafe { _vqshlq_s16(a, b) } +pub fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_mul(a, vdupq_lane_f32::(b)) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"] -#[inline(always)] +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl) + assert_instr(fmul, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38104,27 +32325,21 @@ pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshl.v2i32" - )] - fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } - unsafe { _vqshl_s32(a, b) } +pub fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdupq_laneq_f32::(b)) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38133,27 +32348,21 @@ pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshl.v4i32" - )] - fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } - unsafe { _vqshlq_s32(a, b) } +pub fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdup_lane_s16::(b)) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38162,27 +32371,44 @@ pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshl.v1i64" - )] - fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; - } - unsafe { _vqshl_s64(a, b) } +pub fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdupq_lane_s16::(b)) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_mul(a, vdup_lane_s32::(b)) } } -#[doc = "Signed saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38191,27 +32417,21 @@ pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshl.v2i64" - )] - fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; - } - unsafe { _vqshlq_s64(a, b) } +pub fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_mul(a, vdupq_lane_s32::(b)) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38220,27 +32440,21 @@ pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshl.v8i8" - )] - fn _vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; - } - unsafe { _vqshl_u8(a, b) } +pub fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdup_lane_u16::(b)) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38249,27 +32463,21 @@ pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshl.v16i8" - )] - fn _vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; - } - unsafe { _vqshlq_u8(a, b) } +pub fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdupq_lane_u16::(b)) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38278,27 +32486,21 @@ pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshl.v4i16" - )] - fn _vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; - } - unsafe { _vqshl_u16(a, b) } +pub fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_mul(a, vdup_lane_u32::(b)) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38307,27 +32509,21 @@ pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshl.v8i16" - )] - fn _vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; - } - unsafe { _vqshlq_u16(a, b) } +pub fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_mul(a, vdupq_lane_u32::(b)) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38336,27 +32532,21 @@ pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshl.v2i32" - )] - fn _vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; - } - unsafe { _vqshl_u32(a, b) } +pub fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_mul(a, vdup_laneq_s16::(b)) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38365,27 +32555,21 @@ pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshl.v4i32" - )] - fn _vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; - } - unsafe { _vqshlq_u32(a, b) } +pub fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_mul(a, vdupq_laneq_s16::(b)) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38394,27 +32578,21 @@ pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshl.v1i64" - )] - fn _vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; - } - unsafe { _vqshl_u64(a, b) } +pub fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdup_laneq_s32::(b)) } } -#[doc = "Unsigned saturating shift left"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqshl) + assert_instr(mul, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -38423,621 +32601,380 @@ pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshl.v2i64" - )] - fn _vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; - } - unsafe { _vqshlq_u64(a, b) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")] - fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t; - } - unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")] - fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t; - } - unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")] - fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t; - } - unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")] - fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t; - } - unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 5); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")] - fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t; - } - unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 5); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")] - fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t; - } - unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 6); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")] - fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t; - } - unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 6); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")] - fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t; - } - unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshlu.v8i8" - )] - fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t; - } - unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshlu.v16i8" - )] - fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t; - } - unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshlu.v4i16" - )] - fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t; - } - unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshlu.v8i16" - )] - fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t; - } - unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 5); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshlu.v2i32" - )] - fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t; - } - unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 5); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshlu.v4i32" - )] - fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t; - } - unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) } -} -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 6); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshlu.v1i64" - )] - fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t; - } - unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) } +pub fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdupq_laneq_s32::(b)) } } -#[doc = "Signed saturating shift left unsigned"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 6); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshlu.v2i64" - )] - fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t; - } - unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) } -} -#[doc = "Signed saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")] - fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; - } - unsafe { _vqshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } -} -#[doc = "Signed saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")] - fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; - } - unsafe { _vqshrn_n_s32(a, const { int32x4_t([-N; 4]) }) } -} -#[doc = "Signed saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")] - fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; - } - unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_mul(a, vdup_laneq_u16::(b)) } } -#[doc = "Signed saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshrn.v8i8" - )] - fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; - } - unsafe { _vqshrn_n_s16(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_mul(a, vdupq_laneq_u16::(b)) } } -#[doc = "Signed saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshrn.v4i16" - )] - fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; - } - unsafe { _vqshrn_n_s32(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdup_laneq_u32::(b)) } } -#[doc = "Signed saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshrn.v2i32" - )] - fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; - } - unsafe { _vqshrn_n_s64(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_mul(a, vdupq_laneq_u32::(b)) } } -#[doc = "Unsigned saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")] - fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; - } - unsafe { _vqshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) } +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t { + unsafe { simd_mul(a, vdup_n_f16(b)) } } -#[doc = "Unsigned saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")] - fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; - } - unsafe { _vqshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) } +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { + unsafe { simd_mul(a, vdupq_n_f16(b)) } } -#[doc = "Unsigned saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")] - fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; - } - unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) } +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { + unsafe { simd_mul(a, vdup_n_f32(b)) } } -#[doc = "Unsigned saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] -#[inline(always)] +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshrn.v8i8" - )] - fn _vqshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t; - } - unsafe { _vqshrn_n_u16(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { + unsafe { simd_mul(a, vdupq_n_f32(b)) } } -#[doc = "Unsigned saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] -#[inline(always)] +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshrn.v4i16" - )] - fn _vqshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t; - } - unsafe { _vqshrn_n_u32(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { + unsafe { simd_mul(a, vdup_n_s16(b)) } } -#[doc = "Unsigned saturating shift right narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] -#[inline(always)] +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uqshrn.v2i32" - )] - fn _vqshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t; - } - unsafe { _vqshrn_n_u64(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { + unsafe { simd_mul(a, vdupq_n_s16(b)) } } -#[doc = "Signed saturating shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")] - fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t; - } - unsafe { _vqshrun_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { + unsafe { simd_mul(a, vdup_n_s32(b)) } } -#[doc = "Signed saturating shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")] - fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t; - } - unsafe { _vqshrun_n_s32(a, const { int32x4_t([-N; 4]) }) } +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { + unsafe { simd_mul(a, vdupq_n_s32(b)) } } -#[doc = "Signed saturating shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")] - fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t; - } - unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { + unsafe { simd_mul(a, vdup_n_u16(b)) } } -#[doc = "Signed saturating shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] -#[inline(always)] +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshrun.v8i8" - )] - fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t; - } - unsafe { _vqshrun_n_s16(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { + unsafe { simd_mul(a, vdupq_n_u16(b)) } } -#[doc = "Signed saturating shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] -#[inline(always)] +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshrun.v4i16" - )] - fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t; - } - unsafe { _vqshrun_n_s32(a, N) } +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { + unsafe { simd_mul(a, vdup_n_u32(b)) } } -#[doc = "Signed saturating shift right unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] -#[inline(always)] +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { + unsafe { simd_mul(a, vdupq_n_u32(b)) } +} +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(pmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")] #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sqshrun.v2i32" + link_name = "llvm.aarch64.neon.pmul.v8i8" )] - fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t; + fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t; } - unsafe { _vqshrun_n_s64(a, N) } + unsafe { _vmul_p8(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"] -#[inline(always)] +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqsub) + assert_instr(pmul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39047,18 +32984,26 @@ pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.pmul.v16i8" + )] + fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t; + } + unsafe { _vmulq_p8(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39068,18 +33013,18 @@ pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39089,18 +33034,18 @@ pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39110,18 +33055,18 @@ pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39131,18 +33076,18 @@ pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39152,18 +33097,18 @@ pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39173,18 +33118,18 @@ pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39194,18 +33139,18 @@ pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39215,18 +33160,18 @@ pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39236,18 +33181,18 @@ pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39257,18 +33202,18 @@ pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39278,18 +33223,18 @@ pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"] -#[inline(always)] +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqsub) + assert_instr(mul) )] #[cfg_attr( not(target_arch = "arm"), @@ -39299,19 +33244,20 @@ pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_mul(a, b) } } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"] -#[inline(always)] +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqsub) + assert_instr(smull, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -39320,19 +33266,21 @@ pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmull_s16(a, vdup_lane_s16::(b)) } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"] -#[inline(always)] +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqsub) + assert_instr(smull, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -39341,19 +33289,21 @@ pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmull_s16(a, vdup_laneq_s16::(b)) } -#[doc = "Saturating subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"] -#[inline(always)] +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uqsub) + assert_instr(smull, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -39362,19 +33312,21 @@ pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { simd_saturating_sub(a, b) } +pub fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmull_s32(a, vdup_lane_s32::(b)) } -#[doc = "Rounding Add returning High Narrow (high half)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"] -#[inline(always)] +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn2) + assert_instr(smull, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -39383,20 +33335,21 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let x = vraddhn_s16(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmull_s32(a, vdup_laneq_s32::(b)) } -#[doc = "Rounding Add returning High Narrow (high half)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"] -#[inline(always)] +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn2) + assert_instr(umull, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -39405,20 +33358,21 @@ pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let x = vraddhn_s32(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmull_u16(a, vdup_lane_u16::(b)) } -#[doc = "Rounding Add returning High Narrow (high half)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"] -#[inline(always)] +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn2) + assert_instr(umull, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -39427,20 +33381,21 @@ pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let x = vraddhn_s64(b, c); - unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } +pub fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmull_u16(a, vdup_laneq_u16::(b)) } -#[doc = "Rounding Add returning High Narrow (high half)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"] -#[inline(always)] +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn2) + assert_instr(umull, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -39449,22 +33404,21 @@ pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - unsafe { - let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) - } +pub fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmull_u32(a, vdup_lane_u32::(b)) } -#[doc = "Rounding Add returning High Narrow (high half)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"] -#[inline(always)] +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn2) + assert_instr(umull, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -39473,21 +33427,19 @@ pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - unsafe { - let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) - } +pub fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmull_u32(a, vdup_laneq_u32::(b)) } -#[doc = "Rounding Add returning High Narrow (high half)."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"] -#[inline(always)] +#[doc = "Vector long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn2) + assert_instr(smull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39497,21 +33449,18 @@ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - unsafe { - let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3]) - } +pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { + vmull_s16(a, vdup_n_s16(b)) } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"] -#[inline(always)] +#[doc = "Vector long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(smull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39521,26 +33470,18 @@ pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.raddhn.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v8i8")] - fn _vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; - } - unsafe { _vraddhn_s16(a, b) } +pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { + vmull_s32(a, vdup_n_s32(b)) } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"] -#[inline(always)] +#[doc = "Vector long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(umull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39550,26 +33491,18 @@ pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.raddhn.v4i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v4i16")] - fn _vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; - } - unsafe { _vraddhn_s32(a, b) } +pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { + vmull_u16(a, vdup_n_u16(b)) } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"] -#[inline(always)] +#[doc = "Vector long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(umull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39579,27 +33512,18 @@ pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.raddhn.v2i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v2i32")] - fn _vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; - } - unsafe { _vraddhn_s64(a, b) } +pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { + vmull_u32(a, vdup_n_u32(b)) } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Polynomial multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(pmull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39609,19 +33533,26 @@ pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) } +pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.pmull.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i16")] + fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t; + } + unsafe { _vmull_p8(a, b) } } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(smull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39631,24 +33562,18 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(smull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39658,19 +33583,18 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) } +pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(smull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39680,24 +33604,18 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(umull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39707,19 +33625,18 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) } +pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } -#[doc = "Rounding Add returning High Narrow."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(raddhn) + assert_instr(umull) )] #[cfg_attr( not(target_arch = "arm"), @@ -39729,83 +33646,83 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } -#[doc = "Reciprocal estimate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frecpe) + assert_instr(umull) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frecpe.v4f16" - )] - fn _vrecpe_f16(a: float16x4_t) -> float16x4_t; - } - unsafe { _vrecpe_f16(a) } +pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } -#[doc = "Reciprocal estimate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frecpe) + assert_instr(mvn) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v8f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frecpe.v8f16" - )] - fn _vrecpeq_f16(a: float16x8_t) -> float16x8_t; - } - unsafe { _vrecpeq_f16(a) } +pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t { + let b = poly8x8_t::splat(255); + unsafe { simd_xor(a, b) } +} +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mvn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vmvn_s16(a: int16x4_t) -> int16x4_t { + let b = int16x4_t::splat(-1); + unsafe { simd_xor(a, b) } } -#[doc = "Reciprocal estimate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"] -#[inline(always)] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frecpe) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), @@ -39815,26 +33732,19 @@ pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frecpe.v2f32" - )] - fn _vrecpe_f32(a: float32x2_t) -> float32x2_t; - } - unsafe { _vrecpe_f32(a) } +pub fn vmvn_s32(a: int32x2_t) -> int32x2_t { + let b = int32x2_t::splat(-1); + unsafe { simd_xor(a, b) } } -#[doc = "Reciprocal estimate."] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"] -#[inline(always)] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frecpe) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), @@ -39844,26 +33754,19 @@ pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frecpe.v4f32" - )] - fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t; - } - unsafe { _vrecpeq_f32(a) } +pub fn vmvn_s8(a: int8x8_t) -> int8x8_t { + let b = int8x8_t::splat(-1); + unsafe { simd_xor(a, b) } } -#[doc = "Unsigned reciprocal estimate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"] -#[inline(always)] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urecpe) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), @@ -39873,26 +33776,19 @@ pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urecpe.v2i32" - )] - fn _vrecpe_u32(a: uint32x2_t) -> uint32x2_t; - } - unsafe { _vrecpe_u32(a) } +pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t { + let b = uint16x4_t::splat(65_535); + unsafe { simd_xor(a, b) } } -#[doc = "Unsigned reciprocal estimate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"] -#[inline(always)] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(urecpe) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), @@ -39902,86 +33798,63 @@ pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.urecpe.v4i32" - )] - fn _vrecpeq_u32(a: uint32x4_t) -> uint32x4_t; - } - unsafe { _vrecpeq_u32(a) } +pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t { + let b = uint32x2_t::splat(4_294_967_295); + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point reciprocal step"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frecps) + assert_instr(mvn) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frecps.v4f16" - )] - fn _vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; - } - unsafe { _vrecps_f16(a, b) } +pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t { + let b = uint8x8_t::splat(255); + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point reciprocal step"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frecps) + assert_instr(mvn) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v8f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frecps.v8f16" - )] - fn _vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; - } - unsafe { _vrecpsq_f16(a, b) } +pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t { + let b = poly8x16_t::splat(255); + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point reciprocal step"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"] -#[inline(always)] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frecps) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), @@ -39991,26 +33864,19 @@ pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frecps.v2f32" - )] - fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vrecps_f32(a, b) } +pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t { + let b = int16x8_t::splat(-1); + unsafe { simd_xor(a, b) } } -#[doc = "Floating-point reciprocal step"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"] -#[inline(always)] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(frecps) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), @@ -40020,128 +33886,108 @@ pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.frecps.v4f32" - )] - fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - unsafe { _vrecpsq_f32(a, b) } +pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t { + let b = int32x4_t::splat(-1); + unsafe { simd_xor(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t { + let b = int8x16_t::splat(-1); + unsafe { simd_xor(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t { + let b = uint16x8_t::splat(65_535); + unsafe { simd_xor(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t { + let b = uint32x4_t::splat(4_294_967_295); + unsafe { simd_xor(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise not."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(mvn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { + let b = uint8x16_t::splat(255); + unsafe { simd_xor(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(fneg) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0") @@ -40151,20 +33997,19 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vneg_f16(a: float16x4_t) -> float16x4_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(fneg) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0") @@ -40174,1331 +34019,1236 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vnegq_f16(a: float16x8_t) -> float16x8_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(fneg) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vneg_f32(a: float32x2_t) -> float32x2_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(fneg) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vnegq_f32(a: float32x4_t) -> float32x4_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(neg) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vneg_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(neg) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vnegq_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(neg) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vneg_s16(a: int16x4_t) -> int16x4_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(neg) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vnegq_s16(a: int16x8_t) -> int16x8_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(neg) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vneg_s32(a: int32x2_t) -> int32x2_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(neg) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vnegq_s32(a: int32x4_t) -> int32x4_t { + unsafe { simd_neg(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + let c = int16x4_t::splat(-1); + unsafe { simd_or(simd_xor(b, c), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + let c = int32x2_t::splat(-1); + unsafe { simd_or(simd_xor(b, c), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + let c = int64x1_t::splat(-1); + unsafe { simd_or(simd_xor(b, c), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + let c = int8x8_t::splat(-1); + unsafe { simd_or(simd_xor(b, c), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + let c = int16x8_t::splat(-1); + unsafe { simd_or(simd_xor(b, c), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + let c = int32x4_t::splat(-1); + unsafe { simd_or(simd_xor(b, c), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + let c = int64x2_t::splat(-1); + unsafe { simd_or(simd_xor(b, c), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + let c = int8x16_t::splat(-1); + unsafe { simd_or(simd_xor(b, c), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { - unsafe { transmute(a) } +pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + let c = int16x4_t::splat(-1); + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + let c = int32x2_t::splat(-1); + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + let c = int64x1_t::splat(-1); + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + let c = int8x8_t::splat(-1); + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + let c = int16x8_t::splat(-1); + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + let c = int32x4_t::splat(-1); + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + let c = int64x2_t::splat(-1); + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise inclusive OR NOT"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orn) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + let c = int8x16_t::splat(-1); + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(orr) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_or(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { + let x: int16x4_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadal_s8(a, b); + } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddl_s8(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { + let x: int16x8_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadalq_s8(a, b); } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddlq_s8(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { + let x: int32x2_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadal_s16(a, b); + } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddl_s16(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { + let x: int32x4_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadalq_s16(a, b); } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddlq_s16(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { + let x: int64x1_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadal_s32(a, b); + } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddl_s32(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { + let x: int64x2_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadalq_s32(a, b); } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddlq_s32(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { + let x: uint16x4_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadal_u8(a, b); + } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddl_u8(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { + let x: uint16x8_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadalq_u8(a, b); } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddlq_u8(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { + let x: uint32x2_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadal_u16(a, b); + } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddl_u16(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { + let x: uint32x4_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadalq_u16(a, b); } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddlq_u16(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { + let x: uint64x1_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadal_u32(a, b); + } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddl_u32(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uadalp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { + let x: uint64x2_t; + #[cfg(target_arch = "arm")] + { + x = priv_vpadalq_u32(a, b); } + #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] + unsafe { + x = simd_add(vpaddlq_u32(b), a); + }; + x } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] -#[inline(always)] +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(faddp) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0") @@ -41508,20 +35258,28 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v4f16" + )] + fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vpadd_f16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] -#[inline(always)] +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(faddp) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0") @@ -41531,1015 +35289,1288 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v4f16" + )] + fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = _vpadd_f16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] -#[inline(always)] +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(faddp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v2f32" + )] + fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vpadd_f32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] -#[inline(always)] +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(faddp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { +pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v2f32" + )] + fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpadd_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] -#[inline(always)] +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(addp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")] + fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vpadd_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] -#[inline(always)] +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(addp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")] + fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } unsafe { - let ret_val: float16x8_t = transmute(a); + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = _vpadd_s8(a, b); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] -#[inline(always)] +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(addp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")] + fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vpadd_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] -#[inline(always)] +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(addp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")] + fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } unsafe { - let ret_val: float16x4_t = transmute(a); + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = _vpadd_s16(a, b); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] -#[inline(always)] +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(addp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")] + fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vpadd_s32(a, b) } +} +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(addp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.addp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")] + fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = _vpadd_s32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(addp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(addp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Add pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(addp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(saddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlp.v4i16.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i16.v8i8")] + fn _vpaddl_s8(a: int8x8_t) -> int16x4_t; + } + unsafe { _vpaddl_s8(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(saddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlp.v8i16.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v8i16.v16i8")] + fn _vpaddlq_s8(a: int8x16_t) -> int16x8_t; } + unsafe { _vpaddlq_s8(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(saddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlp.v2i32.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i32.v4i16")] + fn _vpaddl_s16(a: int16x4_t) -> int32x2_t; + } + unsafe { _vpaddl_s16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(saddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlp.v4i32.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i32.v8i16")] + fn _vpaddlq_s16(a: int16x8_t) -> int32x4_t; } + unsafe { _vpaddlq_s16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(saddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlp.v1i64.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v1i64.v2i32")] + fn _vpaddl_s32(a: int32x2_t) -> int64x1_t; + } + unsafe { _vpaddl_s32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(saddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlp.v2i64.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i64.v4i32")] + fn _vpaddlq_s32(a: int32x4_t) -> int64x2_t; } + unsafe { _vpaddlq_s32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uaddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlp.v4i16.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i16.v8i8")] + fn _vpaddl_u8(a: uint8x8_t) -> uint16x4_t; + } + unsafe { _vpaddl_u8(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uaddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlp.v8i16.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v8i16.v16i8")] + fn _vpaddlq_u8(a: uint8x16_t) -> uint16x8_t; } + unsafe { _vpaddlq_u8(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uaddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlp.v2i32.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i32.v4i16")] + fn _vpaddl_u16(a: uint16x4_t) -> uint32x2_t; + } + unsafe { _vpaddl_u16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uaddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlp.v4i32.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i32.v8i16")] + fn _vpaddlq_u16(a: uint16x8_t) -> uint32x4_t; } + unsafe { _vpaddlq_u16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uaddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlp.v1i64.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v1i64.v2i32")] + fn _vpaddl_u32(a: uint32x2_t) -> uint64x1_t; + } + unsafe { _vpaddl_u32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned Add and Accumulate Long Pairwise."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uaddlp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlp.v2i64.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i64.v4i32")] + fn _vpaddlq_u32(a: uint32x4_t) -> uint64x2_t; } + unsafe { _vpaddlq_u32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(fmaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v2f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")] + fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vpmax_f32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(fmaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxp.v2f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")] + fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpmax_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(smaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")] + fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vpmax_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(smaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")] + fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = _vpmax_s8(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(smaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")] + fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vpmax_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(smaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")] + fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = _vpmax_s16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(smaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")] + fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vpmax_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(smaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { +pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smaxp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")] + fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } unsafe { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = _vpmax_s32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(umaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { - unsafe { transmute(a) } +pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")] + fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { _vpmax_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(umaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { - let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")] + fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = _vpmax_u8(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(umaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { - unsafe { transmute(a) } +pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")] + fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { _vpmax_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(umaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")] + fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = _vpmax_u16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(umaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")] + fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { _vpmax_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] -#[inline(always)] +#[doc = "Folding maximum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(umaxp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { - let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umaxp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")] + fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } unsafe { - let ret_val: poly64x2_t = transmute(a); + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = _vpmax_u32(a, b); simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(fminp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { - unsafe { transmute(a) } +pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v2f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")] + fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vpmin_f32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(fminp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { +pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminp.v2f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")] + fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } unsafe { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = _vpmin_f32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sminp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { - unsafe { transmute(a) } +pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")] + fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vpmin_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sminp) )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")] + fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } unsafe { - let ret_val: float16x8_t = transmute(a); + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = _vpmin_s8(a, b); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42549,19 +36580,27 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { - unsafe { transmute(a) } +pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")] + fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vpmin_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42571,22 +36610,32 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { +pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")] + fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } unsafe { - let ret_val: float32x4_t = transmute(a); + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = _vpmin_s16(a, b); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42596,19 +36645,27 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")] + fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vpmin_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42618,23 +36675,32 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sminp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")] + fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = _vpmin_s32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42644,19 +36710,27 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")] + fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } + unsafe { _vpmin_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42666,23 +36740,32 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")] + fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + } unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = _vpmin_u8(a, b); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42692,19 +36775,27 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")] + fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } + unsafe { _vpmin_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42714,23 +36805,32 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")] + fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + } unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = _vpmin_u16(a, b); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42740,42 +36840,27 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")] + fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { _vpmin_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] -#[inline(always)] +#[doc = "Folding minimum of adjacent pairs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } -} -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uminp) )] #[cfg_attr( not(target_arch = "arm"), @@ -42785,19 +36870,31 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uminp.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")] + fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + } + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = _vpmin_u32(a, b); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqabs) )] #[cfg_attr( not(target_arch = "arm"), @@ -42807,23 +36904,26 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqabs_s8(a: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")] + fn _vqabs_s8(a: int8x8_t) -> int8x8_t; } + unsafe { _vqabs_s8(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqabs) )] #[cfg_attr( not(target_arch = "arm"), @@ -42833,19 +36933,26 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")] + fn _vqabsq_s8(a: int8x16_t) -> int8x16_t; + } + unsafe { _vqabsq_s8(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqabs) )] #[cfg_attr( not(target_arch = "arm"), @@ -42855,23 +36962,26 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqabs_s16(a: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")] + fn _vqabs_s16(a: int16x4_t) -> int16x4_t; } + unsafe { _vqabs_s16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqabs) )] #[cfg_attr( not(target_arch = "arm"), @@ -42881,19 +36991,26 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")] + fn _vqabsq_s16(a: int16x8_t) -> int16x8_t; + } + unsafe { _vqabsq_s16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqabs) )] #[cfg_attr( not(target_arch = "arm"), @@ -42903,23 +37020,26 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vqabs_s32(a: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")] + fn _vqabs_s32(a: int32x2_t) -> int32x2_t; } + unsafe { _vqabs_s32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqabs) )] #[cfg_attr( not(target_arch = "arm"), @@ -42929,19 +37049,26 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")] + fn _vqabsq_s32(a: int32x4_t) -> int32x4_t; + } + unsafe { _vqabsq_s32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -42951,20 +37078,18 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -42974,19 +37099,18 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -42996,23 +37120,18 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43022,19 +37141,18 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43044,23 +37162,18 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { - let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43070,19 +37183,18 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { - unsafe { transmute(a) } +pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43092,20 +37204,18 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43115,19 +37225,18 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43137,27 +37246,18 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43167,19 +37267,18 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43189,23 +37288,18 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43215,19 +37309,18 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43237,23 +37330,18 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43263,19 +37351,18 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43285,23 +37372,18 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqadd) )] #[cfg_attr( not(target_arch = "arm"), @@ -43311,20 +37393,24 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_saturating_add(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sqdmlal, N = 2) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43333,28 +37419,25 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqdmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + vqaddq_s32(a, vqdmull_lane_s16::(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sqdmlal, N = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43363,19 +37446,19 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vqdmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + vqaddq_s64(a, vqdmull_lane_s32::(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -43385,23 +37468,18 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { + vqaddq_s32(a, vqdmull_n_s16(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -43411,19 +37489,18 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { + vqaddq_s64(a, vqdmull_n_s32(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -43433,23 +37510,18 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + vqaddq_s32(a, vqdmull_s16(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmlal) )] #[cfg_attr( not(target_arch = "arm"), @@ -43459,20 +37531,24 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + vqaddq_s64(a, vqdmull_s32(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sqdmlsl, N = 2) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43481,24 +37557,25 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqdmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + vqsubq_s32(a, vqdmull_lane_s16::(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sqdmlsl, N = 1) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43507,19 +37584,19 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vqdmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + vqsubq_s64(a, vqdmull_lane_s32::(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmlsl) )] #[cfg_attr( not(target_arch = "arm"), @@ -43529,27 +37606,18 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { + vqsubq_s32(a, vqdmull_n_s16(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmlsl) )] #[cfg_attr( not(target_arch = "arm"), @@ -43559,19 +37627,18 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { + vqsubq_s64(a, vqdmull_n_s32(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmlsl) )] #[cfg_attr( not(target_arch = "arm"), @@ -43581,23 +37648,18 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { - let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + vqsubq_s32(a, vqdmull_s16(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmlsl) )] #[cfg_attr( not(target_arch = "arm"), @@ -43607,20 +37669,20 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + vqsubq_s64(a, vqdmull_s32(b, c)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43629,24 +37691,21 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + vqdmulh_s16(a, vdup_n_s16(vgetq_lane_s16::(b))) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43655,20 +37714,21 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + vqdmulhq_s16(a, vdupq_n_s16(vgetq_lane_s16::(b))) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43677,24 +37737,21 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + vqdmulh_s32(a, vdup_n_s32(vgetq_lane_s32::(b))) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43703,19 +37760,19 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vqdmulhq_s32(a, vdupq_n_s32(vgetq_lane_s32::(b))) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector saturating doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -43725,23 +37782,19 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { + let b: int16x4_t = vdup_n_s16(b); + vqdmulh_s16(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector saturating doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -43751,19 +37804,19 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { + let b: int16x8_t = vdupq_n_s16(b); + vqdmulhq_s16(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector saturating doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -43773,20 +37826,19 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { + let b: int32x2_t = vdup_n_s32(b); + vqdmulh_s32(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector saturating doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -43796,19 +37848,19 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { + let b: int32x4_t = vdupq_n_s32(b); + vqdmulhq_s32(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -43818,23 +37870,26 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulh.v4i16" + )] + fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } + unsafe { _vqdmulh_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -43844,19 +37899,26 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulh.v8i16" + )] + fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { _vqdmulhq_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -43866,23 +37928,26 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulh.v2i32" + )] + fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } + unsafe { _vqdmulh_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -43892,20 +37957,28 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulh.v4i32" + )] + fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { _vqdmulhq_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector saturating doubling long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmull, N = 2) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43914,24 +37987,22 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + let b = vdup_lane_s16::(b); + vqdmull_s16(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector saturating doubling long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmull, N = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -43940,19 +38011,20 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + let b = vdup_lane_s32::(b); + vqdmull_s32(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector saturating doubling long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmull) )] #[cfg_attr( not(target_arch = "arm"), @@ -43962,20 +38034,18 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { + vqdmull_s16(a, vdup_n_s16(b)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector saturating doubling long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmull) )] #[cfg_attr( not(target_arch = "arm"), @@ -43985,19 +38055,18 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { + vqdmull_s32(a, vdup_n_s32(b)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmull) )] #[cfg_attr( not(target_arch = "arm"), @@ -44007,23 +38076,26 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmull.v4i32" + )] + fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; } + unsafe { _vqdmull_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqdmull) )] #[cfg_attr( not(target_arch = "arm"), @@ -44033,19 +38105,26 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmull.v2i64" + )] + fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; + } + unsafe { _vqdmull_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqxtn) )] #[cfg_attr( not(target_arch = "arm"), @@ -44055,23 +38134,26 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtn.v8i8" + )] + fn _vqmovn_s16(a: int16x8_t) -> int8x8_t; } + unsafe { _vqmovn_s16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqxtn) )] #[cfg_attr( not(target_arch = "arm"), @@ -44081,19 +38163,26 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { - unsafe { transmute(a) } +pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtn.v4i16" + )] + fn _vqmovn_s32(a: int32x4_t) -> int16x4_t; + } + unsafe { _vqmovn_s32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqxtn) )] #[cfg_attr( not(target_arch = "arm"), @@ -44103,24 +38192,26 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtn.v2i32" + )] + fn _vqmovn_s64(a: int64x2_t) -> int32x2_t; } + unsafe { _vqmovn_s64(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqxtn) )] #[cfg_attr( not(target_arch = "arm"), @@ -44130,19 +38221,26 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqxtn.v8i8" + )] + fn _vqmovn_u16(a: uint16x8_t) -> uint8x8_t; + } + unsafe { _vqmovn_u16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqxtn) )] #[cfg_attr( not(target_arch = "arm"), @@ -44152,24 +38250,26 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqxtn.v4i16" + )] + fn _vqmovn_u32(a: uint32x4_t) -> uint16x4_t; } + unsafe { _vqmovn_u32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqxtn) )] #[cfg_attr( not(target_arch = "arm"), @@ -44179,19 +38279,26 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqxtn.v2i32" + )] + fn _vqmovn_u64(a: uint64x2_t) -> uint32x2_t; + } + unsafe { _vqmovn_u64(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqxtun) )] #[cfg_attr( not(target_arch = "arm"), @@ -44201,24 +38308,26 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtun.v8i8" + )] + fn _vqmovun_s16(a: int16x8_t) -> uint8x8_t; } + unsafe { _vqmovun_s16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqxtun) )] #[cfg_attr( not(target_arch = "arm"), @@ -44228,19 +38337,26 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtun.v4i16" + )] + fn _vqmovun_s32(a: int32x4_t) -> uint16x4_t; + } + unsafe { _vqmovun_s32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqxtun) )] #[cfg_attr( not(target_arch = "arm"), @@ -44250,24 +38366,26 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtun.v2i32" + )] + fn _vqmovun_s64(a: int64x2_t) -> uint32x2_t; } + unsafe { _vqmovun_s64(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqneg) )] #[cfg_attr( not(target_arch = "arm"), @@ -44277,19 +38395,26 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vqneg_s8(a: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")] + fn _vqneg_s8(a: int8x8_t) -> int8x8_t; + } + unsafe { _vqneg_s8(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqneg) )] #[cfg_attr( not(target_arch = "arm"), @@ -44299,28 +38424,26 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")] + fn _vqnegq_s8(a: int8x16_t) -> int8x16_t; } + unsafe { _vqnegq_s8(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqneg) )] #[cfg_attr( not(target_arch = "arm"), @@ -44330,19 +38453,26 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vqneg_s16(a: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")] + fn _vqneg_s16(a: int16x4_t) -> int16x4_t; + } + unsafe { _vqneg_s16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqneg) )] #[cfg_attr( not(target_arch = "arm"), @@ -44352,24 +38482,26 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")] + fn _vqnegq_s16(a: int16x8_t) -> int16x8_t; } + unsafe { _vqnegq_s16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqneg) )] #[cfg_attr( not(target_arch = "arm"), @@ -44379,19 +38511,26 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vqneg_s32(a: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")] + fn _vqneg_s32(a: int32x2_t) -> int32x2_t; + } + unsafe { _vqneg_s32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqneg) )] #[cfg_attr( not(target_arch = "arm"), @@ -44401,25 +38540,28 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")] + fn _vqnegq_s32(a: int32x4_t) -> int32x4_t; } + unsafe { _vqnegq_s32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -44428,20 +38570,22 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + let b = vdup_lane_s16::(b); + vqrdmulh_s16(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -44450,25 +38594,22 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let b = vdup_lane_s32::(b); + vqrdmulh_s32(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -44477,20 +38618,22 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + let b = vdup_laneq_s16::(b); + vqrdmulh_s16(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -44499,29 +38642,22 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let b = vdup_laneq_s32::(b); + vqrdmulh_s32(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -44530,20 +38666,22 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + let b = vdupq_lane_s16::(b); + vqrdmulhq_s16(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -44552,25 +38690,22 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let b = vdupq_lane_s32::(b); + vqrdmulhq_s32(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -44579,20 +38714,22 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + let b = vdupq_laneq_s16::(b); + vqrdmulhq_s16(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh, LANE = 1) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -44601,23 +38738,20 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let b = vdupq_laneq_s32::(b); + vqrdmulhq_s32(a, b) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector saturating rounding doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -44627,19 +38761,18 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { + vqrdmulh_s16(a, vdup_n_s16(b)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector saturating rounding doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -44649,23 +38782,18 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { + vqrdmulhq_s16(a, vdupq_n_s16(b)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector saturating rounding doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -44675,19 +38803,18 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { + vqrdmulh_s32(a, vdup_n_s32(b)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector saturating rounding doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -44697,23 +38824,18 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { + vqrdmulhq_s32(a, vdupq_n_s32(b)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -44723,19 +38845,26 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmulh.v4i16" + )] + fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vqrdmulh_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -44745,20 +38874,26 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmulh.v8i16" + )] + fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + unsafe { _vqrdmulhq_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -44768,19 +38903,26 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmulh.v2i32" + )] + fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vqrdmulh_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrdmulh) )] #[cfg_attr( not(target_arch = "arm"), @@ -44790,23 +38932,26 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmulh.v4i32" + )] + fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } + unsafe { _vqrdmulhq_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -44816,19 +38961,26 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v8i8" + )] + fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vqrshl_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -44838,23 +38990,26 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v16i8" + )] + fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } + unsafe { _vqrshlq_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -44864,19 +39019,26 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v4i16" + )] + fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vqrshl_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -44886,23 +39048,26 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v8i16" + )] + fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } + unsafe { _vqrshlq_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -44912,19 +39077,26 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v2i32" + )] + fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vqrshl_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -44934,20 +39106,26 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v4i32" + )] + fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { _vqrshlq_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -44957,19 +39135,26 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v1i64" + )] + fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + unsafe { _vqrshl_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -44979,23 +39164,26 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v2i64" + )] + fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } + unsafe { _vqrshlq_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45005,19 +39193,26 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v8i8" + )] + fn _vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; + } + unsafe { _vqrshl_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45027,23 +39222,26 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v16i8" + )] + fn _vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; } + unsafe { _vqrshlq_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45053,19 +39251,26 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { - unsafe { transmute(a) } +pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v4i16" + )] + fn _vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; + } + unsafe { _vqrshl_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45075,23 +39280,26 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v8i16" + )] + fn _vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; } + unsafe { _vqrshlq_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45101,19 +39309,26 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v2i32" + )] + fn _vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; + } + unsafe { _vqrshl_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45123,27 +39338,26 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v4i32" + )] + fn _vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; } + unsafe { _vqrshlq_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45153,19 +39367,26 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v1i64" + )] + fn _vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; + } + unsafe { _vqrshl_u64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqrshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45175,24 +39396,343 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v2i64" + )] + fn _vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; } + unsafe { _vqrshlq_u64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")] + fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; + } + unsafe { _vqrshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } +} +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")] + fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; + } + unsafe { _vqrshrn_n_s32(a, const { int32x4_t([-N; 4]) }) } +} +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")] + fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; + } + unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } +} +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrn.v8i8" + )] + fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; + } + unsafe { _vqrshrn_n_s16(a, N) } +} +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrn.v4i16" + )] + fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; + } + unsafe { _vqrshrn_n_s32(a, N) } +} +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrn.v2i32" + )] + fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; + } + unsafe { _vqrshrn_n_s64(a, N) } +} +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")] + fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; + } + unsafe { _vqrshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) } +} +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")] + fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; + } + unsafe { _vqrshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) } +} +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")] + fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; + } + unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) } +} +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshrn.v8i8" + )] + fn _vqrshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t; + } + unsafe { _vqrshrn_n_u16(a, N) } +} +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshrn.v4i16" + )] + fn _vqrshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t; + } + unsafe { _vqrshrn_n_u32(a, N) } +} +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshrn.v2i32" + )] + fn _vqrshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t; + } + unsafe { _vqrshrn_n_u64(a, N) } +} +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")] + fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t; + } + unsafe { _vqrshrun_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } +} +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")] + fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t; + } + unsafe { _vqrshrun_n_s32(a, const { int32x4_t([-N; 4]) }) } +} +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")] + fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t; + } + unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } +} +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrun.v8i8" + )] + fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t; + } + unsafe { _vqrshrun_n_s16(a, N) } +} +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrun.v4i16" + )] + fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t; + } + unsafe { _vqrshrun_n_s32(a, N) } +} +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrun.v2i32" + )] + fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t; + } + unsafe { _vqrshrun_n_s64(a, N) } +} +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45201,20 +39741,21 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + vqshl_s8(a, vdup_n_s8(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45223,24 +39764,21 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + vqshlq_s8(a, vdupq_n_s8(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45249,20 +39787,21 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 4); + vqshl_s16(a, vdup_n_s16(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45271,28 +39810,21 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 4); + vqshlq_s16(a, vdupq_n_s16(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45301,20 +39833,21 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 5); + vqshl_s32(a, vdup_n_s32(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45323,24 +39856,21 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 5); + vqshlq_s32(a, vdupq_n_s32(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45349,20 +39879,21 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { + static_assert_uimm_bits!(N, 6); + vqshl_s64(a, vdup_n_s64(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45371,24 +39902,21 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 6); + vqshlq_s64(a, vdupq_n_s64(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45397,20 +39925,21 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + vqshl_u8(a, vdup_n_s8(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45419,24 +39948,21 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + vqshlq_u8(a, vdupq_n_s8(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45445,20 +39971,21 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + vqshl_u16(a, vdup_n_s16(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45467,28 +39994,21 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + vqshlq_u16(a, vdupq_n_s16(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45497,20 +40017,21 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 5); + vqshl_u32(a, vdup_n_s32(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45519,24 +40040,21 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 5); + vqshlq_u32(a, vdupq_n_s32(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45545,20 +40063,21 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 6); + vqshl_u64(a, vdup_n_s64(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl, N = 2) )] +#[rustc_legacy_const_generics(1)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -45567,23 +40086,19 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 6); + vqshlq_u64(a, vdupq_n_s64(N as _)) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45593,19 +40108,26 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v8i8" + )] + fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vqshl_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45615,23 +40137,26 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v16i8" + )] + fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } + unsafe { _vqshlq_s8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45641,19 +40166,26 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v4i16" + )] + fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + unsafe { _vqshl_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45663,23 +40195,26 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v8i16" + )] + fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } + unsafe { _vqshlq_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45689,19 +40224,26 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { - unsafe { transmute(a) } +pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v2i32" + )] + fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + unsafe { _vqshl_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45711,20 +40253,26 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v4i32" + )] + fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + unsafe { _vqshlq_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45734,19 +40282,26 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v1i64" + )] + fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + unsafe { _vqshl_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45756,23 +40311,26 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v2i64" + )] + fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } + unsafe { _vqshlq_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45782,19 +40340,26 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v8i8" + )] + fn _vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; + } + unsafe { _vqshl_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45804,23 +40369,26 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v16i8" + )] + fn _vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; } + unsafe { _vqshlq_u8(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45830,19 +40398,26 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v4i16" + )] + fn _vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; + } + unsafe { _vqshl_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45852,23 +40427,26 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v8i16" + )] + fn _vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; } + unsafe { _vqshlq_u16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45878,19 +40456,26 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v2i32" + )] + fn _vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; + } + unsafe { _vqshl_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45900,20 +40485,26 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v4i32" + )] + fn _vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; + } + unsafe { _vqshlq_u32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45923,19 +40514,26 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v1i64" + )] + fn _vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; + } + unsafe { _vqshl_u64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqshl) )] #[cfg_attr( not(target_arch = "arm"), @@ -45945,171 +40543,621 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v2i64" + )] + fn _vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; + } + unsafe { _vqshlq_u64(a, b) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")] + fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t; + } + unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")] + fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t; + } + unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")] + fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t; + } + unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")] + fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t; + } + unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 5); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")] + fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t; + } + unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 5); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")] + fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t; + } + unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 6); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")] + fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t; + } + unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 6); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")] + fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t; + } + unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v8i8" + )] + fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t; + } + unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v16i8" + )] + fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t; + } + unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v4i16" + )] + fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t; + } + unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v8i16" + )] + fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t; + } + unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 5); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v2i32" + )] + fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t; + } + unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 5); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v4i32" + )] + fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t; + } + unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 6); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v1i64" + )] + fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t; + } + unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) } +} +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 6); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v2i64" + )] + fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t; + } + unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) } +} +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")] + fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; + } + unsafe { _vqshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } +} +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")] + fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; + } + unsafe { _vqshrn_n_s32(a, const { int32x4_t([-N; 4]) }) } +} +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")] + fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; + } + unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } +} +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrn.v8i8" + )] + fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; + } + unsafe { _vqshrn_n_s16(a, N) } +} +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrn.v4i16" + )] + fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; + } + unsafe { _vqshrn_n_s32(a, N) } +} +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrn.v2i32" + )] + fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; + } + unsafe { _vqshrn_n_s64(a, N) } +} +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")] + fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; + } + unsafe { _vqshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) } +} +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")] + fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; + } + unsafe { _vqshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) } +} +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")] + fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; + } + unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) } +} +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshrn.v8i8" + )] + fn _vqshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t; + } + unsafe { _vqshrn_n_u16(a, N) } +} +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshrn.v4i16" + )] + fn _vqshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t; } + unsafe { _vqshrn_n_u32(a, N) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshrn.v2i32" + )] + fn _vqshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t; + } + unsafe { _vqshrn_n_u64(a, N) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")] + fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t; } + unsafe { _vqshrun_n_s16(a, const { int16x8_t([-N as i16; 8]) }) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { - unsafe { transmute(a) } +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")] + fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t; + } + unsafe { _vqshrun_n_s32(a, const { int32x4_t([-N; 4]) }) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")] + fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t; + } + unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64; 2]) }) } +} +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrun.v8i8" + )] + fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t; } + unsafe { _vqshrun_n_s16(a, N) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrun.v4i16" + )] + fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t; + } + unsafe { _vqshrun_n_s32(a, N) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrun.v2i32" + )] + fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t; } + unsafe { _vqshrun_n_s64(a, N) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46119,19 +41167,18 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46141,23 +41188,18 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46167,19 +41209,18 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { - unsafe { transmute(a) } +pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46189,23 +41230,18 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46215,19 +41251,18 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46237,27 +41272,18 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46267,19 +41293,18 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46289,23 +41314,18 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46315,19 +41335,18 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46337,23 +41356,18 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46363,19 +41377,18 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { - unsafe { transmute(a) } +pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46385,23 +41398,18 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46411,19 +41419,18 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46433,27 +41440,18 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46463,19 +41461,18 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(uqsub) )] #[cfg_attr( not(target_arch = "arm"), @@ -46485,23 +41482,22 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_saturating_sub(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding Add returning High Narrow (high half)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(raddhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -46511,19 +41507,23 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { - unsafe { transmute(a) } +pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { + let x = vraddhn_s16(b, c); + vcombine_s8(a, x) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding Add returning High Narrow (high half)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(raddhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -46533,22 +41533,23 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { + let x = vraddhn_s32(b, c); + vcombine_s16(a, x) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding Add returning High Narrow (high half)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(raddhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -46558,19 +41559,23 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { + let x = vraddhn_s64(b, c); + vcombine_s32(a, x) } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding Add returning High Narrow (high half)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(raddhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -46580,22 +41585,25 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { +pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c))); + vcombine_u8(a, x) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding Add returning High Narrow (high half)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(raddhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -46605,19 +41613,25 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { + unsafe { + let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c))); + vcombine_u16(a, x) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding Add returning High Narrow (high half)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(raddhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -46627,22 +41641,21 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { +pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c))); + vcombine_u32(a, x) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding Add returning High Narrow."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(raddhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -46652,19 +41665,26 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.raddhn.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v8i8")] + fn _vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; + } + unsafe { _vraddhn_s16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding Add returning High Narrow."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(raddhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -46674,22 +41694,26 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.raddhn.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v4i16")] + fn _vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; } + unsafe { _vraddhn_s32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding Add returning High Narrow."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(raddhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -46699,19 +41723,26 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.raddhn.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v2i32")] + fn _vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; + } + unsafe { _vraddhn_s64(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding Add returning High Narrow."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(raddhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -46721,22 +41752,18 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Rounding Add returning High Narrow."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(raddhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -46746,19 +41773,18 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Rounding Add returning High Narrow."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(raddhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -46768,68 +41794,78 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frecpe) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.v4f16" + )] + fn _vrecpe_f16(a: float16x4_t) -> float16x4_t; + } + unsafe { _vrecpe_f16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frecpe) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.v8f16" + )] + fn _vrecpeq_f16(a: float16x8_t) -> float16x8_t; } + unsafe { _vrecpeq_f16(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"] -#[inline(always)] +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frecpe) )] #[cfg_attr( not(target_arch = "arm"), @@ -46839,19 +41875,26 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { - unsafe { transmute(a) } +pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.v2f32" + )] + fn _vrecpe_f32(a: float32x2_t) -> float32x2_t; + } + unsafe { _vrecpe_f32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frecpe) )] #[cfg_attr( not(target_arch = "arm"), @@ -46861,19 +41904,26 @@ pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.v4f32" + )] + fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t; + } + unsafe { _vrecpeq_f32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Unsigned reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urecpe) )] #[cfg_attr( not(target_arch = "arm"), @@ -46883,22 +41933,26 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urecpe.v2i32" + )] + fn _vrecpe_u32(a: uint32x2_t) -> uint32x2_t; } + unsafe { _vrecpe_u32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Unsigned reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(urecpe) )] #[cfg_attr( not(target_arch = "arm"), @@ -46908,66 +41962,86 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urecpe.v4i32" + )] + fn _vrecpeq_u32(a: uint32x4_t) -> uint32x4_t; + } + unsafe { _vrecpeq_u32(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frecps) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.v4f16" + )] + fn _vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } + unsafe { _vrecps_f16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frecps) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { - unsafe { transmute(a) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.v8f16" + )] + fn _vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vrecpsq_f16(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frecps) )] #[cfg_attr( not(target_arch = "arm"), @@ -46977,23 +42051,26 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.v2f32" + )] + fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } + unsafe { _vrecps_f32(a, b) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(frecps) )] #[cfg_attr( not(target_arch = "arm"), @@ -47003,13 +42080,20 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.v4f32" + )] + fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vrecpsq_f32(a, b) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47019,27 +42103,19 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47049,19 +42125,19 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47071,23 +42147,19 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47097,19 +42169,19 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47119,23 +42191,19 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47145,19 +42213,19 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47167,27 +42235,19 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47197,19 +42257,19 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47219,23 +42279,19 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47245,19 +42301,19 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47267,23 +42323,19 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { + unsafe { transmute(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47293,19 +42345,19 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47315,23 +42367,19 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47341,19 +42389,19 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47363,27 +42411,19 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47393,19 +42433,19 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47415,23 +42455,19 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47441,19 +42477,19 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47463,23 +42499,19 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47489,19 +42521,19 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47511,23 +42543,19 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47537,19 +42565,19 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47559,23 +42587,19 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47585,19 +42609,19 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47607,23 +42631,19 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47633,19 +42653,19 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47655,20 +42675,19 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47678,19 +42697,19 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47700,23 +42719,19 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47726,19 +42741,19 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47748,23 +42763,19 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47774,19 +42785,19 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47796,20 +42807,19 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47819,19 +42829,19 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47841,23 +42851,19 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47867,19 +42873,19 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47889,23 +42895,19 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47915,19 +42917,19 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47937,24 +42939,19 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47964,19 +42961,19 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -47986,28 +42983,19 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48017,19 +43005,19 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48039,24 +43027,19 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48066,19 +43049,19 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48094,18 +43077,12 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48121,13 +43098,12 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { +pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48143,18 +43119,12 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48170,13 +43140,12 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { +pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48192,18 +43161,12 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48219,13 +43182,12 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { +pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48241,18 +43203,12 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48268,13 +43224,12 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { +pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48290,18 +43245,12 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48317,13 +43266,12 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { +pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48339,22 +43287,12 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48370,13 +43308,12 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { +pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48392,18 +43329,12 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48419,13 +43350,12 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { +pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48441,17 +43371,12 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48467,13 +43392,12 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { +pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48489,17 +43413,12 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48515,13 +43434,12 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { +pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48537,17 +43455,12 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48563,13 +43476,12 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { +pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48585,17 +43497,12 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48611,13 +43518,12 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { +pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48633,14 +43539,12 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48656,13 +43560,12 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { +pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48678,17 +43581,12 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48704,13 +43602,12 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { +pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48726,17 +43623,12 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48752,13 +43644,12 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { +pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48774,14 +43665,12 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48797,13 +43686,12 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { +pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48819,17 +43707,12 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48845,13 +43728,12 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { +pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48867,17 +43749,12 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48893,13 +43770,12 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { +pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48915,17 +43791,12 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48941,13 +43812,12 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { +pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48963,21 +43833,12 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -48993,13 +43854,12 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { +pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49015,17 +43875,12 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49041,15 +43896,14 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { +pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -49057,25 +43911,21 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -49083,21 +43933,21 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -49105,25 +43955,21 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -49131,21 +43977,21 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -49153,29 +43999,21 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -49183,19 +44021,19 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49211,17 +44049,12 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49237,13 +44070,12 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { +pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49259,17 +44091,12 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49285,13 +44112,12 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { +pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49307,21 +44133,12 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49337,13 +44154,12 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { +pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49359,17 +44175,12 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49385,13 +44196,12 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { +pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49407,17 +44217,12 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49433,13 +44238,12 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { +pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49455,17 +44259,12 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49481,13 +44280,12 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { +pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49503,17 +44301,12 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49529,13 +44322,12 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { +pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49551,17 +44343,12 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49577,13 +44364,12 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { +pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49599,14 +44385,12 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49622,13 +44406,12 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { +pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49644,17 +44427,12 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49670,13 +44448,12 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { +pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49692,17 +44469,12 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49718,13 +44490,12 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { +pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49740,14 +44511,12 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49763,13 +44532,12 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { +pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49785,17 +44553,12 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49811,13 +44574,12 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { +pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49833,17 +44595,12 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49859,13 +44616,12 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { +pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49881,17 +44637,12 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49907,13 +44658,12 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { +pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49929,21 +44679,12 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49959,13 +44700,12 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { +pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -49981,17 +44721,12 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50007,13 +44742,12 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { +pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50029,17 +44763,12 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50055,13 +44784,12 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { +pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50077,17 +44805,12 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50103,13 +44826,12 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { +pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50125,21 +44847,12 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50155,13 +44868,12 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { +pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50177,17 +44889,12 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50203,13 +44910,12 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { +pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50225,17 +44931,12 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50251,13 +44952,12 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { +pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50273,21 +44973,12 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50303,13 +44994,12 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { +pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50325,17 +45015,12 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50351,13 +45036,12 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { +pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50373,16 +45057,12 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50398,13 +45078,12 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { +pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50420,16 +45099,12 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50445,13 +45120,12 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { +pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50467,16 +45141,12 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50492,13 +45162,12 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { +pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50514,15 +45183,12 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50538,13 +45204,12 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { +pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50560,13 +45225,12 @@ pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { +pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50582,16 +45246,12 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50607,13 +45267,12 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { +pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50629,16 +45288,12 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50654,13 +45309,12 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { +pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50676,16 +45330,12 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50701,13 +45351,12 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { +pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50723,16 +45372,12 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50748,13 +45393,12 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { +pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50770,16 +45414,12 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50795,13 +45435,12 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { +pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50817,17 +45456,12 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50843,13 +45477,12 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { +pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50865,21 +45498,12 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50895,13 +45519,12 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { +pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50917,17 +45540,12 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50943,13 +45561,12 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { +pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50965,17 +45582,12 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -50991,13 +45603,12 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { +pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51013,17 +45624,12 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51039,13 +45645,12 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { +pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51061,21 +45666,12 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51091,13 +45687,12 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { +pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51113,17 +45708,12 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51139,13 +45729,12 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { +pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51161,17 +45750,12 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51187,13 +45771,12 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { +pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51209,21 +45792,12 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51239,13 +45813,12 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { +pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51261,17 +45834,12 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51287,13 +45855,12 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { +pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51309,17 +45876,12 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51335,13 +45897,12 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { +pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51357,17 +45918,12 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51383,13 +45939,12 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { +pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51405,17 +45960,12 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51431,13 +45981,12 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { +pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51453,17 +46002,12 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51479,13 +46023,12 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { +pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51501,14 +46044,12 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51524,13 +46065,12 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { +pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51546,17 +46086,12 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51572,13 +46107,12 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { +pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51594,17 +46128,12 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51620,13 +46149,12 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { +pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51642,17 +46170,12 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51668,13 +46191,12 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { +pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51690,14 +46212,12 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51713,13 +46233,12 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { +pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51735,17 +46254,12 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51761,13 +46275,12 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { +pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51783,18 +46296,12 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51810,13 +46317,12 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { +pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51832,22 +46338,12 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51863,13 +46359,12 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { +pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51885,18 +46380,12 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51912,13 +46401,12 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { +pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51934,18 +46422,12 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51961,13 +46443,12 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { +pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -51983,18 +46464,12 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52010,13 +46485,12 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { +pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52032,22 +46506,12 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52063,13 +46527,12 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { +pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { unsafe { transmute(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52085,18 +46548,12 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52112,13 +46569,12 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { +pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52134,18 +46590,12 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52161,13 +46611,12 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { +pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52183,18 +46632,12 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52210,13 +46653,12 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { +pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52232,18 +46674,12 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52259,13 +46695,12 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { +pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52281,17 +46716,12 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52307,13 +46737,12 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { +pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52329,17 +46758,12 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52355,13 +46779,12 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { +pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52377,17 +46800,12 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52403,13 +46821,12 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { +pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52425,17 +46842,12 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52451,13 +46863,12 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { +pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52473,14 +46884,12 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52496,13 +46905,12 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { +pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52518,17 +46926,12 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52544,13 +46947,12 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { +pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52566,17 +46968,12 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52592,13 +46989,12 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { +pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52614,17 +47010,12 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52640,13 +47031,12 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { +pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52662,14 +47052,12 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52685,13 +47073,12 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { +pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52707,17 +47094,12 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52733,13 +47115,12 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { +pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52755,17 +47136,12 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52781,13 +47157,12 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { +pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52803,21 +47178,12 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52833,13 +47199,12 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { +pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52855,17 +47220,12 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52881,13 +47241,12 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { +pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52903,17 +47262,12 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52929,13 +47283,12 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { +pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52951,17 +47304,12 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52977,13 +47325,12 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { +pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -52999,21 +47346,12 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -53029,13 +47367,12 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { +pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -53051,17 +47388,12 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -53077,13 +47409,12 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { +pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -53099,17 +47430,12 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -53125,13 +47451,12 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { +pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -53147,17 +47472,12 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -53173,13 +47493,12 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { +pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -53195,23 +47514,14 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53225,15 +47535,14 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { +pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53247,22 +47556,14 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { - unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53276,15 +47577,14 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { +pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53298,18 +47598,14 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { - unsafe { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53323,15 +47619,14 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { +pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53345,18 +47640,14 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { - unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53370,15 +47661,14 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { +pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53392,18 +47682,14 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { - unsafe { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53417,15 +47703,14 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { +pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53439,22 +47724,14 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { - unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53468,15 +47745,14 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { +pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53490,18 +47766,14 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { - unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53515,15 +47787,14 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { +pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53537,18 +47808,14 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { - unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } +pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53562,15 +47829,14 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { +pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53584,18 +47850,14 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { - unsafe { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53609,15 +47871,14 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { +pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53631,22 +47892,14 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { - unsafe { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53660,15 +47913,14 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { +pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53682,18 +47934,14 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { - unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } +pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53707,15 +47955,14 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { +pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53729,18 +47976,14 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53754,15 +47997,14 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { +pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53776,16 +48018,14 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53799,15 +48039,14 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { +pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53821,17 +48060,14 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53845,15 +48081,14 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { +pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53867,20 +48102,14 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { - let a: int8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53894,15 +48123,14 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { +pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53916,16 +48144,14 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { - let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53939,15 +48165,14 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { +pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53961,16 +48186,14 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -53984,15 +48207,14 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { +pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54006,19 +48228,14 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { - let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54032,15 +48249,14 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { +pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54054,16 +48270,14 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54077,15 +48291,14 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { +pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54099,16 +48312,14 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54122,15 +48333,14 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { +pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54144,19 +48354,14 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54170,15 +48375,14 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { +pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54192,16 +48396,14 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { - let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54215,15 +48417,14 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { +pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54237,16 +48438,14 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54260,15 +48459,14 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { +pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54282,17 +48480,14 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54306,15 +48501,14 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { +pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54328,20 +48522,14 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54355,15 +48543,14 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { +pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54377,16 +48564,14 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { - let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54400,15 +48585,14 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { +pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54422,16 +48606,14 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54445,15 +48627,14 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { +pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54467,19 +48648,14 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54493,15 +48669,14 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { +pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54515,16 +48690,14 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { - let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54538,15 +48711,14 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { +pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -54560,14 +48732,12 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54583,13 +48753,12 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { +pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54605,17 +48774,12 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54631,13 +48795,12 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { +pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54653,14 +48816,12 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54676,13 +48837,12 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { +pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54698,14 +48858,12 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54721,13 +48879,12 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { +pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54743,15 +48900,12 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54767,13 +48921,12 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { +pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54789,18 +48942,12 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } +pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] -#[inline(always)] -#[cfg(target_endian = "little")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54816,13 +48963,12 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { +pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] -#[inline(always)] -#[cfg(target_endian = "big")] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -54838,20 +48984,19 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { - let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; +pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { unsafe { transmute(a) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -54861,19 +49006,19 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { - unsafe { transmute(a) } +pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -54883,20 +49028,23 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { transmute(a) } +pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -54906,19 +49054,19 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { - unsafe { transmute(a) } +pub fn vrev16_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -54928,23 +49076,23 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { - let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vrev16_s8(a: int8x8_t) -> int8x8_t { unsafe { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -54954,19 +49102,19 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { - unsafe { transmute(a) } +pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -54976,22 +49124,23 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { +pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { unsafe { - let ret_val: int8x8_t = transmute(a); + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -55001,19 +49150,19 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { - unsafe { transmute(a) } +pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -55023,22 +49172,29 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { +pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { unsafe { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -55048,19 +49204,19 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { - unsafe { transmute(a) } +pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -55070,22 +49226,29 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { +pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t { unsafe { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = + simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -55095,19 +49258,19 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { - unsafe { transmute(a) } +pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev16) )] #[cfg_attr( not(target_arch = "arm"), @@ -55117,22 +49280,29 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { +pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { unsafe { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55142,19 +49312,19 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { - unsafe { transmute(a) } +pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55164,22 +49334,23 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { +pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { unsafe { - let ret_val: uint16x4_t = transmute(a); + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55189,19 +49360,19 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { - unsafe { transmute(a) } +pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55211,22 +49382,23 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { +pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { unsafe { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55236,19 +49408,19 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { - unsafe { transmute(a) } +pub fn vrev32_s16(a: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55258,22 +49430,23 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { +pub fn vrev32_s16(a: int16x4_t) -> int16x4_t { unsafe { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55283,19 +49456,19 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { - unsafe { transmute(a) } +pub fn vrev32_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55305,22 +49478,23 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { +pub fn vrev32_s8(a: int8x8_t) -> int8x8_t { unsafe { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55330,19 +49504,19 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { - unsafe { transmute(a) } +pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55352,20 +49526,23 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - unsafe { transmute(a) } +pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55375,19 +49552,19 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { - unsafe { transmute(a) } +pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55397,27 +49574,23 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { unsafe { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55427,19 +49600,19 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { - unsafe { transmute(a) } +pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55449,23 +49622,23 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { unsafe { - let ret_val: int16x8_t = transmute(a); + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55475,19 +49648,19 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { - unsafe { transmute(a) } +pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55497,23 +49670,29 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { unsafe { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55523,19 +49702,19 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { - unsafe { transmute(a) } +pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55545,27 +49724,23 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t { unsafe { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55575,19 +49750,19 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { - unsafe { transmute(a) } +pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55597,23 +49772,29 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t { unsafe { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = + simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55623,19 +49804,19 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { - unsafe { transmute(a) } +pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55645,23 +49826,23 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { unsafe { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55671,19 +49852,19 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { - unsafe { transmute(a) } +pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev32) )] #[cfg_attr( not(target_arch = "arm"), @@ -55693,10 +49874,12 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { unsafe { - let ret_val: poly8x16_t = transmute(a); + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]); simd_shuffle!( ret_val, ret_val, @@ -55704,16 +49887,16 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { ) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55723,19 +49906,19 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { - unsafe { transmute(a) } +pub fn vrev64_f32(a: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } -#[doc = "Vector reinterpret cast operation"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] -#[inline(always)] +#[doc = "Reversing vector elements (swap endianness)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55745,22 +49928,23 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { - let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; +pub fn vrev64_f32(a: float32x2_t) -> float32x2_t { unsafe { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: float32x2_t = simd_shuffle!(a, a, [1, 0]); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55770,18 +49954,19 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } +pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55791,18 +49976,23 @@ pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev16_s8(a: int8x8_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } +pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55812,18 +50002,19 @@ pub fn vrev16_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } +pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55833,18 +50024,23 @@ pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } +pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55854,18 +50050,19 @@ pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } +pub fn vrev64_s16(a: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev16) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55875,18 +50072,23 @@ pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } +pub fn vrev64_s16(a: int16x4_t) -> int16x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55896,18 +50098,19 @@ pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } +pub fn vrev64_s32(a: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55917,18 +50120,23 @@ pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } +pub fn vrev64_s32(a: int32x2_t) -> int32x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: int32x2_t = simd_shuffle!(a, a, [1, 0]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55938,18 +50146,19 @@ pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32_s16(a: int16x4_t) -> int16x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } +pub fn vrev64_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55959,18 +50168,23 @@ pub fn vrev32_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32_s8(a: int8x8_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } +pub fn vrev64_s8(a: int8x8_t) -> int8x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -55980,18 +50194,19 @@ pub fn vrev32_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } +pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -56001,18 +50216,23 @@ pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } +pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -56022,18 +50242,19 @@ pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } +pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -56043,18 +50264,23 @@ pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } +pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let ret_val: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -56064,18 +50290,19 @@ pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } +pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -56085,18 +50312,23 @@ pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } +pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -56106,18 +50338,19 @@ pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } +pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rev32) + assert_instr(rev64) )] #[cfg_attr( not(target_arch = "arm"), @@ -56127,15 +50360,20 @@ pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } +pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t { + unsafe { + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56148,12 +50386,13 @@ pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_f32(a: float32x2_t) -> float32x2_t { - unsafe { simd_shuffle!(a, a, [1, 0]) } +pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] @@ -56169,12 +50408,17 @@ pub fn vrev64_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } +pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] @@ -56190,15 +50434,16 @@ pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } +pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56211,15 +50456,26 @@ pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_s16(a: int16x4_t) -> int16x4_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } +pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = + simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56232,15 +50488,16 @@ pub fn vrev64_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_s32(a: int32x2_t) -> int32x2_t { - unsafe { simd_shuffle!(a, a, [1, 0]) } +pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56253,15 +50510,20 @@ pub fn vrev64_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_s8(a: int8x8_t) -> int8x8_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } +pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56274,12 +50536,13 @@ pub fn vrev64_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } +pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] @@ -56295,12 +50558,17 @@ pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { - unsafe { simd_shuffle!(a, a, [1, 0]) } +pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] @@ -56316,15 +50584,16 @@ pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } +pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56337,12 +50606,23 @@ pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } +pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = + simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] @@ -56358,15 +50638,16 @@ pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { +pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56379,15 +50660,20 @@ pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } +pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56400,12 +50686,13 @@ pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } +pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] @@ -56421,12 +50708,17 @@ pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } +pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_shuffle!(a, a, [1, 0, 3, 2]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] @@ -56442,15 +50734,16 @@ pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t { +pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } #[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) @@ -56463,54 +50756,73 @@ pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } +pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = + simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Reverse elements in 64-bit doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { - unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } -#[doc = "Reversing vector elements (swap endianness)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Reverse elements in 64-bit doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rev64) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { - unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Reverse elements in 64-bit doublewords"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] #[cfg_attr( @@ -56527,12 +50839,13 @@ pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } +pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } #[doc = "Reverse elements in 64-bit doublewords"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] #[cfg_attr( @@ -56550,11 +50863,15 @@ pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { )] #[cfg(not(target_arch = "arm64ec"))] pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t { - unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] @@ -56583,7 +50900,7 @@ pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] @@ -56612,7 +50929,7 @@ pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] @@ -56641,7 +50958,7 @@ pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] @@ -56670,7 +50987,7 @@ pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] @@ -56699,7 +51016,7 @@ pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] @@ -56728,7 +51045,7 @@ pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] @@ -56757,7 +51074,7 @@ pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] @@ -56786,7 +51103,7 @@ pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] @@ -56815,7 +51132,7 @@ pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] @@ -56844,7 +51161,7 @@ pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] @@ -56873,7 +51190,7 @@ pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] @@ -56902,7 +51219,7 @@ pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] #[cfg_attr( @@ -56931,7 +51248,7 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] #[cfg_attr( @@ -56960,7 +51277,7 @@ pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] @@ -56988,7 +51305,7 @@ pub fn vrndn_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] @@ -57016,7 +51333,7 @@ pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57045,7 +51362,7 @@ pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57074,7 +51391,7 @@ pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57103,7 +51420,7 @@ pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57132,7 +51449,7 @@ pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57161,7 +51478,7 @@ pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57190,7 +51507,7 @@ pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57219,7 +51536,7 @@ pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57248,7 +51565,7 @@ pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57277,7 +51594,7 @@ pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57306,7 +51623,7 @@ pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57335,7 +51652,7 @@ pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57364,7 +51681,7 @@ pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57393,7 +51710,7 @@ pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57422,7 +51739,7 @@ pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57451,7 +51768,7 @@ pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] @@ -57480,7 +51797,7 @@ pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57503,7 +51820,7 @@ pub fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57526,7 +51843,7 @@ pub fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57549,7 +51866,7 @@ pub fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57572,7 +51889,7 @@ pub fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57595,7 +51912,7 @@ pub fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57618,7 +51935,7 @@ pub fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57641,7 +51958,7 @@ pub fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57664,7 +51981,7 @@ pub fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57687,7 +52004,7 @@ pub fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57710,7 +52027,7 @@ pub fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57733,7 +52050,7 @@ pub fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57756,7 +52073,7 @@ pub fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57779,7 +52096,7 @@ pub fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57802,7 +52119,7 @@ pub fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57825,7 +52142,7 @@ pub fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] @@ -57848,7 +52165,7 @@ pub fn vrshrq_n_u64(a: uint64x2_t) -> uint64x2_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vrshrn, N = 2))] @@ -57864,7 +52181,7 @@ pub fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vrshrn, N = 2))] @@ -57880,7 +52197,7 @@ pub fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vrshrn, N = 2))] @@ -57896,7 +52213,7 @@ pub fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(rshrn, N = 2))] @@ -57915,7 +52232,7 @@ pub fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(rshrn, N = 2))] @@ -57934,7 +52251,7 @@ pub fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(rshrn, N = 2))] @@ -57953,7 +52270,7 @@ pub fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] @@ -57976,7 +52293,7 @@ pub fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] @@ -57999,7 +52316,7 @@ pub fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] @@ -58022,7 +52339,7 @@ pub fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] @@ -58052,7 +52369,7 @@ pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] @@ -58082,7 +52399,7 @@ pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] @@ -58111,7 +52428,7 @@ pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] @@ -58140,7 +52457,7 @@ pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { } #[doc = "Unsigned reciprocal square root estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] @@ -58169,7 +52486,7 @@ pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Unsigned reciprocal square root estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] @@ -58198,7 +52515,7 @@ pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] @@ -58228,7 +52545,7 @@ pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] @@ -58258,7 +52575,7 @@ pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] @@ -58287,7 +52604,7 @@ pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] @@ -58316,7 +52633,7 @@ pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58339,7 +52656,7 @@ pub fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58362,7 +52679,7 @@ pub fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58385,7 +52702,7 @@ pub fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58408,7 +52725,7 @@ pub fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58431,7 +52748,7 @@ pub fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58454,7 +52771,7 @@ pub fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58477,7 +52794,7 @@ pub fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58500,7 +52817,7 @@ pub fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58523,7 +52840,7 @@ pub fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58546,7 +52863,7 @@ pub fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] @@ -58567,15 +52884,465 @@ pub fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe { simd_add(a, vrshr_n_u16::(b)) } } -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"] -#[inline(always)] +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + unsafe { simd_add(a, vrshrq_n_u16::(b)) } +} +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vrshr_n_u32::(b)) } +} +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + unsafe { simd_add(a, vrshrq_n_u32::(b)) } +} +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vrshr_n_u64::(b)) } +} +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + unsafe { simd_add(a, vrshrq_n_u64::(b)) } +} +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v8i8" + )] + fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; + } + unsafe { _vrsubhn_s16(a, b) } +} +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v4i16" + )] + fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; + } + unsafe { _vrsubhn_s32(a, b) } +} +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v2i32" + )] + fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; + } + unsafe { _vrsubhn_s64(a, b) } +} +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) } +} +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) } +} +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float16x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"] +#[inline] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"] +#[inline] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,fp16")] +#[unstable(feature = "stdarch_neon_f16", issue = "136306")] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: float16x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: float32x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: float32x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) + assert_instr(nop, LANE = 0) )] #[rustc_legacy_const_generics(2)] #[cfg_attr( @@ -58586,19 +53353,20 @@ pub fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - unsafe { simd_add(a, vrshrq_n_u16::(b)) } +pub fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) + assert_instr(nop, LANE = 0) )] #[rustc_legacy_const_generics(2)] #[cfg_attr( @@ -58609,19 +53377,24 @@ pub fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vrshr_n_u32::(b)) } +pub fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) + assert_instr(nop, LANE = 0) )] #[rustc_legacy_const_generics(2)] #[cfg_attr( @@ -58632,19 +53405,20 @@ pub fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - unsafe { simd_add(a, vrshrq_n_u32::(b)) } +pub fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(LANE, 4); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) + assert_instr(nop, LANE = 0) )] #[rustc_legacy_const_generics(2)] #[cfg_attr( @@ -58655,19 +53429,29 @@ pub fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vrshr_n_u64::(b)) } +pub fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(LANE, 4); + unsafe { + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x16_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } -#[doc = "Unsigned rounding shift right and accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ursra, N = 2) + assert_instr(nop, LANE = 0) )] #[rustc_legacy_const_generics(2)] #[cfg_attr( @@ -58678,20 +53462,22 @@ pub fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - unsafe { simd_add(a, vrshrq_n_u64::(b)) } +pub fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58700,27 +53486,26 @@ pub fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rsubhn.v8i8" - )] - fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; +pub fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int16x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } - unsafe { _vrsubhn_s16(a, b) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58729,27 +53514,22 @@ pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rsubhn.v4i16" - )] - fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; - } - unsafe { _vrsubhn_s32(a, b) } +pub fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58758,28 +53538,26 @@ pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.rsubhn.v2i32" - )] - fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; +pub fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int16x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) } - unsafe { _vrsubhn_s64(a, b) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58788,20 +53566,22 @@ pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) } +pub fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58810,25 +53590,26 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { - let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int32x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58837,20 +53618,22 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) } +pub fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58859,25 +53642,26 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; +pub fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { - let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b))); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: int32x4_t = simd_insert!(b, LANE as u32, a); simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58886,20 +53670,22 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) } +pub fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { simd_insert!(b, LANE as u32, a) } } -#[doc = "Rounding subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] -#[inline(always)] +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(rsubhn) + assert_instr(nop, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -58908,51 +53694,70 @@ pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; +pub fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { - let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b))); + let b: int64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: int64x2_t = simd_insert!(b, LANE as u32, a); simd_shuffle!(ret_val, ret_val, [1, 0]) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0) )] #[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x4_t { - static_assert_uimm_bits!(LANE, 2); +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0) )] #[rustc_legacy_const_generics(2)] -#[target_feature(enable = "neon,fp16")] -#[unstable(feature = "stdarch_neon_f16", issue = "136306")] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } + unsafe { + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -58969,13 +53774,14 @@ pub fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(LANE, 4); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -58992,13 +53798,23 @@ pub fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } +pub fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(LANE, 4); + unsafe { + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint8x16_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59015,13 +53831,14 @@ pub fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(LANE, 3); +pub fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59038,13 +53855,18 @@ pub fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(LANE, 4); - unsafe { simd_insert!(b, LANE as u32, a) } +pub fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint16x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59061,13 +53883,14 @@ pub fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); +pub fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59084,13 +53907,18 @@ pub fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { +pub fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } + unsafe { + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: uint16x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59107,13 +53935,14 @@ pub fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { +pub fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59130,13 +53959,18 @@ pub fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } +pub fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint32x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59153,13 +53987,14 @@ pub fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59176,13 +54011,18 @@ pub fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } +pub fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: uint32x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59199,13 +54039,14 @@ pub fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(LANE, 4); +pub fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59222,13 +54063,18 @@ pub fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { simd_insert!(b, LANE as u32, a) } +pub fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { + let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: uint64x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59245,13 +54091,14 @@ pub fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { +pub fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(LANE, 3); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59268,13 +54115,18 @@ pub fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_insert!(b, LANE as u32, a) } +pub fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(LANE, 3); + unsafe { + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59291,13 +54143,14 @@ pub fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); +pub fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(LANE, 4); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59314,13 +54167,23 @@ pub fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - unsafe { simd_insert!(b, LANE as u32, a) } +pub fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(LANE, 4); + unsafe { + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly8x16_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59337,13 +54200,14 @@ pub fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(LANE, 3); +pub fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(LANE, 2); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59360,13 +54224,18 @@ pub fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(LANE, 4); - unsafe { simd_insert!(b, LANE as u32, a) } +pub fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let ret_val: poly16x4_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59383,13 +54252,14 @@ pub fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(LANE, 2); +pub fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(LANE, 3); unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59408,11 +54278,15 @@ pub fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { )] pub fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { simd_insert!(b, LANE as u32, a) } + unsafe { + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: poly16x8_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59435,7 +54309,7 @@ pub fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59458,7 +54332,7 @@ pub fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59481,7 +54355,8 @@ pub fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_t { } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -59502,9 +54377,38 @@ pub fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(LANE, 1); unsafe { simd_insert!(b, LANE as u32, a) } } +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(LANE, 1); + unsafe { + let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]); + let ret_val: poly64x2_t = simd_insert!(b, LANE as u32, a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} #[doc = "SHA1 hash update accelerator, choose."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha1c))] @@ -59527,9 +54431,40 @@ pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32 } unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) } } +#[doc = "SHA1 hash update accelerator, choose."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1c))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1c" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")] + fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } + unsafe { + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1cq_u32(hash_abcd, hash_e, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SHA1 fixed rotate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha1h))] @@ -59554,7 +54489,8 @@ pub fn vsha1h_u32(hash_e: u32) -> u32 { } #[doc = "SHA1 hash update accelerator, majority"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha1m))] @@ -59577,9 +54513,41 @@ pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32 } unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) } } +#[doc = "SHA1 hash update accelerator, majority"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1m))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1m" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")] + fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } + unsafe { + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1mq_u32(hash_abcd, hash_e, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SHA1 hash update accelerator, parity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha1p))] @@ -59602,9 +54570,41 @@ pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32 } unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) } } +#[doc = "SHA1 hash update accelerator, parity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1p))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1p" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")] + fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; + } + unsafe { + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1pq_u32(hash_abcd, hash_e, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SHA1 schedule update accelerator, first part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha1su0))] @@ -59627,9 +54627,42 @@ pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> u } unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) } } +#[doc = "SHA1 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1su0))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1su0" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")] + fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t; + } + unsafe { + let w0_3: uint32x4_t = simd_shuffle!(w0_3, w0_3, [3, 2, 1, 0]); + let w4_7: uint32x4_t = simd_shuffle!(w4_7, w4_7, [3, 2, 1, 0]); + let w8_11: uint32x4_t = simd_shuffle!(w8_11, w8_11, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1su0q_u32(w0_3, w4_7, w8_11); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SHA1 schedule update accelerator, second part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha1su1))] @@ -59652,9 +54685,41 @@ pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { } unsafe { _vsha1su1q_u32(tw0_3, w12_15) } } +#[doc = "SHA1 schedule update accelerator, second part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha1su1))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha1su1" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")] + fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t; + } + unsafe { + let tw0_3: uint32x4_t = simd_shuffle!(tw0_3, tw0_3, [3, 2, 1, 0]); + let w12_15: uint32x4_t = simd_shuffle!(w12_15, w12_15, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha1su1q_u32(tw0_3, w12_15); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SHA1 schedule update accelerator, upper part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha256h2))] @@ -59681,9 +54746,46 @@ pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4 } unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) } } +#[doc = "SHA1 schedule update accelerator, upper part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha256h2))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256h2" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")] + fn _vsha256h2q_u32( + hash_abcd: uint32x4_t, + hash_efgh: uint32x4_t, + wk: uint32x4_t, + ) -> uint32x4_t; + } + unsafe { + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let hash_efgh: uint32x4_t = simd_shuffle!(hash_efgh, hash_efgh, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha256h2q_u32(hash_abcd, hash_efgh, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SHA1 schedule update accelerator, first part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha256h))] @@ -59710,9 +54812,46 @@ pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_ } unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) } } +#[doc = "SHA1 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha256h))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256h" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")] + fn _vsha256hq_u32( + hash_abcd: uint32x4_t, + hash_efgh: uint32x4_t, + wk: uint32x4_t, + ) -> uint32x4_t; + } + unsafe { + let hash_abcd: uint32x4_t = simd_shuffle!(hash_abcd, hash_abcd, [3, 2, 1, 0]); + let hash_efgh: uint32x4_t = simd_shuffle!(hash_efgh, hash_efgh, [3, 2, 1, 0]); + let wk: uint32x4_t = simd_shuffle!(wk, wk, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha256hq_u32(hash_abcd, hash_efgh, wk); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SHA256 schedule update accelerator, first part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha256su0))] @@ -59735,9 +54874,41 @@ pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t { } unsafe { _vsha256su0q_u32(w0_3, w4_7) } } +#[doc = "SHA256 schedule update accelerator, first part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha256su0))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256su0" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")] + fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t; + } + unsafe { + let w0_3: uint32x4_t = simd_shuffle!(w0_3, w0_3, [3, 2, 1, 0]); + let w4_7: uint32x4_t = simd_shuffle!(w4_7, w4_7, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha256su0q_u32(w0_3, w4_7); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "SHA256 schedule update accelerator, second part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(test, assert_instr(sha256su1))] @@ -59761,7 +54932,40 @@ pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) } unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) } } -#[inline(always)] +#[doc = "SHA256 schedule update accelerator, second part."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "sha2")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(test, assert_instr(sha256su1))] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") +)] +pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha256su1" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")] + fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) + -> uint32x4_t; + } + unsafe { + let tw0_3: uint32x4_t = simd_shuffle!(tw0_3, tw0_3, [3, 2, 1, 0]); + let w8_11: uint32x4_t = simd_shuffle!(w8_11, w8_11, [3, 2, 1, 0]); + let w12_15: uint32x4_t = simd_shuffle!(w12_15, w12_15, [3, 2, 1, 0]); + let ret_val: uint32x4_t = _vsha256su1q_u32(tw0_3, w8_11, w12_15); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59774,7 +54978,7 @@ fn vshiftlins_v16i8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } unsafe { _vshiftlins_v16i8(a, b, const { int8x16_t([N as i8; 16]) }) } } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59787,7 +54991,7 @@ fn vshiftlins_v1i64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } unsafe { _vshiftlins_v1i64(a, b, const { int64x1_t([N as i64; 1]) }) } } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59800,7 +55004,7 @@ fn vshiftlins_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } unsafe { _vshiftlins_v2i32(a, b, const { int32x2_t([N; 2]) }) } } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59813,7 +55017,7 @@ fn vshiftlins_v2i64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } unsafe { _vshiftlins_v2i64(a, b, const { int64x2_t([N as i64; 2]) }) } } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59826,7 +55030,7 @@ fn vshiftlins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } unsafe { _vshiftlins_v4i16(a, b, const { int16x4_t([N as i16; 4]) }) } } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59839,7 +55043,7 @@ fn vshiftlins_v4i32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } unsafe { _vshiftlins_v4i32(a, b, const { int32x4_t([N; 4]) }) } } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59852,7 +55056,7 @@ fn vshiftlins_v8i16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } unsafe { _vshiftlins_v8i16(a, b, const { int16x8_t([N as i16; 8]) }) } } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59867,7 +55071,7 @@ fn vshiftlins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v16i8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59882,7 +55086,7 @@ fn vshiftrins_v16i8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v1i64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59897,7 +55101,7 @@ fn vshiftrins_v1i64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59912,7 +55116,7 @@ fn vshiftrins_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59927,7 +55131,7 @@ fn vshiftrins_v2i64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59942,7 +55146,7 @@ fn vshiftrins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59957,7 +55161,7 @@ fn vshiftrins_v4i32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59972,7 +55176,7 @@ fn vshiftrins_v8i16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59987,7 +55191,7 @@ fn vshiftrins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60010,7 +55214,7 @@ pub fn vshl_n_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60033,7 +55237,7 @@ pub fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60056,7 +55260,7 @@ pub fn vshl_n_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60079,7 +55283,7 @@ pub fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60102,7 +55306,7 @@ pub fn vshl_n_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60125,7 +55329,7 @@ pub fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60148,7 +55352,7 @@ pub fn vshl_n_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60171,7 +55375,7 @@ pub fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60194,7 +55398,7 @@ pub fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60217,7 +55421,7 @@ pub fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60240,7 +55444,7 @@ pub fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60263,7 +55467,7 @@ pub fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60286,7 +55490,7 @@ pub fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60309,7 +55513,7 @@ pub fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60332,7 +55536,7 @@ pub fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] @@ -60355,7 +55559,7 @@ pub fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60384,7 +55588,7 @@ pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60413,7 +55617,7 @@ pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60442,7 +55646,7 @@ pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60471,7 +55675,7 @@ pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60500,7 +55704,7 @@ pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60529,7 +55733,7 @@ pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60558,7 +55762,7 @@ pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60587,7 +55791,7 @@ pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60616,7 +55820,7 @@ pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60645,7 +55849,7 @@ pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60674,7 +55878,7 @@ pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60703,7 +55907,7 @@ pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60732,7 +55936,7 @@ pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60761,7 +55965,7 @@ pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60790,7 +55994,7 @@ pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] @@ -60819,7 +56023,7 @@ pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))] @@ -60842,7 +56046,7 @@ pub fn vshll_n_s16(a: int16x4_t) -> int32x4_t { } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))] @@ -60865,7 +56069,7 @@ pub fn vshll_n_s32(a: int32x2_t) -> int64x2_t { } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))] @@ -60888,7 +56092,7 @@ pub fn vshll_n_s8(a: int8x8_t) -> int16x8_t { } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))] @@ -60911,7 +56115,7 @@ pub fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))] @@ -60934,7 +56138,7 @@ pub fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))] @@ -60957,7 +56161,7 @@ pub fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] @@ -60981,7 +56185,7 @@ pub fn vshr_n_s8(a: int8x8_t) -> int8x8_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] @@ -61005,7 +56209,7 @@ pub fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] @@ -61029,7 +56233,7 @@ pub fn vshr_n_s16(a: int16x4_t) -> int16x4_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] @@ -61053,7 +56257,7 @@ pub fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] @@ -61077,7 +56281,7 @@ pub fn vshr_n_s32(a: int32x2_t) -> int32x2_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] @@ -61101,7 +56305,7 @@ pub fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] @@ -61125,7 +56329,7 @@ pub fn vshr_n_s64(a: int64x1_t) -> int64x1_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] @@ -61149,7 +56353,7 @@ pub fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] @@ -61177,7 +56381,7 @@ pub fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] @@ -61205,7 +56409,7 @@ pub fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] @@ -61233,7 +56437,7 @@ pub fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] @@ -61261,7 +56465,7 @@ pub fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] @@ -61289,7 +56493,7 @@ pub fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] @@ -61317,7 +56521,7 @@ pub fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] @@ -61345,7 +56549,7 @@ pub fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] @@ -61373,7 +56577,7 @@ pub fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] @@ -61396,7 +56600,7 @@ pub fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] @@ -61419,7 +56623,7 @@ pub fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] @@ -61442,7 +56646,7 @@ pub fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] @@ -61465,7 +56669,7 @@ pub fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] @@ -61488,7 +56692,7 @@ pub fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] @@ -61511,7 +56715,7 @@ pub fn vshrn_n_u64(a: uint64x2_t) -> uint32x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61523,7 +56727,7 @@ pub fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61535,7 +56739,7 @@ pub fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61547,7 +56751,7 @@ pub fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61559,7 +56763,7 @@ pub fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61571,7 +56775,7 @@ pub fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61583,7 +56787,7 @@ pub fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61595,7 +56799,7 @@ pub fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61607,7 +56811,7 @@ pub fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61619,7 +56823,7 @@ pub fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61631,7 +56835,7 @@ pub fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61643,7 +56847,7 @@ pub fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61655,7 +56859,7 @@ pub fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61667,7 +56871,7 @@ pub fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61679,7 +56883,7 @@ pub fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61691,7 +56895,7 @@ pub fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61703,7 +56907,7 @@ pub fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61715,7 +56919,7 @@ pub fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61727,7 +56931,7 @@ pub fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61739,7 +56943,7 @@ pub fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -61751,7 +56955,7 @@ pub fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61774,7 +56978,7 @@ pub fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61797,7 +57001,7 @@ pub fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61820,7 +57024,7 @@ pub fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61843,7 +57047,7 @@ pub fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61866,7 +57070,7 @@ pub fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61889,7 +57093,7 @@ pub fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61912,7 +57116,7 @@ pub fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61935,7 +57139,7 @@ pub fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61958,7 +57162,7 @@ pub fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -61981,7 +57185,7 @@ pub fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -62004,7 +57208,7 @@ pub fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -62027,7 +57231,7 @@ pub fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -62050,7 +57254,7 @@ pub fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -62073,7 +57277,7 @@ pub fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -62096,7 +57300,7 @@ pub fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] @@ -62119,7 +57323,7 @@ pub fn vsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62131,7 +57335,7 @@ pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62143,7 +57347,7 @@ pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62155,7 +57359,7 @@ pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62167,7 +57371,7 @@ pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62179,7 +57383,7 @@ pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62191,7 +57395,7 @@ pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62203,7 +57407,7 @@ pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62215,7 +57419,7 @@ pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62227,7 +57431,7 @@ pub fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62239,7 +57443,7 @@ pub fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62251,7 +57455,7 @@ pub fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62263,7 +57467,7 @@ pub fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62275,7 +57479,7 @@ pub fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62287,7 +57491,7 @@ pub fn vsriq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62299,7 +57503,7 @@ pub fn vsri_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62311,7 +57515,7 @@ pub fn vsriq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62323,7 +57527,7 @@ pub fn vsri_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62335,7 +57539,7 @@ pub fn vsriq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62347,7 +57551,7 @@ pub fn vsri_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -62361,7 +57565,7 @@ pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -62379,7 +57583,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -62397,7 +57601,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(test, assert_instr(vst1))] @@ -62415,7 +57619,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(test, assert_instr(vst1))] @@ -62433,7 +57637,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -62453,7 +57657,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -62473,7 +57677,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(test, assert_instr(vst1))] @@ -62491,7 +57695,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(test, assert_instr(vst1))] @@ -62509,7 +57713,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -62529,7 +57733,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -62549,7 +57753,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62574,7 +57778,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62599,7 +57803,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -62625,7 +57829,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] #[target_feature(enable = "neon,fp16")] @@ -62651,7 +57855,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62665,7 +57869,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62679,7 +57883,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62693,7 +57897,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62707,7 +57911,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62721,7 +57925,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62735,7 +57939,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62749,7 +57953,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62763,7 +57967,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62777,7 +57981,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62791,7 +57995,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62805,7 +58009,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62819,7 +58023,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62833,7 +58037,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62847,7 +58051,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62861,7 +58065,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62875,7 +58079,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62889,7 +58093,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62903,7 +58107,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62917,7 +58121,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62931,7 +58135,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62945,7 +58149,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62959,7 +58163,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62973,7 +58177,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -62987,7 +58191,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst1))] @@ -63003,7 +58207,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst1))] @@ -63019,7 +58223,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -63038,7 +58242,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -63057,7 +58261,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -63076,7 +58280,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -63095,7 +58299,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -63117,7 +58321,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -63139,7 +58343,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -63164,7 +58368,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -63189,7 +58393,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63209,7 +58413,7 @@ pub unsafe fn vst1_lane_f16(a: *mut f16, b: float16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63229,7 +58433,7 @@ pub unsafe fn vst1q_lane_f16(a: *mut f16, b: float16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63254,7 +58458,7 @@ pub unsafe fn vst1_lane_f32(a: *mut f32, b: float32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63279,7 +58483,7 @@ pub unsafe fn vst1q_lane_f32(a: *mut f32, b: float32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63304,7 +58508,7 @@ pub unsafe fn vst1_lane_s8(a: *mut i8, b: int8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63329,7 +58533,7 @@ pub unsafe fn vst1q_lane_s8(a: *mut i8, b: int8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63354,7 +58558,7 @@ pub unsafe fn vst1_lane_s16(a: *mut i16, b: int16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63379,7 +58583,7 @@ pub unsafe fn vst1q_lane_s16(a: *mut i16, b: int16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63404,7 +58608,7 @@ pub unsafe fn vst1_lane_s32(a: *mut i32, b: int32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63429,7 +58633,7 @@ pub unsafe fn vst1q_lane_s32(a: *mut i32, b: int32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63454,7 +58658,7 @@ pub unsafe fn vst1q_lane_s64(a: *mut i64, b: int64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63479,7 +58683,7 @@ pub unsafe fn vst1_lane_u8(a: *mut u8, b: uint8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63504,7 +58708,7 @@ pub unsafe fn vst1q_lane_u8(a: *mut u8, b: uint8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63529,7 +58733,7 @@ pub unsafe fn vst1_lane_u16(a: *mut u16, b: uint16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63554,7 +58758,7 @@ pub unsafe fn vst1q_lane_u16(a: *mut u16, b: uint16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63579,7 +58783,7 @@ pub unsafe fn vst1_lane_u32(a: *mut u32, b: uint32x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63604,7 +58808,7 @@ pub unsafe fn vst1q_lane_u32(a: *mut u32, b: uint32x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63629,7 +58833,7 @@ pub unsafe fn vst1q_lane_u64(a: *mut u64, b: uint64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63654,7 +58858,7 @@ pub unsafe fn vst1_lane_p8(a: *mut p8, b: poly8x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63679,7 +58883,7 @@ pub unsafe fn vst1q_lane_p8(a: *mut p8, b: poly8x16_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63704,7 +58908,7 @@ pub unsafe fn vst1_lane_p16(a: *mut p16, b: poly16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63729,7 +58933,7 @@ pub unsafe fn vst1q_lane_p16(a: *mut p16, b: poly16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63754,7 +58958,7 @@ pub unsafe fn vst1_lane_p64(a: *mut p64, b: poly64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63779,7 +58983,7 @@ pub unsafe fn vst1_lane_s64(a: *mut i64, b: int64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -63804,7 +59008,7 @@ pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -63827,7 +59031,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -63850,7 +59054,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -63873,7 +59077,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -63896,7 +59100,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -63919,7 +59123,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -63942,7 +59146,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -63961,7 +59165,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -63980,7 +59184,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -63999,7 +59203,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64018,7 +59222,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64037,7 +59241,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64056,7 +59260,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64075,7 +59279,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64094,7 +59298,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64110,7 +59314,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64126,7 +59330,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64142,7 +59346,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64158,7 +59362,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64174,7 +59378,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64190,7 +59394,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64206,7 +59410,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64222,7 +59426,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64241,7 +59445,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64260,7 +59464,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64279,7 +59483,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64298,7 +59502,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64317,7 +59521,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64336,7 +59540,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64355,7 +59559,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64374,7 +59578,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64390,7 +59594,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64406,7 +59610,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64422,7 +59626,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64438,7 +59642,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64454,7 +59658,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64470,7 +59674,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64486,7 +59690,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64502,7 +59706,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64521,7 +59725,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64540,7 +59744,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64559,7 +59763,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64578,7 +59782,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64597,7 +59801,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64616,7 +59820,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64635,7 +59839,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -64654,7 +59858,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64670,7 +59874,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64686,7 +59890,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64702,7 +59906,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64718,7 +59922,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64734,7 +59938,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64750,7 +59954,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64766,7 +59970,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -64782,7 +59986,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64805,7 +60009,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64828,7 +60032,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64851,7 +60055,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64874,7 +60078,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64897,7 +60101,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64920,7 +60124,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64943,7 +60147,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64966,7 +60170,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -64989,7 +60193,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65012,7 +60216,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65035,7 +60239,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65058,7 +60262,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65081,7 +60285,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65104,7 +60308,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65127,7 +60331,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65150,7 +60354,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65173,7 +60377,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65196,7 +60400,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65219,7 +60423,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65242,7 +60446,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65265,7 +60469,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65288,7 +60492,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65311,7 +60515,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65334,7 +60538,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65357,7 +60561,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65380,7 +60584,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65403,7 +60607,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65426,7 +60630,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65449,7 +60653,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65472,7 +60676,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65495,7 +60699,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65518,7 +60722,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65541,7 +60745,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65564,7 +60768,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65587,7 +60791,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] @@ -65606,7 +60810,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) { vst1q_s16_x4(transmute(a), transmute(b)) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65620,7 +60824,7 @@ unsafe fn vst1_v1i64(addr: *const i8, val: int64x1_t) { } _vst1_v1i64(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65634,7 +60838,7 @@ unsafe fn vst1_v2f32(addr: *const i8, val: float32x2_t) { } _vst1_v2f32(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65648,7 +60852,7 @@ unsafe fn vst1_v2i32(addr: *const i8, val: int32x2_t) { } _vst1_v2i32(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65662,7 +60866,7 @@ unsafe fn vst1_v4i16(addr: *const i8, val: int16x4_t) { } _vst1_v4i16(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65676,7 +60880,7 @@ unsafe fn vst1_v8i8(addr: *const i8, val: int8x8_t) { } _vst1_v8i8(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65690,7 +60894,7 @@ unsafe fn vst1q_v16i8(addr: *const i8, val: int8x16_t) { } _vst1q_v16i8(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65704,7 +60908,7 @@ unsafe fn vst1q_v2i64(addr: *const i8, val: int64x2_t) { } _vst1q_v2i64(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65718,7 +60922,7 @@ unsafe fn vst1q_v4f32(addr: *const i8, val: float32x4_t) { } _vst1q_v4f32(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65732,7 +60936,7 @@ unsafe fn vst1q_v4i32(addr: *const i8, val: int32x4_t) { } _vst1q_v4i32(addr, val, ALIGN) } -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65750,7 +60954,7 @@ unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -65768,7 +60972,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -65786,7 +60990,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -65811,7 +61015,7 @@ pub unsafe fn vst1q_lane_p64(a: *mut p64, b: poly64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -65832,7 +61036,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -65853,7 +61057,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65872,7 +61076,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65891,7 +61095,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -65903,7 +61107,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -65915,7 +61119,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -65927,7 +61131,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -65939,7 +61143,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -65951,7 +61155,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -65963,7 +61167,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -65975,7 +61179,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -65987,7 +61191,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66003,7 +61207,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66019,7 +61223,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66035,7 +61239,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66051,7 +61255,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66067,7 +61271,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66083,7 +61287,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66099,7 +61303,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66115,7 +61319,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66138,7 +61342,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66161,7 +61365,7 @@ pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66182,7 +61386,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66192,7 +61396,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { - static_assert_uimm_bits!(LANE, 1); + static_assert_uimm_bits!(LANE, 3); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0.v8f16")] fn _vst2q_lane_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, n: i32, size: i32); @@ -66203,7 +61407,7 @@ pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66224,7 +61428,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66245,7 +61449,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66266,7 +61470,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66287,7 +61491,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66308,7 +61512,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66329,7 +61533,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -66350,7 +61554,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -66368,7 +61572,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -66386,7 +61590,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -66404,7 +61608,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -66422,7 +61626,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -66440,7 +61644,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -66458,7 +61662,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst2, LANE = 0))] @@ -66476,7 +61680,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -66501,7 +61705,7 @@ pub unsafe fn vst2_lane_u8(a: *mut u8, b: uint8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -66526,7 +61730,7 @@ pub unsafe fn vst2_lane_u16(a: *mut u16, b: uint16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -66551,7 +61755,7 @@ pub unsafe fn vst2q_lane_u16(a: *mut u16, b: uint16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -66576,7 +61780,7 @@ pub unsafe fn vst2_lane_u32(a: *mut u32, b: uint32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -66601,7 +61805,7 @@ pub unsafe fn vst2q_lane_u32(a: *mut u32, b: uint32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -66626,7 +61830,7 @@ pub unsafe fn vst2_lane_p8(a: *mut p8, b: poly8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -66651,7 +61855,7 @@ pub unsafe fn vst2_lane_p16(a: *mut p16, b: poly16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] @@ -66676,7 +61880,7 @@ pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -66699,7 +61903,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -66711,7 +61915,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -66723,7 +61927,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -66746,7 +61950,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66769,7 +61973,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66792,7 +61996,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66815,7 +62019,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66838,7 +62042,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66861,7 +62065,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66884,7 +62088,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66907,7 +62111,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66930,7 +62134,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66953,7 +62157,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] @@ -66976,7 +62180,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66995,7 +62199,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67014,7 +62218,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -67035,7 +62239,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -67056,7 +62260,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67068,7 +62272,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67080,7 +62284,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67092,7 +62296,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67104,7 +62308,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67116,7 +62320,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67128,7 +62332,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67140,7 +62344,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67152,159 +62356,103 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2f32.p0" - )] - fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8); - } - _vst3_f32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(f32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4f32.p0" - )] - fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8); - } - _vst3q_f32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(f32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v8i8.p0" - )] - fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8); - } - _vst3_s8(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i8, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v16i8.p0" - )] - fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8); - } - _vst3q_s8(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i8, 16, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4i16.p0" - )] - fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8); - } - _vst3_s16(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i16, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v8i16.p0" - )] - fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8); - } - _vst3q_s16(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i16, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2i32.p0" - )] - fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8); - } - _vst3_s32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4i32.p0" - )] - fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8); - } - _vst3q_s32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67332,7 +62480,7 @@ pub unsafe fn vst3_lane_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67360,7 +62508,7 @@ pub unsafe fn vst3q_lane_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67383,7 +62531,7 @@ pub unsafe fn vst3_lane_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67406,7 +62554,7 @@ pub unsafe fn vst3q_lane_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -67431,7 +62579,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -67456,7 +62604,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -67474,7 +62622,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -67499,7 +62647,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -67524,7 +62672,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -67549,7 +62697,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst3, LANE = 0))] @@ -67574,7 +62722,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67595,7 +62743,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67616,7 +62764,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67637,7 +62785,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67658,7 +62806,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67679,7 +62827,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67700,7 +62848,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -67721,7 +62869,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -67746,7 +62894,7 @@ pub unsafe fn vst3_lane_u8(a: *mut u8, b: uint8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -67771,7 +62919,7 @@ pub unsafe fn vst3_lane_u16(a: *mut u16, b: uint16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -67796,7 +62944,7 @@ pub unsafe fn vst3q_lane_u16(a: *mut u16, b: uint16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -67821,7 +62969,7 @@ pub unsafe fn vst3_lane_u32(a: *mut u32, b: uint32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -67846,7 +62994,7 @@ pub unsafe fn vst3q_lane_u32(a: *mut u32, b: uint32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -67871,7 +63019,7 @@ pub unsafe fn vst3_lane_p8(a: *mut p8, b: poly8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -67896,7 +63044,7 @@ pub unsafe fn vst3_lane_p16(a: *mut p16, b: poly16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] @@ -67921,7 +63069,7 @@ pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -67944,7 +63092,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -67956,7 +63104,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -67968,7 +63116,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] @@ -67991,7 +63139,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68014,7 +63162,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68037,7 +63185,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68060,7 +63208,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68083,7 +63231,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68106,7 +63254,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68129,7 +63277,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68152,7 +63300,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68175,7 +63323,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68198,7 +63346,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] @@ -68221,7 +63369,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68247,7 +63395,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68273,7 +63421,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -68294,7 +63442,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] @@ -68315,7 +63463,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68338,7 +63486,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68361,7 +63509,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68377,7 +63525,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68400,7 +63548,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68423,7 +63571,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68446,7 +63594,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68469,7 +63617,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] @@ -68492,7 +63640,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -68504,7 +63652,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -68516,7 +63664,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -68528,7 +63676,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -68540,7 +63688,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -68552,7 +63700,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -68564,7 +63712,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -68576,7 +63724,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -68588,7 +63736,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68617,7 +63765,7 @@ pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68646,7 +63794,7 @@ pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -68676,7 +63824,7 @@ pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] @@ -68706,7 +63854,7 @@ pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst4, LANE = 0))] @@ -68732,7 +63880,7 @@ pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst4, LANE = 0))] @@ -68758,7 +63906,7 @@ pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst4, LANE = 0))] @@ -68784,7 +63932,7 @@ pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst4, LANE = 0))] @@ -68810,7 +63958,7 @@ pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst4, LANE = 0))] @@ -68836,7 +63984,7 @@ pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst4, LANE = 0))] @@ -68862,7 +64010,7 @@ pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vst4, LANE = 0))] @@ -68885,207 +64033,960 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v2f32.p0" + )] + fn _vst4_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v4f32.p0" + )] + fn _vst4q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v8i8.p0" + )] + fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8); + } + _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v4i16.p0" + )] + fn _vst4_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v8i16.p0" + )] + fn _vst4q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v2i32.p0" + )] + fn _vst4_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v4i32.p0" + )] + fn _vst4q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4_lane_s8::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + vst4_lane_s16::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4q_lane_s16::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + vst4_lane_s32::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + vst4q_lane_s32::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4_lane_s8::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + vst4_lane_s16::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4q_lane_s16::(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { + vst4_s64(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { + core::ptr::write_unaligned(a.cast(), b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { + core::ptr::write_unaligned(a.cast(), b) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { + vst4_s64(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { + vst4_s8(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { + vst4q_s8(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { + vst4_s16(transmute(a), transmute(b)) +} +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v2f32.p0" - )] - fn _vst4_lane_f32( - a: float32x2_t, - b: float32x2_t, - c: float32x2_t, - d: float32x2_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { + vst4q_s16(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v4f32.p0" - )] - fn _vst4q_lane_f32( - a: float32x4_t, - b: float32x4_t, - c: float32x4_t, - d: float32x4_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { + vst4_s32(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v8i8.p0" - )] - fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8); - } - _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { + vst4q_s32(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v4i16.p0" - )] - fn _vst4_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, - d: int16x4_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { + vst4_s8(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v8i16.p0" - )] - fn _vst4q_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, - d: int16x8_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { + vst4q_s8(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v2i32.p0" - )] - fn _vst4_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, - d: int32x2_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { + vst4_s16(transmute(a), transmute(b)) } #[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4lane.v4i32.p0" - )] - fn _vst4q_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, - d: int32x4_t, - n: i64, - ptr: *mut i8, - ); - } - _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { + vst4q_s16(transmute(a), transmute(b)) +} +#[doc = "Store SIMD&FP register (immediate offset)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vstrq_p128(a: *mut p128, b: p128) { + *a = b +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[target_feature(enable = "neon,fp16")] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "stdarch_neon_fp16", since = "1.94.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +#[cfg(not(target_arch = "arm64ec"))] +pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_sub(a, b) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -69094,23 +64995,19 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4_lane_s8::(transmute(a), transmute(b)) +pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -69119,23 +65016,19 @@ pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4_lane_s16::(transmute(a), transmute(b)) +pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -69144,23 +65037,19 @@ pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4q_lane_s16::(transmute(a), transmute(b)) +pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -69169,23 +65058,19 @@ pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - vst4_lane_s32::(transmute(a), transmute(b)) +pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -69194,23 +65079,19 @@ pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4q_lane_s32::(transmute(a), transmute(b)) +pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -69219,23 +65100,19 @@ pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4_lane_s8::(transmute(a), transmute(b)) +pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -69244,23 +65121,19 @@ pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4_lane_s16::(transmute(a), transmute(b)) +pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4, LANE = 0) + assert_instr(sub) )] -#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -69269,21 +65142,18 @@ pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4q_lane_s16::(transmute(a), transmute(b)) +pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(sub) )] #[cfg_attr( not(target_arch = "arm"), @@ -69293,44 +65163,74 @@ pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { - vst4_s64(transmute(a), transmute(b)) +pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_sub(a, b) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { - core::ptr::write_unaligned(a.cast(), b) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { + let d = vsubhn_s16(b, c); + vcombine_s8(a, d) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"] +#[inline] #[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { - core::ptr::write_unaligned(a.cast(), b) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { + let d = vsubhn_s32(b, c); + vcombine_s16(a, d) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -69340,20 +65240,97 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { - vst4_s64(transmute(a), transmute(b)) +pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { + let d = vsubhn_s64(b, c); + vcombine_s32(a, d) } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { + let d = vsubhn_u16(b, c); + vcombine_u8(a, d) +} +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { + let d = vsubhn_u32(b, c); + vcombine_u16(a, d) +} +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { + let d = vsubhn_u64(b, c); + vcombine_u32(a, d) +} +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -69363,20 +65340,19 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { - vst4_s8(transmute(a), transmute(b)) +pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { + let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -69386,20 +65362,19 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { - vst4q_s8(transmute(a), transmute(b)) +pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { + let c: i32x4 = i32x4::new(16, 16, 16, 16); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -69409,20 +65384,19 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { - vst4_s16(transmute(a), transmute(b)) +pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { + let c: i64x2 = i64x2::new(32, 32); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -69432,20 +65406,19 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { - vst4q_s16(transmute(a), transmute(b)) +pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -69455,20 +65428,19 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { - vst4_s32(transmute(a), transmute(b)) +pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + let c: u32x4 = u32x4::new(16, 16, 16, 16); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(subhn) )] #[cfg_attr( not(target_arch = "arm"), @@ -69478,20 +65450,19 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { - vst4q_s32(transmute(a), transmute(b)) +pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + let c: u64x2 = u64x2::new(32, 32); + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(ssubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -69501,20 +65472,22 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { - vst4_s8(transmute(a), transmute(b)) +pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { + unsafe { + let c: int16x8_t = simd_cast(a); + let d: int16x8_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(ssubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -69524,20 +65497,22 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { - vst4q_s8(transmute(a), transmute(b)) +pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + unsafe { + let c: int32x4_t = simd_cast(a); + let d: int32x4_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(ssubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -69547,20 +65522,22 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { - vst4_s16(transmute(a), transmute(b)) +pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + unsafe { + let c: int64x2_t = simd_cast(a); + let d: int64x2_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Store multiple 4-element structures from four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(st4) + assert_instr(usubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -69570,20 +65547,22 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { - vst4q_s16(transmute(a), transmute(b)) +pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { + let c: uint16x8_t = simd_cast(a); + let d: uint16x8_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Store SIMD&FP register (immediate offset)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) + assert_instr(usubl) )] #[cfg_attr( not(target_arch = "arm"), @@ -69593,62 +65572,68 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vstrq_p128(a: *mut p128, b: p128) { - *a = b +pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { + let c: uint32x4_t = simd_cast(a); + let d: uint32x4_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fsub) + assert_instr(usubl) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe { simd_sub(a, b) } +pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { + let c: uint64x2_t = simd_cast(a); + let d: uint64x2_t = simd_cast(b); + simd_sub(c, d) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fsub) + assert_instr(ssubw) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"] -#[inline(always)] +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fsub) + assert_instr(ssubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -69658,18 +65643,18 @@ pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"] -#[inline(always)] +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(fsub) + assert_instr(ssubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -69679,18 +65664,18 @@ pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"] -#[inline(always)] +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(usubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -69700,18 +65685,18 @@ pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"] -#[inline(always)] +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(usubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -69721,18 +65706,18 @@ pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"] -#[inline(always)] +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(usubw) )] #[cfg_attr( not(target_arch = "arm"), @@ -69742,291 +65727,750 @@ pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - unsafe { simd_sub(a, b) } +pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { simd_sub(a, simd_cast(b)) } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sudot, LANE = 0) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + unstable(feature = "stdarch_neon_i8mm", issue = "117223") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { simd_sub(a, b) } +pub fn vsudot_lane_s32(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c = vreinterpret_u32_u8(c); + let c = vdup_lane_u32::(c); + vusdot_s32(a, vreinterpret_u8_u32(c), b) } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sudot, LANE = 0) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + unstable(feature = "stdarch_neon_i8mm", issue = "117223") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - unsafe { simd_sub(a, b) } +pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c = vreinterpret_u32_u8(c); + let c = vdupq_lane_u32::(c); + vusdotq_s32(a, vreinterpretq_u8_u32(c), b) +} +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sudot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c = vreinterpretq_u32_u8(c); + let c = vdup_laneq_u32::(c); + vusdot_s32(a, vreinterpret_u8_u32(c), b) +} +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(sudot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c = vreinterpretq_u32_u8(c); + let c = vdupq_laneq_u32::(c); + vusdotq_s32(a, vreinterpretq_u8_u32(c), b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")] + fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + unsafe { _vtbl1(a, b) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + vtbl1(a, b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbl1(transmute(a), transmute(b))) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbl1(transmute(a), transmute(b))) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")] + fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; + } + unsafe { _vtbl2(a, b, c) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { + vtbl2(a.0, a.1, b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")] + fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; + } + unsafe { _vtbl3(a, b, c, d) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { + vtbl3(a.0, a.1, a.2, b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbl3( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(b), + )) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbl3( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(b), + )) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")] + fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; + } + unsafe { _vtbl4(a, b, c, d, e) } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { + vtbl4(a.0, a.1, a.2, a.3, b) +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + transmute(b), + )) + } +} +#[doc = "Table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(target_arch = "arm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbl))] +pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + transmute(b), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")] + fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; + } + unsafe { _vtbx1(a, b, c) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + vtbx1(a, b, c) +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")] + fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; + } + unsafe { _vtbx2(a, b, c, d) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { + vtbx2(a, b.0, b.1, c) +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx2( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(c), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx2( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(c), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")] + fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; + } + unsafe { _vtbx3(a, b, c, d, e) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { + vtbx3(a, b.0, b.1, b.2, c) +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(c), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(c), + )) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")] + fn _vtbx4( + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + e: int8x8_t, + f: int8x8_t, + ) -> int8x8_t; + } + unsafe { _vtbx4(a, b, c, d, e, f) } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { + unsafe { + vtbx4( + a, + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + ) + } +} +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { + let mut b: int8x8x4_t = b; + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); + b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]); + b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); + b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int8x8_t = vtbx4( + a, + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe { simd_sub(a, b) } +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + transmute(c), + )) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - unsafe { simd_sub(a, b) } +#[doc = "Extended table look-up"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] +#[inline] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vtbx))] +pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + transmute(c), + )) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { simd_sub(a, b) } -} -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(trn2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - unsafe { simd_sub(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { + unsafe { + let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe { simd_sub(a, b) } -} -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(trn2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - unsafe { simd_sub(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { + unsafe { + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: float16x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { simd_sub(a, b) } -} -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(trn2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe { simd_sub(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { + unsafe { + let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe { simd_sub(a, b) } -} -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) + assert_instr(trn2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { simd_sub(a, b) } +#[cfg(not(target_arch = "arm64ec"))] +pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { + unsafe { + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: float16x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } } -#[doc = "Subtract"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sub) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { simd_sub(a, b) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70036,41 +66480,27 @@ pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let d: int8x8_t = vsubhn_s16(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } +pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + unsafe { + let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let d: int16x4_t = vsubhn_s32(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70080,41 +66510,32 @@ pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let d: int32x2_t = vsubhn_s64(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) } +pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + unsafe { + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: float32x2x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let d: uint8x8_t = vsubhn_u16(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70124,41 +66545,27 @@ pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let d: uint16x4_t = vsubhn_u32(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } +pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + unsafe { + let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let d: uint32x2_t = vsubhn_u64(b, c); - unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70168,41 +66575,32 @@ pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { - let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } +pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: int32x2x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { - let c: i32x4 = i32x4::new(16, 16, 16, 16); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70212,41 +66610,27 @@ pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { - let c: i64x2 = i64x2::new(32, 32); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } +pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { + unsafe { + let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(zip1) )] -pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -} -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70256,41 +66640,32 @@ pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - let c: u32x4 = u32x4::new(16, 16, 16, 16); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } +pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: uint32x2x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val + } } -#[doc = "Subtract returning high narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(subhn) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - let c: u64x2 = u64x2::new(32, 32); - unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -} -#[doc = "Signed Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubl) + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70300,47 +66675,27 @@ pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { +pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let c: int16x8_t = simd_cast(a); - let d: int16x8_t = simd_cast(b); - simd_sub(c, d) + let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Signed Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubl) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - unsafe { - let c: int32x4_t = simd_cast(a); - let d: int32x4_t = simd_cast(b); - simd_sub(c, d) - } -} -#[doc = "Signed Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubl) + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70350,22 +66705,32 @@ pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { +pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let c: int64x2_t = simd_cast(a); - let d: int64x2_t = simd_cast(b); - simd_sub(c, d) + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: float32x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unsigned Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubl) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70375,22 +66740,27 @@ pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { +pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let c: uint16x8_t = simd_cast(a); - let d: uint16x8_t = simd_cast(b); - simd_sub(c, d) + let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } } -#[doc = "Unsigned Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubl) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70400,22 +66770,32 @@ pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { +pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let c: uint32x4_t = simd_cast(a); - let d: uint32x4_t = simd_cast(b); - simd_sub(c, d) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: int8x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unsigned Subtract Long"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubl) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70425,22 +66805,35 @@ pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { +pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let c: uint64x2_t = simd_cast(a); - let d: uint64x2_t = simd_cast(b); - simd_sub(c, d) + let a1: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: int8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) } } -#[doc = "Signed Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70450,18 +66843,50 @@ pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + unsafe { + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a1: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: int8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + let mut ret_val: int8x16x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val + } } -#[doc = "Signed Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70471,18 +66896,27 @@ pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + unsafe { + let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } -#[doc = "Signed Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ssubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70492,18 +66926,32 @@ pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: int16x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val + } } -#[doc = "Unsigned Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70513,18 +66961,27 @@ pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + unsafe { + let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } -#[doc = "Unsigned Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubw) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] #[cfg_attr( not(target_arch = "arm"), @@ -70534,1285 +66991,1533 @@ pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { - unsafe { simd_sub(a, simd_cast(b)) } +pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + unsafe { + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: int16x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } } -#[doc = "Unsigned Subtract Wide"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usubw) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(trn1) )] -pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { - unsafe { simd_sub(a, simd_cast(b)) } -} -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 0) + assert_instr(trn2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsudot_lane_s32(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) + let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 0) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsudot_lane_s32(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vusdot_s32(a, transmute(c), b); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: int32x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 0) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) + let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 0) + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: int8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vusdotq_s32(a, transmute(c), b); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 3) -)] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) - } -} -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(sudot, LANE = 3) -)] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")] - fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } - unsafe { _vtbl1(a, b) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - vtbl1(a, b) -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vtbl1(transmute(a), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vtbl1(transmute(a), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")] - fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; - } - unsafe { _vtbl2(a, b, c) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { - vtbl2(a.0, a.1, b) -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")] - fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; - } - unsafe { _vtbl3(a, b, c, d) } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { - vtbl3(a.0, a.1, a.2, b) +pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: uint8x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )) + let a1: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: uint8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a1: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: uint8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + let mut ret_val: uint8x16x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )) + let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: uint16x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")] - fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + unsafe { + let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } - unsafe { _vtbl4(a, b, c, d, e) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { - vtbl4(a.0, a.1, a.2, a.3, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + unsafe { + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: uint16x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )) + let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: uint32x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] +#[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )) + let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] +#[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbl))] -pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")] - fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: poly8x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } - unsafe { _vtbx1(a, b, c) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - vtbx1(a, b, c) -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a1: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: poly8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { - unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: poly8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")] - fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a1: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: poly8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + let mut ret_val: poly8x16x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } - unsafe { _vtbx2(a, b, c, d) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { - vtbx2(a, b.0, b.1, c) } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )) + let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x2_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + let mut ret_val: poly16x4x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { unsafe { - transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )) + let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x2_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")] - fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + let mut ret_val: poly16x8x2_t = transmute((a1, b1)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } - unsafe { _vtbx3(a, b, c, d, e) } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { - vtbx3(a, b.0, b.1, b.2, c) } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { unsafe { - transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )) + let c: int8x8_t = simd_and(a, b); + let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x3_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: int8x16_t = simd_and(a, b); + let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { unsafe { - transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )) + let c: int16x4_t = simd_and(a, b); + let d: i16x4 = i16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x3_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: int16x8_t = simd_and(a, b); + let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")] - fn _vtbx4( - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - d: int8x8_t, - e: int8x8_t, - f: int8x8_t, - ) -> int8x8_t; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe { + let c: int32x2_t = simd_and(a, b); + let d: i32x2 = i32x2::new(0, 0); + simd_ne(c, transmute(d)) } - unsafe { _vtbx4(a, b, c, d, e, f) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { unsafe { - vtbx4( - a, - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - ) + let c: int32x4_t = simd_and(a, b); + let d: i32x4 = i32x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { - let mut b: int8x8x4_t = b; - let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { unsafe { - let ret_val: int8x8_t = vtbx4( - a, - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - ); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: poly8x8_t = simd_and(a, b); + let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { unsafe { - transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )) + let c: poly8x16_t = simd_and(a, b); + let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x4_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { unsafe { - let ret_val: uint8x8_t = transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: poly16x4_t = simd_and(a, b); + let d: i16x4 = i16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { unsafe { - transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )) + let c: poly16x8_t = simd_and(a, b); + let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(vtbx))] -pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x4_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe { - let ret_val: poly8x8_t = transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let c: uint8x8_t = simd_and(a, b); + let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"] -#[inline(always)] +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let c: uint8x16_t = simd_and(a, b); + let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } +} +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(cmtst) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { +pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe { - let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let c: uint16x4_t = simd_and(a, b); + let d: u16x4 = u16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"] -#[inline(always)] +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"] +#[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let c: uint16x8_t = simd_and(a, b); + let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } +} +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(cmtst) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { +pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe { - let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let c: uint32x2_t = simd_and(a, b); + let d: u32x2 = u32x2::new(0, 0); + simd_ne(c, transmute(d)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] -#[inline(always)] +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"] +#[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip1) + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] +pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let c: uint32x4_t = simd_and(a, b); + let d: u32x4 = u32x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) + } +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip2) + assert_instr(usdot, LANE = 0) )] +#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + unstable(feature = "stdarch_neon_i8mm", issue = "117223") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { +pub fn vusdot_lane_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c = vreinterpret_s32_s8(c); + let c = vdup_lane_s32::(c); + vusdot_s32(a, b, vreinterpret_s8_s32(c)) +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c = vreinterpret_s32_s8(c); + let c = vdupq_lane_s32::(c); + vusdotq_s32(a, b, vreinterpretq_s8_s32(c)) +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c = vreinterpretq_s32_s8(c); + let c = vdup_laneq_s32::(c); + vusdot_s32(a, b, vreinterpret_s8_s32(c)) +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c = vreinterpretq_s32_s8(c); + let c = vdupq_laneq_s32::(c); + vusdotq_s32(a, b, vreinterpretq_s8_s32(c)) +} +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] + fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t; + } + unsafe { _vusdot_s32(a, b, c) } +} +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] + fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t; + } unsafe { - let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int32x2_t = _vusdot_s32(a, b, c); + simd_shuffle!(ret_val, ret_val, [1, 0]) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] + fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; + } + unsafe { _vusdotq_s32(a, b, c) } +} +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all( + test, + any(target_arch = "aarch64", target_arch = "arm64ec"), + target_endian = "little" + ), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] + fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; + } + unsafe { + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let c: int8x16_t = + simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let ret_val: int32x4_t = _vusdotq_s32(a, b, c); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usmmla) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")] + fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; + } + unsafe { _vusmmlaq_s32(a, b, c) } +} +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip2) + assert_instr(uzp2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unsafe { - let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) + let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(zip2) + assert_instr(uzp2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unsafe { - let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: float16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { unsafe { - let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { unsafe { - let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: float16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -71822,34 +68527,27 @@ pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { +pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { unsafe { - let a1: int8x16_t = simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ); - let b1: int8x16_t = simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ); - transmute((a1, b1)) + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -71859,26 +68557,32 @@ pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { +pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { unsafe { - let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: float32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -71888,26 +68592,27 @@ pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { +pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { unsafe { - let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -71917,26 +68622,32 @@ pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { +pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { unsafe { - let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: int32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -71946,26 +68657,27 @@ pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { +pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -71975,34 +68687,32 @@ pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { +pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let a1: uint8x16_t = simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ); - let b1: uint8x16_t = simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ); - transmute((a1, b1)) + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: uint32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72012,26 +68722,27 @@ pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { +pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72041,26 +68752,32 @@ pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { +pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: float32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72070,26 +68787,27 @@ pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { +pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72099,26 +68817,32 @@ pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { +pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: int8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72128,34 +68852,35 @@ pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { +pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let a1: poly8x16_t = simd_shuffle!( + let a0: int8x16_t = simd_shuffle!( a, b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] ); - let b1: poly8x16_t = simd_shuffle!( + let b0: int8x16_t = simd_shuffle!( a, b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] ); - transmute((a1, b1)) + transmute((a0, b0)) } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72165,26 +68890,50 @@ pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { +pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + let mut ret_val: int8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } -#[doc = "Transpose elements"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn1) + assert_instr(uzp1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(trn2) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72194,47 +68943,27 @@ pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { +pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { unsafe { - let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) + let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(uzp1) )] -pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - unsafe { - let c: int8x8_t = simd_and(a, b); - let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) - } -} -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72244,22 +68973,32 @@ pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { +pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { unsafe { - let c: int8x16_t = simd_and(a, b); - let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: int16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72269,22 +69008,27 @@ pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { +pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { unsafe { - let c: int16x4_t = simd_and(a, b); - let d: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72294,22 +69038,32 @@ pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { +pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { unsafe { - let c: int16x8_t = simd_and(a, b); - let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: int16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72319,22 +69073,27 @@ pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { +pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let c: int32x2_t = simd_and(a, b); - let d: i32x2 = i32x2::new(0, 0); - simd_ne(c, transmute(d)) + let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72344,22 +69103,32 @@ pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { +pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let c: int32x4_t = simd_and(a, b); - let d: i32x4 = i32x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: int32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72369,22 +69138,27 @@ pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { +pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let c: poly8x8_t = simd_and(a, b); - let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72394,22 +69168,32 @@ pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { +pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let c: poly8x16_t = simd_and(a, b); - let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: uint8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72419,22 +69203,35 @@ pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { +pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let c: poly16x4_t = simd_and(a, b); - let d: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) } } -#[doc = "Signed compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72444,22 +69241,50 @@ pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { +pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let c: poly16x8_t = simd_and(a, b); - let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + let mut ret_val: uint8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72469,22 +69294,27 @@ pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let c: uint8x8_t = simd_and(a, b); - let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72494,22 +69324,32 @@ pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let c: uint8x16_t = simd_and(a, b); - let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: uint16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp1) +)] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72519,22 +69359,27 @@ pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { unsafe { - let c: uint16x4_t = simd_and(a, b); - let d: u16x4 = u16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72544,22 +69389,32 @@ pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { unsafe { - let c: uint16x8_t = simd_and(a, b); - let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: uint16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72569,22 +69424,27 @@ pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let c: uint32x2_t = simd_and(a, b); - let d: u32x2 = u32x2::new(0, 0); - simd_ne(c, transmute(d)) + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Unsigned compare bitwise Test bits nonzero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(cmtst) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), @@ -72594,323 +69454,274 @@ pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let c: uint32x4_t = simd_and(a, b); - let d: u32x4 = u32x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: uint32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 0) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdot_lane_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, transmute(c)) + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 0) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdot_lane_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: poly8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] +#[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 0) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); +pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let c: int32x2_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, transmute(c)) + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] +#[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 0) + assert_instr(uzp1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let c: int32x2_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + let mut ret_val: poly8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] +#[inline] #[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 3) + assert_instr(uzp1) )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, transmute(c)) - } -} -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 3) + assert_instr(uzp2) )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [1, 0]) - } -} -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] #[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 3) + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - let c: int32x4_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, transmute(c)) + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] -#[inline(always)] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] +#[inline] #[cfg(target_endian = "big")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot, LANE = 3) + assert_instr(uzp1) )] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: int8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let c: int32x4_t = transmute(c); - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c)); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) - } -} -#[doc = "Dot product vector form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] - fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t; +pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { + unsafe { + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let mut ret_val: poly16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } - unsafe { _vusdot_s32(a, b, c) } } -#[doc = "Dot product vector form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usdot) -)] -#[cfg_attr( - not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + assert_instr(uzp1) )] -pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] - fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; - } - unsafe { _vusdotq_s32(a, b, c) } -} -#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(usmmla) + assert_instr(uzp2) )] #[cfg_attr( not(target_arch = "arm"), - unstable(feature = "stdarch_neon_i8mm", issue = "117223") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")] - fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; +pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + unsafe { + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) } - unsafe { _vusmmlaq_s32(a, b, c) } } #[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] #[cfg_attr( @@ -72921,35 +69732,39 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp2) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { +pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { unsafe { - let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let mut ret_val: poly16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[target_feature(enable = "neon,fp16")] #[cfg_attr( @@ -72961,19 +69776,19 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] #[cfg(not(target_arch = "arm64ec"))] -pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { +pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unsafe { - let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -72982,27 +69797,34 @@ pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { unsafe { - let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) + let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: float16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"] +#[inline] +#[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73011,27 +69833,29 @@ pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { unsafe { - let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] -#[inline(always)] -#[target_feature(enable = "neon")] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"] +#[inline] +#[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73040,34 +69864,42 @@ pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] +#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { +#[cfg(not(target_arch = "arm64ec"))] +pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { unsafe { - let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) + let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: float16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73077,26 +69909,27 @@ pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { +pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { unsafe { - let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73106,26 +69939,32 @@ pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { +pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { unsafe { - let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) + let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: float32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: float32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73135,34 +69974,27 @@ pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { +pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { unsafe { - let a0: int8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: int8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73172,26 +70004,32 @@ pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { +pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { unsafe { - let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) + let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: int32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: int32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73201,26 +70039,27 @@ pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { +pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73230,26 +70069,32 @@ pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { +pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { unsafe { - let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) + let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); + let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + let mut ret_val: uint32x2x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73259,26 +70104,27 @@ pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { +pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73288,34 +70134,32 @@ pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { +pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { unsafe { - let a0: uint8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: uint8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); - transmute((a0, b0)) + let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: int8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73325,26 +70169,27 @@ pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { +pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { unsafe { - let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73354,26 +70199,32 @@ pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { +pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { unsafe { - let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) + let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: int16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73383,26 +70234,27 @@ pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { +pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73412,26 +70264,32 @@ pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { +pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { unsafe { - let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) + let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: uint8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73441,34 +70299,27 @@ pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { +pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let a0: poly8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: poly8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73478,26 +70329,32 @@ pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { +pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { unsafe { - let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) + let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: uint16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } -#[doc = "Unzip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] -#[inline(always)] +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp1) + assert_instr(zip1) )] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(uzp2) + assert_instr(zip2) )] #[cfg_attr( not(target_arch = "arm"), @@ -73507,18 +70364,20 @@ pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { +pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73527,28 +70386,33 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { +pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { unsafe { - let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: poly8x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] +#[inline] +#[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73557,29 +70421,28 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip2) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "1.94.0") + stable(feature = "neon_intrinsics", since = "1.59.0") )] #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -#[cfg(not(target_arch = "arm64ec"))] -pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { +pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73596,19 +70459,25 @@ pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { +pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { unsafe { - let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) + let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: poly16x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73625,19 +70494,20 @@ pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { +pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73654,19 +70524,25 @@ pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { +pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { unsafe { - let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) + let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: float32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73683,19 +70559,28 @@ pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { +pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73712,19 +70597,43 @@ pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { +pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { unsafe { - let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: int8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: int8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + let mut ret_val: int8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73741,19 +70650,20 @@ pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { +pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { unsafe { - let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73770,19 +70680,25 @@ pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { +pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { unsafe { - let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: int16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73799,19 +70715,20 @@ pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { +pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip1) @@ -73828,16 +70745,22 @@ pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { +pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { unsafe { - let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: int32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -73857,16 +70780,25 @@ pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { +pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -73886,24 +70818,40 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { +pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { unsafe { - let a0: int8x16_t = simd_shuffle!( + let a: uint8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint8x16_t = simd_shuffle!( a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] ); - let b0: int8x16_t = simd_shuffle!( + let b0: uint8x16_t = simd_shuffle!( a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] ); - transmute((a0, b0)) + let mut ret_val: uint8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -73923,16 +70871,17 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { +pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { unsafe { - let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -73952,16 +70901,22 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { +pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { unsafe { - let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) + let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: uint16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -73981,24 +70936,17 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { +pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let a0: uint8x16_t = simd_shuffle!( - a, - b, - [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] - ); - let b0: uint8x16_t = simd_shuffle!( - a, - b, - [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] - ); + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); transmute((a0, b0)) } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -74018,16 +70966,22 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { +pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { unsafe { - let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) + let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); + let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let mut ret_val: uint32x4x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]); + ret_val } } #[doc = "Zip vectors"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] -#[inline(always)] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -74047,16 +71001,25 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { +pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { - let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); transmute((a0, b0)) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -74078,6 +71041,10 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { )] pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { unsafe { + let a: poly8x16_t = + simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly8x16_t = + simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let a0: poly8x16_t = simd_shuffle!( a, b, @@ -74088,12 +71055,24 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] ); - transmute((a0, b0)) + let mut ret_val: poly8x16x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!( + ret_val.0, + ret_val.0, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val.1 = simd_shuffle!( + ret_val.1, + ret_val.1, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ); + ret_val } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"] -#[inline(always)] +#[inline] +#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] @@ -74120,3 +71099,38 @@ pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { transmute((a0, b0)) } } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"] +#[inline] +#[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip1) +)] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + unsafe { + let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); + let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + let mut ret_val: poly16x8x2_t = transmute((a0, b0)); + ret_val.0 = simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val.1 = simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]); + ret_val + } +} diff --git a/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs b/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs index cc821b4af2025..70a37f7c05dad 100644 --- a/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs +++ b/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs @@ -190,6 +190,24 @@ fn test_vld1q_p64() { assert_eq!(r, e) } +#[cfg(not(target_arch = "arm64ec"))] +#[simd_test(enable = "neon,fp16")] +fn test_vld1_f16() { + let a: [f16; 5] = [0., 1., 2., 3., 4.]; + let e = f16x4::new(1., 2., 3., 4.); + let r = unsafe { f16x4::from(vld1_f16(a[1..].as_ptr())) }; + assert_eq!(r, e) +} + +#[cfg(not(target_arch = "arm64ec"))] +#[simd_test(enable = "neon,fp16")] +fn test_vld1q_f16() { + let a: [f16; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; + let e = f16x8::new(1., 2., 3., 4., 5., 6., 7., 8.); + let r = unsafe { f16x8::from(vld1q_f16(a[1..].as_ptr())) }; + assert_eq!(r, e) +} + #[simd_test(enable = "neon")] fn test_vld1_f32() { let a: [f32; 3] = [0., 1., 2.]; diff --git a/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs b/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs index 8a4a6e9228221..4cc7f64f2dc29 100644 --- a/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs @@ -7,7 +7,7 @@ mod generated; #[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] pub use self::generated::*; -use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::*, mem::transmute}; +use crate::{core_arch::simd::*, intrinsics::simd::*, mem::transmute}; #[cfg(test)] use stdarch_test::assert_instr; @@ -1663,235 +1663,6 @@ mod tests { assert_eq!(r, e) } - #[simd_test(enable = "neon")] - fn test_vget_lane_u8() { - let v = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = vget_lane_u8::<1>(v.into()); - assert_eq!(r, 2); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_u32() { - let v = u32x4::new(1, 2, 3, 4); - let r = vgetq_lane_u32::<1>(v.into()); - assert_eq!(r, 2); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_s32() { - let v = i32x4::new(1, 2, 3, 4); - let r = vgetq_lane_s32::<1>(v.into()); - assert_eq!(r, 2); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_u64() { - let v = u64x1::new(1); - let r = vget_lane_u64::<0>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_u16() { - let v = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = vgetq_lane_u16::<1>(v.into()); - assert_eq!(r, 2); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_s8() { - let v = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r = vget_lane_s8::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_s8::<4>(v.into()); - assert_eq!(r, 4); - let r = vget_lane_s8::<5>(v.into()); - assert_eq!(r, 5); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_p8() { - let v = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r = vget_lane_p8::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_p8::<3>(v.into()); - assert_eq!(r, 3); - let r = vget_lane_p8::<5>(v.into()); - assert_eq!(r, 5); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_p16() { - let v = u16x4::new(0, 1, 2, 3); - let r = vget_lane_p16::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_p16::<3>(v.into()); - assert_eq!(r, 3); - let r = vget_lane_p16::<0>(v.into()); - assert_eq!(r, 0); - let r = vget_lane_p16::<1>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_s16() { - let v = i16x4::new(0, 1, 2, 3); - let r = vget_lane_s16::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_s16::<3>(v.into()); - assert_eq!(r, 3); - let r = vget_lane_s16::<0>(v.into()); - assert_eq!(r, 0); - let r = vget_lane_s16::<1>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_u16() { - let v = u16x4::new(0, 1, 2, 3); - let r = vget_lane_u16::<2>(v.into()); - assert_eq!(r, 2); - let r = vget_lane_u16::<3>(v.into()); - assert_eq!(r, 3); - let r = vget_lane_u16::<0>(v.into()); - assert_eq!(r, 0); - let r = vget_lane_u16::<1>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_f32() { - let v = f32x2::new(0.0, 1.0); - let r = vget_lane_f32::<1>(v.into()); - assert_eq!(r, 1.0); - let r = vget_lane_f32::<0>(v.into()); - assert_eq!(r, 0.0); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_s32() { - let v = i32x2::new(0, 1); - let r = vget_lane_s32::<1>(v.into()); - assert_eq!(r, 1); - let r = vget_lane_s32::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_u32() { - let v = u32x2::new(0, 1); - let r = vget_lane_u32::<1>(v.into()); - assert_eq!(r, 1); - let r = vget_lane_u32::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_s64() { - let v = i64x1::new(1); - let r = vget_lane_s64::<0>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vget_lane_p64() { - let v = u64x1::new(1); - let r = vget_lane_p64::<0>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_s8() { - let v = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = vgetq_lane_s8::<7>(v.into()); - assert_eq!(r, 7); - let r = vgetq_lane_s8::<13>(v.into()); - assert_eq!(r, 13); - let r = vgetq_lane_s8::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_s8::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_p8() { - let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = vgetq_lane_p8::<7>(v.into()); - assert_eq!(r, 7); - let r = vgetq_lane_p8::<13>(v.into()); - assert_eq!(r, 13); - let r = vgetq_lane_p8::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_p8::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_u8() { - let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = vgetq_lane_u8::<7>(v.into()); - assert_eq!(r, 7); - let r = vgetq_lane_u8::<13>(v.into()); - assert_eq!(r, 13); - let r = vgetq_lane_u8::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_u8::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_s16() { - let v = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r = vgetq_lane_s16::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_s16::<6>(v.into()); - assert_eq!(r, 6); - let r = vgetq_lane_s16::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_p16() { - let v = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r = vgetq_lane_p16::<3>(v.into()); - assert_eq!(r, 3); - let r = vgetq_lane_p16::<7>(v.into()); - assert_eq!(r, 7); - let r = vgetq_lane_p16::<1>(v.into()); - assert_eq!(r, 1); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_f32() { - let v = f32x4::new(0.0, 1.0, 2.0, 3.0); - let r = vgetq_lane_f32::<3>(v.into()); - assert_eq!(r, 3.0); - let r = vgetq_lane_f32::<0>(v.into()); - assert_eq!(r, 0.0); - let r = vgetq_lane_f32::<2>(v.into()); - assert_eq!(r, 2.0); - let r = vgetq_lane_f32::<1>(v.into()); - assert_eq!(r, 1.0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_s64() { - let v = i64x2::new(0, 1); - let r = vgetq_lane_s64::<1>(v.into()); - assert_eq!(r, 1); - let r = vgetq_lane_s64::<0>(v.into()); - assert_eq!(r, 0); - } - - #[simd_test(enable = "neon")] - fn test_vgetq_lane_p64() { - let v = u64x2::new(0, 1); - let r = vgetq_lane_p64::<1>(v.into()); - assert_eq!(r, 1); - let r = vgetq_lane_p64::<0>(v.into()); - assert_eq!(r, 0); - } - #[simd_test(enable = "neon")] fn test_vext_s64() { let a: i64x1 = i64x1::new(0); @@ -1910,182 +1681,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vget_high_s8() { - let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = i8x8::new(9, 10, 11, 12, 13, 14, 15, 16); - let r = i8x8::from(vget_high_s8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_s16() { - let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = i16x4::new(5, 6, 7, 8); - let r = i16x4::from(vget_high_s16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_s32() { - let a = i32x4::new(1, 2, 3, 4); - let e = i32x2::new(3, 4); - let r = i32x2::from(vget_high_s32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_s64() { - let a = i64x2::new(1, 2); - let e = i64x1::new(2); - let r = i64x1::from(vget_high_s64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_u8() { - let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16); - let r = u8x8::from(vget_high_u8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_u16() { - let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = u16x4::new(5, 6, 7, 8); - let r = u16x4::from(vget_high_u16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_u32() { - let a = u32x4::new(1, 2, 3, 4); - let e = u32x2::new(3, 4); - let r = u32x2::from(vget_high_u32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_u64() { - let a = u64x2::new(1, 2); - let e = u64x1::new(2); - let r = u64x1::from(vget_high_u64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_p8() { - let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16); - let r = u8x8::from(vget_high_p8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_p16() { - let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = u16x4::new(5, 6, 7, 8); - let r = u16x4::from(vget_high_p16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_high_f32() { - let a = f32x4::new(1.0, 2.0, 3.0, 4.0); - let e = f32x2::new(3.0, 4.0); - let r = f32x2::from(vget_high_f32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_s8() { - let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = i8x8::from(vget_low_s8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_s16() { - let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = i16x4::new(1, 2, 3, 4); - let r = i16x4::from(vget_low_s16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_s32() { - let a = i32x4::new(1, 2, 3, 4); - let e = i32x2::new(1, 2); - let r = i32x2::from(vget_low_s32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_s64() { - let a = i64x2::new(1, 2); - let e = i64x1::new(1); - let r = i64x1::from(vget_low_s64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_u8() { - let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = u8x8::from(vget_low_u8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_u16() { - let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = u16x4::new(1, 2, 3, 4); - let r = u16x4::from(vget_low_u16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_u32() { - let a = u32x4::new(1, 2, 3, 4); - let e = u32x2::new(1, 2); - let r = u32x2::from(vget_low_u32(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_u64() { - let a = u64x2::new(1, 2); - let e = u64x1::new(1); - let r = u64x1::from(vget_low_u64(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_p8() { - let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r = u8x8::from(vget_low_p8(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_p16() { - let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e = u16x4::new(1, 2, 3, 4); - let r = u16x4::from(vget_low_p16(a.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vget_low_f32() { - let a = f32x4::new(1.0, 2.0, 3.0, 4.0); - let e = f32x2::new(1.0, 2.0); - let r = f32x2::from(vget_low_f32(a.into())); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] fn test_vdupq_n_s8() { let v: i8 = 42; @@ -2469,13 +2064,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vgetq_lane_u64() { - let v = u64x2::new(1, 2); - let r = vgetq_lane_u64::<1>(v.into()); - assert_eq!(r, 2); - } - #[simd_test(enable = "neon")] fn test_vadd_s8() { test_ari_s8( @@ -2638,72 +2226,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vaddl_high_s8() { - let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let x = i8::MAX; - let b = i8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x); - let x = x as i16; - let e = i16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15); - let r = i16x8::from(vaddl_high_s8(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_s16() { - let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let x = i16::MAX; - let b = i16x8::new(x, x, x, x, x, x, x, x); - let x = x as i32; - let e = i32x4::new(x + 4, x + 5, x + 6, x + 7); - let r = i32x4::from(vaddl_high_s16(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_s32() { - let a = i32x4::new(0, 1, 2, 3); - let x = i32::MAX; - let b = i32x4::new(x, x, x, x); - let x = x as i64; - let e = i64x2::new(x + 2, x + 3); - let r = i64x2::from(vaddl_high_s32(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_u8() { - let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let x = u8::MAX; - let b = u8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x); - let x = x as u16; - let e = u16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15); - let r = u16x8::from(vaddl_high_u8(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_u16() { - let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let x = u16::MAX; - let b = u16x8::new(x, x, x, x, x, x, x, x); - let x = x as u32; - let e = u32x4::new(x + 4, x + 5, x + 6, x + 7); - let r = u32x4::from(vaddl_high_u16(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddl_high_u32() { - let a = u32x4::new(0, 1, 2, 3); - let x = u32::MAX; - let b = u32x4::new(x, x, x, x); - let x = x as u64; - let e = u64x2::new(x + 2, x + 3); - let r = u64x2::from(vaddl_high_u32(a.into(), b.into())); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] fn test_vaddw_s8() { let x = i16::MAX; @@ -2794,96 +2316,6 @@ mod tests { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - fn test_vaddw_high_s8() { - let x = i16::MAX; - let a = i16x8::new(x, 1, 2, 3, 4, 5, 6, 7); - let y = i8::MAX; - let b = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, y, y, y, y, y, y, y, y); - let y = y as i16; - let e = i16x8::new( - x.wrapping_add(y), - 1 + y, - 2 + y, - 3 + y, - 4 + y, - 5 + y, - 6 + y, - 7 + y, - ); - let r = i16x8::from(vaddw_high_s8(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_s16() { - let x = i32::MAX; - let a = i32x4::new(x, 1, 2, 3); - let y = i16::MAX; - let b = i16x8::new(0, 0, 0, 0, y, y, y, y); - let y = y as i32; - let e = i32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y); - let r = i32x4::from(vaddw_high_s16(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_s32() { - let x = i64::MAX; - let a = i64x2::new(x, 1); - let y = i32::MAX; - let b = i32x4::new(0, 0, y, y); - let y = y as i64; - let e = i64x2::new(x.wrapping_add(y), 1 + y); - let r = i64x2::from(vaddw_high_s32(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_u8() { - let x = u16::MAX; - let a = u16x8::new(x, 1, 2, 3, 4, 5, 6, 7); - let y = u8::MAX; - let b = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, y, y, y, y, y, y, y, y); - let y = y as u16; - let e = u16x8::new( - x.wrapping_add(y), - 1 + y, - 2 + y, - 3 + y, - 4 + y, - 5 + y, - 6 + y, - 7 + y, - ); - let r = u16x8::from(vaddw_high_u8(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_u16() { - let x = u32::MAX; - let a = u32x4::new(x, 1, 2, 3); - let y = u16::MAX; - let b = u16x8::new(0, 0, 0, 0, y, y, y, y); - let y = y as u32; - let e = u32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y); - let r = u32x4::from(vaddw_high_u16(a.into(), b.into())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - fn test_vaddw_high_u32() { - let x = u64::MAX; - let a = u64x2::new(x, 1); - let y = u32::MAX; - let b = u32x4::new(0, 0, y, y); - let y = y as u64; - let e = u64x2::new(x.wrapping_add(y), 1 + y); - let r = u64x2::from(vaddw_high_u32(a.into(), b.into())); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] fn test_vmvn_s8() { let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); @@ -5766,54 +5198,134 @@ mod tests { assert_eq!(r, e); } - macro_rules! test_vcombine { - ($test_id:ident => $fn_id:ident ([$($a:expr),*], [$($b:expr),*])) => { - #[allow(unused_assignments)] - #[simd_test(enable = "neon")] - fn $test_id() { - let a = Simd::from_array([$($a),*]); - let b = Simd::from_array([$($b),*]); - let e = Simd::from_array([$($a),* $(, $b)*]); - let c = $fn_id(a.into(), b.into()); - let mut d = e; - d = c.into(); - assert_eq!(d, e); - } + #[cfg(not(target_arch = "arm64ec"))] + mod fp16 { + use super::*; + #[simd_test(enable = "neon,fp16")] + fn test_vld1_lane_f16() { + let a = f16x4::new(0., 1., 2., 3.); + let elem: f16 = 42.; + let e = f16x4::new(0., 1., 2., 42.); + let r = unsafe { f16x4::from(vld1_lane_f16::<3>(&elem, a.into())) }; + assert_eq!(r, e) } - } - test_vcombine!(test_vcombine_s8 => vcombine_s8([3_i8, -4, 5, -6, 7, 8, 9, 10], [13_i8, -14, 15, -16, 17, 18, 19, 110])); - test_vcombine!(test_vcombine_u8 => vcombine_u8([3_u8, 4, 5, 6, 7, 8, 9, 10], [13_u8, 14, 15, 16, 17, 18, 19, 110])); - test_vcombine!(test_vcombine_p8 => vcombine_p8([3_u8, 4, 5, 6, 7, 8, 9, 10], [13_u8, 14, 15, 16, 17, 18, 19, 110])); + #[simd_test(enable = "neon,fp16")] + fn test_vld1q_lane_f16() { + let a = f16x8::new(0., 1., 2., 3., 4., 5., 6., 7.); + let elem: f16 = 42.; + let e = f16x8::new(0., 1., 2., 3., 4., 5., 6., 42.); + let r = unsafe { f16x8::from(vld1q_lane_f16::<7>(&elem, a.into())) }; + assert_eq!(r, e) + } - test_vcombine!(test_vcombine_s16 => vcombine_s16([3_i16, -4, 5, -6], [13_i16, -14, 15, -16])); - test_vcombine!(test_vcombine_u16 => vcombine_u16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16])); - test_vcombine!(test_vcombine_p16 => vcombine_p16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16])); + #[simd_test(enable = "neon,fp16")] + fn test_vld1_dup_f16() { + let elem: f16 = 42.; + let e = f16x4::new(42., 42., 42., 42.); + let r = unsafe { f16x4::from(vld1_dup_f16(&elem)) }; + assert_eq!(r, e) + } - #[cfg(not(target_arch = "arm64ec"))] - mod fp16 { - use super::*; - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,fp16"))] - #[cfg_attr(not(target_arch = "arm"), simd_test(enable = "neon"))] - fn test_vcombine_f16() { - let a = f16x4::from_array([3_f16, 4., 5., 6.]); - let b = f16x4::from_array([13_f16, 14., 15., 16.]); - let e = f16x8::from_array([3_f16, 4., 5., 6., 13_f16, 14., 15., 16.]); - let c = f16x8::from(vcombine_f16(a.into(), b.into())); - assert_eq!(c, e); + #[simd_test(enable = "neon,fp16")] + fn test_vld1q_dup_f16() { + let elem: f16 = 42.; + let e = f16x8::new(42., 42., 42., 42., 42., 42., 42., 42.); + let r = unsafe { f16x8::from(vld1q_dup_f16(&elem)) }; + assert_eq!(r, e) } } - test_vcombine!(test_vcombine_s32 => vcombine_s32([3_i32, -4], [13_i32, -14])); - test_vcombine!(test_vcombine_u32 => vcombine_u32([3_u32, 4], [13_u32, 14])); - // note: poly32x4 does not exist, and neither does vcombine_p32 - test_vcombine!(test_vcombine_f32 => vcombine_f32([3_f32, -4.], [13_f32, -14.])); - - test_vcombine!(test_vcombine_s64 => vcombine_s64([-3_i64], [13_i64])); - test_vcombine!(test_vcombine_u64 => vcombine_u64([3_u64], [13_u64])); - test_vcombine!(test_vcombine_p64 => vcombine_p64([3_u64], [13_u64])); - #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - test_vcombine!(test_vcombine_f64 => vcombine_f64([-3_f64], [13_f64])); + macro_rules! lane_wide_store_load_roundtrip { + ($elem_ty:ty, $len:expr, $idx:expr, $vec_ty:ty, $store:ident, $load:ident) => { + let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); + let a: $vec_ty = transmute(vals); + let mut tmp = [0 as $elem_ty; 4]; + $store::<$idx>(tmp.as_mut_ptr().cast(), a); + let r: $vec_ty = $load::<$idx>(tmp.as_ptr().cast(), a); + let out: [$elem_ty; $len] = transmute(r); + assert_eq!(out, vals); + }; + } + + macro_rules! lane_wide_store_load_roundtrip_neon { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics + #[simd_test(enable = "neon")] + unsafe fn $name() { + lane_wide_store_load_roundtrip! $args; + } + )* + }; + } + + macro_rules! lane_wide_store_load_roundtrip_fp16 { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[cfg_attr(miri, ignore)] // uses unsupported vendor intrinsics + #[simd_test(enable = "neon,fp16")] + #[cfg(not(target_arch = "arm64ec"))] + unsafe fn $name() { + lane_wide_store_load_roundtrip! $args; + } + )* + }; + } + + lane_wide_store_load_roundtrip_neon! { + test_vld2_lane_s8(i8, 16, 7, int8x8x2_t, vst2_lane_s8, vld2_lane_s8); + test_vld3_lane_s8(i8, 24, 7, int8x8x3_t, vst3_lane_s8, vld3_lane_s8); + test_vld4_lane_s8(i8, 32, 7, int8x8x4_t, vst4_lane_s8, vld4_lane_s8); + + test_vld2_lane_u8(u8, 16, 7, uint8x8x2_t, vst2_lane_u8, vld2_lane_u8); + test_vld3_lane_u8(u8, 24, 7, uint8x8x3_t, vst3_lane_u8, vld3_lane_u8); + test_vld4_lane_u8(u8, 32, 7, uint8x8x4_t, vst4_lane_u8, vld4_lane_u8); + + test_vld2_lane_s16(i16, 8, 3, int16x4x2_t, vst2_lane_s16, vld2_lane_s16); + test_vld3_lane_s16(i16, 12, 3, int16x4x3_t, vst3_lane_s16, vld3_lane_s16); + test_vld4_lane_s16(i16, 16, 3, int16x4x4_t, vst4_lane_s16, vld4_lane_s16); + test_vld2q_lane_s16(i16, 16, 7, int16x8x2_t, vst2q_lane_s16, vld2q_lane_s16); + test_vld3q_lane_s16(i16, 24, 7, int16x8x3_t, vst3q_lane_s16, vld3q_lane_s16); + test_vld4q_lane_s16(i16, 32, 7, int16x8x4_t, vst4q_lane_s16, vld4q_lane_s16); + + test_vld2_lane_u16(u16, 8, 3, uint16x4x2_t, vst2_lane_u16, vld2_lane_u16); + test_vld3_lane_u16(u16, 12, 3, uint16x4x3_t, vst3_lane_u16, vld3_lane_u16); + test_vld4_lane_u16(u16, 16, 3, uint16x4x4_t, vst4_lane_u16, vld4_lane_u16); + test_vld2q_lane_u16(u16, 16, 7, uint16x8x2_t, vst2q_lane_u16, vld2q_lane_u16); + test_vld3q_lane_u16(u16, 24, 7, uint16x8x3_t, vst3q_lane_u16, vld3q_lane_u16); + test_vld4q_lane_u16(u16, 32, 7, uint16x8x4_t, vst4q_lane_u16, vld4q_lane_u16); + + test_vld2_lane_s32(i32, 4, 1, int32x2x2_t, vst2_lane_s32, vld2_lane_s32); + test_vld3_lane_s32(i32, 6, 1, int32x2x3_t, vst3_lane_s32, vld3_lane_s32); + test_vld4_lane_s32(i32, 8, 1, int32x2x4_t, vst4_lane_s32, vld4_lane_s32); + test_vld2q_lane_s32(i32, 8, 3, int32x4x2_t, vst2q_lane_s32, vld2q_lane_s32); + test_vld3q_lane_s32(i32, 12, 3, int32x4x3_t, vst3q_lane_s32, vld3q_lane_s32); + test_vld4q_lane_s32(i32, 16, 3, int32x4x4_t, vst4q_lane_s32, vld4q_lane_s32); + + test_vld2_lane_u32(u32, 4, 1, uint32x2x2_t, vst2_lane_u32, vld2_lane_u32); + test_vld3_lane_u32(u32, 6, 1, uint32x2x3_t, vst3_lane_u32, vld3_lane_u32); + test_vld4_lane_u32(u32, 8, 1, uint32x2x4_t, vst4_lane_u32, vld4_lane_u32); + test_vld2q_lane_u32(u32, 8, 3, uint32x4x2_t, vst2q_lane_u32, vld2q_lane_u32); + test_vld3q_lane_u32(u32, 12, 3, uint32x4x3_t, vst3q_lane_u32, vld3q_lane_u32); + test_vld4q_lane_u32(u32, 16, 3, uint32x4x4_t, vst4q_lane_u32, vld4q_lane_u32); + + test_vld2_lane_f32(f32, 4, 1, float32x2x2_t, vst2_lane_f32, vld2_lane_f32); + test_vld3_lane_f32(f32, 6, 1, float32x2x3_t, vst3_lane_f32, vld3_lane_f32); + test_vld4_lane_f32(f32, 8, 1, float32x2x4_t, vst4_lane_f32, vld4_lane_f32); + test_vld2q_lane_f32(f32, 8, 3, float32x4x2_t, vst2q_lane_f32, vld2q_lane_f32); + test_vld3q_lane_f32(f32, 12, 3, float32x4x3_t, vst3q_lane_f32, vld3q_lane_f32); + test_vld4q_lane_f32(f32, 16, 3, float32x4x4_t, vst4q_lane_f32, vld4q_lane_f32); + } + + lane_wide_store_load_roundtrip_fp16! { + test_vld2_lane_f16(f16, 8, 3, float16x4x2_t, vst2_lane_f16, vld2_lane_f16); + test_vld3_lane_f16(f16, 12, 3, float16x4x3_t, vst3_lane_f16, vld3_lane_f16); + test_vld4_lane_f16(f16, 16, 3, float16x4x4_t, vst4_lane_f16, vld4_lane_f16); + test_vld2q_lane_f16(f16, 16, 7, float16x8x2_t, vst2q_lane_f16, vld2q_lane_f16); + test_vld3q_lane_f16(f16, 24, 7, float16x8x3_t, vst3q_lane_f16, vld3q_lane_f16); + test_vld4q_lane_f16(f16, 32, 7, float16x8x4_t, vst4q_lane_f16, vld4q_lane_f16); + } } #[cfg(all(test, target_arch = "arm"))] diff --git a/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs b/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs index 2b10b38f2dd8f..6eb60e4c78bc8 100644 --- a/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs +++ b/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs @@ -406,6 +406,44 @@ fn test_vst1q_p64() { assert_eq!(vals[2], 2); } +#[cfg(not(target_arch = "arm64ec"))] +#[simd_test(enable = "neon,fp16")] +fn test_vst1_f16() { + let mut vals = [0_f16; 5]; + let a = f16x4::new(1., 2., 3., 4.); + + unsafe { + vst1_f16(vals[1..].as_mut_ptr(), a.into()); + } + + assert_eq!(vals[0], 0.); + assert_eq!(vals[1], 1.); + assert_eq!(vals[2], 2.); + assert_eq!(vals[3], 3.); + assert_eq!(vals[4], 4.); +} + +#[cfg(not(target_arch = "arm64ec"))] +#[simd_test(enable = "neon,fp16")] +fn test_vst1q_f16() { + let mut vals = [0_f16; 9]; + let a = f16x8::new(1., 2., 3., 4., 5., 6., 7., 8.); + + unsafe { + vst1q_f16(vals[1..].as_mut_ptr(), a.into()); + } + + assert_eq!(vals[0], 0.); + assert_eq!(vals[1], 1.); + assert_eq!(vals[2], 2.); + assert_eq!(vals[3], 3.); + assert_eq!(vals[4], 4.); + assert_eq!(vals[5], 5.); + assert_eq!(vals[6], 6.); + assert_eq!(vals[7], 7.); + assert_eq!(vals[8], 8.); +} + #[simd_test(enable = "neon")] fn test_vst1_f32() { let mut vals = [0_f32; 3]; diff --git a/stdarch/crates/core_arch/src/hexagon/mod.rs b/stdarch/crates/core_arch/src/hexagon/mod.rs index c370f3da15dfb..c973f7dc62e1a 100644 --- a/stdarch/crates/core_arch/src/hexagon/mod.rs +++ b/stdarch/crates/core_arch/src/hexagon/mod.rs @@ -1,13 +1,18 @@ //! Hexagon architecture intrinsics //! //! This module contains intrinsics for the Qualcomm Hexagon DSP architecture, -//! including the Hexagon Vector Extensions (HVX). +//! including scalar operations and the Hexagon Vector Extensions (HVX). +//! +//! ## Scalar Intrinsics +//! +//! The [`scalar`] module provides intrinsics for scalar DSP operations including +//! arithmetic, multiply, shift, saturate, compare, and floating-point operations. +//! +//! ## HVX Vector Intrinsics //! //! HVX is a wide SIMD architecture designed for high-performance signal processing, //! machine learning, and image processing workloads. //! -//! ## Vector Length Modes -//! //! HVX supports two vector length modes: //! - 64-byte mode (512-bit vectors): Use the [`v64`] module //! - 128-byte mode (1024-bit vectors): Use the [`v128`] module @@ -20,6 +25,10 @@ //! Note that HVX v66 and later default to 128-byte mode, while earlier versions //! (v60-v65) default to 64-byte mode. +/// Scalar intrinsics for Hexagon DSP operations +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub mod scalar; + /// HVX intrinsics for 64-byte vector mode (512-bit vectors) #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub mod v64; diff --git a/stdarch/crates/core_arch/src/hexagon/scalar.rs b/stdarch/crates/core_arch/src/hexagon/scalar.rs new file mode 100644 index 0000000000000..477414de74b85 --- /dev/null +++ b/stdarch/crates/core_arch/src/hexagon/scalar.rs @@ -0,0 +1,12181 @@ +//! Hexagon scalar intrinsics +//! +//! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations, +//! including arithmetic, multiply, shift, saturate, compare, and floating-point +//! operations. +//! +//! [Hexagon V68 Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-45) +//! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `P` (uppercase) = 64-bit register pair (`Word64`) +//! - `p` (lowercase) = predicate register (`Byte`) +//! +//! For example, `Q6_P_and_PP` operates on 64-bit pairs while `Q6_p_and_pp` +//! operates on predicate registers. +//! +//! ## Architecture Versions +//! +//! Most scalar intrinsics are available on all Hexagon architectures. +//! Some intrinsics require specific architecture versions (v60, v62, v65, +//! v66, v67, v68, or v67+audio) and carry +//! `#[target_feature(enable = "v68")]` (or the appropriate version). +//! Enable these with `-C target-feature=+v68` or by setting the target CPU +//! via `-C target-cpu=hexagonv68`. +//! +//! Each version includes all features from previous versions. + +#![allow(non_snake_case)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +// LLVM intrinsic declarations for Hexagon scalar operations +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.hexagon.A2.abs"] + fn hexagon_A2_abs(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.absp"] + fn hexagon_A2_absp(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.abssat"] + fn hexagon_A2_abssat(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.add"] + fn hexagon_A2_add(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.hh"] + fn hexagon_A2_addh_h16_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.hl"] + fn hexagon_A2_addh_h16_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.lh"] + fn hexagon_A2_addh_h16_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.ll"] + fn hexagon_A2_addh_h16_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.sat.hh"] + fn hexagon_A2_addh_h16_sat_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.sat.hl"] + fn hexagon_A2_addh_h16_sat_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.sat.lh"] + fn hexagon_A2_addh_h16_sat_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.h16.sat.ll"] + fn hexagon_A2_addh_h16_sat_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.l16.hl"] + fn hexagon_A2_addh_l16_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.l16.ll"] + fn hexagon_A2_addh_l16_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.l16.sat.hl"] + fn hexagon_A2_addh_l16_sat_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addh.l16.sat.ll"] + fn hexagon_A2_addh_l16_sat_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addi"] + fn hexagon_A2_addi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addp"] + fn hexagon_A2_addp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.addpsat"] + fn hexagon_A2_addpsat(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.addsat"] + fn hexagon_A2_addsat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.addsp"] + fn hexagon_A2_addsp(_: i32, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.and"] + fn hexagon_A2_and(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.andir"] + fn hexagon_A2_andir(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.andp"] + fn hexagon_A2_andp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.aslh"] + fn hexagon_A2_aslh(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.asrh"] + fn hexagon_A2_asrh(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combine.hh"] + fn hexagon_A2_combine_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combine.hl"] + fn hexagon_A2_combine_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combine.lh"] + fn hexagon_A2_combine_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combine.ll"] + fn hexagon_A2_combine_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.combineii"] + fn hexagon_A2_combineii(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A2.combinew"] + fn hexagon_A2_combinew(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A2.max"] + fn hexagon_A2_max(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.maxp"] + fn hexagon_A2_maxp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.maxu"] + fn hexagon_A2_maxu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.maxup"] + fn hexagon_A2_maxup(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.min"] + fn hexagon_A2_min(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.minp"] + fn hexagon_A2_minp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.minu"] + fn hexagon_A2_minu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.minup"] + fn hexagon_A2_minup(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.neg"] + fn hexagon_A2_neg(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.negp"] + fn hexagon_A2_negp(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.negsat"] + fn hexagon_A2_negsat(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.not"] + fn hexagon_A2_not(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.notp"] + fn hexagon_A2_notp(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.or"] + fn hexagon_A2_or(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.orir"] + fn hexagon_A2_orir(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.orp"] + fn hexagon_A2_orp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.roundsat"] + fn hexagon_A2_roundsat(_: i64) -> i32; + #[link_name = "llvm.hexagon.A2.sat"] + fn hexagon_A2_sat(_: i64) -> i32; + #[link_name = "llvm.hexagon.A2.satb"] + fn hexagon_A2_satb(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sath"] + fn hexagon_A2_sath(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.satub"] + fn hexagon_A2_satub(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.satuh"] + fn hexagon_A2_satuh(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sub"] + fn hexagon_A2_sub(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.hh"] + fn hexagon_A2_subh_h16_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.hl"] + fn hexagon_A2_subh_h16_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.lh"] + fn hexagon_A2_subh_h16_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.ll"] + fn hexagon_A2_subh_h16_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.sat.hh"] + fn hexagon_A2_subh_h16_sat_hh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.sat.hl"] + fn hexagon_A2_subh_h16_sat_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.sat.lh"] + fn hexagon_A2_subh_h16_sat_lh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.h16.sat.ll"] + fn hexagon_A2_subh_h16_sat_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.l16.hl"] + fn hexagon_A2_subh_l16_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.l16.ll"] + fn hexagon_A2_subh_l16_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.l16.sat.hl"] + fn hexagon_A2_subh_l16_sat_hl(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subh.l16.sat.ll"] + fn hexagon_A2_subh_l16_sat_ll(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subp"] + fn hexagon_A2_subp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.subri"] + fn hexagon_A2_subri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.subsat"] + fn hexagon_A2_subsat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svaddh"] + fn hexagon_A2_svaddh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svaddhs"] + fn hexagon_A2_svaddhs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svadduhs"] + fn hexagon_A2_svadduhs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svavgh"] + fn hexagon_A2_svavgh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svavghs"] + fn hexagon_A2_svavghs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svnavgh"] + fn hexagon_A2_svnavgh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svsubh"] + fn hexagon_A2_svsubh(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svsubhs"] + fn hexagon_A2_svsubhs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.svsubuhs"] + fn hexagon_A2_svsubuhs(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.swiz"] + fn hexagon_A2_swiz(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sxtb"] + fn hexagon_A2_sxtb(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sxth"] + fn hexagon_A2_sxth(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.sxtw"] + fn hexagon_A2_sxtw(_: i32) -> i64; + #[link_name = "llvm.hexagon.A2.tfr"] + fn hexagon_A2_tfr(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.tfrih"] + fn hexagon_A2_tfrih(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.tfril"] + fn hexagon_A2_tfril(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.tfrp"] + fn hexagon_A2_tfrp(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.tfrpi"] + fn hexagon_A2_tfrpi(_: i32) -> i64; + #[link_name = "llvm.hexagon.A2.tfrsi"] + fn hexagon_A2_tfrsi(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.vabsh"] + fn hexagon_A2_vabsh(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vabshsat"] + fn hexagon_A2_vabshsat(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vabsw"] + fn hexagon_A2_vabsw(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vabswsat"] + fn hexagon_A2_vabswsat(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddb.map"] + fn hexagon_A2_vaddb_map(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddh"] + fn hexagon_A2_vaddh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddhs"] + fn hexagon_A2_vaddhs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddub"] + fn hexagon_A2_vaddub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddubs"] + fn hexagon_A2_vaddubs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vadduhs"] + fn hexagon_A2_vadduhs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddw"] + fn hexagon_A2_vaddw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vaddws"] + fn hexagon_A2_vaddws(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgh"] + fn hexagon_A2_vavgh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavghcr"] + fn hexagon_A2_vavghcr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavghr"] + fn hexagon_A2_vavghr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgub"] + fn hexagon_A2_vavgub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgubr"] + fn hexagon_A2_vavgubr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavguh"] + fn hexagon_A2_vavguh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavguhr"] + fn hexagon_A2_vavguhr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavguw"] + fn hexagon_A2_vavguw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavguwr"] + fn hexagon_A2_vavguwr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgw"] + fn hexagon_A2_vavgw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgwcr"] + fn hexagon_A2_vavgwcr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vavgwr"] + fn hexagon_A2_vavgwr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vcmpbeq"] + fn hexagon_A2_vcmpbeq(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpbgtu"] + fn hexagon_A2_vcmpbgtu(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpheq"] + fn hexagon_A2_vcmpheq(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmphgt"] + fn hexagon_A2_vcmphgt(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmphgtu"] + fn hexagon_A2_vcmphgtu(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpweq"] + fn hexagon_A2_vcmpweq(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpwgt"] + fn hexagon_A2_vcmpwgt(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vcmpwgtu"] + fn hexagon_A2_vcmpwgtu(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A2.vconj"] + fn hexagon_A2_vconj(_: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxb"] + fn hexagon_A2_vmaxb(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxh"] + fn hexagon_A2_vmaxh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxub"] + fn hexagon_A2_vmaxub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxuh"] + fn hexagon_A2_vmaxuh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxuw"] + fn hexagon_A2_vmaxuw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vmaxw"] + fn hexagon_A2_vmaxw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminb"] + fn hexagon_A2_vminb(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminh"] + fn hexagon_A2_vminh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminub"] + fn hexagon_A2_vminub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminuh"] + fn hexagon_A2_vminuh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminuw"] + fn hexagon_A2_vminuw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vminw"] + fn hexagon_A2_vminw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavgh"] + fn hexagon_A2_vnavgh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavghcr"] + fn hexagon_A2_vnavghcr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavghr"] + fn hexagon_A2_vnavghr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavgw"] + fn hexagon_A2_vnavgw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavgwcr"] + fn hexagon_A2_vnavgwcr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vnavgwr"] + fn hexagon_A2_vnavgwr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vraddub"] + fn hexagon_A2_vraddub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vraddub.acc"] + fn hexagon_A2_vraddub_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vrsadub"] + fn hexagon_A2_vrsadub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vrsadub.acc"] + fn hexagon_A2_vrsadub_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubb.map"] + fn hexagon_A2_vsubb_map(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubh"] + fn hexagon_A2_vsubh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubhs"] + fn hexagon_A2_vsubhs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubub"] + fn hexagon_A2_vsubub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsububs"] + fn hexagon_A2_vsububs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubuhs"] + fn hexagon_A2_vsubuhs(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubw"] + fn hexagon_A2_vsubw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.vsubws"] + fn hexagon_A2_vsubws(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.xor"] + fn hexagon_A2_xor(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A2.xorp"] + fn hexagon_A2_xorp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A2.zxtb"] + fn hexagon_A2_zxtb(_: i32) -> i32; + #[link_name = "llvm.hexagon.A2.zxth"] + fn hexagon_A2_zxth(_: i32) -> i32; + #[link_name = "llvm.hexagon.A4.andn"] + fn hexagon_A4_andn(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.andnp"] + fn hexagon_A4_andnp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A4.bitsplit"] + fn hexagon_A4_bitsplit(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.bitspliti"] + fn hexagon_A4_bitspliti(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.boundscheck"] + fn hexagon_A4_boundscheck(_: i32, _: i64) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbeq"] + fn hexagon_A4_cmpbeq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbeqi"] + fn hexagon_A4_cmpbeqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbgt"] + fn hexagon_A4_cmpbgt(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbgti"] + fn hexagon_A4_cmpbgti(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbgtu"] + fn hexagon_A4_cmpbgtu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpbgtui"] + fn hexagon_A4_cmpbgtui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpheq"] + fn hexagon_A4_cmpheq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmpheqi"] + fn hexagon_A4_cmpheqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmphgt"] + fn hexagon_A4_cmphgt(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmphgti"] + fn hexagon_A4_cmphgti(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmphgtu"] + fn hexagon_A4_cmphgtu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cmphgtui"] + fn hexagon_A4_cmphgtui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.combineir"] + fn hexagon_A4_combineir(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.combineri"] + fn hexagon_A4_combineri(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.cround.ri"] + fn hexagon_A4_cround_ri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.cround.rr"] + fn hexagon_A4_cround_rr(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.modwrapu"] + fn hexagon_A4_modwrapu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.orn"] + fn hexagon_A4_orn(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.ornp"] + fn hexagon_A4_ornp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A4.rcmpeq"] + fn hexagon_A4_rcmpeq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.rcmpeqi"] + fn hexagon_A4_rcmpeqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.rcmpneq"] + fn hexagon_A4_rcmpneq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.rcmpneqi"] + fn hexagon_A4_rcmpneqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.round.ri"] + fn hexagon_A4_round_ri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.round.ri.sat"] + fn hexagon_A4_round_ri_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.round.rr"] + fn hexagon_A4_round_rr(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.round.rr.sat"] + fn hexagon_A4_round_rr_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.tlbmatch"] + fn hexagon_A4_tlbmatch(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbeq.any"] + fn hexagon_A4_vcmpbeq_any(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbeqi"] + fn hexagon_A4_vcmpbeqi(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbgt"] + fn hexagon_A4_vcmpbgt(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbgti"] + fn hexagon_A4_vcmpbgti(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpbgtui"] + fn hexagon_A4_vcmpbgtui(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpheqi"] + fn hexagon_A4_vcmpheqi(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmphgti"] + fn hexagon_A4_vcmphgti(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmphgtui"] + fn hexagon_A4_vcmphgtui(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpweqi"] + fn hexagon_A4_vcmpweqi(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpwgti"] + fn hexagon_A4_vcmpwgti(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vcmpwgtui"] + fn hexagon_A4_vcmpwgtui(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.A4.vrmaxh"] + fn hexagon_A4_vrmaxh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrmaxuh"] + fn hexagon_A4_vrmaxuh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrmaxuw"] + fn hexagon_A4_vrmaxuw(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrmaxw"] + fn hexagon_A4_vrmaxw(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrminh"] + fn hexagon_A4_vrminh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrminuh"] + fn hexagon_A4_vrminuh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrminuw"] + fn hexagon_A4_vrminuw(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A4.vrminw"] + fn hexagon_A4_vrminw(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A5.vaddhubs"] + fn hexagon_A5_vaddhubs(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.C2.all8"] + fn hexagon_C2_all8(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.and"] + fn hexagon_C2_and(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.andn"] + fn hexagon_C2_andn(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.any8"] + fn hexagon_C2_any8(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.bitsclr"] + fn hexagon_C2_bitsclr(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.bitsclri"] + fn hexagon_C2_bitsclri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.bitsset"] + fn hexagon_C2_bitsset(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpeq"] + fn hexagon_C2_cmpeq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpeqi"] + fn hexagon_C2_cmpeqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpeqp"] + fn hexagon_C2_cmpeqp(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgei"] + fn hexagon_C2_cmpgei(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgeui"] + fn hexagon_C2_cmpgeui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgt"] + fn hexagon_C2_cmpgt(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgti"] + fn hexagon_C2_cmpgti(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgtp"] + fn hexagon_C2_cmpgtp(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgtu"] + fn hexagon_C2_cmpgtu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgtui"] + fn hexagon_C2_cmpgtui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpgtup"] + fn hexagon_C2_cmpgtup(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.C2.cmplt"] + fn hexagon_C2_cmplt(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.cmpltu"] + fn hexagon_C2_cmpltu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.mask"] + fn hexagon_C2_mask(_: i32) -> i64; + #[link_name = "llvm.hexagon.C2.mux"] + fn hexagon_C2_mux(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.muxii"] + fn hexagon_C2_muxii(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.muxir"] + fn hexagon_C2_muxir(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.muxri"] + fn hexagon_C2_muxri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.not"] + fn hexagon_C2_not(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.or"] + fn hexagon_C2_or(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.orn"] + fn hexagon_C2_orn(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.pxfer.map"] + fn hexagon_C2_pxfer_map(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.tfrpr"] + fn hexagon_C2_tfrpr(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.tfrrp"] + fn hexagon_C2_tfrrp(_: i32) -> i32; + #[link_name = "llvm.hexagon.C2.vitpack"] + fn hexagon_C2_vitpack(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C2.vmux"] + fn hexagon_C2_vmux(_: i32, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.C2.xor"] + fn hexagon_C2_xor(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.and.and"] + fn hexagon_C4_and_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.and.andn"] + fn hexagon_C4_and_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.and.or"] + fn hexagon_C4_and_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.and.orn"] + fn hexagon_C4_and_orn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmplte"] + fn hexagon_C4_cmplte(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmpltei"] + fn hexagon_C4_cmpltei(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmplteu"] + fn hexagon_C4_cmplteu(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmplteui"] + fn hexagon_C4_cmplteui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmpneq"] + fn hexagon_C4_cmpneq(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.cmpneqi"] + fn hexagon_C4_cmpneqi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.fastcorner9"] + fn hexagon_C4_fastcorner9(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.fastcorner9.not"] + fn hexagon_C4_fastcorner9_not(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.nbitsclr"] + fn hexagon_C4_nbitsclr(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.nbitsclri"] + fn hexagon_C4_nbitsclri(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.nbitsset"] + fn hexagon_C4_nbitsset(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.or.and"] + fn hexagon_C4_or_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.or.andn"] + fn hexagon_C4_or_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.or.or"] + fn hexagon_C4_or_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.C4.or.orn"] + fn hexagon_C4_or_orn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.d2df"] + fn hexagon_F2_conv_d2df(_: i64) -> f64; + #[link_name = "llvm.hexagon.F2.conv.d2sf"] + fn hexagon_F2_conv_d2sf(_: i64) -> f32; + #[link_name = "llvm.hexagon.F2.conv.df2d"] + fn hexagon_F2_conv_df2d(_: f64) -> i64; + #[link_name = "llvm.hexagon.F2.conv.df2d.chop"] + fn hexagon_F2_conv_df2d_chop(_: f64) -> i64; + #[link_name = "llvm.hexagon.F2.conv.df2sf"] + fn hexagon_F2_conv_df2sf(_: f64) -> f32; + #[link_name = "llvm.hexagon.F2.conv.df2ud"] + fn hexagon_F2_conv_df2ud(_: f64) -> i64; + #[link_name = "llvm.hexagon.F2.conv.df2ud.chop"] + fn hexagon_F2_conv_df2ud_chop(_: f64) -> i64; + #[link_name = "llvm.hexagon.F2.conv.df2uw"] + fn hexagon_F2_conv_df2uw(_: f64) -> i32; + #[link_name = "llvm.hexagon.F2.conv.df2uw.chop"] + fn hexagon_F2_conv_df2uw_chop(_: f64) -> i32; + #[link_name = "llvm.hexagon.F2.conv.df2w"] + fn hexagon_F2_conv_df2w(_: f64) -> i32; + #[link_name = "llvm.hexagon.F2.conv.df2w.chop"] + fn hexagon_F2_conv_df2w_chop(_: f64) -> i32; + #[link_name = "llvm.hexagon.F2.conv.sf2d"] + fn hexagon_F2_conv_sf2d(_: f32) -> i64; + #[link_name = "llvm.hexagon.F2.conv.sf2d.chop"] + fn hexagon_F2_conv_sf2d_chop(_: f32) -> i64; + #[link_name = "llvm.hexagon.F2.conv.sf2df"] + fn hexagon_F2_conv_sf2df(_: f32) -> f64; + #[link_name = "llvm.hexagon.F2.conv.sf2ud"] + fn hexagon_F2_conv_sf2ud(_: f32) -> i64; + #[link_name = "llvm.hexagon.F2.conv.sf2ud.chop"] + fn hexagon_F2_conv_sf2ud_chop(_: f32) -> i64; + #[link_name = "llvm.hexagon.F2.conv.sf2uw"] + fn hexagon_F2_conv_sf2uw(_: f32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.sf2uw.chop"] + fn hexagon_F2_conv_sf2uw_chop(_: f32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.sf2w"] + fn hexagon_F2_conv_sf2w(_: f32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.sf2w.chop"] + fn hexagon_F2_conv_sf2w_chop(_: f32) -> i32; + #[link_name = "llvm.hexagon.F2.conv.ud2df"] + fn hexagon_F2_conv_ud2df(_: i64) -> f64; + #[link_name = "llvm.hexagon.F2.conv.ud2sf"] + fn hexagon_F2_conv_ud2sf(_: i64) -> f32; + #[link_name = "llvm.hexagon.F2.conv.uw2df"] + fn hexagon_F2_conv_uw2df(_: i32) -> f64; + #[link_name = "llvm.hexagon.F2.conv.uw2sf"] + fn hexagon_F2_conv_uw2sf(_: i32) -> f32; + #[link_name = "llvm.hexagon.F2.conv.w2df"] + fn hexagon_F2_conv_w2df(_: i32) -> f64; + #[link_name = "llvm.hexagon.F2.conv.w2sf"] + fn hexagon_F2_conv_w2sf(_: i32) -> f32; + #[link_name = "llvm.hexagon.F2.dfclass"] + fn hexagon_F2_dfclass(_: f64, _: i32) -> i32; + #[link_name = "llvm.hexagon.F2.dfcmpeq"] + fn hexagon_F2_dfcmpeq(_: f64, _: f64) -> i32; + #[link_name = "llvm.hexagon.F2.dfcmpge"] + fn hexagon_F2_dfcmpge(_: f64, _: f64) -> i32; + #[link_name = "llvm.hexagon.F2.dfcmpgt"] + fn hexagon_F2_dfcmpgt(_: f64, _: f64) -> i32; + #[link_name = "llvm.hexagon.F2.dfcmpuo"] + fn hexagon_F2_dfcmpuo(_: f64, _: f64) -> i32; + #[link_name = "llvm.hexagon.F2.dfimm.n"] + fn hexagon_F2_dfimm_n(_: i32) -> f64; + #[link_name = "llvm.hexagon.F2.dfimm.p"] + fn hexagon_F2_dfimm_p(_: i32) -> f64; + #[link_name = "llvm.hexagon.F2.sfadd"] + fn hexagon_F2_sfadd(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfclass"] + fn hexagon_F2_sfclass(_: f32, _: i32) -> i32; + #[link_name = "llvm.hexagon.F2.sfcmpeq"] + fn hexagon_F2_sfcmpeq(_: f32, _: f32) -> i32; + #[link_name = "llvm.hexagon.F2.sfcmpge"] + fn hexagon_F2_sfcmpge(_: f32, _: f32) -> i32; + #[link_name = "llvm.hexagon.F2.sfcmpgt"] + fn hexagon_F2_sfcmpgt(_: f32, _: f32) -> i32; + #[link_name = "llvm.hexagon.F2.sfcmpuo"] + fn hexagon_F2_sfcmpuo(_: f32, _: f32) -> i32; + #[link_name = "llvm.hexagon.F2.sffixupd"] + fn hexagon_F2_sffixupd(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffixupn"] + fn hexagon_F2_sffixupn(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffixupr"] + fn hexagon_F2_sffixupr(_: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffma"] + fn hexagon_F2_sffma(_: f32, _: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffma.lib"] + fn hexagon_F2_sffma_lib(_: f32, _: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffma.sc"] + fn hexagon_F2_sffma_sc(_: f32, _: f32, _: f32, _: i32) -> f32; + #[link_name = "llvm.hexagon.F2.sffms"] + fn hexagon_F2_sffms(_: f32, _: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sffms.lib"] + fn hexagon_F2_sffms_lib(_: f32, _: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfimm.n"] + fn hexagon_F2_sfimm_n(_: i32) -> f32; + #[link_name = "llvm.hexagon.F2.sfimm.p"] + fn hexagon_F2_sfimm_p(_: i32) -> f32; + #[link_name = "llvm.hexagon.F2.sfmax"] + fn hexagon_F2_sfmax(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfmin"] + fn hexagon_F2_sfmin(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfmpy"] + fn hexagon_F2_sfmpy(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.F2.sfsub"] + fn hexagon_F2_sfsub(_: f32, _: f32) -> f32; + #[link_name = "llvm.hexagon.M2.acci"] + fn hexagon_M2_acci(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.accii"] + fn hexagon_M2_accii(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmaci.s0"] + fn hexagon_M2_cmaci_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacr.s0"] + fn hexagon_M2_cmacr_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacs.s0"] + fn hexagon_M2_cmacs_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacs.s1"] + fn hexagon_M2_cmacs_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacsc.s0"] + fn hexagon_M2_cmacsc_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmacsc.s1"] + fn hexagon_M2_cmacsc_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpyi.s0"] + fn hexagon_M2_cmpyi_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpyr.s0"] + fn hexagon_M2_cmpyr_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpyrs.s0"] + fn hexagon_M2_cmpyrs_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmpyrs.s1"] + fn hexagon_M2_cmpyrs_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmpyrsc.s0"] + fn hexagon_M2_cmpyrsc_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmpyrsc.s1"] + fn hexagon_M2_cmpyrsc_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.cmpys.s0"] + fn hexagon_M2_cmpys_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpys.s1"] + fn hexagon_M2_cmpys_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpysc.s0"] + fn hexagon_M2_cmpysc_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cmpysc.s1"] + fn hexagon_M2_cmpysc_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cnacs.s0"] + fn hexagon_M2_cnacs_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cnacs.s1"] + fn hexagon_M2_cnacs_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cnacsc.s0"] + fn hexagon_M2_cnacsc_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.cnacsc.s1"] + fn hexagon_M2_cnacsc_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyss.acc.s0"] + fn hexagon_M2_dpmpyss_acc_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyss.nac.s0"] + fn hexagon_M2_dpmpyss_nac_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyss.rnd.s0"] + fn hexagon_M2_dpmpyss_rnd_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.dpmpyss.s0"] + fn hexagon_M2_dpmpyss_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyuu.acc.s0"] + fn hexagon_M2_dpmpyuu_acc_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyuu.nac.s0"] + fn hexagon_M2_dpmpyuu_nac_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.dpmpyuu.s0"] + fn hexagon_M2_dpmpyuu_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.hmmpyh.rs1"] + fn hexagon_M2_hmmpyh_rs1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.hmmpyh.s1"] + fn hexagon_M2_hmmpyh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.hmmpyl.rs1"] + fn hexagon_M2_hmmpyl_rs1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.hmmpyl.s1"] + fn hexagon_M2_hmmpyl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.maci"] + fn hexagon_M2_maci(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.macsin"] + fn hexagon_M2_macsin(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.macsip"] + fn hexagon_M2_macsip(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mmachs.rs0"] + fn hexagon_M2_mmachs_rs0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmachs.rs1"] + fn hexagon_M2_mmachs_rs1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmachs.s0"] + fn hexagon_M2_mmachs_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmachs.s1"] + fn hexagon_M2_mmachs_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacls.rs0"] + fn hexagon_M2_mmacls_rs0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacls.rs1"] + fn hexagon_M2_mmacls_rs1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacls.s0"] + fn hexagon_M2_mmacls_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacls.s1"] + fn hexagon_M2_mmacls_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacuhs.rs0"] + fn hexagon_M2_mmacuhs_rs0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacuhs.rs1"] + fn hexagon_M2_mmacuhs_rs1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacuhs.s0"] + fn hexagon_M2_mmacuhs_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmacuhs.s1"] + fn hexagon_M2_mmacuhs_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmaculs.rs0"] + fn hexagon_M2_mmaculs_rs0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmaculs.rs1"] + fn hexagon_M2_mmaculs_rs1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmaculs.s0"] + fn hexagon_M2_mmaculs_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmaculs.s1"] + fn hexagon_M2_mmaculs_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyh.rs0"] + fn hexagon_M2_mmpyh_rs0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyh.rs1"] + fn hexagon_M2_mmpyh_rs1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyh.s0"] + fn hexagon_M2_mmpyh_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyh.s1"] + fn hexagon_M2_mmpyh_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyl.rs0"] + fn hexagon_M2_mmpyl_rs0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyl.rs1"] + fn hexagon_M2_mmpyl_rs1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyl.s0"] + fn hexagon_M2_mmpyl_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyl.s1"] + fn hexagon_M2_mmpyl_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyuh.rs0"] + fn hexagon_M2_mmpyuh_rs0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyuh.rs1"] + fn hexagon_M2_mmpyuh_rs1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyuh.s0"] + fn hexagon_M2_mmpyuh_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyuh.s1"] + fn hexagon_M2_mmpyuh_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyul.rs0"] + fn hexagon_M2_mmpyul_rs0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyul.rs1"] + fn hexagon_M2_mmpyul_rs1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyul.s0"] + fn hexagon_M2_mmpyul_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mmpyul.s1"] + fn hexagon_M2_mmpyul_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s0"] + fn hexagon_M2_mpy_acc_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s1"] + fn hexagon_M2_mpy_acc_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s0"] + fn hexagon_M2_mpy_acc_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s1"] + fn hexagon_M2_mpy_acc_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s0"] + fn hexagon_M2_mpy_acc_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s1"] + fn hexagon_M2_mpy_acc_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s0"] + fn hexagon_M2_mpy_acc_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s1"] + fn hexagon_M2_mpy_acc_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s0"] + fn hexagon_M2_mpy_acc_sat_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s1"] + fn hexagon_M2_mpy_acc_sat_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s0"] + fn hexagon_M2_mpy_acc_sat_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s1"] + fn hexagon_M2_mpy_acc_sat_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s0"] + fn hexagon_M2_mpy_acc_sat_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s1"] + fn hexagon_M2_mpy_acc_sat_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s0"] + fn hexagon_M2_mpy_acc_sat_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s1"] + fn hexagon_M2_mpy_acc_sat_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.hh.s0"] + fn hexagon_M2_mpy_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.hh.s1"] + fn hexagon_M2_mpy_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.hl.s0"] + fn hexagon_M2_mpy_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.hl.s1"] + fn hexagon_M2_mpy_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.lh.s0"] + fn hexagon_M2_mpy_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.lh.s1"] + fn hexagon_M2_mpy_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.ll.s0"] + fn hexagon_M2_mpy_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.ll.s1"] + fn hexagon_M2_mpy_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s0"] + fn hexagon_M2_mpy_nac_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s1"] + fn hexagon_M2_mpy_nac_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s0"] + fn hexagon_M2_mpy_nac_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s1"] + fn hexagon_M2_mpy_nac_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s0"] + fn hexagon_M2_mpy_nac_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s1"] + fn hexagon_M2_mpy_nac_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s0"] + fn hexagon_M2_mpy_nac_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s1"] + fn hexagon_M2_mpy_nac_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s0"] + fn hexagon_M2_mpy_nac_sat_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s1"] + fn hexagon_M2_mpy_nac_sat_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s0"] + fn hexagon_M2_mpy_nac_sat_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s1"] + fn hexagon_M2_mpy_nac_sat_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s0"] + fn hexagon_M2_mpy_nac_sat_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s1"] + fn hexagon_M2_mpy_nac_sat_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s0"] + fn hexagon_M2_mpy_nac_sat_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s1"] + fn hexagon_M2_mpy_nac_sat_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s0"] + fn hexagon_M2_mpy_rnd_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s1"] + fn hexagon_M2_mpy_rnd_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s0"] + fn hexagon_M2_mpy_rnd_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s1"] + fn hexagon_M2_mpy_rnd_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s0"] + fn hexagon_M2_mpy_rnd_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s1"] + fn hexagon_M2_mpy_rnd_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s0"] + fn hexagon_M2_mpy_rnd_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s1"] + fn hexagon_M2_mpy_rnd_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s0"] + fn hexagon_M2_mpy_sat_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s1"] + fn hexagon_M2_mpy_sat_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s0"] + fn hexagon_M2_mpy_sat_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s1"] + fn hexagon_M2_mpy_sat_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s0"] + fn hexagon_M2_mpy_sat_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s1"] + fn hexagon_M2_mpy_sat_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s0"] + fn hexagon_M2_mpy_sat_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s1"] + fn hexagon_M2_mpy_sat_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s0"] + fn hexagon_M2_mpy_sat_rnd_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s1"] + fn hexagon_M2_mpy_sat_rnd_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s0"] + fn hexagon_M2_mpy_sat_rnd_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s1"] + fn hexagon_M2_mpy_sat_rnd_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s0"] + fn hexagon_M2_mpy_sat_rnd_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s1"] + fn hexagon_M2_mpy_sat_rnd_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s0"] + fn hexagon_M2_mpy_sat_rnd_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s1"] + fn hexagon_M2_mpy_sat_rnd_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.up"] + fn hexagon_M2_mpy_up(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.up.s1"] + fn hexagon_M2_mpy_up_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpy.up.s1.sat"] + fn hexagon_M2_mpy_up_s1_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s0"] + fn hexagon_M2_mpyd_acc_hh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s1"] + fn hexagon_M2_mpyd_acc_hh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s0"] + fn hexagon_M2_mpyd_acc_hl_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s1"] + fn hexagon_M2_mpyd_acc_hl_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s0"] + fn hexagon_M2_mpyd_acc_lh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s1"] + fn hexagon_M2_mpyd_acc_lh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s0"] + fn hexagon_M2_mpyd_acc_ll_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s1"] + fn hexagon_M2_mpyd_acc_ll_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.hh.s0"] + fn hexagon_M2_mpyd_hh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.hh.s1"] + fn hexagon_M2_mpyd_hh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.hl.s0"] + fn hexagon_M2_mpyd_hl_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.hl.s1"] + fn hexagon_M2_mpyd_hl_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.lh.s0"] + fn hexagon_M2_mpyd_lh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.lh.s1"] + fn hexagon_M2_mpyd_lh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.ll.s0"] + fn hexagon_M2_mpyd_ll_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.ll.s1"] + fn hexagon_M2_mpyd_ll_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s0"] + fn hexagon_M2_mpyd_nac_hh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s1"] + fn hexagon_M2_mpyd_nac_hh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s0"] + fn hexagon_M2_mpyd_nac_hl_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s1"] + fn hexagon_M2_mpyd_nac_hl_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s0"] + fn hexagon_M2_mpyd_nac_lh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s1"] + fn hexagon_M2_mpyd_nac_lh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s0"] + fn hexagon_M2_mpyd_nac_ll_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s1"] + fn hexagon_M2_mpyd_nac_ll_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s0"] + fn hexagon_M2_mpyd_rnd_hh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s1"] + fn hexagon_M2_mpyd_rnd_hh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s0"] + fn hexagon_M2_mpyd_rnd_hl_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s1"] + fn hexagon_M2_mpyd_rnd_hl_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s0"] + fn hexagon_M2_mpyd_rnd_lh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s1"] + fn hexagon_M2_mpyd_rnd_lh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s0"] + fn hexagon_M2_mpyd_rnd_ll_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s1"] + fn hexagon_M2_mpyd_rnd_ll_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyi"] + fn hexagon_M2_mpyi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpysmi"] + fn hexagon_M2_mpysmi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpysu.up"] + fn hexagon_M2_mpysu_up(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s0"] + fn hexagon_M2_mpyu_acc_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s1"] + fn hexagon_M2_mpyu_acc_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s0"] + fn hexagon_M2_mpyu_acc_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s1"] + fn hexagon_M2_mpyu_acc_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s0"] + fn hexagon_M2_mpyu_acc_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s1"] + fn hexagon_M2_mpyu_acc_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s0"] + fn hexagon_M2_mpyu_acc_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s1"] + fn hexagon_M2_mpyu_acc_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.hh.s0"] + fn hexagon_M2_mpyu_hh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.hh.s1"] + fn hexagon_M2_mpyu_hh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.hl.s0"] + fn hexagon_M2_mpyu_hl_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.hl.s1"] + fn hexagon_M2_mpyu_hl_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.lh.s0"] + fn hexagon_M2_mpyu_lh_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.lh.s1"] + fn hexagon_M2_mpyu_lh_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.ll.s0"] + fn hexagon_M2_mpyu_ll_s0(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.ll.s1"] + fn hexagon_M2_mpyu_ll_s1(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s0"] + fn hexagon_M2_mpyu_nac_hh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s1"] + fn hexagon_M2_mpyu_nac_hh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s0"] + fn hexagon_M2_mpyu_nac_hl_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s1"] + fn hexagon_M2_mpyu_nac_hl_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s0"] + fn hexagon_M2_mpyu_nac_lh_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s1"] + fn hexagon_M2_mpyu_nac_lh_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s0"] + fn hexagon_M2_mpyu_nac_ll_s0(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s1"] + fn hexagon_M2_mpyu_nac_ll_s1(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyu.up"] + fn hexagon_M2_mpyu_up(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s0"] + fn hexagon_M2_mpyud_acc_hh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s1"] + fn hexagon_M2_mpyud_acc_hh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s0"] + fn hexagon_M2_mpyud_acc_hl_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s1"] + fn hexagon_M2_mpyud_acc_hl_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s0"] + fn hexagon_M2_mpyud_acc_lh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s1"] + fn hexagon_M2_mpyud_acc_lh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s0"] + fn hexagon_M2_mpyud_acc_ll_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s1"] + fn hexagon_M2_mpyud_acc_ll_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.hh.s0"] + fn hexagon_M2_mpyud_hh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.hh.s1"] + fn hexagon_M2_mpyud_hh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.hl.s0"] + fn hexagon_M2_mpyud_hl_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.hl.s1"] + fn hexagon_M2_mpyud_hl_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.lh.s0"] + fn hexagon_M2_mpyud_lh_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.lh.s1"] + fn hexagon_M2_mpyud_lh_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.ll.s0"] + fn hexagon_M2_mpyud_ll_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.ll.s1"] + fn hexagon_M2_mpyud_ll_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s0"] + fn hexagon_M2_mpyud_nac_hh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s1"] + fn hexagon_M2_mpyud_nac_hh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s0"] + fn hexagon_M2_mpyud_nac_hl_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s1"] + fn hexagon_M2_mpyud_nac_hl_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s0"] + fn hexagon_M2_mpyud_nac_lh_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s1"] + fn hexagon_M2_mpyud_nac_lh_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s0"] + fn hexagon_M2_mpyud_nac_ll_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s1"] + fn hexagon_M2_mpyud_nac_ll_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.mpyui"] + fn hexagon_M2_mpyui(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.nacci"] + fn hexagon_M2_nacci(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.naccii"] + fn hexagon_M2_naccii(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.subacc"] + fn hexagon_M2_subacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.vabsdiffh"] + fn hexagon_M2_vabsdiffh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vabsdiffw"] + fn hexagon_M2_vabsdiffw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.i"] + fn hexagon_M2_vcmac_s0_sat_i(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.r"] + fn hexagon_M2_vcmac_s0_sat_r(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.i"] + fn hexagon_M2_vcmpy_s0_sat_i(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.r"] + fn hexagon_M2_vcmpy_s0_sat_r(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.i"] + fn hexagon_M2_vcmpy_s1_sat_i(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.r"] + fn hexagon_M2_vcmpy_s1_sat_r(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vdmacs.s0"] + fn hexagon_M2_vdmacs_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vdmacs.s1"] + fn hexagon_M2_vdmacs_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vdmpyrs.s0"] + fn hexagon_M2_vdmpyrs_s0(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M2.vdmpyrs.s1"] + fn hexagon_M2_vdmpyrs_s1(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M2.vdmpys.s0"] + fn hexagon_M2_vdmpys_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vdmpys.s1"] + fn hexagon_M2_vdmpys_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2"] + fn hexagon_M2_vmac2(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2es"] + fn hexagon_M2_vmac2es(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2es.s0"] + fn hexagon_M2_vmac2es_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2es.s1"] + fn hexagon_M2_vmac2es_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2s.s0"] + fn hexagon_M2_vmac2s_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2s.s1"] + fn hexagon_M2_vmac2s_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2su.s0"] + fn hexagon_M2_vmac2su_s0(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmac2su.s1"] + fn hexagon_M2_vmac2su_s1(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2es.s0"] + fn hexagon_M2_vmpy2es_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2es.s1"] + fn hexagon_M2_vmpy2es_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2s.s0"] + fn hexagon_M2_vmpy2s_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2s.s0pack"] + fn hexagon_M2_vmpy2s_s0pack(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.vmpy2s.s1"] + fn hexagon_M2_vmpy2s_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2s.s1pack"] + fn hexagon_M2_vmpy2s_s1pack(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.vmpy2su.s0"] + fn hexagon_M2_vmpy2su_s0(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vmpy2su.s1"] + fn hexagon_M2_vmpy2su_s1(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vraddh"] + fn hexagon_M2_vraddh(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M2.vradduh"] + fn hexagon_M2_vradduh(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M2.vrcmaci.s0"] + fn hexagon_M2_vrcmaci_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmaci.s0c"] + fn hexagon_M2_vrcmaci_s0c(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmacr.s0"] + fn hexagon_M2_vrcmacr_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmacr.s0c"] + fn hexagon_M2_vrcmacr_s0c(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpyi.s0"] + fn hexagon_M2_vrcmpyi_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpyi.s0c"] + fn hexagon_M2_vrcmpyi_s0c(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpyr.s0"] + fn hexagon_M2_vrcmpyr_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpyr.s0c"] + fn hexagon_M2_vrcmpyr_s0c(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpys.acc.s1"] + fn hexagon_M2_vrcmpys_acc_s1(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpys.s1"] + fn hexagon_M2_vrcmpys_s1(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.M2.vrcmpys.s1rp"] + fn hexagon_M2_vrcmpys_s1rp(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M2.vrmac.s0"] + fn hexagon_M2_vrmac_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.vrmpy.s0"] + fn hexagon_M2_vrmpy_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M2.xor.xacc"] + fn hexagon_M2_xor_xacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.and.and"] + fn hexagon_M4_and_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.and.andn"] + fn hexagon_M4_and_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.and.or"] + fn hexagon_M4_and_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.and.xor"] + fn hexagon_M4_and_xor(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.cmpyi.wh"] + fn hexagon_M4_cmpyi_wh(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.cmpyi.whc"] + fn hexagon_M4_cmpyi_whc(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.cmpyr.wh"] + fn hexagon_M4_cmpyr_wh(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.cmpyr.whc"] + fn hexagon_M4_cmpyr_whc(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mac.up.s1.sat"] + fn hexagon_M4_mac_up_s1_sat(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyri.addi"] + fn hexagon_M4_mpyri_addi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyri.addr"] + fn hexagon_M4_mpyri_addr(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyri.addr.u2"] + fn hexagon_M4_mpyri_addr_u2(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyrr.addi"] + fn hexagon_M4_mpyrr_addi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.mpyrr.addr"] + fn hexagon_M4_mpyrr_addr(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.nac.up.s1.sat"] + fn hexagon_M4_nac_up_s1_sat(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.or.and"] + fn hexagon_M4_or_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.or.andn"] + fn hexagon_M4_or_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.or.or"] + fn hexagon_M4_or_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.or.xor"] + fn hexagon_M4_or_xor(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.pmpyw"] + fn hexagon_M4_pmpyw(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M4.pmpyw.acc"] + fn hexagon_M4_pmpyw_acc(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M4.vpmpyh"] + fn hexagon_M4_vpmpyh(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M4.vpmpyh.acc"] + fn hexagon_M4_vpmpyh_acc(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s0"] + fn hexagon_M4_vrmpyeh_acc_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s1"] + fn hexagon_M4_vrmpyeh_acc_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyeh.s0"] + fn hexagon_M4_vrmpyeh_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyeh.s1"] + fn hexagon_M4_vrmpyeh_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s0"] + fn hexagon_M4_vrmpyoh_acc_s0(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s1"] + fn hexagon_M4_vrmpyoh_acc_s1(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyoh.s0"] + fn hexagon_M4_vrmpyoh_s0(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.vrmpyoh.s1"] + fn hexagon_M4_vrmpyoh_s1(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M4.xor.and"] + fn hexagon_M4_xor_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.xor.andn"] + fn hexagon_M4_xor_andn(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.xor.or"] + fn hexagon_M4_xor_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M4.xor.xacc"] + fn hexagon_M4_xor_xacc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vdmacbsu"] + fn hexagon_M5_vdmacbsu(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vdmpybsu"] + fn hexagon_M5_vdmpybsu(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vmacbsu"] + fn hexagon_M5_vmacbsu(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M5.vmacbuu"] + fn hexagon_M5_vmacbuu(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M5.vmpybsu"] + fn hexagon_M5_vmpybsu(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M5.vmpybuu"] + fn hexagon_M5_vmpybuu(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.M5.vrmacbsu"] + fn hexagon_M5_vrmacbsu(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vrmacbuu"] + fn hexagon_M5_vrmacbuu(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vrmpybsu"] + fn hexagon_M5_vrmpybsu(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M5.vrmpybuu"] + fn hexagon_M5_vrmpybuu(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.addasl.rrri"] + fn hexagon_S2_addasl_rrri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.p"] + fn hexagon_S2_asl_i_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.acc"] + fn hexagon_S2_asl_i_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.and"] + fn hexagon_S2_asl_i_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.nac"] + fn hexagon_S2_asl_i_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.or"] + fn hexagon_S2_asl_i_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.p.xacc"] + fn hexagon_S2_asl_i_p_xacc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.r"] + fn hexagon_S2_asl_i_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.acc"] + fn hexagon_S2_asl_i_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.and"] + fn hexagon_S2_asl_i_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.nac"] + fn hexagon_S2_asl_i_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.or"] + fn hexagon_S2_asl_i_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.sat"] + fn hexagon_S2_asl_i_r_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.r.xacc"] + fn hexagon_S2_asl_i_r_xacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.i.vh"] + fn hexagon_S2_asl_i_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.i.vw"] + fn hexagon_S2_asl_i_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p"] + fn hexagon_S2_asl_r_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.acc"] + fn hexagon_S2_asl_r_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.and"] + fn hexagon_S2_asl_r_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.nac"] + fn hexagon_S2_asl_r_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.or"] + fn hexagon_S2_asl_r_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.p.xor"] + fn hexagon_S2_asl_r_p_xor(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.r"] + fn hexagon_S2_asl_r_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.acc"] + fn hexagon_S2_asl_r_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.and"] + fn hexagon_S2_asl_r_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.nac"] + fn hexagon_S2_asl_r_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.or"] + fn hexagon_S2_asl_r_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.r.sat"] + fn hexagon_S2_asl_r_r_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asl.r.vh"] + fn hexagon_S2_asl_r_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asl.r.vw"] + fn hexagon_S2_asl_r_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p"] + fn hexagon_S2_asr_i_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.acc"] + fn hexagon_S2_asr_i_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.and"] + fn hexagon_S2_asr_i_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.nac"] + fn hexagon_S2_asr_i_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.or"] + fn hexagon_S2_asr_i_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.rnd"] + fn hexagon_S2_asr_i_p_rnd(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax"] + fn hexagon_S2_asr_i_p_rnd_goodsyntax(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.r"] + fn hexagon_S2_asr_i_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.acc"] + fn hexagon_S2_asr_i_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.and"] + fn hexagon_S2_asr_i_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.nac"] + fn hexagon_S2_asr_i_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.or"] + fn hexagon_S2_asr_i_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.rnd"] + fn hexagon_S2_asr_i_r_rnd(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax"] + fn hexagon_S2_asr_i_r_rnd_goodsyntax(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.svw.trun"] + fn hexagon_S2_asr_i_svw_trun(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.i.vh"] + fn hexagon_S2_asr_i_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.i.vw"] + fn hexagon_S2_asr_i_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p"] + fn hexagon_S2_asr_r_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.acc"] + fn hexagon_S2_asr_r_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.and"] + fn hexagon_S2_asr_r_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.nac"] + fn hexagon_S2_asr_r_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.or"] + fn hexagon_S2_asr_r_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.p.xor"] + fn hexagon_S2_asr_r_p_xor(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.r"] + fn hexagon_S2_asr_r_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.acc"] + fn hexagon_S2_asr_r_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.and"] + fn hexagon_S2_asr_r_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.nac"] + fn hexagon_S2_asr_r_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.or"] + fn hexagon_S2_asr_r_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.r.sat"] + fn hexagon_S2_asr_r_r_sat(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.svw.trun"] + fn hexagon_S2_asr_r_svw_trun(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.asr.r.vh"] + fn hexagon_S2_asr_r_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.asr.r.vw"] + fn hexagon_S2_asr_r_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.brev"] + fn hexagon_S2_brev(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.brevp"] + fn hexagon_S2_brevp(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.cl0"] + fn hexagon_S2_cl0(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.cl0p"] + fn hexagon_S2_cl0p(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.cl1"] + fn hexagon_S2_cl1(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.cl1p"] + fn hexagon_S2_cl1p(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.clb"] + fn hexagon_S2_clb(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.clbnorm"] + fn hexagon_S2_clbnorm(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.clbp"] + fn hexagon_S2_clbp(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.clrbit.i"] + fn hexagon_S2_clrbit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.clrbit.r"] + fn hexagon_S2_clrbit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.ct0"] + fn hexagon_S2_ct0(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.ct0p"] + fn hexagon_S2_ct0p(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.ct1"] + fn hexagon_S2_ct1(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.ct1p"] + fn hexagon_S2_ct1p(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.deinterleave"] + fn hexagon_S2_deinterleave(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.extractu"] + fn hexagon_S2_extractu(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.extractu.rp"] + fn hexagon_S2_extractu_rp(_: i32, _: i64) -> i32; + #[link_name = "llvm.hexagon.S2.extractup"] + fn hexagon_S2_extractup(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.extractup.rp"] + fn hexagon_S2_extractup_rp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.insert"] + fn hexagon_S2_insert(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.insert.rp"] + fn hexagon_S2_insert_rp(_: i32, _: i32, _: i64) -> i32; + #[link_name = "llvm.hexagon.S2.insertp"] + fn hexagon_S2_insertp(_: i64, _: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.insertp.rp"] + fn hexagon_S2_insertp_rp(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.interleave"] + fn hexagon_S2_interleave(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.lfsp"] + fn hexagon_S2_lfsp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p"] + fn hexagon_S2_lsl_r_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.acc"] + fn hexagon_S2_lsl_r_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.and"] + fn hexagon_S2_lsl_r_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.nac"] + fn hexagon_S2_lsl_r_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.or"] + fn hexagon_S2_lsl_r_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.p.xor"] + fn hexagon_S2_lsl_r_p_xor(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.r"] + fn hexagon_S2_lsl_r_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.r.acc"] + fn hexagon_S2_lsl_r_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.r.and"] + fn hexagon_S2_lsl_r_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.r.nac"] + fn hexagon_S2_lsl_r_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.r.or"] + fn hexagon_S2_lsl_r_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsl.r.vh"] + fn hexagon_S2_lsl_r_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsl.r.vw"] + fn hexagon_S2_lsl_r_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p"] + fn hexagon_S2_lsr_i_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.acc"] + fn hexagon_S2_lsr_i_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.and"] + fn hexagon_S2_lsr_i_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.nac"] + fn hexagon_S2_lsr_i_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.or"] + fn hexagon_S2_lsr_i_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.p.xacc"] + fn hexagon_S2_lsr_i_p_xacc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.r"] + fn hexagon_S2_lsr_i_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.acc"] + fn hexagon_S2_lsr_i_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.and"] + fn hexagon_S2_lsr_i_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.nac"] + fn hexagon_S2_lsr_i_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.or"] + fn hexagon_S2_lsr_i_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.r.xacc"] + fn hexagon_S2_lsr_i_r_xacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.i.vh"] + fn hexagon_S2_lsr_i_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.i.vw"] + fn hexagon_S2_lsr_i_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p"] + fn hexagon_S2_lsr_r_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.acc"] + fn hexagon_S2_lsr_r_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.and"] + fn hexagon_S2_lsr_r_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.nac"] + fn hexagon_S2_lsr_r_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.or"] + fn hexagon_S2_lsr_r_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.p.xor"] + fn hexagon_S2_lsr_r_p_xor(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.r"] + fn hexagon_S2_lsr_r_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.r.acc"] + fn hexagon_S2_lsr_r_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.r.and"] + fn hexagon_S2_lsr_r_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.r.nac"] + fn hexagon_S2_lsr_r_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.r.or"] + fn hexagon_S2_lsr_r_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.lsr.r.vh"] + fn hexagon_S2_lsr_r_vh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.lsr.r.vw"] + fn hexagon_S2_lsr_r_vw(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.packhl"] + fn hexagon_S2_packhl(_: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.parityp"] + fn hexagon_S2_parityp(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.S2.setbit.i"] + fn hexagon_S2_setbit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.setbit.r"] + fn hexagon_S2_setbit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.shuffeb"] + fn hexagon_S2_shuffeb(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.shuffeh"] + fn hexagon_S2_shuffeh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.shuffob"] + fn hexagon_S2_shuffob(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.shuffoh"] + fn hexagon_S2_shuffoh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.svsathb"] + fn hexagon_S2_svsathb(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.svsathub"] + fn hexagon_S2_svsathub(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tableidxb.goodsyntax"] + fn hexagon_S2_tableidxb_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tableidxd.goodsyntax"] + fn hexagon_S2_tableidxd_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tableidxh.goodsyntax"] + fn hexagon_S2_tableidxh_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tableidxw.goodsyntax"] + fn hexagon_S2_tableidxw_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.togglebit.i"] + fn hexagon_S2_togglebit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.togglebit.r"] + fn hexagon_S2_togglebit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tstbit.i"] + fn hexagon_S2_tstbit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.tstbit.r"] + fn hexagon_S2_tstbit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.valignib"] + fn hexagon_S2_valignib(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.valignrb"] + fn hexagon_S2_valignrb(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vcnegh"] + fn hexagon_S2_vcnegh(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vcrotate"] + fn hexagon_S2_vcrotate(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vrcnegh"] + fn hexagon_S2_vrcnegh(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vrndpackwh"] + fn hexagon_S2_vrndpackwh(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vrndpackwhs"] + fn hexagon_S2_vrndpackwhs(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsathb"] + fn hexagon_S2_vsathb(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsathb.nopack"] + fn hexagon_S2_vsathb_nopack(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vsathub"] + fn hexagon_S2_vsathub(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsathub.nopack"] + fn hexagon_S2_vsathub_nopack(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vsatwh"] + fn hexagon_S2_vsatwh(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsatwh.nopack"] + fn hexagon_S2_vsatwh_nopack(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vsatwuh"] + fn hexagon_S2_vsatwuh(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vsatwuh.nopack"] + fn hexagon_S2_vsatwuh_nopack(_: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vsplatrb"] + fn hexagon_S2_vsplatrb(_: i32) -> i32; + #[link_name = "llvm.hexagon.S2.vsplatrh"] + fn hexagon_S2_vsplatrh(_: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vspliceib"] + fn hexagon_S2_vspliceib(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vsplicerb"] + fn hexagon_S2_vsplicerb(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vsxtbh"] + fn hexagon_S2_vsxtbh(_: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vsxthw"] + fn hexagon_S2_vsxthw(_: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vtrunehb"] + fn hexagon_S2_vtrunehb(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vtrunewh"] + fn hexagon_S2_vtrunewh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vtrunohb"] + fn hexagon_S2_vtrunohb(_: i64) -> i32; + #[link_name = "llvm.hexagon.S2.vtrunowh"] + fn hexagon_S2_vtrunowh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S2.vzxtbh"] + fn hexagon_S2_vzxtbh(_: i32) -> i64; + #[link_name = "llvm.hexagon.S2.vzxthw"] + fn hexagon_S2_vzxthw(_: i32) -> i64; + #[link_name = "llvm.hexagon.S4.addaddi"] + fn hexagon_S4_addaddi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.addi.asl.ri"] + fn hexagon_S4_addi_asl_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.addi.lsr.ri"] + fn hexagon_S4_addi_lsr_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.andi.asl.ri"] + fn hexagon_S4_andi_asl_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.andi.lsr.ri"] + fn hexagon_S4_andi_lsr_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.clbaddi"] + fn hexagon_S4_clbaddi(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.clbpaddi"] + fn hexagon_S4_clbpaddi(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.clbpnorm"] + fn hexagon_S4_clbpnorm(_: i64) -> i32; + #[link_name = "llvm.hexagon.S4.extract"] + fn hexagon_S4_extract(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.extract.rp"] + fn hexagon_S4_extract_rp(_: i32, _: i64) -> i32; + #[link_name = "llvm.hexagon.S4.extractp"] + fn hexagon_S4_extractp(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S4.extractp.rp"] + fn hexagon_S4_extractp_rp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.lsli"] + fn hexagon_S4_lsli(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.ntstbit.i"] + fn hexagon_S4_ntstbit_i(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.ntstbit.r"] + fn hexagon_S4_ntstbit_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.or.andi"] + fn hexagon_S4_or_andi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.or.andix"] + fn hexagon_S4_or_andix(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.or.ori"] + fn hexagon_S4_or_ori(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.ori.asl.ri"] + fn hexagon_S4_ori_asl_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.ori.lsr.ri"] + fn hexagon_S4_ori_lsr_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.parity"] + fn hexagon_S4_parity(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.subaddi"] + fn hexagon_S4_subaddi(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.subi.asl.ri"] + fn hexagon_S4_subi_asl_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.subi.lsr.ri"] + fn hexagon_S4_subi_lsr_ri(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S4.vrcrotate"] + fn hexagon_S4_vrcrotate(_: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S4.vrcrotate.acc"] + fn hexagon_S4_vrcrotate_acc(_: i64, _: i64, _: i32, _: i32) -> i64; + #[link_name = "llvm.hexagon.S4.vxaddsubh"] + fn hexagon_S4_vxaddsubh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxaddsubhr"] + fn hexagon_S4_vxaddsubhr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxaddsubw"] + fn hexagon_S4_vxaddsubw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxsubaddh"] + fn hexagon_S4_vxsubaddh(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxsubaddhr"] + fn hexagon_S4_vxsubaddhr(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S4.vxsubaddw"] + fn hexagon_S4_vxsubaddw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax"] + fn hexagon_S5_asrhub_rnd_sat_goodsyntax(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S5.asrhub.sat"] + fn hexagon_S5_asrhub_sat(_: i64, _: i32) -> i32; + #[link_name = "llvm.hexagon.S5.popcountp"] + fn hexagon_S5_popcountp(_: i64) -> i32; + #[link_name = "llvm.hexagon.S5.vasrhrnd.goodsyntax"] + fn hexagon_S5_vasrhrnd_goodsyntax(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.Y2.dccleana"] + fn hexagon_Y2_dccleana(_: i32); + #[link_name = "llvm.hexagon.Y2.dccleaninva"] + fn hexagon_Y2_dccleaninva(_: i32); + #[link_name = "llvm.hexagon.Y2.dcfetch"] + fn hexagon_Y2_dcfetch(_: i32); + #[link_name = "llvm.hexagon.Y2.dcinva"] + fn hexagon_Y2_dcinva(_: i32); + #[link_name = "llvm.hexagon.Y2.dczeroa"] + fn hexagon_Y2_dczeroa(_: i32); + #[link_name = "llvm.hexagon.Y4.l2fetch"] + fn hexagon_Y4_l2fetch(_: i32, _: i32); + #[link_name = "llvm.hexagon.Y5.l2fetch"] + fn hexagon_Y5_l2fetch(_: i32, _: i64); + #[link_name = "llvm.hexagon.S6.rol.i.p"] + fn hexagon_S6_rol_i_p(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.acc"] + fn hexagon_S6_rol_i_p_acc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.and"] + fn hexagon_S6_rol_i_p_and(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.nac"] + fn hexagon_S6_rol_i_p_nac(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.or"] + fn hexagon_S6_rol_i_p_or(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.p.xacc"] + fn hexagon_S6_rol_i_p_xacc(_: i64, _: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.S6.rol.i.r"] + fn hexagon_S6_rol_i_r(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.acc"] + fn hexagon_S6_rol_i_r_acc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.and"] + fn hexagon_S6_rol_i_r_and(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.nac"] + fn hexagon_S6_rol_i_r_nac(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.or"] + fn hexagon_S6_rol_i_r_or(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S6.rol.i.r.xacc"] + fn hexagon_S6_rol_i_r_xacc(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.M6.vabsdiffb"] + fn hexagon_M6_vabsdiffb(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M6.vabsdiffub"] + fn hexagon_M6_vabsdiffub(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S6.vsplatrbp"] + fn hexagon_S6_vsplatrbp(_: i32) -> i64; + #[link_name = "llvm.hexagon.S6.vtrunehb.ppp"] + fn hexagon_S6_vtrunehb_ppp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.S6.vtrunohb.ppp"] + fn hexagon_S6_vtrunohb_ppp(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.A6.vcmpbeq.notany"] + fn hexagon_A6_vcmpbeq_notany(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.F2.dfadd"] + fn hexagon_F2_dfadd(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfsub"] + fn hexagon_F2_dfsub(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.M2.mnaci"] + fn hexagon_M2_mnaci(_: i32, _: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.S2.mask"] + fn hexagon_S2_mask(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A7.clip"] + fn hexagon_A7_clip(_: i32, _: i32) -> i32; + #[link_name = "llvm.hexagon.A7.croundd.ri"] + fn hexagon_A7_croundd_ri(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A7.croundd.rr"] + fn hexagon_A7_croundd_rr(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.A7.vclip"] + fn hexagon_A7_vclip(_: i64, _: i32) -> i64; + #[link_name = "llvm.hexagon.F2.dfmax"] + fn hexagon_F2_dfmax(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmin"] + fn hexagon_F2_dfmin(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmpyfix"] + fn hexagon_F2_dfmpyfix(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmpyhh"] + fn hexagon_F2_dfmpyhh(_: f64, _: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmpylh"] + fn hexagon_F2_dfmpylh(_: f64, _: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.F2.dfmpyll"] + fn hexagon_F2_dfmpyll(_: f64, _: f64) -> f64; + #[link_name = "llvm.hexagon.M7.dcmpyiw"] + fn hexagon_M7_dcmpyiw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyiw.acc"] + fn hexagon_M7_dcmpyiw_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyiwc"] + fn hexagon_M7_dcmpyiwc(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyiwc.acc"] + fn hexagon_M7_dcmpyiwc_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyrw"] + fn hexagon_M7_dcmpyrw(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyrw.acc"] + fn hexagon_M7_dcmpyrw_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyrwc"] + fn hexagon_M7_dcmpyrwc(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.dcmpyrwc.acc"] + fn hexagon_M7_dcmpyrwc_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.vdmpy"] + fn hexagon_M7_vdmpy(_: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.vdmpy.acc"] + fn hexagon_M7_vdmpy_acc(_: i64, _: i64, _: i64) -> i64; + #[link_name = "llvm.hexagon.M7.wcmpyiw"] + fn hexagon_M7_wcmpyiw(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyiw.rnd"] + fn hexagon_M7_wcmpyiw_rnd(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyiwc"] + fn hexagon_M7_wcmpyiwc(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyiwc.rnd"] + fn hexagon_M7_wcmpyiwc_rnd(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyrw"] + fn hexagon_M7_wcmpyrw(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyrw.rnd"] + fn hexagon_M7_wcmpyrw_rnd(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyrwc"] + fn hexagon_M7_wcmpyrwc(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.M7.wcmpyrwc.rnd"] + fn hexagon_M7_wcmpyrwc_rnd(_: i64, _: i64) -> i32; + #[link_name = "llvm.hexagon.Y6.dmlink"] + fn hexagon_Y6_dmlink(_: i32, _: i32); + #[link_name = "llvm.hexagon.Y6.dmpause"] + fn hexagon_Y6_dmpause() -> i32; + #[link_name = "llvm.hexagon.Y6.dmpoll"] + fn hexagon_Y6_dmpoll() -> i32; + #[link_name = "llvm.hexagon.Y6.dmresume"] + fn hexagon_Y6_dmresume(_: i32); + #[link_name = "llvm.hexagon.Y6.dmstart"] + fn hexagon_Y6_dmstart(_: i32); + #[link_name = "llvm.hexagon.Y6.dmwait"] + fn hexagon_Y6_dmwait() -> i32; +} + +/// `Rd32=abs(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(abs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_abs_R(rs: i32) -> i32 { + hexagon_A2_abs(rs) +} + +/// `Rdd32=abs(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(abs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_abs_P(rss: i64) -> i64 { + hexagon_A2_absp(rss) +} + +/// `Rd32=abs(Rs32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(abs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_abs_R_sat(rs: i32) -> i32 { + hexagon_A2_abssat(rs) +} + +/// `Rd32=add(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_add(rs, rt) +} + +/// `Rd32=add(Rt32.h,Rs32.h):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RhRh_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_hh(rt, rs) +} + +/// `Rd32=add(Rt32.h,Rs32.l):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RhRl_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_hl(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.h):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRh_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_lh(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.l):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRl_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_ll(rt, rs) +} + +/// `Rd32=add(Rt32.h,Rs32.h):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RhRh_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_sat_hh(rt, rs) +} + +/// `Rd32=add(Rt32.h,Rs32.l):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RhRl_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_sat_hl(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.h):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRh_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_sat_lh(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.l):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRl_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_h16_sat_ll(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.h)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRh(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_l16_hl(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.l)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRl(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_l16_ll(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.h):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRh_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_l16_sat_hl(rt, rs) +} + +/// `Rd32=add(Rt32.l,Rs32.l):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RlRl_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_addh_l16_sat_ll(rt, rs) +} + +/// `Rd32=add(Rs32,#s16)` +/// +/// Instruction Type: ALU32_ADDI +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IS16 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS16, 16); + hexagon_A2_addi(rs, IS16) +} + +/// `Rdd32=add(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_add_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_addp(rss, rtt) +} + +/// `Rdd32=add(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_add_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_addpsat(rss, rtt) +} + +/// `Rd32=add(Rs32,Rt32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_A2_addsat(rs, rt) +} + +/// `Rdd32=add(Rs32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_add_RP(rs: i32, rtt: i64) -> i64 { + hexagon_A2_addsp(rs, rtt) +} + +/// `Rd32=and(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_and(rs, rt) +} + +/// `Rd32=and(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(and, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_A2_andir(rs, IS10) +} + +/// `Rdd32=and(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_and_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_andp(rss, rtt) +} + +/// `Rd32=aslh(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(aslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslh_R(rs: i32) -> i32 { + hexagon_A2_aslh(rs) +} + +/// `Rd32=asrh(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(asrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrh_R(rs: i32) -> i32 { + hexagon_A2_asrh(rs) +} + +/// `Rd32=combine(Rt32.h,Rs32.h)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_combine_RhRh(rt: i32, rs: i32) -> i32 { + hexagon_A2_combine_hh(rt, rs) +} + +/// `Rd32=combine(Rt32.h,Rs32.l)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_combine_RhRl(rt: i32, rs: i32) -> i32 { + hexagon_A2_combine_hl(rt, rs) +} + +/// `Rd32=combine(Rt32.l,Rs32.h)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_combine_RlRh(rt: i32, rs: i32) -> i32 { + hexagon_A2_combine_lh(rt, rs) +} + +/// `Rd32=combine(Rt32.l,Rs32.l)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_combine_RlRl(rt: i32, rs: i32) -> i32 { + hexagon_A2_combine_ll(rt, rs) +} + +/// `Rdd32=combine(#s8,#S8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0, 1)] +#[cfg_attr(test, assert_instr(combine, IS8 = 0, IS8_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_combine_II() -> i64 { + static_assert_simm_bits!(IS8, 8); + static_assert_simm_bits!(IS8_2, 8); + hexagon_A2_combineii(IS8, IS8_2) +} + +/// `Rdd32=combine(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(combine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_combine_RR(rs: i32, rt: i32) -> i64 { + hexagon_A2_combinew(rs, rt) +} + +/// `Rd32=max(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(max))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_max_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_max(rs, rt) +} + +/// `Rdd32=max(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(max))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_max_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_maxp(rss, rtt) +} + +/// `Rd32=maxu(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(maxu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_maxu_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_maxu(rs, rt) +} + +/// `Rdd32=maxu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(maxu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_maxu_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_maxup(rss, rtt) +} + +/// `Rd32=min(Rt32,Rs32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(min))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_min_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_min(rt, rs) +} + +/// `Rdd32=min(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(min))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_min_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_minp(rtt, rss) +} + +/// `Rd32=minu(Rt32,Rs32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(minu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_minu_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_minu(rt, rs) +} + +/// `Rdd32=minu(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(minu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_minu_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_minup(rtt, rss) +} + +/// `Rd32=neg(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(neg))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_neg_R(rs: i32) -> i32 { + hexagon_A2_neg(rs) +} + +/// `Rdd32=neg(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(neg))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_neg_P(rss: i64) -> i64 { + hexagon_A2_negp(rss) +} + +/// `Rd32=neg(Rs32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(neg))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_neg_R_sat(rs: i32) -> i32 { + hexagon_A2_negsat(rs) +} + +/// `Rd32=not(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(not))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_not_R(rs: i32) -> i32 { + hexagon_A2_not(rs) +} + +/// `Rdd32=not(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(not))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_not_P(rss: i64) -> i64 { + hexagon_A2_notp(rss) +} + +/// `Rd32=or(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_or(rs, rt) +} + +/// `Rd32=or(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(or, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_A2_orir(rs, IS10) +} + +/// `Rdd32=or(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_or_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_orp(rss, rtt) +} + +/// `Rd32=round(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(round))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_P_sat(rss: i64) -> i32 { + hexagon_A2_roundsat(rss) +} + +/// `Rd32=sat(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sat_P(rss: i64) -> i32 { + hexagon_A2_sat(rss) +} + +/// `Rd32=satb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(satb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_satb_R(rs: i32) -> i32 { + hexagon_A2_satb(rs) +} + +/// `Rd32=sath(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sath_R(rs: i32) -> i32 { + hexagon_A2_sath(rs) +} + +/// `Rd32=satub(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(satub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_satub_R(rs: i32) -> i32 { + hexagon_A2_satub(rs) +} + +/// `Rd32=satuh(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(satuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_satuh_R(rs: i32) -> i32 { + hexagon_A2_satuh(rs) +} + +/// `Rd32=sub(Rt32,Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_sub(rt, rs) +} + +/// `Rd32=sub(Rt32.h,Rs32.h):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RhRh_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_hh(rt, rs) +} + +/// `Rd32=sub(Rt32.h,Rs32.l):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RhRl_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_hl(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.h):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRh_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_lh(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.l):<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRl_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_ll(rt, rs) +} + +/// `Rd32=sub(Rt32.h,Rs32.h):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RhRh_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_sat_hh(rt, rs) +} + +/// `Rd32=sub(Rt32.h,Rs32.l):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RhRl_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_sat_hl(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.h):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRh_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_sat_lh(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.l):sat:<<16` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRl_sat_s16(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_h16_sat_ll(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.h)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRh(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_l16_hl(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.l)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRl(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_l16_ll(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.h):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRh_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_l16_sat_hl(rt, rs) +} + +/// `Rd32=sub(Rt32.l,Rs32.l):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RlRl_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_subh_l16_sat_ll(rt, rs) +} + +/// `Rdd32=sub(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_sub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_subp(rtt, rss) +} + +/// `Rd32=sub(#s10,Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(sub, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_IR(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_A2_subri(IS10, rs) +} + +/// `Rd32=sub(Rt32,Rs32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_RR_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_subsat(rt, rs) +} + +/// `Rd32=vaddh(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vaddh_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_svaddh(rs, rt) +} + +/// `Rd32=vaddh(Rs32,Rt32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vaddh_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_A2_svaddhs(rs, rt) +} + +/// `Rd32=vadduh(Rs32,Rt32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vadduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vadduh_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_A2_svadduhs(rs, rt) +} + +/// `Rd32=vavgh(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vavgh_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_svavgh(rs, rt) +} + +/// `Rd32=vavgh(Rs32,Rt32):rnd` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vavgh_RR_rnd(rs: i32, rt: i32) -> i32 { + hexagon_A2_svavghs(rs, rt) +} + +/// `Rd32=vnavgh(Rt32,Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vnavgh_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_svnavgh(rt, rs) +} + +/// `Rd32=vsubh(Rt32,Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsubh_RR(rt: i32, rs: i32) -> i32 { + hexagon_A2_svsubh(rt, rs) +} + +/// `Rd32=vsubh(Rt32,Rs32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsubh_RR_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_svsubhs(rt, rs) +} + +/// `Rd32=vsubuh(Rt32,Rs32):sat` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsubuh_RR_sat(rt: i32, rs: i32) -> i32 { + hexagon_A2_svsubuhs(rt, rs) +} + +/// `Rd32=swiz(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(swiz))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_swiz_R(rs: i32) -> i32 { + hexagon_A2_swiz(rs) +} + +/// `Rd32=sxtb(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(sxtb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sxtb_R(rs: i32) -> i32 { + hexagon_A2_sxtb(rs) +} + +/// `Rd32=sxth(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(sxth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sxth_R(rs: i32) -> i32 { + hexagon_A2_sxth(rs) +} + +/// `Rdd32=sxtw(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sxtw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_sxtw_R(rs: i32) -> i64 { + hexagon_A2_sxtw(rs) +} + +/// `Rd32=Rs32` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_equals_R(rs: i32) -> i32 { + hexagon_A2_tfr(rs) +} + +/// `Rx32.h=#u16` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Rh_equals_I(rx: i32) -> i32 { + static_assert_uimm_bits!(IU16, 16); + hexagon_A2_tfrih(rx, IU16 as i32) +} + +/// `Rx32.l=#u16` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_Rl_equals_I(rx: i32) -> i32 { + static_assert_uimm_bits!(IU16, 16); + hexagon_A2_tfril(rx, IU16 as i32) +} + +/// `Rdd32=Rss32` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_equals_P(rss: i64) -> i64 { + hexagon_A2_tfrp(rss) +} + +/// `Rdd32=#s8` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_equals_I() -> i64 { + static_assert_simm_bits!(IS8, 8); + hexagon_A2_tfrpi(IS8) +} + +/// `Rd32=#s16` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_equals_I() -> i32 { + static_assert_simm_bits!(IS16, 16); + hexagon_A2_tfrsi(IS16) +} + +/// `Rdd32=vabsh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsh_P(rss: i64) -> i64 { + hexagon_A2_vabsh(rss) +} + +/// `Rdd32=vabsh(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsh_P_sat(rss: i64) -> i64 { + hexagon_A2_vabshsat(rss) +} + +/// `Rdd32=vabsw(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsw_P(rss: i64) -> i64 { + hexagon_A2_vabsw(rss) +} + +/// `Rdd32=vabsw(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsw_P_sat(rss: i64) -> i64 { + hexagon_A2_vabswsat(rss) +} + +/// `Rdd32=vaddb(Rss32,Rtt32)` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddb_map(rss, rtt) +} + +/// `Rdd32=vaddh(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddh(rss, rtt) +} + +/// `Rdd32=vaddh(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddhs(rss, rtt) +} + +/// `Rdd32=vaddub(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddub_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddub(rss, rtt) +} + +/// `Rdd32=vaddub(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddub_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddubs(rss, rtt) +} + +/// `Rdd32=vadduh(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vadduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vadduh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vadduhs(rss, rtt) +} + +/// `Rdd32=vaddw(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddw(rss, rtt) +} + +/// `Rdd32=vaddw(Rss32,Rtt32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaddw_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vaddws(rss, rtt) +} + +/// `Rdd32=vavgh(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgh(rss, rtt) +} + +/// `Rdd32=vavgh(Rss32,Rtt32):crnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgh_PP_crnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavghcr(rss, rtt) +} + +/// `Rdd32=vavgh(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgh_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavghr(rss, rtt) +} + +/// `Rdd32=vavgub(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgub_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgub(rss, rtt) +} + +/// `Rdd32=vavgub(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgub_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgubr(rss, rtt) +} + +/// `Rdd32=vavguh(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavguh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavguh(rss, rtt) +} + +/// `Rdd32=vavguh(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavguh_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavguhr(rss, rtt) +} + +/// `Rdd32=vavguw(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavguw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavguw(rss, rtt) +} + +/// `Rdd32=vavguw(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavguw_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavguwr(rss, rtt) +} + +/// `Rdd32=vavgw(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgw(rss, rtt) +} + +/// `Rdd32=vavgw(Rss32,Rtt32):crnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgw_PP_crnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgwcr(rss, rtt) +} + +/// `Rdd32=vavgw(Rss32,Rtt32):rnd` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vavgw_PP_rnd(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vavgwr(rss, rtt) +} + +/// `Pd4=vcmpb.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpbeq(rss, rtt) +} + +/// `Pd4=vcmpb.gtu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_gtu_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpbgtu(rss, rtt) +} + +/// `Pd4=vcmph.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpheq(rss, rtt) +} + +/// `Pd4=vcmph.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_gt_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmphgt(rss, rtt) +} + +/// `Pd4=vcmph.gtu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_gtu_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmphgtu(rss, rtt) +} + +/// `Pd4=vcmpw.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpweq(rss, rtt) +} + +/// `Pd4=vcmpw.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_gt_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpwgt(rss, rtt) +} + +/// `Pd4=vcmpw.gtu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_gtu_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A2_vcmpwgtu(rss, rtt) +} + +/// `Rdd32=vconj(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vconj))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vconj_P_sat(rss: i64) -> i64 { + hexagon_A2_vconj(rss) +} + +/// `Rdd32=vmaxb(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxb_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxb(rtt, rss) +} + +/// `Rdd32=vmaxh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxh(rtt, rss) +} + +/// `Rdd32=vmaxub(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxub(rtt, rss) +} + +/// `Rdd32=vmaxuh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxuh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxuh(rtt, rss) +} + +/// `Rdd32=vmaxuw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxuw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxuw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxuw(rtt, rss) +} + +/// `Rdd32=vmaxw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmaxw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vmaxw(rtt, rss) +} + +/// `Rdd32=vminb(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminb_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminb(rtt, rss) +} + +/// `Rdd32=vminh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminh(rtt, rss) +} + +/// `Rdd32=vminub(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminub(rtt, rss) +} + +/// `Rdd32=vminuh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminuh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminuh(rtt, rss) +} + +/// `Rdd32=vminuw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminuw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminuw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminuw(rtt, rss) +} + +/// `Rdd32=vminw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vminw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vminw(rtt, rss) +} + +/// `Rdd32=vnavgh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavgh(rtt, rss) +} + +/// `Rdd32=vnavgh(Rtt32,Rss32):crnd:sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgh_PP_crnd_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavghcr(rtt, rss) +} + +/// `Rdd32=vnavgh(Rtt32,Rss32):rnd:sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgh_PP_rnd_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavghr(rtt, rss) +} + +/// `Rdd32=vnavgw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavgw(rtt, rss) +} + +/// `Rdd32=vnavgw(Rtt32,Rss32):crnd:sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgw_PP_crnd_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavgwcr(rtt, rss) +} + +/// `Rdd32=vnavgw(Rtt32,Rss32):rnd:sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vnavgw_PP_rnd_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vnavgwr(rtt, rss) +} + +/// `Rdd32=vraddub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vraddub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vraddub_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vraddub(rss, rtt) +} + +/// `Rxx32+=vraddub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vraddub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vraddubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_A2_vraddub_acc(rxx, rss, rtt) +} + +/// `Rdd32=vrsadub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrsadub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrsadub_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vrsadub(rss, rtt) +} + +/// `Rxx32+=vrsadub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrsadub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrsadubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_A2_vrsadub_acc(rxx, rss, rtt) +} + +/// `Rdd32=vsubb(Rss32,Rtt32)` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_vsubb_map(rss, rtt) +} + +/// `Rdd32=vsubh(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubh(rtt, rss) +} + +/// `Rdd32=vsubh(Rtt32,Rss32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubh_PP_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubhs(rtt, rss) +} + +/// `Rdd32=vsubub(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubub(rtt, rss) +} + +/// `Rdd32=vsubub(Rtt32,Rss32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubub_PP_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsububs(rtt, rss) +} + +/// `Rdd32=vsubuh(Rtt32,Rss32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubuh_PP_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubuhs(rtt, rss) +} + +/// `Rdd32=vsubw(Rtt32,Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubw(rtt, rss) +} + +/// `Rdd32=vsubw(Rtt32,Rss32):sat` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsubw_PP_sat(rtt: i64, rss: i64) -> i64 { + hexagon_A2_vsubws(rtt, rss) +} + +/// `Rd32=xor(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_xor_RR(rs: i32, rt: i32) -> i32 { + hexagon_A2_xor(rs, rt) +} + +/// `Rdd32=xor(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_xor_PP(rss: i64, rtt: i64) -> i64 { + hexagon_A2_xorp(rss, rtt) +} + +/// `Rd32=zxtb(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(zxtb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_zxtb_R(rs: i32) -> i32 { + hexagon_A2_zxtb(rs) +} + +/// `Rd32=zxth(Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(zxth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_zxth_R(rs: i32) -> i32 { + hexagon_A2_zxth(rs) +} + +/// `Rd32=and(Rt32,~Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_RnR(rt: i32, rs: i32) -> i32 { + hexagon_A4_andn(rt, rs) +} + +/// `Rdd32=and(Rtt32,~Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_and_PnP(rtt: i64, rss: i64) -> i64 { + hexagon_A4_andnp(rtt, rss) +} + +/// `Rdd32=bitsplit(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(bitsplit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_bitsplit_RR(rs: i32, rt: i32) -> i64 { + hexagon_A4_bitsplit(rs, rt) +} + +/// `Rdd32=bitsplit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(bitsplit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_bitsplit_RI(rs: i32) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A4_bitspliti(rs, IU5 as i32) +} + +/// `Pd4=boundscheck(Rs32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(boundscheck))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_boundscheck_RP(rs: i32, rtt: i64) -> i32 { + hexagon_A4_boundscheck(rs, rtt) +} + +/// `Pd4=cmpb.eq(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmpbeq(rs, rt) +} + +/// `Pd4=cmpb.eq(Rs32,#u8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmpb, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_eq_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_A4_cmpbeqi(rs, IU8 as i32) +} + +/// `Pd4=cmpb.gt(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_gt_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmpbgt(rs, rt) +} + +/// `Pd4=cmpb.gt(Rs32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmpb, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_gt_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_cmpbgti(rs, IS8) +} + +/// `Pd4=cmpb.gtu(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_gtu_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmpbgtu(rs, rt) +} + +/// `Pd4=cmpb.gtu(Rs32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmpb, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmpb_gtu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_cmpbgtui(rs, IU7 as i32) +} + +/// `Pd4=cmph.eq(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmpheq(rs, rt) +} + +/// `Pd4=cmph.eq(Rs32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmph, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_cmpheqi(rs, IS8) +} + +/// `Pd4=cmph.gt(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_gt_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmphgt(rs, rt) +} + +/// `Pd4=cmph.gt(Rs32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmph, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_gt_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_cmphgti(rs, IS8) +} + +/// `Pd4=cmph.gtu(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmph))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_gtu_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cmphgtu(rs, rt) +} + +/// `Pd4=cmph.gtu(Rs32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmph, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmph_gtu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_cmphgtui(rs, IU7 as i32) +} + +/// `Rdd32=combine(#s8,Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(combine, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_combine_IR(rs: i32) -> i64 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_combineir(IS8, rs) +} + +/// `Rdd32=combine(Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(combine, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_combine_RI(rs: i32) -> i64 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_combineri(rs, IS8) +} + +/// `Rd32=cround(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cround, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cround_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A4_cround_ri(rs, IU5 as i32) +} + +/// `Rd32=cround(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cround))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cround_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_cround_rr(rs, rt) +} + +/// `Rd32=modwrap(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(modwrap))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_modwrap_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_modwrapu(rs, rt) +} + +/// `Rd32=or(Rt32,~Rs32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_RnR(rt: i32, rs: i32) -> i32 { + hexagon_A4_orn(rt, rs) +} + +/// `Rdd32=or(Rtt32,~Rss32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_or_PnP(rtt: i64, rss: i64) -> i64 { + hexagon_A4_ornp(rtt, rss) +} + +/// `Rd32=cmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmp_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_rcmpeq(rs, rt) +} + +/// `Rd32=cmp.eq(Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmp_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_rcmpeqi(rs, IS8) +} + +/// `Rd32=!cmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_rcmpneq(rs, rt) +} + +/// `Rd32=!cmp.eq(Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_not_cmp_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_rcmpneqi(rs, IS8) +} + +/// `Rd32=round(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(round, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A4_round_ri(rs, IU5 as i32) +} + +/// `Rd32=round(Rs32,#u5):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(round, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_RI_sat(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A4_round_ri_sat(rs, IU5 as i32) +} + +/// `Rd32=round(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(round))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_RR(rs: i32, rt: i32) -> i32 { + hexagon_A4_round_rr(rs, rt) +} + +/// `Rd32=round(Rs32,Rt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(round))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_round_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_A4_round_rr_sat(rs, rt) +} + +/// `Pd4=tlbmatch(Rss32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(tlbmatch))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_tlbmatch_PR(rss: i64, rt: i32) -> i32 { + hexagon_A4_tlbmatch(rss, rt) +} + +/// `Pd4=any8(vcmpb.eq(Rss32,Rtt32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(any8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A4_vcmpbeq_any(rss, rtt) +} + +/// `Pd4=vcmpb.eq(Rss32,#u8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpb, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_eq_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_A4_vcmpbeqi(rss, IU8 as i32) +} + +/// `Pd4=vcmpb.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_gt_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A4_vcmpbgt(rss, rtt) +} + +/// `Pd4=vcmpb.gt(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpb, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_gt_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmpbgti(rss, IS8) +} + +/// `Pd4=vcmpb.gtu(Rss32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpb, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpb_gtu_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_vcmpbgtui(rss, IU7 as i32) +} + +/// `Pd4=vcmph.eq(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_eq_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmpheqi(rss, IS8) +} + +/// `Pd4=vcmph.gt(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_gt_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmphgti(rss, IS8) +} + +/// `Pd4=vcmph.gtu(Rss32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmph, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmph_gtu_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_vcmphgtui(rss, IU7 as i32) +} + +/// `Pd4=vcmpw.eq(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_eq_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmpweqi(rss, IS8) +} + +/// `Pd4=vcmpw.gt(Rss32,#s8)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_gt_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_A4_vcmpwgti(rss, IS8) +} + +/// `Pd4=vcmpw.gtu(Rss32,#u7)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vcmpw, IU7 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_vcmpw_gtu_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU7, 7); + hexagon_A4_vcmpwgtui(rss, IU7 as i32) +} + +/// `Rxx32=vrmaxh(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmaxh_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrmaxh(rxx, rss, ru) +} + +/// `Rxx32=vrmaxuh(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmaxuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrmaxuh(rxx, rss, ru) +} + +/// `Rxx32=vrmaxuw(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmaxuw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmaxuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrmaxuw(rxx, rss, ru) +} + +/// `Rxx32=vrmaxw(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmaxw_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrmaxw(rxx, rss, ru) +} + +/// `Rxx32=vrminh(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrminh_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrminh(rxx, rss, ru) +} + +/// `Rxx32=vrminuh(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrminuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrminuh(rxx, rss, ru) +} + +/// `Rxx32=vrminuw(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrminuw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrminuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrminuw(rxx, rss, ru) +} + +/// `Rxx32=vrminw(Rss32,Ru32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrminw_PR(rxx: i64, rss: i64, ru: i32) -> i64 { + hexagon_A4_vrminw(rxx, rss, ru) +} + +/// `Rd32=vaddhub(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaddhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vaddhub_PP_sat(rss: i64, rtt: i64) -> i32 { + hexagon_A5_vaddhubs(rss, rtt) +} + +/// `Pd4=all8(Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(all8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_all8_p(ps: i32) -> i32 { + hexagon_C2_all8(ps) +} + +/// `Pd4=and(Pt4,Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_pp(pt: i32, ps: i32) -> i32 { + hexagon_C2_and(pt, ps) +} + +/// `Pd4=and(Pt4,!Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_pnp(pt: i32, ps: i32) -> i32 { + hexagon_C2_andn(pt, ps) +} + +/// `Pd4=any8(Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(any8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_any8_p(ps: i32) -> i32 { + hexagon_C2_any8(ps) +} + +/// `Pd4=bitsclr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(bitsclr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_bitsclr_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_bitsclr(rs, rt) +} + +/// `Pd4=bitsclr(Rs32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(bitsclr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_bitsclr_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + hexagon_C2_bitsclri(rs, IU6 as i32) +} + +/// `Pd4=bitsset(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(bitsset))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_bitsset_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_bitsset(rs, rt) +} + +/// `Pd4=cmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmpeq(rs, rt) +} + +/// `Pd4=cmp.eq(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_C2_cmpeqi(rs, IS10) +} + +/// `Pd4=cmp.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_C2_cmpeqp(rss, rtt) +} + +/// `Pd4=cmp.ge(Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_ge_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_C2_cmpgei(rs, IS8) +} + +/// `Pd4=cmp.geu(Rs32,#u8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_geu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_C2_cmpgeui(rs, IU8 as i32) +} + +/// `Pd4=cmp.gt(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gt_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmpgt(rs, rt) +} + +/// `Pd4=cmp.gt(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gt_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_C2_cmpgti(rs, IS10) +} + +/// `Pd4=cmp.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gt_PP(rss: i64, rtt: i64) -> i32 { + hexagon_C2_cmpgtp(rss, rtt) +} + +/// `Pd4=cmp.gtu(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gtu_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmpgtu(rs, rt) +} + +/// `Pd4=cmp.gtu(Rs32,#u9)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cmp, IU9 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gtu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU9, 9); + hexagon_C2_cmpgtui(rs, IU9 as i32) +} + +/// `Pd4=cmp.gtu(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_gtu_PP(rss: i64, rtt: i64) -> i32 { + hexagon_C2_cmpgtup(rss, rtt) +} + +/// `Pd4=cmp.lt(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_lt_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmplt(rs, rt) +} + +/// `Pd4=cmp.ltu(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_cmp_ltu_RR(rs: i32, rt: i32) -> i32 { + hexagon_C2_cmpltu(rs, rt) +} + +/// `Rdd32=mask(Pt4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mask))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mask_p(pt: i32) -> i64 { + hexagon_C2_mask(pt) +} + +/// `Rd32=mux(Pu4,Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(mux))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mux_pRR(pu: i32, rs: i32, rt: i32) -> i32 { + hexagon_C2_mux(pu, rs, rt) +} + +/// `Rd32=mux(Pu4,#s8,#S8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(mux, IS8 = 0, IS8_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mux_pII(pu: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + static_assert_simm_bits!(IS8_2, 8); + hexagon_C2_muxii(pu, IS8, IS8_2) +} + +/// `Rd32=mux(Pu4,Rs32,#s8)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(mux, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mux_pRI(pu: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_C2_muxir(pu, rs, IS8) +} + +/// `Rd32=mux(Pu4,#s8,Rs32)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mux, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mux_pIR(pu: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_C2_muxri(pu, IS8, rs) +} + +/// `Pd4=not(Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(not))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_p(ps: i32) -> i32 { + hexagon_C2_not(ps) +} + +/// `Pd4=or(Pt4,Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_pp(pt: i32, ps: i32) -> i32 { + hexagon_C2_or(pt, ps) +} + +/// `Pd4=or(Pt4,!Ps4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_pnp(pt: i32, ps: i32) -> i32 { + hexagon_C2_orn(pt, ps) +} + +/// `Pd4=Ps4` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_equals_p(ps: i32) -> i32 { + hexagon_C2_pxfer_map(ps) +} + +/// `Rd32=Ps4` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_equals_p(ps: i32) -> i32 { + hexagon_C2_tfrpr(ps) +} + +/// `Pd4=Rs32` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_equals_R(rs: i32) -> i32 { + hexagon_C2_tfrrp(rs) +} + +/// `Rd32=vitpack(Ps4,Pt4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vitpack))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vitpack_pp(ps: i32, pt: i32) -> i32 { + hexagon_C2_vitpack(ps, pt) +} + +/// `Rdd32=vmux(Pu4,Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmux))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmux_pPP(pu: i32, rss: i64, rtt: i64) -> i64 { + hexagon_C2_vmux(pu, rss, rtt) +} + +/// `Pd4=xor(Ps4,Pt4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_xor_pp(ps: i32, pt: i32) -> i32 { + hexagon_C2_xor(ps, pt) +} + +/// `Pd4=and(Ps4,and(Pt4,Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_and_and(ps, pt, pu) +} + +/// `Pd4=and(Ps4,and(Pt4,!Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_and_andn(ps, pt, pu) +} + +/// `Pd4=and(Ps4,or(Pt4,Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_and_or(ps, pt, pu) +} + +/// `Pd4=and(Ps4,or(Pt4,!Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_and_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_and_orn(ps, pt, pu) +} + +/// `Pd4=!cmp.gt(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_gt_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_cmplte(rs, rt) +} + +/// `Pd4=!cmp.gt(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_gt_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_C4_cmpltei(rs, IS10) +} + +/// `Pd4=!cmp.gtu(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_gtu_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_cmplteu(rs, rt) +} + +/// `Pd4=!cmp.gtu(Rs32,#u9)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_gtu_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU9, 9); + hexagon_C4_cmplteui(rs, IU9 as i32) +} + +/// `Pd4=!cmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_cmpneq(rs, rt) +} + +/// `Pd4=!cmp.eq(Rs32,#s10)` +/// +/// Instruction Type: ALU32_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_cmp_eq_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_C4_cmpneqi(rs, IS10) +} + +/// `Pd4=fastcorner9(Ps4,Pt4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(fastcorner9))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_fastcorner9_pp(ps: i32, pt: i32) -> i32 { + hexagon_C4_fastcorner9(ps, pt) +} + +/// `Pd4=!fastcorner9(Ps4,Pt4)` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_fastcorner9_pp(ps: i32, pt: i32) -> i32 { + hexagon_C4_fastcorner9_not(ps, pt) +} + +/// `Pd4=!bitsclr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_bitsclr_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_nbitsclr(rs, rt) +} + +/// `Pd4=!bitsclr(Rs32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_bitsclr_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + hexagon_C4_nbitsclri(rs, IU6 as i32) +} + +/// `Pd4=!bitsset(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_bitsset_RR(rs: i32, rt: i32) -> i32 { + hexagon_C4_nbitsset(rs, rt) +} + +/// `Pd4=or(Ps4,and(Pt4,Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_or_and(ps, pt, pu) +} + +/// `Pd4=or(Ps4,and(Pt4,!Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_or_andn(ps, pt, pu) +} + +/// `Pd4=or(Ps4,or(Pt4,Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_or_or(ps, pt, pu) +} + +/// `Pd4=or(Ps4,or(Pt4,!Pu4))` +/// +/// Instruction Type: CR +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_or_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 { + hexagon_C4_or_orn(ps, pt, pu) +} + +/// `Rdd32=convert_d2df(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_d2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_d2df_P(rss: i64) -> f64 { + hexagon_F2_conv_d2df(rss) +} + +/// `Rd32=convert_d2sf(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_d2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_d2sf_P(rss: i64) -> f32 { + hexagon_F2_conv_d2sf(rss) +} + +/// `Rdd32=convert_df2d(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2d))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_df2d_P(rss: f64) -> i64 { + hexagon_F2_conv_df2d(rss) +} + +/// `Rdd32=convert_df2d(Rss32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2d))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_df2d_P_chop(rss: f64) -> i64 { + hexagon_F2_conv_df2d_chop(rss) +} + +/// `Rd32=convert_df2sf(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2sf_P(rss: f64) -> f32 { + hexagon_F2_conv_df2sf(rss) +} + +/// `Rdd32=convert_df2ud(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2ud))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_df2ud_P(rss: f64) -> i64 { + hexagon_F2_conv_df2ud(rss) +} + +/// `Rdd32=convert_df2ud(Rss32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2ud))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_df2ud_P_chop(rss: f64) -> i64 { + hexagon_F2_conv_df2ud_chop(rss) +} + +/// `Rd32=convert_df2uw(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2uw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2uw_P(rss: f64) -> i32 { + hexagon_F2_conv_df2uw(rss) +} + +/// `Rd32=convert_df2uw(Rss32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2uw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2uw_P_chop(rss: f64) -> i32 { + hexagon_F2_conv_df2uw_chop(rss) +} + +/// `Rd32=convert_df2w(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2w_P(rss: f64) -> i32 { + hexagon_F2_conv_df2w(rss) +} + +/// `Rd32=convert_df2w(Rss32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_df2w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_df2w_P_chop(rss: f64) -> i32 { + hexagon_F2_conv_df2w_chop(rss) +} + +/// `Rdd32=convert_sf2d(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2d))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2d_R(rs: f32) -> i64 { + hexagon_F2_conv_sf2d(rs) +} + +/// `Rdd32=convert_sf2d(Rs32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2d))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2d_R_chop(rs: f32) -> i64 { + hexagon_F2_conv_sf2d_chop(rs) +} + +/// `Rdd32=convert_sf2df(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2df_R(rs: f32) -> f64 { + hexagon_F2_conv_sf2df(rs) +} + +/// `Rdd32=convert_sf2ud(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2ud))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2ud_R(rs: f32) -> i64 { + hexagon_F2_conv_sf2ud(rs) +} + +/// `Rdd32=convert_sf2ud(Rs32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2ud))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_sf2ud_R_chop(rs: f32) -> i64 { + hexagon_F2_conv_sf2ud_chop(rs) +} + +/// `Rd32=convert_sf2uw(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2uw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_sf2uw_R(rs: f32) -> i32 { + hexagon_F2_conv_sf2uw(rs) +} + +/// `Rd32=convert_sf2uw(Rs32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2uw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_sf2uw_R_chop(rs: f32) -> i32 { + hexagon_F2_conv_sf2uw_chop(rs) +} + +/// `Rd32=convert_sf2w(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_sf2w_R(rs: f32) -> i32 { + hexagon_F2_conv_sf2w(rs) +} + +/// `Rd32=convert_sf2w(Rs32):chop` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_sf2w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_sf2w_R_chop(rs: f32) -> i32 { + hexagon_F2_conv_sf2w_chop(rs) +} + +/// `Rdd32=convert_ud2df(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_ud2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_ud2df_P(rss: i64) -> f64 { + hexagon_F2_conv_ud2df(rss) +} + +/// `Rd32=convert_ud2sf(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_ud2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_ud2sf_P(rss: i64) -> f32 { + hexagon_F2_conv_ud2sf(rss) +} + +/// `Rdd32=convert_uw2df(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_uw2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_uw2df_R(rs: i32) -> f64 { + hexagon_F2_conv_uw2df(rs) +} + +/// `Rd32=convert_uw2sf(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_uw2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_uw2sf_R(rs: i32) -> f32 { + hexagon_F2_conv_uw2sf(rs) +} + +/// `Rdd32=convert_w2df(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_w2df))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_convert_w2df_R(rs: i32) -> f64 { + hexagon_F2_conv_w2df(rs) +} + +/// `Rd32=convert_w2sf(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(convert_w2sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_convert_w2sf_R(rs: i32) -> f32 { + hexagon_F2_conv_w2sf(rs) +} + +/// `Pd4=dfclass(Rss32,#u5)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(dfclass, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfclass_PI(rss: f64) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_F2_dfclass(rss, IU5 as i32) +} + +/// `Pd4=dfcmp.eq(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(dfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfcmp_eq_PP(rss: f64, rtt: f64) -> i32 { + hexagon_F2_dfcmpeq(rss, rtt) +} + +/// `Pd4=dfcmp.ge(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(dfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfcmp_ge_PP(rss: f64, rtt: f64) -> i32 { + hexagon_F2_dfcmpge(rss, rtt) +} + +/// `Pd4=dfcmp.gt(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(dfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfcmp_gt_PP(rss: f64, rtt: f64) -> i32 { + hexagon_F2_dfcmpgt(rss, rtt) +} + +/// `Pd4=dfcmp.uo(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(dfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_dfcmp_uo_PP(rss: f64, rtt: f64) -> i32 { + hexagon_F2_dfcmpuo(rss, rtt) +} + +/// `Rdd32=dfmake(#u10):neg` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmake_I_neg() -> f64 { + static_assert_uimm_bits!(IU10, 10); + hexagon_F2_dfimm_n(IU10 as i32) +} + +/// `Rdd32=dfmake(#u10):pos` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmake_I_pos() -> f64 { + static_assert_uimm_bits!(IU10, 10); + hexagon_F2_dfimm_p(IU10 as i32) +} + +/// `Rd32=sfadd(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfadd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfadd_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfadd(rs, rt) +} + +/// `Pd4=sfclass(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(sfclass, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfclass_RI(rs: f32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_F2_sfclass(rs, IU5 as i32) +} + +/// `Pd4=sfcmp.eq(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfcmp_eq_RR(rs: f32, rt: f32) -> i32 { + hexagon_F2_sfcmpeq(rs, rt) +} + +/// `Pd4=sfcmp.ge(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfcmp_ge_RR(rs: f32, rt: f32) -> i32 { + hexagon_F2_sfcmpge(rs, rt) +} + +/// `Pd4=sfcmp.gt(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfcmp_gt_RR(rs: f32, rt: f32) -> i32 { + hexagon_F2_sfcmpgt(rs, rt) +} + +/// `Pd4=sfcmp.uo(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfcmp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_sfcmp_uo_RR(rs: f32, rt: f32) -> i32 { + hexagon_F2_sfcmpuo(rs, rt) +} + +/// `Rd32=sffixupd(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sffixupd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sffixupd_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sffixupd(rs, rt) +} + +/// `Rd32=sffixupn(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sffixupn))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sffixupn_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sffixupn(rs, rt) +} + +/// `Rd32=sffixupr(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sffixupr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sffixupr_R(rs: f32) -> f32 { + hexagon_F2_sffixupr(rs) +} + +/// `Rx32+=sfmpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpyacc_RR(rx: f32, rs: f32, rt: f32) -> f32 { + hexagon_F2_sffma(rx, rs, rt) +} + +/// `Rx32+=sfmpy(Rs32,Rt32):lib` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpyacc_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 { + hexagon_F2_sffma_lib(rx, rs, rt) +} + +/// `Rx32+=sfmpy(Rs32,Rt32,Pu4):scale` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpyacc_RRp_scale(rx: f32, rs: f32, rt: f32, pu: i32) -> f32 { + hexagon_F2_sffma_sc(rx, rs, rt, pu) +} + +/// `Rx32-=sfmpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpynac_RR(rx: f32, rs: f32, rt: f32) -> f32 { + hexagon_F2_sffms(rx, rs, rt) +} + +/// `Rx32-=sfmpy(Rs32,Rt32):lib` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpynac_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 { + hexagon_F2_sffms_lib(rx, rs, rt) +} + +/// `Rd32=sfmake(#u10):neg` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmake_I_neg() -> f32 { + static_assert_uimm_bits!(IU10, 10); + hexagon_F2_sfimm_n(IU10 as i32) +} + +/// `Rd32=sfmake(#u10):pos` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmake_I_pos() -> f32 { + static_assert_uimm_bits!(IU10, 10); + hexagon_F2_sfimm_p(IU10 as i32) +} + +/// `Rd32=sfmax(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmax))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmax_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfmax(rs, rt) +} + +/// `Rd32=sfmin(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmin))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmin_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfmin(rs, rt) +} + +/// `Rd32=sfmpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfmpy_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfmpy(rs, rt) +} + +/// `Rd32=sfsub(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sfsub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sfsub_RR(rs: f32, rt: f32) -> f32 { + hexagon_F2_sfsub(rs, rt) +} + +/// `Rx32+=add(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_acci(rx, rs, rt) +} + +/// `Rx32+=add(Rs32,#s8)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(add, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_M2_accii(rx, rs, IS8) +} + +/// `Rxx32+=cmpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmaci_s0(rxx, rs, rt) +} + +/// `Rxx32+=cmpyr(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyracc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacr_s0(rxx, rs, rt) +} + +/// `Rxx32+=cmpy(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacs_s0(rxx, rs, rt) +} + +/// `Rxx32+=cmpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacs_s1(rxx, rs, rt) +} + +/// `Rxx32+=cmpy(Rs32,Rt32*):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyacc_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacsc_s0(rxx, rs, rt) +} + +/// `Rxx32+=cmpy(Rs32,Rt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyacc_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cmacsc_s1(rxx, rs, rt) +} + +/// `Rdd32=cmpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyi_RR(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpyi_s0(rs, rt) +} + +/// `Rdd32=cmpyr(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyr_RR(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpyr_s0(rs, rt) +} + +/// `Rd32=cmpy(Rs32,Rt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpy_RR_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_cmpyrs_s0(rs, rt) +} + +/// `Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpy_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_cmpyrs_s1(rs, rt) +} + +/// `Rd32=cmpy(Rs32,Rt32*):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpy_RR_conj_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_cmpyrsc_s0(rs, rt) +} + +/// `Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpy_RR_conj_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_cmpyrsc_s1(rs, rt) +} + +/// `Rdd32=cmpy(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpy_RR_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpys_s0(rs, rt) +} + +/// `Rdd32=cmpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpy_RR_s1_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpys_s1(rs, rt) +} + +/// `Rdd32=cmpy(Rs32,Rt32*):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpy_RR_conj_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpysc_s0(rs, rt) +} + +/// `Rdd32=cmpy(Rs32,Rt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpy_RR_conj_s1_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_cmpysc_s1(rs, rt) +} + +/// `Rxx32-=cmpy(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpynac_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cnacs_s0(rxx, rs, rt) +} + +/// `Rxx32-=cmpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpynac_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cnacs_s1(rxx, rs, rt) +} + +/// `Rxx32-=cmpy(Rs32,Rt32*):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpynac_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cnacsc_s0(rxx, rs, rt) +} + +/// `Rxx32-=cmpy(Rs32,Rt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpynac_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_cnacsc_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyss_acc_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyss_nac_s0(rxx, rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RR_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_dpmpyss_rnd_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RR(rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyss_s0(rs, rt) +} + +/// `Rxx32+=mpyu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyuu_acc_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyuu_nac_s0(rxx, rs, rt) +} + +/// `Rdd32=mpyu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RR(rs: i32, rt: i32) -> i64 { + hexagon_M2_dpmpyuu_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_hmmpyh_rs1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RRh_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_hmmpyh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_hmmpyl_rs1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RRl_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_hmmpyl_s1(rs, rt) +} + +/// `Rx32+=mpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyiacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_maci(rx, rs, rt) +} + +/// `Rx32-=mpyi(Rs32,#u8)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyinac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_M2_macsin(rx, rs, IU8 as i32) +} + +/// `Rx32+=mpyi(Rs32,#u8)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyiacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + hexagon_M2_macsip(rx, rs, IU8 as i32) +} + +/// `Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywohacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmachs_rs0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywohacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmachs_rs1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywoh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywohacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmachs_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywohacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmachs_s1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywehacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacls_rs0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywehacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacls_rs1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacls_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacls_s1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacuhs_rs0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacuhs_rs1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywouh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacuhs_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmacuhs_s1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmaculs_rs0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmaculs_rs1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweuh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmaculs_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmaculs_s1(rxx, rss, rtt) +} + +/// `Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywoh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyh_rs0(rss, rtt) +} + +/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywoh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyh_rs1(rss, rtt) +} + +/// `Rdd32=vmpywoh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywoh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyh_s0(rss, rtt) +} + +/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywoh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyh_s1(rss, rtt) +} + +/// `Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyl_rs0(rss, rtt) +} + +/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyl_rs1(rss, rtt) +} + +/// `Rdd32=vmpyweh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyl_s0(rss, rtt) +} + +/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyl_s1(rss, rtt) +} + +/// `Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyuh_rs0(rss, rtt) +} + +/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyuh_rs1(rss, rtt) +} + +/// `Rdd32=vmpywouh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyuh_s0(rss, rtt) +} + +/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpywouh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpywouh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyuh_s1(rss, rtt) +} + +/// `Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyul_rs0(rss, rtt) +} + +/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyul_rs1(rss, rtt) +} + +/// `Rdd32=vmpyweuh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyul_s0(rss, rtt) +} + +/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyweuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyweuh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_mmpyul_s1(rss, rtt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_hh_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_hh_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_hl_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_hl_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_lh_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_lh_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_ll_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_ll_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_hh_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_hh_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_hl_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_hl_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_lh_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_lh_s1(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_ll_s0(rx, rs, rt) +} + +/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_acc_sat_ll_s1(rx, rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_hh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_hh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_hl_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_hl_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_lh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_lh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_ll_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_ll_s1(rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_hh_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_hh_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_hl_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_hl_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_lh_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_lh_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_ll_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_ll_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_hh_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_hh_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_hl_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_hl_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_lh_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_lh_s1(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_ll_s0(rx, rs, rt) +} + +/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_nac_sat_ll_s1(rx, rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_hh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_hh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_hl_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_hl_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_lh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_lh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_ll_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_rnd_ll_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_hh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_hh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_hl_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_hl_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_lh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_lh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_ll_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_ll_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_hh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_hh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_hl_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RhRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_hl_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_lh_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_lh_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_ll_s0(rs, rt) +} + +/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RlRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_sat_rnd_ll_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_up(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RR_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_up_s1(rs, rt) +} + +/// `Rd32=mpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpy_RR_s1_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpy_up_s1_sat(rs, rt) +} + +/// `Rxx32+=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_hh_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_hh_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_hl_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_hl_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_lh_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_lh_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_ll_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_acc_ll_s1(rxx, rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRh(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_hh_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRh_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_hh_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRl(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_hl_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRl_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_hl_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRh(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_lh_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRh_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_lh_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRl(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_ll_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRl_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_ll_s1(rs, rt) +} + +/// `Rxx32-=mpy(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_hh_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_hh_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_hl_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_hl_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_lh_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_lh_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_ll_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpy(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpynac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_nac_ll_s1(rxx, rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.h):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRh_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_hh_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_hh_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.l):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRl_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_hl_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_hl_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.h):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRh_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_lh_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_lh_s1(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.l):rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRl_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_ll_s0(rs, rt) +} + +/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyd_rnd_ll_s1(rs, rt) +} + +/// `Rd32=mpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyi_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyi(rs, rt) +} + +/// `Rd32=mpyi(Rs32,#m9)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyi_RI(rs: i32, im9: i32) -> i32 { + hexagon_M2_mpysmi(rs, im9) +} + +/// `Rd32=mpysu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpysu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpysu_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpysu_up(rs, rt) +} + +/// `Rx32+=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_hh_s0(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_hh_s1(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_hl_s0(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_hl_s1(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_lh_s0(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_lh_s1(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_ll_s0(rx, rs, rt) +} + +/// `Rx32+=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyuacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_acc_ll_s1(rx, rs, rt) +} + +/// `Rd32=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RhRh(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_hh_s0(rs, rt) +} + +/// `Rd32=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RhRh_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_hh_s1(rs, rt) +} + +/// `Rd32=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RhRl(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_hl_s0(rs, rt) +} + +/// `Rd32=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RhRl_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_hl_s1(rs, rt) +} + +/// `Rd32=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RlRh(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_lh_s0(rs, rt) +} + +/// `Rd32=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RlRh_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_lh_s1(rs, rt) +} + +/// `Rd32=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RlRl(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_ll_s0(rs, rt) +} + +/// `Rd32=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RlRl_s1(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_ll_s1(rs, rt) +} + +/// `Rx32-=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_hh_s0(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_hh_s1(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_hl_s0(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_hl_s1(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_lh_s0(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_lh_s1(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_ll_s0(rx, rs, rt) +} + +/// `Rx32-=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyunac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_nac_ll_s1(rx, rs, rt) +} + +/// `Rd32=mpyu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyu_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyu_up(rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_hh_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_hh_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_hl_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_hl_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_lh_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_lh_s1(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_ll_s0(rxx, rs, rt) +} + +/// `Rxx32+=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyuacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_acc_ll_s1(rxx, rs, rt) +} + +/// `Rdd32=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RhRh(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_hh_s0(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RhRh_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_hh_s1(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RhRl(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_hl_s0(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RhRl_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_hl_s1(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RlRh(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_lh_s0(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RlRh_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_lh_s1(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RlRl(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_ll_s0(rs, rt) +} + +/// `Rdd32=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyu_RlRl_s1(rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_ll_s1(rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.h,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_hh_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.h,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_hh_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.h,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_hl_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.h,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_hl_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.l,Rt32.h)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_lh_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.l,Rt32.h):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_lh_s1(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.l,Rt32.l)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_ll_s0(rxx, rs, rt) +} + +/// `Rxx32-=mpyu(Rs32.l,Rt32.l):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_mpyunac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_mpyud_nac_ll_s1(rxx, rs, rt) +} + +/// `Rd32=mpyui(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpyui))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyui_RR(rs: i32, rt: i32) -> i32 { + hexagon_M2_mpyui(rs, rt) +} + +/// `Rx32-=add(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_nacci(rx, rs, rt) +} + +/// `Rx32-=add(Rs32,#s8)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(add, IS8 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS8, 8); + hexagon_M2_naccii(rx, rs, IS8) +} + +/// `Rx32+=sub(Rt32,Rs32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(sub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_subacc_RR(rx: i32, rt: i32, rs: i32) -> i32 { + hexagon_M2_subacc(rx, rt, rs) +} + +/// `Rdd32=vabsdiffh(Rtt32,Rss32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsdiffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsdiffh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_M2_vabsdiffh(rtt, rss) +} + +/// `Rdd32=vabsdiffw(Rtt32,Rss32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vabsdiffw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsdiffw_PP(rtt: i64, rss: i64) -> i64 { + hexagon_M2_vabsdiffw(rtt, rss) +} + +/// `Rxx32+=vcmpyi(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyiacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmac_s0_sat_i(rxx, rss, rtt) +} + +/// `Rxx32+=vcmpyr(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyracc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmac_s0_sat_r(rxx, rss, rtt) +} + +/// `Rdd32=vcmpyi(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyi_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmpy_s0_sat_i(rss, rtt) +} + +/// `Rdd32=vcmpyr(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyr_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmpy_s0_sat_r(rss, rtt) +} + +/// `Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyi_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmpy_s1_sat_i(rss, rtt) +} + +/// `Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcmpyr_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vcmpy_s1_sat_r(rss, rtt) +} + +/// `Rxx32+=vdmpy(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpyacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vdmacs_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpyacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vdmacs_s1(rxx, rss, rtt) +} + +/// `Rd32=vdmpy(Rss32,Rtt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vdmpy_PP_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M2_vdmpyrs_s0(rss, rtt) +} + +/// `Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vdmpy_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M2_vdmpyrs_s1(rss, rtt) +} + +/// `Rdd32=vdmpy(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpy_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vdmpys_s0(rss, rtt) +} + +/// `Rdd32=vdmpy(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpy_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vdmpys_s1(rss, rtt) +} + +/// `Rxx32+=vmpyh(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2(rxx, rs, rt) +} + +/// `Rxx32+=vmpyeh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmac2es(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyeh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmac2es_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmac2es_s1(rxx, rss, rtt) +} + +/// `Rxx32+=vmpyh(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2s_s0(rxx, rs, rt) +} + +/// `Rxx32+=vmpyh(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2s_s1(rxx, rs, rt) +} + +/// `Rxx32+=vmpyhsu(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyhsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhsuacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2su_s0(rxx, rs, rt) +} + +/// `Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyhsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhsuacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M2_vmac2su_s1(rxx, rs, rt) +} + +/// `Rdd32=vmpyeh(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyeh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmpy2es_s0(rss, rtt) +} + +/// `Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyeh_PP_s1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vmpy2es_s1(rss, rtt) +} + +/// `Rdd32=vmpyh(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyh_RR_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_vmpy2s_s0(rs, rt) +} + +/// `Rd32=vmpyh(Rs32,Rt32):rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vmpyh_RR_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_vmpy2s_s0pack(rs, rt) +} + +/// `Rdd32=vmpyh(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyh_RR_s1_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_vmpy2s_s1(rs, rt) +} + +/// `Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vmpyh_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 { + hexagon_M2_vmpy2s_s1pack(rs, rt) +} + +/// `Rdd32=vmpyhsu(Rs32,Rt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyhsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhsu_RR_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_vmpy2su_s0(rs, rt) +} + +/// `Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpyhsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpyhsu_RR_s1_sat(rs: i32, rt: i32) -> i64 { + hexagon_M2_vmpy2su_s1(rs, rt) +} + +/// `Rd32=vraddh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vraddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vraddh_PP(rss: i64, rtt: i64) -> i32 { + hexagon_M2_vraddh(rss, rtt) +} + +/// `Rd32=vradduh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vradduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vradduh_PP(rss: i64, rtt: i64) -> i32 { + hexagon_M2_vradduh(rss, rtt) +} + +/// `Rxx32+=vrcmpyi(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyiacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmaci_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vrcmpyi(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyiacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmaci_s0c(rxx, rss, rtt) +} + +/// `Rxx32+=vrcmpyr(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyracc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmacr_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vrcmpyr(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyracc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmacr_s0c(rxx, rss, rtt) +} + +/// `Rdd32=vrcmpyi(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyi_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmpyi_s0(rss, rtt) +} + +/// `Rdd32=vrcmpyi(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyi_PP_conj(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmpyi_s0c(rss, rtt) +} + +/// `Rdd32=vrcmpyr(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyr_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmpyr_s0(rss, rtt) +} + +/// `Rdd32=vrcmpyr(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpyr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpyr_PP_conj(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrcmpyr_s0c(rss, rtt) +} + +/// `Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpys))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpysacc_PR_s1_sat(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_M2_vrcmpys_acc_s1(rxx, rss, rt) +} + +/// `Rdd32=vrcmpys(Rss32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpys))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcmpys_PR_s1_sat(rss: i64, rt: i32) -> i64 { + hexagon_M2_vrcmpys_s1(rss, rt) +} + +/// `Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcmpys))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vrcmpys_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M2_vrcmpys_s1rp(rss, rt) +} + +/// `Rxx32+=vrmpyh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpyhacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrmac_s0(rxx, rss, rtt) +} + +/// `Rdd32=vrmpyh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpyh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M2_vrmpy_s0(rss, rtt) +} + +/// `Rx32^=xor(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_xorxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_xor_xacc(rx, rs, rt) +} + +/// `Rx32&=and(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_and_and(rx, rs, rt) +} + +/// `Rx32&=and(Rs32,~Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andand_RnR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_and_andn(rx, rs, rt) +} + +/// `Rx32&=or(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_orand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_and_or(rx, rs, rt) +} + +/// `Rx32&=xor(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_xorand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_and_xor(rx, rs, rt) +} + +/// `Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M4_cmpyi_wh(rss, rt) +} + +/// `Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M4_cmpyi_whc(rss, rt) +} + +/// `Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M4_cmpyr_wh(rss, rt) +} + +/// `Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cmpyrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 { + hexagon_M4_cmpyr_whc(rss, rt) +} + +/// `Rx32+=mpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyacc_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_mac_up_s1_sat(rx, rs, rt) +} + +/// `Rd32=add(#u6,mpyi(Rs32,#U6))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(add, IU6 = 0, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_IRI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + static_assert_uimm_bits!(IU6_2, 6); + hexagon_M4_mpyri_addi(IU6 as i32, rs, IU6_2 as i32) +} + +/// `Rd32=add(Ru32,mpyi(Rs32,#u6))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(add, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_RRI(ru: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + hexagon_M4_mpyri_addr(ru, rs, IU6 as i32) +} + +/// `Rd32=add(Ru32,mpyi(#u6:2,Rs32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_RIR(ru: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU6_2, 6); + hexagon_M4_mpyri_addr_u2(ru, IU6_2 as i32, rs) +} + +/// `Rd32=add(#u6,mpyi(Rs32,Rt32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(add, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_IRR(rs: i32, rt: i32) -> i32 { + static_assert_uimm_bits!(IU6, 6); + hexagon_M4_mpyrr_addi(IU6 as i32, rs, rt) +} + +/// `Ry32=add(Ru32,mpyi(Ry32,Rs32))` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_mpyi_RRR(ru: i32, ry: i32, rs: i32) -> i32 { + hexagon_M4_mpyrr_addr(ru, ry, rs) +} + +/// `Rx32-=mpy(Rs32,Rt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(mpy))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpynac_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_nac_up_s1_sat(rx, rs, rt) +} + +/// `Rx32|=and(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andor_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_or_and(rx, rs, rt) +} + +/// `Rx32|=and(Rs32,~Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andor_RnR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_or_andn(rx, rs, rt) +} + +/// `Rx32|=or(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_oror_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_or_or(rx, rs, rt) +} + +/// `Rx32|=xor(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_xoror_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_or_xor(rx, rs, rt) +} + +/// `Rdd32=pmpyw(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(pmpyw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_pmpyw_RR(rs: i32, rt: i32) -> i64 { + hexagon_M4_pmpyw(rs, rt) +} + +/// `Rxx32^=pmpyw(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(pmpyw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_pmpywxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M4_pmpyw_acc(rxx, rs, rt) +} + +/// `Rdd32=vpmpyh(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vpmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vpmpyh_RR(rs: i32, rt: i32) -> i64 { + hexagon_M4_vpmpyh(rs, rt) +} + +/// `Rxx32^=vpmpyh(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vpmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vpmpyhxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M4_vpmpyh_acc(rxx, rs, rt) +} + +/// `Rxx32+=vrmpyweh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyeh_acc_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vrmpyweh(Rss32,Rtt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywehacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyeh_acc_s1(rxx, rss, rtt) +} + +/// `Rdd32=vrmpyweh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpyweh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyeh_s0(rss, rtt) +} + +/// `Rdd32=vrmpyweh(Rss32,Rtt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpyweh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpyweh_PP_s1(rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyeh_s1(rss, rtt) +} + +/// `Rxx32+=vrmpywoh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywohacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyoh_acc_s0(rxx, rss, rtt) +} + +/// `Rxx32+=vrmpywoh(Rss32,Rtt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywohacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyoh_acc_s1(rxx, rss, rtt) +} + +/// `Rdd32=vrmpywoh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywoh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyoh_s0(rss, rtt) +} + +/// `Rdd32=vrmpywoh(Rss32,Rtt32):<<1` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpywoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpywoh_PP_s1(rss: i64, rtt: i64) -> i64 { + hexagon_M4_vrmpyoh_s1(rss, rtt) +} + +/// `Rx32^=and(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_xor_and(rx, rs, rt) +} + +/// `Rx32^=and(Rs32,~Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(and))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andxacc_RnR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_xor_andn(rx, rs, rt) +} + +/// `Rx32^=or(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(or))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_orxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M4_xor_or(rx, rs, rt) +} + +/// `Rxx32^=xor(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(xor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_xorxacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M4_xor_xacc(rxx, rss, rtt) +} + +/// `Rxx32+=vdmpybsu(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpybsuacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M5_vdmacbsu(rxx, rss, rtt) +} + +/// `Rdd32=vdmpybsu(Rss32,Rtt32):sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vdmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpybsu_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_M5_vdmpybsu(rss, rtt) +} + +/// `Rxx32+=vmpybsu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpybsuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M5_vmacbsu(rxx, rs, rt) +} + +/// `Rxx32+=vmpybu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpybu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpybuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 { + hexagon_M5_vmacbuu(rxx, rs, rt) +} + +/// `Rdd32=vmpybsu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpybsu_RR(rs: i32, rt: i32) -> i64 { + hexagon_M5_vmpybsu(rs, rt) +} + +/// `Rdd32=vmpybu(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vmpybu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vmpybu_RR(rs: i32, rt: i32) -> i64 { + hexagon_M5_vmpybuu(rs, rt) +} + +/// `Rxx32+=vrmpybsu(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpybsuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M5_vrmacbsu(rxx, rss, rtt) +} + +/// `Rxx32+=vrmpybu(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpybu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpybuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M5_vrmacbuu(rxx, rss, rtt) +} + +/// `Rdd32=vrmpybsu(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpybsu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpybsu_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M5_vrmpybsu(rss, rtt) +} + +/// `Rdd32=vrmpybu(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrmpybu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrmpybu_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M5_vrmpybuu(rss, rtt) +} + +/// `Rd32=addasl(Rt32,Rs32,#u3)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(addasl, IU3 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_addasl_RRI(rt: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU3, 3); + hexagon_S2_addasl_rrri(rt, rs, IU3 as i32) +} + +/// `Rdd32=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asl_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p(rss, IU6 as i32) +} + +/// `Rxx32+=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_acc(rxx, rss, IU6 as i32) +} + +/// `Rxx32&=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asland_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_and(rxx, rss, IU6 as i32) +} + +/// `Rxx32-=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslnac_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_nac(rxx, rss, IU6 as i32) +} + +/// `Rxx32|=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslor_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_or(rxx, rss, IU6 as i32) +} + +/// `Rxx32^=asl(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslxacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asl_i_p_xacc(rxx, rss, IU6 as i32) +} + +/// `Rd32=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asl_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r(rs, IU5 as i32) +} + +/// `Rx32+=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_acc(rx, rs, IU5 as i32) +} + +/// `Rx32&=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asland_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_and(rx, rs, IU5 as i32) +} + +/// `Rx32-=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_nac(rx, rs, IU5 as i32) +} + +/// `Rx32|=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslor_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_or(rx, rs, IU5 as i32) +} + +/// `Rd32=asl(Rs32,#u5):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asl_RI_sat(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_sat(rs, IU5 as i32) +} + +/// `Rx32^=asl(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asl, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslxacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_r_xacc(rx, rs, IU5 as i32) +} + +/// `Rdd32=vaslh(Rss32,#u4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vaslh, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaslh_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S2_asl_i_vh(rss, IU4 as i32) +} + +/// `Rdd32=vaslw(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vaslw, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaslw_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asl_i_vw(rss, IU5 as i32) +} + +/// `Rdd32=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asl_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p(rss, rt) +} + +/// `Rxx32+=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_acc(rxx, rss, rt) +} + +/// `Rxx32&=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asland_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_and(rxx, rss, rt) +} + +/// `Rxx32-=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_nac(rxx, rss, rt) +} + +/// `Rxx32|=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_or(rxx, rss, rt) +} + +/// `Rxx32^=asl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_aslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_p_xor(rxx, rss, rt) +} + +/// `Rd32=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asl_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r(rs, rt) +} + +/// `Rx32+=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_acc(rx, rs, rt) +} + +/// `Rx32&=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asland_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_and(rx, rs, rt) +} + +/// `Rx32-=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_nac(rx, rs, rt) +} + +/// `Rx32|=asl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_aslor_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_or(rx, rs, rt) +} + +/// `Rd32=asl(Rs32,Rt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asl_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_S2_asl_r_r_sat(rs, rt) +} + +/// `Rdd32=vaslh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaslh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_vh(rss, rt) +} + +/// `Rdd32=vaslw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vaslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vaslw_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asl_r_vw(rss, rt) +} + +/// `Rdd32=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asr_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p(rss, IU6 as i32) +} + +/// `Rxx32+=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asracc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_acc(rxx, rss, IU6 as i32) +} + +/// `Rxx32&=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrand_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_and(rxx, rss, IU6 as i32) +} + +/// `Rxx32-=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrnac_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_nac(rxx, rss, IU6 as i32) +} + +/// `Rxx32|=asr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asror_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_or(rxx, rss, IU6 as i32) +} + +/// `Rdd32=asr(Rss32,#u6):rnd` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asr_PI_rnd(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_rnd(rss, IU6 as i32) +} + +/// `Rdd32=asrrnd(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asrrnd, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrrnd_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_asr_i_p_rnd_goodsyntax(rss, IU6 as i32) +} + +/// `Rd32=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asr_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r(rs, IU5 as i32) +} + +/// `Rx32+=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asracc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_acc(rx, rs, IU5 as i32) +} + +/// `Rx32&=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrand_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_and(rx, rs, IU5 as i32) +} + +/// `Rx32-=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_nac(rx, rs, IU5 as i32) +} + +/// `Rx32|=asr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asror_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_or(rx, rs, IU5 as i32) +} + +/// `Rd32=asr(Rs32,#u5):rnd` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asr_RI_rnd(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_rnd(rs, IU5 as i32) +} + +/// `Rd32=asrrnd(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(asrrnd, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrrnd_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_r_rnd_goodsyntax(rs, IU5 as i32) +} + +/// `Rd32=vasrw(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vasrw_PI(rss: i64) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_svw_trun(rss, IU5 as i32) +} + +/// `Rdd32=vasrh(Rss32,#u4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrh_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S2_asr_i_vh(rss, IU4 as i32) +} + +/// `Rdd32=vasrw(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrw_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_asr_i_vw(rss, IU5 as i32) +} + +/// `Rdd32=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asr_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p(rss, rt) +} + +/// `Rxx32+=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_acc(rxx, rss, rt) +} + +/// `Rxx32&=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_and(rxx, rss, rt) +} + +/// `Rxx32-=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_nac(rxx, rss, rt) +} + +/// `Rxx32|=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asror_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_or(rxx, rss, rt) +} + +/// `Rxx32^=asr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_asrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_p_xor(rxx, rss, rt) +} + +/// `Rd32=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asr_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r(rs, rt) +} + +/// `Rx32+=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asracc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_acc(rx, rs, rt) +} + +/// `Rx32&=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_and(rx, rs, rt) +} + +/// `Rx32-=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_nac(rx, rs, rt) +} + +/// `Rx32|=asr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asror_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_or(rx, rs, rt) +} + +/// `Rd32=asr(Rs32,Rt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(asr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_asr_RR_sat(rs: i32, rt: i32) -> i32 { + hexagon_S2_asr_r_r_sat(rs, rt) +} + +/// `Rd32=vasrw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vasrw_PR(rss: i64, rt: i32) -> i32 { + hexagon_S2_asr_r_svw_trun(rss, rt) +} + +/// `Rdd32=vasrh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vasrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_vh(rss, rt) +} + +/// `Rdd32=vasrw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrw_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_asr_r_vw(rss, rt) +} + +/// `Rd32=brev(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(brev))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_brev_R(rs: i32) -> i32 { + hexagon_S2_brev(rs) +} + +/// `Rdd32=brev(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(brev))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_brev_P(rss: i64) -> i64 { + hexagon_S2_brevp(rss) +} + +/// `Rd32=cl0(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cl0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cl0_R(rs: i32) -> i32 { + hexagon_S2_cl0(rs) +} + +/// `Rd32=cl0(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cl0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cl0_P(rss: i64) -> i32 { + hexagon_S2_cl0p(rss) +} + +/// `Rd32=cl1(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cl1))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cl1_R(rs: i32) -> i32 { + hexagon_S2_cl1(rs) +} + +/// `Rd32=cl1(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(cl1))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cl1_P(rss: i64) -> i32 { + hexagon_S2_cl1p(rss) +} + +/// `Rd32=clb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(clb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clb_R(rs: i32) -> i32 { + hexagon_S2_clb(rs) +} + +/// `Rd32=normamt(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(normamt))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_normamt_R(rs: i32) -> i32 { + hexagon_S2_clbnorm(rs) +} + +/// `Rd32=clb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(clb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clb_P(rss: i64) -> i32 { + hexagon_S2_clbp(rss) +} + +/// `Rd32=clrbit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(clrbit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clrbit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_clrbit_i(rs, IU5 as i32) +} + +/// `Rd32=clrbit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(clrbit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clrbit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_clrbit_r(rs, rt) +} + +/// `Rd32=ct0(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(ct0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_ct0_R(rs: i32) -> i32 { + hexagon_S2_ct0(rs) +} + +/// `Rd32=ct0(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(ct0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_ct0_P(rss: i64) -> i32 { + hexagon_S2_ct0p(rss) +} + +/// `Rd32=ct1(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(ct1))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_ct1_R(rs: i32) -> i32 { + hexagon_S2_ct1(rs) +} + +/// `Rd32=ct1(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(ct1))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_ct1_P(rss: i64) -> i32 { + hexagon_S2_ct1p(rss) +} + +/// `Rdd32=deinterleave(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(deinterleave))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_deinterleave_P(rss: i64) -> i64 { + hexagon_S2_deinterleave(rss) +} + +/// `Rd32=extractu(Rs32,#u5,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(extractu, IU5 = 0, IU5_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_extractu_RII(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + static_assert_uimm_bits!(IU5_2, 5); + hexagon_S2_extractu(rs, IU5 as i32, IU5_2 as i32) +} + +/// `Rd32=extractu(Rs32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(extractu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_extractu_RP(rs: i32, rtt: i64) -> i32 { + hexagon_S2_extractu_rp(rs, rtt) +} + +/// `Rdd32=extractu(Rss32,#u6,#U6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(extractu, IU6 = 0, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_extractu_PII(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + static_assert_uimm_bits!(IU6_2, 6); + hexagon_S2_extractup(rss, IU6 as i32, IU6_2 as i32) +} + +/// `Rdd32=extractu(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(extractu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_extractu_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_extractup_rp(rss, rtt) +} + +/// `Rx32=insert(Rs32,#u5,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(insert, IU5 = 0, IU5_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_insert_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + static_assert_uimm_bits!(IU5_2, 5); + hexagon_S2_insert(rx, rs, IU5 as i32, IU5_2 as i32) +} + +/// `Rx32=insert(Rs32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(insert))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_insert_RP(rx: i32, rs: i32, rtt: i64) -> i32 { + hexagon_S2_insert_rp(rx, rs, rtt) +} + +/// `Rxx32=insert(Rss32,#u6,#U6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(insert, IU6 = 0, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_insert_PII(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + static_assert_uimm_bits!(IU6_2, 6); + hexagon_S2_insertp(rxx, rss, IU6 as i32, IU6_2 as i32) +} + +/// `Rxx32=insert(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(insert))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_insert_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_S2_insertp_rp(rxx, rss, rtt) +} + +/// `Rdd32=interleave(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(interleave))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_interleave_P(rss: i64) -> i64 { + hexagon_S2_interleave(rss) +} + +/// `Rdd32=lfs(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lfs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lfs_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_lfsp(rss, rtt) +} + +/// `Rdd32=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsl_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p(rss, rt) +} + +/// `Rxx32+=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_acc(rxx, rss, rt) +} + +/// `Rxx32&=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsland_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_and(rxx, rss, rt) +} + +/// `Rxx32-=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_nac(rxx, rss, rt) +} + +/// `Rxx32|=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_or(rxx, rss, rt) +} + +/// `Rxx32^=lsl(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_p_xor(rxx, rss, rt) +} + +/// `Rd32=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsl_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r(rs, rt) +} + +/// `Rx32+=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r_acc(rx, rs, rt) +} + +/// `Rx32&=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsland_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r_and(rx, rs, rt) +} + +/// `Rx32-=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r_nac(rx, rs, rt) +} + +/// `Rx32|=lsl(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lslor_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsl_r_r_or(rx, rs, rt) +} + +/// `Rdd32=vlslh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vlslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlslh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_vh(rss, rt) +} + +/// `Rdd32=vlslw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vlslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlslw_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsl_r_vw(rss, rt) +} + +/// `Rdd32=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsr_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p(rss, IU6 as i32) +} + +/// `Rxx32+=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsracc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_acc(rxx, rss, IU6 as i32) +} + +/// `Rxx32&=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrand_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_and(rxx, rss, IU6 as i32) +} + +/// `Rxx32-=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrnac_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_nac(rxx, rss, IU6 as i32) +} + +/// `Rxx32|=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsror_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_or(rxx, rss, IU6 as i32) +} + +/// `Rxx32^=lsr(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrxacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S2_lsr_i_p_xacc(rxx, rss, IU6 as i32) +} + +/// `Rd32=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsr_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r(rs, IU5 as i32) +} + +/// `Rx32+=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsracc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_acc(rx, rs, IU5 as i32) +} + +/// `Rx32&=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrand_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_and(rx, rs, IU5 as i32) +} + +/// `Rx32-=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_nac(rx, rs, IU5 as i32) +} + +/// `Rx32|=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsror_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_or(rx, rs, IU5 as i32) +} + +/// `Rx32^=lsr(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(lsr, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrxacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_r_xacc(rx, rs, IU5 as i32) +} + +/// `Rdd32=vlsrh(Rss32,#u4)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vlsrh, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlsrh_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S2_lsr_i_vh(rss, IU4 as i32) +} + +/// `Rdd32=vlsrw(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vlsrw, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlsrw_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_lsr_i_vw(rss, IU5 as i32) +} + +/// `Rdd32=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsr_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p(rss, rt) +} + +/// `Rxx32+=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_acc(rxx, rss, rt) +} + +/// `Rxx32&=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_and(rxx, rss, rt) +} + +/// `Rxx32-=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_nac(rxx, rss, rt) +} + +/// `Rxx32|=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsror_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_or(rxx, rss, rt) +} + +/// `Rxx32^=lsr(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_lsrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_p_xor(rxx, rss, rt) +} + +/// `Rd32=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsr_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r(rs, rt) +} + +/// `Rx32+=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsracc_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r_acc(rx, rs, rt) +} + +/// `Rx32&=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrand_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r_and(rx, rs, rt) +} + +/// `Rx32-=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r_nac(rx, rs, rt) +} + +/// `Rx32|=lsr(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(lsr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsror_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_S2_lsr_r_r_or(rx, rs, rt) +} + +/// `Rdd32=vlsrh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vlsrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlsrh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_vh(rss, rt) +} + +/// `Rdd32=vlsrw(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vlsrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vlsrw_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_lsr_r_vw(rss, rt) +} + +/// `Rdd32=packhl(Rs32,Rt32)` +/// +/// Instruction Type: ALU32_3op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(packhl))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_packhl_RR(rs: i32, rt: i32) -> i64 { + hexagon_S2_packhl(rs, rt) +} + +/// `Rd32=parity(Rss32,Rtt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(parity))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_parity_PP(rss: i64, rtt: i64) -> i32 { + hexagon_S2_parityp(rss, rtt) +} + +/// `Rd32=setbit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(setbit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_setbit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_setbit_i(rs, IU5 as i32) +} + +/// `Rd32=setbit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(setbit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_setbit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_setbit_r(rs, rt) +} + +/// `Rdd32=shuffeb(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(shuffeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_shuffeb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_shuffeb(rss, rtt) +} + +/// `Rdd32=shuffeh(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(shuffeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_shuffeh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_shuffeh(rss, rtt) +} + +/// `Rdd32=shuffob(Rtt32,Rss32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(shuffob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_shuffob_PP(rtt: i64, rss: i64) -> i64 { + hexagon_S2_shuffob(rtt, rss) +} + +/// `Rdd32=shuffoh(Rtt32,Rss32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(shuffoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_shuffoh_PP(rtt: i64, rss: i64) -> i64 { + hexagon_S2_shuffoh(rtt, rss) +} + +/// `Rd32=vsathb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsathb_R(rs: i32) -> i32 { + hexagon_S2_svsathb(rs) +} + +/// `Rd32=vsathub(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsathub_R(rs: i32) -> i32 { + hexagon_S2_svsathub(rs) +} + +/// `Rx32=tableidxb(Rs32,#u4,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(tableidxb, IU4 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_tableidxb_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU4, 4); + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tableidxb_goodsyntax(rx, rs, IU4 as i32, IU5 as i32) +} + +/// `Rx32=tableidxd(Rs32,#u4,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(tableidxd, IU4 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_tableidxd_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU4, 4); + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tableidxd_goodsyntax(rx, rs, IU4 as i32, IU5 as i32) +} + +/// `Rx32=tableidxh(Rs32,#u4,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(tableidxh, IU4 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_tableidxh_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU4, 4); + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tableidxh_goodsyntax(rx, rs, IU4 as i32, IU5 as i32) +} + +/// `Rx32=tableidxw(Rs32,#u4,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(2, 3)] +#[cfg_attr(test, assert_instr(tableidxw, IU4 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_tableidxw_RII(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU4, 4); + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tableidxw_goodsyntax(rx, rs, IU4 as i32, IU5 as i32) +} + +/// `Rd32=togglebit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(togglebit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_togglebit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_togglebit_i(rs, IU5 as i32) +} + +/// `Rd32=togglebit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(togglebit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_togglebit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_togglebit_r(rs, rt) +} + +/// `Pd4=tstbit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(tstbit, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_tstbit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S2_tstbit_i(rs, IU5 as i32) +} + +/// `Pd4=tstbit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(tstbit))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_tstbit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S2_tstbit_r(rs, rt) +} + +/// `Rdd32=valignb(Rtt32,Rss32,#u3)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(valignb, IU3 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_valignb_PPI(rtt: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU3, 3); + hexagon_S2_valignib(rtt, rss, IU3 as i32) +} + +/// `Rdd32=valignb(Rtt32,Rss32,Pu4)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(valignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_valignb_PPp(rtt: i64, rss: i64, pu: i32) -> i64 { + hexagon_S2_valignrb(rtt, rss, pu) +} + +/// `Rdd32=vcnegh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcnegh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcnegh_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_vcnegh(rss, rt) +} + +/// `Rdd32=vcrotate(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vcrotate))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vcrotate_PR(rss: i64, rt: i32) -> i64 { + hexagon_S2_vcrotate(rss, rt) +} + +/// `Rxx32+=vrcnegh(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrcnegh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcneghacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 { + hexagon_S2_vrcnegh(rxx, rss, rt) +} + +/// `Rd32=vrndwh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrndwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vrndwh_P(rss: i64) -> i32 { + hexagon_S2_vrndpackwh(rss) +} + +/// `Rd32=vrndwh(Rss32):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vrndwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vrndwh_P_sat(rss: i64) -> i32 { + hexagon_S2_vrndpackwhs(rss) +} + +/// `Rd32=vsathb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsathb_P(rss: i64) -> i32 { + hexagon_S2_vsathb(rss) +} + +/// `Rdd32=vsathb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsathb_P(rss: i64) -> i64 { + hexagon_S2_vsathb_nopack(rss) +} + +/// `Rd32=vsathub(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsathub_P(rss: i64) -> i32 { + hexagon_S2_vsathub(rss) +} + +/// `Rdd32=vsathub(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsathub_P(rss: i64) -> i64 { + hexagon_S2_vsathub_nopack(rss) +} + +/// `Rd32=vsatwh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsatwh_P(rss: i64) -> i32 { + hexagon_S2_vsatwh(rss) +} + +/// `Rdd32=vsatwh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsatwh_P(rss: i64) -> i64 { + hexagon_S2_vsatwh_nopack(rss) +} + +/// `Rd32=vsatwuh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsatwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsatwuh_P(rss: i64) -> i32 { + hexagon_S2_vsatwuh(rss) +} + +/// `Rdd32=vsatwuh(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsatwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsatwuh_P(rss: i64) -> i64 { + hexagon_S2_vsatwuh_nopack(rss) +} + +/// `Rd32=vsplatb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vsplatb_R(rs: i32) -> i32 { + hexagon_S2_vsplatrb(rs) +} + +/// `Rdd32=vsplath(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsplath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsplath_R(rs: i32) -> i64 { + hexagon_S2_vsplatrh(rs) +} + +/// `Rdd32=vspliceb(Rss32,Rtt32,#u3)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vspliceb, IU3 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vspliceb_PPI(rss: i64, rtt: i64) -> i64 { + static_assert_uimm_bits!(IU3, 3); + hexagon_S2_vspliceib(rss, rtt, IU3 as i32) +} + +/// `Rdd32=vspliceb(Rss32,Rtt32,Pu4)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vspliceb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vspliceb_PPp(rss: i64, rtt: i64, pu: i32) -> i64 { + hexagon_S2_vsplicerb(rss, rtt, pu) +} + +/// `Rdd32=vsxtbh(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsxtbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsxtbh_R(rs: i32) -> i64 { + hexagon_S2_vsxtbh(rs) +} + +/// `Rdd32=vsxthw(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vsxthw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsxthw_R(rs: i32) -> i64 { + hexagon_S2_vsxthw(rs) +} + +/// `Rd32=vtrunehb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vtrunehb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vtrunehb_P(rss: i64) -> i32 { + hexagon_S2_vtrunehb(rss) +} + +/// `Rdd32=vtrunewh(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vtrunewh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vtrunewh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_vtrunewh(rss, rtt) +} + +/// `Rd32=vtrunohb(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vtrunohb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vtrunohb_P(rss: i64) -> i32 { + hexagon_S2_vtrunohb(rss) +} + +/// `Rdd32=vtrunowh(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vtrunowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vtrunowh_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S2_vtrunowh(rss, rtt) +} + +/// `Rdd32=vzxtbh(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vzxtbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vzxtbh_R(rs: i32) -> i64 { + hexagon_S2_vzxtbh(rs) +} + +/// `Rdd32=vzxthw(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vzxthw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vzxthw_R(rs: i32) -> i64 { + hexagon_S2_vzxthw(rs) +} + +/// `Rd32=add(Rs32,add(Ru32,#s6))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(add, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_add_RRI(rs: i32, ru: i32) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_addaddi(rs, ru, IS6) +} + +/// `Rx32=add(#u8,asl(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_asl_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_addi_asl_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=add(#u8,lsr(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_lsr_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_addi_lsr_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=and(#u8,asl(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_asl_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_andi_asl_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=and(#u8,lsr(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_and_lsr_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_andi_lsr_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rd32=add(clb(Rs32),#s6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_clb_RI(rs: i32) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_clbaddi(rs, IS6) +} + +/// `Rd32=add(clb(Rss32),#s6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_clb_PI(rss: i64) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_clbpaddi(rss, IS6) +} + +/// `Rd32=normamt(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(normamt))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_normamt_P(rss: i64) -> i32 { + hexagon_S4_clbpnorm(rss) +} + +/// `Rd32=extract(Rs32,#u5,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(extract, IU5 = 0, IU5_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_extract_RII(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + static_assert_uimm_bits!(IU5_2, 5); + hexagon_S4_extract(rs, IU5 as i32, IU5_2 as i32) +} + +/// `Rd32=extract(Rs32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(extract))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_extract_RP(rs: i32, rtt: i64) -> i32 { + hexagon_S4_extract_rp(rs, rtt) +} + +/// `Rdd32=extract(Rss32,#u6,#U6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1, 2)] +#[cfg_attr(test, assert_instr(extract, IU6 = 0, IU6_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_extract_PII(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + static_assert_uimm_bits!(IU6_2, 6); + hexagon_S4_extractp(rss, IU6 as i32, IU6_2 as i32) +} + +/// `Rdd32=extract(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(extract))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_extract_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S4_extractp_rp(rss, rtt) +} + +/// `Rd32=lsl(#s6,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0)] +#[cfg_attr(test, assert_instr(lsl, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_lsl_IR(rt: i32) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_lsli(IS6, rt) +} + +/// `Pd4=!tstbit(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_tstbit_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_ntstbit_i(rs, IU5 as i32) +} + +/// `Pd4=!tstbit(Rs32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_tstbit_RR(rs: i32, rt: i32) -> i32 { + hexagon_S4_ntstbit_r(rs, rt) +} + +/// `Rx32|=and(Rs32,#s10)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(and, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_andor_RI(rx: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_S4_or_andi(rx, rs, IS10) +} + +/// `Rx32=or(Ru32,and(Rx32,#s10))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(or, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_and_RRI(ru: i32, rx: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_S4_or_andix(ru, rx, IS10) +} + +/// `Rx32|=or(Rs32,#s10)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(or, IS10 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_oror_RI(rx: i32, rs: i32) -> i32 { + static_assert_simm_bits!(IS10, 10); + hexagon_S4_or_ori(rx, rs, IS10) +} + +/// `Rx32=or(#u8,asl(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_asl_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_ori_asl_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=or(#u8,lsr(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_or_lsr_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_ori_lsr_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rd32=parity(Rs32,Rt32)` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(parity))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_parity_RR(rs: i32, rt: i32) -> i32 { + hexagon_S4_parity(rs, rt) +} + +/// `Rd32=add(Rs32,sub(#s6,Ru32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(add, IS6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_add_sub_RIR(rs: i32, ru: i32) -> i32 { + static_assert_simm_bits!(IS6, 6); + hexagon_S4_subaddi(rs, IS6, ru) +} + +/// `Rx32=sub(#u8,asl(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_asl_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_subi_asl_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rx32=sub(#u8,lsr(Rx32,#U5))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(0, 2)] +#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_sub_lsr_IRI(rx: i32) -> i32 { + static_assert_uimm_bits!(IU8, 8); + static_assert_uimm_bits!(IU5, 5); + hexagon_S4_subi_lsr_ri(IU8 as i32, rx, IU5 as i32) +} + +/// `Rdd32=vrcrotate(Rss32,Rt32,#u2)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcrotate_PRI(rss: i64, rt: i32) -> i64 { + static_assert_uimm_bits!(IU2, 2); + hexagon_S4_vrcrotate(rss, rt, IU2 as i32) +} + +/// `Rxx32+=vrcrotate(Rss32,Rt32,#u2)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vrcrotateacc_PRI(rxx: i64, rss: i64, rt: i32) -> i64 { + static_assert_uimm_bits!(IU2, 2); + hexagon_S4_vrcrotate_acc(rxx, rss, rt, IU2 as i32) +} + +/// `Rdd32=vxaddsubh(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxaddsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxaddsubh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxaddsubh(rss, rtt) +} + +/// `Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxaddsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxaddsubh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxaddsubhr(rss, rtt) +} + +/// `Rdd32=vxaddsubw(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxaddsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxaddsubw_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxaddsubw(rss, rtt) +} + +/// `Rdd32=vxsubaddh(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxsubaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxsubaddh_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxsubaddh(rss, rtt) +} + +/// `Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxsubaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxsubaddh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxsubaddhr(rss, rtt) +} + +/// `Rdd32=vxsubaddw(Rss32,Rtt32):sat` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(vxsubaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vxsubaddw_PP_sat(rss: i64, rtt: i64) -> i64 { + hexagon_S4_vxsubaddw(rss, rtt) +} + +/// `Rd32=vasrhub(Rss32,#u4):rnd:sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vasrhub_PI_rnd_sat(rss: i64) -> i32 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S5_asrhub_rnd_sat_goodsyntax(rss, IU4 as i32) +} + +/// `Rd32=vasrhub(Rss32,#u4):sat` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_vasrhub_PI_sat(rss: i64) -> i32 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S5_asrhub_sat(rss, IU4 as i32) +} + +/// `Rd32=popcount(Rss32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(test, assert_instr(popcount))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_popcount_P(rss: i64) -> i32 { + hexagon_S5_popcountp(rss) +} + +/// `Rdd32=vasrh(Rss32,#u4):rnd` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT0123 +#[inline(always)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vasrh_PI_rnd(rss: i64) -> i64 { + static_assert_uimm_bits!(IU4, 4); + hexagon_S5_vasrhrnd_goodsyntax(rss, IU4 as i32) +} + +/// `dccleana(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(dccleana))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dccleana_A(rs: i32) { + hexagon_Y2_dccleana(rs) +} + +/// `dccleaninva(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(dccleaninva))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dccleaninva_A(rs: i32) { + hexagon_Y2_dccleaninva(rs) +} + +/// `dcfetch(Rs32)` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(test, assert_instr(dcfetch))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dcfetch_A(rs: i32) { + hexagon_Y2_dcfetch(rs) +} + +/// `dcinva(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(dcinva))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dcinva_A(rs: i32) { + hexagon_Y2_dcinva(rs) +} + +/// `dczeroa(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(dczeroa))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dczeroa_A(rs: i32) { + hexagon_Y2_dczeroa(rs) +} + +/// `l2fetch(Rs32,Rt32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(l2fetch))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_l2fetch_AR(rs: i32, rt: i32) { + hexagon_Y4_l2fetch(rs, rt) +} + +/// `l2fetch(Rs32,Rtt32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(test, assert_instr(l2fetch))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_l2fetch_AP(rs: i32, rtt: i64) { + hexagon_Y5_l2fetch(rs, rtt) +} + +/// `Rdd32=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rol_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p(rss, IU6 as i32) +} + +/// `Rxx32+=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rolacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_acc(rxx, rss, IU6 as i32) +} + +/// `Rxx32&=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_roland_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_and(rxx, rss, IU6 as i32) +} + +/// `Rxx32-=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rolnac_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_nac(rxx, rss, IU6 as i32) +} + +/// `Rxx32|=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rolor_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_or(rxx, rss, IU6 as i32) +} + +/// `Rxx32^=rol(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_rolxacc_PI(rxx: i64, rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_S6_rol_i_p_xacc(rxx, rss, IU6 as i32) +} + +/// `Rd32=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rol_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r(rs, IU5 as i32) +} + +/// `Rx32+=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rolacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_acc(rx, rs, IU5 as i32) +} + +/// `Rx32&=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_roland_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_and(rx, rs, IU5 as i32) +} + +/// `Rx32-=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rolnac_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_nac(rx, rs, IU5 as i32) +} + +/// `Rx32|=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rolor_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_or(rx, rs, IU5 as i32) +} + +/// `Rx32^=rol(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V60 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(rol, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_rolxacc_RI(rx: i32, rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_S6_rol_i_r_xacc(rx, rs, IU5 as i32) +} + +/// `Rdd32=vabsdiffb(Rtt32,Rss32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vabsdiffb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsdiffb_PP(rtt: i64, rss: i64) -> i64 { + hexagon_M6_vabsdiffb(rtt, rss) +} + +/// `Rdd32=vabsdiffub(Rtt32,Rss32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vabsdiffub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vabsdiffub_PP(rtt: i64, rss: i64) -> i64 { + hexagon_M6_vabsdiffub(rtt, rss) +} + +/// `Rdd32=vsplatb(Rs32)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vsplatb_R(rs: i32) -> i64 { + hexagon_S6_vsplatrbp(rs) +} + +/// `Rdd32=vtrunehb(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vtrunehb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vtrunehb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S6_vtrunehb_ppp(rss, rtt) +} + +/// `Rdd32=vtrunohb(Rss32,Rtt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +/// Requires: V62 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))] +#[cfg_attr(test, assert_instr(vtrunohb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vtrunohb_PP(rss: i64, rtt: i64) -> i64 { + hexagon_S6_vtrunohb_ppp(rss, rtt) +} + +/// `Pd4=!any8(vcmpb.eq(Rss32,Rtt32))` +/// +/// Instruction Type: ALU64 +/// Execution Slots: SLOT23 +/// Requires: V65 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_p_not_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 { + hexagon_A6_vcmpbeq_notany(rss, rtt) +} + +/// `Rdd32=dfadd(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V66 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] +#[cfg_attr(test, assert_instr(dfadd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfadd_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfadd(rss, rtt) +} + +/// `Rdd32=dfsub(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V66 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] +#[cfg_attr(test, assert_instr(dfsub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfsub_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfsub(rss, rtt) +} + +/// `Rx32-=mpyi(Rs32,Rt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V66 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] +#[cfg_attr(test, assert_instr(mpyi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mpyinac_RR(rx: i32, rs: i32, rt: i32) -> i32 { + hexagon_M2_mnaci(rx, rs, rt) +} + +/// `Rd32=mask(#u5,#U5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V66 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] +#[rustc_legacy_const_generics(0, 1)] +#[cfg_attr(test, assert_instr(mask, IU5 = 0, IU5_2 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_mask_II() -> i32 { + static_assert_uimm_bits!(IU5, 5); + static_assert_uimm_bits!(IU5_2, 5); + hexagon_S2_mask(IU5 as i32, IU5_2 as i32) +} + +/// `Rd32=clip(Rs32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(clip, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_clip_RI(rs: i32) -> i32 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A7_clip(rs, IU5 as i32) +} + +/// `Rdd32=cround(Rss32,#u6)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(cround, IU6 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cround_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU6, 6); + hexagon_A7_croundd_ri(rss, IU6 as i32) +} + +/// `Rdd32=cround(Rss32,Rt32)` +/// +/// Instruction Type: S_3op +/// Execution Slots: SLOT23 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cround))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cround_PR(rss: i64, rt: i32) -> i64 { + hexagon_A7_croundd_rr(rss, rt) +} + +/// `Rdd32=vclip(Rss32,#u5)` +/// +/// Instruction Type: S_2op +/// Execution Slots: SLOT23 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(vclip, IU5 = 0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vclip_PI(rss: i64) -> i64 { + static_assert_uimm_bits!(IU5, 5); + hexagon_A7_vclip(rss, IU5 as i32) +} + +/// `Rdd32=dfmax(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmax))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmax_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmax(rss, rtt) +} + +/// `Rdd32=dfmin(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmin))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmin_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmin(rss, rtt) +} + +/// `Rdd32=dfmpyfix(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmpyfix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmpyfix_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmpyfix(rss, rtt) +} + +/// `Rxx32+=dfmpyhh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmpyhh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmpyhhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmpyhh(rxx, rss, rtt) +} + +/// `Rxx32+=dfmpylh(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmpylh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmpylhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmpylh(rxx, rss, rtt) +} + +/// `Rdd32=dfmpyll(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT23 +/// Requires: V67 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))] +#[cfg_attr(test, assert_instr(dfmpyll))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_dfmpyll_PP(rss: f64, rtt: f64) -> f64 { + hexagon_F2_dfmpyll(rss, rtt) +} + +/// `Rdd32=cmpyiw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyiw(rss, rtt) +} + +/// `Rxx32+=cmpyiw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyiw_acc(rxx, rss, rtt) +} + +/// `Rdd32=cmpyiw(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiw_PP_conj(rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyiwc(rss, rtt) +} + +/// `Rxx32+=cmpyiw(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyiwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyiwc_acc(rxx, rss, rtt) +} + +/// `Rdd32=cmpyrw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyrw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyrw(rss, rtt) +} + +/// `Rxx32+=cmpyrw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyrwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyrw_acc(rxx, rss, rtt) +} + +/// `Rdd32=cmpyrw(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyrw_PP_conj(rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyrwc(rss, rtt) +} + +/// `Rxx32+=cmpyrw(Rss32,Rtt32*)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_cmpyrwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_dcmpyrwc_acc(rxx, rss, rtt) +} + +/// `Rdd32=vdmpyw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(vdmpyw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpyw_PP(rss: i64, rtt: i64) -> i64 { + hexagon_M7_vdmpy(rss, rtt) +} + +/// `Rxx32+=vdmpyw(Rss32,Rtt32)` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(vdmpyw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_P_vdmpywacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 { + hexagon_M7_vdmpy_acc(rxx, rss, rtt) +} + +/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiw_PP_s1_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyiw(rss, rtt) +} + +/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyiw_rnd(rss, rtt) +} + +/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyiwc(rss, rtt) +} + +/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyiw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyiwc_rnd(rss, rtt) +} + +/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrw_PP_s1_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyrw(rss, rtt) +} + +/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyrw_rnd(rss, rtt) +} + +/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyrwc(rss, rtt) +} + +/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat` +/// +/// Instruction Type: M +/// Execution Slots: SLOT3 +/// Requires: V67, Audio +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] +#[cfg_attr(test, assert_instr(cmpyrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 { + hexagon_M7_wcmpyrwc_rnd(rss, rtt) +} + +/// `dmlink(Rs32,Rt32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmlink))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dmlink_AA(rs: i32, rt: i32) { + hexagon_Y6_dmlink(rs, rt) +} + +/// `Rd32=dmpause` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmpause))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_dmpause() -> i32 { + hexagon_Y6_dmpause() +} + +/// `Rd32=dmpoll` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmpoll))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_dmpoll() -> i32 { + hexagon_Y6_dmpoll() +} + +/// `dmresume(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmresume))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dmresume_A(rs: i32) { + hexagon_Y6_dmresume(rs) +} + +/// `dmstart(Rs32)` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmstart))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_dmstart_A(rs: i32) { + hexagon_Y6_dmstart(rs) +} + +/// `Rd32=dmwait` +/// +/// Instruction Type: ST +/// Execution Slots: SLOT0 +/// Requires: V68 +#[inline] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))] +#[cfg_attr(test, assert_instr(dmwait))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn Q6_R_dmwait() -> i32 { + hexagon_Y6_dmwait() +} diff --git a/stdarch/crates/core_arch/src/hexagon/v128.rs b/stdarch/crates/core_arch/src/hexagon/v128.rs index ef7ff4205c71d..1f0566af78ef3 100644 --- a/stdarch/crates/core_arch/src/hexagon/v128.rs +++ b/stdarch/crates/core_arch/src/hexagon/v128.rs @@ -15,6 +15,18 @@ //! //! To use this module, compile with `-C target-feature=+hvx-length128b`. //! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! //! ## Architecture Versions //! //! Different intrinsics require different HVX architecture versions. Use the @@ -31,6 +43,7 @@ //! Each version includes all features from previous versions. #![allow(non_camel_case_types)] +#![allow(non_snake_case)] #[cfg(test)] use stdarch_test::assert_instr; @@ -1030,11 +1043,11 @@ unsafe extern "unadjusted" { /// /// Instruction Type: LD /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(extractw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { +pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 { extractw(vu, rs) } @@ -1042,11 +1055,11 @@ pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(hi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector { hi(vss) } @@ -1054,11 +1067,11 @@ pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(lo))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector { lo(vss) } @@ -1066,11 +1079,11 @@ pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(lvsplatw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector { lvsplatw(rt) } @@ -1078,11 +1091,11 @@ pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffh(vu, vv) } @@ -1090,11 +1103,11 @@ pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffub(vu, vv) } @@ -1102,11 +1115,11 @@ pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffuh(vu, vv) } @@ -1114,11 +1127,11 @@ pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffw(vu, vv) } @@ -1126,11 +1139,11 @@ pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector { vabsh(vu) } @@ -1138,11 +1151,11 @@ pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector { vabsh_sat(vu) } @@ -1150,11 +1163,11 @@ pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector { vabsw(vu) } @@ -1162,11 +1175,11 @@ pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsw_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector { vabsw_sat(vu) } @@ -1174,11 +1187,11 @@ pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddb(vu, vv) } @@ -1186,11 +1199,11 @@ pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddb_dv(vuu, vvv) } @@ -1198,11 +1211,11 @@ pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddh(vu, vv) } @@ -1210,11 +1223,11 @@ pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddh_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddh_dv(vuu, vvv) } @@ -1222,11 +1235,11 @@ pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddhsat(vu, vv) } @@ -1234,11 +1247,11 @@ pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddhsat_dv(vuu, vvv) } @@ -1246,11 +1259,11 @@ pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vaddhw(vu, vv) } @@ -1258,11 +1271,11 @@ pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vaddubh(vu, vv) } @@ -1270,11 +1283,11 @@ pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddubsat(vu, vv) } @@ -1282,11 +1295,11 @@ pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddubsat_dv(vuu, vvv) } @@ -1294,11 +1307,11 @@ pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vadduhsat(vu, vv) } @@ -1306,11 +1319,11 @@ pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vadduhsat_dv(vuu, vvv) } @@ -1318,11 +1331,11 @@ pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vadduhw(vu, vv) } @@ -1330,11 +1343,11 @@ pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_add(vu, vv) } @@ -1342,11 +1355,11 @@ pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddw_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddw_dv(vuu, vvv) } @@ -1354,11 +1367,11 @@ pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddwsat(vu, vv) } @@ -1366,11 +1379,11 @@ pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddwsat_dv(vuu, vvv) } @@ -1378,11 +1391,11 @@ pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(valignb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { valignb(vu, vv, rt) } @@ -1390,11 +1403,11 @@ pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(valignbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { valignbi(vu, vv, iu3) } @@ -1402,11 +1415,11 @@ pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vand))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_and(vu, vv) } @@ -1414,11 +1427,11 @@ pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector { vaslh(vu, rt) } @@ -1426,11 +1439,11 @@ pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaslhv(vu, vv) } @@ -1438,11 +1451,11 @@ pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector { vaslw(vu, rt) } @@ -1450,11 +1463,11 @@ pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vaslw_acc(vx, vu, rt) } @@ -1462,11 +1475,11 @@ pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vaslwv(vu, vv) } @@ -1474,11 +1487,11 @@ pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector { vasrh(vu, rt) } @@ -1486,11 +1499,11 @@ pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhbrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhbrndsat(vu, vv, rt) } @@ -1498,11 +1511,11 @@ pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhubrndsat(vu, vv, rt) } @@ -1510,11 +1523,11 @@ pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhubsat(vu, vv, rt) } @@ -1522,11 +1535,11 @@ pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vasrhv(vu, vv) } @@ -1534,11 +1547,11 @@ pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector { vasrw(vu, rt) } @@ -1546,11 +1559,11 @@ pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vasrw_acc(vx, vu, rt) } @@ -1558,11 +1571,11 @@ pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwh(vu, vv, rt) } @@ -1570,11 +1583,11 @@ pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwhrndsat(vu, vv, rt) } @@ -1582,11 +1595,11 @@ pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwhsat(vu, vv, rt) } @@ -1594,11 +1607,11 @@ pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwuhsat(vu, vv, rt) } @@ -1606,11 +1619,11 @@ pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vasrwv(vu, vv) } @@ -1618,11 +1631,11 @@ pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vassign))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector { vassign(vu) } @@ -1630,11 +1643,11 @@ pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vassignp))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair { vassignp(vuu) } @@ -1642,11 +1655,11 @@ pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgh(vu, vv) } @@ -1654,11 +1667,11 @@ pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavghrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavghrnd(vu, vv) } @@ -1666,11 +1679,11 @@ pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgub(vu, vv) } @@ -1678,11 +1691,11 @@ pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgubrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgubrnd(vu, vv) } @@ -1690,11 +1703,11 @@ pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavguh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguh(vu, vv) } @@ -1702,11 +1715,11 @@ pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavguhrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguhrnd(vu, vv) } @@ -1714,11 +1727,11 @@ pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgw(vu, vv) } @@ -1726,11 +1739,11 @@ pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgwrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgwrnd(vu, vv) } @@ -1738,11 +1751,11 @@ pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcl0h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector { vcl0h(vu) } @@ -1750,11 +1763,11 @@ pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcl0w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector { vcl0w(vu) } @@ -1762,11 +1775,11 @@ pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcombine))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vcombine(vu, vv) } @@ -1774,11 +1787,11 @@ pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vd0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vzero() -> HvxVector { +pub unsafe fn Q6_V_vzero() -> HvxVector { vd0() } @@ -1786,11 +1799,11 @@ pub unsafe fn q6_v_vzero() -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector { vdealb(vu) } @@ -1798,11 +1811,11 @@ pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealb4w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vdealb4w(vu, vv) } @@ -1810,11 +1823,11 @@ pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector { vdealh(vu) } @@ -1822,11 +1835,11 @@ pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealvdd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vdealvdd(vu, vv, rt) } @@ -1834,11 +1847,11 @@ pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdelta))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vdelta(vu, vv) } @@ -1846,11 +1859,11 @@ pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { vdmpybus(vu, rt) } @@ -1858,11 +1871,11 @@ pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpybus_acc(vx, vu, rt) } @@ -1870,11 +1883,11 @@ pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdmpybus_dv(vuu, rt) } @@ -1882,11 +1895,11 @@ pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vdmpyacc_whwubrb( +pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -1898,11 +1911,11 @@ pub unsafe fn q6_wh_vdmpyacc_whwubrb( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhb(vu, rt) } @@ -1910,11 +1923,11 @@ pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhb_acc(vx, vu, rt) } @@ -1922,11 +1935,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdmpyhb_dv(vuu, rt) } @@ -1934,11 +1947,11 @@ pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vdmpyacc_wwwhrb( +pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -1950,11 +1963,11 @@ pub unsafe fn q6_ww_vdmpyacc_wwwhrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhisat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhisat(vuu, rt) } @@ -1962,11 +1975,11 @@ pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhisat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhisat_acc(vx, vuu, rt) } @@ -1974,11 +1987,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsat(vu, rt) } @@ -1986,11 +1999,11 @@ pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsat_acc(vx, vu, rt) } @@ -1998,11 +2011,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsuisat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhsuisat(vuu, rt) } @@ -2010,11 +2023,11 @@ pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhsuisat_acc(vx, vuu, rt) } @@ -2022,11 +2035,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsusat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsusat(vu, rt) } @@ -2034,11 +2047,11 @@ pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsusat_acc(vx, vu, rt) } @@ -2046,11 +2059,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhvsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpyhvsat(vu, vv) } @@ -2058,11 +2071,11 @@ pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpyhvsat_acc(vx, vu, vv) } @@ -2070,11 +2083,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVec /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdsaduh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdsaduh(vuu, rt) } @@ -2082,11 +2095,11 @@ pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdsaduh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( +pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2098,11 +2111,11 @@ pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vinsertwr))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector { vinsertwr(vx, rt) } @@ -2110,11 +2123,11 @@ pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlalignb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlalignb(vu, vv, rt) } @@ -2122,11 +2135,11 @@ pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlalignbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { vlalignbi(vu, vv, iu3) } @@ -2134,11 +2147,11 @@ pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVec /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector { vlsrh(vu, rt) } @@ -2146,11 +2159,11 @@ pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vlsrhv(vu, vv) } @@ -2158,11 +2171,11 @@ pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector { vlsrw(vu, rt) } @@ -2170,11 +2183,11 @@ pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vlsrwv(vu, vv) } @@ -2182,11 +2195,11 @@ pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvvb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlutvvb(vu, vv, rt) } @@ -2194,11 +2207,11 @@ pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvvb_oracc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32or_vbvbvbr( +pub unsafe fn Q6_Vb_vlut32or_VbVbVbR( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2211,11 +2224,11 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbr( /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vlutvwh(vu, vv, rt) } @@ -2223,11 +2236,11 @@ pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvwh_oracc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16or_whvbvhr( +pub unsafe fn Q6_Wh_vlut16or_WhVbVhR( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2240,11 +2253,11 @@ pub unsafe fn q6_wh_vlut16or_whvbvhr( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxh(vu, vv) } @@ -2252,11 +2265,11 @@ pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxub(vu, vv) } @@ -2264,11 +2277,11 @@ pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxuh(vu, vv) } @@ -2276,11 +2289,11 @@ pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxw(vu, vv) } @@ -2288,11 +2301,11 @@ pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vminh(vu, vv) } @@ -2300,11 +2313,11 @@ pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vminub(vu, vv) } @@ -2312,11 +2325,11 @@ pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vminuh(vu, vv) } @@ -2324,11 +2337,11 @@ pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vminw(vu, vv) } @@ -2336,11 +2349,11 @@ pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpabus(vuu, rt) } @@ -2348,11 +2361,11 @@ pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpaacc_whwubrb( +pub unsafe fn Q6_Wh_vmpaacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2364,11 +2377,11 @@ pub unsafe fn q6_wh_vmpaacc_whwubrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vmpabusv(vuu, vvv) } @@ -2376,11 +2389,11 @@ pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVec /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabuuv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vmpabuuv(vuu, vvv) } @@ -2388,11 +2401,11 @@ pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVe /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpahb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpahb(vuu, rt) } @@ -2400,11 +2413,11 @@ pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpahb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpaacc_wwwhrb( +pub unsafe fn Q6_Ww_vmpaacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2416,11 +2429,11 @@ pub unsafe fn q6_ww_vmpaacc_wwwhrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpybus(vu, rt) } @@ -2428,11 +2441,11 @@ pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { vmpybus_acc(vxx, vu, rt) } @@ -2440,11 +2453,11 @@ pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpybusv(vu, vv) } @@ -2452,11 +2465,11 @@ pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybusv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvubvb( +pub unsafe fn Q6_Wh_vmpyacc_WhVubVb( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2468,11 +2481,11 @@ pub unsafe fn q6_wh_vmpyacc_whvubvb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpybv(vu, vv) } @@ -2480,11 +2493,11 @@ pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvbvb( +pub unsafe fn Q6_Wh_vmpyacc_WhVbVb( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2496,11 +2509,11 @@ pub unsafe fn q6_wh_vmpyacc_whvbvb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyewuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyewuh(vu, vv) } @@ -2508,11 +2521,11 @@ pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyh(vu, rt) } @@ -2520,11 +2533,11 @@ pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2536,11 +2549,11 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhsrs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { vmpyhsrs(vu, rt) } @@ -2548,11 +2561,11 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhss))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { vmpyhss(vu, rt) } @@ -2560,11 +2573,11 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyhus(vu, vv) } @@ -2572,11 +2585,11 @@ pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhvuh( +pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2588,11 +2601,11 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvuh( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyhv(vu, vv) } @@ -2600,11 +2613,11 @@ pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhvh( +pub unsafe fn Q6_Ww_vmpyacc_WwVhVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2616,11 +2629,11 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvh( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhvsrs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyhvsrs(vu, vv) } @@ -2628,11 +2641,11 @@ pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVec /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyieoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyieoh(vu, vv) } @@ -2640,11 +2653,11 @@ pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewh_acc(vx, vu, vv) } @@ -2652,11 +2665,11 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewuh(vu, vv) } @@ -2664,11 +2677,11 @@ pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewuh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewuh_acc(vx, vu, vv) } @@ -2676,11 +2689,11 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVecto /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyih))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyih(vu, vv) } @@ -2688,11 +2701,11 @@ pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyih_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyih_acc(vx, vu, vv) } @@ -2700,11 +2713,11 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyihb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector { vmpyihb(vu, rt) } @@ -2712,11 +2725,11 @@ pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyihb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyihb_acc(vx, vu, rt) } @@ -2724,11 +2737,11 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiowh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiowh(vu, vv) } @@ -2736,11 +2749,11 @@ pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwb(vu, rt) } @@ -2748,11 +2761,11 @@ pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwb_acc(vx, vu, rt) } @@ -2760,11 +2773,11 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwh(vu, rt) } @@ -2772,11 +2785,11 @@ pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwh_acc(vx, vu, rt) } @@ -2784,11 +2797,11 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyowh(vu, vv) } @@ -2796,11 +2809,11 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_rnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyowh_rnd(vu, vv) } @@ -2808,11 +2821,11 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVe /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2824,11 +2837,11 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_sacc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2840,11 +2853,11 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyub(vu, rt) } @@ -2852,11 +2865,11 @@ pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2868,11 +2881,11 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyubv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyubv(vu, vv) } @@ -2880,11 +2893,11 @@ pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyubv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2896,11 +2909,11 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyuh(vu, rt) } @@ -2908,11 +2921,11 @@ pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2924,11 +2937,11 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyuhv(vu, vv) } @@ -2936,11 +2949,11 @@ pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuhv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2952,11 +2965,11 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgh(vu, vv) } @@ -2964,11 +2977,11 @@ pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgub(vu, vv) } @@ -2976,11 +2989,11 @@ pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgw(vu, vv) } @@ -2988,11 +3001,11 @@ pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnormamth))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector { vnormamth(vu) } @@ -3000,11 +3013,11 @@ pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnormamtw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector { vnormamtw(vu) } @@ -3012,11 +3025,11 @@ pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnot))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector { vnot(vu) } @@ -3024,11 +3037,11 @@ pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vor))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_or(vu, vv) } @@ -3036,11 +3049,11 @@ pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackeb(vu, vv) } @@ -3048,11 +3061,11 @@ pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackeh(vu, vv) } @@ -3060,11 +3073,11 @@ pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackhb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackhb_sat(vu, vv) } @@ -3072,11 +3085,11 @@ pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackhub_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackhub_sat(vu, vv) } @@ -3084,11 +3097,11 @@ pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackob(vu, vv) } @@ -3096,11 +3109,11 @@ pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackoh(vu, vv) } @@ -3108,11 +3121,11 @@ pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackwh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackwh_sat(vu, vv) } @@ -3120,11 +3133,11 @@ pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackwuh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackwuh_sat(vu, vv) } @@ -3132,11 +3145,11 @@ pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpopcounth))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector { vpopcounth(vu) } @@ -3144,11 +3157,11 @@ pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrdelta))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vrdelta(vu, vv) } @@ -3156,11 +3169,11 @@ pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { vrmpybus(vu, rt) } @@ -3168,11 +3181,11 @@ pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vrmpybus_acc(vx, vu, rt) } @@ -3180,11 +3193,11 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrmpybusi(vuu, rt, iu1) } @@ -3192,11 +3205,11 @@ pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVe /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( +pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3209,11 +3222,11 @@ pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybusv(vu, vv) } @@ -3221,11 +3234,11 @@ pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybusv_acc(vx, vu, vv) } @@ -3233,11 +3246,11 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybv(vu, vv) } @@ -3245,11 +3258,11 @@ pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybv_acc(vx, vu, vv) } @@ -3257,11 +3270,11 @@ pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector { vrmpyub(vu, rt) } @@ -3269,11 +3282,11 @@ pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vrmpyub_acc(vx, vu, rt) } @@ -3281,11 +3294,11 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrmpyubi(vuu, rt, iu1) } @@ -3293,11 +3306,11 @@ pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( +pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3310,11 +3323,11 @@ pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpyubv(vu, vv) } @@ -3322,11 +3335,11 @@ pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpyubv_acc(vx, vu, vv) } @@ -3334,11 +3347,11 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVec /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vror))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector { vror(vu, rt) } @@ -3346,11 +3359,11 @@ pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundhb(vu, vv) } @@ -3358,11 +3371,11 @@ pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundhub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundhub(vu, vv) } @@ -3370,11 +3383,11 @@ pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundwh(vu, vv) } @@ -3382,11 +3395,11 @@ pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundwuh(vu, vv) } @@ -3394,11 +3407,11 @@ pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrsadubi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrsadubi(vuu, rt, iu1) } @@ -3406,11 +3419,11 @@ pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrsadubi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( +pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3423,11 +3436,11 @@ pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsathub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vsathub(vu, vv) } @@ -3435,11 +3448,11 @@ pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsatwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatwh(vu, vv) } @@ -3447,11 +3460,11 @@ pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair { vsb(vu) } @@ -3459,11 +3472,11 @@ pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair { vsh(vu) } @@ -3471,11 +3484,11 @@ pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vshufeh(vu, vv) } @@ -3483,11 +3496,11 @@ pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector { vshuffb(vu) } @@ -3495,11 +3508,11 @@ pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vshuffeb(vu, vv) } @@ -3507,11 +3520,11 @@ pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector { vshuffh(vu) } @@ -3519,11 +3532,11 @@ pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vshuffob(vu, vv) } @@ -3531,11 +3544,11 @@ pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffvdd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vshuffvdd(vu, vv, rt) } @@ -3543,11 +3556,11 @@ pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vshufoeb(vu, vv) } @@ -3555,11 +3568,11 @@ pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vshufoeh(vu, vv) } @@ -3567,11 +3580,11 @@ pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vshufoh(vu, vv) } @@ -3579,11 +3592,11 @@ pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubb(vu, vv) } @@ -3591,11 +3604,11 @@ pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubb_dv(vuu, vvv) } @@ -3603,11 +3616,11 @@ pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubh(vu, vv) } @@ -3615,11 +3628,11 @@ pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubh_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubh_dv(vuu, vvv) } @@ -3627,11 +3640,11 @@ pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubhsat(vu, vv) } @@ -3639,11 +3652,11 @@ pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubhsat_dv(vuu, vvv) } @@ -3651,11 +3664,11 @@ pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsubhw(vu, vv) } @@ -3663,11 +3676,11 @@ pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsububh(vu, vv) } @@ -3675,11 +3688,11 @@ pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsububsat(vu, vv) } @@ -3687,11 +3700,11 @@ pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsububsat_dv(vuu, vvv) } @@ -3699,11 +3712,11 @@ pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubuhsat(vu, vv) } @@ -3711,11 +3724,11 @@ pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubuhsat_dv(vuu, vvv) } @@ -3723,11 +3736,11 @@ pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsubuhw(vu, vv) } @@ -3735,11 +3748,11 @@ pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_sub(vu, vv) } @@ -3747,11 +3760,11 @@ pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubw_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubw_dv(vuu, vvv) } @@ -3759,11 +3772,11 @@ pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubwsat(vu, vv) } @@ -3771,11 +3784,11 @@ pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubwsat_dv(vuu, vvv) } @@ -3783,11 +3796,11 @@ pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpyb(vuu, rt) } @@ -3795,11 +3808,11 @@ pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpyacc_whwbrb( +pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3811,11 +3824,11 @@ pub unsafe fn q6_wh_vtmpyacc_whwbrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpybus(vuu, rt) } @@ -3823,11 +3836,11 @@ pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpyacc_whwubrb( +pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3839,11 +3852,11 @@ pub unsafe fn q6_wh_vtmpyacc_whwubrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpyhb(vuu, rt) } @@ -3851,11 +3864,11 @@ pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vtmpyacc_wwwhrb( +pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3867,11 +3880,11 @@ pub unsafe fn q6_ww_vtmpyacc_wwwhrb( /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair { vunpackb(vu) } @@ -3879,11 +3892,11 @@ pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair { vunpackh(vu) } @@ -3891,11 +3904,11 @@ pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { vunpackob(vxx, vu) } @@ -3903,11 +3916,11 @@ pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { vunpackoh(vxx, vu) } @@ -3915,11 +3928,11 @@ pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair { vunpackub(vu) } @@ -3927,11 +3940,11 @@ pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair { vunpackuh(vu) } @@ -3939,11 +3952,11 @@ pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vxor))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_xor(vu, vv) } @@ -3951,11 +3964,11 @@ pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vzb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair { vzb(vu) } @@ -3963,11 +3976,11 @@ pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vzh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair { vzh(vu) } @@ -3975,11 +3988,11 @@ pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(lvsplatb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector { lvsplatb(rt) } @@ -3987,11 +4000,11 @@ pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(lvsplath))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector { lvsplath(rt) } @@ -3999,11 +4012,11 @@ pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddbsat(vu, vv) } @@ -4011,11 +4024,11 @@ pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddbsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddbsat_dv(vuu, vvv) } @@ -4023,11 +4036,11 @@ pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddclbh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddclbh(vu, vv) } @@ -4035,11 +4048,11 @@ pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddclbw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddclbw(vu, vv) } @@ -4047,11 +4060,11 @@ pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddhw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vaddacc_wwvhvh( +pub unsafe fn Q6_Ww_vaddacc_WwVhVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4063,11 +4076,11 @@ pub unsafe fn q6_ww_vaddacc_wwvhvh( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddubh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vaddacc_whvubvub( +pub unsafe fn Q6_Wh_vaddacc_WhVubVub( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4079,11 +4092,11 @@ pub unsafe fn q6_wh_vaddacc_whvubvub( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddububb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddububb_sat(vu, vv) } @@ -4091,11 +4104,11 @@ pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduhw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vaddacc_wwvuhvuh( +pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4107,11 +4120,11 @@ pub unsafe fn q6_ww_vaddacc_wwvuhvuh( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vadduwsat(vu, vv) } @@ -4119,11 +4132,11 @@ pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vadduwsat_dv(vuu, vvv) } @@ -4131,11 +4144,11 @@ pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasrhbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhbsat(vu, vv, rt) } @@ -4143,11 +4156,11 @@ pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasruwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruwuhrndsat(vu, vv, rt) } @@ -4155,11 +4168,11 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasrwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwuhrndsat(vu, vv, rt) } @@ -4167,11 +4180,11 @@ pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlsrb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector { vlsrb(vu, rt) } @@ -4179,11 +4192,11 @@ pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvb_nm))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlutvvb_nm(vu, vv, rt) } @@ -4191,11 +4204,11 @@ pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvb_oracci))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32or_vbvbvbi( +pub unsafe fn Q6_Vb_vlut32or_VbVbVbI( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -4208,11 +4221,11 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbi( /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { vlutvvbi(vu, vv, iu3) } @@ -4220,11 +4233,11 @@ pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwh_nm))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vlutvwh_nm(vu, vv, rt) } @@ -4232,11 +4245,11 @@ pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwh_oracci))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16or_whvbvhi( +pub unsafe fn Q6_Wh_vlut16or_WhVbVhI( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4249,11 +4262,11 @@ pub unsafe fn q6_wh_vlut16or_whvbvhi( /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwhi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { vlutvwhi(vu, vv, iu3) } @@ -4261,11 +4274,11 @@ pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmaxb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxb(vu, vv) } @@ -4273,11 +4286,11 @@ pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vminb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vminb(vu, vv) } @@ -4285,11 +4298,11 @@ pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpauhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpauhb(vuu, rt) } @@ -4297,11 +4310,11 @@ pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpauhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpaacc_wwwuhrb( +pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -4313,11 +4326,11 @@ pub unsafe fn q6_ww_vmpaacc_wwwuhrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyewuh_64))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyewuh_64(vu, vv) } @@ -4325,11 +4338,11 @@ pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyiwub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwub(vu, rt) } @@ -4337,11 +4350,11 @@ pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyiwub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwub_acc(vx, vu, rt) } @@ -4349,11 +4362,11 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> H /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyowh_64_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vmpyoacc_wvwvh( +pub unsafe fn Q6_W_vmpyoacc_WVwVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4365,11 +4378,11 @@ pub unsafe fn q6_w_vmpyoacc_wvwvh( /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vrounduhub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vrounduhub(vu, vv) } @@ -4377,11 +4390,11 @@ pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vrounduwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vrounduwuh(vu, vv) } @@ -4389,11 +4402,11 @@ pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsatuwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatuwuh(vu, vv) } @@ -4401,11 +4414,11 @@ pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubbsat(vu, vv) } @@ -4413,11 +4426,11 @@ pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubbsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubbsat_dv(vuu, vvv) } @@ -4425,11 +4438,11 @@ pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubububb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubububb_sat(vu, vv) } @@ -4437,11 +4450,11 @@ pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubuwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubuwsat(vu, vv) } @@ -4449,11 +4462,11 @@ pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubuwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubuwsat_dv(vuu, vvv) } @@ -4461,11 +4474,11 @@ pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vabsb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector { vabsb(vu) } @@ -4473,11 +4486,11 @@ pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vabsb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector { vabsb_sat(vu) } @@ -4485,11 +4498,11 @@ pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vaslh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vaslh_acc(vx, vu, rt) } @@ -4497,11 +4510,11 @@ pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasrh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vasrh_acc(vx, vu, rt) } @@ -4509,11 +4522,11 @@ pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruhubrndsat(vu, vv, rt) } @@ -4521,11 +4534,11 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruhubsat(vu, vv, rt) } @@ -4533,11 +4546,11 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruwuhsat(vu, vv, rt) } @@ -4545,11 +4558,11 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavgb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgb(vu, vv) } @@ -4557,11 +4570,11 @@ pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavgbrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgbrnd(vu, vv) } @@ -4569,11 +4582,11 @@ pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavguw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguw(vu, vv) } @@ -4581,11 +4594,11 @@ pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavguwrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguwrnd(vu, vv) } @@ -4593,11 +4606,11 @@ pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: MAPPING /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vdd0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vzero() -> HvxVectorPair { +pub unsafe fn Q6_W_vzero() -> HvxVectorPair { vdd0() } @@ -4605,11 +4618,11 @@ pub unsafe fn q6_w_vzero() -> HvxVectorPair { /// /// Instruction Type: CVI_GATHER /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { +pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { vgathermh(rs, rt, mu, vv) } @@ -4617,11 +4630,11 @@ pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect /// /// Instruction Type: CVI_GATHER_DV /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { +pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { vgathermhw(rs, rt, mu, vvv) } @@ -4629,11 +4642,11 @@ pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVec /// /// Instruction Type: CVI_GATHER /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { +pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { vgathermw(rs, rt, mu, vv) } @@ -4641,11 +4654,11 @@ pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpabuu))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpabuu(vuu, rt) } @@ -4653,11 +4666,11 @@ pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpabuu_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpaacc_whwubrub( +pub unsafe fn Q6_Wh_vmpaacc_WhWubRub( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -4669,11 +4682,11 @@ pub unsafe fn q6_wh_vmpaacc_whwubrub( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyh_acc(vxx, vu, rt) } @@ -4681,11 +4694,11 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyuhe))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector { vmpyuhe(vu, rt) } @@ -4693,11 +4706,11 @@ pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyuhe_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyuhe_acc(vx, vu, rt) } @@ -4705,11 +4718,11 @@ pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vnavgb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgb(vu, vv) } @@ -4717,11 +4730,11 @@ pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermh(rt, mu, vv, vw) } @@ -4729,11 +4742,11 @@ pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) /// /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermh_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermh_add(rt, mu, vv, vw) } @@ -4741,11 +4754,11 @@ pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto /// /// Instruction Type: CVI_SCATTER_DV /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { vscattermhw(rt, mu, vvv, vw) } @@ -4753,11 +4766,11 @@ pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVec /// /// Instruction Type: CVI_SCATTER_DV /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermhw_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { vscattermhw_add(rt, mu, vvv, vw) } @@ -4765,11 +4778,11 @@ pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: Hvx /// /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermw(rt, mu, vv, vw) } @@ -4777,11 +4790,11 @@ pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) /// /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermw_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermw_add(rt, mu, vv, vw) } @@ -4789,11 +4802,11 @@ pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vasr_into))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vasrinto_wwvwvw( +pub unsafe fn Q6_Ww_vasrinto_WwVwVw( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4805,11 +4818,11 @@ pub unsafe fn q6_ww_vasrinto_wwvwvw( /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vrotr))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vrotr(vu, vv) } @@ -4817,11 +4830,11 @@ pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vsatdw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatdw(vu, vv) } @@ -4829,11 +4842,11 @@ pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyhubs10))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpy_wubwbi_h( +pub unsafe fn Q6_Ww_v6mpy_WubWbI_h( vuu: HvxVectorPair, vvv: HvxVectorPair, iu2: i32, @@ -4845,11 +4858,11 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_h( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h( vxx: HvxVectorPair, vuu: HvxVectorPair, vvv: HvxVectorPair, @@ -4862,11 +4875,11 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyvubs10))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpy_wubwbi_v( +pub unsafe fn Q6_Ww_v6mpy_WubWbI_v( vuu: HvxVectorPair, vvv: HvxVectorPair, iu2: i32, @@ -4878,11 +4891,11 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_v( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v( vxx: HvxVectorPair, vuu: HvxVectorPair, vvv: HvxVectorPair, @@ -4895,11 +4908,11 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vabs_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector { vabs_hf(vu) } @@ -4907,11 +4920,11 @@ pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vabs_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector { vabs_sf(vu) } @@ -4919,11 +4932,11 @@ pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_hf(vu, vv) } @@ -4931,11 +4944,11 @@ pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_hf_hf(vu, vv) } @@ -4943,11 +4956,11 @@ pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf16(vu, vv) } @@ -4955,11 +4968,11 @@ pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf16_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf16_mix(vu, vv) } @@ -4967,11 +4980,11 @@ pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf32(vu, vv) } @@ -4979,11 +4992,11 @@ pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf32_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf32_mix(vu, vv) } @@ -4991,11 +5004,11 @@ pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_sf(vu, vv) } @@ -5003,11 +5016,11 @@ pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vadd_sf_hf(vu, vv) } @@ -5015,11 +5028,11 @@ pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_sf_sf(vu, vv) } @@ -5027,11 +5040,11 @@ pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vassign_fp))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector { vassign_fp(vu) } @@ -5039,11 +5052,11 @@ pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_hf_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector { vconv_hf_qf16(vu) } @@ -5051,11 +5064,11 @@ pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_hf_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector { vconv_hf_qf32(vuu) } @@ -5063,11 +5076,11 @@ pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_sf_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector { vconv_sf_qf32(vu) } @@ -5075,11 +5088,11 @@ pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_b_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_b_hf(vu, vv) } @@ -5087,11 +5100,11 @@ pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_h_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector { vcvt_h_hf(vu) } @@ -5099,11 +5112,11 @@ pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_b))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair { vcvt_hf_b(vu) } @@ -5111,11 +5124,11 @@ pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector { vcvt_hf_h(vu) } @@ -5123,11 +5136,11 @@ pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_hf_sf(vu, vv) } @@ -5135,11 +5148,11 @@ pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_ub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair { vcvt_hf_ub(vu) } @@ -5147,11 +5160,11 @@ pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_uh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector { vcvt_hf_uh(vu) } @@ -5159,11 +5172,11 @@ pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair { vcvt_sf_hf(vu) } @@ -5171,11 +5184,11 @@ pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_ub_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_ub_hf(vu, vv) } @@ -5183,11 +5196,11 @@ pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_uh_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector { vcvt_uh_hf(vu) } @@ -5195,11 +5208,11 @@ pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vdmpy_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpy_sf_hf(vu, vv) } @@ -5207,11 +5220,11 @@ pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpy_sf_hf_acc(vx, vu, vv) } @@ -5219,11 +5232,11 @@ pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVec /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmax_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_hf(vu, vv) } @@ -5231,11 +5244,11 @@ pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmax_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_sf(vu, vv) } @@ -5243,11 +5256,11 @@ pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmin_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_hf(vu, vv) } @@ -5255,11 +5268,11 @@ pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmin_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_sf(vu, vv) } @@ -5267,11 +5280,11 @@ pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfneg_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector { vfneg_hf(vu) } @@ -5279,11 +5292,11 @@ pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfneg_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector { vfneg_sf(vu) } @@ -5291,11 +5304,11 @@ pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmax_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmax_hf(vu, vv) } @@ -5303,11 +5316,11 @@ pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmax_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmax_sf(vu, vv) } @@ -5315,11 +5328,11 @@ pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmin_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmin_hf(vu, vv) } @@ -5327,11 +5340,11 @@ pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmin_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmin_sf(vu, vv) } @@ -5339,11 +5352,11 @@ pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_hf_hf(vu, vv) } @@ -5351,11 +5364,11 @@ pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_hf_hf_acc(vx, vu, vv) } @@ -5363,11 +5376,11 @@ pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVect /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16(vu, vv) } @@ -5375,11 +5388,11 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16_hf(vu, vv) } @@ -5387,11 +5400,11 @@ pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16_mix_hf(vu, vv) } @@ -5399,11 +5412,11 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf32(vu, vv) } @@ -5411,11 +5424,11 @@ pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_hf(vu, vv) } @@ -5423,11 +5436,11 @@ pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPai /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_mix_hf(vu, vv) } @@ -5435,11 +5448,11 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorP /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_qf16(vu, vv) } @@ -5447,11 +5460,11 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf32_sf(vu, vv) } @@ -5459,11 +5472,11 @@ pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_sf_hf(vu, vv) } @@ -5471,11 +5484,11 @@ pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( +pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -5487,11 +5500,11 @@ pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_sf_sf(vu, vv) } @@ -5499,11 +5512,11 @@ pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_hf(vu, vv) } @@ -5511,11 +5524,11 @@ pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_hf_hf(vu, vv) } @@ -5523,11 +5536,11 @@ pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf16(vu, vv) } @@ -5535,11 +5548,11 @@ pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf16_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf16_mix(vu, vv) } @@ -5547,11 +5560,11 @@ pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf32(vu, vv) } @@ -5559,11 +5572,11 @@ pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf32_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf32_mix(vu, vv) } @@ -5571,11 +5584,11 @@ pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_sf(vu, vv) } @@ -5583,11 +5596,11 @@ pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsub_sf_hf(vu, vv) } @@ -5595,11 +5608,11 @@ pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_sf_sf(vu, vv) } @@ -5607,11 +5620,11 @@ pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvuhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvuhubrndsat(vuu, vv) } @@ -5619,11 +5632,11 @@ pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> H /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvuhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvuhubsat(vuu, vv) } @@ -5631,11 +5644,11 @@ pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVe /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvwuhrndsat(vuu, vv) } @@ -5643,11 +5656,11 @@ pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> Hv /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvwuhsat(vuu, vv) } @@ -5655,11 +5668,11 @@ pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVec /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vmpyuhvs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyuhvs(vu, vv) } @@ -5667,11 +5680,11 @@ pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_h_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector { vconv_h_hf(vu) } @@ -5679,11 +5692,11 @@ pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_hf_h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector { vconv_hf_h(vu) } @@ -5691,11 +5704,11 @@ pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_sf_w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector { vconv_sf_w(vu) } @@ -5703,11 +5716,11 @@ pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_w_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector { vconv_w_sf(vu) } @@ -5715,11 +5728,11 @@ pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(get_qfext))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { get_qfext(vu, rt) } @@ -5727,11 +5740,11 @@ pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(set_qfext))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { set_qfext(vu, rt) } @@ -5739,11 +5752,11 @@ pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vabs_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector { vabs_f8(vu) } @@ -5751,11 +5764,11 @@ pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt2_hf_b))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair { vcvt2_hf_b(vu) } @@ -5763,11 +5776,11 @@ pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt2_hf_ub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair { vcvt2_hf_ub(vu) } @@ -5775,11 +5788,11 @@ pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt_hf_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair { vcvt_hf_f8(vu) } @@ -5787,11 +5800,11 @@ pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfmax_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_f8(vu, vv) } @@ -5799,11 +5812,11 @@ pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfmin_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_f8(vu, vv) } @@ -5811,11 +5824,11 @@ pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfneg_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector { vfneg_f8(vu) } @@ -5824,10 +5837,10 @@ pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_and( vandvrt(core::mem::transmute::(qs), -1), @@ -5842,10 +5855,10 @@ pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_and_n( vandvrt(core::mem::transmute::(qs), -1), @@ -5860,10 +5873,10 @@ pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPre /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_not(vandvrt( core::mem::transmute::(qs), @@ -5878,10 +5891,10 @@ pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_or( vandvrt(core::mem::transmute::(qs), -1), @@ -5896,10 +5909,10 @@ pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_or_n( vandvrt(core::mem::transmute::(qs), -1), @@ -5914,10 +5927,10 @@ pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) } @@ -5926,10 +5939,10 @@ pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_xor( vandvrt(core::mem::transmute::(qs), -1), @@ -5944,10 +5957,10 @@ pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VM_ST /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nqpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5960,10 +5973,10 @@ pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VM_ST /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nt_nqpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5976,10 +5989,10 @@ pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVec /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VM_ST /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nt_qpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5992,10 +6005,10 @@ pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VM_ST /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_qpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -6008,10 +6021,10 @@ pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddbnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6024,10 +6037,10 @@ pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddbq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6040,10 +6053,10 @@ pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddhnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6056,10 +6069,10 @@ pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddhq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6072,10 +6085,10 @@ pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddwnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6088,10 +6101,10 @@ pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddwq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6104,10 +6117,10 @@ pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector { vandvrt(core::mem::transmute::(qu), rt) } @@ -6116,10 +6129,10 @@ pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { vandvrt_acc(vx, core::mem::transmute::(qu), rt) } @@ -6128,10 +6141,10 @@ pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxV /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(vu, rt)) } @@ -6140,10 +6153,10 @@ pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt_acc( core::mem::transmute::(qx), vu, @@ -6156,10 +6169,10 @@ pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxV /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) } @@ -6168,10 +6181,10 @@ pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqand_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6191,10 +6204,10 @@ pub unsafe fn q6_q_vcmp_eqand_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqor_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6214,10 +6227,10 @@ pub unsafe fn q6_q_vcmp_eqor_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6237,10 +6250,10 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) } @@ -6249,10 +6262,10 @@ pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqand_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6272,10 +6285,10 @@ pub unsafe fn q6_q_vcmp_eqand_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqor_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6295,10 +6308,10 @@ pub unsafe fn q6_q_vcmp_eqor_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6318,10 +6331,10 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) } @@ -6330,10 +6343,10 @@ pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqand_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6353,10 +6366,10 @@ pub unsafe fn q6_q_vcmp_eqand_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqor_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6376,10 +6389,10 @@ pub unsafe fn q6_q_vcmp_eqor_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6399,10 +6412,10 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) } @@ -6411,10 +6424,10 @@ pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtand_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6434,10 +6447,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtor_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6457,10 +6470,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6480,10 +6493,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) } @@ -6492,10 +6505,10 @@ pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtand_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6515,10 +6528,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtor_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6538,10 +6551,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6561,10 +6574,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) } @@ -6573,10 +6586,10 @@ pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtand_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6596,10 +6609,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvubvub( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtor_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6619,10 +6632,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvubvub( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6642,10 +6655,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) } @@ -6654,10 +6667,10 @@ pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6677,10 +6690,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6700,10 +6713,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6723,10 +6736,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) } @@ -6735,10 +6748,10 @@ pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6758,10 +6771,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6781,10 +6794,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6804,10 +6817,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) } @@ -6816,10 +6829,10 @@ pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtand_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6839,10 +6852,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtor_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6862,10 +6875,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6885,10 +6898,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { vmux( vandvrt(core::mem::transmute::(qt), -1), vu, @@ -6901,10 +6914,10 @@ pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubbnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6917,10 +6930,10 @@ pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubbq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6933,10 +6946,10 @@ pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubhnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6949,10 +6962,10 @@ pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubhq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6965,10 +6978,10 @@ pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubwnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6981,10 +6994,10 @@ pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubwq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6997,10 +7010,10 @@ pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vswap( vandvrt(core::mem::transmute::(qt), -1), vu, @@ -7013,10 +7026,10 @@ pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) } @@ -7025,10 +7038,10 @@ pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( shuffeqh( vandvrt(core::mem::transmute::(qs), -1), @@ -7043,10 +7056,10 @@ pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( shuffeqw( vandvrt(core::mem::transmute::(qs), -1), @@ -7061,10 +7074,10 @@ pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector { vandnqrt( vandvrt(core::mem::transmute::(qu), -1), rt, @@ -7076,10 +7089,10 @@ pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { vandnqrt_acc( vx, vandvrt(core::mem::transmute::(qu), -1), @@ -7092,10 +7105,10 @@ pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> Hvx /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { vandvnqv( vandvrt(core::mem::transmute::(qv), -1), vu, @@ -7107,10 +7120,10 @@ pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { vandvqv( vandvrt(core::mem::transmute::(qv), -1), vu, @@ -7122,10 +7135,10 @@ pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_GATHER /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmvh( +pub unsafe fn Q6_vgather_AQRMVh( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7146,10 +7159,10 @@ pub unsafe fn q6_vgather_aqrmvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_GATHER_DV /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmww( +pub unsafe fn Q6_vgather_AQRMWw( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7170,10 +7183,10 @@ pub unsafe fn q6_vgather_aqrmww( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_GATHER /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmvw( +pub unsafe fn Q6_vgather_AQRMVw( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7194,10 +7207,10 @@ pub unsafe fn q6_vgather_aqrmvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqb(vandvrt( core::mem::transmute::(qv), -1, @@ -7209,10 +7222,10 @@ pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqh(vandvrt( core::mem::transmute::(qv), -1, @@ -7224,10 +7237,10 @@ pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqw(vandvrt( core::mem::transmute::(qv), -1, @@ -7239,10 +7252,10 @@ pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmvhv( +pub unsafe fn Q6_vscatter_QRMVhV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7263,10 +7276,10 @@ pub unsafe fn q6_vscatter_qrmvhv( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_SCATTER_DV /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmwwv( +pub unsafe fn Q6_vscatter_QRMWwV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7287,10 +7300,10 @@ pub unsafe fn q6_vscatter_qrmwwv( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmvwv( +pub unsafe fn Q6_vscatter_QRMVwV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7311,10 +7324,10 @@ pub unsafe fn q6_vscatter_qrmvwv( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( +pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat( vu: HvxVector, vv: HvxVector, qs: HvxVectorPred, @@ -7331,10 +7344,10 @@ pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) } @@ -7343,10 +7356,10 @@ pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7366,10 +7379,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7389,10 +7402,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7412,10 +7425,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) } @@ -7424,10 +7437,10 @@ pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7447,10 +7460,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7470,10 +7483,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, diff --git a/stdarch/crates/core_arch/src/hexagon/v64.rs b/stdarch/crates/core_arch/src/hexagon/v64.rs index 023a8711d21f3..e9b18b2fd8efe 100644 --- a/stdarch/crates/core_arch/src/hexagon/v64.rs +++ b/stdarch/crates/core_arch/src/hexagon/v64.rs @@ -15,6 +15,18 @@ //! //! To use this module, compile with `-C target-feature=+hvx-length64b`. //! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! //! ## Architecture Versions //! //! Different intrinsics require different HVX architecture versions. Use the @@ -31,6 +43,7 @@ //! Each version includes all features from previous versions. #![allow(non_camel_case_types)] +#![allow(non_snake_case)] #[cfg(test)] use stdarch_test::assert_instr; @@ -1030,11 +1043,11 @@ unsafe extern "unadjusted" { /// /// Instruction Type: LD /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(extractw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { +pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 { extractw(vu, rs) } @@ -1042,11 +1055,11 @@ pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(hi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector { hi(vss) } @@ -1054,11 +1067,11 @@ pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(lo))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector { lo(vss) } @@ -1066,11 +1079,11 @@ pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(lvsplatw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector { lvsplatw(rt) } @@ -1078,11 +1091,11 @@ pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffh(vu, vv) } @@ -1090,11 +1103,11 @@ pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffub(vu, vv) } @@ -1102,11 +1115,11 @@ pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffuh(vu, vv) } @@ -1114,11 +1127,11 @@ pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffw(vu, vv) } @@ -1126,11 +1139,11 @@ pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector { vabsh(vu) } @@ -1138,11 +1151,11 @@ pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector { vabsh_sat(vu) } @@ -1150,11 +1163,11 @@ pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector { vabsw(vu) } @@ -1162,11 +1175,11 @@ pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsw_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector { vabsw_sat(vu) } @@ -1174,11 +1187,11 @@ pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddb(vu, vv) } @@ -1186,11 +1199,11 @@ pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddb_dv(vuu, vvv) } @@ -1198,11 +1211,11 @@ pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddh(vu, vv) } @@ -1210,11 +1223,11 @@ pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddh_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddh_dv(vuu, vvv) } @@ -1222,11 +1235,11 @@ pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddhsat(vu, vv) } @@ -1234,11 +1247,11 @@ pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddhsat_dv(vuu, vvv) } @@ -1246,11 +1259,11 @@ pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vaddhw(vu, vv) } @@ -1258,11 +1271,11 @@ pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vaddubh(vu, vv) } @@ -1270,11 +1283,11 @@ pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddubsat(vu, vv) } @@ -1282,11 +1295,11 @@ pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddubsat_dv(vuu, vvv) } @@ -1294,11 +1307,11 @@ pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vadduhsat(vu, vv) } @@ -1306,11 +1319,11 @@ pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vadduhsat_dv(vuu, vvv) } @@ -1318,11 +1331,11 @@ pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vadduhw(vu, vv) } @@ -1330,11 +1343,11 @@ pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_add(vu, vv) } @@ -1342,11 +1355,11 @@ pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddw_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddw_dv(vuu, vvv) } @@ -1354,11 +1367,11 @@ pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddwsat(vu, vv) } @@ -1366,11 +1379,11 @@ pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddwsat_dv(vuu, vvv) } @@ -1378,11 +1391,11 @@ pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(valignb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { valignb(vu, vv, rt) } @@ -1390,11 +1403,11 @@ pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(valignbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { valignbi(vu, vv, iu3) } @@ -1402,11 +1415,11 @@ pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vand))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_and(vu, vv) } @@ -1414,11 +1427,11 @@ pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector { vaslh(vu, rt) } @@ -1426,11 +1439,11 @@ pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaslhv(vu, vv) } @@ -1438,11 +1451,11 @@ pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector { vaslw(vu, rt) } @@ -1450,11 +1463,11 @@ pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vaslw_acc(vx, vu, rt) } @@ -1462,11 +1475,11 @@ pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vaslwv(vu, vv) } @@ -1474,11 +1487,11 @@ pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector { vasrh(vu, rt) } @@ -1486,11 +1499,11 @@ pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhbrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhbrndsat(vu, vv, rt) } @@ -1498,11 +1511,11 @@ pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhubrndsat(vu, vv, rt) } @@ -1510,11 +1523,11 @@ pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhubsat(vu, vv, rt) } @@ -1522,11 +1535,11 @@ pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vasrhv(vu, vv) } @@ -1534,11 +1547,11 @@ pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector { vasrw(vu, rt) } @@ -1546,11 +1559,11 @@ pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vasrw_acc(vx, vu, rt) } @@ -1558,11 +1571,11 @@ pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwh(vu, vv, rt) } @@ -1570,11 +1583,11 @@ pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwhrndsat(vu, vv, rt) } @@ -1582,11 +1595,11 @@ pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwhsat(vu, vv, rt) } @@ -1594,11 +1607,11 @@ pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwuhsat(vu, vv, rt) } @@ -1606,11 +1619,11 @@ pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vasrwv(vu, vv) } @@ -1618,11 +1631,11 @@ pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vassign))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector { vassign(vu) } @@ -1630,11 +1643,11 @@ pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vassignp))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair { vassignp(vuu) } @@ -1642,11 +1655,11 @@ pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgh(vu, vv) } @@ -1654,11 +1667,11 @@ pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavghrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavghrnd(vu, vv) } @@ -1666,11 +1679,11 @@ pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgub(vu, vv) } @@ -1678,11 +1691,11 @@ pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgubrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgubrnd(vu, vv) } @@ -1690,11 +1703,11 @@ pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavguh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguh(vu, vv) } @@ -1702,11 +1715,11 @@ pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavguhrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguhrnd(vu, vv) } @@ -1714,11 +1727,11 @@ pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgw(vu, vv) } @@ -1726,11 +1739,11 @@ pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgwrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgwrnd(vu, vv) } @@ -1738,11 +1751,11 @@ pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcl0h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector { vcl0h(vu) } @@ -1750,11 +1763,11 @@ pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcl0w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector { vcl0w(vu) } @@ -1762,11 +1775,11 @@ pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcombine))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vcombine(vu, vv) } @@ -1774,11 +1787,11 @@ pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vd0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vzero() -> HvxVector { +pub unsafe fn Q6_V_vzero() -> HvxVector { vd0() } @@ -1786,11 +1799,11 @@ pub unsafe fn q6_v_vzero() -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector { vdealb(vu) } @@ -1798,11 +1811,11 @@ pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealb4w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vdealb4w(vu, vv) } @@ -1810,11 +1823,11 @@ pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector { vdealh(vu) } @@ -1822,11 +1835,11 @@ pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealvdd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vdealvdd(vu, vv, rt) } @@ -1834,11 +1847,11 @@ pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdelta))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vdelta(vu, vv) } @@ -1846,11 +1859,11 @@ pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { vdmpybus(vu, rt) } @@ -1858,11 +1871,11 @@ pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpybus_acc(vx, vu, rt) } @@ -1870,11 +1883,11 @@ pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdmpybus_dv(vuu, rt) } @@ -1882,11 +1895,11 @@ pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vdmpyacc_whwubrb( +pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -1898,11 +1911,11 @@ pub unsafe fn q6_wh_vdmpyacc_whwubrb( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhb(vu, rt) } @@ -1910,11 +1923,11 @@ pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhb_acc(vx, vu, rt) } @@ -1922,11 +1935,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdmpyhb_dv(vuu, rt) } @@ -1934,11 +1947,11 @@ pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vdmpyacc_wwwhrb( +pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -1950,11 +1963,11 @@ pub unsafe fn q6_ww_vdmpyacc_wwwhrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhisat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhisat(vuu, rt) } @@ -1962,11 +1975,11 @@ pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhisat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhisat_acc(vx, vuu, rt) } @@ -1974,11 +1987,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsat(vu, rt) } @@ -1986,11 +1999,11 @@ pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsat_acc(vx, vu, rt) } @@ -1998,11 +2011,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsuisat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhsuisat(vuu, rt) } @@ -2010,11 +2023,11 @@ pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhsuisat_acc(vx, vuu, rt) } @@ -2022,11 +2035,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsusat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsusat(vu, rt) } @@ -2034,11 +2047,11 @@ pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsusat_acc(vx, vu, rt) } @@ -2046,11 +2059,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhvsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpyhvsat(vu, vv) } @@ -2058,11 +2071,11 @@ pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpyhvsat_acc(vx, vu, vv) } @@ -2070,11 +2083,11 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVec /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdsaduh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdsaduh(vuu, rt) } @@ -2082,11 +2095,11 @@ pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdsaduh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( +pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2098,11 +2111,11 @@ pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vinsertwr))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector { vinsertwr(vx, rt) } @@ -2110,11 +2123,11 @@ pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlalignb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlalignb(vu, vv, rt) } @@ -2122,11 +2135,11 @@ pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlalignbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { vlalignbi(vu, vv, iu3) } @@ -2134,11 +2147,11 @@ pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVec /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector { vlsrh(vu, rt) } @@ -2146,11 +2159,11 @@ pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vlsrhv(vu, vv) } @@ -2158,11 +2171,11 @@ pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector { vlsrw(vu, rt) } @@ -2170,11 +2183,11 @@ pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vlsrwv(vu, vv) } @@ -2182,11 +2195,11 @@ pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvvb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlutvvb(vu, vv, rt) } @@ -2194,11 +2207,11 @@ pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvvb_oracc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32or_vbvbvbr( +pub unsafe fn Q6_Vb_vlut32or_VbVbVbR( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2211,11 +2224,11 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbr( /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vlutvwh(vu, vv, rt) } @@ -2223,11 +2236,11 @@ pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvwh_oracc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16or_whvbvhr( +pub unsafe fn Q6_Wh_vlut16or_WhVbVhR( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2240,11 +2253,11 @@ pub unsafe fn q6_wh_vlut16or_whvbvhr( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxh(vu, vv) } @@ -2252,11 +2265,11 @@ pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxub(vu, vv) } @@ -2264,11 +2277,11 @@ pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxuh(vu, vv) } @@ -2276,11 +2289,11 @@ pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxw(vu, vv) } @@ -2288,11 +2301,11 @@ pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vminh(vu, vv) } @@ -2300,11 +2313,11 @@ pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vminub(vu, vv) } @@ -2312,11 +2325,11 @@ pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vminuh(vu, vv) } @@ -2324,11 +2337,11 @@ pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vminw(vu, vv) } @@ -2336,11 +2349,11 @@ pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpabus(vuu, rt) } @@ -2348,11 +2361,11 @@ pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpaacc_whwubrb( +pub unsafe fn Q6_Wh_vmpaacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2364,11 +2377,11 @@ pub unsafe fn q6_wh_vmpaacc_whwubrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vmpabusv(vuu, vvv) } @@ -2376,11 +2389,11 @@ pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVec /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabuuv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vmpabuuv(vuu, vvv) } @@ -2388,11 +2401,11 @@ pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVe /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpahb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpahb(vuu, rt) } @@ -2400,11 +2413,11 @@ pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpahb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpaacc_wwwhrb( +pub unsafe fn Q6_Ww_vmpaacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2416,11 +2429,11 @@ pub unsafe fn q6_ww_vmpaacc_wwwhrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpybus(vu, rt) } @@ -2428,11 +2441,11 @@ pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { vmpybus_acc(vxx, vu, rt) } @@ -2440,11 +2453,11 @@ pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpybusv(vu, vv) } @@ -2452,11 +2465,11 @@ pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybusv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvubvb( +pub unsafe fn Q6_Wh_vmpyacc_WhVubVb( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2468,11 +2481,11 @@ pub unsafe fn q6_wh_vmpyacc_whvubvb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpybv(vu, vv) } @@ -2480,11 +2493,11 @@ pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvbvb( +pub unsafe fn Q6_Wh_vmpyacc_WhVbVb( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2496,11 +2509,11 @@ pub unsafe fn q6_wh_vmpyacc_whvbvb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyewuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyewuh(vu, vv) } @@ -2508,11 +2521,11 @@ pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyh(vu, rt) } @@ -2520,11 +2533,11 @@ pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2536,11 +2549,11 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhsrs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { vmpyhsrs(vu, rt) } @@ -2548,11 +2561,11 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhss))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { vmpyhss(vu, rt) } @@ -2560,11 +2573,11 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyhus(vu, vv) } @@ -2572,11 +2585,11 @@ pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhvuh( +pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2588,11 +2601,11 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvuh( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyhv(vu, vv) } @@ -2600,11 +2613,11 @@ pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhvh( +pub unsafe fn Q6_Ww_vmpyacc_WwVhVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2616,11 +2629,11 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvh( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhvsrs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyhvsrs(vu, vv) } @@ -2628,11 +2641,11 @@ pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVec /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyieoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyieoh(vu, vv) } @@ -2640,11 +2653,11 @@ pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewh_acc(vx, vu, vv) } @@ -2652,11 +2665,11 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewuh(vu, vv) } @@ -2664,11 +2677,11 @@ pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewuh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewuh_acc(vx, vu, vv) } @@ -2676,11 +2689,11 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVecto /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyih))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyih(vu, vv) } @@ -2688,11 +2701,11 @@ pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyih_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyih_acc(vx, vu, vv) } @@ -2700,11 +2713,11 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyihb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector { vmpyihb(vu, rt) } @@ -2712,11 +2725,11 @@ pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyihb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyihb_acc(vx, vu, rt) } @@ -2724,11 +2737,11 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiowh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiowh(vu, vv) } @@ -2736,11 +2749,11 @@ pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwb(vu, rt) } @@ -2748,11 +2761,11 @@ pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwb_acc(vx, vu, rt) } @@ -2760,11 +2773,11 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwh(vu, rt) } @@ -2772,11 +2785,11 @@ pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwh_acc(vx, vu, rt) } @@ -2784,11 +2797,11 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyowh(vu, vv) } @@ -2796,11 +2809,11 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_rnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyowh_rnd(vu, vv) } @@ -2808,11 +2821,11 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVe /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2824,11 +2837,11 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_sacc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2840,11 +2853,11 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyub(vu, rt) } @@ -2852,11 +2865,11 @@ pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2868,11 +2881,11 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyubv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyubv(vu, vv) } @@ -2880,11 +2893,11 @@ pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyubv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2896,11 +2909,11 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyuh(vu, rt) } @@ -2908,11 +2921,11 @@ pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2924,11 +2937,11 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyuhv(vu, vv) } @@ -2936,11 +2949,11 @@ pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuhv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2952,11 +2965,11 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgh(vu, vv) } @@ -2964,11 +2977,11 @@ pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgub(vu, vv) } @@ -2976,11 +2989,11 @@ pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgw(vu, vv) } @@ -2988,11 +3001,11 @@ pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnormamth))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector { vnormamth(vu) } @@ -3000,11 +3013,11 @@ pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnormamtw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector { vnormamtw(vu) } @@ -3012,11 +3025,11 @@ pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnot))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector { vnot(vu) } @@ -3024,11 +3037,11 @@ pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vor))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_or(vu, vv) } @@ -3036,11 +3049,11 @@ pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackeb(vu, vv) } @@ -3048,11 +3061,11 @@ pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackeh(vu, vv) } @@ -3060,11 +3073,11 @@ pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackhb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackhb_sat(vu, vv) } @@ -3072,11 +3085,11 @@ pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackhub_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackhub_sat(vu, vv) } @@ -3084,11 +3097,11 @@ pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackob(vu, vv) } @@ -3096,11 +3109,11 @@ pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackoh(vu, vv) } @@ -3108,11 +3121,11 @@ pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackwh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackwh_sat(vu, vv) } @@ -3120,11 +3133,11 @@ pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackwuh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackwuh_sat(vu, vv) } @@ -3132,11 +3145,11 @@ pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpopcounth))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector { vpopcounth(vu) } @@ -3144,11 +3157,11 @@ pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrdelta))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vrdelta(vu, vv) } @@ -3156,11 +3169,11 @@ pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { vrmpybus(vu, rt) } @@ -3168,11 +3181,11 @@ pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vrmpybus_acc(vx, vu, rt) } @@ -3180,11 +3193,11 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrmpybusi(vuu, rt, iu1) } @@ -3192,11 +3205,11 @@ pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVe /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( +pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3209,11 +3222,11 @@ pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybusv(vu, vv) } @@ -3221,11 +3234,11 @@ pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybusv_acc(vx, vu, vv) } @@ -3233,11 +3246,11 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybv(vu, vv) } @@ -3245,11 +3258,11 @@ pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybv_acc(vx, vu, vv) } @@ -3257,11 +3270,11 @@ pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector { vrmpyub(vu, rt) } @@ -3269,11 +3282,11 @@ pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vrmpyub_acc(vx, vu, rt) } @@ -3281,11 +3294,11 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrmpyubi(vuu, rt, iu1) } @@ -3293,11 +3306,11 @@ pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( +pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3310,11 +3323,11 @@ pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpyubv(vu, vv) } @@ -3322,11 +3335,11 @@ pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpyubv_acc(vx, vu, vv) } @@ -3334,11 +3347,11 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVec /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vror))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector { vror(vu, rt) } @@ -3346,11 +3359,11 @@ pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundhb(vu, vv) } @@ -3358,11 +3371,11 @@ pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundhub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundhub(vu, vv) } @@ -3370,11 +3383,11 @@ pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundwh(vu, vv) } @@ -3382,11 +3395,11 @@ pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundwuh(vu, vv) } @@ -3394,11 +3407,11 @@ pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrsadubi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrsadubi(vuu, rt, iu1) } @@ -3406,11 +3419,11 @@ pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrsadubi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( +pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3423,11 +3436,11 @@ pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsathub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vsathub(vu, vv) } @@ -3435,11 +3448,11 @@ pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsatwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatwh(vu, vv) } @@ -3447,11 +3460,11 @@ pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair { vsb(vu) } @@ -3459,11 +3472,11 @@ pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair { vsh(vu) } @@ -3471,11 +3484,11 @@ pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vshufeh(vu, vv) } @@ -3483,11 +3496,11 @@ pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector { vshuffb(vu) } @@ -3495,11 +3508,11 @@ pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vshuffeb(vu, vv) } @@ -3507,11 +3520,11 @@ pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector { vshuffh(vu) } @@ -3519,11 +3532,11 @@ pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vshuffob(vu, vv) } @@ -3531,11 +3544,11 @@ pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffvdd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vshuffvdd(vu, vv, rt) } @@ -3543,11 +3556,11 @@ pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vshufoeb(vu, vv) } @@ -3555,11 +3568,11 @@ pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vshufoeh(vu, vv) } @@ -3567,11 +3580,11 @@ pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vshufoh(vu, vv) } @@ -3579,11 +3592,11 @@ pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubb(vu, vv) } @@ -3591,11 +3604,11 @@ pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubb_dv(vuu, vvv) } @@ -3603,11 +3616,11 @@ pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubh(vu, vv) } @@ -3615,11 +3628,11 @@ pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubh_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubh_dv(vuu, vvv) } @@ -3627,11 +3640,11 @@ pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubhsat(vu, vv) } @@ -3639,11 +3652,11 @@ pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubhsat_dv(vuu, vvv) } @@ -3651,11 +3664,11 @@ pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsubhw(vu, vv) } @@ -3663,11 +3676,11 @@ pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsububh(vu, vv) } @@ -3675,11 +3688,11 @@ pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsububsat(vu, vv) } @@ -3687,11 +3700,11 @@ pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsububsat_dv(vuu, vvv) } @@ -3699,11 +3712,11 @@ pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubuhsat(vu, vv) } @@ -3711,11 +3724,11 @@ pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubuhsat_dv(vuu, vvv) } @@ -3723,11 +3736,11 @@ pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsubuhw(vu, vv) } @@ -3735,11 +3748,11 @@ pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_sub(vu, vv) } @@ -3747,11 +3760,11 @@ pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubw_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubw_dv(vuu, vvv) } @@ -3759,11 +3772,11 @@ pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubwsat(vu, vv) } @@ -3771,11 +3784,11 @@ pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubwsat_dv(vuu, vvv) } @@ -3783,11 +3796,11 @@ pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpyb(vuu, rt) } @@ -3795,11 +3808,11 @@ pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpyacc_whwbrb( +pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3811,11 +3824,11 @@ pub unsafe fn q6_wh_vtmpyacc_whwbrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpybus(vuu, rt) } @@ -3823,11 +3836,11 @@ pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpyacc_whwubrb( +pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3839,11 +3852,11 @@ pub unsafe fn q6_wh_vtmpyacc_whwubrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpyhb(vuu, rt) } @@ -3851,11 +3864,11 @@ pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vtmpyacc_wwwhrb( +pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3867,11 +3880,11 @@ pub unsafe fn q6_ww_vtmpyacc_wwwhrb( /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair { vunpackb(vu) } @@ -3879,11 +3892,11 @@ pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair { vunpackh(vu) } @@ -3891,11 +3904,11 @@ pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { vunpackob(vxx, vu) } @@ -3903,11 +3916,11 @@ pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { vunpackoh(vxx, vu) } @@ -3915,11 +3928,11 @@ pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair { vunpackub(vu) } @@ -3927,11 +3940,11 @@ pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair { vunpackuh(vu) } @@ -3939,11 +3952,11 @@ pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vxor))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_xor(vu, vv) } @@ -3951,11 +3964,11 @@ pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vzb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair { vzb(vu) } @@ -3963,11 +3976,11 @@ pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vzh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair { vzh(vu) } @@ -3975,11 +3988,11 @@ pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(lvsplatb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector { lvsplatb(rt) } @@ -3987,11 +4000,11 @@ pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(lvsplath))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector { lvsplath(rt) } @@ -3999,11 +4012,11 @@ pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddbsat(vu, vv) } @@ -4011,11 +4024,11 @@ pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddbsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddbsat_dv(vuu, vvv) } @@ -4023,11 +4036,11 @@ pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddclbh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddclbh(vu, vv) } @@ -4035,11 +4048,11 @@ pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddclbw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddclbw(vu, vv) } @@ -4047,11 +4060,11 @@ pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddhw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vaddacc_wwvhvh( +pub unsafe fn Q6_Ww_vaddacc_WwVhVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4063,11 +4076,11 @@ pub unsafe fn q6_ww_vaddacc_wwvhvh( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddubh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vaddacc_whvubvub( +pub unsafe fn Q6_Wh_vaddacc_WhVubVub( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4079,11 +4092,11 @@ pub unsafe fn q6_wh_vaddacc_whvubvub( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddububb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddububb_sat(vu, vv) } @@ -4091,11 +4104,11 @@ pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduhw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vaddacc_wwvuhvuh( +pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4107,11 +4120,11 @@ pub unsafe fn q6_ww_vaddacc_wwvuhvuh( /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vadduwsat(vu, vv) } @@ -4119,11 +4132,11 @@ pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vadduwsat_dv(vuu, vvv) } @@ -4131,11 +4144,11 @@ pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasrhbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhbsat(vu, vv, rt) } @@ -4143,11 +4156,11 @@ pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasruwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruwuhrndsat(vu, vv, rt) } @@ -4155,11 +4168,11 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasrwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwuhrndsat(vu, vv, rt) } @@ -4167,11 +4180,11 @@ pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlsrb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector { vlsrb(vu, rt) } @@ -4179,11 +4192,11 @@ pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvb_nm))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlutvvb_nm(vu, vv, rt) } @@ -4191,11 +4204,11 @@ pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvb_oracci))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32or_vbvbvbi( +pub unsafe fn Q6_Vb_vlut32or_VbVbVbI( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -4208,11 +4221,11 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbi( /// /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { vlutvvbi(vu, vv, iu3) } @@ -4220,11 +4233,11 @@ pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwh_nm))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vlutvwh_nm(vu, vv, rt) } @@ -4232,11 +4245,11 @@ pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwh_oracci))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16or_whvbvhi( +pub unsafe fn Q6_Wh_vlut16or_WhVbVhI( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4249,11 +4262,11 @@ pub unsafe fn q6_wh_vlut16or_whvbvhi( /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwhi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { vlutvwhi(vu, vv, iu3) } @@ -4261,11 +4274,11 @@ pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmaxb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxb(vu, vv) } @@ -4273,11 +4286,11 @@ pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vminb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vminb(vu, vv) } @@ -4285,11 +4298,11 @@ pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpauhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpauhb(vuu, rt) } @@ -4297,11 +4310,11 @@ pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpauhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpaacc_wwwuhrb( +pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -4313,11 +4326,11 @@ pub unsafe fn q6_ww_vmpaacc_wwwuhrb( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyewuh_64))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyewuh_64(vu, vv) } @@ -4325,11 +4338,11 @@ pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyiwub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwub(vu, rt) } @@ -4337,11 +4350,11 @@ pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyiwub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwub_acc(vx, vu, rt) } @@ -4349,11 +4362,11 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> H /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyowh_64_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vmpyoacc_wvwvh( +pub unsafe fn Q6_W_vmpyoacc_WVwVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4365,11 +4378,11 @@ pub unsafe fn q6_w_vmpyoacc_wvwvh( /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vrounduhub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vrounduhub(vu, vv) } @@ -4377,11 +4390,11 @@ pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vrounduwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vrounduwuh(vu, vv) } @@ -4389,11 +4402,11 @@ pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsatuwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatuwuh(vu, vv) } @@ -4401,11 +4414,11 @@ pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubbsat(vu, vv) } @@ -4413,11 +4426,11 @@ pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubbsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubbsat_dv(vuu, vvv) } @@ -4425,11 +4438,11 @@ pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubububb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubububb_sat(vu, vv) } @@ -4437,11 +4450,11 @@ pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubuwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubuwsat(vu, vv) } @@ -4449,11 +4462,11 @@ pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubuwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubuwsat_dv(vuu, vvv) } @@ -4461,11 +4474,11 @@ pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vabsb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector { vabsb(vu) } @@ -4473,11 +4486,11 @@ pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vabsb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector { vabsb_sat(vu) } @@ -4485,11 +4498,11 @@ pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vaslh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vaslh_acc(vx, vu, rt) } @@ -4497,11 +4510,11 @@ pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasrh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vasrh_acc(vx, vu, rt) } @@ -4509,11 +4522,11 @@ pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruhubrndsat(vu, vv, rt) } @@ -4521,11 +4534,11 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruhubsat(vu, vv, rt) } @@ -4533,11 +4546,11 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruwuhsat(vu, vv, rt) } @@ -4545,11 +4558,11 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavgb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgb(vu, vv) } @@ -4557,11 +4570,11 @@ pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavgbrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgbrnd(vu, vv) } @@ -4569,11 +4582,11 @@ pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavguw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguw(vu, vv) } @@ -4581,11 +4594,11 @@ pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavguwrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguwrnd(vu, vv) } @@ -4593,11 +4606,11 @@ pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: MAPPING /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vdd0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vzero() -> HvxVectorPair { +pub unsafe fn Q6_W_vzero() -> HvxVectorPair { vdd0() } @@ -4605,11 +4618,11 @@ pub unsafe fn q6_w_vzero() -> HvxVectorPair { /// /// Instruction Type: CVI_GATHER /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { +pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { vgathermh(rs, rt, mu, vv) } @@ -4617,11 +4630,11 @@ pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect /// /// Instruction Type: CVI_GATHER_DV /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { +pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { vgathermhw(rs, rt, mu, vvv) } @@ -4629,11 +4642,11 @@ pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVec /// /// Instruction Type: CVI_GATHER /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { +pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { vgathermw(rs, rt, mu, vv) } @@ -4641,11 +4654,11 @@ pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpabuu))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpabuu(vuu, rt) } @@ -4653,11 +4666,11 @@ pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpabuu_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpaacc_whwubrub( +pub unsafe fn Q6_Wh_vmpaacc_WhWubRub( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -4669,11 +4682,11 @@ pub unsafe fn q6_wh_vmpaacc_whwubrub( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyh_acc(vxx, vu, rt) } @@ -4681,11 +4694,11 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyuhe))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector { vmpyuhe(vu, rt) } @@ -4693,11 +4706,11 @@ pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyuhe_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyuhe_acc(vx, vu, rt) } @@ -4705,11 +4718,11 @@ pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) - /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vnavgb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgb(vu, vv) } @@ -4717,11 +4730,11 @@ pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermh(rt, mu, vv, vw) } @@ -4729,11 +4742,11 @@ pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) /// /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermh_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermh_add(rt, mu, vv, vw) } @@ -4741,11 +4754,11 @@ pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto /// /// Instruction Type: CVI_SCATTER_DV /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { vscattermhw(rt, mu, vvv, vw) } @@ -4753,11 +4766,11 @@ pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVec /// /// Instruction Type: CVI_SCATTER_DV /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermhw_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { vscattermhw_add(rt, mu, vvv, vw) } @@ -4765,11 +4778,11 @@ pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: Hvx /// /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermw(rt, mu, vv, vw) } @@ -4777,11 +4790,11 @@ pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) /// /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermw_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermw_add(rt, mu, vv, vw) } @@ -4789,11 +4802,11 @@ pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto /// /// Instruction Type: CVI_VP_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vasr_into))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vasrinto_wwvwvw( +pub unsafe fn Q6_Ww_vasrinto_WwVwVw( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4805,11 +4818,11 @@ pub unsafe fn q6_ww_vasrinto_wwvwvw( /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vrotr))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vrotr(vu, vv) } @@ -4817,11 +4830,11 @@ pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vsatdw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatdw(vu, vv) } @@ -4829,11 +4842,11 @@ pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyhubs10))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpy_wubwbi_h( +pub unsafe fn Q6_Ww_v6mpy_WubWbI_h( vuu: HvxVectorPair, vvv: HvxVectorPair, iu2: i32, @@ -4845,11 +4858,11 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_h( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h( vxx: HvxVectorPair, vuu: HvxVectorPair, vvv: HvxVectorPair, @@ -4862,11 +4875,11 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyvubs10))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpy_wubwbi_v( +pub unsafe fn Q6_Ww_v6mpy_WubWbI_v( vuu: HvxVectorPair, vvv: HvxVectorPair, iu2: i32, @@ -4878,11 +4891,11 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_v( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v( vxx: HvxVectorPair, vuu: HvxVectorPair, vvv: HvxVectorPair, @@ -4895,11 +4908,11 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vabs_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector { vabs_hf(vu) } @@ -4907,11 +4920,11 @@ pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vabs_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector { vabs_sf(vu) } @@ -4919,11 +4932,11 @@ pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_hf(vu, vv) } @@ -4931,11 +4944,11 @@ pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_hf_hf(vu, vv) } @@ -4943,11 +4956,11 @@ pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf16(vu, vv) } @@ -4955,11 +4968,11 @@ pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf16_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf16_mix(vu, vv) } @@ -4967,11 +4980,11 @@ pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf32(vu, vv) } @@ -4979,11 +4992,11 @@ pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf32_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf32_mix(vu, vv) } @@ -4991,11 +5004,11 @@ pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_sf(vu, vv) } @@ -5003,11 +5016,11 @@ pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vadd_sf_hf(vu, vv) } @@ -5015,11 +5028,11 @@ pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_sf_sf(vu, vv) } @@ -5027,11 +5040,11 @@ pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vassign_fp))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector { vassign_fp(vu) } @@ -5039,11 +5052,11 @@ pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_hf_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector { vconv_hf_qf16(vu) } @@ -5051,11 +5064,11 @@ pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_hf_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector { vconv_hf_qf32(vuu) } @@ -5063,11 +5076,11 @@ pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_sf_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector { vconv_sf_qf32(vu) } @@ -5075,11 +5088,11 @@ pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_b_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_b_hf(vu, vv) } @@ -5087,11 +5100,11 @@ pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_h_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector { vcvt_h_hf(vu) } @@ -5099,11 +5112,11 @@ pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_b))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair { vcvt_hf_b(vu) } @@ -5111,11 +5124,11 @@ pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector { vcvt_hf_h(vu) } @@ -5123,11 +5136,11 @@ pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_hf_sf(vu, vv) } @@ -5135,11 +5148,11 @@ pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_ub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair { vcvt_hf_ub(vu) } @@ -5147,11 +5160,11 @@ pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_uh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector { vcvt_hf_uh(vu) } @@ -5159,11 +5172,11 @@ pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair { vcvt_sf_hf(vu) } @@ -5171,11 +5184,11 @@ pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_ub_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_ub_hf(vu, vv) } @@ -5183,11 +5196,11 @@ pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_uh_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector { vcvt_uh_hf(vu) } @@ -5195,11 +5208,11 @@ pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vdmpy_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpy_sf_hf(vu, vv) } @@ -5207,11 +5220,11 @@ pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpy_sf_hf_acc(vx, vu, vv) } @@ -5219,11 +5232,11 @@ pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVec /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmax_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_hf(vu, vv) } @@ -5231,11 +5244,11 @@ pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmax_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_sf(vu, vv) } @@ -5243,11 +5256,11 @@ pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmin_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_hf(vu, vv) } @@ -5255,11 +5268,11 @@ pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmin_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_sf(vu, vv) } @@ -5267,11 +5280,11 @@ pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfneg_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector { vfneg_hf(vu) } @@ -5279,11 +5292,11 @@ pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfneg_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector { vfneg_sf(vu) } @@ -5291,11 +5304,11 @@ pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmax_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmax_hf(vu, vv) } @@ -5303,11 +5316,11 @@ pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmax_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmax_sf(vu, vv) } @@ -5315,11 +5328,11 @@ pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmin_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmin_hf(vu, vv) } @@ -5327,11 +5340,11 @@ pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmin_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmin_sf(vu, vv) } @@ -5339,11 +5352,11 @@ pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_hf_hf(vu, vv) } @@ -5351,11 +5364,11 @@ pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_hf_hf_acc(vx, vu, vv) } @@ -5363,11 +5376,11 @@ pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVect /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16(vu, vv) } @@ -5375,11 +5388,11 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16_hf(vu, vv) } @@ -5387,11 +5400,11 @@ pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16_mix_hf(vu, vv) } @@ -5399,11 +5412,11 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf32(vu, vv) } @@ -5411,11 +5424,11 @@ pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_hf(vu, vv) } @@ -5423,11 +5436,11 @@ pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPai /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_mix_hf(vu, vv) } @@ -5435,11 +5448,11 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorP /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_qf16(vu, vv) } @@ -5447,11 +5460,11 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf32_sf(vu, vv) } @@ -5459,11 +5472,11 @@ pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_sf_hf(vu, vv) } @@ -5471,11 +5484,11 @@ pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( +pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -5487,11 +5500,11 @@ pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_sf_sf(vu, vv) } @@ -5499,11 +5512,11 @@ pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_hf(vu, vv) } @@ -5511,11 +5524,11 @@ pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_hf_hf(vu, vv) } @@ -5523,11 +5536,11 @@ pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf16(vu, vv) } @@ -5535,11 +5548,11 @@ pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf16_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf16_mix(vu, vv) } @@ -5547,11 +5560,11 @@ pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf32(vu, vv) } @@ -5559,11 +5572,11 @@ pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf32_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf32_mix(vu, vv) } @@ -5571,11 +5584,11 @@ pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_sf(vu, vv) } @@ -5583,11 +5596,11 @@ pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsub_sf_hf(vu, vv) } @@ -5595,11 +5608,11 @@ pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_sf_sf(vu, vv) } @@ -5607,11 +5620,11 @@ pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvuhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvuhubrndsat(vuu, vv) } @@ -5619,11 +5632,11 @@ pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> H /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvuhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvuhubsat(vuu, vv) } @@ -5631,11 +5644,11 @@ pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVe /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvwuhrndsat(vuu, vv) } @@ -5643,11 +5656,11 @@ pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> Hv /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvwuhsat(vuu, vv) } @@ -5655,11 +5668,11 @@ pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVec /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vmpyuhvs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyuhvs(vu, vv) } @@ -5667,11 +5680,11 @@ pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_h_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector { vconv_h_hf(vu) } @@ -5679,11 +5692,11 @@ pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_hf_h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector { vconv_hf_h(vu) } @@ -5691,11 +5704,11 @@ pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_sf_w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector { vconv_sf_w(vu) } @@ -5703,11 +5716,11 @@ pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_w_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector { vconv_w_sf(vu) } @@ -5715,11 +5728,11 @@ pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(get_qfext))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { get_qfext(vu, rt) } @@ -5727,11 +5740,11 @@ pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(set_qfext))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { set_qfext(vu, rt) } @@ -5739,11 +5752,11 @@ pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vabs_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector { vabs_f8(vu) } @@ -5751,11 +5764,11 @@ pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt2_hf_b))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair { vcvt2_hf_b(vu) } @@ -5763,11 +5776,11 @@ pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt2_hf_ub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair { vcvt2_hf_ub(vu) } @@ -5775,11 +5788,11 @@ pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_DV /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt_hf_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair { vcvt_hf_f8(vu) } @@ -5787,11 +5800,11 @@ pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfmax_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_f8(vu, vv) } @@ -5799,11 +5812,11 @@ pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfmin_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_f8(vu, vv) } @@ -5811,11 +5824,11 @@ pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { /// /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfneg_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector { vfneg_f8(vu) } @@ -5824,10 +5837,10 @@ pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_and( vandvrt(core::mem::transmute::(qs), -1), @@ -5842,10 +5855,10 @@ pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_and_n( vandvrt(core::mem::transmute::(qs), -1), @@ -5860,10 +5873,10 @@ pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPre /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_not(vandvrt( core::mem::transmute::(qs), @@ -5878,10 +5891,10 @@ pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_or( vandvrt(core::mem::transmute::(qs), -1), @@ -5896,10 +5909,10 @@ pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_or_n( vandvrt(core::mem::transmute::(qs), -1), @@ -5914,10 +5927,10 @@ pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) } @@ -5926,10 +5939,10 @@ pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_xor( vandvrt(core::mem::transmute::(qs), -1), @@ -5944,10 +5957,10 @@ pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VM_ST /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nqpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5960,10 +5973,10 @@ pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VM_ST /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nt_nqpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5976,10 +5989,10 @@ pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVec /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VM_ST /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nt_qpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5992,10 +6005,10 @@ pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VM_ST /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_qpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -6008,10 +6021,10 @@ pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddbnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6024,10 +6037,10 @@ pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddbq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6040,10 +6053,10 @@ pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddhnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6056,10 +6069,10 @@ pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddhq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6072,10 +6085,10 @@ pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddwnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6088,10 +6101,10 @@ pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddwq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6104,10 +6117,10 @@ pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector { vandvrt(core::mem::transmute::(qu), rt) } @@ -6116,10 +6129,10 @@ pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { vandvrt_acc(vx, core::mem::transmute::(qu), rt) } @@ -6128,10 +6141,10 @@ pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxV /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(vu, rt)) } @@ -6140,10 +6153,10 @@ pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt_acc( core::mem::transmute::(qx), vu, @@ -6156,10 +6169,10 @@ pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxV /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) } @@ -6168,10 +6181,10 @@ pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqand_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6191,10 +6204,10 @@ pub unsafe fn q6_q_vcmp_eqand_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqor_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6214,10 +6227,10 @@ pub unsafe fn q6_q_vcmp_eqor_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6237,10 +6250,10 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) } @@ -6249,10 +6262,10 @@ pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqand_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6272,10 +6285,10 @@ pub unsafe fn q6_q_vcmp_eqand_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqor_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6295,10 +6308,10 @@ pub unsafe fn q6_q_vcmp_eqor_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6318,10 +6331,10 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) } @@ -6330,10 +6343,10 @@ pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqand_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6353,10 +6366,10 @@ pub unsafe fn q6_q_vcmp_eqand_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqor_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6376,10 +6389,10 @@ pub unsafe fn q6_q_vcmp_eqor_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6399,10 +6412,10 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) } @@ -6411,10 +6424,10 @@ pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtand_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6434,10 +6447,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtor_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6457,10 +6470,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6480,10 +6493,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) } @@ -6492,10 +6505,10 @@ pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtand_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6515,10 +6528,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtor_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6538,10 +6551,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6561,10 +6574,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) } @@ -6573,10 +6586,10 @@ pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtand_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6596,10 +6609,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvubvub( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtor_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6619,10 +6632,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvubvub( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6642,10 +6655,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) } @@ -6654,10 +6667,10 @@ pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6677,10 +6690,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6700,10 +6713,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6723,10 +6736,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) } @@ -6735,10 +6748,10 @@ pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6758,10 +6771,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6781,10 +6794,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6804,10 +6817,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) } @@ -6816,10 +6829,10 @@ pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtand_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6839,10 +6852,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtor_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6862,10 +6875,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6885,10 +6898,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { vmux( vandvrt(core::mem::transmute::(qt), -1), vu, @@ -6901,10 +6914,10 @@ pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubbnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6917,10 +6930,10 @@ pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubbq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6933,10 +6946,10 @@ pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubhnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6949,10 +6962,10 @@ pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubhq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6965,10 +6978,10 @@ pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubwnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6981,10 +6994,10 @@ pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubwq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6997,10 +7010,10 @@ pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vswap( vandvrt(core::mem::transmute::(qt), -1), vu, @@ -7013,10 +7026,10 @@ pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VP /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) } @@ -7025,10 +7038,10 @@ pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( shuffeqh( vandvrt(core::mem::transmute::(qs), -1), @@ -7043,10 +7056,10 @@ pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA_DV /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( shuffeqw( vandvrt(core::mem::transmute::(qs), -1), @@ -7061,10 +7074,10 @@ pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector { vandnqrt( vandvrt(core::mem::transmute::(qu), -1), rt, @@ -7076,10 +7089,10 @@ pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VX_LATE /// Execution Slots: SLOT23 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { vandnqrt_acc( vx, vandvrt(core::mem::transmute::(qu), -1), @@ -7092,10 +7105,10 @@ pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> Hvx /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { vandvnqv( vandvrt(core::mem::transmute::(qv), -1), vu, @@ -7107,10 +7120,10 @@ pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { vandvqv( vandvrt(core::mem::transmute::(qv), -1), vu, @@ -7122,10 +7135,10 @@ pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_GATHER /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmvh( +pub unsafe fn Q6_vgather_AQRMVh( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7146,10 +7159,10 @@ pub unsafe fn q6_vgather_aqrmvh( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_GATHER_DV /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmww( +pub unsafe fn Q6_vgather_AQRMWw( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7170,10 +7183,10 @@ pub unsafe fn q6_vgather_aqrmww( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_GATHER /// Execution Slots: SLOT01 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmvw( +pub unsafe fn Q6_vgather_AQRMVw( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7194,10 +7207,10 @@ pub unsafe fn q6_vgather_aqrmvw( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqb(vandvrt( core::mem::transmute::(qv), -1, @@ -7209,10 +7222,10 @@ pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqh(vandvrt( core::mem::transmute::(qv), -1, @@ -7224,10 +7237,10 @@ pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VS /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqw(vandvrt( core::mem::transmute::(qv), -1, @@ -7239,10 +7252,10 @@ pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmvhv( +pub unsafe fn Q6_vscatter_QRMVhV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7263,10 +7276,10 @@ pub unsafe fn q6_vscatter_qrmvhv( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_SCATTER_DV /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmwwv( +pub unsafe fn Q6_vscatter_QRMWwV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7287,10 +7300,10 @@ pub unsafe fn q6_vscatter_qrmwwv( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_SCATTER /// Execution Slots: SLOT0 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmvwv( +pub unsafe fn Q6_vscatter_QRMVwV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7311,10 +7324,10 @@ pub unsafe fn q6_vscatter_qrmvwv( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( +pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat( vu: HvxVector, vv: HvxVector, qs: HvxVectorPred, @@ -7331,10 +7344,10 @@ pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) } @@ -7343,10 +7356,10 @@ pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7366,10 +7379,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7389,10 +7402,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7412,10 +7425,10 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) } @@ -7424,10 +7437,10 @@ pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7447,10 +7460,10 @@ pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7470,10 +7483,10 @@ pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( /// This is a compound operation composed of multiple HVX instructions. /// Instruction Type: CVI_VA /// Execution Slots: SLOT0123 -#[inline(always)] +#[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, diff --git a/stdarch/crates/core_arch/src/lib.rs b/stdarch/crates/core_arch/src/lib.rs index 9255994e5ee81..b9d63b44975ab 100644 --- a/stdarch/crates/core_arch/src/lib.rs +++ b/stdarch/crates/core_arch/src/lib.rs @@ -33,14 +33,14 @@ x86_amx_intrinsics, f16, aarch64_unstable_target_feature, - target_feature_inline_always, funnel_shifts, avx10_target_feature, const_trait_impl, const_cmp, const_eval_select, maybe_uninit_as_bytes, - movrs_target_feature + movrs_target_feature, + min_adt_const_params )] #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))] #![deny(clippy::missing_inline_in_public_items)] @@ -70,7 +70,11 @@ )] #![cfg_attr( test, - feature(stdarch_arm_feature_detection, stdarch_powerpc_feature_detection,) + feature( + stdarch_arm_feature_detection, + stdarch_mips_feature_detection, + stdarch_powerpc_feature_detection, + ) )] #[cfg(test)] diff --git a/stdarch/crates/core_arch/src/loongarch32/mod.rs b/stdarch/crates/core_arch/src/loongarch32/mod.rs index 4e3f3d27182e4..6cc1116113e1d 100644 --- a/stdarch/crates/core_arch/src/loongarch32/mod.rs +++ b/stdarch/crates/core_arch/src/loongarch32/mod.rs @@ -15,7 +15,7 @@ unsafe extern "unadjusted" { } /// Generates the cache operation instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn cacop(b: i32) { static_assert_uimm_bits!(IMM5, 5); @@ -24,7 +24,7 @@ pub unsafe fn cacop(b: i32) { } /// Reads the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrrd() -> i32 { static_assert_uimm_bits!(IMM14, 14); @@ -32,7 +32,7 @@ pub unsafe fn csrrd() -> i32 { } /// Writes the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrwr(a: i32) -> i32 { static_assert_uimm_bits!(IMM14, 14); @@ -40,7 +40,7 @@ pub unsafe fn csrwr(a: i32) -> i32 { } /// Exchanges the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrxchg(a: i32, b: i32) -> i32 { static_assert_uimm_bits!(IMM14, 14); diff --git a/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs b/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs index 1d9d4e8248e63..ec7693e27747a 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs @@ -11,38 +11,6 @@ use super::super::*; #[allow(improper_ctypes)] unsafe extern "unadjusted" { - #[link_name = "llvm.loongarch.lasx.xvsll.b"] - fn __lasx_xvsll_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsll.h"] - fn __lasx_xvsll_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsll.w"] - fn __lasx_xvsll_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsll.d"] - fn __lasx_xvsll_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslli.b"] - fn __lasx_xvslli_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslli.h"] - fn __lasx_xvslli_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslli.w"] - fn __lasx_xvslli_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslli.d"] - fn __lasx_xvslli_d(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsra.b"] - fn __lasx_xvsra_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsra.h"] - fn __lasx_xvsra_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsra.w"] - fn __lasx_xvsra_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsra.d"] - fn __lasx_xvsra_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsrai.b"] - fn __lasx_xvsrai_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsrai.h"] - fn __lasx_xvsrai_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsrai.w"] - fn __lasx_xvsrai_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsrai.d"] - fn __lasx_xvsrai_d(a: __v4i64, b: u32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsrar.b"] fn __lasx_xvsrar_b(a: __v32i8, b: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvsrar.h"] @@ -59,22 +27,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsrari_w(a: __v8i32, b: u32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvsrari.d"] fn __lasx_xvsrari_d(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsrl.b"] - fn __lasx_xvsrl_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsrl.h"] - fn __lasx_xvsrl_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsrl.w"] - fn __lasx_xvsrl_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsrl.d"] - fn __lasx_xvsrl_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsrli.b"] - fn __lasx_xvsrli_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsrli.h"] - fn __lasx_xvsrli_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsrli.w"] - fn __lasx_xvsrli_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsrli.d"] - fn __lasx_xvsrli_d(a: __v4i64, b: u32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsrlr.b"] fn __lasx_xvsrlr_b(a: __v32i8, b: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvsrlr.h"] @@ -91,14 +43,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsrlri_w(a: __v8i32, b: u32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvsrlri.d"] fn __lasx_xvsrlri_d(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvbitclr.b"] - fn __lasx_xvbitclr_b(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvbitclr.h"] - fn __lasx_xvbitclr_h(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvbitclr.w"] - fn __lasx_xvbitclr_w(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvbitclr.d"] - fn __lasx_xvbitclr_d(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvbitclri.b"] fn __lasx_xvbitclri_b(a: __v32u8, b: u32) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitclri.h"] @@ -107,14 +51,6 @@ unsafe extern "unadjusted" { fn __lasx_xvbitclri_w(a: __v8u32, b: u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvbitclri.d"] fn __lasx_xvbitclri_d(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvbitset.b"] - fn __lasx_xvbitset_b(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvbitset.h"] - fn __lasx_xvbitset_h(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvbitset.w"] - fn __lasx_xvbitset_w(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvbitset.d"] - fn __lasx_xvbitset_d(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvbitseti.b"] fn __lasx_xvbitseti_b(a: __v32u8, b: u32) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitseti.h"] @@ -123,14 +59,6 @@ unsafe extern "unadjusted" { fn __lasx_xvbitseti_w(a: __v8u32, b: u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvbitseti.d"] fn __lasx_xvbitseti_d(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvbitrev.b"] - fn __lasx_xvbitrev_b(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvbitrev.h"] - fn __lasx_xvbitrev_h(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvbitrev.w"] - fn __lasx_xvbitrev_w(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvbitrev.d"] - fn __lasx_xvbitrev_d(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvbitrevi.b"] fn __lasx_xvbitrevi_b(a: __v32u8, b: u32) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitrevi.h"] @@ -139,30 +67,6 @@ unsafe extern "unadjusted" { fn __lasx_xvbitrevi_w(a: __v8u32, b: u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvbitrevi.d"] fn __lasx_xvbitrevi_d(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvadd.b"] - fn __lasx_xvadd_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvadd.h"] - fn __lasx_xvadd_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvadd.w"] - fn __lasx_xvadd_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvadd.d"] - fn __lasx_xvadd_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvaddi.bu"] - fn __lasx_xvaddi_bu(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvaddi.hu"] - fn __lasx_xvaddi_hu(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvaddi.wu"] - fn __lasx_xvaddi_wu(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvaddi.du"] - fn __lasx_xvaddi_du(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsub.b"] - fn __lasx_xvsub_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsub.h"] - fn __lasx_xvsub_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsub.w"] - fn __lasx_xvsub_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsub.d"] - fn __lasx_xvsub_d(a: __v4i64, b: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsubi.bu"] fn __lasx_xvsubi_bu(a: __v32i8, b: u32) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvsubi.hu"] @@ -171,150 +75,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsubi_wu(a: __v8i32, b: u32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvsubi.du"] fn __lasx_xvsubi_du(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmax.b"] - fn __lasx_xvmax_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmax.h"] - fn __lasx_xvmax_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmax.w"] - fn __lasx_xvmax_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmax.d"] - fn __lasx_xvmax_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmaxi.b"] - fn __lasx_xvmaxi_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmaxi.h"] - fn __lasx_xvmaxi_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmaxi.w"] - fn __lasx_xvmaxi_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmaxi.d"] - fn __lasx_xvmaxi_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmax.bu"] - fn __lasx_xvmax_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmax.hu"] - fn __lasx_xvmax_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmax.wu"] - fn __lasx_xvmax_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmax.du"] - fn __lasx_xvmax_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvmaxi.bu"] - fn __lasx_xvmaxi_bu(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmaxi.hu"] - fn __lasx_xvmaxi_hu(a: __v16u16, b: u32) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmaxi.wu"] - fn __lasx_xvmaxi_wu(a: __v8u32, b: u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmaxi.du"] - fn __lasx_xvmaxi_du(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvmin.b"] - fn __lasx_xvmin_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmin.h"] - fn __lasx_xvmin_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmin.w"] - fn __lasx_xvmin_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmin.d"] - fn __lasx_xvmin_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmini.b"] - fn __lasx_xvmini_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmini.h"] - fn __lasx_xvmini_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmini.w"] - fn __lasx_xvmini_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmini.d"] - fn __lasx_xvmini_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmin.bu"] - fn __lasx_xvmin_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmin.hu"] - fn __lasx_xvmin_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmin.wu"] - fn __lasx_xvmin_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmin.du"] - fn __lasx_xvmin_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvmini.bu"] - fn __lasx_xvmini_bu(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmini.hu"] - fn __lasx_xvmini_hu(a: __v16u16, b: u32) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmini.wu"] - fn __lasx_xvmini_wu(a: __v8u32, b: u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmini.du"] - fn __lasx_xvmini_du(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvseq.b"] - fn __lasx_xvseq_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvseq.h"] - fn __lasx_xvseq_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvseq.w"] - fn __lasx_xvseq_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvseq.d"] - fn __lasx_xvseq_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvseqi.b"] - fn __lasx_xvseqi_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvseqi.h"] - fn __lasx_xvseqi_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvseqi.w"] - fn __lasx_xvseqi_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvseqi.d"] - fn __lasx_xvseqi_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslt.b"] - fn __lasx_xvslt_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslt.h"] - fn __lasx_xvslt_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslt.w"] - fn __lasx_xvslt_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslt.d"] - fn __lasx_xvslt_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslti.b"] - fn __lasx_xvslti_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslti.h"] - fn __lasx_xvslti_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslti.w"] - fn __lasx_xvslti_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslti.d"] - fn __lasx_xvslti_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslt.bu"] - fn __lasx_xvslt_bu(a: __v32u8, b: __v32u8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslt.hu"] - fn __lasx_xvslt_hu(a: __v16u16, b: __v16u16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslt.wu"] - fn __lasx_xvslt_wu(a: __v8u32, b: __v8u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslt.du"] - fn __lasx_xvslt_du(a: __v4u64, b: __v4u64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslti.bu"] - fn __lasx_xvslti_bu(a: __v32u8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslti.hu"] - fn __lasx_xvslti_hu(a: __v16u16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslti.wu"] - fn __lasx_xvslti_wu(a: __v8u32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslti.du"] - fn __lasx_xvslti_du(a: __v4u64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsle.b"] - fn __lasx_xvsle_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsle.h"] - fn __lasx_xvsle_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsle.w"] - fn __lasx_xvsle_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsle.d"] - fn __lasx_xvsle_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslei.b"] - fn __lasx_xvslei_b(a: __v32i8, b: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslei.h"] - fn __lasx_xvslei_h(a: __v16i16, b: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslei.w"] - fn __lasx_xvslei_w(a: __v8i32, b: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslei.d"] - fn __lasx_xvslei_d(a: __v4i64, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsle.bu"] - fn __lasx_xvsle_bu(a: __v32u8, b: __v32u8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsle.hu"] - fn __lasx_xvsle_hu(a: __v16u16, b: __v16u16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsle.wu"] - fn __lasx_xvsle_wu(a: __v8u32, b: __v8u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsle.du"] - fn __lasx_xvsle_du(a: __v4u64, b: __v4u64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvslei.bu"] - fn __lasx_xvslei_bu(a: __v32u8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvslei.hu"] - fn __lasx_xvslei_hu(a: __v16u16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvslei.wu"] - fn __lasx_xvslei_wu(a: __v8u32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvslei.du"] - fn __lasx_xvslei_du(a: __v4u64, b: u32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvsat.b"] fn __lasx_xvsat_b(a: __v32i8, b: u32) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvsat.h"] @@ -331,30 +91,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsat_wu(a: __v8u32, b: u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvsat.du"] fn __lasx_xvsat_du(a: __v4u64, b: u32) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvadda.b"] - fn __lasx_xvadda_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvadda.h"] - fn __lasx_xvadda_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvadda.w"] - fn __lasx_xvadda_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvadda.d"] - fn __lasx_xvadda_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsadd.b"] - fn __lasx_xvsadd_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvsadd.h"] - fn __lasx_xvsadd_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvsadd.w"] - fn __lasx_xvsadd_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvsadd.d"] - fn __lasx_xvsadd_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvsadd.bu"] - fn __lasx_xvsadd_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvsadd.hu"] - fn __lasx_xvsadd_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvsadd.wu"] - fn __lasx_xvsadd_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvsadd.du"] - fn __lasx_xvsadd_du(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvavg.b"] fn __lasx_xvavg_b(a: __v32i8, b: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvavg.h"] @@ -387,78 +123,6 @@ unsafe extern "unadjusted" { fn __lasx_xvavgr_wu(a: __v8u32, b: __v8u32) -> __v8u32; #[link_name = "llvm.loongarch.lasx.xvavgr.du"] fn __lasx_xvavgr_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvssub.b"] - fn __lasx_xvssub_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvssub.h"] - fn __lasx_xvssub_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvssub.w"] - fn __lasx_xvssub_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvssub.d"] - fn __lasx_xvssub_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvssub.bu"] - fn __lasx_xvssub_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvssub.hu"] - fn __lasx_xvssub_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvssub.wu"] - fn __lasx_xvssub_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvssub.du"] - fn __lasx_xvssub_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvabsd.b"] - fn __lasx_xvabsd_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvabsd.h"] - fn __lasx_xvabsd_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvabsd.w"] - fn __lasx_xvabsd_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvabsd.d"] - fn __lasx_xvabsd_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvabsd.bu"] - fn __lasx_xvabsd_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvabsd.hu"] - fn __lasx_xvabsd_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvabsd.wu"] - fn __lasx_xvabsd_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvabsd.du"] - fn __lasx_xvabsd_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvmul.b"] - fn __lasx_xvmul_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmul.h"] - fn __lasx_xvmul_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmul.w"] - fn __lasx_xvmul_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmul.d"] - fn __lasx_xvmul_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmadd.b"] - fn __lasx_xvmadd_b(a: __v32i8, b: __v32i8, c: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmadd.h"] - fn __lasx_xvmadd_h(a: __v16i16, b: __v16i16, c: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmadd.w"] - fn __lasx_xvmadd_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmadd.d"] - fn __lasx_xvmadd_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmsub.b"] - fn __lasx_xvmsub_b(a: __v32i8, b: __v32i8, c: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmsub.h"] - fn __lasx_xvmsub_h(a: __v16i16, b: __v16i16, c: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmsub.w"] - fn __lasx_xvmsub_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmsub.d"] - fn __lasx_xvmsub_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvdiv.b"] - fn __lasx_xvdiv_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvdiv.h"] - fn __lasx_xvdiv_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvdiv.w"] - fn __lasx_xvdiv_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvdiv.d"] - fn __lasx_xvdiv_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvdiv.bu"] - fn __lasx_xvdiv_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvdiv.hu"] - fn __lasx_xvdiv_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvdiv.wu"] - fn __lasx_xvdiv_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvdiv.du"] - fn __lasx_xvdiv_du(a: __v4u64, b: __v4u64) -> __v4u64; #[link_name = "llvm.loongarch.lasx.xvhaddw.h.b"] fn __lasx_xvhaddw_h_b(a: __v32i8, b: __v32i8) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvhaddw.w.h"] @@ -483,62 +147,6 @@ unsafe extern "unadjusted" { fn __lasx_xvhsubw_wu_hu(a: __v16u16, b: __v16u16) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvhsubw.du.wu"] fn __lasx_xvhsubw_du_wu(a: __v8u32, b: __v8u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmod.b"] - fn __lasx_xvmod_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvmod.h"] - fn __lasx_xvmod_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvmod.w"] - fn __lasx_xvmod_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvmod.d"] - fn __lasx_xvmod_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvmod.bu"] - fn __lasx_xvmod_bu(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvmod.hu"] - fn __lasx_xvmod_hu(a: __v16u16, b: __v16u16) -> __v16u16; - #[link_name = "llvm.loongarch.lasx.xvmod.wu"] - fn __lasx_xvmod_wu(a: __v8u32, b: __v8u32) -> __v8u32; - #[link_name = "llvm.loongarch.lasx.xvmod.du"] - fn __lasx_xvmod_du(a: __v4u64, b: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvrepl128vei.b"] - fn __lasx_xvrepl128vei_b(a: __v32i8, b: u32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvrepl128vei.h"] - fn __lasx_xvrepl128vei_h(a: __v16i16, b: u32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvrepl128vei.w"] - fn __lasx_xvrepl128vei_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvrepl128vei.d"] - fn __lasx_xvrepl128vei_d(a: __v4i64, b: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpickev.b"] - fn __lasx_xvpickev_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvpickev.h"] - fn __lasx_xvpickev_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvpickev.w"] - fn __lasx_xvpickev_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvpickev.d"] - fn __lasx_xvpickev_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpickod.b"] - fn __lasx_xvpickod_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvpickod.h"] - fn __lasx_xvpickod_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvpickod.w"] - fn __lasx_xvpickod_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvpickod.d"] - fn __lasx_xvpickod_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvilvh.b"] - fn __lasx_xvilvh_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvilvh.h"] - fn __lasx_xvilvh_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvilvh.w"] - fn __lasx_xvilvh_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvilvh.d"] - fn __lasx_xvilvh_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvilvl.b"] - fn __lasx_xvilvl_b(a: __v32i8, b: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvilvl.h"] - fn __lasx_xvilvl_h(a: __v16i16, b: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvilvl.w"] - fn __lasx_xvilvl_w(a: __v8i32, b: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvilvl.d"] - fn __lasx_xvilvl_d(a: __v4i64, b: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvpackev.b"] fn __lasx_xvpackev_b(a: __v32i8, b: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvpackev.h"] @@ -563,20 +171,12 @@ unsafe extern "unadjusted" { fn __lasx_xvshuf_w(a: __v8i32, b: __v8i32, c: __v8i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvshuf.d"] fn __lasx_xvshuf_d(a: __v4i64, b: __v4i64, c: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvand.v"] - fn __lasx_xvand_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvandi.b"] fn __lasx_xvandi_b(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvor.v"] - fn __lasx_xvor_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvori.b"] fn __lasx_xvori_b(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvnor.v"] - fn __lasx_xvnor_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvnori.b"] fn __lasx_xvnori_b(a: __v32u8, b: u32) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvxor.v"] - fn __lasx_xvxor_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvxori.b"] fn __lasx_xvxori_b(a: __v32u8, b: u32) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvbitsel.v"] @@ -589,22 +189,6 @@ unsafe extern "unadjusted" { fn __lasx_xvshuf4i_h(a: __v16i16, b: u32) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvshuf4i.w"] fn __lasx_xvshuf4i_w(a: __v8i32, b: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.b"] - fn __lasx_xvreplgr2vr_b(a: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.h"] - fn __lasx_xvreplgr2vr_h(a: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.w"] - fn __lasx_xvreplgr2vr_w(a: i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvreplgr2vr.d"] - fn __lasx_xvreplgr2vr_d(a: i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpcnt.b"] - fn __lasx_xvpcnt_b(a: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvpcnt.h"] - fn __lasx_xvpcnt_h(a: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvpcnt.w"] - fn __lasx_xvpcnt_w(a: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvpcnt.d"] - fn __lasx_xvpcnt_d(a: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvclo.b"] fn __lasx_xvclo_b(a: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvclo.h"] @@ -613,30 +197,6 @@ unsafe extern "unadjusted" { fn __lasx_xvclo_w(a: __v8i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvclo.d"] fn __lasx_xvclo_d(a: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvclz.b"] - fn __lasx_xvclz_b(a: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvclz.h"] - fn __lasx_xvclz_h(a: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvclz.w"] - fn __lasx_xvclz_w(a: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvclz.d"] - fn __lasx_xvclz_d(a: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvfadd.s"] - fn __lasx_xvfadd_s(a: __v8f32, b: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfadd.d"] - fn __lasx_xvfadd_d(a: __v4f64, b: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfsub.s"] - fn __lasx_xvfsub_s(a: __v8f32, b: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfsub.d"] - fn __lasx_xvfsub_d(a: __v4f64, b: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfmul.s"] - fn __lasx_xvfmul_s(a: __v8f32, b: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfmul.d"] - fn __lasx_xvfmul_d(a: __v4f64, b: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfdiv.s"] - fn __lasx_xvfdiv_s(a: __v8f32, b: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfdiv.d"] - fn __lasx_xvfdiv_d(a: __v4f64, b: __v4f64) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvfcvt.h.s"] fn __lasx_xvfcvt_h_s(a: __v8f32, b: __v8f32) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvfcvt.s.d"] @@ -661,10 +221,6 @@ unsafe extern "unadjusted" { fn __lasx_xvfclass_s(a: __v8f32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvfclass.d"] fn __lasx_xvfclass_d(a: __v4f64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvfsqrt.s"] - fn __lasx_xvfsqrt_s(a: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfsqrt.d"] - fn __lasx_xvfsqrt_d(a: __v4f64) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvfrecip.s"] fn __lasx_xvfrecip_s(a: __v8f32) -> __v8f32; #[link_name = "llvm.loongarch.lasx.xvfrecip.d"] @@ -731,16 +287,6 @@ unsafe extern "unadjusted" { fn __lasx_xvreplve_d(a: __v4i64, b: i32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvpermi.w"] fn __lasx_xvpermi_w(a: __v8i32, b: __v8i32, c: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvandn.v"] - fn __lasx_xvandn_v(a: __v32u8, b: __v32u8) -> __v32u8; - #[link_name = "llvm.loongarch.lasx.xvneg.b"] - fn __lasx_xvneg_b(a: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvneg.h"] - fn __lasx_xvneg_h(a: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvneg.w"] - fn __lasx_xvneg_w(a: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvneg.d"] - fn __lasx_xvneg_d(a: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvmuh.b"] fn __lasx_xvmuh_b(a: __v32i8, b: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.xvmuh.h"] @@ -867,22 +413,6 @@ unsafe extern "unadjusted" { fn __lasx_xvsigncov_w(a: __v8i32, b: __v8i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvsigncov.d"] fn __lasx_xvsigncov_d(a: __v4i64, b: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvfmadd.s"] - fn __lasx_xvfmadd_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfmadd.d"] - fn __lasx_xvfmadd_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfmsub.s"] - fn __lasx_xvfmsub_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfmsub.d"] - fn __lasx_xvfmsub_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfnmadd.s"] - fn __lasx_xvfnmadd_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfnmadd.d"] - fn __lasx_xvfnmadd_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64; - #[link_name = "llvm.loongarch.lasx.xvfnmsub.s"] - fn __lasx_xvfnmsub_s(a: __v8f32, b: __v8f32, c: __v8f32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvfnmsub.d"] - fn __lasx_xvfnmsub_d(a: __v4f64, b: __v4f64, c: __v4f64) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvftintrne.w.s"] fn __lasx_xvftintrne_w_s(a: __v8f32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvftintrne.l.d"] @@ -979,8 +509,6 @@ unsafe extern "unadjusted" { fn __lasx_xvssrln_h_w(a: __v8i32, b: __v8i32) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvssrln.w.d"] fn __lasx_xvssrln_w_d(a: __v4i64, b: __v4i64) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvorn.v"] - fn __lasx_xvorn_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvldi"] fn __lasx_xvldi(a: i32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvldx"] @@ -989,20 +517,6 @@ unsafe extern "unadjusted" { fn __lasx_xvstx(a: __v32i8, b: *mut i8, c: i64); #[link_name = "llvm.loongarch.lasx.xvextl.qu.du"] fn __lasx_xvextl_qu_du(a: __v4u64) -> __v4u64; - #[link_name = "llvm.loongarch.lasx.xvinsgr2vr.w"] - fn __lasx_xvinsgr2vr_w(a: __v8i32, b: i32, c: u32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvinsgr2vr.d"] - fn __lasx_xvinsgr2vr_d(a: __v4i64, b: i64, c: u32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvreplve0.b"] - fn __lasx_xvreplve0_b(a: __v32i8) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvreplve0.h"] - fn __lasx_xvreplve0_h(a: __v16i16) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvreplve0.w"] - fn __lasx_xvreplve0_w(a: __v8i32) -> __v8i32; - #[link_name = "llvm.loongarch.lasx.xvreplve0.d"] - fn __lasx_xvreplve0_d(a: __v4i64) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvreplve0.q"] - fn __lasx_xvreplve0_q(a: __v32i8) -> __v32i8; #[link_name = "llvm.loongarch.lasx.vext2xv.h.b"] fn __lasx_vext2xv_h_b(a: __v32i8) -> __v16i16; #[link_name = "llvm.loongarch.lasx.vext2xv.w.h"] @@ -1041,14 +555,6 @@ unsafe extern "unadjusted" { fn __lasx_xvldrepl_w(a: *const i8, b: i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvldrepl.d"] fn __lasx_xvldrepl_d(a: *const i8, b: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvpickve2gr.w"] - fn __lasx_xvpickve2gr_w(a: __v8i32, b: u32) -> i32; - #[link_name = "llvm.loongarch.lasx.xvpickve2gr.wu"] - fn __lasx_xvpickve2gr_wu(a: __v8i32, b: u32) -> u32; - #[link_name = "llvm.loongarch.lasx.xvpickve2gr.d"] - fn __lasx_xvpickve2gr_d(a: __v4i64, b: u32) -> i64; - #[link_name = "llvm.loongarch.lasx.xvpickve2gr.du"] - fn __lasx_xvpickve2gr_du(a: __v4i64, b: u32) -> u64; #[link_name = "llvm.loongarch.lasx.xvaddwev.q.d"] fn __lasx_xvaddwev_q_d(a: __v4i64, b: __v4i64) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvaddwev.d.w"] @@ -1483,14 +989,6 @@ unsafe extern "unadjusted" { fn __lasx_xvpickve_d_f(a: __v4f64, b: u32) -> __v4f64; #[link_name = "llvm.loongarch.lasx.xvpickve.w.f"] fn __lasx_xvpickve_w_f(a: __v8f32, b: u32) -> __v8f32; - #[link_name = "llvm.loongarch.lasx.xvrepli.b"] - fn __lasx_xvrepli_b(a: i32) -> __v32i8; - #[link_name = "llvm.loongarch.lasx.xvrepli.d"] - fn __lasx_xvrepli_d(a: i32) -> __v4i64; - #[link_name = "llvm.loongarch.lasx.xvrepli.h"] - fn __lasx_xvrepli_h(a: i32) -> __v16i16; - #[link_name = "llvm.loongarch.lasx.xvrepli.w"] - fn __lasx_xvrepli_w(a: i32) -> __v8i32; #[link_name = "llvm.loongarch.lasx.cast.128.s"] fn __lasx_cast_128_s(a: __v4f32) -> __v8f32; #[link_name = "llvm.loongarch.lasx.cast.128.d"] @@ -1532,2384 +1030,732 @@ unsafe extern "unadjusted" { #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsll_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsll_b(transmute(a), transmute(b))) } +pub fn lasx_xvsrar_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsrar_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsll_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsll_h(transmute(a), transmute(b))) } +pub fn lasx_xvsrar_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsrar_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsll_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsll_w(transmute(a), transmute(b))) } +pub fn lasx_xvsrar_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsrar_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsll_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsll_d(transmute(a), transmute(b))) } +pub fn lasx_xvsrar_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsrar_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslli_b(a: m256i) -> m256i { +pub fn lasx_xvsrari_b(a: m256i) -> m256i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvslli_b(transmute(a), IMM3)) } + unsafe { transmute(__lasx_xvsrari_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslli_h(a: m256i) -> m256i { +pub fn lasx_xvsrari_h(a: m256i) -> m256i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvslli_h(transmute(a), IMM4)) } + unsafe { transmute(__lasx_xvsrari_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslli_w(a: m256i) -> m256i { +pub fn lasx_xvsrari_w(a: m256i) -> m256i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslli_w(transmute(a), IMM5)) } + unsafe { transmute(__lasx_xvsrari_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslli_d(a: m256i) -> m256i { +pub fn lasx_xvsrari_d(a: m256i) -> m256i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvslli_d(transmute(a), IMM6)) } + unsafe { transmute(__lasx_xvsrari_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsra_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsra_b(transmute(a), transmute(b))) } +pub fn lasx_xvsrlr_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsrlr_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsra_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsra_h(transmute(a), transmute(b))) } +pub fn lasx_xvsrlr_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsrlr_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsra_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsra_w(transmute(a), transmute(b))) } +pub fn lasx_xvsrlr_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsrlr_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsra_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsra_d(transmute(a), transmute(b))) } +pub fn lasx_xvsrlr_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvsrlr_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrai_b(a: m256i) -> m256i { +pub fn lasx_xvsrlri_b(a: m256i) -> m256i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsrai_b(transmute(a), IMM3)) } + unsafe { transmute(__lasx_xvsrlri_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrai_h(a: m256i) -> m256i { +pub fn lasx_xvsrlri_h(a: m256i) -> m256i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsrai_h(transmute(a), IMM4)) } + unsafe { transmute(__lasx_xvsrlri_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrai_w(a: m256i) -> m256i { +pub fn lasx_xvsrlri_w(a: m256i) -> m256i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsrai_w(transmute(a), IMM5)) } + unsafe { transmute(__lasx_xvsrlri_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrai_d(a: m256i) -> m256i { +pub fn lasx_xvsrlri_d(a: m256i) -> m256i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsrai_d(transmute(a), IMM6)) } + unsafe { transmute(__lasx_xvsrlri_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrar_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrar_b(transmute(a), transmute(b))) } +pub fn lasx_xvbitclri_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lasx_xvbitclri_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrar_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrar_h(transmute(a), transmute(b))) } +pub fn lasx_xvbitclri_h(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lasx_xvbitclri_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrar_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrar_w(transmute(a), transmute(b))) } +pub fn lasx_xvbitclri_w(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvbitclri_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrar_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrar_d(transmute(a), transmute(b))) } +pub fn lasx_xvbitclri_d(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lasx_xvbitclri_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrari_b(a: m256i) -> m256i { +pub fn lasx_xvbitseti_b(a: m256i) -> m256i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsrari_b(transmute(a), IMM3)) } + unsafe { transmute(__lasx_xvbitseti_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrari_h(a: m256i) -> m256i { +pub fn lasx_xvbitseti_h(a: m256i) -> m256i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsrari_h(transmute(a), IMM4)) } + unsafe { transmute(__lasx_xvbitseti_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrari_w(a: m256i) -> m256i { +pub fn lasx_xvbitseti_w(a: m256i) -> m256i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsrari_w(transmute(a), IMM5)) } + unsafe { transmute(__lasx_xvbitseti_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrari_d(a: m256i) -> m256i { +pub fn lasx_xvbitseti_d(a: m256i) -> m256i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsrari_d(transmute(a), IMM6)) } + unsafe { transmute(__lasx_xvbitseti_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrl_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrl_b(transmute(a), transmute(b))) } +pub fn lasx_xvbitrevi_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lasx_xvbitrevi_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrl_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrl_h(transmute(a), transmute(b))) } +pub fn lasx_xvbitrevi_h(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lasx_xvbitrevi_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrl_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrl_w(transmute(a), transmute(b))) } +pub fn lasx_xvbitrevi_w(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvbitrevi_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrl_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrl_d(transmute(a), transmute(b))) } +pub fn lasx_xvbitrevi_d(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lasx_xvbitrevi_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrli_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsrli_b(transmute(a), IMM3)) } +pub fn lasx_xvsubi_bu(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrli_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsrli_h(transmute(a), IMM4)) } +pub fn lasx_xvsubi_hu(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrli_w(a: m256i) -> m256i { +pub fn lasx_xvsubi_wu(a: m256i) -> m256i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsrli_w(transmute(a), IMM5)) } + unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrli_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsrli_d(transmute(a), IMM6)) } +pub fn lasx_xvsubi_du(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrlr_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrlr_b(transmute(a), transmute(b))) } +pub fn lasx_xvsat_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrlr_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrlr_h(transmute(a), transmute(b))) } +pub fn lasx_xvsat_h(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrlr_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrlr_w(transmute(a), transmute(b))) } +pub fn lasx_xvsat_w(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrlr_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsrlr_d(transmute(a), transmute(b))) } +pub fn lasx_xvsat_d(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrlri_b(a: m256i) -> m256i { +pub fn lasx_xvsat_bu(a: m256i) -> m256i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsrlri_b(transmute(a), IMM3)) } + unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrlri_h(a: m256i) -> m256i { +pub fn lasx_xvsat_hu(a: m256i) -> m256i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsrlri_h(transmute(a), IMM4)) } + unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrlri_w(a: m256i) -> m256i { +pub fn lasx_xvsat_wu(a: m256i) -> m256i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsrlri_w(transmute(a), IMM5)) } + unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsrlri_d(a: m256i) -> m256i { +pub fn lasx_xvsat_du(a: m256i) -> m256i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsrlri_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclr_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitclr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclr_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitclr_h(transmute(a), transmute(b))) } + unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclr_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitclr_w(transmute(a), transmute(b))) } +pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclr_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitclr_d(transmute(a), transmute(b))) } +pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclri_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvbitclri_b(transmute(a), IMM3)) } +pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclri_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvbitclri_h(transmute(a), IMM4)) } +pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclri_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvbitclri_w(transmute(a), IMM5)) } +pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitclri_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvbitclri_d(transmute(a), IMM6)) } +pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitset_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitset_b(transmute(a), transmute(b))) } +pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitset_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitset_h(transmute(a), transmute(b))) } +pub fn lasx_xvavg_du(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavg_du(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitset_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitset_w(transmute(a), transmute(b))) } +pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitset_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitset_d(transmute(a), transmute(b))) } +pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitseti_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvbitseti_b(transmute(a), IMM3)) } +pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitseti_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvbitseti_h(transmute(a), IMM4)) } +pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitseti_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvbitseti_w(transmute(a), IMM5)) } +pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitseti_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvbitseti_d(transmute(a), IMM6)) } +pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrev_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitrev_b(transmute(a), transmute(b))) } +pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrev_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitrev_h(transmute(a), transmute(b))) } +pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrev_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitrev_w(transmute(a), transmute(b))) } +pub fn lasx_xvhaddw_h_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_h_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrev_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitrev_d(transmute(a), transmute(b))) } +pub fn lasx_xvhaddw_w_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_w_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrevi_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvbitrevi_b(transmute(a), IMM3)) } +pub fn lasx_xvhaddw_d_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_d_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrevi_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvbitrevi_h(transmute(a), IMM4)) } +pub fn lasx_xvhaddw_hu_bu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_hu_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrevi_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvbitrevi_w(transmute(a), IMM5)) } +pub fn lasx_xvhaddw_wu_hu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_wu_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitrevi_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvbitrevi_d(transmute(a), IMM6)) } +pub fn lasx_xvhaddw_du_wu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhaddw_du_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadd_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadd_b(transmute(a), transmute(b))) } +pub fn lasx_xvhsubw_h_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_h_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadd_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadd_h(transmute(a), transmute(b))) } +pub fn lasx_xvhsubw_w_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_w_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadd_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadd_w(transmute(a), transmute(b))) } +pub fn lasx_xvhsubw_d_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_d_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadd_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadd_d(transmute(a), transmute(b))) } +pub fn lasx_xvhsubw_hu_bu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_hu_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvaddi_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvaddi_bu(transmute(a), IMM5)) } +pub fn lasx_xvhsubw_wu_hu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_wu_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvaddi_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvaddi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvaddi_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvaddi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvaddi_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvaddi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsub_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsub_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsub_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsub_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsub_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsub_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsub_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsub_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsubi_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsubi_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsubi_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsubi_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmaxi_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmaxi_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmaxi_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmaxi_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmax_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmax_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmaxi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmaxi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmaxi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmaxi_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmaxi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmini_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmini_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmini_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvmini_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmin_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmin_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmini_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmini_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmini_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmini_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvmini_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseq_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvseq_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseq_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvseq_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseq_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvseq_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseq_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvseq_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseqi_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvseqi_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseqi_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvseqi_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseqi_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvseqi_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvseqi_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvseqi_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslti_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslti_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslti_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslti_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslt_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvslt_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslti_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslti_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslti_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslti_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslti_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_b(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslei_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_h(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslei_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_w(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslei_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_d(a: m256i) -> m256i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lasx_xvslei_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsle_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsle_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslei_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslei_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslei_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvslei_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvslei_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_bu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_hu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_wu(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsat_du(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadda_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadda_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadda_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadda_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadda_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadda_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvsadd_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvsadd_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavg_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavg_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvssub_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvssub_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvabsd_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvabsd_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmul_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmul_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmul_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmul_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmul_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmul_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmul_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmul_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmadd_b(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmadd_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmadd_h(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmadd_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmadd_w(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmadd_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmadd_d(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmsub_b(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmsub_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmsub_h(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmsub_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmsub_w(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmsub_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmsub_d(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvmsub_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvdiv_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvdiv_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_h_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_h_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_w_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_w_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_d_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_d_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_hu_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_hu_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_wu_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_wu_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhaddw_du_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhaddw_du_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_h_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_h_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_w_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_w_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_d_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_d_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_hu_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_hu_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_wu_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_wu_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvhsubw_du_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvhsubw_du_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_bu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_hu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_wu(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvmod_du(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvmod_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepl128vei_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lasx_xvrepl128vei_b(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepl128vei_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvrepl128vei_h(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepl128vei_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lasx_xvrepl128vei_w(transmute(a), IMM2)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepl128vei_d(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lasx_xvrepl128vei_d(transmute(a), IMM1)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickev_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickev_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickev_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickev_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickev_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickod_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickod_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickod_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickod_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpickod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvh_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvh_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvh_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvh_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvh_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvh_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvh_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvh_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvl_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvl_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvl_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvl_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvl_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvl_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvilvl_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvilvl_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackev_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackev_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackev_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackev_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackev_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackod_b(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackod_h(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackod_w(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpackod_d(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvpackod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvand_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvand_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvandi_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvor_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvori_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvnor_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvnor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvnori_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvxor_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvxor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvxori_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i { - unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvbitseli_b(a: m256i, b: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf4i_b(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvshuf4i_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf4i_h(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvshuf4i_h(transmute(a), IMM8)) } +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_xvhsubw_du_wu(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvhsubw_du_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvshuf4i_w(a: m256i) -> m256i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lasx_xvshuf4i_w(transmute(a), IMM8)) } +pub fn lasx_xvpackev_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvpackev_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplgr2vr_b(a: i32) -> m256i { - unsafe { transmute(__lasx_xvreplgr2vr_b(transmute(a))) } +pub fn lasx_xvpackev_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvpackev_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplgr2vr_h(a: i32) -> m256i { - unsafe { transmute(__lasx_xvreplgr2vr_h(transmute(a))) } +pub fn lasx_xvpackev_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvpackev_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplgr2vr_w(a: i32) -> m256i { - unsafe { transmute(__lasx_xvreplgr2vr_w(transmute(a))) } +pub fn lasx_xvpackev_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvpackev_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplgr2vr_d(a: i64) -> m256i { - unsafe { transmute(__lasx_xvreplgr2vr_d(transmute(a))) } +pub fn lasx_xvpackod_b(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvpackod_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpcnt_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvpcnt_b(transmute(a))) } +pub fn lasx_xvpackod_h(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvpackod_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpcnt_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvpcnt_h(transmute(a))) } +pub fn lasx_xvpackod_w(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvpackod_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpcnt_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvpcnt_w(transmute(a))) } +pub fn lasx_xvpackod_d(a: m256i, b: m256i) -> m256i { + unsafe { transmute(__lasx_xvpackod_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpcnt_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvpcnt_d(transmute(a))) } +pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclo_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclo_b(transmute(a))) } +pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclo_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclo_h(transmute(a))) } +pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclo_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclo_w(transmute(a))) } +pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclo_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclo_d(transmute(a))) } +pub fn lasx_xvandi_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclz_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclz_b(transmute(a))) } +pub fn lasx_xvori_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclz_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclz_h(transmute(a))) } +pub fn lasx_xvnori_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclz_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclz_w(transmute(a))) } +pub fn lasx_xvxori_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvclz_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvclz_d(transmute(a))) } +pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i { + unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfadd_s(a: m256, b: m256) -> m256 { - unsafe { transmute(__lasx_xvfadd_s(transmute(a), transmute(b))) } +pub fn lasx_xvbitseli_b(a: m256i, b: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfadd_d(a: m256d, b: m256d) -> m256d { - unsafe { transmute(__lasx_xvfadd_d(transmute(a), transmute(b))) } +pub fn lasx_xvshuf4i_b(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvshuf4i_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfsub_s(a: m256, b: m256) -> m256 { - unsafe { transmute(__lasx_xvfsub_s(transmute(a), transmute(b))) } +pub fn lasx_xvshuf4i_h(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvshuf4i_h(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfsub_d(a: m256d, b: m256d) -> m256d { - unsafe { transmute(__lasx_xvfsub_d(transmute(a), transmute(b))) } +pub fn lasx_xvshuf4i_w(a: m256i) -> m256i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lasx_xvshuf4i_w(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmul_s(a: m256, b: m256) -> m256 { - unsafe { transmute(__lasx_xvfmul_s(transmute(a), transmute(b))) } +pub fn lasx_xvclo_b(a: m256i) -> m256i { + unsafe { transmute(__lasx_xvclo_b(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmul_d(a: m256d, b: m256d) -> m256d { - unsafe { transmute(__lasx_xvfmul_d(transmute(a), transmute(b))) } +pub fn lasx_xvclo_h(a: m256i) -> m256i { + unsafe { transmute(__lasx_xvclo_h(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfdiv_s(a: m256, b: m256) -> m256 { - unsafe { transmute(__lasx_xvfdiv_s(transmute(a), transmute(b))) } +pub fn lasx_xvclo_w(a: m256i) -> m256i { + unsafe { transmute(__lasx_xvclo_w(transmute(a))) } } #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfdiv_d(a: m256d, b: m256d) -> m256d { - unsafe { transmute(__lasx_xvfdiv_d(transmute(a), transmute(b))) } +pub fn lasx_xvclo_d(a: m256i) -> m256i { + unsafe { transmute(__lasx_xvclo_d(transmute(a))) } } #[inline] @@ -3996,20 +1842,6 @@ pub fn lasx_xvfclass_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvfclass_d(transmute(a))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfsqrt_s(a: m256) -> m256 { - unsafe { transmute(__lasx_xvfsqrt_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfsqrt_d(a: m256d) -> m256d { - unsafe { transmute(__lasx_xvfsqrt_d(transmute(a))) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4243,41 +2075,6 @@ pub fn lasx_xvpermi_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpermi_w(transmute(a), transmute(b), IMM8)) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvandn_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvandn_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvneg_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvneg_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvneg_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvneg_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvneg_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvneg_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvneg_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvneg_d(transmute(a))) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4749,62 +2546,6 @@ pub fn lasx_xvsigncov_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsigncov_d(transmute(a), transmute(b))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmadd_s(a: m256, b: m256, c: m256) -> m256 { - unsafe { transmute(__lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmadd_d(a: m256d, b: m256d, c: m256d) -> m256d { - unsafe { transmute(__lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmsub_s(a: m256, b: m256, c: m256) -> m256 { - unsafe { transmute(__lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfmsub_d(a: m256d, b: m256d, c: m256d) -> m256d { - unsafe { transmute(__lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfnmadd_s(a: m256, b: m256, c: m256) -> m256 { - unsafe { transmute(__lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfnmadd_d(a: m256d, b: m256d, c: m256d) -> m256d { - unsafe { transmute(__lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfnmsub_s(a: m256, b: m256, c: m256) -> m256 { - unsafe { transmute(__lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvfnmsub_d(a: m256d, b: m256d, c: m256d) -> m256d { - unsafe { transmute(__lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c))) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5044,7 +2785,7 @@ pub unsafe fn lasx_xvld(mem_addr: *const i8) -> m256i { #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvst(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S12, 12); - transmute(__lasx_xvst(transmute(a), mem_addr, IMM_S12)) + __lasx_xvst(transmute(a), mem_addr, IMM_S12) } #[inline] @@ -5054,7 +2795,7 @@ pub unsafe fn lasx_xvst(a: m256i, mem_addr: *mut i8) { pub unsafe fn lasx_xvstelm_b(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM4, 4); - transmute(__lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)) + __lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4) } #[inline] @@ -5064,7 +2805,7 @@ pub unsafe fn lasx_xvstelm_b(a: m256i, mem_a pub unsafe fn lasx_xvstelm_h(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM3, 3); - transmute(__lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)) + __lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3) } #[inline] @@ -5074,7 +2815,7 @@ pub unsafe fn lasx_xvstelm_h(a: m256i, mem_a pub unsafe fn lasx_xvstelm_w(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM2, 2); - transmute(__lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)) + __lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2) } #[inline] @@ -5084,7 +2825,7 @@ pub unsafe fn lasx_xvstelm_w(a: m256i, mem_a pub unsafe fn lasx_xvstelm_d(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM1, 1); - transmute(__lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)) + __lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1) } #[inline] @@ -5165,13 +2906,6 @@ pub fn lasx_xvssrln_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrln_w_d(transmute(a), transmute(b))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvorn_v(a: m256i, b: m256i) -> m256i { - unsafe { transmute(__lasx_xvorn_v(transmute(a), transmute(b))) } -} - #[inline] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(0)] @@ -5192,7 +2926,7 @@ pub unsafe fn lasx_xvldx(mem_addr: *const i8, b: i64) -> m256i { #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvstx(a: m256i, mem_addr: *mut i8, b: i64) { - transmute(__lasx_xvstx(transmute(a), mem_addr, transmute(b))) + __lasx_xvstx(transmute(a), mem_addr, transmute(b)) } #[inline] @@ -5202,59 +2936,6 @@ pub fn lasx_xvextl_qu_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvextl_qu_du(transmute(a))) } } -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvinsgr2vr_w(a: m256i, b: i32) -> m256i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvinsgr2vr_w(transmute(a), transmute(b), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvinsgr2vr_d(a: m256i, b: i64) -> m256i { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lasx_xvinsgr2vr_d(transmute(a), transmute(b), IMM2)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_b(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_h(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_w(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_d(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_d(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvreplve0_q(a: m256i) -> m256i { - unsafe { transmute(__lasx_xvreplve0_q(transmute(a))) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5400,42 +3081,6 @@ pub unsafe fn lasx_xvldrepl_d(mem_addr: *const i8) -> m256i { transmute(__lasx_xvldrepl_d(mem_addr, IMM_S9)) } -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickve2gr_w(a: m256i) -> i32 { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvpickve2gr_w(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickve2gr_wu(a: m256i) -> u32 { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lasx_xvpickve2gr_wu(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickve2gr_d(a: m256i) -> i64 { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lasx_xvpickve2gr_d(transmute(a), IMM2)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvpickve2gr_du(a: m256i) -> u64 { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lasx_xvpickve2gr_du(transmute(a), IMM2)) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -7063,42 +4708,6 @@ pub fn lasx_xvpickve_w_f(a: m256) -> m256 { unsafe { transmute(__lasx_xvpickve_w_f(transmute(a), IMM3)) } } -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepli_b() -> m256i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lasx_xvrepli_b(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepli_d() -> m256i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lasx_xvrepli_d(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepli_h() -> m256i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lasx_xvrepli_h(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lasx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lasx_xvrepli_w() -> m256i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lasx_xvrepli_w(IMM_S10)) } -} - #[inline] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] diff --git a/stdarch/crates/core_arch/src/loongarch64/lasx/mod.rs b/stdarch/crates/core_arch/src/loongarch64/lasx/mod.rs index c3a244e740e9f..cc449e94924f0 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lasx/mod.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lasx/mod.rs @@ -16,6 +16,13 @@ mod generated; #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub use self::generated::*; +#[rustfmt::skip] +mod portable; + +#[rustfmt::skip] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub use self::portable::*; + #[rustfmt::skip] #[cfg(test)] mod tests; diff --git a/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs b/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs new file mode 100644 index 0000000000000..aa4144cbb4da2 --- /dev/null +++ b/stdarch/crates/core_arch/src/loongarch64/lasx/portable.rs @@ -0,0 +1,466 @@ +//! LoongArch64 LASX intrinsics - intrinsics::simd implementation + +use super::super::{simd as ls, simd::*, *}; +use crate::core_arch::simd::{self as cs, *}; +use crate::intrinsics::simd as is; +use crate::mem::transmute; + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickev_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 0, 2, 4, 6, 8, 10, 12, 14, 32, 34, 36, 38, 40, 42, 44, 46, + 16, 18, 20, 22, 24, 26, 28, 30, 48, 50, 52, 54, 56, 58, 60, 62 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickev_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 4, 2, 6]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickev_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 8, 10, 4, 6, 12, 14]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickev_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickod_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 1, 3, 5, 7, 9, 11, 13, 15, 33, 35, 37, 39, 41, 43, 45, 47, + 17, 19, 21, 23, 25, 27, 29, 31, 49, 51, 53, 55, 57, 59, 61, 63 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickod_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 5, 3, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickod_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 9, 11, 5, 7, 13, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickod_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvh_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47, + 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvh_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [4, 20, 5, 21, 6, 22, 7, 23, 12, 28, 13, 29, 14, 30, 15, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvh_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [2, 10, 3, 11, 6, 14, 7, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvh_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 5, 3, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvl_b(a: T, b: T) -> T { + simd_shuffle!( + b, + a, + [ + 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39, + 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvl_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 16, 1, 17, 2, 18, 3, 19, 8, 24, 9, 25, 10, 26, 11, 27]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvl_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 8, 1, 9, 4, 12, 5, 13]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvl_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 4, 2, 6]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_replvei_b(a: T) -> T { + simd_shuffle!( + a, + a, + [ + I, I, I, I, I, I, I, I, I, I, I, I, I, I, I, I, + I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, + I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, I + 16, I + 16 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_replvei_h(a: T) -> T { + simd_shuffle!( + a, + a, + [ + I, I, I, I, I, I, I, I, + I + 8, I + 8, I + 8, I + 8, I + 8, I + 8, I + 8, I + 8 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_replvei_w(a: T) -> T { + simd_shuffle!(a, a, [I, I, I, I, I + 4, I + 4, I + 4, I + 4]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_replvei_d(a: T) -> T { + simd_shuffle!(a, a, [I, I, I + 2, I + 2]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_replve0_b(a: T) -> T { + simd_shuffle!( + a, + a, + [ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + ] + ) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_replve0_h(a: T) -> T { + simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_replve0_w(a: T) -> T { + simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_replve0_d(a: T) -> T { + simd_shuffle!(a, a, [0, 0, 0, 0]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_replve0_q(a: T) -> T { + simd_shuffle!(a, a, [0, 1, 0, 1]) +} + +impl_vv!("lasx", lasx_xvpcnt_b, is::simd_ctpop, m256i, i8x32); +impl_vv!("lasx", lasx_xvpcnt_h, is::simd_ctpop, m256i, i16x16); +impl_vv!("lasx", lasx_xvpcnt_w, is::simd_ctpop, m256i, i32x8); +impl_vv!("lasx", lasx_xvpcnt_d, is::simd_ctpop, m256i, i64x4); +impl_vv!("lasx", lasx_xvclz_b, is::simd_ctlz, m256i, i8x32); +impl_vv!("lasx", lasx_xvclz_h, is::simd_ctlz, m256i, i16x16); +impl_vv!("lasx", lasx_xvclz_w, is::simd_ctlz, m256i, i32x8); +impl_vv!("lasx", lasx_xvclz_d, is::simd_ctlz, m256i, i64x4); +impl_vv!("lasx", lasx_xvneg_b, is::simd_neg, m256i, i8x32); +impl_vv!("lasx", lasx_xvneg_h, is::simd_neg, m256i, i16x16); +impl_vv!("lasx", lasx_xvneg_w, is::simd_neg, m256i, i32x8); +impl_vv!("lasx", lasx_xvneg_d, is::simd_neg, m256i, i64x4); +impl_vv!("lasx", lasx_xvfsqrt_s, is::simd_fsqrt, m256, f32x8); +impl_vv!("lasx", lasx_xvfsqrt_d, is::simd_fsqrt, m256d, f64x4); +impl_vv!("lasx", lasx_xvreplve0_b, simd_replve0_b, m256i, i8x32); +impl_vv!("lasx", lasx_xvreplve0_h, simd_replve0_h, m256i, i16x16); +impl_vv!("lasx", lasx_xvreplve0_w, simd_replve0_w, m256i, i32x8); +impl_vv!("lasx", lasx_xvreplve0_d, simd_replve0_d, m256i, i64x4); +impl_vv!("lasx", lasx_xvreplve0_q, simd_replve0_q, m256i, i64x4); + +impl_gv!("lasx", lasx_xvreplgr2vr_b, ls::simd_splat, m256i, i8x32, i32); +impl_gv!("lasx", lasx_xvreplgr2vr_h, ls::simd_splat, m256i, i16x16, i32); +impl_gv!("lasx", lasx_xvreplgr2vr_w, ls::simd_splat, m256i, i32x8, i32); +impl_gv!("lasx", lasx_xvreplgr2vr_d, ls::simd_splat, m256i, i64x4, i64); + +impl_sv!("lasx", lasx_xvrepli_b, ls::simd_splat, m256i, i8x32, 10); +impl_sv!("lasx", lasx_xvrepli_h, ls::simd_splat, m256i, i16x16, 10); +impl_sv!("lasx", lasx_xvrepli_w, ls::simd_splat, m256i, i32x8, 10); +impl_sv!("lasx", lasx_xvrepli_d, ls::simd_splat, m256i, i64x4, 10); + +impl_vvv!("lasx", lasx_xvadd_b, is::simd_add, m256i, i8x32); +impl_vvv!("lasx", lasx_xvadd_h, is::simd_add, m256i, i16x16); +impl_vvv!("lasx", lasx_xvadd_w, is::simd_add, m256i, i32x8); +impl_vvv!("lasx", lasx_xvadd_d, is::simd_add, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsub_b, is::simd_sub, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsub_h, is::simd_sub, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsub_w, is::simd_sub, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsub_d, is::simd_sub, m256i, i64x4); +impl_vvv!("lasx", lasx_xvmax_b, cs::simd_imax, m256i, i8x32); +impl_vvv!("lasx", lasx_xvmax_h, cs::simd_imax, m256i, i16x16); +impl_vvv!("lasx", lasx_xvmax_w, cs::simd_imax, m256i, i32x8); +impl_vvv!("lasx", lasx_xvmax_d, cs::simd_imax, m256i, i64x4); +impl_vvv!("lasx", lasx_xvmax_bu, cs::simd_imax, m256i, u8x32); +impl_vvv!("lasx", lasx_xvmax_hu, cs::simd_imax, m256i, u16x16); +impl_vvv!("lasx", lasx_xvmax_wu, cs::simd_imax, m256i, u32x8); +impl_vvv!("lasx", lasx_xvmax_du, cs::simd_imax, m256i, u64x4); +impl_vvv!("lasx", lasx_xvmin_b, cs::simd_imin, m256i, i8x32); +impl_vvv!("lasx", lasx_xvmin_h, cs::simd_imin, m256i, i16x16); +impl_vvv!("lasx", lasx_xvmin_w, cs::simd_imin, m256i, i32x8); +impl_vvv!("lasx", lasx_xvmin_d, cs::simd_imin, m256i, i64x4); +impl_vvv!("lasx", lasx_xvmin_bu, cs::simd_imin, m256i, u8x32); +impl_vvv!("lasx", lasx_xvmin_hu, cs::simd_imin, m256i, u16x16); +impl_vvv!("lasx", lasx_xvmin_wu, cs::simd_imin, m256i, u32x8); +impl_vvv!("lasx", lasx_xvmin_du, cs::simd_imin, m256i, u64x4); +impl_vvv!("lasx", lasx_xvseq_b, is::simd_eq, m256i, i8x32); +impl_vvv!("lasx", lasx_xvseq_h, is::simd_eq, m256i, i16x16); +impl_vvv!("lasx", lasx_xvseq_w, is::simd_eq, m256i, i32x8); +impl_vvv!("lasx", lasx_xvseq_d, is::simd_eq, m256i, i64x4); +impl_vvv!("lasx", lasx_xvslt_b, is::simd_lt, m256i, i8x32); +impl_vvv!("lasx", lasx_xvslt_h, is::simd_lt, m256i, i16x16); +impl_vvv!("lasx", lasx_xvslt_w, is::simd_lt, m256i, i32x8); +impl_vvv!("lasx", lasx_xvslt_d, is::simd_lt, m256i, i64x4); +impl_vvv!("lasx", lasx_xvslt_bu, is::simd_lt, m256i, u8x32); +impl_vvv!("lasx", lasx_xvslt_hu, is::simd_lt, m256i, u16x16); +impl_vvv!("lasx", lasx_xvslt_wu, is::simd_lt, m256i, u32x8); +impl_vvv!("lasx", lasx_xvslt_du, is::simd_lt, m256i, u64x4); +impl_vvv!("lasx", lasx_xvsle_b, is::simd_le, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsle_h, is::simd_le, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsle_w, is::simd_le, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsle_d, is::simd_le, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsle_bu, is::simd_le, m256i, u8x32); +impl_vvv!("lasx", lasx_xvsle_hu, is::simd_le, m256i, u16x16); +impl_vvv!("lasx", lasx_xvsle_wu, is::simd_le, m256i, u32x8); +impl_vvv!("lasx", lasx_xvsle_du, is::simd_le, m256i, u64x4); +impl_vvv!("lasx", lasx_xvmul_b, is::simd_mul, m256i, i8x32); +impl_vvv!("lasx", lasx_xvmul_h, is::simd_mul, m256i, i16x16); +impl_vvv!("lasx", lasx_xvmul_w, is::simd_mul, m256i, i32x8); +impl_vvv!("lasx", lasx_xvmul_d, is::simd_mul, m256i, i64x4); +impl_vvv!("lasx", lasx_xvdiv_b, is::simd_div, m256i, i8x32); +impl_vvv!("lasx", lasx_xvdiv_h, is::simd_div, m256i, i16x16); +impl_vvv!("lasx", lasx_xvdiv_w, is::simd_div, m256i, i32x8); +impl_vvv!("lasx", lasx_xvdiv_d, is::simd_div, m256i, i64x4); +impl_vvv!("lasx", lasx_xvdiv_bu, is::simd_div, m256i, u8x32); +impl_vvv!("lasx", lasx_xvdiv_hu, is::simd_div, m256i, u16x16); +impl_vvv!("lasx", lasx_xvdiv_wu, is::simd_div, m256i, u32x8); +impl_vvv!("lasx", lasx_xvdiv_du, is::simd_div, m256i, u64x4); +impl_vvv!("lasx", lasx_xvmod_b, is::simd_rem, m256i, i8x32); +impl_vvv!("lasx", lasx_xvmod_h, is::simd_rem, m256i, i16x16); +impl_vvv!("lasx", lasx_xvmod_w, is::simd_rem, m256i, i32x8); +impl_vvv!("lasx", lasx_xvmod_d, is::simd_rem, m256i, i64x4); +impl_vvv!("lasx", lasx_xvmod_bu, is::simd_rem, m256i, u8x32); +impl_vvv!("lasx", lasx_xvmod_hu, is::simd_rem, m256i, u16x16); +impl_vvv!("lasx", lasx_xvmod_wu, is::simd_rem, m256i, u32x8); +impl_vvv!("lasx", lasx_xvmod_du, is::simd_rem, m256i, u64x4); +impl_vvv!("lasx", lasx_xvand_v, is::simd_and, m256i, u8x32); +impl_vvv!("lasx", lasx_xvandn_v, ls::simd_andn, m256i, u8x32); +impl_vvv!("lasx", lasx_xvor_v, is::simd_or, m256i, u8x32); +impl_vvv!("lasx", lasx_xvorn_v, ls::simd_orn, m256i, u8x32); +impl_vvv!("lasx", lasx_xvnor_v, ls::simd_nor, m256i, u8x32); +impl_vvv!("lasx", lasx_xvxor_v, is::simd_xor, m256i, u8x32); +impl_vvv!("lasx", lasx_xvfadd_s, is::simd_add, m256, f32x8); +impl_vvv!("lasx", lasx_xvfadd_d, is::simd_add, m256d, f64x4); +impl_vvv!("lasx", lasx_xvfsub_s, is::simd_sub, m256, f32x8); +impl_vvv!("lasx", lasx_xvfsub_d, is::simd_sub, m256d, f64x4); +impl_vvv!("lasx", lasx_xvfmul_s, is::simd_mul, m256, f32x8); +impl_vvv!("lasx", lasx_xvfmul_d, is::simd_mul, m256d, f64x4); +impl_vvv!("lasx", lasx_xvfdiv_s, is::simd_div, m256, f32x8); +impl_vvv!("lasx", lasx_xvfdiv_d, is::simd_div, m256d, f64x4); +impl_vvv!("lasx", lasx_xvsll_b, ls::simd_shl, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsll_h, ls::simd_shl, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsll_w, ls::simd_shl, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsll_d, ls::simd_shl, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsra_b, ls::simd_shr, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsra_h, ls::simd_shr, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsra_w, ls::simd_shr, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsra_d, ls::simd_shr, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsrl_b, ls::simd_shr, m256i, u8x32); +impl_vvv!("lasx", lasx_xvsrl_h, ls::simd_shr, m256i, u16x16); +impl_vvv!("lasx", lasx_xvsrl_w, ls::simd_shr, m256i, u32x8); +impl_vvv!("lasx", lasx_xvsrl_d, ls::simd_shr, m256i, u64x4); +impl_vvv!("lasx", lasx_xvbitclr_b, ls::simd_bitclr, m256i, u8x32); +impl_vvv!("lasx", lasx_xvbitclr_h, ls::simd_bitclr, m256i, u16x16); +impl_vvv!("lasx", lasx_xvbitclr_w, ls::simd_bitclr, m256i, u32x8); +impl_vvv!("lasx", lasx_xvbitclr_d, ls::simd_bitclr, m256i, u64x4); +impl_vvv!("lasx", lasx_xvbitset_b, ls::simd_bitset, m256i, u8x32); +impl_vvv!("lasx", lasx_xvbitset_h, ls::simd_bitset, m256i, u16x16); +impl_vvv!("lasx", lasx_xvbitset_w, ls::simd_bitset, m256i, u32x8); +impl_vvv!("lasx", lasx_xvbitset_d, ls::simd_bitset, m256i, u64x4); +impl_vvv!("lasx", lasx_xvbitrev_b, ls::simd_bitrev, m256i, u8x32); +impl_vvv!("lasx", lasx_xvbitrev_h, ls::simd_bitrev, m256i, u16x16); +impl_vvv!("lasx", lasx_xvbitrev_w, ls::simd_bitrev, m256i, u32x8); +impl_vvv!("lasx", lasx_xvbitrev_d, ls::simd_bitrev, m256i, u64x4); +impl_vvv!("lasx", lasx_xvsadd_b, is::simd_saturating_add, m256i, i8x32); +impl_vvv!("lasx", lasx_xvsadd_h, is::simd_saturating_add, m256i, i16x16); +impl_vvv!("lasx", lasx_xvsadd_w, is::simd_saturating_add, m256i, i32x8); +impl_vvv!("lasx", lasx_xvsadd_d, is::simd_saturating_add, m256i, i64x4); +impl_vvv!("lasx", lasx_xvsadd_bu, is::simd_saturating_add, m256i, u8x32); +impl_vvv!("lasx", lasx_xvsadd_hu, is::simd_saturating_add, m256i, u16x16); +impl_vvv!("lasx", lasx_xvsadd_wu, is::simd_saturating_add, m256i, u32x8); +impl_vvv!("lasx", lasx_xvsadd_du, is::simd_saturating_add, m256i, u64x4); +impl_vvv!("lasx", lasx_xvssub_b, is::simd_saturating_sub, m256i, i8x32); +impl_vvv!("lasx", lasx_xvssub_h, is::simd_saturating_sub, m256i, i16x16); +impl_vvv!("lasx", lasx_xvssub_w, is::simd_saturating_sub, m256i, i32x8); +impl_vvv!("lasx", lasx_xvssub_d, is::simd_saturating_sub, m256i, i64x4); +impl_vvv!("lasx", lasx_xvssub_bu, is::simd_saturating_sub, m256i, u8x32); +impl_vvv!("lasx", lasx_xvssub_hu, is::simd_saturating_sub, m256i, u16x16); +impl_vvv!("lasx", lasx_xvssub_wu, is::simd_saturating_sub, m256i, u32x8); +impl_vvv!("lasx", lasx_xvssub_du, is::simd_saturating_sub, m256i, u64x4); +impl_vvv!("lasx", lasx_xvadda_b, ls::simd_adda, m256i, i8x32); +impl_vvv!("lasx", lasx_xvadda_h, ls::simd_adda, m256i, i16x16); +impl_vvv!("lasx", lasx_xvadda_w, ls::simd_adda, m256i, i32x8); +impl_vvv!("lasx", lasx_xvadda_d, ls::simd_adda, m256i, i64x4); +impl_vvv!("lasx", lasx_xvabsd_b, ls::simd_absd, m256i, i8x32); +impl_vvv!("lasx", lasx_xvabsd_h, ls::simd_absd, m256i, i16x16); +impl_vvv!("lasx", lasx_xvabsd_w, ls::simd_absd, m256i, i32x8); +impl_vvv!("lasx", lasx_xvabsd_d, ls::simd_absd, m256i, i64x4); +impl_vvv!("lasx", lasx_xvabsd_bu, ls::simd_absd, m256i, u8x32); +impl_vvv!("lasx", lasx_xvabsd_hu, ls::simd_absd, m256i, u16x16); +impl_vvv!("lasx", lasx_xvabsd_wu, ls::simd_absd, m256i, u32x8); +impl_vvv!("lasx", lasx_xvabsd_du, ls::simd_absd, m256i, u64x4); +impl_vvv!("lasx", lasx_xvpickev_b, simd_pickev_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvpickev_h, simd_pickev_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvpickev_w, simd_pickev_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvpickev_d, simd_pickev_d, m256i, i64x4); +impl_vvv!("lasx", lasx_xvpickod_b, simd_pickod_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvpickod_h, simd_pickod_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvpickod_w, simd_pickod_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvpickod_d, simd_pickod_d, m256i, i64x4); +impl_vvv!("lasx", lasx_xvilvh_b, simd_ilvh_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvilvh_h, simd_ilvh_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvilvh_w, simd_ilvh_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvilvh_d, simd_ilvh_d, m256i, i64x4); +impl_vvv!("lasx", lasx_xvilvl_b, simd_ilvl_b, m256i, i8x32); +impl_vvv!("lasx", lasx_xvilvl_h, simd_ilvl_h, m256i, i16x16); +impl_vvv!("lasx", lasx_xvilvl_w, simd_ilvl_w, m256i, i32x8); +impl_vvv!("lasx", lasx_xvilvl_d, simd_ilvl_d, m256i, i64x4); + +impl_vuv!("lasx", lasx_xvslli_b, is::simd_shl, m256i, i8x32); +impl_vuv!("lasx", lasx_xvslli_h, is::simd_shl, m256i, i16x16); +impl_vuv!("lasx", lasx_xvslli_w, is::simd_shl, m256i, i32x8); +impl_vuv!("lasx", lasx_xvslli_d, is::simd_shl, m256i, i64x4); +impl_vuv!("lasx", lasx_xvsrai_b, is::simd_shr, m256i, i8x32); +impl_vuv!("lasx", lasx_xvsrai_h, is::simd_shr, m256i, i16x16); +impl_vuv!("lasx", lasx_xvsrai_w, is::simd_shr, m256i, i32x8); +impl_vuv!("lasx", lasx_xvsrai_d, is::simd_shr, m256i, i64x4); +impl_vuv!("lasx", lasx_xvsrli_b, is::simd_shr, m256i, u8x32); +impl_vuv!("lasx", lasx_xvsrli_h, is::simd_shr, m256i, u16x16); +impl_vuv!("lasx", lasx_xvsrli_w, is::simd_shr, m256i, u32x8); +impl_vuv!("lasx", lasx_xvsrli_d, is::simd_shr, m256i, u64x4); +impl_vuv!("lasx", lasx_xvaddi_bu, is::simd_add, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvaddi_hu, is::simd_add, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvaddi_wu, is::simd_add, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvaddi_du, is::simd_add, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvslti_bu, is::simd_lt, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvslti_hu, is::simd_lt, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvslti_wu, is::simd_lt, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvslti_du, is::simd_lt, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvslei_bu, is::simd_le, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvslei_hu, is::simd_le, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvslei_wu, is::simd_le, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvslei_du, is::simd_le, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvmaxi_bu, cs::simd_imax, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvmaxi_hu, cs::simd_imax, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvmaxi_wu, cs::simd_imax, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvmaxi_du, cs::simd_imax, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvmini_bu, cs::simd_imin, m256i, u8x32, 5); +impl_vuv!("lasx", lasx_xvmini_hu, cs::simd_imin, m256i, u16x16, 5); +impl_vuv!("lasx", lasx_xvmini_wu, cs::simd_imin, m256i, u32x8, 5); +impl_vuv!("lasx", lasx_xvmini_du, cs::simd_imin, m256i, u64x4, 5); +impl_vuv!("lasx", lasx_xvrepl128vei_b, simd_replvei_b, m256i, i8x32, 4, const); +impl_vuv!("lasx", lasx_xvrepl128vei_h, simd_replvei_h, m256i, i16x16, 3, const); +impl_vuv!("lasx", lasx_xvrepl128vei_w, simd_replvei_w, m256i, i32x8, 2, const); +impl_vuv!("lasx", lasx_xvrepl128vei_d, simd_replvei_d, m256i, i64x4, 1, const); + +impl_vug!("lasx", lasx_xvpickve2gr_w, is::simd_extract, m256i, i32x8, i32, 3); +impl_vug!("lasx", lasx_xvpickve2gr_d, is::simd_extract, m256i, i64x4, i64, 2); +impl_vug!("lasx", lasx_xvpickve2gr_wu, is::simd_extract, m256i, u32x8, u32, 3); +impl_vug!("lasx", lasx_xvpickve2gr_du, is::simd_extract, m256i, u64x4, u64, 2); + +impl_vsv!("lasx", lasx_xvseqi_b, is::simd_eq, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvseqi_h, is::simd_eq, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvseqi_w, is::simd_eq, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvseqi_d, is::simd_eq, m256i, i64x4, 5); +impl_vsv!("lasx", lasx_xvslti_b, is::simd_lt, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvslti_h, is::simd_lt, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvslti_w, is::simd_lt, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvslti_d, is::simd_lt, m256i, i64x4, 5); +impl_vsv!("lasx", lasx_xvslei_b, is::simd_le, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvslei_h, is::simd_le, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvslei_w, is::simd_le, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvslei_d, is::simd_le, m256i, i64x4, 5); +impl_vsv!("lasx", lasx_xvmaxi_b, cs::simd_imax, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvmaxi_h, cs::simd_imax, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvmaxi_w, cs::simd_imax, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvmaxi_d, cs::simd_imax, m256i, i64x4, 5); +impl_vsv!("lasx", lasx_xvmini_b, cs::simd_imin, m256i, i8x32, 5); +impl_vsv!("lasx", lasx_xvmini_h, cs::simd_imin, m256i, i16x16, 5); +impl_vsv!("lasx", lasx_xvmini_w, cs::simd_imin, m256i, i32x8, 5); +impl_vsv!("lasx", lasx_xvmini_d, cs::simd_imin, m256i, i64x4, 5); + +impl_vvvv!("lasx", lasx_xvmadd_b, ls::simd_madd, m256i, i8x32); +impl_vvvv!("lasx", lasx_xvmadd_h, ls::simd_madd, m256i, i16x16); +impl_vvvv!("lasx", lasx_xvmadd_w, ls::simd_madd, m256i, i32x8); +impl_vvvv!("lasx", lasx_xvmadd_d, ls::simd_madd, m256i, i64x4); +impl_vvvv!("lasx", lasx_xvmsub_b, ls::simd_msub, m256i, i8x32); +impl_vvvv!("lasx", lasx_xvmsub_h, ls::simd_msub, m256i, i16x16); +impl_vvvv!("lasx", lasx_xvmsub_w, ls::simd_msub, m256i, i32x8); +impl_vvvv!("lasx", lasx_xvmsub_d, ls::simd_msub, m256i, i64x4); +impl_vvvv!("lasx", lasx_xvfmadd_s, is::simd_fma, m256, f32x8); +impl_vvvv!("lasx", lasx_xvfmadd_d, is::simd_fma, m256d, f64x4); +impl_vvvv!("lasx", lasx_xvfmsub_s, ls::simd_fmsub, m256, f32x8); +impl_vvvv!("lasx", lasx_xvfmsub_d, ls::simd_fmsub, m256d, f64x4); +impl_vvvv!("lasx", lasx_xvfnmadd_s, ls::simd_fnmadd, m256, f32x8); +impl_vvvv!("lasx", lasx_xvfnmadd_d, ls::simd_fnmadd, m256d, f64x4); +impl_vvvv!("lasx", lasx_xvfnmsub_s, ls::simd_fnmsub, m256, f32x8); +impl_vvvv!("lasx", lasx_xvfnmsub_d, ls::simd_fnmsub, m256d, f64x4); + +impl_vugv!("lasx", lasx_xvinsgr2vr_w, is::simd_insert, m256i, i32x8, i32, 3); +impl_vugv!("lasx", lasx_xvinsgr2vr_d, is::simd_insert, m256i, i64x4, i64, 2); diff --git a/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs b/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs index 319ce7cf98195..bd22d25771948 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs @@ -5,6 +5,7 @@ use crate::{ core_arch::{loongarch64::*, simd::*}, mem::transmute, }; +use std::hint::black_box; use stdarch_test::simd_test; #[simd_test(enable = "lasx")] @@ -24,7 +25,13 @@ unsafe fn test_lasx_xvsll_b() { 2882304449461665880, ); - assert_eq!(r, transmute(lasx_xvsll_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -44,7 +51,13 @@ unsafe fn test_lasx_xvsll_h() { 7061899947028838480, ); - assert_eq!(r, transmute(lasx_xvsll_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -76,7 +89,13 @@ unsafe fn test_lasx_xvsll_w() { 3598939055443673088, ); - assert_eq!(r, transmute(lasx_xvsll_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -100,7 +119,13 @@ unsafe fn test_lasx_xvsll_d() { -289787284616642560, ); - assert_eq!(r, transmute(lasx_xvsll_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -116,7 +141,7 @@ unsafe fn test_lasx_xvslli_b() { 5775955139904200724, ); - assert_eq!(r, transmute(lasx_xvslli_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -132,7 +157,7 @@ unsafe fn test_lasx_xvslli_h() { -9223160928474759168, ); - assert_eq!(r, transmute(lasx_xvslli_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -154,7 +179,7 @@ unsafe fn test_lasx_xvslli_w() { -1585267064908546048, ); - assert_eq!(r, transmute(lasx_xvslli_w::<24>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_w::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -172,7 +197,7 @@ unsafe fn test_lasx_xvslli_d() { -2305843009213693952, ); - assert_eq!(r, transmute(lasx_xvslli_d::<61>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_d::<61>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -192,7 +217,13 @@ unsafe fn test_lasx_xvsra_b() { -505532365968836077, ); - assert_eq!(r, transmute(lasx_xvsra_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -212,7 +243,13 @@ unsafe fn test_lasx_xvsra_h() { 8725659825471543, ); - assert_eq!(r, transmute(lasx_xvsra_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -244,7 +281,13 @@ unsafe fn test_lasx_xvsra_w() { -36696200575105, ); - assert_eq!(r, transmute(lasx_xvsra_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -263,7 +306,13 @@ unsafe fn test_lasx_xvsra_d() { ); let r = i64x4::new(1, -129761412875, -1, 8464978396185); - assert_eq!(r, transmute(lasx_xvsra_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -279,7 +328,7 @@ unsafe fn test_lasx_xvsrai_b() { -218421283493247239, ); - assert_eq!(r, transmute(lasx_xvsrai_b::<4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_b::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -290,7 +339,7 @@ unsafe fn test_lasx_xvsrai_h() { ); let r = i64x4::new(-281474976710658, 8589803520, -4295098367, 562941363552256); - assert_eq!(r, transmute(lasx_xvsrai_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -307,7 +356,7 @@ unsafe fn test_lasx_xvsrai_w() { ); let r = i64x4::new(68719476730, -16, 17179869169, -25769803773); - assert_eq!(r, transmute(lasx_xvsrai_w::<27>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_w::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -320,7 +369,7 @@ unsafe fn test_lasx_xvsrai_d() { ); let r = i64x4::new(-2, 2, -6, -8); - assert_eq!(r, transmute(lasx_xvsrai_d::<60>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_d::<60>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -340,7 +389,13 @@ unsafe fn test_lasx_xvsrar_b() { 302862676776648704, ); - assert_eq!(r, transmute(lasx_xvsrar_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -360,7 +415,13 @@ unsafe fn test_lasx_xvsrar_h() { -2251658079567874, ); - assert_eq!(r, transmute(lasx_xvsrar_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -392,7 +453,13 @@ unsafe fn test_lasx_xvsrar_w() { -1668156707832192, ); - assert_eq!(r, transmute(lasx_xvsrar_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -411,7 +478,13 @@ unsafe fn test_lasx_xvsrar_d() { ); let r = i64x4::new(19951225, 505, -1907248091287715676, 362); - assert_eq!(r, transmute(lasx_xvsrar_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -427,7 +500,7 @@ unsafe fn test_lasx_xvsrari_b() { 790117907428411639, ); - assert_eq!(r, transmute(lasx_xvsrari_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -443,7 +516,7 @@ unsafe fn test_lasx_xvsrari_h() { -24488623625338826, ); - assert_eq!(r, transmute(lasx_xvsrari_h::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_h::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -460,7 +533,7 @@ unsafe fn test_lasx_xvsrari_w() { ); let r = i64x4::new(-1, 4294967294, -2, -1); - assert_eq!(r, transmute(lasx_xvsrari_w::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_w::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -473,7 +546,7 @@ unsafe fn test_lasx_xvsrari_d() { ); let r = i64x4::new(-3228, 4782, -4328, -2120); - assert_eq!(r, transmute(lasx_xvsrari_d::<50>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_d::<50>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -493,7 +566,13 @@ unsafe fn test_lasx_xvsrl_b() { 3996105849293766692, ); - assert_eq!(r, transmute(lasx_xvsrl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -513,7 +592,13 @@ unsafe fn test_lasx_xvsrl_h() { 12385032119328029, ); - assert_eq!(r, transmute(lasx_xvsrl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -540,7 +625,13 @@ unsafe fn test_lasx_xvsrl_w() { ); let r = i64x4::new(3152506611213, 910538585043, 150899, 25769803779); - assert_eq!(r, transmute(lasx_xvsrl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -559,7 +650,13 @@ unsafe fn test_lasx_xvsrl_d() { ); let r = i64x4::new(22, 8215, 774027732, 338970735904462); - assert_eq!(r, transmute(lasx_xvsrl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -575,7 +672,7 @@ unsafe fn test_lasx_xvsrli_b() { 3694315145030590091, ); - assert_eq!(r, transmute(lasx_xvsrli_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -586,7 +683,7 @@ unsafe fn test_lasx_xvsrli_h() { ); let r = i64x4::new(7036883009470493, 73014771737, 38655688722, 3096241924866048); - assert_eq!(r, transmute(lasx_xvsrli_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -608,7 +705,7 @@ unsafe fn test_lasx_xvsrli_w() { 11669426172998, ); - assert_eq!(r, transmute(lasx_xvsrli_w::<17>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_w::<17>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -621,7 +718,7 @@ unsafe fn test_lasx_xvsrli_d() { ); let r = i64x4::new(16617962184, 1898365962, 5054169972, 27969530398); - assert_eq!(r, transmute(lasx_xvsrli_d::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_d::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -641,7 +738,13 @@ unsafe fn test_lasx_xvsrlr_b() { 150872911094481483, ); - assert_eq!(r, transmute(lasx_xvsrlr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -661,7 +764,13 @@ unsafe fn test_lasx_xvsrlr_h() { 565118914199555, ); - assert_eq!(r, transmute(lasx_xvsrlr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -693,7 +802,13 @@ unsafe fn test_lasx_xvsrlr_w() { 7085854838990307330, ); - assert_eq!(r, transmute(lasx_xvsrlr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -712,7 +827,13 @@ unsafe fn test_lasx_xvsrlr_d() { ); let r = i64x4::new(1801, 481878, 1923591164085, 6280495597); - assert_eq!(r, transmute(lasx_xvsrlr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -728,7 +849,7 @@ unsafe fn test_lasx_xvsrlri_b() { 2893318883870770962, ); - assert_eq!(r, transmute(lasx_xvsrlri_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -744,7 +865,7 @@ unsafe fn test_lasx_xvsrlri_h() { 32932658182619167, ); - assert_eq!(r, transmute(lasx_xvsrlri_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -761,7 +882,7 @@ unsafe fn test_lasx_xvsrlri_w() { ); let r = i64x4::new(8589934592, 8589934594, 4294967296, 8589934593); - assert_eq!(r, transmute(lasx_xvsrlri_w::<31>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_w::<31>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -779,7 +900,7 @@ unsafe fn test_lasx_xvsrlri_d() { 197693428197319479, ); - assert_eq!(r, transmute(lasx_xvsrlri_d::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_d::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -799,7 +920,13 @@ unsafe fn test_lasx_xvbitclr_b() { 2031321085346416701, ); - assert_eq!(r, transmute(lasx_xvbitclr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -819,7 +946,13 @@ unsafe fn test_lasx_xvbitclr_h() { -8417099780160452424, ); - assert_eq!(r, transmute(lasx_xvbitclr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -839,7 +972,13 @@ unsafe fn test_lasx_xvbitclr_w() { 436221668492520778, ); - assert_eq!(r, transmute(lasx_xvbitclr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -863,7 +1002,13 @@ unsafe fn test_lasx_xvbitclr_d() { 3668272799860684125, ); - assert_eq!(r, transmute(lasx_xvbitclr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -879,7 +1024,7 @@ unsafe fn test_lasx_xvbitclri_b() { 3065582154070828979, ); - assert_eq!(r, transmute(lasx_xvbitclri_b::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitclri_b::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -895,7 +1040,7 @@ unsafe fn test_lasx_xvbitclri_h() { 7727381349517352021, ); - assert_eq!(r, transmute(lasx_xvbitclri_h::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitclri_h::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -911,7 +1056,10 @@ unsafe fn test_lasx_xvbitclri_w() { -5611395396043530126, ); - assert_eq!(r, transmute(lasx_xvbitclri_w::<30>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitclri_w::<30>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -929,7 +1077,10 @@ unsafe fn test_lasx_xvbitclri_d() { -63139220754952887, ); - assert_eq!(r, transmute(lasx_xvbitclri_d::<46>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitclri_d::<46>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -949,7 +1100,13 @@ unsafe fn test_lasx_xvbitset_b() { -7702318388235109826, ); - assert_eq!(r, transmute(lasx_xvbitset_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -969,7 +1126,13 @@ unsafe fn test_lasx_xvbitset_h() { 1674099372676878223, ); - assert_eq!(r, transmute(lasx_xvbitset_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -989,7 +1152,13 @@ unsafe fn test_lasx_xvbitset_w() { -4953617511697867204, ); - assert_eq!(r, transmute(lasx_xvbitset_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1013,7 +1182,13 @@ unsafe fn test_lasx_xvbitset_d() { 8641001130845153939, ); - assert_eq!(r, transmute(lasx_xvbitset_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1029,7 +1204,7 @@ unsafe fn test_lasx_xvbitseti_b() { -3539275497407339017, ); - assert_eq!(r, transmute(lasx_xvbitseti_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitseti_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1045,7 +1220,10 @@ unsafe fn test_lasx_xvbitseti_h() { -1050847327214912781, ); - assert_eq!(r, transmute(lasx_xvbitseti_h::<13>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_h::<13>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1061,7 +1239,10 @@ unsafe fn test_lasx_xvbitseti_w() { -1933536090599238411, ); - assert_eq!(r, transmute(lasx_xvbitseti_w::<29>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_w::<29>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1079,7 +1260,10 @@ unsafe fn test_lasx_xvbitseti_d() { 7640056937583456779, ); - assert_eq!(r, transmute(lasx_xvbitseti_d::<17>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_d::<17>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1099,7 +1283,13 @@ unsafe fn test_lasx_xvbitrev_b() { 8353346322052154032, ); - assert_eq!(r, transmute(lasx_xvbitrev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1119,7 +1309,13 @@ unsafe fn test_lasx_xvbitrev_h() { 1161012008856358603, ); - assert_eq!(r, transmute(lasx_xvbitrev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1139,7 +1335,13 @@ unsafe fn test_lasx_xvbitrev_w() { 2239715596821320928, ); - assert_eq!(r, transmute(lasx_xvbitrev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1163,7 +1365,13 @@ unsafe fn test_lasx_xvbitrev_d() { -7824300689033275105, ); - assert_eq!(r, transmute(lasx_xvbitrev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1179,7 +1387,7 @@ unsafe fn test_lasx_xvbitrevi_b() { -468434338938596352, ); - assert_eq!(r, transmute(lasx_xvbitrevi_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitrevi_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1195,7 +1403,10 @@ unsafe fn test_lasx_xvbitrevi_h() { 4180481285432101679, ); - assert_eq!(r, transmute(lasx_xvbitrevi_h::<11>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_h::<11>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1211,7 +1422,10 @@ unsafe fn test_lasx_xvbitrevi_w() { -7201777846932221130, ); - assert_eq!(r, transmute(lasx_xvbitrevi_w::<30>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_w::<30>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1229,7 +1443,10 @@ unsafe fn test_lasx_xvbitrevi_d() { -1340750007927221124, ); - assert_eq!(r, transmute(lasx_xvbitrevi_d::<25>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_d::<25>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1249,7 +1466,13 @@ unsafe fn test_lasx_xvadd_b() { 39834845715162790, ); - assert_eq!(r, transmute(lasx_xvadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1269,7 +1492,13 @@ unsafe fn test_lasx_xvadd_h() { 3485514723534807729, ); - assert_eq!(r, transmute(lasx_xvadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1301,7 +1530,13 @@ unsafe fn test_lasx_xvadd_w() { 449408456544649458, ); - assert_eq!(r, transmute(lasx_xvadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1325,7 +1560,13 @@ unsafe fn test_lasx_xvadd_d() { -3333036084724254699, ); - assert_eq!(r, transmute(lasx_xvadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1341,7 +1582,7 @@ unsafe fn test_lasx_xvaddi_bu() { 1765491911008659808, ); - assert_eq!(r, transmute(lasx_xvaddi_bu::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_bu::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1357,7 +1598,7 @@ unsafe fn test_lasx_xvaddi_hu() { 4257614802810591100, ); - assert_eq!(r, transmute(lasx_xvaddi_hu::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_hu::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1379,7 +1620,7 @@ unsafe fn test_lasx_xvaddi_wu() { 8831113348648816385, ); - assert_eq!(r, transmute(lasx_xvaddi_wu::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_wu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1397,7 +1638,7 @@ unsafe fn test_lasx_xvaddi_du() { -4546559236496052074, ); - assert_eq!(r, transmute(lasx_xvaddi_du::<24>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_du::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1417,7 +1658,13 @@ unsafe fn test_lasx_xvsub_b() { -7947080804470620196, ); - assert_eq!(r, transmute(lasx_xvsub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1437,7 +1684,13 @@ unsafe fn test_lasx_xvsub_h() { -2694318201466204009, ); - assert_eq!(r, transmute(lasx_xvsub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1469,7 +1722,13 @@ unsafe fn test_lasx_xvsub_w() { -4928352995773315889, ); - assert_eq!(r, transmute(lasx_xvsub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1493,7 +1752,13 @@ unsafe fn test_lasx_xvsub_d() { -1297126209654251318, ); - assert_eq!(r, transmute(lasx_xvsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1509,7 +1774,7 @@ unsafe fn test_lasx_xvsubi_bu() { 6185872108420092159, ); - assert_eq!(r, transmute(lasx_xvsubi_bu::<13>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_bu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1525,7 +1790,7 @@ unsafe fn test_lasx_xvsubi_hu() { 1522443898558080492, ); - assert_eq!(r, transmute(lasx_xvsubi_hu::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_hu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1547,7 +1812,7 @@ unsafe fn test_lasx_xvsubi_wu() { 1285045436848317605, ); - assert_eq!(r, transmute(lasx_xvsubi_wu::<26>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_wu::<26>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1565,7 +1830,7 @@ unsafe fn test_lasx_xvsubi_du() { 4145748346670499010, ); - assert_eq!(r, transmute(lasx_xvsubi_du::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_du::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1585,7 +1850,13 @@ unsafe fn test_lasx_xvmax_b() { 8535488153625188193, ); - assert_eq!(r, transmute(lasx_xvmax_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1605,7 +1876,13 @@ unsafe fn test_lasx_xvmax_h() { -4332902052436023459, ); - assert_eq!(r, transmute(lasx_xvmax_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1637,7 +1914,13 @@ unsafe fn test_lasx_xvmax_w() { 6702174376295843649, ); - assert_eq!(r, transmute(lasx_xvmax_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1661,7 +1944,13 @@ unsafe fn test_lasx_xvmax_d() { -880822478913123851, ); - assert_eq!(r, transmute(lasx_xvmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1677,7 +1966,7 @@ unsafe fn test_lasx_xvmaxi_b() { 5914634738497113077, ); - assert_eq!(r, transmute(lasx_xvmaxi_b::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_b::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1693,7 +1982,7 @@ unsafe fn test_lasx_xvmaxi_h() { 4406209242478280693, ); - assert_eq!(r, transmute(lasx_xvmaxi_h::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_h::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1715,7 +2004,7 @@ unsafe fn test_lasx_xvmaxi_w() { 22981864337, ); - assert_eq!(r, transmute(lasx_xvmaxi_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1733,7 +2022,7 @@ unsafe fn test_lasx_xvmaxi_d() { 2429249725865673045, ); - assert_eq!(r, transmute(lasx_xvmaxi_d::<-3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_d::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1753,7 +2042,13 @@ unsafe fn test_lasx_xvmax_bu() { 4233495576175936231, ); - assert_eq!(r, transmute(lasx_xvmax_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1773,7 +2068,13 @@ unsafe fn test_lasx_xvmax_hu() { -1573457187787184228, ); - assert_eq!(r, transmute(lasx_xvmax_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1793,7 +2094,13 @@ unsafe fn test_lasx_xvmax_wu() { -7315994376096540525, ); - assert_eq!(r, transmute(lasx_xvmax_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1817,7 +2124,13 @@ unsafe fn test_lasx_xvmax_du() { 5141420152487342561, ); - assert_eq!(r, transmute(lasx_xvmax_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1833,7 +2146,7 @@ unsafe fn test_lasx_xvmaxi_bu() { -8478920119441971628, ); - assert_eq!(r, transmute(lasx_xvmaxi_bu::<10>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_bu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1849,7 +2162,7 @@ unsafe fn test_lasx_xvmaxi_hu() { 2580949584734723198, ); - assert_eq!(r, transmute(lasx_xvmaxi_hu::<15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_hu::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1865,7 +2178,7 @@ unsafe fn test_lasx_xvmaxi_wu() { 6328395255824707620, ); - assert_eq!(r, transmute(lasx_xvmaxi_wu::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_wu::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1883,7 +2196,7 @@ unsafe fn test_lasx_xvmaxi_du() { 3280369825537805033, ); - assert_eq!(r, transmute(lasx_xvmaxi_du::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_du::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1903,7 +2216,13 @@ unsafe fn test_lasx_xvmin_b() { -433018640497265418, ); - assert_eq!(r, transmute(lasx_xvmin_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1923,7 +2242,13 @@ unsafe fn test_lasx_xvmin_h() { -1753422264687927210, ); - assert_eq!(r, transmute(lasx_xvmin_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1949,7 +2274,13 @@ unsafe fn test_lasx_xvmin_w() { -710046880263550629, ); - assert_eq!(r, transmute(lasx_xvmin_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1973,7 +2304,13 @@ unsafe fn test_lasx_xvmin_d() { -3792381296290037631, ); - assert_eq!(r, transmute(lasx_xvmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1989,7 +2326,7 @@ unsafe fn test_lasx_xvmini_b() { -1088282380739546975, ); - assert_eq!(r, transmute(lasx_xvmini_b::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_b::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2005,7 +2342,7 @@ unsafe fn test_lasx_xvmini_h() { 2439077560844296, ); - assert_eq!(r, transmute(lasx_xvmini_h::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_h::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2027,7 +2364,7 @@ unsafe fn test_lasx_xvmini_w() { -3162971646443594334, ); - assert_eq!(r, transmute(lasx_xvmini_w::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_w::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2040,7 +2377,7 @@ unsafe fn test_lasx_xvmini_d() { ); let r = i64x4::new(-8, -8, -8, -8); - assert_eq!(r, transmute(lasx_xvmini_d::<-8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_d::<-8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2060,7 +2397,13 @@ unsafe fn test_lasx_xvmin_bu() { 481055128827070653, ); - assert_eq!(r, transmute(lasx_xvmin_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2080,7 +2423,13 @@ unsafe fn test_lasx_xvmin_hu() { 4690886800975071114, ); - assert_eq!(r, transmute(lasx_xvmin_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2100,7 +2449,13 @@ unsafe fn test_lasx_xvmin_wu() { 841320412252129092, ); - assert_eq!(r, transmute(lasx_xvmin_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2124,7 +2479,13 @@ unsafe fn test_lasx_xvmin_du() { 168959420679376173, ); - assert_eq!(r, transmute(lasx_xvmin_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2140,7 +2501,7 @@ unsafe fn test_lasx_xvmini_bu() { 1803156197610166553, ); - assert_eq!(r, transmute(lasx_xvmini_bu::<25>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_bu::<25>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2156,7 +2517,7 @@ unsafe fn test_lasx_xvmini_hu() { 7881419608817692, ); - assert_eq!(r, transmute(lasx_xvmini_hu::<28>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_hu::<28>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2167,7 +2528,7 @@ unsafe fn test_lasx_xvmini_wu() { ); let r = i64x4::new(94489280534, 94489280534, 94489280534, 94489280534); - assert_eq!(r, transmute(lasx_xvmini_wu::<22>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_wu::<22>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2180,7 +2541,7 @@ unsafe fn test_lasx_xvmini_du() { ); let r = i64x4::new(18, 18, 18, 18); - assert_eq!(r, transmute(lasx_xvmini_du::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_du::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2195,7 +2556,13 @@ unsafe fn test_lasx_xvseq_b() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2210,7 +2577,13 @@ unsafe fn test_lasx_xvseq_h() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2237,7 +2610,13 @@ unsafe fn test_lasx_xvseq_w() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2256,7 +2635,13 @@ unsafe fn test_lasx_xvseq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2267,7 +2652,7 @@ unsafe fn test_lasx_xvseqi_b() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2278,7 +2663,7 @@ unsafe fn test_lasx_xvseqi_h() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_h::<-8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_h::<-8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2295,7 +2680,7 @@ unsafe fn test_lasx_xvseqi_w() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_w::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_w::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2308,7 +2693,7 @@ unsafe fn test_lasx_xvseqi_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_d::<-2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_d::<-2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2328,7 +2713,13 @@ unsafe fn test_lasx_xvslt_b() { 71776119077994495, ); - assert_eq!(r, transmute(lasx_xvslt_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2348,7 +2739,13 @@ unsafe fn test_lasx_xvslt_h() { -281470681743361, ); - assert_eq!(r, transmute(lasx_xvslt_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2375,7 +2772,13 @@ unsafe fn test_lasx_xvslt_w() { ); let r = i64x4::new(4294967295, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslt_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2394,7 +2797,13 @@ unsafe fn test_lasx_xvslt_d() { ); let r = i64x4::new(0, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2410,7 +2819,7 @@ unsafe fn test_lasx_xvslti_b() { 71777218556067840, ); - assert_eq!(r, transmute(lasx_xvslti_b::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_b::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2421,7 +2830,7 @@ unsafe fn test_lasx_xvslti_h() { ); let r = i64x4::new(4294967295, -1, -281470681743361, 65535); - assert_eq!(r, transmute(lasx_xvslti_h::<-4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_h::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2438,7 +2847,7 @@ unsafe fn test_lasx_xvslti_w() { ); let r = i64x4::new(-1, 0, -4294967296, -1); - assert_eq!(r, transmute(lasx_xvslti_w::<-4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_w::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2451,7 +2860,7 @@ unsafe fn test_lasx_xvslti_d() { ); let r = i64x4::new(-1, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_d::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_d::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2466,7 +2875,13 @@ unsafe fn test_lasx_xvslt_bu() { ); let r = i64x4::new(-1095216660481, 280375465083135, -1099494915841, 16711680); - assert_eq!(r, transmute(lasx_xvslt_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2481,7 +2896,13 @@ unsafe fn test_lasx_xvslt_hu() { ); let r = i64x4::new(-281470681808896, 4294901760, -65536, 281470681808895); - assert_eq!(r, transmute(lasx_xvslt_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2496,7 +2917,13 @@ unsafe fn test_lasx_xvslt_wu() { ); let r = i64x4::new(-1, -1, -4294967296, -1); - assert_eq!(r, transmute(lasx_xvslt_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2515,7 +2942,13 @@ unsafe fn test_lasx_xvslt_du() { ); let r = i64x4::new(-1, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvslt_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2526,7 +2959,7 @@ unsafe fn test_lasx_xvslti_bu() { ); let r = i64x4::new(16711680, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_bu::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_bu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2537,7 +2970,7 @@ unsafe fn test_lasx_xvslti_hu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_hu::<13>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_hu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2548,7 +2981,7 @@ unsafe fn test_lasx_xvslti_wu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_wu::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_wu::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2561,7 +2994,7 @@ unsafe fn test_lasx_xvslti_du() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_du::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_du::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2581,7 +3014,13 @@ unsafe fn test_lasx_xvsle_b() { 1095216726015, ); - assert_eq!(r, transmute(lasx_xvsle_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2596,7 +3035,13 @@ unsafe fn test_lasx_xvsle_h() { ); let r = i64x4::new(-1, 4294901760, 4294901760, -281470681743361); - assert_eq!(r, transmute(lasx_xvsle_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2623,7 +3068,13 @@ unsafe fn test_lasx_xvsle_w() { ); let r = i64x4::new(-4294967296, 0, -1, -4294967296); - assert_eq!(r, transmute(lasx_xvsle_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2642,7 +3093,13 @@ unsafe fn test_lasx_xvsle_d() { ); let r = i64x4::new(-1, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvsle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2658,7 +3115,7 @@ unsafe fn test_lasx_xvslei_b() { 280375465148415, ); - assert_eq!(r, transmute(lasx_xvslei_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2669,7 +3126,7 @@ unsafe fn test_lasx_xvslei_h() { ); let r = i64x4::new(-65536, -4294901761, 281474976710655, -65536); - assert_eq!(r, transmute(lasx_xvslei_h::<-15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_h::<-15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2680,7 +3137,7 @@ unsafe fn test_lasx_xvslei_w() { ); let r = i64x4::new(-4294967296, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslei_w::<-3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_w::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2693,7 +3150,7 @@ unsafe fn test_lasx_xvslei_d() { ); let r = i64x4::new(-1, 0, -1, -1); - assert_eq!(r, transmute(lasx_xvslei_d::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_d::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2713,7 +3170,13 @@ unsafe fn test_lasx_xvsle_bu() { 281474976710655, ); - assert_eq!(r, transmute(lasx_xvsle_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2728,7 +3191,13 @@ unsafe fn test_lasx_xvsle_hu() { ); let r = i64x4::new(281474976645120, -4294967296, 281470681808895, 0); - assert_eq!(r, transmute(lasx_xvsle_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2743,7 +3212,13 @@ unsafe fn test_lasx_xvsle_wu() { ); let r = i64x4::new(-4294967296, -1, 0, 0); - assert_eq!(r, transmute(lasx_xvsle_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2762,7 +3237,13 @@ unsafe fn test_lasx_xvsle_du() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvsle_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2773,7 +3254,7 @@ unsafe fn test_lasx_xvslei_bu() { ); let r = i64x4::new(72056494526365440, 280375465082880, 71776119077928960, 0); - assert_eq!(r, transmute(lasx_xvslei_bu::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_bu::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2784,7 +3265,7 @@ unsafe fn test_lasx_xvslei_hu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_hu::<30>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_hu::<30>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2795,7 +3276,7 @@ unsafe fn test_lasx_xvslei_wu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_wu::<31>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_wu::<31>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2808,7 +3289,7 @@ unsafe fn test_lasx_xvslei_du() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_du::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_du::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2824,7 +3305,7 @@ unsafe fn test_lasx_xvsat_b() { 1985954429852520914, ); - assert_eq!(r, transmute(lasx_xvsat_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2840,7 +3321,7 @@ unsafe fn test_lasx_xvsat_h() { 1152903912689234618, ); - assert_eq!(r, transmute(lasx_xvsat_h::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_h::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2857,7 +3338,7 @@ unsafe fn test_lasx_xvsat_w() { ); let r = i64x4::new(-34359738361, 34359738360, -30064771080, -34359738361); - assert_eq!(r, transmute(lasx_xvsat_w::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_w::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2875,7 +3356,7 @@ unsafe fn test_lasx_xvsat_d() { 6102033771404793023, ); - assert_eq!(r, transmute(lasx_xvsat_d::<63>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_d::<63>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2891,7 +3372,7 @@ unsafe fn test_lasx_xvsat_bu() { 2539795165049929535, ); - assert_eq!(r, transmute(lasx_xvsat_bu::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_bu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2907,7 +3388,7 @@ unsafe fn test_lasx_xvsat_hu() { 1970354902204423, ); - assert_eq!(r, transmute(lasx_xvsat_hu::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_hu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2918,7 +3399,7 @@ unsafe fn test_lasx_xvsat_wu() { ); let r = i64x4::new(270582939711, 270582939711, 270582939711, 270582939711); - assert_eq!(r, transmute(lasx_xvsat_wu::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_wu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2931,7 +3412,7 @@ unsafe fn test_lasx_xvsat_du() { ); let r = i64x4::new(8796093022207, 8796093022207, 8796093022207, 8796093022207); - assert_eq!(r, transmute(lasx_xvsat_du::<42>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_du::<42>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2951,7 +3432,13 @@ unsafe fn test_lasx_xvadda_b() { -6512388827583513148, ); - assert_eq!(r, transmute(lasx_xvadda_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2971,7 +3458,13 @@ unsafe fn test_lasx_xvadda_h() { 4288196905584441792, ); - assert_eq!(r, transmute(lasx_xvadda_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2997,7 +3490,13 @@ unsafe fn test_lasx_xvadda_w() { 7114837115730115925, ); - assert_eq!(r, transmute(lasx_xvadda_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3021,7 +3520,13 @@ unsafe fn test_lasx_xvadda_d() { -3532969990801796507, ); - assert_eq!(r, transmute(lasx_xvadda_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3041,7 +3546,13 @@ unsafe fn test_lasx_xvsadd_b() { 3530119333939728429, ); - assert_eq!(r, transmute(lasx_xvsadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3061,7 +3572,13 @@ unsafe fn test_lasx_xvsadd_h() { -5137195089227040637, ); - assert_eq!(r, transmute(lasx_xvsadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3093,7 +3610,13 @@ unsafe fn test_lasx_xvsadd_w() { 6493388403303310332, ); - assert_eq!(r, transmute(lasx_xvsadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3117,7 +3640,13 @@ unsafe fn test_lasx_xvsadd_d() { -1670245304326307655, ); - assert_eq!(r, transmute(lasx_xvsadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3137,7 +3666,13 @@ unsafe fn test_lasx_xvsadd_bu() { -380207497217, ); - assert_eq!(r, transmute(lasx_xvsadd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3157,7 +3692,13 @@ unsafe fn test_lasx_xvsadd_hu() { -2766274561, ); - assert_eq!(r, transmute(lasx_xvsadd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3177,7 +3718,13 @@ unsafe fn test_lasx_xvsadd_wu() { 9110967605937569791, ); - assert_eq!(r, transmute(lasx_xvsadd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3196,7 +3743,13 @@ unsafe fn test_lasx_xvsadd_du() { ); let r = i64x4::new(-1, -7683287700352967836, -3264735658191843562, -1); - assert_eq!(r, transmute(lasx_xvsadd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3216,7 +3769,13 @@ unsafe fn test_lasx_xvavg_b() { -2451086284962613015, ); - assert_eq!(r, transmute(lasx_xvavg_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3236,7 +3795,13 @@ unsafe fn test_lasx_xvavg_h() { -6082277202109387491, ); - assert_eq!(r, transmute(lasx_xvavg_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3268,7 +3833,13 @@ unsafe fn test_lasx_xvavg_w() { -97541447405991454, ); - assert_eq!(r, transmute(lasx_xvavg_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3292,7 +3863,13 @@ unsafe fn test_lasx_xvavg_d() { 743619511763122382, ); - assert_eq!(r, transmute(lasx_xvavg_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3312,7 +3889,13 @@ unsafe fn test_lasx_xvavg_bu() { 5794025379951354001, ); - assert_eq!(r, transmute(lasx_xvavg_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3332,7 +3915,13 @@ unsafe fn test_lasx_xvavg_hu() { -3939723307751543404, ); - assert_eq!(r, transmute(lasx_xvavg_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3351,7 +3940,13 @@ unsafe fn test_lasx_xvavg_wu() { 6180173283312674740, ); - assert_eq!(r, transmute(lasx_xvavg_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3375,7 +3970,13 @@ unsafe fn test_lasx_xvavg_du() { -9048945872629561085, ); - assert_eq!(r, transmute(lasx_xvavg_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3395,7 +3996,13 @@ unsafe fn test_lasx_xvavgr_b() { -1577916506278329386, ); - assert_eq!(r, transmute(lasx_xvavgr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3415,7 +4022,13 @@ unsafe fn test_lasx_xvavgr_h() { 1044782302812228671, ); - assert_eq!(r, transmute(lasx_xvavgr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3447,7 +4060,13 @@ unsafe fn test_lasx_xvavgr_w() { 4983380877656540978, ); - assert_eq!(r, transmute(lasx_xvavgr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3471,7 +4090,13 @@ unsafe fn test_lasx_xvavgr_d() { 229317404291257478, ); - assert_eq!(r, transmute(lasx_xvavgr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3491,7 +4116,13 @@ unsafe fn test_lasx_xvavgr_bu() { 8511681618342279077, ); - assert_eq!(r, transmute(lasx_xvavgr_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3511,7 +4142,13 @@ unsafe fn test_lasx_xvavgr_hu() { -4835281559523879916, ); - assert_eq!(r, transmute(lasx_xvavgr_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3531,7 +4168,13 @@ unsafe fn test_lasx_xvavgr_wu() { 2489338192049926342, ); - assert_eq!(r, transmute(lasx_xvavgr_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3555,7 +4198,13 @@ unsafe fn test_lasx_xvavgr_du() { 6414723233875186966, ); - assert_eq!(r, transmute(lasx_xvavgr_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3575,7 +4224,13 @@ unsafe fn test_lasx_xvssub_b() { -4561472970538678093, ); - assert_eq!(r, transmute(lasx_xvssub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3595,7 +4250,13 @@ unsafe fn test_lasx_xvssub_h() { 8048307602867637285, ); - assert_eq!(r, transmute(lasx_xvssub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3627,7 +4288,13 @@ unsafe fn test_lasx_xvssub_w() { 4655436811119524629, ); - assert_eq!(r, transmute(lasx_xvssub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3651,7 +4318,13 @@ unsafe fn test_lasx_xvssub_d() { -9223372036854775808, ); - assert_eq!(r, transmute(lasx_xvssub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3671,7 +4344,13 @@ unsafe fn test_lasx_xvssub_bu() { 864691185841012929, ); - assert_eq!(r, transmute(lasx_xvssub_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3691,7 +4370,13 @@ unsafe fn test_lasx_xvssub_hu() { 188750927758467, ); - assert_eq!(r, transmute(lasx_xvssub_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3711,7 +4396,13 @@ unsafe fn test_lasx_xvssub_wu() { 3974517532346153551, ); - assert_eq!(r, transmute(lasx_xvssub_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3730,7 +4421,13 @@ unsafe fn test_lasx_xvssub_du() { ); let r = i64x4::new(1075384133325788465, 0, 8236940487074099359, 0); - assert_eq!(r, transmute(lasx_xvssub_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3750,7 +4447,13 @@ unsafe fn test_lasx_xvabsd_b() { 4109603046844106624, ); - assert_eq!(r, transmute(lasx_xvabsd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3770,7 +4473,13 @@ unsafe fn test_lasx_xvabsd_h() { 5513891007581016946, ); - assert_eq!(r, transmute(lasx_xvabsd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3802,7 +4511,13 @@ unsafe fn test_lasx_xvabsd_w() { -7014776540975538355, ); - assert_eq!(r, transmute(lasx_xvabsd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3826,7 +4541,13 @@ unsafe fn test_lasx_xvabsd_d() { 4722306005291245989, ); - assert_eq!(r, transmute(lasx_xvabsd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3846,7 +4567,13 @@ unsafe fn test_lasx_xvabsd_bu() { 1887319547440621943, ); - assert_eq!(r, transmute(lasx_xvabsd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3866,7 +4593,13 @@ unsafe fn test_lasx_xvabsd_hu() { 1864011964690965056, ); - assert_eq!(r, transmute(lasx_xvabsd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3886,7 +4619,13 @@ unsafe fn test_lasx_xvabsd_wu() { 1525979489064328670, ); - assert_eq!(r, transmute(lasx_xvabsd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3910,7 +4649,13 @@ unsafe fn test_lasx_xvabsd_du() { 2127486190004927946, ); - assert_eq!(r, transmute(lasx_xvabsd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3930,7 +4675,13 @@ unsafe fn test_lasx_xvmul_b() { -9159357540886189840, ); - assert_eq!(r, transmute(lasx_xvmul_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3950,7 +4701,13 @@ unsafe fn test_lasx_xvmul_h() { -7534790044979024262, ); - assert_eq!(r, transmute(lasx_xvmul_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3982,7 +4739,13 @@ unsafe fn test_lasx_xvmul_w() { 1142495638330554240, ); - assert_eq!(r, transmute(lasx_xvmul_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4006,7 +4769,13 @@ unsafe fn test_lasx_xvmul_d() { -3668010491661410128, ); - assert_eq!(r, transmute(lasx_xvmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4032,7 +4801,11 @@ unsafe fn test_lasx_xvmadd_b() { assert_eq!( r, - transmute(lasx_xvmadd_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4059,7 +4832,11 @@ unsafe fn test_lasx_xvmadd_h() { assert_eq!( r, - transmute(lasx_xvmadd_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4104,7 +4881,11 @@ unsafe fn test_lasx_xvmadd_w() { assert_eq!( r, - transmute(lasx_xvmadd_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4137,7 +4918,11 @@ unsafe fn test_lasx_xvmadd_d() { assert_eq!( r, - transmute(lasx_xvmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4164,7 +4949,11 @@ unsafe fn test_lasx_xvmsub_b() { assert_eq!( r, - transmute(lasx_xvmsub_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4191,7 +4980,11 @@ unsafe fn test_lasx_xvmsub_h() { assert_eq!( r, - transmute(lasx_xvmsub_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4236,7 +5029,11 @@ unsafe fn test_lasx_xvmsub_w() { assert_eq!( r, - transmute(lasx_xvmsub_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4269,7 +5066,11 @@ unsafe fn test_lasx_xvmsub_d() { assert_eq!( r, - transmute(lasx_xvmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4285,7 +5086,13 @@ unsafe fn test_lasx_xvdiv_b() { ); let r = i64x4::new(67174400, 843334041468931, 16515072, 1090921824000); - assert_eq!(r, transmute(lasx_xvdiv_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4305,7 +5112,13 @@ unsafe fn test_lasx_xvdiv_h() { -281470681939967, ); - assert_eq!(r, transmute(lasx_xvdiv_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4332,7 +5145,13 @@ unsafe fn test_lasx_xvdiv_w() { ); let r = i64x4::new(-25769803778, 4294967295, 34359738365, 1); - assert_eq!(r, transmute(lasx_xvdiv_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4351,7 +5170,13 @@ unsafe fn test_lasx_xvdiv_d() { ); let r = i64x4::new(-3, 0, -3, 0); - assert_eq!(r, transmute(lasx_xvdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4371,7 +5196,13 @@ unsafe fn test_lasx_xvdiv_bu() { 144118486677848127, ); - assert_eq!(r, transmute(lasx_xvdiv_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4386,7 +5217,13 @@ unsafe fn test_lasx_xvdiv_hu() { ); let r = i64x4::new(4295098372, 38654705665, 281474976776212, 283467841601537); - assert_eq!(r, transmute(lasx_xvdiv_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4401,7 +5238,13 @@ unsafe fn test_lasx_xvdiv_wu() { ); let r = i64x4::new(0, 1, 46, 4294967299); - assert_eq!(r, transmute(lasx_xvdiv_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4420,7 +5263,13 @@ unsafe fn test_lasx_xvdiv_du() { ); let r = i64x4::new(0, 0, 1, 6); - assert_eq!(r, transmute(lasx_xvdiv_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4440,7 +5289,13 @@ unsafe fn test_lasx_xvhaddw_h_b() { -18859072538017839, ); - assert_eq!(r, transmute(lasx_xvhaddw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4460,7 +5315,13 @@ unsafe fn test_lasx_xvhaddw_w_h() { -36597416302335, ); - assert_eq!(r, transmute(lasx_xvhaddw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4487,7 +5348,13 @@ unsafe fn test_lasx_xvhaddw_d_w() { ); let r = i64x4::new(1043954543, 64421064, -1003667433, -119821715); - assert_eq!(r, transmute(lasx_xvhaddw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4507,7 +5374,13 @@ unsafe fn test_lasx_xvhaddw_hu_bu() { 56014362196705476, ); - assert_eq!(r, transmute(lasx_xvhaddw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4527,7 +5400,13 @@ unsafe fn test_lasx_xvhaddw_wu_hu() { 392255068231306, ); - assert_eq!(r, transmute(lasx_xvhaddw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4542,7 +5421,13 @@ unsafe fn test_lasx_xvhaddw_du_wu() { ); let r = i64x4::new(2983569336, 4514288382, 2479696956, 1680431840); - assert_eq!(r, transmute(lasx_xvhaddw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4562,7 +5447,13 @@ unsafe fn test_lasx_xvhsubw_h_b() { -21955597927907350, ); - assert_eq!(r, transmute(lasx_xvhsubw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4582,7 +5473,13 @@ unsafe fn test_lasx_xvhsubw_w_h() { -108800111503156, ); - assert_eq!(r, transmute(lasx_xvhsubw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4603,7 +5500,13 @@ unsafe fn test_lasx_xvhsubw_d_w() { ); let r = i64x4::new(2748898148, -45146293, 958916832, 1285325893); - assert_eq!(r, transmute(lasx_xvhsubw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4623,7 +5526,13 @@ unsafe fn test_lasx_xvhsubw_hu_bu() { 9289103727198239, ); - assert_eq!(r, transmute(lasx_xvhsubw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4643,7 +5552,13 @@ unsafe fn test_lasx_xvhsubw_wu_hu() { 32018981198856, ); - assert_eq!(r, transmute(lasx_xvhsubw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4658,7 +5573,13 @@ unsafe fn test_lasx_xvhsubw_du_wu() { ); let r = i64x4::new(-1056733131, -2613149992, 384615677, -1588276541); - assert_eq!(r, transmute(lasx_xvhsubw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4678,7 +5599,13 @@ unsafe fn test_lasx_xvmod_b() { -48385121157714142, ); - assert_eq!(r, transmute(lasx_xvmod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4698,7 +5625,13 @@ unsafe fn test_lasx_xvmod_h() { -194216204870745003, ); - assert_eq!(r, transmute(lasx_xvmod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4723,8 +5656,14 @@ unsafe fn test_lasx_xvmod_w() { -1953977774316925897, 807808928635455307, ); - - assert_eq!(r, transmute(lasx_xvmod_w(transmute(a), transmute(b)))); + + assert_eq!( + r, + transmute(lasx_xvmod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4748,7 +5687,13 @@ unsafe fn test_lasx_xvmod_d() { -3048989907394276239, ); - assert_eq!(r, transmute(lasx_xvmod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4768,7 +5713,13 @@ unsafe fn test_lasx_xvmod_bu() { 5417620637589803790, ); - assert_eq!(r, transmute(lasx_xvmod_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4788,7 +5739,13 @@ unsafe fn test_lasx_xvmod_hu() { 129490854556368167, ); - assert_eq!(r, transmute(lasx_xvmod_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4808,7 +5765,13 @@ unsafe fn test_lasx_xvmod_wu() { 480682694340619302, ); - assert_eq!(r, transmute(lasx_xvmod_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4832,7 +5795,13 @@ unsafe fn test_lasx_xvmod_du() { 150087784552479859, ); - assert_eq!(r, transmute(lasx_xvmod_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4848,7 +5817,10 @@ unsafe fn test_lasx_xvrepl128vei_b() { 8970181431921507452, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_b::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_b::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4864,7 +5836,10 @@ unsafe fn test_lasx_xvrepl128vei_h() { -3904680457625679409, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_h::<3>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_h::<3>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4886,7 +5861,10 @@ unsafe fn test_lasx_xvrepl128vei_w() { -1327396365108239351, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_w::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_w::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4904,7 +5882,10 @@ unsafe fn test_lasx_xvrepl128vei_d() { 4427502889722976813, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_d::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_d::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4924,7 +5905,13 @@ unsafe fn test_lasx_xvpickev_b() { 4502896606534087725, ); - assert_eq!(r, transmute(lasx_xvpickev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4944,7 +5931,13 @@ unsafe fn test_lasx_xvpickev_h() { -2117051360895385090, ); - assert_eq!(r, transmute(lasx_xvpickev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4976,7 +5969,13 @@ unsafe fn test_lasx_xvpickev_w() { -4454806063744691677, ); - assert_eq!(r, transmute(lasx_xvpickev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5000,7 +5999,13 @@ unsafe fn test_lasx_xvpickev_d() { 1952973857169882715, ); - assert_eq!(r, transmute(lasx_xvpickev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5020,7 +6025,13 @@ unsafe fn test_lasx_xvpickod_b() { 4092165317489988560, ); - assert_eq!(r, transmute(lasx_xvpickod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5040,7 +6051,13 @@ unsafe fn test_lasx_xvpickod_h() { 5912677724127371711, ); - assert_eq!(r, transmute(lasx_xvpickod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5072,7 +6089,13 @@ unsafe fn test_lasx_xvpickod_w() { 14200989743342145, ); - assert_eq!(r, transmute(lasx_xvpickod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5096,7 +6119,13 @@ unsafe fn test_lasx_xvpickod_d() { 3923084493864153244, ); - assert_eq!(r, transmute(lasx_xvpickod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5116,7 +6145,13 @@ unsafe fn test_lasx_xvilvh_b() { 6070396101995813657, ); - assert_eq!(r, transmute(lasx_xvilvh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5136,7 +6171,13 @@ unsafe fn test_lasx_xvilvh_h() { 6944594579025051980, ); - assert_eq!(r, transmute(lasx_xvilvh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5168,7 +6209,13 @@ unsafe fn test_lasx_xvilvh_w() { 2557948893958412086, ); - assert_eq!(r, transmute(lasx_xvilvh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5192,7 +6239,13 @@ unsafe fn test_lasx_xvilvh_d() { -1576924492614617443, ); - assert_eq!(r, transmute(lasx_xvilvh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5212,7 +6265,13 @@ unsafe fn test_lasx_xvilvl_b() { -1661662459983806644, ); - assert_eq!(r, transmute(lasx_xvilvl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5232,7 +6291,13 @@ unsafe fn test_lasx_xvilvl_h() { -894657396213105965, ); - assert_eq!(r, transmute(lasx_xvilvl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5264,7 +6329,13 @@ unsafe fn test_lasx_xvilvl_w() { 6940426927105417163, ); - assert_eq!(r, transmute(lasx_xvilvl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5288,7 +6359,13 @@ unsafe fn test_lasx_xvilvl_d() { -2688716944239585727, ); - assert_eq!(r, transmute(lasx_xvilvl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5308,7 +6385,13 @@ unsafe fn test_lasx_xvpackev_b() { -9004682544879989266, ); - assert_eq!(r, transmute(lasx_xvpackev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5328,7 +6411,13 @@ unsafe fn test_lasx_xvpackev_h() { -5280992525495869891, ); - assert_eq!(r, transmute(lasx_xvpackev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5360,7 +6449,13 @@ unsafe fn test_lasx_xvpackev_w() { 338692385926626324, ); - assert_eq!(r, transmute(lasx_xvpackev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5384,7 +6479,13 @@ unsafe fn test_lasx_xvpackev_d() { -3601691172781761847, ); - assert_eq!(r, transmute(lasx_xvpackev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5404,7 +6505,13 @@ unsafe fn test_lasx_xvpackod_b() { 3700670962761760653, ); - assert_eq!(r, transmute(lasx_xvpackod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5424,7 +6531,13 @@ unsafe fn test_lasx_xvpackod_h() { -5523279134117035742, ); - assert_eq!(r, transmute(lasx_xvpackod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5456,7 +6569,13 @@ unsafe fn test_lasx_xvpackod_w() { -7292079267755798519, ); - assert_eq!(r, transmute(lasx_xvpackod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5480,7 +6599,13 @@ unsafe fn test_lasx_xvpackod_d() { -8628096693516187272, ); - assert_eq!(r, transmute(lasx_xvpackod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5506,7 +6631,11 @@ unsafe fn test_lasx_xvshuf_b() { assert_eq!( r, - transmute(lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5530,7 +6659,11 @@ unsafe fn test_lasx_xvshuf_h() { assert_eq!( r, - transmute(lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5566,7 +6699,11 @@ unsafe fn test_lasx_xvshuf_w() { assert_eq!( r, - transmute(lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5594,7 +6731,11 @@ unsafe fn test_lasx_xvshuf_d() { assert_eq!( r, - transmute(lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5615,7 +6756,13 @@ unsafe fn test_lasx_xvand_v() { -7998109804568426495, ); - assert_eq!(r, transmute(lasx_xvand_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvand_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5631,7 +6778,7 @@ unsafe fn test_lasx_xvandi_b() { 793492300495455493, ); - assert_eq!(r, transmute(lasx_xvandi_b::<47>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvandi_b::<47>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5651,7 +6798,13 @@ unsafe fn test_lasx_xvor_v() { -198266276987019378, ); - assert_eq!(r, transmute(lasx_xvor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5667,7 +6820,7 @@ unsafe fn test_lasx_xvori_b() { 8466485259632311926, ); - assert_eq!(r, transmute(lasx_xvori_b::<116>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvori_b::<116>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5687,7 +6840,13 @@ unsafe fn test_lasx_xvnor_v() { -8601510250130767824, ); - assert_eq!(r, transmute(lasx_xvnor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvnor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5703,7 +6862,7 @@ unsafe fn test_lasx_xvnori_b() { 6053994920729270286, ); - assert_eq!(r, transmute(lasx_xvnori_b::<161>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvnori_b::<161>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5723,7 +6882,13 @@ unsafe fn test_lasx_xvxor_v() { 4786489823605581252, ); - assert_eq!(r, transmute(lasx_xvxor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvxor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5739,7 +6904,7 @@ unsafe fn test_lasx_xvxori_b() { 1979210996964535887, ); - assert_eq!(r, transmute(lasx_xvxori_b::<179>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvxori_b::<179>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5765,7 +6930,11 @@ unsafe fn test_lasx_xvbitsel_v() { assert_eq!( r, - transmute(lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvbitsel_v( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5788,7 +6957,10 @@ unsafe fn test_lasx_xvbitseli_b() { assert_eq!( r, - transmute(lasx_xvbitseli_b::<156>(transmute(a), transmute(b))) + transmute(lasx_xvbitseli_b::<156>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5805,7 +6977,10 @@ unsafe fn test_lasx_xvshuf4i_b() { 1357573681433480718, ); - assert_eq!(r, transmute(lasx_xvshuf4i_b::<117>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvshuf4i_b::<117>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -5821,7 +6996,10 @@ unsafe fn test_lasx_xvshuf4i_h() { 4406041774853078309, ); - assert_eq!(r, transmute(lasx_xvshuf4i_h::<125>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvshuf4i_h::<125>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -5843,7 +7021,7 @@ unsafe fn test_lasx_xvshuf4i_w() { -206225345846487261, ); - assert_eq!(r, transmute(lasx_xvshuf4i_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvshuf4i_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5855,7 +7033,7 @@ unsafe fn test_lasx_xvreplgr2vr_b() { 8463800222054970741, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_b(-139770763))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_b(black_box(-139770763)))); } #[simd_test(enable = "lasx")] @@ -5867,7 +7045,7 @@ unsafe fn test_lasx_xvreplgr2vr_h() { -1100020993973555013, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_h(-111546181))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_h(black_box(-111546181)))); } #[simd_test(enable = "lasx")] @@ -5879,7 +7057,7 @@ unsafe fn test_lasx_xvreplgr2vr_w() { -8112237653938959659, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_w(-1888777515))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_w(black_box(-1888777515)))); } #[simd_test(enable = "lasx")] @@ -5891,7 +7069,10 @@ unsafe fn test_lasx_xvreplgr2vr_d() { -1472556476011894783, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_d(-1472556476011894783))); + assert_eq!( + r, + transmute(lasx_xvreplgr2vr_d(black_box(-1472556476011894783))) + ); } #[simd_test(enable = "lasx")] @@ -5907,7 +7088,7 @@ unsafe fn test_lasx_xvpcnt_b() { 288795538114413315, ); - assert_eq!(r, transmute(lasx_xvpcnt_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5923,7 +7104,7 @@ unsafe fn test_lasx_xvpcnt_h() { 2251829878980617, ); - assert_eq!(r, transmute(lasx_xvpcnt_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5940,7 +7121,7 @@ unsafe fn test_lasx_xvpcnt_w() { ); let r = i64x4::new(77309411341, 60129542155, 73014444046, 55834574863); - assert_eq!(r, transmute(lasx_xvpcnt_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5953,7 +7134,7 @@ unsafe fn test_lasx_xvpcnt_d() { ); let r = i64x4::new(33, 31, 29, 33); - assert_eq!(r, transmute(lasx_xvpcnt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5964,7 +7145,7 @@ unsafe fn test_lasx_xvclo_b() { ); let r = i64x4::new(2207613190657, 8589934592, 1103806726660, 3298568503554); - assert_eq!(r, transmute(lasx_xvclo_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5980,7 +7161,7 @@ unsafe fn test_lasx_xvclo_h() { 281479271677953, ); - assert_eq!(r, transmute(lasx_xvclo_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5997,7 +7178,7 @@ unsafe fn test_lasx_xvclo_w() { ); let r = i64x4::new(4294967299, 1, 1, 8589934593); - assert_eq!(r, transmute(lasx_xvclo_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6010,7 +7191,7 @@ unsafe fn test_lasx_xvclo_d() { ); let r = i64x4::new(2, 0, 1, 0); - assert_eq!(r, transmute(lasx_xvclo_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6021,7 +7202,7 @@ unsafe fn test_lasx_xvclz_b() { ); let r = i64x4::new(65538, 72621643502977024, 216173885920575744, 3302846693380); - assert_eq!(r, transmute(lasx_xvclz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6037,7 +7218,7 @@ unsafe fn test_lasx_xvclz_h() { 17179934721, ); - assert_eq!(r, transmute(lasx_xvclz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6054,7 +7235,7 @@ unsafe fn test_lasx_xvclz_w() { ); let r = i64x4::new(8589934592, 0, 3, 4294967296); - assert_eq!(r, transmute(lasx_xvclz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6067,7 +7248,7 @@ unsafe fn test_lasx_xvclz_d() { ); let r = i64x4::new(0, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvclz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6087,7 +7268,13 @@ unsafe fn test_lasx_xvfadd_s() { 4545553165339792015, ); - assert_eq!(r, transmute(lasx_xvfadd_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfadd_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6111,7 +7298,13 @@ unsafe fn test_lasx_xvfadd_d() { 4607242424158867483, ); - assert_eq!(r, transmute(lasx_xvfadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6131,7 +7324,13 @@ unsafe fn test_lasx_xvfsub_s() { -4716328899074058446, ); - assert_eq!(r, transmute(lasx_xvfsub_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfsub_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6155,7 +7354,13 @@ unsafe fn test_lasx_xvfsub_d() { 4602885236169716939, ); - assert_eq!(r, transmute(lasx_xvfsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6175,7 +7380,13 @@ unsafe fn test_lasx_xvfmul_s() { 4412217640780718091, ); - assert_eq!(r, transmute(lasx_xvfmul_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmul_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6199,7 +7410,13 @@ unsafe fn test_lasx_xvfmul_d() { 4604645288864682176, ); - assert_eq!(r, transmute(lasx_xvfmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6219,7 +7436,13 @@ unsafe fn test_lasx_xvfdiv_s() { 4544549637634302505, ); - assert_eq!(r, transmute(lasx_xvfdiv_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfdiv_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6243,7 +7466,13 @@ unsafe fn test_lasx_xvfdiv_d() { 4608170208670026319, ); - assert_eq!(r, transmute(lasx_xvfdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6263,7 +7492,13 @@ unsafe fn test_lasx_xvfcvt_h_s() { 4182498428240214789, ); - assert_eq!(r, transmute(lasx_xvfcvt_h_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcvt_h_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6287,7 +7522,13 @@ unsafe fn test_lasx_xvfcvt_s_d() { 4509540616169896248, ); - assert_eq!(r, transmute(lasx_xvfcvt_s_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcvt_s_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6307,7 +7548,13 @@ unsafe fn test_lasx_xvfmin_s() { 4470137692837414470, ); - assert_eq!(r, transmute(lasx_xvfmin_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmin_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6331,7 +7578,13 @@ unsafe fn test_lasx_xvfmin_d() { 4596668800324369880, ); - assert_eq!(r, transmute(lasx_xvfmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6351,7 +7604,13 @@ unsafe fn test_lasx_xvfmina_s() { 4561809912873379512, ); - assert_eq!(r, transmute(lasx_xvfmina_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmina_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6375,7 +7634,13 @@ unsafe fn test_lasx_xvfmina_d() { 4597161583916257152, ); - assert_eq!(r, transmute(lasx_xvfmina_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmina_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6395,7 +7660,13 @@ unsafe fn test_lasx_xvfmax_s() { 4574742780979947531, ); - assert_eq!(r, transmute(lasx_xvfmax_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmax_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6419,7 +7690,13 @@ unsafe fn test_lasx_xvfmax_d() { 4602928137069840177, ); - assert_eq!(r, transmute(lasx_xvfmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6439,7 +7716,13 @@ unsafe fn test_lasx_xvfmaxa_s() { 4527767521076114844, ); - assert_eq!(r, transmute(lasx_xvfmaxa_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmaxa_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6463,7 +7746,13 @@ unsafe fn test_lasx_xvfmaxa_d() { 4596362093665607644, ); - assert_eq!(r, transmute(lasx_xvfmaxa_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmaxa_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6474,7 +7763,7 @@ unsafe fn test_lasx_xvfclass_s() { ); let r = i64x4::new(549755814016, 549755814016, 549755814016, 549755814016); - assert_eq!(r, transmute(lasx_xvfclass_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfclass_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6487,7 +7776,7 @@ unsafe fn test_lasx_xvfclass_d() { ); let r = i64x4::new(128, 128, 128, 128); - assert_eq!(r, transmute(lasx_xvfclass_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfclass_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6503,7 +7792,7 @@ unsafe fn test_lasx_xvfsqrt_s() { 4566109703441416989, ); - assert_eq!(r, transmute(lasx_xvfsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6521,7 +7810,7 @@ unsafe fn test_lasx_xvfsqrt_d() { 4601138545884238765, ); - assert_eq!(r, transmute(lasx_xvfsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6537,7 +7826,7 @@ unsafe fn test_lasx_xvfrecip_s() { 4585242601638738136, ); - assert_eq!(r, transmute(lasx_xvfrecip_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecip_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6555,7 +7844,7 @@ unsafe fn test_lasx_xvfrecip_d() { 4611482062367896141, ); - assert_eq!(r, transmute(lasx_xvfrecip_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecip_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6571,7 +7860,7 @@ unsafe fn test_lasx_xvfrecipe_s() { 4728509413412007938, ); - assert_eq!(r, transmute(lasx_xvfrecipe_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecipe_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6589,7 +7878,7 @@ unsafe fn test_lasx_xvfrecipe_d() { 4611499011256352768, ); - assert_eq!(r, transmute(lasx_xvfrecipe_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecipe_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6605,7 +7894,7 @@ unsafe fn test_lasx_xvfrsqrte_s() { 4612427253546066334, ); - assert_eq!(r, transmute(lasx_xvfrsqrte_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrte_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6623,7 +7912,7 @@ unsafe fn test_lasx_xvfrsqrte_d() { 4612346183891812352, ); - assert_eq!(r, transmute(lasx_xvfrsqrte_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrte_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6634,7 +7923,7 @@ unsafe fn test_lasx_xvfrint_s() { ); let r = i64x4::new(0, 4575657222473777152, 1065353216, 4575657222473777152); - assert_eq!(r, transmute(lasx_xvfrint_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrint_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6652,7 +7941,7 @@ unsafe fn test_lasx_xvfrint_d() { 0, ); - assert_eq!(r, transmute(lasx_xvfrint_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrint_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6668,7 +7957,7 @@ unsafe fn test_lasx_xvfrsqrt_s() { 4651901116840286347, ); - assert_eq!(r, transmute(lasx_xvfrsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6686,7 +7975,7 @@ unsafe fn test_lasx_xvfrsqrt_d() { 4612495411087822923, ); - assert_eq!(r, transmute(lasx_xvfrsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6702,7 +7991,7 @@ unsafe fn test_lasx_xvflogb_s() { -4575657218195587072, ); - assert_eq!(r, transmute(lasx_xvflogb_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvflogb_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6720,7 +8009,7 @@ unsafe fn test_lasx_xvflogb_d() { -4616189618054758400, ); - assert_eq!(r, transmute(lasx_xvflogb_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvflogb_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6736,7 +8025,7 @@ unsafe fn test_lasx_xvfcvth_s_h() { 4931511963987271680, ); - assert_eq!(r, transmute(lasx_xvfcvth_s_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvth_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6752,7 +8041,7 @@ unsafe fn test_lasx_xvfcvth_d_s() { 4605684912954015744, ); - assert_eq!(r, transmute(lasx_xvfcvth_d_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvth_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6768,7 +8057,7 @@ unsafe fn test_lasx_xvfcvtl_s_h() { 4719033540912152576, ); - assert_eq!(r, transmute(lasx_xvfcvtl_s_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvtl_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6784,7 +8073,7 @@ unsafe fn test_lasx_xvfcvtl_d_s() { 4598772185639682048, ); - assert_eq!(r, transmute(lasx_xvfcvtl_d_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvtl_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6795,7 +8084,7 @@ unsafe fn test_lasx_xvftint_w_s() { ); let r = i64x4::new(0, 0, 1, 0); - assert_eq!(r, transmute(lasx_xvftint_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6808,7 +8097,7 @@ unsafe fn test_lasx_xvftint_l_d() { ); let r = i64x4::new(0, 0, 1, 1); - assert_eq!(r, transmute(lasx_xvftint_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6819,7 +8108,7 @@ unsafe fn test_lasx_xvftint_wu_s() { ); let r = i64x4::new(1, 4294967297, 1, 4294967297); - assert_eq!(r, transmute(lasx_xvftint_wu_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6832,7 +8121,7 @@ unsafe fn test_lasx_xvftint_lu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftint_lu_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6843,7 +8132,7 @@ unsafe fn test_lasx_xvftintrz_w_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6856,7 +8145,7 @@ unsafe fn test_lasx_xvftintrz_l_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6867,7 +8156,7 @@ unsafe fn test_lasx_xvftintrz_wu_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_wu_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6880,7 +8169,7 @@ unsafe fn test_lasx_xvftintrz_lu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_lu_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6902,7 +8191,7 @@ unsafe fn test_lasx_xvffint_s_w() { 5669248528000103797, ); - assert_eq!(r, transmute(lasx_xvffint_s_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_s_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6920,7 +8209,7 @@ unsafe fn test_lasx_xvffint_d_l() { -4362160337941248997, ); - assert_eq!(r, transmute(lasx_xvffint_d_l(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_d_l(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6936,7 +8225,7 @@ unsafe fn test_lasx_xvffint_s_wu() { 5723492283472660471, ); - assert_eq!(r, transmute(lasx_xvffint_s_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_s_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6954,7 +8243,7 @@ unsafe fn test_lasx_xvffint_d_lu() { 4892265567869239358, ); - assert_eq!(r, transmute(lasx_xvffint_d_lu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_d_lu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6970,7 +8259,7 @@ unsafe fn test_lasx_xvreplve_b() { -5280832617179597130, ); - assert_eq!(r, transmute(lasx_xvreplve_b(transmute(a), 5))); + assert_eq!(r, transmute(lasx_xvreplve_b(black_box(transmute(a)), 5))); } #[simd_test(enable = "lasx")] @@ -6986,7 +8275,7 @@ unsafe fn test_lasx_xvreplve_h() { -8907411554322709406, ); - assert_eq!(r, transmute(lasx_xvreplve_h(transmute(a), -5))); + assert_eq!(r, transmute(lasx_xvreplve_h(black_box(transmute(a)), -5))); } #[simd_test(enable = "lasx")] @@ -7008,7 +8297,7 @@ unsafe fn test_lasx_xvreplve_w() { -2569718735257041300, ); - assert_eq!(r, transmute(lasx_xvreplve_w(transmute(a), 1))); + assert_eq!(r, transmute(lasx_xvreplve_w(black_box(transmute(a)), 1))); } #[simd_test(enable = "lasx")] @@ -7026,7 +8315,7 @@ unsafe fn test_lasx_xvreplve_d() { -7945890434069746992, ); - assert_eq!(r, transmute(lasx_xvreplve_d(transmute(a), -6))); + assert_eq!(r, transmute(lasx_xvreplve_d(black_box(transmute(a)), -6))); } #[simd_test(enable = "lasx")] @@ -7060,7 +8349,10 @@ unsafe fn test_lasx_xvpermi_w() { assert_eq!( r, - transmute(lasx_xvpermi_w::<217>(transmute(a), transmute(b))) + transmute(lasx_xvpermi_w::<217>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -7081,7 +8373,13 @@ unsafe fn test_lasx_xvandn_v() { 5350223724150917, ); - assert_eq!(r, transmute(lasx_xvandn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvandn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7097,7 +8395,7 @@ unsafe fn test_lasx_xvneg_b() { -5388239603749330053, ); - assert_eq!(r, transmute(lasx_xvneg_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7113,7 +8411,7 @@ unsafe fn test_lasx_xvneg_h() { 5510114370614593991, ); - assert_eq!(r, transmute(lasx_xvneg_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7135,7 +8433,7 @@ unsafe fn test_lasx_xvneg_w() { -6240794077010148150, ); - assert_eq!(r, transmute(lasx_xvneg_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7153,7 +8451,7 @@ unsafe fn test_lasx_xvneg_d() { -906750919774206543, ); - assert_eq!(r, transmute(lasx_xvneg_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7173,7 +8471,13 @@ unsafe fn test_lasx_xvmuh_b() { 131228860074087168, ); - assert_eq!(r, transmute(lasx_xvmuh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7193,7 +8497,13 @@ unsafe fn test_lasx_xvmuh_h() { -14890625691814142, ); - assert_eq!(r, transmute(lasx_xvmuh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7225,7 +8535,13 @@ unsafe fn test_lasx_xvmuh_w() { 15710306989437773, ); - assert_eq!(r, transmute(lasx_xvmuh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7249,7 +8565,13 @@ unsafe fn test_lasx_xvmuh_d() { 273863514955286020, ); - assert_eq!(r, transmute(lasx_xvmuh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7268,8 +8590,14 @@ unsafe fn test_lasx_xvmuh_bu() { 4579080056940291892, 442221464076014683, ); - - assert_eq!(r, transmute(lasx_xvmuh_bu(transmute(a), transmute(b)))); + + assert_eq!( + r, + transmute(lasx_xvmuh_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7289,7 +8617,13 @@ unsafe fn test_lasx_xvmuh_hu() { 108786773599653576, ); - assert_eq!(r, transmute(lasx_xvmuh_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7309,7 +8643,13 @@ unsafe fn test_lasx_xvmuh_wu() { 3278999485098399815, ); - assert_eq!(r, transmute(lasx_xvmuh_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7333,7 +8673,13 @@ unsafe fn test_lasx_xvmuh_du() { 1569823798457591419, ); - assert_eq!(r, transmute(lasx_xvmuh_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7349,7 +8695,10 @@ unsafe fn test_lasx_xvsllwil_h_b() { 283732621893107440, ); - assert_eq!(r, transmute(lasx_xvsllwil_h_b::<4>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_h_b::<4>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7365,7 +8714,10 @@ unsafe fn test_lasx_xvsllwil_w_h() { -19087521822982144, ); - assert_eq!(r, transmute(lasx_xvsllwil_w_h::<11>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_w_h::<11>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7387,7 +8739,10 @@ unsafe fn test_lasx_xvsllwil_d_w() { -21769464725504, ); - assert_eq!(r, transmute(lasx_xvsllwil_d_w::<14>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_d_w::<14>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7403,7 +8758,10 @@ unsafe fn test_lasx_xvsllwil_hu_bu() { 180156217344131904, ); - assert_eq!(r, transmute(lasx_xvsllwil_hu_bu::<5>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_hu_bu::<5>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7419,7 +8777,10 @@ unsafe fn test_lasx_xvsllwil_wu_hu() { 3493526673607606272, ); - assert_eq!(r, transmute(lasx_xvsllwil_wu_hu::<14>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_wu_hu::<14>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7435,7 +8796,10 @@ unsafe fn test_lasx_xvsllwil_du_wu() { 147522340803051520, ); - assert_eq!(r, transmute(lasx_xvsllwil_du_wu::<28>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_du_wu::<28>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7450,7 +8814,13 @@ unsafe fn test_lasx_xvsran_b_h() { ); let r = i64x4::new(-5107013816536599300, 0, -576745268203292981, 0); - assert_eq!(r, transmute(lasx_xvsran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7477,7 +8847,13 @@ unsafe fn test_lasx_xvsran_h_w() { ); let r = i64x4::new(-7492863874014043255, 0, -5145548381371170633, 0); - assert_eq!(r, transmute(lasx_xvsran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7496,7 +8872,13 @@ unsafe fn test_lasx_xvsran_w_d() { ); let r = i64x4::new(58054624080, 0, 1863787881113495402, 0); - assert_eq!(r, transmute(lasx_xvsran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7511,7 +8893,13 @@ unsafe fn test_lasx_xvssran_b_h() { ); let r = i64x4::new(179865806513864501, 0, -9222296776751415043, 0); - assert_eq!(r, transmute(lasx_xvssran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7538,7 +8926,13 @@ unsafe fn test_lasx_xvssran_h_w() { ); let r = i64x4::new(281015415144451, 0, 281472829161978, 0); - assert_eq!(r, transmute(lasx_xvssran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7557,7 +8951,13 @@ unsafe fn test_lasx_xvssran_w_d() { ); let r = i64x4::new(-109363692856335914, 0, -713658208354305, 0); - assert_eq!(r, transmute(lasx_xvssran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7572,7 +8972,13 @@ unsafe fn test_lasx_xvssran_bu_h() { ); let r = i64x4::new(144116287595479055, 0, 71776131929997312, 0); - assert_eq!(r, transmute(lasx_xvssran_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7587,7 +8993,13 @@ unsafe fn test_lasx_xvssran_hu_w() { ); let r = i64x4::new(254837589540863, 0, 281470681765343, 0); - assert_eq!(r, transmute(lasx_xvssran_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7606,7 +9018,13 @@ unsafe fn test_lasx_xvssran_wu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvssran_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7621,7 +9039,13 @@ unsafe fn test_lasx_xvsrarn_b_h() { ); let r = i64x4::new(-7204067930850651184, 0, -5909457163402939758, 0); - assert_eq!(r, transmute(lasx_xvsrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7648,7 +9072,13 @@ unsafe fn test_lasx_xvsrarn_h_w() { ); let r = i64x4::new(4021320339558432771, 0, -5499970420202995712, 0); - assert_eq!(r, transmute(lasx_xvsrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7667,7 +9097,13 @@ unsafe fn test_lasx_xvsrarn_w_d() { ); let r = i64x4::new(-69752906595470, 0, -7240468610764767136, 0); - assert_eq!(r, transmute(lasx_xvsrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7682,7 +9118,13 @@ unsafe fn test_lasx_xvssrarn_b_h() { ); let r = i64x4::new(142413695971000447, 0, -141179869986524, 0); - assert_eq!(r, transmute(lasx_xvssrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7709,7 +9151,13 @@ unsafe fn test_lasx_xvssrarn_h_w() { ); let r = i64x4::new(-10414028872220672, 0, 9223104806137135104, 0); - assert_eq!(r, transmute(lasx_xvssrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7728,7 +9176,13 @@ unsafe fn test_lasx_xvssrarn_w_d() { ); let r = i64x4::new(2147483648, 0, 326062786704572415, 0); - assert_eq!(r, transmute(lasx_xvssrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7743,7 +9197,13 @@ unsafe fn test_lasx_xvssrarn_bu_h() { ); let r = i64x4::new(4286578689, 0, 8163878114427135, 0); - assert_eq!(r, transmute(lasx_xvssrarn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7758,7 +9218,13 @@ unsafe fn test_lasx_xvssrarn_hu_w() { ); let r = i64x4::new(-281474976710656, 0, 2199023255552, 0); - assert_eq!(r, transmute(lasx_xvssrarn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7777,7 +9243,13 @@ unsafe fn test_lasx_xvssrarn_wu_d() { ); let r = i64x4::new(-3539373509, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvssrarn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7792,7 +9264,13 @@ unsafe fn test_lasx_xvsrln_b_h() { ); let r = i64x4::new(776589499955319005, 0, 285495199351976, 0); - assert_eq!(r, transmute(lasx_xvsrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7819,7 +9297,13 @@ unsafe fn test_lasx_xvsrln_h_w() { ); let r = i64x4::new(-6090306652816735409, 0, -1175228277373752196, 0); - assert_eq!(r, transmute(lasx_xvsrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7838,7 +9322,13 @@ unsafe fn test_lasx_xvsrln_w_d() { ); let r = i64x4::new(262796920316080678, 0, 1866060245111069, 0); - assert_eq!(r, transmute(lasx_xvsrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7853,7 +9343,13 @@ unsafe fn test_lasx_xvssrln_bu_h() { ); let r = i64x4::new(-996419305685, 0, -71773920038018305, 0); - assert_eq!(r, transmute(lasx_xvssrln_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7867,7 +9363,13 @@ unsafe fn test_lasx_xvssrln_hu_w() { ); let r = i64x4::new(2319476961249468, 0, 208855326080470286, 0); - assert_eq!(r, transmute(lasx_xvssrln_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7886,7 +9388,13 @@ unsafe fn test_lasx_xvssrln_wu_d() { ); let r = i64x4::new(-1, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvssrln_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7901,7 +9409,13 @@ unsafe fn test_lasx_xvsrlrn_b_h() { ); let r = i64x4::new(-6693460433276960310, 0, -6122543899663285619, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7928,7 +9442,13 @@ unsafe fn test_lasx_xvsrlrn_h_w() { ); let r = i64x4::new(390723813551243448, 0, 6015496732136052023, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7947,7 +9467,13 @@ unsafe fn test_lasx_xvsrlrn_w_d() { ); let r = i64x4::new(4295025675, 0, -3281590872273059757, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7962,7 +9488,13 @@ unsafe fn test_lasx_xvssrlrn_bu_h() { ); let r = i64x4::new(-258385232527491, 0, 4034951496335359804, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7977,7 +9509,13 @@ unsafe fn test_lasx_xvssrlrn_hu_w() { ); let r = i64x4::new(-3854303052, 0, -4029743103, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7996,7 +9534,13 @@ unsafe fn test_lasx_xvssrlrn_wu_d() { ); let r = i64x4::new(-3223981555, 0, 35952127557763071, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8018,7 +9562,10 @@ unsafe fn test_lasx_xvfrstpi_b() { assert_eq!( r, - transmute(lasx_xvfrstpi_b::<24>(transmute(a), transmute(b))) + transmute(lasx_xvfrstpi_b::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8041,7 +9588,10 @@ unsafe fn test_lasx_xvfrstpi_h() { assert_eq!( r, - transmute(lasx_xvfrstpi_h::<10>(transmute(a), transmute(b))) + transmute(lasx_xvfrstpi_h::<10>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8068,7 +9618,11 @@ unsafe fn test_lasx_xvfrstp_b() { assert_eq!( r, - transmute(lasx_xvfrstp_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfrstp_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8095,7 +9649,11 @@ unsafe fn test_lasx_xvfrstp_h() { assert_eq!( r, - transmute(lasx_xvfrstp_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfrstp_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8122,7 +9680,10 @@ unsafe fn test_lasx_xvshuf4i_d() { assert_eq!( r, - transmute(lasx_xvshuf4i_d::<115>(transmute(a), transmute(b))) + transmute(lasx_xvshuf4i_d::<115>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8139,7 +9700,7 @@ unsafe fn test_lasx_xvbsrl_v() { 8842437361645499941, ); - assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8155,7 +9716,7 @@ unsafe fn test_lasx_xvbsll_v() { 5030360181484275352, ); - assert_eq!(r, transmute(lasx_xvbsll_v::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbsll_v::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8177,7 +9738,10 @@ unsafe fn test_lasx_xvextrins_b() { assert_eq!( r, - transmute(lasx_xvextrins_b::<69>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_b::<69>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8200,7 +9764,10 @@ unsafe fn test_lasx_xvextrins_h() { assert_eq!( r, - transmute(lasx_xvextrins_h::<190>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_h::<190>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8235,7 +9802,10 @@ unsafe fn test_lasx_xvextrins_w() { assert_eq!( r, - transmute(lasx_xvextrins_w::<133>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_w::<133>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8262,7 +9832,10 @@ unsafe fn test_lasx_xvextrins_d() { assert_eq!( r, - transmute(lasx_xvextrins_d::<210>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_d::<210>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8274,7 +9847,7 @@ unsafe fn test_lasx_xvmskltz_b() { ); let r = i64x4::new(5684, 0, 36244, 0); - assert_eq!(r, transmute(lasx_xvmskltz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8285,7 +9858,7 @@ unsafe fn test_lasx_xvmskltz_h() { ); let r = i64x4::new(225, 0, 96, 0); - assert_eq!(r, transmute(lasx_xvmskltz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8302,7 +9875,7 @@ unsafe fn test_lasx_xvmskltz_w() { ); let r = i64x4::new(13, 0, 10, 0); - assert_eq!(r, transmute(lasx_xvmskltz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8315,7 +9888,7 @@ unsafe fn test_lasx_xvmskltz_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvmskltz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8335,7 +9908,13 @@ unsafe fn test_lasx_xvsigncov_b() { -6215157037026399088, ); - assert_eq!(r, transmute(lasx_xvsigncov_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8355,7 +9934,13 @@ unsafe fn test_lasx_xvsigncov_h() { 2866604565619890601, ); - assert_eq!(r, transmute(lasx_xvsigncov_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8387,7 +9972,13 @@ unsafe fn test_lasx_xvsigncov_w() { -180354238538399451, ); - assert_eq!(r, transmute(lasx_xvsigncov_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8411,7 +10002,13 @@ unsafe fn test_lasx_xvsigncov_d() { 293290471183495768, ); - assert_eq!(r, transmute(lasx_xvsigncov_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8437,7 +10034,11 @@ unsafe fn test_lasx_xvfmadd_s() { assert_eq!( r, - transmute(lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8470,7 +10071,11 @@ unsafe fn test_lasx_xvfmadd_d() { assert_eq!( r, - transmute(lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8497,7 +10102,11 @@ unsafe fn test_lasx_xvfmsub_s() { assert_eq!( r, - transmute(lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8530,7 +10139,11 @@ unsafe fn test_lasx_xvfmsub_d() { assert_eq!( r, - transmute(lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8557,7 +10170,11 @@ unsafe fn test_lasx_xvfnmadd_s() { assert_eq!( r, - transmute(lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8590,7 +10207,11 @@ unsafe fn test_lasx_xvfnmadd_d() { assert_eq!( r, - transmute(lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8617,7 +10238,11 @@ unsafe fn test_lasx_xvfnmsub_s() { assert_eq!( r, - transmute(lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8650,7 +10275,11 @@ unsafe fn test_lasx_xvfnmsub_d() { assert_eq!( r, - transmute(lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8662,7 +10291,7 @@ unsafe fn test_lasx_xvftintrne_w_s() { ); let r = i64x4::new(1, 0, 1, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrne_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrne_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8675,7 +10304,7 @@ unsafe fn test_lasx_xvftintrne_l_d() { ); let r = i64x4::new(0, 1, 1, 0); - assert_eq!(r, transmute(lasx_xvftintrne_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrne_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8686,7 +10315,7 @@ unsafe fn test_lasx_xvftintrp_w_s() { ); let r = i64x4::new(4294967297, 4294967297, 4294967297, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrp_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrp_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8699,7 +10328,7 @@ unsafe fn test_lasx_xvftintrp_l_d() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrp_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrp_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8710,7 +10339,7 @@ unsafe fn test_lasx_xvftintrm_w_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrm_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8723,7 +10352,7 @@ unsafe fn test_lasx_xvftintrm_l_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrm_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8742,7 +10371,13 @@ unsafe fn test_lasx_xvftint_w_d() { ); let r = i64x4::new(0, 0, 4294967297, 4294967296); - assert_eq!(r, transmute(lasx_xvftint_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftint_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8766,7 +10401,13 @@ unsafe fn test_lasx_xvffint_s_l() { -2383622820954443903, ); - assert_eq!(r, transmute(lasx_xvffint_s_l(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvffint_s_l( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8785,7 +10426,13 @@ unsafe fn test_lasx_xvftintrz_w_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrz_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8804,7 +10451,13 @@ unsafe fn test_lasx_xvftintrp_w_d() { ); let r = i64x4::new(4294967297, 4294967297, 4294967297, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrp_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrp_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8823,7 +10476,13 @@ unsafe fn test_lasx_xvftintrm_w_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrm_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8844,7 +10503,10 @@ unsafe fn test_lasx_xvftintrne_w_d() { assert_eq!( r, - transmute(lasx_xvftintrne_w_d(transmute(a), transmute(b))) + transmute(lasx_xvftintrne_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8856,7 +10518,7 @@ unsafe fn test_lasx_xvftinth_l_s() { ); let r = i64x4::new(0, 1, 0, 1); - assert_eq!(r, transmute(lasx_xvftinth_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftinth_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8867,7 +10529,7 @@ unsafe fn test_lasx_xvftintl_l_s() { ); let r = i64x4::new(0, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvftintl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8889,7 +10551,7 @@ unsafe fn test_lasx_xvffinth_d_w() { -4485741486683455488, ); - assert_eq!(r, transmute(lasx_xvffinth_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffinth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8911,7 +10573,7 @@ unsafe fn test_lasx_xvffintl_d_w() { -4489746915386195968, ); - assert_eq!(r, transmute(lasx_xvffintl_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffintl_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8922,7 +10584,7 @@ unsafe fn test_lasx_xvftintrzh_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrzh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrzh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8933,7 +10595,7 @@ unsafe fn test_lasx_xvftintrzl_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrzl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrzl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8944,7 +10606,7 @@ unsafe fn test_lasx_xvftintrph_l_s() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrph_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrph_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8955,7 +10617,7 @@ unsafe fn test_lasx_xvftintrpl_l_s() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrpl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrpl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8966,7 +10628,7 @@ unsafe fn test_lasx_xvftintrmh_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrmh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrmh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8977,7 +10639,7 @@ unsafe fn test_lasx_xvftintrml_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrml_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrml_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8988,7 +10650,7 @@ unsafe fn test_lasx_xvftintrneh_l_s() { ); let r = i64x4::new(1, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvftintrneh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrneh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8999,7 +10661,7 @@ unsafe fn test_lasx_xvftintrnel_l_s() { ); let r = i64x4::new(0, 1, 1, 0); - assert_eq!(r, transmute(lasx_xvftintrnel_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrnel_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9015,7 +10677,7 @@ unsafe fn test_lasx_xvfrintrne_s() { 1065353216, ); - assert_eq!(r, transmute(lasx_xvfrintrne_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrne_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9028,7 +10690,7 @@ unsafe fn test_lasx_xvfrintrne_d() { ); let r = i64x4::new(0, 0, 4607182418800017408, 0); - assert_eq!(r, transmute(lasx_xvfrintrne_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrne_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9039,7 +10701,7 @@ unsafe fn test_lasx_xvfrintrz_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrz_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrz_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9052,7 +10714,7 @@ unsafe fn test_lasx_xvfrintrz_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9068,7 +10730,7 @@ unsafe fn test_lasx_xvfrintrp_s() { 4575657222473777152, ); - assert_eq!(r, transmute(lasx_xvfrintrp_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrp_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9086,7 +10748,7 @@ unsafe fn test_lasx_xvfrintrp_d() { 4607182418800017408, ); - assert_eq!(r, transmute(lasx_xvfrintrp_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrp_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9097,7 +10759,7 @@ unsafe fn test_lasx_xvfrintrm_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrm_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrm_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9110,7 +10772,7 @@ unsafe fn test_lasx_xvfrintrm_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrm_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrm_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9146,7 +10808,7 @@ unsafe fn test_lasx_xvst() { -1239470096778490055, ); - lasx_xvst::<0>(transmute(a), o.as_mut_ptr()); + lasx_xvst::<0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9167,7 +10829,7 @@ unsafe fn test_lasx_xvstelm_b() { -1243134694581333281, ); - lasx_xvstelm_b::<0, 9>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_b::<0, 9>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9188,7 +10850,7 @@ unsafe fn test_lasx_xvstelm_h() { 4649151313692342074, ); - lasx_xvstelm_h::<0, 6>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_h::<0, 6>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9215,7 +10877,7 @@ unsafe fn test_lasx_xvstelm_w() { 5471549130760739388, ); - lasx_xvstelm_w::<0, 3>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_w::<0, 3>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9238,7 +10900,7 @@ unsafe fn test_lasx_xvstelm_d() { -4006899083251152793, ); - lasx_xvstelm_d::<0, 0>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_d::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9273,7 +10935,10 @@ unsafe fn test_lasx_xvinsve0_w() { assert_eq!( r, - transmute(lasx_xvinsve0_w::<5>(transmute(a), transmute(b))) + transmute(lasx_xvinsve0_w::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9300,7 +10965,10 @@ unsafe fn test_lasx_xvinsve0_d() { assert_eq!( r, - transmute(lasx_xvinsve0_d::<3>(transmute(a), transmute(b))) + transmute(lasx_xvinsve0_d::<3>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9318,7 +10986,7 @@ unsafe fn test_lasx_xvpickve_w() { ); let r = i64x4::new(1138467779, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpickve_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9331,7 +10999,7 @@ unsafe fn test_lasx_xvpickve_d() { ); let r = i64x4::new(8402618222187512066, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_d::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpickve_d::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9346,7 +11014,13 @@ unsafe fn test_lasx_xvssrlrn_b_h() { ); let r = i64x4::new(3463408299017240959, 0, 35748968851799935, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9373,7 +11047,13 @@ unsafe fn test_lasx_xvssrlrn_h_w() { ); let r = i64x4::new(422210317549567, 0, 11259106657337343, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9392,7 +11072,13 @@ unsafe fn test_lasx_xvssrlrn_w_d() { ); let r = i64x4::new(33428474336875, 0, 9223372034707292159, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9407,7 +11093,13 @@ unsafe fn test_lasx_xvssrln_b_h() { ); let r = i64x4::new(657383790217428863, 0, 941881790371430152, 0); - assert_eq!(r, transmute(lasx_xvssrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9434,7 +11126,13 @@ unsafe fn test_lasx_xvssrln_h_w() { ); let r = i64x4::new(9223103287866884105, 0, 1696871892814295669, 0); - assert_eq!(r, transmute(lasx_xvssrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9453,7 +11151,13 @@ unsafe fn test_lasx_xvssrln_w_d() { ); let r = i64x4::new(3937140138060021759, 0, 9223372034707292159, 0); - assert_eq!(r, transmute(lasx_xvssrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9473,7 +11177,13 @@ unsafe fn test_lasx_xvorn_v() { -126121887133672977, ); - assert_eq!(r, transmute(lasx_xvorn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvorn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9521,7 +11231,7 @@ unsafe fn test_lasx_xvstx() { -4162173646616256791, ); - lasx_xvstx(transmute(a), o.as_mut_ptr(), 0); + lasx_xvstx(black_box(transmute(a)), o.as_mut_ptr(), 0); assert_eq!(r, transmute(o)); } @@ -9535,7 +11245,7 @@ unsafe fn test_lasx_xvextl_qu_du() { ); let r = i64x4::new(-5083351180651141737, 0, 4121325568380818738, 0); - assert_eq!(r, transmute(lasx_xvextl_qu_du(transmute(a)))); + assert_eq!(r, transmute(lasx_xvextl_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9559,7 +11269,7 @@ unsafe fn test_lasx_xvinsgr2vr_w() { assert_eq!( r, - transmute(lasx_xvinsgr2vr_w::<4>(transmute(a), -596457645)) + transmute(lasx_xvinsgr2vr_w::<4>(black_box(transmute(a)), -596457645)) ); } @@ -9580,7 +11290,7 @@ unsafe fn test_lasx_xvinsgr2vr_d() { assert_eq!( r, - transmute(lasx_xvinsgr2vr_d::<3>(transmute(a), -1262509914)) + transmute(lasx_xvinsgr2vr_d::<3>(black_box(transmute(a)), -1262509914)) ); } @@ -9597,7 +11307,7 @@ unsafe fn test_lasx_xvreplve0_b() { 3472328296227680304, ); - assert_eq!(r, transmute(lasx_xvreplve0_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9613,7 +11323,7 @@ unsafe fn test_lasx_xvreplve0_h() { 115969459958317468, ); - assert_eq!(r, transmute(lasx_xvreplve0_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9635,7 +11345,7 @@ unsafe fn test_lasx_xvreplve0_w() { 5341799334363128369, ); - assert_eq!(r, transmute(lasx_xvreplve0_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9653,7 +11363,7 @@ unsafe fn test_lasx_xvreplve0_d() { -7669512117913941619, ); - assert_eq!(r, transmute(lasx_xvreplve0_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9669,7 +11379,7 @@ unsafe fn test_lasx_xvreplve0_q() { -7451765666000961269, ); - assert_eq!(r, transmute(lasx_xvreplve0_q(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_q(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9685,7 +11395,7 @@ unsafe fn test_lasx_vext2xv_h_b() { 24207148650070059, ); - assert_eq!(r, transmute(lasx_vext2xv_h_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9701,7 +11411,7 @@ unsafe fn test_lasx_vext2xv_w_h() { -34359738358622, ); - assert_eq!(r, transmute(lasx_vext2xv_w_h(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9718,7 +11428,7 @@ unsafe fn test_lasx_vext2xv_d_w() { ); let r = i64x4::new(-585251458, -2113345963, -1846838006, -474453663); - assert_eq!(r, transmute(lasx_vext2xv_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9729,7 +11439,7 @@ unsafe fn test_lasx_vext2xv_w_b() { ); let r = i64x4::new(-240518168540, -528280977282, 30064770965, -489626271740); - assert_eq!(r, transmute(lasx_vext2xv_w_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_w_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9740,7 +11450,7 @@ unsafe fn test_lasx_vext2xv_d_h() { ); let r = i64x4::new(28568, -25911, 12053, -2728); - assert_eq!(r, transmute(lasx_vext2xv_d_h(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9751,7 +11461,7 @@ unsafe fn test_lasx_vext2xv_d_b() { ); let r = i64x4::new(18, 112, -36, -67); - assert_eq!(r, transmute(lasx_vext2xv_d_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9767,7 +11477,7 @@ unsafe fn test_lasx_vext2xv_hu_bu() { 16888898041348298, ); - assert_eq!(r, transmute(lasx_vext2xv_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9783,7 +11493,7 @@ unsafe fn test_lasx_vext2xv_wu_hu() { 225172250484459, ); - assert_eq!(r, transmute(lasx_vext2xv_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9800,7 +11510,7 @@ unsafe fn test_lasx_vext2xv_du_wu() { ); let r = i64x4::new(4027501046, 3358638690, 2495633600, 1035808674); - assert_eq!(r, transmute(lasx_vext2xv_du_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9811,7 +11521,7 @@ unsafe fn test_lasx_vext2xv_wu_bu() { ); let r = i64x4::new(987842478134, 481036337184, 266287972487, 979252543649); - assert_eq!(r, transmute(lasx_vext2xv_wu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_wu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9822,7 +11532,7 @@ unsafe fn test_lasx_vext2xv_du_hu() { ); let r = i64x4::new(61301, 41410, 35355, 19598); - assert_eq!(r, transmute(lasx_vext2xv_du_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9833,7 +11543,7 @@ unsafe fn test_lasx_vext2xv_du_bu() { ); let r = i64x4::new(69, 25, 36, 204); - assert_eq!(r, transmute(lasx_vext2xv_du_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9855,7 +11565,10 @@ unsafe fn test_lasx_xvpermi_q() { assert_eq!( r, - transmute(lasx_xvpermi_q::<49>(transmute(a), transmute(b))) + transmute(lasx_xvpermi_q::<49>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9874,7 +11587,7 @@ unsafe fn test_lasx_xvpermi_d() { 1609032298240495217, ); - assert_eq!(r, transmute(lasx_xvpermi_d::<137>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpermi_d::<137>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9900,7 +11613,13 @@ unsafe fn test_lasx_xvperm_w() { -3042141963630030871, ); - assert_eq!(r, transmute(lasx_xvperm_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvperm_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9981,7 +11700,10 @@ unsafe fn test_lasx_xvpickve2gr_w() { ); let r: i32 = 1367768596; - assert_eq!(r, transmute(lasx_xvpickve2gr_w::<4>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_w::<4>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -9998,7 +11720,10 @@ unsafe fn test_lasx_xvpickve2gr_wu() { ); let r: u32 = 3194994707; - assert_eq!(r, transmute(lasx_xvpickve2gr_wu::<7>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_wu::<7>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10011,7 +11736,10 @@ unsafe fn test_lasx_xvpickve2gr_d() { ); let r: i64 = 6739870851682505277; - assert_eq!(r, transmute(lasx_xvpickve2gr_d::<2>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_d::<2>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10022,9 +11750,12 @@ unsafe fn test_lasx_xvpickve2gr_du() { -4272175049937479582, -8920910898336101981, ); - let r: u64 = 9525833175373449635; - - assert_eq!(r, transmute(lasx_xvpickve2gr_du::<3>(transmute(a)))); + let r: u64 = 9525833175373449635; + + assert_eq!( + r, + transmute(lasx_xvpickve2gr_du::<3>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10043,7 +11774,13 @@ unsafe fn test_lasx_xvaddwev_q_d() { ); let r = i64x4::new(-7472750192138786681, -1, -7758725841623301722, -1); - assert_eq!(r, transmute(lasx_xvaddwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10070,7 +11807,13 @@ unsafe fn test_lasx_xvaddwev_d_w() { ); let r = i64x4::new(614980351, -1946929141, -3309402607, -619077207); - assert_eq!(r, transmute(lasx_xvaddwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10090,7 +11833,13 @@ unsafe fn test_lasx_xvaddwev_w_h() { -232787227420502, ); - assert_eq!(r, transmute(lasx_xvaddwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10110,7 +11859,13 @@ unsafe fn test_lasx_xvaddwev_h_b() { -10414449598922739, ); - assert_eq!(r, transmute(lasx_xvaddwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10129,7 +11884,13 @@ unsafe fn test_lasx_xvaddwev_q_du() { ); let r = i64x4::new(4866121314102936184, 1, 898239984703082844, 1); - assert_eq!(r, transmute(lasx_xvaddwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10144,7 +11905,13 @@ unsafe fn test_lasx_xvaddwev_d_wu() { ); let r = i64x4::new(4001409528, 3398767892, 6021892971, 4349349069); - assert_eq!(r, transmute(lasx_xvaddwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10164,7 +11931,13 @@ unsafe fn test_lasx_xvaddwev_w_hu() { 376479653317006, ); - assert_eq!(r, transmute(lasx_xvaddwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10184,7 +11957,13 @@ unsafe fn test_lasx_xvaddwev_h_bu() { 68962872563859917, ); - assert_eq!(r, transmute(lasx_xvaddwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10203,7 +11982,13 @@ unsafe fn test_lasx_xvsubwev_q_d() { ); let r = i64x4::new(8183582659207736591, -1, 5496584216395980167, -1); - assert_eq!(r, transmute(lasx_xvsubwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10230,7 +12015,13 @@ unsafe fn test_lasx_xvsubwev_d_w() { ); let r = i64x4::new(-1945765730, 1700549847, -1218066002, -827282692); - assert_eq!(r, transmute(lasx_xvsubwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10250,7 +12041,13 @@ unsafe fn test_lasx_xvsubwev_w_h() { 217514323726817, ); - assert_eq!(r, transmute(lasx_xvsubwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10270,7 +12067,13 @@ unsafe fn test_lasx_xvsubwev_h_b() { -5910188531122352, ); - assert_eq!(r, transmute(lasx_xvsubwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10289,7 +12092,13 @@ unsafe fn test_lasx_xvsubwev_q_du() { ); let r = i64x4::new(-7180841769120666233, -1, -3901807980557405007, -1); - assert_eq!(r, transmute(lasx_xvsubwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10304,7 +12113,13 @@ unsafe fn test_lasx_xvsubwev_d_wu() { ); let r = i64x4::new(-2531041484, -1085343469, -1900376905, 1600829569); - assert_eq!(r, transmute(lasx_xvsubwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10324,7 +12139,13 @@ unsafe fn test_lasx_xvsubwev_w_hu() { -117029268872947, ); - assert_eq!(r, transmute(lasx_xvsubwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10344,7 +12165,13 @@ unsafe fn test_lasx_xvsubwev_h_bu() { -7035942402260810, ); - assert_eq!(r, transmute(lasx_xvsubwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10368,7 +12195,13 @@ unsafe fn test_lasx_xvmulwev_q_d() { -2723954123981949807, ); - assert_eq!(r, transmute(lasx_xvmulwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10400,7 +12233,13 @@ unsafe fn test_lasx_xvmulwev_d_w() { 904288373202150940, ); - assert_eq!(r, transmute(lasx_xvmulwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10420,7 +12259,13 @@ unsafe fn test_lasx_xvmulwev_w_h() { -218736636965849761, ); - assert_eq!(r, transmute(lasx_xvmulwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10440,7 +12285,13 @@ unsafe fn test_lasx_xvmulwev_h_b() { -532018857412992924, ); - assert_eq!(r, transmute(lasx_xvmulwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10464,7 +12315,13 @@ unsafe fn test_lasx_xvmulwev_q_du() { 1973424773030267173, ); - assert_eq!(r, transmute(lasx_xvmulwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10484,7 +12341,13 @@ unsafe fn test_lasx_xvmulwev_d_wu() { 312983850752328844, ); - assert_eq!(r, transmute(lasx_xvmulwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10504,7 +12367,13 @@ unsafe fn test_lasx_xvmulwev_w_hu() { -4803214827614038190, ); - assert_eq!(r, transmute(lasx_xvmulwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10524,7 +12393,13 @@ unsafe fn test_lasx_xvmulwev_h_bu() { 4458585836433706972, ); - assert_eq!(r, transmute(lasx_xvmulwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10543,7 +12418,13 @@ unsafe fn test_lasx_xvaddwod_q_d() { ); let r = i64x4::new(-3813723879058076957, 0, 200103109406722390, 0); - assert_eq!(r, transmute(lasx_xvaddwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10570,7 +12451,13 @@ unsafe fn test_lasx_xvaddwod_d_w() { ); let r = i64x4::new(3142724184, -2585235328, -785720463, 926940003); - assert_eq!(r, transmute(lasx_xvaddwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10590,7 +12477,13 @@ unsafe fn test_lasx_xvaddwod_w_h() { -148498494282599, ); - assert_eq!(r, transmute(lasx_xvaddwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10610,7 +12503,13 @@ unsafe fn test_lasx_xvaddwod_h_b() { -9570449863999416, ); - assert_eq!(r, transmute(lasx_xvaddwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10629,7 +12528,13 @@ unsafe fn test_lasx_xvaddwod_q_du() { ); let r = i64x4::new(751645223963476143, 1, -1275901335613508018, 0); - assert_eq!(r, transmute(lasx_xvaddwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10644,7 +12549,13 @@ unsafe fn test_lasx_xvaddwod_d_wu() { ); let r = i64x4::new(4757884041, 1673456593, 2162927615, 5143136401); - assert_eq!(r, transmute(lasx_xvaddwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10664,7 +12575,13 @@ unsafe fn test_lasx_xvaddwod_w_hu() { 248416613500221, ); - assert_eq!(r, transmute(lasx_xvaddwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10684,7 +12601,13 @@ unsafe fn test_lasx_xvaddwod_h_bu() { 83880238860075230, ); - assert_eq!(r, transmute(lasx_xvaddwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10703,7 +12626,13 @@ unsafe fn test_lasx_xvsubwod_q_d() { ); let r = i64x4::new(1764856097736252489, 0, 7683656878360999333, -1); - assert_eq!(r, transmute(lasx_xvsubwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10730,7 +12659,13 @@ unsafe fn test_lasx_xvsubwod_d_w() { ); let r = i64x4::new(-959924898, 7572903, 2106559810, 3976421257); - assert_eq!(r, transmute(lasx_xvsubwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10750,7 +12685,13 @@ unsafe fn test_lasx_xvsubwod_w_h() { -17665200524651, ); - assert_eq!(r, transmute(lasx_xvsubwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10770,7 +12711,13 @@ unsafe fn test_lasx_xvsubwod_h_b() { -3939721971105776, ); - assert_eq!(r, transmute(lasx_xvsubwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10789,7 +12736,13 @@ unsafe fn test_lasx_xvsubwod_q_du() { ); let r = i64x4::new(-6069526046627127478, -1, -1804068722113556285, -1); - assert_eq!(r, transmute(lasx_xvsubwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10804,7 +12757,13 @@ unsafe fn test_lasx_xvsubwod_d_wu() { ); let r = i64x4::new(762157671, -772219478, -1655146846, -1402401592); - assert_eq!(r, transmute(lasx_xvsubwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10824,7 +12783,13 @@ unsafe fn test_lasx_xvsubwod_w_hu() { 164866614644743, ); - assert_eq!(r, transmute(lasx_xvsubwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10844,7 +12809,13 @@ unsafe fn test_lasx_xvsubwod_h_bu() { -280740536975491, ); - assert_eq!(r, transmute(lasx_xvsubwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10868,7 +12839,13 @@ unsafe fn test_lasx_xvmulwod_q_d() { -113061080830775254, ); - assert_eq!(r, transmute(lasx_xvmulwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10900,7 +12877,13 @@ unsafe fn test_lasx_xvmulwod_d_w() { -1334126209007208500, ); - assert_eq!(r, transmute(lasx_xvmulwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10920,7 +12903,13 @@ unsafe fn test_lasx_xvmulwod_w_h() { 337273560374881751, ); - assert_eq!(r, transmute(lasx_xvmulwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10940,7 +12929,13 @@ unsafe fn test_lasx_xvmulwod_h_b() { -797714991416606612, ); - assert_eq!(r, transmute(lasx_xvmulwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10964,7 +12959,13 @@ unsafe fn test_lasx_xvmulwod_q_du() { -6864651532066967840, ); - assert_eq!(r, transmute(lasx_xvmulwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10984,7 +12985,13 @@ unsafe fn test_lasx_xvmulwod_d_wu() { 170736982952013264, ); - assert_eq!(r, transmute(lasx_xvmulwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11004,7 +13011,13 @@ unsafe fn test_lasx_xvmulwod_w_hu() { 648970298882764352, ); - assert_eq!(r, transmute(lasx_xvmulwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11024,7 +13037,13 @@ unsafe fn test_lasx_xvmulwod_h_bu() { 861263883582730760, ); - assert_eq!(r, transmute(lasx_xvmulwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11047,7 +13066,10 @@ unsafe fn test_lasx_xvaddwev_d_wu_w() { assert_eq!( r, - transmute(lasx_xvaddwev_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11070,7 +13092,10 @@ unsafe fn test_lasx_xvaddwev_w_hu_h() { assert_eq!( r, - transmute(lasx_xvaddwev_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11093,7 +13118,10 @@ unsafe fn test_lasx_xvaddwev_h_bu_b() { assert_eq!( r, - transmute(lasx_xvaddwev_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11122,7 +13150,10 @@ unsafe fn test_lasx_xvmulwev_d_wu_w() { assert_eq!( r, - transmute(lasx_xvmulwev_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11145,7 +13176,10 @@ unsafe fn test_lasx_xvmulwev_w_hu_h() { assert_eq!( r, - transmute(lasx_xvmulwev_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11168,7 +13202,10 @@ unsafe fn test_lasx_xvmulwev_h_bu_b() { assert_eq!( r, - transmute(lasx_xvmulwev_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11192,7 +13229,10 @@ unsafe fn test_lasx_xvaddwod_d_wu_w() { assert_eq!( r, - transmute(lasx_xvaddwod_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11215,7 +13255,10 @@ unsafe fn test_lasx_xvaddwod_w_hu_h() { assert_eq!( r, - transmute(lasx_xvaddwod_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11238,7 +13281,10 @@ unsafe fn test_lasx_xvaddwod_h_bu_b() { assert_eq!( r, - transmute(lasx_xvaddwod_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11267,7 +13313,10 @@ unsafe fn test_lasx_xvmulwod_d_wu_w() { assert_eq!( r, - transmute(lasx_xvmulwod_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11290,7 +13339,10 @@ unsafe fn test_lasx_xvmulwod_w_hu_h() { assert_eq!( r, - transmute(lasx_xvmulwod_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11313,7 +13365,10 @@ unsafe fn test_lasx_xvmulwod_h_bu_b() { assert_eq!( r, - transmute(lasx_xvmulwod_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11333,7 +13388,13 @@ unsafe fn test_lasx_xvhaddw_q_d() { ); let r = i64x4::new(7070440900316630840, -1, 4582440905924999074, 0); - assert_eq!(r, transmute(lasx_xvhaddw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11352,7 +13413,13 @@ unsafe fn test_lasx_xvhaddw_qu_du() { ); let r = i64x4::new(-6342973196760799579, 0, -6232960347008472572, 1); - assert_eq!(r, transmute(lasx_xvhaddw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11371,7 +13438,13 @@ unsafe fn test_lasx_xvhsubw_q_d() { ); let r = i64x4::new(5317548498597883842, 0, 6155348192460751216, -1); - assert_eq!(r, transmute(lasx_xvhsubw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11390,7 +13463,13 @@ unsafe fn test_lasx_xvhsubw_qu_du() { ); let r = i64x4::new(11053881530518619, 0, -1215853579082277290, -1); - assert_eq!(r, transmute(lasx_xvhsubw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11422,7 +13501,11 @@ unsafe fn test_lasx_xvmaddwev_q_d() { assert_eq!( r, - transmute(lasx_xvmaddwev_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11463,7 +13546,11 @@ unsafe fn test_lasx_xvmaddwev_d_w() { assert_eq!( r, - transmute(lasx_xvmaddwev_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11496,7 +13583,11 @@ unsafe fn test_lasx_xvmaddwev_w_h() { assert_eq!( r, - transmute(lasx_xvmaddwev_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11523,7 +13614,11 @@ unsafe fn test_lasx_xvmaddwev_h_b() { assert_eq!( r, - transmute(lasx_xvmaddwev_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11557,9 +13652,9 @@ unsafe fn test_lasx_xvmaddwev_q_du() { assert_eq!( r, transmute(lasx_xvmaddwev_q_du( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11590,9 +13685,9 @@ unsafe fn test_lasx_xvmaddwev_d_wu() { assert_eq!( r, transmute(lasx_xvmaddwev_d_wu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11621,9 +13716,9 @@ unsafe fn test_lasx_xvmaddwev_w_hu() { assert_eq!( r, transmute(lasx_xvmaddwev_w_hu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11652,9 +13747,9 @@ unsafe fn test_lasx_xvmaddwev_h_bu() { assert_eq!( r, transmute(lasx_xvmaddwev_h_bu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11688,7 +13783,11 @@ unsafe fn test_lasx_xvmaddwod_q_d() { assert_eq!( r, - transmute(lasx_xvmaddwod_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11729,7 +13828,11 @@ unsafe fn test_lasx_xvmaddwod_d_w() { assert_eq!( r, - transmute(lasx_xvmaddwod_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11762,7 +13865,11 @@ unsafe fn test_lasx_xvmaddwod_w_h() { assert_eq!( r, - transmute(lasx_xvmaddwod_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11789,7 +13896,11 @@ unsafe fn test_lasx_xvmaddwod_h_b() { assert_eq!( r, - transmute(lasx_xvmaddwod_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11823,9 +13934,9 @@ unsafe fn test_lasx_xvmaddwod_q_du() { assert_eq!( r, transmute(lasx_xvmaddwod_q_du( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11856,9 +13967,9 @@ unsafe fn test_lasx_xvmaddwod_d_wu() { assert_eq!( r, transmute(lasx_xvmaddwod_d_wu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11887,9 +13998,9 @@ unsafe fn test_lasx_xvmaddwod_w_hu() { assert_eq!( r, transmute(lasx_xvmaddwod_w_hu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11918,9 +14029,9 @@ unsafe fn test_lasx_xvmaddwod_h_bu() { assert_eq!( r, transmute(lasx_xvmaddwod_h_bu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11955,9 +14066,9 @@ unsafe fn test_lasx_xvmaddwev_q_du_d() { assert_eq!( r, transmute(lasx_xvmaddwev_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11994,9 +14105,9 @@ unsafe fn test_lasx_xvmaddwev_d_wu_w() { assert_eq!( r, transmute(lasx_xvmaddwev_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12031,9 +14142,9 @@ unsafe fn test_lasx_xvmaddwev_w_hu_h() { assert_eq!( r, transmute(lasx_xvmaddwev_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12062,9 +14173,9 @@ unsafe fn test_lasx_xvmaddwev_h_bu_b() { assert_eq!( r, transmute(lasx_xvmaddwev_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12099,9 +14210,9 @@ unsafe fn test_lasx_xvmaddwod_q_du_d() { assert_eq!( r, transmute(lasx_xvmaddwod_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12138,9 +14249,9 @@ unsafe fn test_lasx_xvmaddwod_d_wu_w() { assert_eq!( r, transmute(lasx_xvmaddwod_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12169,9 +14280,9 @@ unsafe fn test_lasx_xvmaddwod_w_hu_h() { assert_eq!( r, transmute(lasx_xvmaddwod_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12200,9 +14311,9 @@ unsafe fn test_lasx_xvmaddwod_h_bu_b() { assert_eq!( r, transmute(lasx_xvmaddwod_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12224,7 +14335,13 @@ unsafe fn test_lasx_xvrotr_b() { 5842271601646106402, ); - assert_eq!(r, transmute(lasx_xvrotr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12244,7 +14361,13 @@ unsafe fn test_lasx_xvrotr_h() { 8109266518466894464, ); - assert_eq!(r, transmute(lasx_xvrotr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12264,7 +14387,13 @@ unsafe fn test_lasx_xvrotr_w() { 8567937817891640092, ); - assert_eq!(r, transmute(lasx_xvrotr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12288,7 +14417,13 @@ unsafe fn test_lasx_xvrotr_d() { 4254025119287920211, ); - assert_eq!(r, transmute(lasx_xvrotr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12312,7 +14447,13 @@ unsafe fn test_lasx_xvadd_q() { 1706530784161666452, ); - assert_eq!(r, transmute(lasx_xvadd_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_q( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12336,7 +14477,13 @@ unsafe fn test_lasx_xvsub_q() { 1242748497994781383, ); - assert_eq!(r, transmute(lasx_xvsub_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_q( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12357,7 +14504,10 @@ unsafe fn test_lasx_xvaddwev_q_du_d() { assert_eq!( r, - transmute(lasx_xvaddwev_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12379,7 +14529,10 @@ unsafe fn test_lasx_xvaddwod_q_du_d() { assert_eq!( r, - transmute(lasx_xvaddwod_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12406,7 +14559,10 @@ unsafe fn test_lasx_xvmulwev_q_du_d() { assert_eq!( r, - transmute(lasx_xvmulwev_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12433,7 +14589,10 @@ unsafe fn test_lasx_xvmulwod_q_du_d() { assert_eq!( r, - transmute(lasx_xvmulwod_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12445,7 +14604,7 @@ unsafe fn test_lasx_xvmskgez_b() { ); let r = i64x4::new(13289, 0, 4927, 0); - assert_eq!(r, transmute(lasx_xvmskgez_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskgez_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12456,7 +14615,7 @@ unsafe fn test_lasx_xvmsknz_b() { ); let r = i64x4::new(65535, 0, 65535, 0); - assert_eq!(r, transmute(lasx_xvmsknz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmsknz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12472,7 +14631,7 @@ unsafe fn test_lasx_xvexth_h_b() { -1689051729887256, ); - assert_eq!(r, transmute(lasx_xvexth_h_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12488,7 +14647,7 @@ unsafe fn test_lasx_xvexth_w_h() { -117171002791439, ); - assert_eq!(r, transmute(lasx_xvexth_w_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12505,7 +14664,7 @@ unsafe fn test_lasx_xvexth_d_w() { ); let r = i64x4::new(78514216, -1063299454, -1487536177, 1875317589); - assert_eq!(r, transmute(lasx_xvexth_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12518,7 +14677,7 @@ unsafe fn test_lasx_xvexth_q_d() { ); let r = i64x4::new(5196480214883180720, 0, 7776492634988202392, 0); - assert_eq!(r, transmute(lasx_xvexth_q_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12534,7 +14693,7 @@ unsafe fn test_lasx_xvexth_hu_bu() { 11259067788754993, ); - assert_eq!(r, transmute(lasx_xvexth_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12550,7 +14709,7 @@ unsafe fn test_lasx_xvexth_wu_hu() { 211376815493177, ); - assert_eq!(r, transmute(lasx_xvexth_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12561,7 +14720,7 @@ unsafe fn test_lasx_xvexth_du_wu() { ); let r = i64x4::new(3486710391, 717721410, 1954296323, 1406265475); - assert_eq!(r, transmute(lasx_xvexth_du_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12574,7 +14733,7 @@ unsafe fn test_lasx_xvexth_qu_du() { ); let r = i64x4::new(6305760528044738869, 0, 3857202168052068182, 0); - assert_eq!(r, transmute(lasx_xvexth_qu_du(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12590,7 +14749,7 @@ unsafe fn test_lasx_xvrotri_b() { -3500418816657076903, ); - assert_eq!(r, transmute(lasx_xvrotri_b::<4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_b::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12606,7 +14765,7 @@ unsafe fn test_lasx_xvrotri_h() { 4779464405959485451, ); - assert_eq!(r, transmute(lasx_xvrotri_h::<15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_h::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12628,7 +14787,7 @@ unsafe fn test_lasx_xvrotri_w() { -1679179889808014898, ); - assert_eq!(r, transmute(lasx_xvrotri_w::<11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_w::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12646,7 +14805,7 @@ unsafe fn test_lasx_xvrotri_d() { -7958311692822812825, ); - assert_eq!(r, transmute(lasx_xvrotri_d::<16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_d::<16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12659,7 +14818,7 @@ unsafe fn test_lasx_xvextl_q_d() { ); let r = i64x4::new(-4167783494125842132, -1, 7476993593286219399, 0); - assert_eq!(r, transmute(lasx_xvextl_q_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvextl_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12681,7 +14840,10 @@ unsafe fn test_lasx_xvsrlni_b_h() { assert_eq!( r, - transmute(lasx_xvsrlni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12704,7 +14866,10 @@ unsafe fn test_lasx_xvsrlni_h_w() { assert_eq!( r, - transmute(lasx_xvsrlni_h_w::<16>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_h_w::<16>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12739,7 +14904,10 @@ unsafe fn test_lasx_xvsrlni_w_d() { assert_eq!( r, - transmute(lasx_xvsrlni_w_d::<26>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_w_d::<26>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12761,7 +14929,10 @@ unsafe fn test_lasx_xvsrlni_d_q() { assert_eq!( r, - transmute(lasx_xvsrlni_d_q::<102>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_d_q::<102>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12784,7 +14955,10 @@ unsafe fn test_lasx_xvsrlrni_b_h() { assert_eq!( r, - transmute(lasx_xvsrlrni_b_h::<8>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_b_h::<8>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12807,7 +14981,10 @@ unsafe fn test_lasx_xvsrlrni_h_w() { assert_eq!( r, - transmute(lasx_xvsrlrni_h_w::<5>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_h_w::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12842,7 +15019,10 @@ unsafe fn test_lasx_xvsrlrni_w_d() { assert_eq!( r, - transmute(lasx_xvsrlrni_w_d::<43>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_w_d::<43>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12864,7 +15044,10 @@ unsafe fn test_lasx_xvsrlrni_d_q() { assert_eq!( r, - transmute(lasx_xvsrlrni_d_q::<126>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_d_q::<126>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12887,7 +15070,10 @@ unsafe fn test_lasx_xvssrlni_b_h() { assert_eq!( r, - transmute(lasx_xvssrlni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12905,7 +15091,10 @@ unsafe fn test_lasx_xvssrlni_h_w() { assert_eq!( r, - transmute(lasx_xvssrlni_h_w::<31>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_h_w::<31>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12940,7 +15129,10 @@ unsafe fn test_lasx_xvssrlni_w_d() { assert_eq!( r, - transmute(lasx_xvssrlni_w_d::<14>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_w_d::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12967,7 +15159,10 @@ unsafe fn test_lasx_xvssrlni_d_q() { assert_eq!( r, - transmute(lasx_xvssrlni_d_q::<35>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_d_q::<35>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12990,7 +15185,10 @@ unsafe fn test_lasx_xvssrlni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrlni_bu_h::<11>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_bu_h::<11>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13008,7 +15206,10 @@ unsafe fn test_lasx_xvssrlni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrlni_hu_w::<31>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_hu_w::<31>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13032,7 +15233,10 @@ unsafe fn test_lasx_xvssrlni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrlni_wu_d::<24>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_wu_d::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13054,7 +15258,10 @@ unsafe fn test_lasx_xvssrlni_du_q() { assert_eq!( r, - transmute(lasx_xvssrlni_du_q::<109>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_du_q::<109>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13077,7 +15284,10 @@ unsafe fn test_lasx_xvssrlrni_b_h() { assert_eq!( r, - transmute(lasx_xvssrlrni_b_h::<7>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_b_h::<7>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13100,7 +15310,10 @@ unsafe fn test_lasx_xvssrlrni_h_w() { assert_eq!( r, - transmute(lasx_xvssrlrni_h_w::<11>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_h_w::<11>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13135,7 +15348,10 @@ unsafe fn test_lasx_xvssrlrni_w_d() { assert_eq!( r, - transmute(lasx_xvssrlrni_w_d::<27>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_w_d::<27>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13157,7 +15373,10 @@ unsafe fn test_lasx_xvssrlrni_d_q() { assert_eq!( r, - transmute(lasx_xvssrlrni_d_q::<94>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_d_q::<94>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13175,7 +15394,10 @@ unsafe fn test_lasx_xvssrlrni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrlrni_bu_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_bu_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13198,7 +15420,10 @@ unsafe fn test_lasx_xvssrlrni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrlrni_hu_w::<16>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_hu_w::<16>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13227,7 +15452,10 @@ unsafe fn test_lasx_xvssrlrni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrlrni_wu_d::<50>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_wu_d::<50>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13249,7 +15477,10 @@ unsafe fn test_lasx_xvssrlrni_du_q() { assert_eq!( r, - transmute(lasx_xvssrlrni_du_q::<53>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_du_q::<53>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13272,7 +15503,10 @@ unsafe fn test_lasx_xvsrani_b_h() { assert_eq!( r, - transmute(lasx_xvsrani_b_h::<8>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_b_h::<8>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13295,7 +15529,10 @@ unsafe fn test_lasx_xvsrani_h_w() { assert_eq!( r, - transmute(lasx_xvsrani_h_w::<0>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_h_w::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13330,7 +15567,10 @@ unsafe fn test_lasx_xvsrani_w_d() { assert_eq!( r, - transmute(lasx_xvsrani_w_d::<28>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_w_d::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13357,7 +15597,10 @@ unsafe fn test_lasx_xvsrani_d_q() { assert_eq!( r, - transmute(lasx_xvsrani_d_q::<66>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_d_q::<66>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13380,7 +15623,10 @@ unsafe fn test_lasx_xvsrarni_b_h() { assert_eq!( r, - transmute(lasx_xvsrarni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13403,7 +15649,10 @@ unsafe fn test_lasx_xvsrarni_h_w() { assert_eq!( r, - transmute(lasx_xvsrarni_h_w::<9>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_h_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13427,7 +15676,10 @@ unsafe fn test_lasx_xvsrarni_w_d() { assert_eq!( r, - transmute(lasx_xvsrarni_w_d::<63>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_w_d::<63>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13449,7 +15701,10 @@ unsafe fn test_lasx_xvsrarni_d_q() { assert_eq!( r, - transmute(lasx_xvsrarni_d_q::<102>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_d_q::<102>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13472,7 +15727,10 @@ unsafe fn test_lasx_xvssrani_b_h() { assert_eq!( r, - transmute(lasx_xvssrani_b_h::<5>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_b_h::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13495,7 +15753,10 @@ unsafe fn test_lasx_xvssrani_h_w() { assert_eq!( r, - transmute(lasx_xvssrani_h_w::<0>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_h_w::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13530,7 +15791,10 @@ unsafe fn test_lasx_xvssrani_w_d() { assert_eq!( r, - transmute(lasx_xvssrani_w_d::<45>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_w_d::<45>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13557,7 +15821,10 @@ unsafe fn test_lasx_xvssrani_d_q() { assert_eq!( r, - transmute(lasx_xvssrani_d_q::<73>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_d_q::<73>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13575,7 +15842,10 @@ unsafe fn test_lasx_xvssrani_bu_h() { assert_eq!( r, - transmute(lasx_xvssrani_bu_h::<12>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_bu_h::<12>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13593,7 +15863,10 @@ unsafe fn test_lasx_xvssrani_hu_w() { assert_eq!( r, - transmute(lasx_xvssrani_hu_w::<9>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_hu_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13617,7 +15890,10 @@ unsafe fn test_lasx_xvssrani_wu_d() { assert_eq!( r, - transmute(lasx_xvssrani_wu_d::<42>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_wu_d::<42>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13639,7 +15915,10 @@ unsafe fn test_lasx_xvssrani_du_q() { assert_eq!( r, - transmute(lasx_xvssrani_du_q::<115>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_du_q::<115>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13662,7 +15941,10 @@ unsafe fn test_lasx_xvssrarni_b_h() { assert_eq!( r, - transmute(lasx_xvssrarni_b_h::<6>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_b_h::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13685,7 +15967,10 @@ unsafe fn test_lasx_xvssrarni_h_w() { assert_eq!( r, - transmute(lasx_xvssrarni_h_w::<25>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_h_w::<25>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13715,7 +16000,10 @@ unsafe fn test_lasx_xvssrarni_w_d() { assert_eq!( r, - transmute(lasx_xvssrarni_w_d::<61>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_w_d::<61>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13737,7 +16025,10 @@ unsafe fn test_lasx_xvssrarni_d_q() { assert_eq!( r, - transmute(lasx_xvssrarni_d_q::<123>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_d_q::<123>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13760,7 +16051,10 @@ unsafe fn test_lasx_xvssrarni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrarni_bu_h::<10>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_bu_h::<10>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13778,7 +16072,10 @@ unsafe fn test_lasx_xvssrarni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrarni_hu_w::<30>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_hu_w::<30>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13802,7 +16099,10 @@ unsafe fn test_lasx_xvssrarni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrarni_wu_d::<61>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_wu_d::<61>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13824,7 +16124,10 @@ unsafe fn test_lasx_xvssrarni_du_q() { assert_eq!( r, - transmute(lasx_xvssrarni_du_q::<15>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_du_q::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13836,7 +16139,7 @@ unsafe fn test_lasx_xbnz_b() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13849,7 +16152,7 @@ unsafe fn test_lasx_xbnz_d() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13860,7 +16163,7 @@ unsafe fn test_lasx_xbnz_h() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13871,7 +16174,7 @@ unsafe fn test_lasx_xbnz_v() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_v(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_v(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13882,7 +16185,7 @@ unsafe fn test_lasx_xbnz_w() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13893,7 +16196,7 @@ unsafe fn test_lasx_xbz_b() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13906,7 +16209,7 @@ unsafe fn test_lasx_xbz_d() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13917,7 +16220,7 @@ unsafe fn test_lasx_xbz_h() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13928,7 +16231,7 @@ unsafe fn test_lasx_xbz_v() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_v(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_v(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13939,7 +16242,7 @@ unsafe fn test_lasx_xbz_w() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13958,7 +16261,13 @@ unsafe fn test_lasx_xvfcmp_caf_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_caf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_caf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -13973,7 +16282,13 @@ unsafe fn test_lasx_xvfcmp_caf_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_caf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_caf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -13992,7 +16307,13 @@ unsafe fn test_lasx_xvfcmp_ceq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_ceq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_ceq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14007,7 +16328,13 @@ unsafe fn test_lasx_xvfcmp_ceq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_ceq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_ceq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14026,7 +16353,13 @@ unsafe fn test_lasx_xvfcmp_cle_d() { ); let r = i64x4::new(-1, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14041,7 +16374,13 @@ unsafe fn test_lasx_xvfcmp_cle_s() { ); let r = i64x4::new(0, -1, -1, -4294967296); - assert_eq!(r, transmute(lasx_xvfcmp_cle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14060,7 +16399,13 @@ unsafe fn test_lasx_xvfcmp_clt_d() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvfcmp_clt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_clt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14075,7 +16420,13 @@ unsafe fn test_lasx_xvfcmp_clt_s() { ); let r = i64x4::new(-1, 4294967295, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_clt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_clt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14094,7 +16445,13 @@ unsafe fn test_lasx_xvfcmp_cne_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14109,7 +16466,13 @@ unsafe fn test_lasx_xvfcmp_cne_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14128,7 +16491,13 @@ unsafe fn test_lasx_xvfcmp_cor_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14143,7 +16512,13 @@ unsafe fn test_lasx_xvfcmp_cor_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14162,7 +16537,13 @@ unsafe fn test_lasx_xvfcmp_cueq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14177,7 +16558,13 @@ unsafe fn test_lasx_xvfcmp_cueq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14196,7 +16583,13 @@ unsafe fn test_lasx_xvfcmp_cule_d() { ); let r = i64x4::new(0, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14211,7 +16604,13 @@ unsafe fn test_lasx_xvfcmp_cule_s() { ); let r = i64x4::new(-4294967296, 4294967295, 4294967295, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14230,7 +16629,13 @@ unsafe fn test_lasx_xvfcmp_cult_d() { ); let r = i64x4::new(0, -1, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14245,7 +16650,13 @@ unsafe fn test_lasx_xvfcmp_cult_s() { ); let r = i64x4::new(-1, 0, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14264,7 +16675,13 @@ unsafe fn test_lasx_xvfcmp_cun_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14283,7 +16700,13 @@ unsafe fn test_lasx_xvfcmp_cune_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14298,7 +16721,13 @@ unsafe fn test_lasx_xvfcmp_cune_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14313,7 +16742,13 @@ unsafe fn test_lasx_xvfcmp_cun_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14332,7 +16767,13 @@ unsafe fn test_lasx_xvfcmp_saf_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_saf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_saf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14347,7 +16788,13 @@ unsafe fn test_lasx_xvfcmp_saf_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_saf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_saf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14366,7 +16813,13 @@ unsafe fn test_lasx_xvfcmp_seq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_seq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_seq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14381,7 +16834,13 @@ unsafe fn test_lasx_xvfcmp_seq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_seq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_seq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14400,7 +16859,13 @@ unsafe fn test_lasx_xvfcmp_sle_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14415,7 +16880,13 @@ unsafe fn test_lasx_xvfcmp_sle_s() { ); let r = i64x4::new(0, 4294967295, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14434,7 +16905,13 @@ unsafe fn test_lasx_xvfcmp_slt_d() { ); let r = i64x4::new(0, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_slt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_slt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14449,7 +16926,13 @@ unsafe fn test_lasx_xvfcmp_slt_s() { ); let r = i64x4::new(0, -4294967296, 4294967295, -1); - assert_eq!(r, transmute(lasx_xvfcmp_slt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_slt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14468,7 +16951,13 @@ unsafe fn test_lasx_xvfcmp_sne_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14483,7 +16972,13 @@ unsafe fn test_lasx_xvfcmp_sne_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14502,7 +16997,13 @@ unsafe fn test_lasx_xvfcmp_sor_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14517,7 +17018,13 @@ unsafe fn test_lasx_xvfcmp_sor_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14536,7 +17043,13 @@ unsafe fn test_lasx_xvfcmp_sueq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14551,7 +17064,13 @@ unsafe fn test_lasx_xvfcmp_sueq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14570,7 +17089,13 @@ unsafe fn test_lasx_xvfcmp_sule_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14585,7 +17110,13 @@ unsafe fn test_lasx_xvfcmp_sule_s() { ); let r = i64x4::new(0, 4294967295, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14604,7 +17135,13 @@ unsafe fn test_lasx_xvfcmp_sult_d() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14619,7 +17156,13 @@ unsafe fn test_lasx_xvfcmp_sult_s() { ); let r = i64x4::new(-1, 4294967295, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14638,7 +17181,13 @@ unsafe fn test_lasx_xvfcmp_sun_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14657,7 +17206,13 @@ unsafe fn test_lasx_xvfcmp_sune_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14672,7 +17227,13 @@ unsafe fn test_lasx_xvfcmp_sune_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14687,7 +17248,13 @@ unsafe fn test_lasx_xvfcmp_sun_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14700,7 +17267,10 @@ unsafe fn test_lasx_xvpickve_d_f() { ); let r = i64x4::new(4605596490350167974, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_d_f::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve_d_f::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -14711,7 +17281,10 @@ unsafe fn test_lasx_xvpickve_w_f() { ); let r = i64x4::new(1040565756, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_w_f::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve_w_f::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -14764,7 +17337,7 @@ unsafe fn test_lasx_cast_128_s() { assert_eq!( r.as_array()[0..2], - transmute::<_, i64x4>(lasx_cast_128_s(transmute(a))).as_array()[0..2] + transmute::<_, i64x4>(lasx_cast_128_s(black_box(transmute(a)))).as_array()[0..2] ); } @@ -14780,7 +17353,7 @@ unsafe fn test_lasx_cast_128_d() { assert_eq!( r.as_array()[0..2], - transmute::<_, i64x4>(lasx_cast_128_d(transmute(a))).as_array()[0..2] + transmute::<_, i64x4>(lasx_cast_128_d(black_box(transmute(a)))).as_array()[0..2] ); } @@ -14796,7 +17369,7 @@ unsafe fn test_lasx_cast_128() { assert_eq!( r.as_array()[0..2], - transmute::<_, i64x4>(lasx_cast_128(transmute(a))).as_array()[0..2] + transmute::<_, i64x4>(lasx_cast_128(black_box(transmute(a)))).as_array()[0..2] ); } @@ -14811,7 +17384,13 @@ unsafe fn test_lasx_concat_128_s() { 4410275898954698048, ); - assert_eq!(r, transmute(lasx_concat_128_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_concat_128_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14825,7 +17404,13 @@ unsafe fn test_lasx_concat_128_d() { 4600308396523102002, ); - assert_eq!(r, transmute(lasx_concat_128_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_concat_128_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14839,7 +17424,13 @@ unsafe fn test_lasx_concat_128() { 7751541408133090748, ); - assert_eq!(r, transmute(lasx_concat_128(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_concat_128( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14850,7 +17441,7 @@ unsafe fn test_lasx_extract_128_lo_s() { ); let r = i64x2::new(4524431379435545192, 4532741359493293580); - assert_eq!(r, transmute(lasx_extract_128_lo_s(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_lo_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14861,7 +17452,7 @@ unsafe fn test_lasx_extract_128_hi_s() { ); let r = i64x2::new(4572785117706267614, 4549394373627784333); - assert_eq!(r, transmute(lasx_extract_128_hi_s(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_hi_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14874,7 +17465,7 @@ unsafe fn test_lasx_extract_128_lo_d() { ); let r = i64x2::new(4606487981487128637, 4592443779247846248); - assert_eq!(r, transmute(lasx_extract_128_lo_d(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_lo_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14887,7 +17478,7 @@ unsafe fn test_lasx_extract_128_hi_d() { ); let r = i64x2::new(4603881047625519227, 4604218419306666352); - assert_eq!(r, transmute(lasx_extract_128_hi_d(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_hi_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14900,7 +17491,7 @@ unsafe fn test_lasx_extract_128_lo() { ); let r = i64x2::new(1690990426210778543, -1056924033489771427); - assert_eq!(r, transmute(lasx_extract_128_lo(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_lo(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14913,7 +17504,7 @@ unsafe fn test_lasx_extract_128_hi() { ); let r = i64x2::new(-1903780563362068813, -7449796170151383489); - assert_eq!(r, transmute(lasx_extract_128_hi(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_hi(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14932,7 +17523,10 @@ unsafe fn test_lasx_insert_128_lo_s() { assert_eq!( r, - transmute(lasx_insert_128_lo_s(transmute(a), transmute(b))) + transmute(lasx_insert_128_lo_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -14952,7 +17546,10 @@ unsafe fn test_lasx_insert_128_hi_s() { assert_eq!( r, - transmute(lasx_insert_128_hi_s(transmute(a), transmute(b))) + transmute(lasx_insert_128_hi_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -14974,7 +17571,10 @@ unsafe fn test_lasx_insert_128_lo_d() { assert_eq!( r, - transmute(lasx_insert_128_lo_d(transmute(a), transmute(b))) + transmute(lasx_insert_128_lo_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -14996,7 +17596,10 @@ unsafe fn test_lasx_insert_128_hi_d() { assert_eq!( r, - transmute(lasx_insert_128_hi_d(transmute(a), transmute(b))) + transmute(lasx_insert_128_hi_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -15016,7 +17619,13 @@ unsafe fn test_lasx_insert_128_lo() { -4396186135186039276, ); - assert_eq!(r, transmute(lasx_insert_128_lo(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_insert_128_lo( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -15035,5 +17644,11 @@ unsafe fn test_lasx_insert_128_hi() { -7502655081590988207, ); - assert_eq!(r, transmute(lasx_insert_128_hi(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_insert_128_hi( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } diff --git a/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs b/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs index 25efaadb42880..9f13d2b3c43b4 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs @@ -11,38 +11,6 @@ use super::super::*; #[allow(improper_ctypes)] unsafe extern "unadjusted" { - #[link_name = "llvm.loongarch.lsx.vsll.b"] - fn __lsx_vsll_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsll.h"] - fn __lsx_vsll_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsll.w"] - fn __lsx_vsll_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsll.d"] - fn __lsx_vsll_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslli.b"] - fn __lsx_vslli_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslli.h"] - fn __lsx_vslli_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslli.w"] - fn __lsx_vslli_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslli.d"] - fn __lsx_vslli_d(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsra.b"] - fn __lsx_vsra_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsra.h"] - fn __lsx_vsra_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsra.w"] - fn __lsx_vsra_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsra.d"] - fn __lsx_vsra_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsrai.b"] - fn __lsx_vsrai_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsrai.h"] - fn __lsx_vsrai_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsrai.w"] - fn __lsx_vsrai_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsrai.d"] - fn __lsx_vsrai_d(a: __v2i64, b: u32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsrar.b"] fn __lsx_vsrar_b(a: __v16i8, b: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vsrar.h"] @@ -59,22 +27,6 @@ unsafe extern "unadjusted" { fn __lsx_vsrari_w(a: __v4i32, b: u32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vsrari.d"] fn __lsx_vsrari_d(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsrl.b"] - fn __lsx_vsrl_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsrl.h"] - fn __lsx_vsrl_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsrl.w"] - fn __lsx_vsrl_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsrl.d"] - fn __lsx_vsrl_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsrli.b"] - fn __lsx_vsrli_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsrli.h"] - fn __lsx_vsrli_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsrli.w"] - fn __lsx_vsrli_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsrli.d"] - fn __lsx_vsrli_d(a: __v2i64, b: u32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsrlr.b"] fn __lsx_vsrlr_b(a: __v16i8, b: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vsrlr.h"] @@ -91,14 +43,6 @@ unsafe extern "unadjusted" { fn __lsx_vsrlri_w(a: __v4i32, b: u32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vsrlri.d"] fn __lsx_vsrlri_d(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vbitclr.b"] - fn __lsx_vbitclr_b(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vbitclr.h"] - fn __lsx_vbitclr_h(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vbitclr.w"] - fn __lsx_vbitclr_w(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vbitclr.d"] - fn __lsx_vbitclr_d(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vbitclri.b"] fn __lsx_vbitclri_b(a: __v16u8, b: u32) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitclri.h"] @@ -107,14 +51,6 @@ unsafe extern "unadjusted" { fn __lsx_vbitclri_w(a: __v4u32, b: u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vbitclri.d"] fn __lsx_vbitclri_d(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vbitset.b"] - fn __lsx_vbitset_b(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vbitset.h"] - fn __lsx_vbitset_h(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vbitset.w"] - fn __lsx_vbitset_w(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vbitset.d"] - fn __lsx_vbitset_d(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vbitseti.b"] fn __lsx_vbitseti_b(a: __v16u8, b: u32) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitseti.h"] @@ -123,14 +59,6 @@ unsafe extern "unadjusted" { fn __lsx_vbitseti_w(a: __v4u32, b: u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vbitseti.d"] fn __lsx_vbitseti_d(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vbitrev.b"] - fn __lsx_vbitrev_b(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vbitrev.h"] - fn __lsx_vbitrev_h(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vbitrev.w"] - fn __lsx_vbitrev_w(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vbitrev.d"] - fn __lsx_vbitrev_d(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vbitrevi.b"] fn __lsx_vbitrevi_b(a: __v16u8, b: u32) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitrevi.h"] @@ -139,30 +67,6 @@ unsafe extern "unadjusted" { fn __lsx_vbitrevi_w(a: __v4u32, b: u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vbitrevi.d"] fn __lsx_vbitrevi_d(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vadd.b"] - fn __lsx_vadd_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vadd.h"] - fn __lsx_vadd_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vadd.w"] - fn __lsx_vadd_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vadd.d"] - fn __lsx_vadd_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vaddi.bu"] - fn __lsx_vaddi_bu(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vaddi.hu"] - fn __lsx_vaddi_hu(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vaddi.wu"] - fn __lsx_vaddi_wu(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vaddi.du"] - fn __lsx_vaddi_du(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsub.b"] - fn __lsx_vsub_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsub.h"] - fn __lsx_vsub_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsub.w"] - fn __lsx_vsub_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsub.d"] - fn __lsx_vsub_d(a: __v2i64, b: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsubi.bu"] fn __lsx_vsubi_bu(a: __v16i8, b: u32) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vsubi.hu"] @@ -171,150 +75,6 @@ unsafe extern "unadjusted" { fn __lsx_vsubi_wu(a: __v4i32, b: u32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vsubi.du"] fn __lsx_vsubi_du(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmax.b"] - fn __lsx_vmax_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmax.h"] - fn __lsx_vmax_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmax.w"] - fn __lsx_vmax_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmax.d"] - fn __lsx_vmax_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmaxi.b"] - fn __lsx_vmaxi_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmaxi.h"] - fn __lsx_vmaxi_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmaxi.w"] - fn __lsx_vmaxi_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmaxi.d"] - fn __lsx_vmaxi_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmax.bu"] - fn __lsx_vmax_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmax.hu"] - fn __lsx_vmax_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmax.wu"] - fn __lsx_vmax_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmax.du"] - fn __lsx_vmax_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vmaxi.bu"] - fn __lsx_vmaxi_bu(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmaxi.hu"] - fn __lsx_vmaxi_hu(a: __v8u16, b: u32) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmaxi.wu"] - fn __lsx_vmaxi_wu(a: __v4u32, b: u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmaxi.du"] - fn __lsx_vmaxi_du(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vmin.b"] - fn __lsx_vmin_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmin.h"] - fn __lsx_vmin_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmin.w"] - fn __lsx_vmin_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmin.d"] - fn __lsx_vmin_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmini.b"] - fn __lsx_vmini_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmini.h"] - fn __lsx_vmini_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmini.w"] - fn __lsx_vmini_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmini.d"] - fn __lsx_vmini_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmin.bu"] - fn __lsx_vmin_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmin.hu"] - fn __lsx_vmin_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmin.wu"] - fn __lsx_vmin_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmin.du"] - fn __lsx_vmin_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vmini.bu"] - fn __lsx_vmini_bu(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmini.hu"] - fn __lsx_vmini_hu(a: __v8u16, b: u32) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmini.wu"] - fn __lsx_vmini_wu(a: __v4u32, b: u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmini.du"] - fn __lsx_vmini_du(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vseq.b"] - fn __lsx_vseq_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vseq.h"] - fn __lsx_vseq_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vseq.w"] - fn __lsx_vseq_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vseq.d"] - fn __lsx_vseq_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vseqi.b"] - fn __lsx_vseqi_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vseqi.h"] - fn __lsx_vseqi_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vseqi.w"] - fn __lsx_vseqi_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vseqi.d"] - fn __lsx_vseqi_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslti.b"] - fn __lsx_vslti_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslt.b"] - fn __lsx_vslt_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslt.h"] - fn __lsx_vslt_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslt.w"] - fn __lsx_vslt_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslt.d"] - fn __lsx_vslt_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslti.h"] - fn __lsx_vslti_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslti.w"] - fn __lsx_vslti_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslti.d"] - fn __lsx_vslti_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslt.bu"] - fn __lsx_vslt_bu(a: __v16u8, b: __v16u8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslt.hu"] - fn __lsx_vslt_hu(a: __v8u16, b: __v8u16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslt.wu"] - fn __lsx_vslt_wu(a: __v4u32, b: __v4u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslt.du"] - fn __lsx_vslt_du(a: __v2u64, b: __v2u64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslti.bu"] - fn __lsx_vslti_bu(a: __v16u8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslti.hu"] - fn __lsx_vslti_hu(a: __v8u16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslti.wu"] - fn __lsx_vslti_wu(a: __v4u32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslti.du"] - fn __lsx_vslti_du(a: __v2u64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsle.b"] - fn __lsx_vsle_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsle.h"] - fn __lsx_vsle_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsle.w"] - fn __lsx_vsle_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsle.d"] - fn __lsx_vsle_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslei.b"] - fn __lsx_vslei_b(a: __v16i8, b: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslei.h"] - fn __lsx_vslei_h(a: __v8i16, b: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslei.w"] - fn __lsx_vslei_w(a: __v4i32, b: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslei.d"] - fn __lsx_vslei_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsle.bu"] - fn __lsx_vsle_bu(a: __v16u8, b: __v16u8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsle.hu"] - fn __lsx_vsle_hu(a: __v8u16, b: __v8u16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsle.wu"] - fn __lsx_vsle_wu(a: __v4u32, b: __v4u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsle.du"] - fn __lsx_vsle_du(a: __v2u64, b: __v2u64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vslei.bu"] - fn __lsx_vslei_bu(a: __v16u8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vslei.hu"] - fn __lsx_vslei_hu(a: __v8u16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vslei.wu"] - fn __lsx_vslei_wu(a: __v4u32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vslei.du"] - fn __lsx_vslei_du(a: __v2u64, b: u32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vsat.b"] fn __lsx_vsat_b(a: __v16i8, b: u32) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vsat.h"] @@ -331,30 +91,6 @@ unsafe extern "unadjusted" { fn __lsx_vsat_wu(a: __v4u32, b: u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vsat.du"] fn __lsx_vsat_du(a: __v2u64, b: u32) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vadda.b"] - fn __lsx_vadda_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vadda.h"] - fn __lsx_vadda_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vadda.w"] - fn __lsx_vadda_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vadda.d"] - fn __lsx_vadda_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsadd.b"] - fn __lsx_vsadd_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vsadd.h"] - fn __lsx_vsadd_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vsadd.w"] - fn __lsx_vsadd_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vsadd.d"] - fn __lsx_vsadd_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vsadd.bu"] - fn __lsx_vsadd_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vsadd.hu"] - fn __lsx_vsadd_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vsadd.wu"] - fn __lsx_vsadd_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vsadd.du"] - fn __lsx_vsadd_du(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vavg.b"] fn __lsx_vavg_b(a: __v16i8, b: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vavg.h"] @@ -387,78 +123,6 @@ unsafe extern "unadjusted" { fn __lsx_vavgr_wu(a: __v4u32, b: __v4u32) -> __v4u32; #[link_name = "llvm.loongarch.lsx.vavgr.du"] fn __lsx_vavgr_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vssub.b"] - fn __lsx_vssub_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vssub.h"] - fn __lsx_vssub_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vssub.w"] - fn __lsx_vssub_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vssub.d"] - fn __lsx_vssub_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vssub.bu"] - fn __lsx_vssub_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vssub.hu"] - fn __lsx_vssub_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vssub.wu"] - fn __lsx_vssub_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vssub.du"] - fn __lsx_vssub_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vabsd.b"] - fn __lsx_vabsd_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vabsd.h"] - fn __lsx_vabsd_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vabsd.w"] - fn __lsx_vabsd_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vabsd.d"] - fn __lsx_vabsd_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vabsd.bu"] - fn __lsx_vabsd_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vabsd.hu"] - fn __lsx_vabsd_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vabsd.wu"] - fn __lsx_vabsd_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vabsd.du"] - fn __lsx_vabsd_du(a: __v2u64, b: __v2u64) -> __v2u64; - #[link_name = "llvm.loongarch.lsx.vmul.b"] - fn __lsx_vmul_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmul.h"] - fn __lsx_vmul_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmul.w"] - fn __lsx_vmul_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmul.d"] - fn __lsx_vmul_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmadd.b"] - fn __lsx_vmadd_b(a: __v16i8, b: __v16i8, c: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmadd.h"] - fn __lsx_vmadd_h(a: __v8i16, b: __v8i16, c: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmadd.w"] - fn __lsx_vmadd_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmadd.d"] - fn __lsx_vmadd_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmsub.b"] - fn __lsx_vmsub_b(a: __v16i8, b: __v16i8, c: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmsub.h"] - fn __lsx_vmsub_h(a: __v8i16, b: __v8i16, c: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmsub.w"] - fn __lsx_vmsub_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmsub.d"] - fn __lsx_vmsub_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vdiv.b"] - fn __lsx_vdiv_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vdiv.h"] - fn __lsx_vdiv_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vdiv.w"] - fn __lsx_vdiv_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vdiv.d"] - fn __lsx_vdiv_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vdiv.bu"] - fn __lsx_vdiv_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vdiv.hu"] - fn __lsx_vdiv_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vdiv.wu"] - fn __lsx_vdiv_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vdiv.du"] - fn __lsx_vdiv_du(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vhaddw.h.b"] fn __lsx_vhaddw_h_b(a: __v16i8, b: __v16i8) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vhaddw.w.h"] @@ -483,22 +147,6 @@ unsafe extern "unadjusted" { fn __lsx_vhsubw_wu_hu(a: __v8u16, b: __v8u16) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vhsubw.du.wu"] fn __lsx_vhsubw_du_wu(a: __v4u32, b: __v4u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmod.b"] - fn __lsx_vmod_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vmod.h"] - fn __lsx_vmod_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vmod.w"] - fn __lsx_vmod_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vmod.d"] - fn __lsx_vmod_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vmod.bu"] - fn __lsx_vmod_bu(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vmod.hu"] - fn __lsx_vmod_hu(a: __v8u16, b: __v8u16) -> __v8u16; - #[link_name = "llvm.loongarch.lsx.vmod.wu"] - fn __lsx_vmod_wu(a: __v4u32, b: __v4u32) -> __v4u32; - #[link_name = "llvm.loongarch.lsx.vmod.du"] - fn __lsx_vmod_du(a: __v2u64, b: __v2u64) -> __v2u64; #[link_name = "llvm.loongarch.lsx.vreplve.b"] fn __lsx_vreplve_b(a: __v16i8, b: i32) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vreplve.h"] @@ -507,46 +155,6 @@ unsafe extern "unadjusted" { fn __lsx_vreplve_w(a: __v4i32, b: i32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vreplve.d"] fn __lsx_vreplve_d(a: __v2i64, b: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vreplvei.b"] - fn __lsx_vreplvei_b(a: __v16i8, b: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vreplvei.h"] - fn __lsx_vreplvei_h(a: __v8i16, b: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vreplvei.w"] - fn __lsx_vreplvei_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vreplvei.d"] - fn __lsx_vreplvei_d(a: __v2i64, b: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpickev.b"] - fn __lsx_vpickev_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vpickev.h"] - fn __lsx_vpickev_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vpickev.w"] - fn __lsx_vpickev_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vpickev.d"] - fn __lsx_vpickev_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpickod.b"] - fn __lsx_vpickod_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vpickod.h"] - fn __lsx_vpickod_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vpickod.w"] - fn __lsx_vpickod_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vpickod.d"] - fn __lsx_vpickod_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vilvh.b"] - fn __lsx_vilvh_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vilvh.h"] - fn __lsx_vilvh_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vilvh.w"] - fn __lsx_vilvh_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vilvh.d"] - fn __lsx_vilvh_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vilvl.b"] - fn __lsx_vilvl_b(a: __v16i8, b: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vilvl.h"] - fn __lsx_vilvl_h(a: __v8i16, b: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vilvl.w"] - fn __lsx_vilvl_w(a: __v4i32, b: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vilvl.d"] - fn __lsx_vilvl_d(a: __v2i64, b: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vpackev.b"] fn __lsx_vpackev_b(a: __v16i8, b: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vpackev.h"] @@ -569,20 +177,12 @@ unsafe extern "unadjusted" { fn __lsx_vshuf_w(a: __v4i32, b: __v4i32, c: __v4i32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vshuf.d"] fn __lsx_vshuf_d(a: __v2i64, b: __v2i64, c: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vand.v"] - fn __lsx_vand_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vandi.b"] fn __lsx_vandi_b(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vor.v"] - fn __lsx_vor_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vori.b"] fn __lsx_vori_b(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vnor.v"] - fn __lsx_vnor_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vnori.b"] fn __lsx_vnori_b(a: __v16u8, b: u32) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vxor.v"] - fn __lsx_vxor_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vxori.b"] fn __lsx_vxori_b(a: __v16u8, b: u32) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vbitsel.v"] @@ -595,22 +195,6 @@ unsafe extern "unadjusted" { fn __lsx_vshuf4i_h(a: __v8i16, b: u32) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vshuf4i.w"] fn __lsx_vshuf4i_w(a: __v4i32, b: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vreplgr2vr.b"] - fn __lsx_vreplgr2vr_b(a: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vreplgr2vr.h"] - fn __lsx_vreplgr2vr_h(a: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vreplgr2vr.w"] - fn __lsx_vreplgr2vr_w(a: i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vreplgr2vr.d"] - fn __lsx_vreplgr2vr_d(a: i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpcnt.b"] - fn __lsx_vpcnt_b(a: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vpcnt.h"] - fn __lsx_vpcnt_h(a: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vpcnt.w"] - fn __lsx_vpcnt_w(a: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vpcnt.d"] - fn __lsx_vpcnt_d(a: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vclo.b"] fn __lsx_vclo_b(a: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vclo.h"] @@ -619,54 +203,6 @@ unsafe extern "unadjusted" { fn __lsx_vclo_w(a: __v4i32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vclo.d"] fn __lsx_vclo_d(a: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vclz.b"] - fn __lsx_vclz_b(a: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vclz.h"] - fn __lsx_vclz_h(a: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vclz.w"] - fn __lsx_vclz_w(a: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vclz.d"] - fn __lsx_vclz_d(a: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.b"] - fn __lsx_vpickve2gr_b(a: __v16i8, b: u32) -> i32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.h"] - fn __lsx_vpickve2gr_h(a: __v8i16, b: u32) -> i32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.w"] - fn __lsx_vpickve2gr_w(a: __v4i32, b: u32) -> i32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.d"] - fn __lsx_vpickve2gr_d(a: __v2i64, b: u32) -> i64; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.bu"] - fn __lsx_vpickve2gr_bu(a: __v16i8, b: u32) -> u32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.hu"] - fn __lsx_vpickve2gr_hu(a: __v8i16, b: u32) -> u32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.wu"] - fn __lsx_vpickve2gr_wu(a: __v4i32, b: u32) -> u32; - #[link_name = "llvm.loongarch.lsx.vpickve2gr.du"] - fn __lsx_vpickve2gr_du(a: __v2i64, b: u32) -> u64; - #[link_name = "llvm.loongarch.lsx.vinsgr2vr.b"] - fn __lsx_vinsgr2vr_b(a: __v16i8, b: i32, c: u32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vinsgr2vr.h"] - fn __lsx_vinsgr2vr_h(a: __v8i16, b: i32, c: u32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vinsgr2vr.w"] - fn __lsx_vinsgr2vr_w(a: __v4i32, b: i32, c: u32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vinsgr2vr.d"] - fn __lsx_vinsgr2vr_d(a: __v2i64, b: i64, c: u32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vfadd.s"] - fn __lsx_vfadd_s(a: __v4f32, b: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfadd.d"] - fn __lsx_vfadd_d(a: __v2f64, b: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfsub.s"] - fn __lsx_vfsub_s(a: __v4f32, b: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfsub.d"] - fn __lsx_vfsub_d(a: __v2f64, b: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfmul.s"] - fn __lsx_vfmul_s(a: __v4f32, b: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfmul.d"] - fn __lsx_vfmul_d(a: __v2f64, b: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfdiv.s"] - fn __lsx_vfdiv_s(a: __v4f32, b: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfdiv.d"] - fn __lsx_vfdiv_d(a: __v2f64, b: __v2f64) -> __v2f64; #[link_name = "llvm.loongarch.lsx.vfcvt.h.s"] fn __lsx_vfcvt_h_s(a: __v4f32, b: __v4f32) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vfcvt.s.d"] @@ -691,10 +227,6 @@ unsafe extern "unadjusted" { fn __lsx_vfclass_s(a: __v4f32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vfclass.d"] fn __lsx_vfclass_d(a: __v2f64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vfsqrt.s"] - fn __lsx_vfsqrt_s(a: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfsqrt.d"] - fn __lsx_vfsqrt_d(a: __v2f64) -> __v2f64; #[link_name = "llvm.loongarch.lsx.vfrecip.s"] fn __lsx_vfrecip_s(a: __v4f32) -> __v4f32; #[link_name = "llvm.loongarch.lsx.vfrecip.d"] @@ -751,16 +283,6 @@ unsafe extern "unadjusted" { fn __lsx_vffint_s_wu(a: __v4u32) -> __v4f32; #[link_name = "llvm.loongarch.lsx.vffint.d.lu"] fn __lsx_vffint_d_lu(a: __v2u64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vandn.v"] - fn __lsx_vandn_v(a: __v16u8, b: __v16u8) -> __v16u8; - #[link_name = "llvm.loongarch.lsx.vneg.b"] - fn __lsx_vneg_b(a: __v16i8) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vneg.h"] - fn __lsx_vneg_h(a: __v8i16) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vneg.w"] - fn __lsx_vneg_w(a: __v4i32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vneg.d"] - fn __lsx_vneg_d(a: __v2i64) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vmuh.b"] fn __lsx_vmuh_b(a: __v16i8, b: __v16i8) -> __v16i8; #[link_name = "llvm.loongarch.lsx.vmuh.h"] @@ -887,22 +409,6 @@ unsafe extern "unadjusted" { fn __lsx_vsigncov_w(a: __v4i32, b: __v4i32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vsigncov.d"] fn __lsx_vsigncov_d(a: __v2i64, b: __v2i64) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vfmadd.s"] - fn __lsx_vfmadd_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfmadd.d"] - fn __lsx_vfmadd_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfmsub.s"] - fn __lsx_vfmsub_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfmsub.d"] - fn __lsx_vfmsub_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfnmadd.s"] - fn __lsx_vfnmadd_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfnmadd.d"] - fn __lsx_vfnmadd_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64; - #[link_name = "llvm.loongarch.lsx.vfnmsub.s"] - fn __lsx_vfnmsub_s(a: __v4f32, b: __v4f32, c: __v4f32) -> __v4f32; - #[link_name = "llvm.loongarch.lsx.vfnmsub.d"] - fn __lsx_vfnmsub_d(a: __v2f64, b: __v2f64, c: __v2f64) -> __v2f64; #[link_name = "llvm.loongarch.lsx.vftintrne.w.s"] fn __lsx_vftintrne_w_s(a: __v4f32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vftintrne.l.d"] @@ -1323,8 +829,6 @@ unsafe extern "unadjusted" { fn __lsx_vssrln_h_w(a: __v4i32, b: __v4i32) -> __v8i16; #[link_name = "llvm.loongarch.lsx.vssrln.w.d"] fn __lsx_vssrln_w_d(a: __v2i64, b: __v2i64) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vorn.v"] - fn __lsx_vorn_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vldi"] fn __lsx_vldi(a: i32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vshuf.b"] @@ -1443,2526 +947,758 @@ unsafe extern "unadjusted" { fn __lsx_vfcmp_sune_s(a: __v4f32, b: __v4f32) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vfcmp.sun.s"] fn __lsx_vfcmp_sun_s(a: __v4f32, b: __v4f32) -> __v4i32; - #[link_name = "llvm.loongarch.lsx.vrepli.b"] - fn __lsx_vrepli_b(a: i32) -> __v16i8; - #[link_name = "llvm.loongarch.lsx.vrepli.d"] - fn __lsx_vrepli_d(a: i32) -> __v2i64; - #[link_name = "llvm.loongarch.lsx.vrepli.h"] - fn __lsx_vrepli_h(a: i32) -> __v8i16; - #[link_name = "llvm.loongarch.lsx.vrepli.w"] - fn __lsx_vrepli_w(a: i32) -> __v4i32; } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsll_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsll_b(transmute(a), transmute(b))) } +pub fn lsx_vsrar_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrar_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsll_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsll_h(transmute(a), transmute(b))) } +pub fn lsx_vsrar_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrar_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsll_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsll_w(transmute(a), transmute(b))) } +pub fn lsx_vsrar_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrar_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsll_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsll_d(transmute(a), transmute(b))) } +pub fn lsx_vsrar_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrar_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslli_b(a: m128i) -> m128i { +pub fn lsx_vsrari_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vslli_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vsrari_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslli_h(a: m128i) -> m128i { +pub fn lsx_vsrari_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vslli_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vsrari_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslli_w(a: m128i) -> m128i { +pub fn lsx_vsrari_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslli_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vsrari_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslli_d(a: m128i) -> m128i { +pub fn lsx_vsrari_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vslli_d(transmute(a), IMM6)) } + unsafe { transmute(__lsx_vsrari_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsra_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsra_b(transmute(a), transmute(b))) } +pub fn lsx_vsrlr_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrlr_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsra_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsra_h(transmute(a), transmute(b))) } +pub fn lsx_vsrlr_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrlr_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsra_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsra_w(transmute(a), transmute(b))) } +pub fn lsx_vsrlr_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrlr_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsra_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsra_d(transmute(a), transmute(b))) } +pub fn lsx_vsrlr_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vsrlr_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrai_b(a: m128i) -> m128i { +pub fn lsx_vsrlri_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsrai_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vsrlri_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrai_h(a: m128i) -> m128i { +pub fn lsx_vsrlri_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsrai_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vsrlri_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrai_w(a: m128i) -> m128i { +pub fn lsx_vsrlri_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsrai_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vsrlri_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrai_d(a: m128i) -> m128i { +pub fn lsx_vsrlri_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsrai_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrar_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrar_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrar_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrar_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrar_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrar_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrar_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrar_d(transmute(a), transmute(b))) } + unsafe { transmute(__lsx_vsrlri_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrari_b(a: m128i) -> m128i { +pub fn lsx_vbitclri_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsrari_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vbitclri_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrari_h(a: m128i) -> m128i { +pub fn lsx_vbitclri_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsrari_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vbitclri_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrari_w(a: m128i) -> m128i { +pub fn lsx_vbitclri_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsrari_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vbitclri_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrari_d(a: m128i) -> m128i { +pub fn lsx_vbitclri_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsrari_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrl_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrl_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrl_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrl_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrl_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrl_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrl_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrl_d(transmute(a), transmute(b))) } + unsafe { transmute(__lsx_vbitclri_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrli_b(a: m128i) -> m128i { +pub fn lsx_vbitseti_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsrli_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vbitseti_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrli_h(a: m128i) -> m128i { +pub fn lsx_vbitseti_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsrli_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vbitseti_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrli_w(a: m128i) -> m128i { +pub fn lsx_vbitseti_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsrli_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vbitseti_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrli_d(a: m128i) -> m128i { +pub fn lsx_vbitseti_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsrli_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlr_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrlr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlr_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrlr_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlr_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrlr_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlr_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsrlr_d(transmute(a), transmute(b))) } + unsafe { transmute(__lsx_vbitseti_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlri_b(a: m128i) -> m128i { +pub fn lsx_vbitrevi_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsrlri_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vbitrevi_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlri_h(a: m128i) -> m128i { +pub fn lsx_vbitrevi_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsrlri_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vbitrevi_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlri_w(a: m128i) -> m128i { +pub fn lsx_vbitrevi_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsrlri_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vbitrevi_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsrlri_d(a: m128i) -> m128i { +pub fn lsx_vbitrevi_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsrlri_d(transmute(a), IMM6)) } + unsafe { transmute(__lsx_vbitrevi_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclr_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitclr_b(transmute(a), transmute(b))) } +pub fn lsx_vsubi_bu(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclr_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitclr_h(transmute(a), transmute(b))) } +pub fn lsx_vsubi_hu(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclr_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitclr_w(transmute(a), transmute(b))) } +pub fn lsx_vsubi_wu(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclr_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitclr_d(transmute(a), transmute(b))) } +pub fn lsx_vsubi_du(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclri_b(a: m128i) -> m128i { +pub fn lsx_vsat_b(a: m128i) -> m128i { static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vbitclri_b(transmute(a), IMM3)) } + unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclri_h(a: m128i) -> m128i { +pub fn lsx_vsat_h(a: m128i) -> m128i { static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vbitclri_h(transmute(a), IMM4)) } + unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclri_w(a: m128i) -> m128i { +pub fn lsx_vsat_w(a: m128i) -> m128i { static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vbitclri_w(transmute(a), IMM5)) } + unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitclri_d(a: m128i) -> m128i { +pub fn lsx_vsat_d(a: m128i) -> m128i { static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vbitclri_d(transmute(a), IMM6)) } + unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitset_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitset_b(transmute(a), transmute(b))) } +pub fn lsx_vsat_bu(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM3, 3); + unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitset_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitset_h(transmute(a), transmute(b))) } +pub fn lsx_vsat_hu(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM4, 4); + unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitset_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitset_w(transmute(a), transmute(b))) } +pub fn lsx_vsat_wu(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM5, 5); + unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitset_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitset_d(transmute(a), transmute(b))) } +pub fn lsx_vsat_du(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM6, 6); + unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseti_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vbitseti_b(transmute(a), IMM3)) } +pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseti_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vbitseti_h(transmute(a), IMM4)) } +pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseti_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vbitseti_w(transmute(a), IMM5)) } +pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseti_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vbitseti_d(transmute(a), IMM6)) } +pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrev_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitrev_b(transmute(a), transmute(b))) } +pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrev_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitrev_h(transmute(a), transmute(b))) } +pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrev_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitrev_w(transmute(a), transmute(b))) } +pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrev_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vbitrev_d(transmute(a), transmute(b))) } +pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrevi_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vbitrevi_b(transmute(a), IMM3)) } +pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrevi_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vbitrevi_h(transmute(a), IMM4)) } +pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrevi_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vbitrevi_w(transmute(a), IMM5)) } +pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitrevi_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vbitrevi_d(transmute(a), IMM6)) } +pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadd_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadd_b(transmute(a), transmute(b))) } +pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadd_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadd_h(transmute(a), transmute(b))) } +pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadd_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadd_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vaddi_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vaddi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vaddi_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vaddi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vaddi_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vaddi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vaddi_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vaddi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsub_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsub_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsub_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsub_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsub_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsub_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsub_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsub_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsubi_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsubi_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsubi_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsubi_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmaxi_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmaxi_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmaxi_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmaxi_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmax_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmax_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmaxi_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmaxi_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmaxi_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmaxi_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmaxi_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmini_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmini_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmini_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vmini_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmin_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmin_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmini_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmini_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmini_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmini_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vmini_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseq_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vseq_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseq_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vseq_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseq_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vseq_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseq_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vseq_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseqi_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vseqi_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseqi_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vseqi_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseqi_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vseqi_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vseqi_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vseqi_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslti_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslti_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslti_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslti_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslt_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vslt_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslti_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslti_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslti_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslti_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslti_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_b(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslei_b(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_h(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslei_h(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_w(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslei_w(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_d(a: m128i) -> m128i { - static_assert_simm_bits!(IMM_S5, 5); - unsafe { transmute(__lsx_vslei_d(transmute(a), IMM_S5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsle_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsle_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslei_bu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslei_hu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslei_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vslei_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vslei_du(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_bu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_hu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_wu(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM5, 5); - unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsat_du(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM6, 6); - unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadda_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadda_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadda_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadda_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadda_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadda_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vsadd_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vsadd_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vssub_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vssub_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vabsd_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vabsd_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmul_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmul_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmul_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmul_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmul_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmul_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmul_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmul_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmadd_b(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmadd_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmadd_h(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmadd_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmadd_w(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmadd_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmadd_d(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmsub_b(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmsub_b(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmsub_h(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmsub_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmsub_w(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmsub_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmsub_d(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vmsub_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vdiv_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vdiv_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_bu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_bu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_hu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_hu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_wu(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_wu(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vmod_du(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vmod_du(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i { - unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i { - unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i { - unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i { - unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplvei_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vreplvei_b(transmute(a), IMM4)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplvei_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vreplvei_h(transmute(a), IMM3)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplvei_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lsx_vreplvei_w(transmute(a), IMM2)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplvei_d(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lsx_vreplvei_d(transmute(a), IMM1)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickev_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickev_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickev_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickev_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickev_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickod_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickod_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickod_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickod_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpickod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvh_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvh_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvh_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvh_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvh_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvh_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvh_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvh_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvl_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvl_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvl_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvl_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvl_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvl_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vilvl_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vilvl_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackev_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackev_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackev_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackev_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackev_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackev_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackev_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackev_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackod_b(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackod_b(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackod_h(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackod_h(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackod_w(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackod_w(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpackod_d(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vpackod_d(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vand_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vand_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vandi_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vor_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vori_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vnor_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vnor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vnori_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vxor_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vxor_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vxori_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) } +pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i { - unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) } +pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vbitseli_b(a: m128i, b: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) } +pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf4i_b(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vshuf4i_b(transmute(a), IMM8)) } +pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf4i_h(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vshuf4i_h(transmute(a), IMM8)) } +pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vshuf4i_w(a: m128i) -> m128i { - static_assert_uimm_bits!(IMM8, 8); - unsafe { transmute(__lsx_vshuf4i_w(transmute(a), IMM8)) } +pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplgr2vr_b(a: i32) -> m128i { - unsafe { transmute(__lsx_vreplgr2vr_b(transmute(a))) } +pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplgr2vr_h(a: i32) -> m128i { - unsafe { transmute(__lsx_vreplgr2vr_h(transmute(a))) } +pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplgr2vr_w(a: i32) -> m128i { - unsafe { transmute(__lsx_vreplgr2vr_w(transmute(a))) } +pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vreplgr2vr_d(a: i64) -> m128i { - unsafe { transmute(__lsx_vreplgr2vr_d(transmute(a))) } +pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpcnt_b(a: m128i) -> m128i { - unsafe { transmute(__lsx_vpcnt_b(transmute(a))) } +pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpcnt_h(a: m128i) -> m128i { - unsafe { transmute(__lsx_vpcnt_h(transmute(a))) } +pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpcnt_w(a: m128i) -> m128i { - unsafe { transmute(__lsx_vpcnt_w(transmute(a))) } +pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpcnt_d(a: m128i) -> m128i { - unsafe { transmute(__lsx_vpcnt_d(transmute(a))) } +pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclo_b(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclo_b(transmute(a))) } +pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i { + unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclo_h(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclo_h(transmute(a))) } +pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i { + unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclo_w(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclo_w(transmute(a))) } +pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i { + unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclo_d(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclo_d(transmute(a))) } +pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i { + unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclz_b(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclz_b(transmute(a))) } +pub fn lsx_vpackev_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vpackev_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclz_h(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclz_h(transmute(a))) } +pub fn lsx_vpackev_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vpackev_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclz_w(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclz_w(transmute(a))) } +pub fn lsx_vpackev_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vpackev_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vclz_d(a: m128i) -> m128i { - unsafe { transmute(__lsx_vclz_d(transmute(a))) } +pub fn lsx_vpackev_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vpackev_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_b(a: m128i) -> i32 { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vpickve2gr_b(transmute(a), IMM4)) } +pub fn lsx_vpackod_b(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vpackod_b(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_h(a: m128i) -> i32 { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vpickve2gr_h(transmute(a), IMM3)) } +pub fn lsx_vpackod_h(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vpackod_h(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_w(a: m128i) -> i32 { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lsx_vpickve2gr_w(transmute(a), IMM2)) } +pub fn lsx_vpackod_w(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vpackod_w(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_d(a: m128i) -> i64 { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lsx_vpickve2gr_d(transmute(a), IMM1)) } +pub fn lsx_vpackod_d(a: m128i, b: m128i) -> m128i { + unsafe { transmute(__lsx_vpackod_d(transmute(a), transmute(b))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_bu(a: m128i) -> u32 { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vpickve2gr_bu(transmute(a), IMM4)) } +pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i { + unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_hu(a: m128i) -> u32 { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vpickve2gr_hu(transmute(a), IMM3)) } +pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i { + unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_wu(a: m128i) -> u32 { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lsx_vpickve2gr_wu(transmute(a), IMM2)) } +pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i { + unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vpickve2gr_du(a: m128i) -> u64 { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lsx_vpickve2gr_du(transmute(a), IMM1)) } +pub fn lsx_vandi_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vinsgr2vr_b(a: m128i, b: i32) -> m128i { - static_assert_uimm_bits!(IMM4, 4); - unsafe { transmute(__lsx_vinsgr2vr_b(transmute(a), transmute(b), IMM4)) } +pub fn lsx_vori_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vinsgr2vr_h(a: m128i, b: i32) -> m128i { - static_assert_uimm_bits!(IMM3, 3); - unsafe { transmute(__lsx_vinsgr2vr_h(transmute(a), transmute(b), IMM3)) } +pub fn lsx_vnori_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vinsgr2vr_w(a: m128i, b: i32) -> m128i { - static_assert_uimm_bits!(IMM2, 2); - unsafe { transmute(__lsx_vinsgr2vr_w(transmute(a), transmute(b), IMM2)) } +pub fn lsx_vxori_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vinsgr2vr_d(a: m128i, b: i64) -> m128i { - static_assert_uimm_bits!(IMM1, 1); - unsafe { transmute(__lsx_vinsgr2vr_d(transmute(a), transmute(b), IMM1)) } +pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i { + unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfadd_s(a: m128, b: m128) -> m128 { - unsafe { transmute(__lsx_vfadd_s(transmute(a), transmute(b))) } +pub fn lsx_vbitseli_b(a: m128i, b: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfadd_d(a: m128d, b: m128d) -> m128d { - unsafe { transmute(__lsx_vfadd_d(transmute(a), transmute(b))) } +pub fn lsx_vshuf4i_b(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vshuf4i_b(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfsub_s(a: m128, b: m128) -> m128 { - unsafe { transmute(__lsx_vfsub_s(transmute(a), transmute(b))) } +pub fn lsx_vshuf4i_h(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vshuf4i_h(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfsub_d(a: m128d, b: m128d) -> m128d { - unsafe { transmute(__lsx_vfsub_d(transmute(a), transmute(b))) } +pub fn lsx_vshuf4i_w(a: m128i) -> m128i { + static_assert_uimm_bits!(IMM8, 8); + unsafe { transmute(__lsx_vshuf4i_w(transmute(a), IMM8)) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmul_s(a: m128, b: m128) -> m128 { - unsafe { transmute(__lsx_vfmul_s(transmute(a), transmute(b))) } +pub fn lsx_vclo_b(a: m128i) -> m128i { + unsafe { transmute(__lsx_vclo_b(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmul_d(a: m128d, b: m128d) -> m128d { - unsafe { transmute(__lsx_vfmul_d(transmute(a), transmute(b))) } +pub fn lsx_vclo_h(a: m128i) -> m128i { + unsafe { transmute(__lsx_vclo_h(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfdiv_s(a: m128, b: m128) -> m128 { - unsafe { transmute(__lsx_vfdiv_s(transmute(a), transmute(b))) } +pub fn lsx_vclo_w(a: m128i) -> m128i { + unsafe { transmute(__lsx_vclo_w(transmute(a))) } } #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfdiv_d(a: m128d, b: m128d) -> m128d { - unsafe { transmute(__lsx_vfdiv_d(transmute(a), transmute(b))) } +pub fn lsx_vclo_d(a: m128i) -> m128i { + unsafe { transmute(__lsx_vclo_d(transmute(a))) } } #[inline] @@ -4049,20 +1785,6 @@ pub fn lsx_vfclass_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vfclass_d(transmute(a))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfsqrt_s(a: m128) -> m128 { - unsafe { transmute(__lsx_vfsqrt_s(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfsqrt_d(a: m128d) -> m128d { - unsafe { transmute(__lsx_vfsqrt_d(transmute(a))) } -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4259,41 +1981,6 @@ pub fn lsx_vffint_d_lu(a: m128i) -> m128d { unsafe { transmute(__lsx_vffint_d_lu(transmute(a))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vandn_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vandn_v(transmute(a), transmute(b))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vneg_b(a: m128i) -> m128i { - unsafe { transmute(__lsx_vneg_b(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vneg_h(a: m128i) -> m128i { - unsafe { transmute(__lsx_vneg_h(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vneg_w(a: m128i) -> m128i { - unsafe { transmute(__lsx_vneg_w(transmute(a))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vneg_d(a: m128i) -> m128i { - unsafe { transmute(__lsx_vneg_d(transmute(a))) } -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4765,62 +2452,6 @@ pub fn lsx_vsigncov_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsigncov_d(transmute(a), transmute(b))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmadd_s(a: m128, b: m128, c: m128) -> m128 { - unsafe { transmute(__lsx_vfmadd_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmadd_d(a: m128d, b: m128d, c: m128d) -> m128d { - unsafe { transmute(__lsx_vfmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmsub_s(a: m128, b: m128, c: m128) -> m128 { - unsafe { transmute(__lsx_vfmsub_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfmsub_d(a: m128d, b: m128d, c: m128d) -> m128d { - unsafe { transmute(__lsx_vfmsub_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfnmadd_s(a: m128, b: m128, c: m128) -> m128 { - unsafe { transmute(__lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfnmadd_d(a: m128d, b: m128d, c: m128d) -> m128d { - unsafe { transmute(__lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfnmsub_s(a: m128, b: m128, c: m128) -> m128 { - unsafe { transmute(__lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c))) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vfnmsub_d(a: m128d, b: m128d, c: m128d) -> m128d { - unsafe { transmute(__lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c))) } -} - #[inline] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5052,7 +2683,7 @@ pub fn lsx_vfrintrm_d(a: m128d) -> m128d { pub unsafe fn lsx_vstelm_b(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM4, 4); - transmute(__lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)) + __lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4) } #[inline] @@ -5062,7 +2693,7 @@ pub unsafe fn lsx_vstelm_b(a: m128i, mem_add pub unsafe fn lsx_vstelm_h(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM3, 3); - transmute(__lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)) + __lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3) } #[inline] @@ -5072,7 +2703,7 @@ pub unsafe fn lsx_vstelm_h(a: m128i, mem_add pub unsafe fn lsx_vstelm_w(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM2, 2); - transmute(__lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)) + __lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2) } #[inline] @@ -5082,7 +2713,7 @@ pub unsafe fn lsx_vstelm_w(a: m128i, mem_add pub unsafe fn lsx_vstelm_d(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM1, 1); - transmute(__lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)) + __lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1) } #[inline] @@ -6376,7 +4007,7 @@ pub unsafe fn lsx_vld(mem_addr: *const i8) -> m128i { #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vst(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S12, 12); - transmute(__lsx_vst(transmute(a), mem_addr, IMM_S12)) + __lsx_vst(transmute(a), mem_addr, IMM_S12) } #[inline] @@ -6421,13 +4052,6 @@ pub fn lsx_vssrln_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrln_w_d(transmute(a), transmute(b))) } } -#[inline] -#[target_feature(enable = "lsx")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vorn_v(a: m128i, b: m128i) -> m128i { - unsafe { transmute(__lsx_vorn_v(transmute(a), transmute(b))) } -} - #[inline] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(0)] @@ -6455,7 +4079,7 @@ pub unsafe fn lsx_vldx(mem_addr: *const i8, b: i64) -> m128i { #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vstx(a: m128i, mem_addr: *mut i8, b: i64) { - transmute(__lsx_vstx(transmute(a), mem_addr, transmute(b))) + __lsx_vstx(transmute(a), mem_addr, transmute(b)) } #[inline] @@ -6842,39 +4466,3 @@ pub fn lsx_vfcmp_sune_s(a: m128, b: m128) -> m128i { pub fn lsx_vfcmp_sun_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sun_s(transmute(a), transmute(b))) } } - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrepli_b() -> m128i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lsx_vrepli_b(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrepli_d() -> m128i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lsx_vrepli_d(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrepli_h() -> m128i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lsx_vrepli_h(IMM_S10)) } -} - -#[inline] -#[target_feature(enable = "lsx")] -#[rustc_legacy_const_generics(0)] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn lsx_vrepli_w() -> m128i { - static_assert_simm_bits!(IMM_S10, 10); - unsafe { transmute(__lsx_vrepli_w(IMM_S10)) } -} diff --git a/stdarch/crates/core_arch/src/loongarch64/lsx/mod.rs b/stdarch/crates/core_arch/src/loongarch64/lsx/mod.rs index 67a08985a9637..0d353746ea859 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lsx/mod.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lsx/mod.rs @@ -16,6 +16,13 @@ mod generated; #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub use self::generated::*; +#[rustfmt::skip] +mod portable; + +#[rustfmt::skip] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub use self::portable::*; + #[rustfmt::skip] #[cfg(test)] mod tests; diff --git a/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs b/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs new file mode 100644 index 0000000000000..2d24256838b21 --- /dev/null +++ b/stdarch/crates/core_arch/src/loongarch64/lsx/portable.rs @@ -0,0 +1,387 @@ +//! LoongArch64 LSX intrinsics - intrinsics::simd implementation + +use super::super::{simd as ls, simd::*, *}; +use crate::core_arch::simd::{self as cs, *}; +use crate::intrinsics::simd as is; +use crate::mem::transmute; + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickev_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickev_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 4, 6, 8, 10, 12, 14]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickev_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2, 4, 6]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickev_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickod_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickod_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 5, 7, 9, 11, 13, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickod_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3, 5, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +const unsafe fn simd_pickod_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvh_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvh_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [4, 12, 5, 13, 6, 14, 7, 15]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvh_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [2, 6, 3, 7]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvh_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [1, 3]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvl_b(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvl_h(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 8, 1, 9, 2, 10, 3, 11]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvl_w(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 4, 1, 5]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_ilvl_d(a: T, b: T) -> T { + simd_shuffle!(b, a, [0, 2]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_replvei_b(a: T) -> T { + simd_shuffle!(a, a, [I, I, I, I, I, I, I, I, I, I, I, I, I, I, I, I]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_replvei_h(a: T) -> T { + simd_shuffle!(a, a, [I, I, I, I, I, I, I, I]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_replvei_w(a: T) -> T { + simd_shuffle!(a, a, [I, I, I, I]) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_replvei_d(a: T) -> T { + simd_shuffle!(a, a, [I, I]) +} + +impl_vv!("lsx", lsx_vpcnt_b, is::simd_ctpop, m128i, i8x16); +impl_vv!("lsx", lsx_vpcnt_h, is::simd_ctpop, m128i, i16x8); +impl_vv!("lsx", lsx_vpcnt_w, is::simd_ctpop, m128i, i32x4); +impl_vv!("lsx", lsx_vpcnt_d, is::simd_ctpop, m128i, i64x2); +impl_vv!("lsx", lsx_vclz_b, is::simd_ctlz, m128i, i8x16); +impl_vv!("lsx", lsx_vclz_h, is::simd_ctlz, m128i, i16x8); +impl_vv!("lsx", lsx_vclz_w, is::simd_ctlz, m128i, i32x4); +impl_vv!("lsx", lsx_vclz_d, is::simd_ctlz, m128i, i64x2); +impl_vv!("lsx", lsx_vneg_b, is::simd_neg, m128i, i8x16); +impl_vv!("lsx", lsx_vneg_h, is::simd_neg, m128i, i16x8); +impl_vv!("lsx", lsx_vneg_w, is::simd_neg, m128i, i32x4); +impl_vv!("lsx", lsx_vneg_d, is::simd_neg, m128i, i64x2); +impl_vv!("lsx", lsx_vfsqrt_s, is::simd_fsqrt, m128, f32x4); +impl_vv!("lsx", lsx_vfsqrt_d, is::simd_fsqrt, m128d, f64x2); + +impl_gv!("lsx", lsx_vreplgr2vr_b, ls::simd_splat, m128i, i8x16, i32); +impl_gv!("lsx", lsx_vreplgr2vr_h, ls::simd_splat, m128i, i16x8, i32); +impl_gv!("lsx", lsx_vreplgr2vr_w, ls::simd_splat, m128i, i32x4, i32); +impl_gv!("lsx", lsx_vreplgr2vr_d, ls::simd_splat, m128i, i64x2, i64); + +impl_sv!("lsx", lsx_vrepli_b, ls::simd_splat, m128i, i8x16, 10); +impl_sv!("lsx", lsx_vrepli_h, ls::simd_splat, m128i, i16x8, 10); +impl_sv!("lsx", lsx_vrepli_w, ls::simd_splat, m128i, i32x4, 10); +impl_sv!("lsx", lsx_vrepli_d, ls::simd_splat, m128i, i64x2, 10); + +impl_vvv!("lsx", lsx_vadd_b, is::simd_add, m128i, i8x16); +impl_vvv!("lsx", lsx_vadd_h, is::simd_add, m128i, i16x8); +impl_vvv!("lsx", lsx_vadd_w, is::simd_add, m128i, i32x4); +impl_vvv!("lsx", lsx_vadd_d, is::simd_add, m128i, i64x2); +impl_vvv!("lsx", lsx_vsub_b, is::simd_sub, m128i, i8x16); +impl_vvv!("lsx", lsx_vsub_h, is::simd_sub, m128i, i16x8); +impl_vvv!("lsx", lsx_vsub_w, is::simd_sub, m128i, i32x4); +impl_vvv!("lsx", lsx_vsub_d, is::simd_sub, m128i, i64x2); +impl_vvv!("lsx", lsx_vmax_b, cs::simd_imax, m128i, i8x16); +impl_vvv!("lsx", lsx_vmax_h, cs::simd_imax, m128i, i16x8); +impl_vvv!("lsx", lsx_vmax_w, cs::simd_imax, m128i, i32x4); +impl_vvv!("lsx", lsx_vmax_d, cs::simd_imax, m128i, i64x2); +impl_vvv!("lsx", lsx_vmax_bu, cs::simd_imax, m128i, u8x16); +impl_vvv!("lsx", lsx_vmax_hu, cs::simd_imax, m128i, u16x8); +impl_vvv!("lsx", lsx_vmax_wu, cs::simd_imax, m128i, u32x4); +impl_vvv!("lsx", lsx_vmax_du, cs::simd_imax, m128i, u64x2); +impl_vvv!("lsx", lsx_vmin_b, cs::simd_imin, m128i, i8x16); +impl_vvv!("lsx", lsx_vmin_h, cs::simd_imin, m128i, i16x8); +impl_vvv!("lsx", lsx_vmin_w, cs::simd_imin, m128i, i32x4); +impl_vvv!("lsx", lsx_vmin_d, cs::simd_imin, m128i, i64x2); +impl_vvv!("lsx", lsx_vmin_bu, cs::simd_imin, m128i, u8x16); +impl_vvv!("lsx", lsx_vmin_hu, cs::simd_imin, m128i, u16x8); +impl_vvv!("lsx", lsx_vmin_wu, cs::simd_imin, m128i, u32x4); +impl_vvv!("lsx", lsx_vmin_du, cs::simd_imin, m128i, u64x2); +impl_vvv!("lsx", lsx_vseq_b, is::simd_eq, m128i, i8x16); +impl_vvv!("lsx", lsx_vseq_h, is::simd_eq, m128i, i16x8); +impl_vvv!("lsx", lsx_vseq_w, is::simd_eq, m128i, i32x4); +impl_vvv!("lsx", lsx_vseq_d, is::simd_eq, m128i, i64x2); +impl_vvv!("lsx", lsx_vslt_b, is::simd_lt, m128i, i8x16); +impl_vvv!("lsx", lsx_vslt_h, is::simd_lt, m128i, i16x8); +impl_vvv!("lsx", lsx_vslt_w, is::simd_lt, m128i, i32x4); +impl_vvv!("lsx", lsx_vslt_d, is::simd_lt, m128i, i64x2); +impl_vvv!("lsx", lsx_vslt_bu, is::simd_lt, m128i, u8x16); +impl_vvv!("lsx", lsx_vslt_hu, is::simd_lt, m128i, u16x8); +impl_vvv!("lsx", lsx_vslt_wu, is::simd_lt, m128i, u32x4); +impl_vvv!("lsx", lsx_vslt_du, is::simd_lt, m128i, u64x2); +impl_vvv!("lsx", lsx_vsle_b, is::simd_le, m128i, i8x16); +impl_vvv!("lsx", lsx_vsle_h, is::simd_le, m128i, i16x8); +impl_vvv!("lsx", lsx_vsle_w, is::simd_le, m128i, i32x4); +impl_vvv!("lsx", lsx_vsle_d, is::simd_le, m128i, i64x2); +impl_vvv!("lsx", lsx_vsle_bu, is::simd_le, m128i, u8x16); +impl_vvv!("lsx", lsx_vsle_hu, is::simd_le, m128i, u16x8); +impl_vvv!("lsx", lsx_vsle_wu, is::simd_le, m128i, u32x4); +impl_vvv!("lsx", lsx_vsle_du, is::simd_le, m128i, u64x2); +impl_vvv!("lsx", lsx_vmul_b, is::simd_mul, m128i, i8x16); +impl_vvv!("lsx", lsx_vmul_h, is::simd_mul, m128i, i16x8); +impl_vvv!("lsx", lsx_vmul_w, is::simd_mul, m128i, i32x4); +impl_vvv!("lsx", lsx_vmul_d, is::simd_mul, m128i, i64x2); +impl_vvv!("lsx", lsx_vdiv_b, is::simd_div, m128i, i8x16); +impl_vvv!("lsx", lsx_vdiv_h, is::simd_div, m128i, i16x8); +impl_vvv!("lsx", lsx_vdiv_w, is::simd_div, m128i, i32x4); +impl_vvv!("lsx", lsx_vdiv_d, is::simd_div, m128i, i64x2); +impl_vvv!("lsx", lsx_vdiv_bu, is::simd_div, m128i, u8x16); +impl_vvv!("lsx", lsx_vdiv_hu, is::simd_div, m128i, u16x8); +impl_vvv!("lsx", lsx_vdiv_wu, is::simd_div, m128i, u32x4); +impl_vvv!("lsx", lsx_vdiv_du, is::simd_div, m128i, u64x2); +impl_vvv!("lsx", lsx_vmod_b, is::simd_rem, m128i, i8x16); +impl_vvv!("lsx", lsx_vmod_h, is::simd_rem, m128i, i16x8); +impl_vvv!("lsx", lsx_vmod_w, is::simd_rem, m128i, i32x4); +impl_vvv!("lsx", lsx_vmod_d, is::simd_rem, m128i, i64x2); +impl_vvv!("lsx", lsx_vmod_bu, is::simd_rem, m128i, u8x16); +impl_vvv!("lsx", lsx_vmod_hu, is::simd_rem, m128i, u16x8); +impl_vvv!("lsx", lsx_vmod_wu, is::simd_rem, m128i, u32x4); +impl_vvv!("lsx", lsx_vmod_du, is::simd_rem, m128i, u64x2); +impl_vvv!("lsx", lsx_vand_v, is::simd_and, m128i, u8x16); +impl_vvv!("lsx", lsx_vandn_v, ls::simd_andn, m128i, u8x16); +impl_vvv!("lsx", lsx_vor_v, is::simd_or, m128i, u8x16); +impl_vvv!("lsx", lsx_vorn_v, ls::simd_orn, m128i, u8x16); +impl_vvv!("lsx", lsx_vnor_v, ls::simd_nor, m128i, u8x16); +impl_vvv!("lsx", lsx_vxor_v, is::simd_xor, m128i, u8x16); +impl_vvv!("lsx", lsx_vfadd_s, is::simd_add, m128, f32x4); +impl_vvv!("lsx", lsx_vfadd_d, is::simd_add, m128d, f64x2); +impl_vvv!("lsx", lsx_vfsub_s, is::simd_sub, m128, f32x4); +impl_vvv!("lsx", lsx_vfsub_d, is::simd_sub, m128d, f64x2); +impl_vvv!("lsx", lsx_vfmul_s, is::simd_mul, m128, f32x4); +impl_vvv!("lsx", lsx_vfmul_d, is::simd_mul, m128d, f64x2); +impl_vvv!("lsx", lsx_vfdiv_s, is::simd_div, m128, f32x4); +impl_vvv!("lsx", lsx_vfdiv_d, is::simd_div, m128d, f64x2); +impl_vvv!("lsx", lsx_vsll_b, ls::simd_shl, m128i, i8x16); +impl_vvv!("lsx", lsx_vsll_h, ls::simd_shl, m128i, i16x8); +impl_vvv!("lsx", lsx_vsll_w, ls::simd_shl, m128i, i32x4); +impl_vvv!("lsx", lsx_vsll_d, ls::simd_shl, m128i, i64x2); +impl_vvv!("lsx", lsx_vsra_b, ls::simd_shr, m128i, i8x16); +impl_vvv!("lsx", lsx_vsra_h, ls::simd_shr, m128i, i16x8); +impl_vvv!("lsx", lsx_vsra_w, ls::simd_shr, m128i, i32x4); +impl_vvv!("lsx", lsx_vsra_d, ls::simd_shr, m128i, i64x2); +impl_vvv!("lsx", lsx_vsrl_b, ls::simd_shr, m128i, u8x16); +impl_vvv!("lsx", lsx_vsrl_h, ls::simd_shr, m128i, u16x8); +impl_vvv!("lsx", lsx_vsrl_w, ls::simd_shr, m128i, u32x4); +impl_vvv!("lsx", lsx_vsrl_d, ls::simd_shr, m128i, u64x2); +impl_vvv!("lsx", lsx_vbitclr_b, ls::simd_bitclr, m128i, u8x16); +impl_vvv!("lsx", lsx_vbitclr_h, ls::simd_bitclr, m128i, u16x8); +impl_vvv!("lsx", lsx_vbitclr_w, ls::simd_bitclr, m128i, u32x4); +impl_vvv!("lsx", lsx_vbitclr_d, ls::simd_bitclr, m128i, u64x2); +impl_vvv!("lsx", lsx_vbitset_b, ls::simd_bitset, m128i, u8x16); +impl_vvv!("lsx", lsx_vbitset_h, ls::simd_bitset, m128i, u16x8); +impl_vvv!("lsx", lsx_vbitset_w, ls::simd_bitset, m128i, u32x4); +impl_vvv!("lsx", lsx_vbitset_d, ls::simd_bitset, m128i, u64x2); +impl_vvv!("lsx", lsx_vbitrev_b, ls::simd_bitrev, m128i, u8x16); +impl_vvv!("lsx", lsx_vbitrev_h, ls::simd_bitrev, m128i, u16x8); +impl_vvv!("lsx", lsx_vbitrev_w, ls::simd_bitrev, m128i, u32x4); +impl_vvv!("lsx", lsx_vbitrev_d, ls::simd_bitrev, m128i, u64x2); +impl_vvv!("lsx", lsx_vsadd_b, is::simd_saturating_add, m128i, i8x16); +impl_vvv!("lsx", lsx_vsadd_h, is::simd_saturating_add, m128i, i16x8); +impl_vvv!("lsx", lsx_vsadd_w, is::simd_saturating_add, m128i, i32x4); +impl_vvv!("lsx", lsx_vsadd_d, is::simd_saturating_add, m128i, i64x2); +impl_vvv!("lsx", lsx_vsadd_bu, is::simd_saturating_add, m128i, u8x16); +impl_vvv!("lsx", lsx_vsadd_hu, is::simd_saturating_add, m128i, u16x8); +impl_vvv!("lsx", lsx_vsadd_wu, is::simd_saturating_add, m128i, u32x4); +impl_vvv!("lsx", lsx_vsadd_du, is::simd_saturating_add, m128i, u64x2); +impl_vvv!("lsx", lsx_vssub_b, is::simd_saturating_sub, m128i, i8x16); +impl_vvv!("lsx", lsx_vssub_h, is::simd_saturating_sub, m128i, i16x8); +impl_vvv!("lsx", lsx_vssub_w, is::simd_saturating_sub, m128i, i32x4); +impl_vvv!("lsx", lsx_vssub_d, is::simd_saturating_sub, m128i, i64x2); +impl_vvv!("lsx", lsx_vssub_bu, is::simd_saturating_sub, m128i, u8x16); +impl_vvv!("lsx", lsx_vssub_hu, is::simd_saturating_sub, m128i, u16x8); +impl_vvv!("lsx", lsx_vssub_wu, is::simd_saturating_sub, m128i, u32x4); +impl_vvv!("lsx", lsx_vssub_du, is::simd_saturating_sub, m128i, u64x2); +impl_vvv!("lsx", lsx_vadda_b, ls::simd_adda, m128i, i8x16); +impl_vvv!("lsx", lsx_vadda_h, ls::simd_adda, m128i, i16x8); +impl_vvv!("lsx", lsx_vadda_w, ls::simd_adda, m128i, i32x4); +impl_vvv!("lsx", lsx_vadda_d, ls::simd_adda, m128i, i64x2); +impl_vvv!("lsx", lsx_vabsd_b, ls::simd_absd, m128i, i8x16); +impl_vvv!("lsx", lsx_vabsd_h, ls::simd_absd, m128i, i16x8); +impl_vvv!("lsx", lsx_vabsd_w, ls::simd_absd, m128i, i32x4); +impl_vvv!("lsx", lsx_vabsd_d, ls::simd_absd, m128i, i64x2); +impl_vvv!("lsx", lsx_vabsd_bu, ls::simd_absd, m128i, u8x16); +impl_vvv!("lsx", lsx_vabsd_hu, ls::simd_absd, m128i, u16x8); +impl_vvv!("lsx", lsx_vabsd_wu, ls::simd_absd, m128i, u32x4); +impl_vvv!("lsx", lsx_vabsd_du, ls::simd_absd, m128i, u64x2); +impl_vvv!("lsx", lsx_vpickev_b, simd_pickev_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vpickev_h, simd_pickev_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vpickev_w, simd_pickev_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vpickev_d, simd_pickev_d, m128i, i64x2); +impl_vvv!("lsx", lsx_vpickod_b, simd_pickod_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vpickod_h, simd_pickod_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vpickod_w, simd_pickod_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vpickod_d, simd_pickod_d, m128i, i64x2); +impl_vvv!("lsx", lsx_vilvh_b, simd_ilvh_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vilvh_h, simd_ilvh_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vilvh_w, simd_ilvh_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vilvh_d, simd_ilvh_d, m128i, i64x2); +impl_vvv!("lsx", lsx_vilvl_b, simd_ilvl_b, m128i, i8x16); +impl_vvv!("lsx", lsx_vilvl_h, simd_ilvl_h, m128i, i16x8); +impl_vvv!("lsx", lsx_vilvl_w, simd_ilvl_w, m128i, i32x4); +impl_vvv!("lsx", lsx_vilvl_d, simd_ilvl_d, m128i, i64x2); + +impl_vuv!("lsx", lsx_vslli_b, is::simd_shl, m128i, i8x16); +impl_vuv!("lsx", lsx_vslli_h, is::simd_shl, m128i, i16x8); +impl_vuv!("lsx", lsx_vslli_w, is::simd_shl, m128i, i32x4); +impl_vuv!("lsx", lsx_vslli_d, is::simd_shl, m128i, i64x2); +impl_vuv!("lsx", lsx_vsrai_b, is::simd_shr, m128i, i8x16); +impl_vuv!("lsx", lsx_vsrai_h, is::simd_shr, m128i, i16x8); +impl_vuv!("lsx", lsx_vsrai_w, is::simd_shr, m128i, i32x4); +impl_vuv!("lsx", lsx_vsrai_d, is::simd_shr, m128i, i64x2); +impl_vuv!("lsx", lsx_vsrli_b, is::simd_shr, m128i, u8x16); +impl_vuv!("lsx", lsx_vsrli_h, is::simd_shr, m128i, u16x8); +impl_vuv!("lsx", lsx_vsrli_w, is::simd_shr, m128i, u32x4); +impl_vuv!("lsx", lsx_vsrli_d, is::simd_shr, m128i, u64x2); +impl_vuv!("lsx", lsx_vaddi_bu, is::simd_add, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vaddi_hu, is::simd_add, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vaddi_wu, is::simd_add, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vaddi_du, is::simd_add, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vslti_bu, is::simd_lt, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vslti_hu, is::simd_lt, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vslti_wu, is::simd_lt, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vslti_du, is::simd_lt, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vslei_bu, is::simd_le, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vslei_hu, is::simd_le, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vslei_wu, is::simd_le, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vslei_du, is::simd_le, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vmaxi_bu, cs::simd_imax, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vmaxi_hu, cs::simd_imax, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vmaxi_wu, cs::simd_imax, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vmaxi_du, cs::simd_imax, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vmini_bu, cs::simd_imin, m128i, u8x16, 5); +impl_vuv!("lsx", lsx_vmini_hu, cs::simd_imin, m128i, u16x8, 5); +impl_vuv!("lsx", lsx_vmini_wu, cs::simd_imin, m128i, u32x4, 5); +impl_vuv!("lsx", lsx_vmini_du, cs::simd_imin, m128i, u64x2, 5); +impl_vuv!("lsx", lsx_vreplvei_b, simd_replvei_b, m128i, i8x16, 4, const); +impl_vuv!("lsx", lsx_vreplvei_h, simd_replvei_h, m128i, i16x8, 3, const); +impl_vuv!("lsx", lsx_vreplvei_w, simd_replvei_w, m128i, i32x4, 2, const); +impl_vuv!("lsx", lsx_vreplvei_d, simd_replvei_d, m128i, i64x2, 1, const); + +impl_vug!("lsx", lsx_vpickve2gr_b, is::simd_extract, m128i, i8x16, i32, 4); +impl_vug!("lsx", lsx_vpickve2gr_h, is::simd_extract, m128i, i16x8, i32, 3); +impl_vug!("lsx", lsx_vpickve2gr_w, is::simd_extract, m128i, i32x4, i32, 2); +impl_vug!("lsx", lsx_vpickve2gr_d, is::simd_extract, m128i, i64x2, i64, 1); +impl_vug!("lsx", lsx_vpickve2gr_bu, is::simd_extract, m128i, u8x16, u32, 4); +impl_vug!("lsx", lsx_vpickve2gr_hu, is::simd_extract, m128i, u16x8, u32, 3); +impl_vug!("lsx", lsx_vpickve2gr_wu, is::simd_extract, m128i, u32x4, u32, 2); +impl_vug!("lsx", lsx_vpickve2gr_du, is::simd_extract, m128i, u64x2, u64, 1); + +impl_vsv!("lsx", lsx_vseqi_b, is::simd_eq, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vseqi_h, is::simd_eq, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vseqi_w, is::simd_eq, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vseqi_d, is::simd_eq, m128i, i64x2, 5); +impl_vsv!("lsx", lsx_vslti_b, is::simd_lt, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vslti_h, is::simd_lt, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vslti_w, is::simd_lt, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vslti_d, is::simd_lt, m128i, i64x2, 5); +impl_vsv!("lsx", lsx_vslei_b, is::simd_le, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vslei_h, is::simd_le, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vslei_w, is::simd_le, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vslei_d, is::simd_le, m128i, i64x2, 5); +impl_vsv!("lsx", lsx_vmaxi_b, cs::simd_imax, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vmaxi_h, cs::simd_imax, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vmaxi_w, cs::simd_imax, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vmaxi_d, cs::simd_imax, m128i, i64x2, 5); +impl_vsv!("lsx", lsx_vmini_b, cs::simd_imin, m128i, i8x16, 5); +impl_vsv!("lsx", lsx_vmini_h, cs::simd_imin, m128i, i16x8, 5); +impl_vsv!("lsx", lsx_vmini_w, cs::simd_imin, m128i, i32x4, 5); +impl_vsv!("lsx", lsx_vmini_d, cs::simd_imin, m128i, i64x2, 5); + +impl_vvvv!("lsx", lsx_vmadd_b, ls::simd_madd, m128i, i8x16); +impl_vvvv!("lsx", lsx_vmadd_h, ls::simd_madd, m128i, i16x8); +impl_vvvv!("lsx", lsx_vmadd_w, ls::simd_madd, m128i, i32x4); +impl_vvvv!("lsx", lsx_vmadd_d, ls::simd_madd, m128i, i64x2); +impl_vvvv!("lsx", lsx_vmsub_b, ls::simd_msub, m128i, i8x16); +impl_vvvv!("lsx", lsx_vmsub_h, ls::simd_msub, m128i, i16x8); +impl_vvvv!("lsx", lsx_vmsub_w, ls::simd_msub, m128i, i32x4); +impl_vvvv!("lsx", lsx_vmsub_d, ls::simd_msub, m128i, i64x2); +impl_vvvv!("lsx", lsx_vfmadd_s, is::simd_fma, m128, f32x4); +impl_vvvv!("lsx", lsx_vfmadd_d, is::simd_fma, m128d, f64x2); +impl_vvvv!("lsx", lsx_vfmsub_s, ls::simd_fmsub, m128, f32x4); +impl_vvvv!("lsx", lsx_vfmsub_d, ls::simd_fmsub, m128d, f64x2); +impl_vvvv!("lsx", lsx_vfnmadd_s, ls::simd_fnmadd, m128, f32x4); +impl_vvvv!("lsx", lsx_vfnmadd_d, ls::simd_fnmadd, m128d, f64x2); +impl_vvvv!("lsx", lsx_vfnmsub_s, ls::simd_fnmsub, m128, f32x4); +impl_vvvv!("lsx", lsx_vfnmsub_d, ls::simd_fnmsub, m128d, f64x2); + +impl_vugv!("lsx", lsx_vinsgr2vr_b, is::simd_insert, m128i, i8x16, i32, 4); +impl_vugv!("lsx", lsx_vinsgr2vr_h, is::simd_insert, m128i, i16x8, i32, 3); +impl_vugv!("lsx", lsx_vinsgr2vr_w, is::simd_insert, m128i, i32x4, i32, 2); +impl_vugv!("lsx", lsx_vinsgr2vr_d, is::simd_insert, m128i, i64x2, i64, 1); diff --git a/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs b/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs index 5670bd4378a84..748e2b597ada7 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs @@ -5,6 +5,7 @@ use crate::{ core_arch::{loongarch64::*, simd::*}, mem::transmute, }; +use std::hint::black_box; use stdarch_test::simd_test; #[simd_test(enable = "lsx")] @@ -17,7 +18,10 @@ unsafe fn test_lsx_vsll_b() { ); let r = i64x2::new(70990221811840, -3257029622096690968); - assert_eq!(r, transmute(lsx_vsll_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -26,7 +30,10 @@ unsafe fn test_lsx_vsll_h() { let b = i16x8::new(-10317, -20778, -9962, -8975, 25298, 12929, -13803, -18669); let r = i64x2::new(-5063658964307128392, -3539825456407336052); - assert_eq!(r, transmute(lsx_vsll_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -35,7 +42,10 @@ unsafe fn test_lsx_vsll_w() { let b = i32x4::new(82237029, -819106294, -96895338, -456101700); let r = i64x2::new(-7163824029380778240, 2305843009528266752); - assert_eq!(r, transmute(lsx_vsll_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -44,7 +54,10 @@ unsafe fn test_lsx_vsll_d() { let b = i64x2::new(8592669249977019309, -1379694176202045825); let r = i64x2::new(1790743801833193472, 0); - assert_eq!(r, transmute(lsx_vsll_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -54,7 +67,7 @@ unsafe fn test_lsx_vslli_b() { ); let r = i64x2::new(-2780807324588213414, -3708578564830607166); - assert_eq!(r, transmute(lsx_vslli_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -62,7 +75,7 @@ unsafe fn test_lsx_vslli_h() { let a = i16x8::new(18469, -14840, 23655, -3474, 7467, 2798, -15418, 26847); let r = i64x2::new(-7241759886206301888, 4017476402818337472); - assert_eq!(r, transmute(lsx_vslli_h::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_h::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -70,7 +83,7 @@ unsafe fn test_lsx_vslli_w() { let a = i32x4::new(20701902, -1777432355, 6349179, 1747667894); let r = i64x2::new(4189319625752393728, -5967594959501136896); - assert_eq!(r, transmute(lsx_vslli_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -78,7 +91,7 @@ unsafe fn test_lsx_vslli_d() { let a = i64x2::new(-5896889635782282086, -8807609320972692839); let r = i64x2::new(-4233027607937510592, -5142337165482896608); - assert_eq!(r, transmute(lsx_vslli_d::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_d::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -91,7 +104,10 @@ unsafe fn test_lsx_vsra_b() { ); let r = i64x2::new(-1080315035391229440, 720022881735668484); - assert_eq!(r, transmute(lsx_vsra_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -100,7 +116,10 @@ unsafe fn test_lsx_vsra_h() { let b = i16x8::new(14017, 3796, 23987, -27244, -13363, 21333, -10262, 23633); let r = i64x2::new(164116464290576704, -1935703552267190275); - assert_eq!(r, transmute(lsx_vsra_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -109,7 +128,10 @@ unsafe fn test_lsx_vsra_w() { let b = i32x4::new(-670772992, 2044335288, -1224858031, 520588790); let r = i64x2::new(-210763200496, 1619202657181); - assert_eq!(r, transmute(lsx_vsra_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -118,7 +140,10 @@ unsafe fn test_lsx_vsra_d() { let b = i64x2::new(4251079558060308329, 4657697142994416829); let r = i64x2::new(-623956, 3); - assert_eq!(r, transmute(lsx_vsra_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -128,7 +153,7 @@ unsafe fn test_lsx_vsrai_b() { ); let r = i64x2::new(-2018743940785760257, -2093355901512246518); - assert_eq!(r, transmute(lsx_vsrai_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -136,7 +161,7 @@ unsafe fn test_lsx_vsrai_h() { let a = i16x8::new(-22502, -7299, 19084, -21578, -28082, 20851, 23456, 15524); let r = i64x2::new(-1688828385492998, 844446405361657); - assert_eq!(r, transmute(lsx_vsrai_h::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_h::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -144,7 +169,7 @@ unsafe fn test_lsx_vsrai_w() { let a = i32x4::new(743537539, 1831641900, -1639033567, -984629971); let r = i64x2::new(30008936499988, -16131897170029); - assert_eq!(r, transmute(lsx_vsrai_w::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_w::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -152,7 +177,7 @@ unsafe fn test_lsx_vsrai_d() { let a = i64x2::new(-8375997486414293750, 1714581574012370587); let r = i64x2::new(-476121, 97462); - assert_eq!(r, transmute(lsx_vsrai_d::<44>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_d::<44>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -165,7 +190,13 @@ unsafe fn test_lsx_vsrar_b() { ); let r = i64x2::new(139917463134404866, 143840305941130491); - assert_eq!(r, transmute(lsx_vsrar_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -174,7 +205,13 @@ unsafe fn test_lsx_vsrar_h() { let b = i16x8::new(-26450, 2176, 31587, 2222, 13726, 30172, 1067, -14273); let r = i64x2::new(-287115463426050, 42950131714); - assert_eq!(r, transmute(lsx_vsrar_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -183,7 +220,13 @@ unsafe fn test_lsx_vsrar_w() { let b = i32x4::new(-1532076758, 940127488, 1781366421, 1497262222); let r = i64x2::new(7179867468326627830, 560544771735247); - assert_eq!(r, transmute(lsx_vsrar_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -192,7 +235,13 @@ unsafe fn test_lsx_vsrar_d() { let b = i64x2::new(3571440266112779495, -725943254065719378); let r = i64x2::new(-890187, -17811); - assert_eq!(r, transmute(lsx_vsrar_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -202,7 +251,7 @@ unsafe fn test_lsx_vsrari_b() { ); let r = i64x2::new(867219992078845182, -503291487652282122); - assert_eq!(r, transmute(lsx_vsrari_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -210,7 +259,7 @@ unsafe fn test_lsx_vsrari_h() { let a = i16x8::new(29939, -1699, 12357, 30805, -30883, 31936, 15701, -11818); let r = i64x2::new(4222154715365391, -1688815499411471); - assert_eq!(r, transmute(lsx_vsrari_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -218,7 +267,7 @@ unsafe fn test_lsx_vsrari_w() { let a = i32x4::new(588196178, -1058764534, 1325397591, 1169671026); let r = i64x2::new(-4294967295, 4294967297); - assert_eq!(r, transmute(lsx_vsrari_w::<30>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_w::<30>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -226,7 +275,7 @@ unsafe fn test_lsx_vsrari_d() { let a = i64x2::new(-2795326946470057100, 6746045132217841338); let r = i64x2::new(-174707934154378569, 421627820763615084); - assert_eq!(r, transmute(lsx_vsrari_d::<4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_d::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -239,7 +288,10 @@ unsafe fn test_lsx_vsrl_b() { ); let r = i64x2::new(1300161376517358116, 72917012339034650); - assert_eq!(r, transmute(lsx_vsrl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -248,7 +300,10 @@ unsafe fn test_lsx_vsrl_h() { let b = i16x8::new(16605, -13577, -26644, -17739, 11000, -29283, -15971, 20169); let r = i64x2::new(468374382728249347, 20829178341621860); - assert_eq!(r, transmute(lsx_vsrl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -257,7 +312,10 @@ unsafe fn test_lsx_vsrl_w() { let b = i32x4::new(1777885221, -1725401090, 1849724045, -1051851102); let r = i64x2::new(12953227061, 1599606693325790121); - assert_eq!(r, transmute(lsx_vsrl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -266,7 +324,10 @@ unsafe fn test_lsx_vsrl_d() { let b = i64x2::new(-7903128394835365398, 7601347629202818185); let r = i64x2::new(649044, 1572171616025062); - assert_eq!(r, transmute(lsx_vsrl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -276,7 +337,7 @@ unsafe fn test_lsx_vsrli_b() { ); let r = i64x2::new(1952909805632365845, 3971107439766933248); - assert_eq!(r, transmute(lsx_vsrli_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -284,7 +345,7 @@ unsafe fn test_lsx_vsrli_h() { let a = i16x8::new(29545, 354, 27695, 20915, -32766, -24491, 10641, 20310); let r = i64x2::new(11259230996660281, 10977609996304448); - assert_eq!(r, transmute(lsx_vsrli_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -292,7 +353,7 @@ unsafe fn test_lsx_vsrli_w() { let a = i32x4::new(627703601, 922874410, -234412645, -1216101872); let r = i64x2::new(3870813506329215, 12913695352717769); - assert_eq!(r, transmute(lsx_vsrli_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -300,7 +361,7 @@ unsafe fn test_lsx_vsrli_d() { let a = i64x2::new(1407685950714554203, -6076144426076800688); let r = i64x2::new(9, 85); - assert_eq!(r, transmute(lsx_vsrli_d::<57>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_d::<57>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -313,7 +374,13 @@ unsafe fn test_lsx_vsrlr_b() { ); let r = i64x2::new(3317746744565237249, 144420860932066826); - assert_eq!(r, transmute(lsx_vsrlr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -322,7 +389,13 @@ unsafe fn test_lsx_vsrlr_h() { let b = i16x8::new(19500, -26403, -1282, 12290, -18989, 25105, -24347, 6707); let r = i64x2::new(1991716935204929539, 311033695131730530); - assert_eq!(r, transmute(lsx_vsrlr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -331,7 +404,13 @@ unsafe fn test_lsx_vsrlr_w() { let b = i32x4::new(1830015593, -1452673200, 962662328, -252736055); let r = i64x2::new(7864089021084, 20473000998469780); - assert_eq!(r, transmute(lsx_vsrlr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -340,7 +419,13 @@ unsafe fn test_lsx_vsrlr_d() { let b = i64x2::new(-1543621369665313706, 8544381131364512650); let r = i64x2::new(1428972826343, 4256393046182047); - assert_eq!(r, transmute(lsx_vsrlr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -350,7 +435,7 @@ unsafe fn test_lsx_vsrlri_b() { ); let r = i64x2::new(93866580842851436, 1896906350202744602); - assert_eq!(r, transmute(lsx_vsrlri_b::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_b::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -358,7 +443,7 @@ unsafe fn test_lsx_vsrlri_h() { let a = i16x8::new(-18045, 1968, 22966, 3692, 2010, -17108, 3373, -30706); let r = i64x2::new(1039304252363684227, -8642956144778934310); - assert_eq!(r, transmute(lsx_vsrlri_h::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_h::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -366,7 +451,7 @@ unsafe fn test_lsx_vsrlri_w() { let a = i32x4::new(1306456564, -1401620667, -839707416, -1634862919); let r = i64x2::new(1553353645217275455, 1428132662790218397); - assert_eq!(r, transmute(lsx_vsrlri_w::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_w::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -374,7 +459,7 @@ unsafe fn test_lsx_vsrlri_d() { let a = i64x2::new(-3683179565838693027, 6160461828074490983); let r = i64x2::new(205, 85); - assert_eq!(r, transmute(lsx_vsrlri_d::<56>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_d::<56>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -387,7 +472,13 @@ unsafe fn test_lsx_vbitclr_b() { ); let r = i64x2::new(-7325372782311046420, -5316383129963115396); - assert_eq!(r, transmute(lsx_vbitclr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -396,7 +487,13 @@ unsafe fn test_lsx_vbitclr_h() { let b = u16x8::new(26587, 57597, 34751, 38678, 23919, 45729, 62569, 5978); let r = i64x2::new(-5495443997997256700, -3317648531059028099); - assert_eq!(r, transmute(lsx_vbitclr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -405,7 +502,13 @@ unsafe fn test_lsx_vbitclr_w() { let b = u32x4::new(1968231094, 2827365864, 4097273355, 4016923215); let r = i64x2::new(-7626667807832507452, 546969093373761021); - assert_eq!(r, transmute(lsx_vbitclr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -414,7 +517,13 @@ unsafe fn test_lsx_vbitclr_d() { let b = u64x2::new(5723204188033770667, 2981956604140378920); let r = i64x2::new(-1242851545812588193, -5509634528458855560); - assert_eq!(r, transmute(lsx_vbitclr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -424,7 +533,7 @@ unsafe fn test_lsx_vbitclri_b() { ); let r = i64x2::new(7503621968728299154, -6865556469255070542); - assert_eq!(r, transmute(lsx_vbitclri_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -432,7 +541,7 @@ unsafe fn test_lsx_vbitclri_h() { let a = u16x8::new(17366, 58985, 22108, 45942, 27326, 19605, 9632, 32322); let r = i64x2::new(-5515130134779575338, 8809640793386347198); - assert_eq!(r, transmute(lsx_vbitclri_h::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_h::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -440,7 +549,7 @@ unsafe fn test_lsx_vbitclri_w() { let a = u32x4::new(718858183, 3771164920, 1842485081, 896350597); let r = i64x2::new(-2249714073768237625, 3849796501707560281); - assert_eq!(r, transmute(lsx_vbitclri_w::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_w::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -448,7 +557,7 @@ unsafe fn test_lsx_vbitclri_d() { let a = u64x2::new(10838658690401820648, 3833745076866321369); let r = i64x2::new(-7608085933063544856, 3833744527110507481); - assert_eq!(r, transmute(lsx_vbitclri_d::<39>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_d::<39>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -461,7 +570,13 @@ unsafe fn test_lsx_vbitset_b() { ); let r = i64x2::new(-7941579666116909337, -8620998056061183460); - assert_eq!(r, transmute(lsx_vbitset_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -470,7 +585,13 @@ unsafe fn test_lsx_vbitset_h() { let b = u16x8::new(64512, 23847, 57770, 47705, 8024, 31966, 14493, 50266); let r = i64x2::new(8218739538452480967, 9190693790629616954); - assert_eq!(r, transmute(lsx_vbitset_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -479,7 +600,13 @@ unsafe fn test_lsx_vbitset_w() { let b = u32x4::new(3259082048, 1303228302, 1429001720, 209615081); let r = i64x2::new(5472281065241838073, -4235320193476931022); - assert_eq!(r, transmute(lsx_vbitset_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -488,7 +615,13 @@ unsafe fn test_lsx_vbitset_d() { let b = u64x2::new(12687331714071910183, 1753585392879336372); let r = i64x2::new(8117422612773760492, 5031452210401715131); - assert_eq!(r, transmute(lsx_vbitset_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -498,7 +631,7 @@ unsafe fn test_lsx_vbitseti_b() { ); let r = i64x2::new(6185254145054243811, 5860546440891134157); - assert_eq!(r, transmute(lsx_vbitseti_b::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_b::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -506,7 +639,7 @@ unsafe fn test_lsx_vbitseti_h() { let a = u16x8::new(15222, 59961, 52253, 2908, 61562, 41309, 63627, 4191); let r = i64x2::new(819316619673811830, 1179934905985921146); - assert_eq!(r, transmute(lsx_vbitseti_h::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_h::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -514,7 +647,7 @@ unsafe fn test_lsx_vbitseti_w() { let a = u32x4::new(3788412756, 1863556832, 1913138259, 1199998627); let r = i64x2::new(8012922850722617172, 5162962059379878995); - assert_eq!(r, transmute(lsx_vbitseti_w::<21>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_w::<21>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -522,7 +655,7 @@ unsafe fn test_lsx_vbitseti_d() { let a = u64x2::new(10744510173660993785, 16946223211744108759); let r = i64x2::new(-7702233900048557831, -1500520861831225129); - assert_eq!(r, transmute(lsx_vbitseti_d::<27>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_d::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -535,7 +668,13 @@ unsafe fn test_lsx_vbitrev_b() { ); let r = i64x2::new(7553563628828981794, -3550669970358088907); - assert_eq!(r, transmute(lsx_vbitrev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -544,7 +683,13 @@ unsafe fn test_lsx_vbitrev_h() { let b = u16x8::new(21347, 23131, 57157, 13786, 34463, 33445, 23964, 48087); let r = i64x2::new(-2253077037977362312, -1686202867067838120); - assert_eq!(r, transmute(lsx_vbitrev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -553,7 +698,13 @@ unsafe fn test_lsx_vbitrev_w() { let b = u32x4::new(3330530584, 4153020036, 822570638, 2652744506); let r = i64x2::new(4583672484591007782, 3195058299616182309); - assert_eq!(r, transmute(lsx_vbitrev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -562,7 +713,13 @@ unsafe fn test_lsx_vbitrev_d() { let b = u64x2::new(10942298949673565895, 12884740754463765660); let r = i64x2::new(-2430080033105247697, -384636561250515393); - assert_eq!(r, transmute(lsx_vbitrev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -572,7 +729,7 @@ unsafe fn test_lsx_vbitrevi_b() { ); let r = i64x2::new(8727320563398842300, 7658903196653594166); - assert_eq!(r, transmute(lsx_vbitrevi_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -580,7 +737,7 @@ unsafe fn test_lsx_vbitrevi_h() { let a = u16x8::new(15083, 24599, 61212, 12408, 48399, 59833, 45416, 58826); let r = i64x2::new(8104420064785562347, -6500117680329458417); - assert_eq!(r, transmute(lsx_vbitrevi_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -588,7 +745,7 @@ unsafe fn test_lsx_vbitrevi_w() { let a = u32x4::new(1200613355, 1418062686, 3847355950, 3312937419); let r = i64x2::new(6099540060505368555, -4226793400815190482); - assert_eq!(r, transmute(lsx_vbitrevi_w::<21>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_w::<21>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -596,7 +753,7 @@ unsafe fn test_lsx_vbitrevi_d() { let a = u64x2::new(295858379748270823, 1326723086853575042); let r = i64x2::new(295858379748254439, 1326723086853591426); - assert_eq!(r, transmute(lsx_vbitrevi_d::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_d::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -609,7 +766,10 @@ unsafe fn test_lsx_vadd_b() { ); let r = i64x2::new(5228548393274527852, 1107461330348121713); - assert_eq!(r, transmute(lsx_vadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -618,7 +778,10 @@ unsafe fn test_lsx_vadd_h() { let b = i16x8::new(-25040, 15453, -28080, -31322, -24429, -12453, -18073, 27019); let r = i64x2::new(1938006946753467667, 3264410328302682781); - assert_eq!(r, transmute(lsx_vadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -627,7 +790,10 @@ unsafe fn test_lsx_vadd_w() { let b = i32x4::new(-1169804484, 389773725, -731843701, -1825112934); let r = i64x2::new(-2841313158179161935, -1386205072290870384); - assert_eq!(r, transmute(lsx_vadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -636,7 +802,10 @@ unsafe fn test_lsx_vadd_d() { let b = i64x2::new(7093939531558864473, 4047047970310912233); let r = i64x2::new(-204689461315224217, -5456447511965942904); - assert_eq!(r, transmute(lsx_vadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -646,7 +815,7 @@ unsafe fn test_lsx_vaddi_bu() { ); let r = i64x2::new(-7790681010872578420, 298548864442153210); - assert_eq!(r, transmute(lsx_vaddi_bu::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_bu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -654,7 +823,7 @@ unsafe fn test_lsx_vaddi_hu() { let a = i16x8::new(-16986, -28417, 11657, 16608, -30167, 18602, 8897, -854); let r = i64x2::new(4681541984598867390, -233585914045887935); - assert_eq!(r, transmute(lsx_vaddi_hu::<24>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_hu::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -662,7 +831,7 @@ unsafe fn test_lsx_vaddi_wu() { let a = i32x4::new(1142343549, 56714754, -180143297, 408668191); let r = i64x2::new(243588023362963327, 1755216527965240129); - assert_eq!(r, transmute(lsx_vaddi_wu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_wu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -670,7 +839,7 @@ unsafe fn test_lsx_vaddi_du() { let a = i64x2::new(4516502893749962130, 9158051921593642947); let r = i64x2::new(4516502893749962139, 9158051921593642956); - assert_eq!(r, transmute(lsx_vaddi_du::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_du::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -683,7 +852,10 @@ unsafe fn test_lsx_vsub_b() { ); let r = i64x2::new(-4051929421319416371, 8737463450488952169); - assert_eq!(r, transmute(lsx_vsub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -692,7 +864,10 @@ unsafe fn test_lsx_vsub_h() { let b = i16x8::new(15368, 16207, 9677, 21447, -29583, -22036, 1845, 15671); let r = i64x2::new(-913983189443969573, 2742472381424198215); - assert_eq!(r, transmute(lsx_vsub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -701,7 +876,10 @@ unsafe fn test_lsx_vsub_w() { let b = i32x4::new(617176389, -1376778690, 1463940361, 620446698); let r = i64x2::new(-7247543435452521192, -8067077040042720878); - assert_eq!(r, transmute(lsx_vsub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -710,7 +888,10 @@ unsafe fn test_lsx_vsub_d() { let b = i64x2::new(1314101702815749241, 7673634401554993450); let r = i64x2::new(5925090640479842026, 5645651807574135757); - assert_eq!(r, transmute(lsx_vsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -720,7 +901,7 @@ unsafe fn test_lsx_vsubi_bu() { ); let r = i64x2::new(-8192169673836457574, 4758493248402185941); - assert_eq!(r, transmute(lsx_vsubi_bu::<19>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_bu::<19>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -728,7 +909,7 @@ unsafe fn test_lsx_vsubi_hu() { let a = i16x8::new(13272, -26858, -235, 16054, 29698, 1377, 4604, -3878); let r = i64x2::new(4514576075959186376, -1096043853912116238); - assert_eq!(r, transmute(lsx_vsubi_hu::<16>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_hu::<16>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -736,7 +917,7 @@ unsafe fn test_lsx_vsubi_wu() { let a = i32x4::new(1277091145, -2076591216, -1523555105, -945754023); let r = i64x2::new(-8918891362898748088, -4061982600368986914); - assert_eq!(r, transmute(lsx_vsubi_wu::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_wu::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -744,7 +925,7 @@ unsafe fn test_lsx_vsubi_du() { let a = i64x2::new(-8248876128472283209, -2119651236628000925); let r = i64x2::new(-8248876128472283234, -2119651236628000950); - assert_eq!(r, transmute(lsx_vsubi_du::<25>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_du::<25>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -757,7 +938,10 @@ unsafe fn test_lsx_vmax_b() { ); let r = i64x2::new(1260734548147228113, 7591133008682590587); - assert_eq!(r, transmute(lsx_vmax_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -766,7 +950,10 @@ unsafe fn test_lsx_vmax_h() { let b = i16x8::new(25637, -11569, -23103, 6983, -17125, 5183, -709, 5986); let r = i64x2::new(1965654441534120997, 1684966995419662474); - assert_eq!(r, transmute(lsx_vmax_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -775,7 +962,10 @@ unsafe fn test_lsx_vmax_w() { let b = i32x4::new(643859790, -389733899, -1309288060, 1934346522); let r = i64x2::new(-1673894349703707314, 8307955054730158361); - assert_eq!(r, transmute(lsx_vmax_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -784,7 +974,10 @@ unsafe fn test_lsx_vmax_d() { let b = i64x2::new(-6137495199657896371, 2160025776787809810); let r = i64x2::new(-990960773872867733, 6406870358170165030); - assert_eq!(r, transmute(lsx_vmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -794,7 +987,7 @@ unsafe fn test_lsx_vmaxi_b() { ); let r = i64x2::new(5908253215318699518, 1728939149412407162); - assert_eq!(r, transmute(lsx_vmaxi_b::<-2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_b::<-2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -802,7 +995,7 @@ unsafe fn test_lsx_vmaxi_h() { let a = i16x8::new(-14059, 19536, 15816, 28251, 23079, -10486, -11781, 25565); let r = i64x2::new(7952017497535807498, 7195907822558272039); - assert_eq!(r, transmute(lsx_vmaxi_h::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_h::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -810,7 +1003,7 @@ unsafe fn test_lsx_vmaxi_w() { let a = i32x4::new(-1136628686, -168033999, -2082324641, -1789957469); let r = i64x2::new(55834574861, 55834574861); - assert_eq!(r, transmute(lsx_vmaxi_w::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_w::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -818,7 +1011,7 @@ unsafe fn test_lsx_vmaxi_d() { let a = i64x2::new(-490958606840895025, -602287987736508723); let r = i64x2::new(-5, -5); - assert_eq!(r, transmute(lsx_vmaxi_d::<-5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_d::<-5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -831,7 +1024,13 @@ unsafe fn test_lsx_vmax_bu() { ); let r = i64x2::new(-5712542810735052010, 4588590651995571688); - assert_eq!(r, transmute(lsx_vmax_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -840,7 +1039,13 @@ unsafe fn test_lsx_vmax_hu() { let b = u16x8::new(61508, 27224, 11696, 15294, 30725, 4809, 55995, 24012); let r = i64x2::new(6366821095949791300, 6759017637785204741); - assert_eq!(r, transmute(lsx_vmax_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -849,7 +1054,13 @@ unsafe fn test_lsx_vmax_wu() { let b = u32x4::new(2856502284, 546582019, 3814541188, 2370198139); let r = i64x2::new(2347551899043152908, -8266820577849948284); - assert_eq!(r, transmute(lsx_vmax_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -858,7 +1069,13 @@ unsafe fn test_lsx_vmax_du() { let b = u64x2::new(15559502733477870114, 3537017767853389449); let r = i64x2::new(-1341110034690820781, -6520089917898609068); - assert_eq!(r, transmute(lsx_vmax_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -868,7 +1085,7 @@ unsafe fn test_lsx_vmaxi_bu() { ); let r = i64x2::new(-1045930669804428840, -8076220938123067729); - assert_eq!(r, transmute(lsx_vmaxi_bu::<27>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_bu::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -876,7 +1093,7 @@ unsafe fn test_lsx_vmaxi_hu() { let a = u16x8::new(56394, 18974, 59, 64239, 15178, 38205, 20044, 21066); let r = i64x2::new(-365072790147113910, 5929637950214978378); - assert_eq!(r, transmute(lsx_vmaxi_hu::<23>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_hu::<23>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -884,7 +1101,7 @@ unsafe fn test_lsx_vmaxi_wu() { let a = u32x4::new(2234002286, 3837532269, 3218694441, 2956128392); let r = i64x2::new(-1964668478775874706, -5750269304073789143); - assert_eq!(r, transmute(lsx_vmaxi_wu::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_wu::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -892,7 +1109,7 @@ unsafe fn test_lsx_vmaxi_du() { let a = u64x2::new(3145066433415682744, 697260191203805367); let r = i64x2::new(3145066433415682744, 697260191203805367); - assert_eq!(r, transmute(lsx_vmaxi_du::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_du::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -905,7 +1122,10 @@ unsafe fn test_lsx_vmin_b() { ); let r = i64x2::new(1870285769536668398, -8941449826914199819); - assert_eq!(r, transmute(lsx_vmin_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -914,7 +1134,10 @@ unsafe fn test_lsx_vmin_h() { let b = i16x8::new(-5519, 15267, -28304, -5842, 32145, 6582, -9646, -24918); let r = i64x2::new(-1644216902720689551, -7013553423522578637); - assert_eq!(r, transmute(lsx_vmin_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -923,7 +1146,10 @@ unsafe fn test_lsx_vmin_w() { let b = i32x4::new(-425011290, -2104111279, 175390640, 571448257); let r = i64x2::new(-9037089126579775578, 2454351575346593712); - assert_eq!(r, transmute(lsx_vmin_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -932,7 +1158,10 @@ unsafe fn test_lsx_vmin_d() { let b = i64x2::new(7269804448576860985, -2384075780126369706); let r = i64x2::new(5262417572890363865, -2384075780126369706); - assert_eq!(r, transmute(lsx_vmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -942,7 +1171,7 @@ unsafe fn test_lsx_vmini_b() { ); let r = i64x2::new(-1187557278141451540, -940475489144045070); - assert_eq!(r, transmute(lsx_vmini_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -950,7 +1179,7 @@ unsafe fn test_lsx_vmini_h() { let a = i16x8::new(26119, -26421, -26720, 11534, 11181, -13024, -9525, -1565); let r = i64x2::new(-677708916064259, -440267769697468419); - assert_eq!(r, transmute(lsx_vmini_h::<-3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_h::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -958,7 +1187,7 @@ unsafe fn test_lsx_vmini_w() { let a = i32x4::new(1937226480, -56354461, -210581139, 118641668); let r = i64x2::new(-242040566978707451, 25559222637); - assert_eq!(r, transmute(lsx_vmini_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -966,7 +1195,7 @@ unsafe fn test_lsx_vmini_d() { let a = i64x2::new(-6839357499730806877, 2982085289136510651); let r = i64x2::new(-6839357499730806877, 11); - assert_eq!(r, transmute(lsx_vmini_d::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_d::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -979,7 +1208,13 @@ unsafe fn test_lsx_vmin_bu() { ); let r = i64x2::new(3617816997909406996, 4784078933357220137); - assert_eq!(r, transmute(lsx_vmin_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -988,7 +1223,13 @@ unsafe fn test_lsx_vmin_hu() { let b = u16x8::new(30424, 14541, 7654, 46014, 42452, 14971, 14903, 13871); let r = i64x2::new(-5494921620712753448, 3904403410832303572); - assert_eq!(r, transmute(lsx_vmin_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -997,7 +1238,13 @@ unsafe fn test_lsx_vmin_wu() { let b = u32x4::new(1456829356, 2264966310, 1587887390, 645429404); let r = i64x2::new(-8718787844260924500, 2772098183187911585); - assert_eq!(r, transmute(lsx_vmin_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1006,7 +1253,13 @@ unsafe fn test_lsx_vmin_du() { let b = u64x2::new(15079551366517035256, 13891052596545854864); let r = i64x2::new(6641707046382446478, 5750385968612732680); - assert_eq!(r, transmute(lsx_vmin_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1016,7 +1269,7 @@ unsafe fn test_lsx_vmini_bu() { ); let r = i64x2::new(361700864190383365, 361700864190317829); - assert_eq!(r, transmute(lsx_vmini_bu::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_bu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1024,7 +1277,7 @@ unsafe fn test_lsx_vmini_hu() { let a = u16x8::new(51791, 41830, 16737, 31634, 36341, 58491, 48701, 8690); let r = i64x2::new(5066626891382802, 5066626891382802); - assert_eq!(r, transmute(lsx_vmini_hu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_hu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1032,7 +1285,7 @@ unsafe fn test_lsx_vmini_wu() { let a = u32x4::new(1158888991, 2639721369, 556001789, 2902942998); let r = i64x2::new(77309411346, 77309411346); - assert_eq!(r, transmute(lsx_vmini_wu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_wu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1040,7 +1293,7 @@ unsafe fn test_lsx_vmini_du() { let a = u64x2::new(17903595768445663391, 13119300660970895532); let r = i64x2::new(13, 13); - assert_eq!(r, transmute(lsx_vmini_du::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_du::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1053,7 +1306,10 @@ unsafe fn test_lsx_vseq_b() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1062,7 +1318,10 @@ unsafe fn test_lsx_vseq_h() { let b = i16x8::new(-7387, -24074, 15709, -4629, 30465, -9504, -21403, -30287); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1071,7 +1330,10 @@ unsafe fn test_lsx_vseq_w() { let b = i32x4::new(-493722413, -522973881, -1254416384, -884207273); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1080,7 +1342,10 @@ unsafe fn test_lsx_vseq_d() { let b = i64x2::new(3023654898382436999, 1783520577741396523); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1090,7 +1355,7 @@ unsafe fn test_lsx_vseqi_b() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_b::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_b::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1098,7 +1363,7 @@ unsafe fn test_lsx_vseqi_h() { let a = i16x8::new(-3205, 25452, 20774, 22065, -8424, 16590, -15971, -14154); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_h::<-1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_h::<-1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1106,7 +1371,7 @@ unsafe fn test_lsx_vseqi_w() { let a = i32x4::new(199798215, -798304779, -1812193878, -1830438161); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_w::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_w::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1114,7 +1379,7 @@ unsafe fn test_lsx_vseqi_d() { let a = i64x2::new(-7376858177879278972, 1947027764115386661); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_d::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_d::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1124,7 +1389,7 @@ unsafe fn test_lsx_vslti_b() { ); let r = i64x2::new(-1099511627776, 1095216660480); - assert_eq!(r, transmute(lsx_vslti_b::<-4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_b::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1137,7 +1402,10 @@ unsafe fn test_lsx_vslt_b() { ); let r = i64x2::new(-72056494526365441, -280375465148416); - assert_eq!(r, transmute(lsx_vslt_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1146,7 +1414,10 @@ unsafe fn test_lsx_vslt_h() { let b = i16x8::new(-10624, 12762, 31216, 13253, 2299, -12591, -8652, -22348); let r = i64x2::new(-4294967296, 65535); - assert_eq!(r, transmute(lsx_vslt_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1155,7 +1426,10 @@ unsafe fn test_lsx_vslt_w() { let b = i32x4::new(-1849021639, -756143028, 54274044, 646446450); let r = i64x2::new(-4294967296, -1); - assert_eq!(r, transmute(lsx_vslt_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1164,7 +1438,10 @@ unsafe fn test_lsx_vslt_d() { let b = i64x2::new(1481173131774551907, 270656941607020532); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vslt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1172,7 +1449,7 @@ unsafe fn test_lsx_vslti_h() { let a = i16x8::new(-8902, 5527, 17224, -27356, 4424, 28839, 29975, 18805); let r = i64x2::new(-281474976645121, 0); - assert_eq!(r, transmute(lsx_vslti_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1180,7 +1457,7 @@ unsafe fn test_lsx_vslti_w() { let a = i32x4::new(995282502, -1964668207, -996118772, 1812234755); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vslti_w::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_w::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1188,7 +1465,7 @@ unsafe fn test_lsx_vslti_d() { let a = i64x2::new(1441753618400573134, 3878439049744730841); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_d::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_d::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1201,7 +1478,13 @@ unsafe fn test_lsx_vslt_bu() { ); let r = i64x2::new(-281474959998721, -72057589742960896); - assert_eq!(r, transmute(lsx_vslt_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1210,7 +1493,13 @@ unsafe fn test_lsx_vslt_hu() { let b = u16x8::new(513, 13075, 20319, 44422, 12609, 18638, 20227, 21354); let r = i64x2::new(281474976645120, -281474976645121); - assert_eq!(r, transmute(lsx_vslt_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1219,7 +1508,13 @@ unsafe fn test_lsx_vslt_wu() { let b = u32x4::new(1402243125, 1129899238, 2591537060, 4152171743); let r = i64x2::new(4294967295, -1); - assert_eq!(r, transmute(lsx_vslt_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1228,7 +1523,13 @@ unsafe fn test_lsx_vslt_du() { let b = u64x2::new(835355141719377733, 10472626544222695938); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslt_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1238,7 +1539,7 @@ unsafe fn test_lsx_vslti_bu() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_bu::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_bu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1246,7 +1547,7 @@ unsafe fn test_lsx_vslti_hu() { let a = u16x8::new(60550, 12178, 30950, 44771, 25514, 35987, 55940, 21614); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_hu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_hu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1254,7 +1555,7 @@ unsafe fn test_lsx_vslti_wu() { let a = u32x4::new(912580668, 18660032, 3405726641, 4033549497); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_wu::<8>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_wu::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1262,7 +1563,7 @@ unsafe fn test_lsx_vslti_du() { let a = u64x2::new(17196150830761730262, 5893061291971214149); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_du::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_du::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1275,7 +1576,10 @@ unsafe fn test_lsx_vsle_b() { ); let r = i64x2::new(281470681808895, 280375465148415); - assert_eq!(r, transmute(lsx_vsle_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1284,7 +1588,10 @@ unsafe fn test_lsx_vsle_h() { let b = i16x8::new(-30602, -9535, 10944, 3343, -1093, 6600, -19453, -4561); let r = i64x2::new(281470681743360, -281470681808896); - assert_eq!(r, transmute(lsx_vsle_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1293,7 +1600,10 @@ unsafe fn test_lsx_vsle_w() { let b = i32x4::new(-1810853975, 2021418524, 215198844, 1124361386); let r = i64x2::new(-4294967296, -4294967296); - assert_eq!(r, transmute(lsx_vsle_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1302,7 +1612,10 @@ unsafe fn test_lsx_vsle_d() { let b = i64x2::new(71694374951002423, -4307912969104303925); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vsle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1312,7 +1625,7 @@ unsafe fn test_lsx_vslei_b() { ); let r = i64x2::new(72056494526365440, 280375465082880); - assert_eq!(r, transmute(lsx_vslei_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1320,7 +1633,7 @@ unsafe fn test_lsx_vslei_h() { let a = i16x8::new(31276, -16628, -30006, -20587, 2104, -30062, 18261, -6449); let r = i64x2::new(-65536, -281470681808896); - assert_eq!(r, transmute(lsx_vslei_h::<-3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_h::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1328,7 +1641,7 @@ unsafe fn test_lsx_vslei_w() { let a = i32x4::new(-1890390435, 1289536678, 1490122113, 2120063492); let r = i64x2::new(4294967295, 0); - assert_eq!(r, transmute(lsx_vslei_w::<-16>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_w::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1336,7 +1649,7 @@ unsafe fn test_lsx_vslei_d() { let a = i64x2::new(-123539898448811963, 8007480165241051883); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vslei_d::<8>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_d::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1349,7 +1662,13 @@ unsafe fn test_lsx_vsle_bu() { ); let r = i64x2::new(1095216660480, 72057594021150720); - assert_eq!(r, transmute(lsx_vsle_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1358,7 +1677,13 @@ unsafe fn test_lsx_vsle_hu() { let b = u16x8::new(50529, 35111, 24746, 62465, 21587, 30574, 11054, 11653); let r = i64x2::new(-4294967296, 281474976710655); - assert_eq!(r, transmute(lsx_vsle_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1367,7 +1692,13 @@ unsafe fn test_lsx_vsle_wu() { let b = u32x4::new(1321018603, 1091195011, 3525236625, 4061062671); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vsle_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1376,7 +1707,13 @@ unsafe fn test_lsx_vsle_du() { let b = u64x2::new(16044633718831874991, 3531311371811276914); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vsle_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1386,7 +1723,7 @@ unsafe fn test_lsx_vslei_bu() { ); let r = i64x2::new(71776119061217280, 280375465082880); - assert_eq!(r, transmute(lsx_vslei_bu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_bu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1394,7 +1731,7 @@ unsafe fn test_lsx_vslei_hu() { let a = u16x8::new(1430, 10053, 35528, 28458, 2394, 22098, 40236, 20853); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_hu::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_hu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1402,7 +1739,7 @@ unsafe fn test_lsx_vslei_wu() { let a = u32x4::new(3289026584, 3653636092, 2919866047, 2895662832); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_wu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_wu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1410,7 +1747,7 @@ unsafe fn test_lsx_vslei_du() { let a = u64x2::new(17462377852989253439, 17741928456729041079); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_du::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_du::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1420,7 +1757,7 @@ unsafe fn test_lsx_vsat_b() { ); let r = i64x2::new(-2964542792447819074, 3186937137643144200); - assert_eq!(r, transmute(lsx_vsat_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1428,7 +1765,7 @@ unsafe fn test_lsx_vsat_h() { let a = i16x8::new(-22234, -8008, -23350, 13768, 26313, -27447, -3569, 6025); let r = i64x2::new(576451960371214336, 576451960371152895); - assert_eq!(r, transmute(lsx_vsat_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1436,7 +1773,7 @@ unsafe fn test_lsx_vsat_w() { let a = i32x4::new(-84179653, 874415975, 1823119516, 1667850968); let r = i64x2::new(137438953440, 133143986207); - assert_eq!(r, transmute(lsx_vsat_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1444,7 +1781,7 @@ unsafe fn test_lsx_vsat_d() { let a = i64x2::new(6859869867233872152, 2514172105675226457); let r = i64x2::new(262143, 262143); - assert_eq!(r, transmute(lsx_vsat_d::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_d::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1454,7 +1791,7 @@ unsafe fn test_lsx_vsat_bu() { ); let r = i64x2::new(2125538672170008439, 6577605268441825038); - assert_eq!(r, transmute(lsx_vsat_bu::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_bu::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1462,7 +1799,7 @@ unsafe fn test_lsx_vsat_hu() { let a = u16x8::new(36681, 34219, 6160, 8687, 4544, 20195, 35034, 916); let r = i64x2::new(287953294993589247, 257835472485549055); - assert_eq!(r, transmute(lsx_vsat_hu::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_hu::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1470,7 +1807,7 @@ unsafe fn test_lsx_vsat_wu() { let a = u32x4::new(1758000759, 4138051566, 2705324001, 3927640324); let r = i64x2::new(70364449226751, 70364449226751); - assert_eq!(r, transmute(lsx_vsat_wu::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_wu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1478,7 +1815,7 @@ unsafe fn test_lsx_vsat_du() { let a = u64x2::new(1953136817312581670, 2606878300382729363); let r = i64x2::new(9007199254740991, 9007199254740991); - assert_eq!(r, transmute(lsx_vsat_du::<52>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_du::<52>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1491,7 +1828,13 @@ unsafe fn test_lsx_vadda_b() { ); let r = i64x2::new(8248499858970022011, 8535863472581999270); - assert_eq!(r, transmute(lsx_vadda_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1500,7 +1843,13 @@ unsafe fn test_lsx_vadda_h() { let b = i16x8::new(-21543, 21720, 14529, -19143, -28953, 13450, 8037, 29413); let r = i64x2::new(-8646732423142600033, 8924050915627474398); - assert_eq!(r, transmute(lsx_vadda_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1509,7 +1858,13 @@ unsafe fn test_lsx_vadda_w() { let b = i32x4::new(287041349, 249467792, 312776520, 1314435078); let r = i64x2::new(8345875378983299469, 6092442344252138029); - assert_eq!(r, transmute(lsx_vadda_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1518,7 +1873,13 @@ unsafe fn test_lsx_vadda_d() { let b = i64x2::new(-4324432602362661920, 6402427893748093984); let r = i64x2::new(6071741662385212188, -5328622052402301597); - assert_eq!(r, transmute(lsx_vadda_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1531,7 +1892,13 @@ unsafe fn test_lsx_vsadd_b() { ); let r = i64x2::new(-3422653801050278697, 1909270979770548186); - assert_eq!(r, transmute(lsx_vsadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1540,7 +1907,13 @@ unsafe fn test_lsx_vsadd_h() { let b = i16x8::new(26970, 17131, 15547, -7614, -8479, 22338, 3567, -22299); let r = i64x2::new(6720170624686097630, -304244782337649222); - assert_eq!(r, transmute(lsx_vsadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1549,7 +1922,13 @@ unsafe fn test_lsx_vsadd_w() { let b = i32x4::new(-1026388582, 222487110, 501504960, -1863994162); let r = i64x2::new(-6565289918505943040, -6915373914453178024); - assert_eq!(r, transmute(lsx_vsadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1558,7 +1937,13 @@ unsafe fn test_lsx_vsadd_d() { let b = i64x2::new(-6599608819082608284, -5088169537193133686); let r = i64x2::new(-8567396806692999839, -9223372036854775808); - assert_eq!(r, transmute(lsx_vsadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1571,7 +1956,13 @@ unsafe fn test_lsx_vsadd_bu() { ); let r = i64x2::new(-5404438145481572386, -7318352348905473); - assert_eq!(r, transmute(lsx_vsadd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1580,7 +1971,13 @@ unsafe fn test_lsx_vsadd_hu() { let b = u16x8::new(31219, 59227, 25607, 62798, 18845, 3238, 19902, 24978); let r = i64x2::new(-8740258447361, -136834913009665); - assert_eq!(r, transmute(lsx_vsadd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1589,7 +1986,13 @@ unsafe fn test_lsx_vsadd_wu() { let b = u32x4::new(3676524021, 3894343575, 904432536, 1616820031); let r = i64x2::new(-1, -7583652642497232897); - assert_eq!(r, transmute(lsx_vsadd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1598,7 +2001,13 @@ unsafe fn test_lsx_vsadd_du() { let b = u64x2::new(11054638512585704882, 3549000132135395099); let r = i64x2::new(-3651327027786652925, -623479558932885349); - assert_eq!(r, transmute(lsx_vsadd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1611,7 +2020,10 @@ unsafe fn test_lsx_vavg_b() { ); let r = i64x2::new(-152206416164856247, 4369276355735447089); - assert_eq!(r, transmute(lsx_vavg_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1620,7 +2032,10 @@ unsafe fn test_lsx_vavg_h() { let b = i16x8::new(-3088, -25854, -32552, -8417, 7808, -12495, 22032, -5168); let r = i64x2::new(696836182083297626, -4337760619710117321); - assert_eq!(r, transmute(lsx_vavg_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1629,7 +2044,10 @@ unsafe fn test_lsx_vavg_w() { let b = i32x4::new(-324844828, -1580060766, -1909832882, 328273785); let r = i64x2::new(475428188150908257, 4521676108535152711); - assert_eq!(r, transmute(lsx_vavg_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1638,7 +2056,10 @@ unsafe fn test_lsx_vavg_d() { let b = i64x2::new(3169904420607189220, 5159962511251707672); let r = i64x2::new(2328313764472338215, 5669256157716045974); - assert_eq!(r, transmute(lsx_vavg_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1651,7 +2072,13 @@ unsafe fn test_lsx_vavg_bu() { ); let r = i64x2::new(-5663745084945885565, 2801126043194071837); - assert_eq!(r, transmute(lsx_vavg_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1660,7 +2087,13 @@ unsafe fn test_lsx_vavg_hu() { let b = u16x8::new(44835, 36733, 12115, 42874, 4819, 12201, 27397, 25394); let r = i64x2::new(-4196978047981735086, -6439149718662907396); - assert_eq!(r, transmute(lsx_vavg_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1669,7 +2102,13 @@ unsafe fn test_lsx_vavg_wu() { let b = u32x4::new(160886383, 26081142, 459122380, 2523086630); let r = i64x2::new(123816739188229069, -5586965600173345916); - assert_eq!(r, transmute(lsx_vavg_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1678,7 +2117,13 @@ unsafe fn test_lsx_vavg_du() { let b = u64x2::new(9749063966076740681, 5963120178993456389); let r = i64x2::new(-7770235857859936532, 7939635441364553211); - assert_eq!(r, transmute(lsx_vavg_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1691,7 +2136,13 @@ unsafe fn test_lsx_vavgr_b() { ); let r = i64x2::new(1883712581662731545, -1226681417271426582); - assert_eq!(r, transmute(lsx_vavgr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1700,7 +2151,13 @@ unsafe fn test_lsx_vavgr_h() { let b = i16x8::new(-9758, -8332, 20577, 31066, 31120, 14788, -22323, 16722); let r = i64x2::new(3801916629507170613, 3994084079587580569); - assert_eq!(r, transmute(lsx_vavgr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1709,7 +2166,13 @@ unsafe fn test_lsx_vavgr_w() { let b = i32x4::new(1278058715, -155858446, -195547847, -750518746); let r = i64x2::new(4040594005688324125, -5795079921582298726); - assert_eq!(r, transmute(lsx_vavgr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1718,7 +2181,13 @@ unsafe fn test_lsx_vavgr_d() { let b = i64x2::new(8758126674980055299, -7441643514470614533); let r = i64x2::new(3399991646978312393, -1904131665097658207); - assert_eq!(r, transmute(lsx_vavgr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1731,7 +2200,13 @@ unsafe fn test_lsx_vavgr_bu() { ); let r = i64x2::new(9122444831751176042, 6010164553039771699); - assert_eq!(r, transmute(lsx_vavgr_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1740,7 +2215,13 @@ unsafe fn test_lsx_vavgr_hu() { let b = u16x8::new(26111, 34713, 61420, 23702, 29204, 9543, 62786, 7043); let r = i64x2::new(7022187818705851223, 4754859411904311722); - assert_eq!(r, transmute(lsx_vavgr_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1749,7 +2230,13 @@ unsafe fn test_lsx_vavgr_wu() { let b = u32x4::new(1930150361, 3668628165, 2983921396, 2410913126); let r = i64x2::new(-5401180487351753235, 8140240017388800980); - assert_eq!(r, transmute(lsx_vavgr_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1758,7 +2245,13 @@ unsafe fn test_lsx_vavgr_du() { let b = u64x2::new(8650759135311802962, 11380630663742852932); let r = i64x2::new(6046550632940509412, 8095423581736830430); - assert_eq!(r, transmute(lsx_vavgr_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1771,7 +2264,13 @@ unsafe fn test_lsx_vssub_b() { ); let r = i64x2::new(628822736562549631, -9187601072510296593); - assert_eq!(r, transmute(lsx_vssub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1780,7 +2279,13 @@ unsafe fn test_lsx_vssub_h() { let b = i16x8::new(-26027, 6118, -13204, 25080, 12458, 8441, 24701, 11617); let r = i64x2::new(-9223231300041015297, 1942699741282756937); - assert_eq!(r, transmute(lsx_vssub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1789,7 +2294,13 @@ unsafe fn test_lsx_vssub_w() { let b = i32x4::new(-1808829767, 2144666490, 146236682, 1180114488); let r = i64x2::new(-9223372035405031217, -177933965588659662); - assert_eq!(r, transmute(lsx_vssub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1798,7 +2309,13 @@ unsafe fn test_lsx_vssub_d() { let b = i64x2::new(-2293337525465880409, 5736255249834646932); let r = i64x2::new(2921430482628531027, -4208815595153969049); - assert_eq!(r, transmute(lsx_vssub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1811,7 +2328,13 @@ unsafe fn test_lsx_vssub_bu() { ); let r = i64x2::new(1441151919413273782, 87960930222283); - assert_eq!(r, transmute(lsx_vssub_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1820,7 +2343,13 @@ unsafe fn test_lsx_vssub_hu() { let b = u16x8::new(50468, 33060, 15257, 59071, 59343, 21993, 42978, 20097); let r = i64x2::new(902801202201243247, -7922957643493867520); - assert_eq!(r, transmute(lsx_vssub_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1829,7 +2358,13 @@ unsafe fn test_lsx_vssub_wu() { let b = u32x4::new(31483972, 3489479082, 152079374, 1875131600); let r = i64x2::new(66202020638834260, 1378022115978010238); - assert_eq!(r, transmute(lsx_vssub_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1838,7 +2373,13 @@ unsafe fn test_lsx_vssub_du() { let b = u64x2::new(6460869225596371206, 16765308520486969885); let r = i64x2::new(8426906920692365065, 0); - assert_eq!(r, transmute(lsx_vssub_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1851,7 +2392,13 @@ unsafe fn test_lsx_vabsd_b() { ); let r = i64x2::new(4230359294854509733, 2116586434120326452); - assert_eq!(r, transmute(lsx_vabsd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1860,7 +2407,13 @@ unsafe fn test_lsx_vabsd_h() { let b = i16x8::new(9346, 27961, 21592, 10762, -6831, 17219, 14968, -1750); let r = i64x2::new(4018377481144584593, 2994052849949411737); - assert_eq!(r, transmute(lsx_vabsd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1869,7 +2422,13 @@ unsafe fn test_lsx_vabsd_w() { let b = i32x4::new(-638463360, -1154268425, 818053243, -1766966029); let r = i64x2::new(4346218292750542585, 1613133471209364690); - assert_eq!(r, transmute(lsx_vabsd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1878,7 +2437,13 @@ unsafe fn test_lsx_vabsd_d() { let b = i64x2::new(-8533946706796471089, 1165272962517390961); let r = i64x2::new(7188249046367538699, 8146605509049538382); - assert_eq!(r, transmute(lsx_vabsd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1891,7 +2456,13 @@ unsafe fn test_lsx_vabsd_bu() { ); let r = i64x2::new(2316568964225934796, 5350198762417854927); - assert_eq!(r, transmute(lsx_vabsd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1900,7 +2471,13 @@ unsafe fn test_lsx_vabsd_hu() { let b = u16x8::new(42102, 40052, 6807, 16289, 29686, 38061, 42843, 26642); let r = i64x2::new(-6889746235852116468, 1175584127230950722); - assert_eq!(r, transmute(lsx_vabsd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1909,7 +2486,13 @@ unsafe fn test_lsx_vabsd_wu() { let b = u32x4::new(3008439409, 976530727, 1726048801, 4235308512); let r = i64x2::new(-5056055741505581388, 103751774096297765); - assert_eq!(r, transmute(lsx_vabsd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1918,7 +2501,13 @@ unsafe fn test_lsx_vabsd_du() { let b = u64x2::new(305704565845198935, 18327726360649467511); let r = i64x2::new(-4540227154002526968, -1590034053554043722); - assert_eq!(r, transmute(lsx_vabsd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1931,7 +2520,10 @@ unsafe fn test_lsx_vmul_b() { ); let r = i64x2::new(-836412611799730432, -7959044669412588992); - assert_eq!(r, transmute(lsx_vmul_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1940,7 +2532,10 @@ unsafe fn test_lsx_vmul_h() { let b = i16x8::new(-18582, -25667, 17674, 8424, -17121, -21798, 28934, -353); let r = i64x2::new(-7419436171490628650, 3947512047518358605); - assert_eq!(r, transmute(lsx_vmul_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1949,7 +2544,10 @@ unsafe fn test_lsx_vmul_w() { let b = i32x4::new(1754730718, 782084571, 894216679, -1895747372); let r = i64x2::new(6602438528086061106, 4680306660704041039); - assert_eq!(r, transmute(lsx_vmul_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1958,7 +2556,10 @@ unsafe fn test_lsx_vmul_d() { let b = i64x2::new(8096709215426138432, -5454415917204378153); let r = i64x2::new(-1062747544199352000, -649255846668983579); - assert_eq!(r, transmute(lsx_vmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1976,7 +2577,11 @@ unsafe fn test_lsx_vmadd_b() { assert_eq!( r, - transmute(lsx_vmadd_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -1989,7 +2594,11 @@ unsafe fn test_lsx_vmadd_h() { assert_eq!( r, - transmute(lsx_vmadd_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2002,7 +2611,11 @@ unsafe fn test_lsx_vmadd_w() { assert_eq!( r, - transmute(lsx_vmadd_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2015,7 +2628,11 @@ unsafe fn test_lsx_vmadd_d() { assert_eq!( r, - transmute(lsx_vmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2034,7 +2651,11 @@ unsafe fn test_lsx_vmsub_b() { assert_eq!( r, - transmute(lsx_vmsub_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2047,7 +2668,11 @@ unsafe fn test_lsx_vmsub_h() { assert_eq!( r, - transmute(lsx_vmsub_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2060,7 +2685,11 @@ unsafe fn test_lsx_vmsub_w() { assert_eq!( r, - transmute(lsx_vmsub_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2073,7 +2702,11 @@ unsafe fn test_lsx_vmsub_d() { assert_eq!( r, - transmute(lsx_vmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2087,7 +2720,10 @@ unsafe fn test_lsx_vdiv_b() { ); let r = i64x2::new(720575944674246657, 281475060530176); - assert_eq!(r, transmute(lsx_vdiv_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2096,7 +2732,10 @@ unsafe fn test_lsx_vdiv_h() { let b = i16x8::new(-11221, 24673, 19931, 3799, -3251, -21373, -13758, -31286); let r = i64x2::new(-1125904201744385, 281470681743353); - assert_eq!(r, transmute(lsx_vdiv_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2105,7 +2744,10 @@ unsafe fn test_lsx_vdiv_w() { let b = i32x4::new(-775731190, 1887886939, 1001718213, 1135075421); let r = i64x2::new(4294967295, 4294967297); - assert_eq!(r, transmute(lsx_vdiv_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2114,7 +2756,10 @@ unsafe fn test_lsx_vdiv_d() { let b = i64x2::new(-9175012156877545557, -6390704898809702209); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2127,7 +2772,13 @@ unsafe fn test_lsx_vdiv_bu() { ); let r = i64x2::new(261, 72058702139687425); - assert_eq!(r, transmute(lsx_vdiv_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2136,7 +2787,13 @@ unsafe fn test_lsx_vdiv_hu() { let b = u16x8::new(25282, 44917, 13706, 63351, 58837, 46710, 29092, 57823); let r = i64x2::new(4294967297, 0); - assert_eq!(r, transmute(lsx_vdiv_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2145,7 +2802,13 @@ unsafe fn test_lsx_vdiv_wu() { let b = u32x4::new(1130189258, 1211056894, 2357258312, 3855913706); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vdiv_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2154,7 +2817,13 @@ unsafe fn test_lsx_vdiv_du() { let b = u64x2::new(14945948123666054968, 10864054932328247404); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vdiv_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2167,7 +2836,13 @@ unsafe fn test_lsx_vhaddw_h_b() { ); let r = i64x2::new(13791943145684950, -562821104926904); - assert_eq!(r, transmute(lsx_vhaddw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2178,7 +2853,13 @@ unsafe fn test_lsx_vhaddw_w_h() { ); let r = i64x2::new(56307021213062, 183021441324639); - assert_eq!(r, transmute(lsx_vhaddw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2187,7 +2868,13 @@ unsafe fn test_lsx_vhaddw_d_w() { let b = i32x4::new(-1119468785, -1334232049, -1752131604, -2016112631); let r = i64x2::new(-2502031305, -1217615295); - assert_eq!(r, transmute(lsx_vhaddw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2200,7 +2887,13 @@ unsafe fn test_lsx_vhaddw_hu_bu() { ); let r = i64x2::new(45601115212087520, 21110838012870921); - assert_eq!(r, transmute(lsx_vhaddw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2209,7 +2902,13 @@ unsafe fn test_lsx_vhaddw_wu_hu() { let b = u16x8::new(40369, 53005, 64424, 35720, 9231, 19965, 20662, 8208); let r = i64x2::new(411432097222434, 312888367535410); - assert_eq!(r, transmute(lsx_vhaddw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2218,7 +2917,13 @@ unsafe fn test_lsx_vhaddw_du_wu() { let b = u32x4::new(728838120, 1267673009, 2659634151, 2264611356); let r = i64x2::new(4172122985, 4839922613); - assert_eq!(r, transmute(lsx_vhaddw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2231,7 +2936,13 @@ unsafe fn test_lsx_vhsubw_h_b() { ); let r = i64x2::new(-4503363402989617, -31243430355664844); - assert_eq!(r, transmute(lsx_vhsubw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2240,7 +2951,13 @@ unsafe fn test_lsx_vhsubw_w_h() { let b = i16x8::new(-14204, -13312, 8240, -4455, -6362, -4711, -30790, -15773); let r = i64x2::new(70059506530916, 60275571046613); - assert_eq!(r, transmute(lsx_vhsubw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2249,7 +2966,13 @@ unsafe fn test_lsx_vhsubw_d_w() { let b = i32x4::new(-1671723008, 870456702, 264823818, 13322401); let r = i64x2::new(-201438605, 449141316); - assert_eq!(r, transmute(lsx_vhsubw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2262,7 +2985,13 @@ unsafe fn test_lsx_vhsubw_hu_bu() { ); let r = i64x2::new(-62206416523952172, 42783380429340790); - assert_eq!(r, transmute(lsx_vhsubw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2271,7 +3000,13 @@ unsafe fn test_lsx_vhsubw_wu_hu() { let b = u16x8::new(5212, 32159, 36502, 59290, 7604, 229, 35511, 47443); let r = i64x2::new(24696062008394, -147484881944276); - assert_eq!(r, transmute(lsx_vhsubw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2280,7 +3015,13 @@ unsafe fn test_lsx_vhsubw_du_wu() { let b = u32x4::new(1383087137, 2403951939, 360532131, 3513614550); let r = i64x2::new(-601935499, 31776736); - assert_eq!(r, transmute(lsx_vhsubw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2293,7 +3034,10 @@ unsafe fn test_lsx_vmod_b() { ); let r = i64x2::new(2804691417388804007, -2461515231199824166); - assert_eq!(r, transmute(lsx_vmod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2302,7 +3046,10 @@ unsafe fn test_lsx_vmod_h() { let b = i16x8::new(1550, 9221, -12080, 14553, -24847, 28286, 1074, 192); let r = i64x2::new(3930282117007147005, -10982007906888970); - assert_eq!(r, transmute(lsx_vmod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2311,7 +3058,10 @@ unsafe fn test_lsx_vmod_w() { let b = i32x4::new(344507881, 1692387020, -1397506903, -1257953510); let r = i64x2::new(-5027973877095011085, 2553570821342119010); - assert_eq!(r, transmute(lsx_vmod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2320,7 +3070,10 @@ unsafe fn test_lsx_vmod_d() { let b = i64x2::new(4636642606889723746, -259899475747531088); let r = i64x2::new(-1381676014874400835, -257849503742906530); - assert_eq!(r, transmute(lsx_vmod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2333,7 +3086,13 @@ unsafe fn test_lsx_vmod_bu() { ); let r = i64x2::new(7287961163701724026, 4745974892933063220); - assert_eq!(r, transmute(lsx_vmod_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2342,7 +3101,13 @@ unsafe fn test_lsx_vmod_hu() { let b = u16x8::new(15317, 24954, 61354, 3720, 21471, 6193, 8193, 35745); let r = i64x2::new(315403234587388856, 7101062794264266609); - assert_eq!(r, transmute(lsx_vmod_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2351,7 +3116,13 @@ unsafe fn test_lsx_vmod_wu() { let b = u32x4::new(49228057, 2249712923, 358897384, 1782599598); let r = i64x2::new(1070413902953059662, 3340025749258890964); - assert_eq!(r, transmute(lsx_vmod_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2360,7 +3131,13 @@ unsafe fn test_lsx_vmod_du() { let b = u64x2::new(16850073055169051895, 16069565262862467484); let r = i64x2::new(7747010922784437137, 20234676239478699); - assert_eq!(r, transmute(lsx_vmod_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2370,7 +3147,7 @@ unsafe fn test_lsx_vreplve_b() { ); let r = i64x2::new(-2893606913523066921, -2893606913523066921); - assert_eq!(r, transmute(lsx_vreplve_b(transmute(a), -8))); + assert_eq!(r, transmute(lsx_vreplve_b(black_box(transmute(a)), -8))); } #[simd_test(enable = "lsx")] @@ -2378,7 +3155,7 @@ unsafe fn test_lsx_vreplve_h() { let a = i16x8::new(-29429, -23495, 8705, -7614, -25353, 11887, -25989, -12818); let r = i64x2::new(-3607719825936298514, -3607719825936298514); - assert_eq!(r, transmute(lsx_vreplve_h(transmute(a), 7))); + assert_eq!(r, transmute(lsx_vreplve_h(black_box(transmute(a)), 7))); } #[simd_test(enable = "lsx")] @@ -2386,7 +3163,7 @@ unsafe fn test_lsx_vreplve_w() { let a = i32x4::new(1584940676, 95787593, -1655264847, 682404402); let r = i64x2::new(411404579393346121, 411404579393346121); - assert_eq!(r, transmute(lsx_vreplve_w(transmute(a), -3))); + assert_eq!(r, transmute(lsx_vreplve_w(black_box(transmute(a)), -3))); } #[simd_test(enable = "lsx")] @@ -2394,7 +3171,7 @@ unsafe fn test_lsx_vreplve_d() { let a = i64x2::new(7614424214598615675, -7096892795239148002); let r = i64x2::new(7614424214598615675, 7614424214598615675); - assert_eq!(r, transmute(lsx_vreplve_d(transmute(a), 0))); + assert_eq!(r, transmute(lsx_vreplve_d(black_box(transmute(a)), 0))); } #[simd_test(enable = "lsx")] @@ -2404,7 +3181,7 @@ unsafe fn test_lsx_vreplvei_b() { ); let r = i64x2::new(-2097865012304223518, -2097865012304223518); - assert_eq!(r, transmute(lsx_vreplvei_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2412,7 +3189,7 @@ unsafe fn test_lsx_vreplvei_h() { let a = i16x8::new(-15455, -4410, 5029, 25863, -23170, 26570, 27423, -834); let r = i64x2::new(7719006069021698847, 7719006069021698847); - assert_eq!(r, transmute(lsx_vreplvei_h::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_h::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2420,7 +3197,7 @@ unsafe fn test_lsx_vreplvei_w() { let a = i32x4::new(1843143434, 491125746, -328585251, -1996512058); let r = i64x2::new(7916240772710277898, 7916240772710277898); - assert_eq!(r, transmute(lsx_vreplvei_w::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_w::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2428,7 +3205,7 @@ unsafe fn test_lsx_vreplvei_d() { let a = i64x2::new(4333963848299154309, -8310246545782080694); let r = i64x2::new(-8310246545782080694, -8310246545782080694); - assert_eq!(r, transmute(lsx_vreplvei_d::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_d::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2441,7 +3218,13 @@ unsafe fn test_lsx_vpickev_b() { ); let r = i64x2::new(3921750152141124833, -933322373843017127); - assert_eq!(r, transmute(lsx_vpickev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2450,7 +3233,13 @@ unsafe fn test_lsx_vpickev_h() { let b = i16x8::new(-5248, -1786, -21768, 23214, -4223, 23538, -24936, -32316); let r = i64x2::new(-7018596679058658432, 139073165196191894); - assert_eq!(r, transmute(lsx_vpickev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2459,7 +3248,13 @@ unsafe fn test_lsx_vpickev_w() { let b = i32x4::new(-1187277846, -787064901, -980229113, 1746235326); let r = i64x2::new(-4210051979814398998, -769258006856513132); - assert_eq!(r, transmute(lsx_vpickev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2468,7 +3263,13 @@ unsafe fn test_lsx_vpickev_d() { let b = i64x2::new(6574352346370076190, -3979792156310826694); let r = i64x2::new(6574352346370076190, 1789073368466131160); - assert_eq!(r, transmute(lsx_vpickev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2481,7 +3282,13 @@ unsafe fn test_lsx_vpickod_b() { ); let r = i64x2::new(8220640377280882872, -6083110277645985532); - assert_eq!(r, transmute(lsx_vpickod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2490,7 +3297,13 @@ unsafe fn test_lsx_vpickod_h() { let b = i16x8::new(12047, 25024, -10709, -28077, 24357, 19934, 10289, 28546); let r = i64x2::new(8035070303515402688, 6167254016163165900); - assert_eq!(r, transmute(lsx_vpickod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2499,7 +3312,13 @@ unsafe fn test_lsx_vpickod_w() { let b = i32x4::new(-99240403, 314407358, 543396756, 1976776696); let r = i64x2::new(8490191261129341374, -7045044594236590438); - assert_eq!(r, transmute(lsx_vpickod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2508,7 +3327,13 @@ unsafe fn test_lsx_vpickod_d() { let b = i64x2::new(-4197243771252175958, -543692393753629390); let r = i64x2::new(-543692393753629390, -7578696032343374601); - assert_eq!(r, transmute(lsx_vpickod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2521,7 +3346,13 @@ unsafe fn test_lsx_vilvh_b() { ); let r = i64x2::new(1211180715666052671, -2634368371891034045); - assert_eq!(r, transmute(lsx_vilvh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2530,7 +3361,13 @@ unsafe fn test_lsx_vilvh_h() { let b = i16x8::new(23768, -31845, 28689, 14757, 9499, 7795, -13573, -10011); let r = i64x2::new(-4714953853167983333, 4564918175499275003); - assert_eq!(r, transmute(lsx_vilvh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2539,7 +3376,13 @@ unsafe fn test_lsx_vilvh_w() { let b = i32x4::new(-737076987, 38515006, 602108871, -63099569); let r = i64x2::new(-5365723764939852857, -1200522227779556017); - assert_eq!(r, transmute(lsx_vilvh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2548,7 +3391,13 @@ unsafe fn test_lsx_vilvh_d() { let b = i64x2::new(-2160658667838026389, 1449429407527660400); let r = i64x2::new(1449429407527660400, 5375050218784453679); - assert_eq!(r, transmute(lsx_vilvh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2561,7 +3410,13 @@ unsafe fn test_lsx_vilvl_b() { ); let r = i64x2::new(6945744258789947856, 8515979671552484861); - assert_eq!(r, transmute(lsx_vilvl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2570,7 +3425,13 @@ unsafe fn test_lsx_vilvl_h() { let b = i16x8::new(11601, 6788, 3174, -4208, -25999, -25660, -4591, 7133); let r = i64x2::new(-6560589601043632815, -2260825085889541018); - assert_eq!(r, transmute(lsx_vilvl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2579,7 +3440,13 @@ unsafe fn test_lsx_vilvl_w() { let b = i32x4::new(486029703, 1245981961, 112180197, 1939621508); let r = i64x2::new(-4282490222245561977, 7435326725564935433); - assert_eq!(r, transmute(lsx_vilvl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2588,7 +3455,13 @@ unsafe fn test_lsx_vilvl_d() { let b = i64x2::new(3142531875873363679, 736682102982019415); let r = i64x2::new(3142531875873363679, 7063413230460842607); - assert_eq!(r, transmute(lsx_vilvl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2601,7 +3474,13 @@ unsafe fn test_lsx_vpackev_b() { ); let r = i64x2::new(-1928363389519380677, -1882898104368665381); - assert_eq!(r, transmute(lsx_vpackev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2610,7 +3489,13 @@ unsafe fn test_lsx_vpackev_h() { let b = i16x8::new(-9444, 5210, -14402, 17972, 16606, 2450, 5123, 14727); let r = i64x2::new(7533052947329899292, 1461440082551914718); - assert_eq!(r, transmute(lsx_vpackev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2619,7 +3504,13 @@ unsafe fn test_lsx_vpackev_w() { let b = i32x4::new(-872903277, 1255047449, -2110158279, 682925573); let r = i64x2::new(5636997704425442707, -8345976908349339079); - assert_eq!(r, transmute(lsx_vpackev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2628,7 +3519,13 @@ unsafe fn test_lsx_vpackev_d() { let b = i64x2::new(-9119315954224042738, -4563700463464702181); let r = i64x2::new(-9119315954224042738, 7118943335298607169); - assert_eq!(r, transmute(lsx_vpackev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2641,7 +3538,13 @@ unsafe fn test_lsx_vpackod_b() { ); let r = i64x2::new(4389351353151377653, -4315624792288929032); - assert_eq!(r, transmute(lsx_vpackod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2650,7 +3553,13 @@ unsafe fn test_lsx_vpackod_h() { let b = i16x8::new(-23247, 17928, -13353, -20146, 5696, 22071, -10728, -30262); let r = i64x2::new(-4433598883325590008, -9178747487946648009); - assert_eq!(r, transmute(lsx_vpackod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2659,7 +3568,13 @@ unsafe fn test_lsx_vpackod_w() { let b = i32x4::new(445270781, 793617340, -1461557030, -22199234); let r = i64x2::new(51238874735551420, 6731566319615689790); - assert_eq!(r, transmute(lsx_vpackod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2668,7 +3583,13 @@ unsafe fn test_lsx_vpackod_d() { let b = i64x2::new(9039771682296134623, -6404442538060227683); let r = i64x2::new(-6404442538060227683, -4670773907187480618); - assert_eq!(r, transmute(lsx_vpackod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2680,7 +3601,11 @@ unsafe fn test_lsx_vshuf_h() { assert_eq!( r, - transmute(lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2693,7 +3618,11 @@ unsafe fn test_lsx_vshuf_w() { assert_eq!( r, - transmute(lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2706,7 +3635,11 @@ unsafe fn test_lsx_vshuf_d() { assert_eq!( r, - transmute(lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2720,7 +3653,10 @@ unsafe fn test_lsx_vand_v() { ); let r = i64x2::new(244105884219744360, -9223116804091473582); - assert_eq!(r, transmute(lsx_vand_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vand_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2730,7 +3666,7 @@ unsafe fn test_lsx_vandi_b() { ); let r = i64x2::new(-8135737750142058361, -7666517314596397435); - assert_eq!(r, transmute(lsx_vandi_b::<159>(transmute(a)))); + assert_eq!(r, transmute(lsx_vandi_b::<159>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2743,7 +3679,10 @@ unsafe fn test_lsx_vor_v() { ); let r = i64x2::new(-2351582766212852737, -4924766118269159990); - assert_eq!(r, transmute(lsx_vor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2753,7 +3692,7 @@ unsafe fn test_lsx_vori_b() { ); let r = i64x2::new(-589140355308650538, -3179554720060804109); - assert_eq!(r, transmute(lsx_vori_b::<210>(transmute(a)))); + assert_eq!(r, transmute(lsx_vori_b::<210>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2766,7 +3705,10 @@ unsafe fn test_lsx_vnor_v() { ); let r = i64x2::new(3036560889408918025, 7823034030269427744); - assert_eq!(r, transmute(lsx_vnor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vnor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2776,7 +3718,7 @@ unsafe fn test_lsx_vnori_b() { ); let r = i64x2::new(5227628601268782144, 596802560304890884); - assert_eq!(r, transmute(lsx_vnori_b::<51>(transmute(a)))); + assert_eq!(r, transmute(lsx_vnori_b::<51>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2789,7 +3731,10 @@ unsafe fn test_lsx_vxor_v() { ); let r = i64x2::new(8732028225622312747, 6858262329367852470); - assert_eq!(r, transmute(lsx_vxor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vxor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2799,7 +3744,7 @@ unsafe fn test_lsx_vxori_b() { ); let r = i64x2::new(3478586993001400570, 4687744515358339026); - assert_eq!(r, transmute(lsx_vxori_b::<225>(transmute(a)))); + assert_eq!(r, transmute(lsx_vxori_b::<225>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2817,7 +3762,11 @@ unsafe fn test_lsx_vbitsel_v() { assert_eq!( r, - transmute(lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vbitsel_v( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2833,7 +3782,10 @@ unsafe fn test_lsx_vbitseli_b() { assert_eq!( r, - transmute(lsx_vbitseli_b::<65>(transmute(a), transmute(b))) + transmute(lsx_vbitseli_b::<65>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -2844,7 +3796,7 @@ unsafe fn test_lsx_vshuf4i_b() { ); let r = i64x2::new(3937170420478429898, -3347145886530736916); - assert_eq!(r, transmute(lsx_vshuf4i_b::<234>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_b::<234>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2852,7 +3804,7 @@ unsafe fn test_lsx_vshuf4i_h() { let a = i16x8::new(27707, -1094, -15784, -28387, 31634, -12323, -30387, -11480); let r = i64x2::new(-7989953385787032646, -3231104182470389795); - assert_eq!(r, transmute(lsx_vshuf4i_h::<209>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_h::<209>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2860,35 +3812,38 @@ unsafe fn test_lsx_vshuf4i_w() { let a = i32x4::new(768986805, -1036149600, -1196682940, -214444511); let r = i64x2::new(3302773179299516085, -5139714087882845884); - assert_eq!(r, transmute(lsx_vshuf4i_w::<160>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_w::<160>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_b() { let r = i64x2::new(795741901218843403, 795741901218843403); - assert_eq!(r, transmute(lsx_vreplgr2vr_b(970839819))); + assert_eq!(r, transmute(lsx_vreplgr2vr_b(black_box(970839819)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_h() { let r = i64x2::new(-6504141532176800324, -6504141532176800324); - assert_eq!(r, transmute(lsx_vreplgr2vr_h(93693372))); + assert_eq!(r, transmute(lsx_vreplgr2vr_h(black_box(93693372)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_w() { let r = i64x2::new(-6737078705572473188, -6737078705572473188); - assert_eq!(r, transmute(lsx_vreplgr2vr_w(-1568598372))); + assert_eq!(r, transmute(lsx_vreplgr2vr_w(black_box(-1568598372)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_d() { let r = i64x2::new(5000134708087557572, 5000134708087557572); - assert_eq!(r, transmute(lsx_vreplgr2vr_d(5000134708087557572))); + assert_eq!( + r, + transmute(lsx_vreplgr2vr_d(black_box(5000134708087557572))) + ); } #[simd_test(enable = "lsx")] @@ -2898,7 +3853,7 @@ unsafe fn test_lsx_vpcnt_b() { ); let r = i64x2::new(217867142450840068, 145528077781566722); - assert_eq!(r, transmute(lsx_vpcnt_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2906,7 +3861,7 @@ unsafe fn test_lsx_vpcnt_h() { let a = i16x8::new(-512, 10388, -21267, -27094, 1085, -26444, -29360, -11576); let r = i64x2::new(1970367786975239, 1970350607237126); - assert_eq!(r, transmute(lsx_vpcnt_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2914,7 +3869,7 @@ unsafe fn test_lsx_vpcnt_w() { let a = i32x4::new(1399276601, -2094725994, -100739325, -1239551533); let r = i64x2::new(47244640271, 81604378645); - assert_eq!(r, transmute(lsx_vpcnt_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2922,7 +3877,7 @@ unsafe fn test_lsx_vpcnt_d() { let a = i64x2::new(-4470823169399930539, 3184270543884128372); let r = i64x2::new(29, 25); - assert_eq!(r, transmute(lsx_vpcnt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2932,7 +3887,7 @@ unsafe fn test_lsx_vclo_b() { ); let r = i64x2::new(72057594071547904, 3311470116864); - assert_eq!(r, transmute(lsx_vclo_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2940,7 +3895,7 @@ unsafe fn test_lsx_vclo_h() { let a = i16x8::new(-5432, 27872, -9150, 27393, 25236, 1028, -21312, -25189); let r = i64x2::new(8589934595, 281479271677952); - assert_eq!(r, transmute(lsx_vclo_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2948,7 +3903,7 @@ unsafe fn test_lsx_vclo_w() { let a = i32x4::new(1214322611, -1755838761, -1222326743, -1511364419); let r = i64x2::new(4294967296, 4294967297); - assert_eq!(r, transmute(lsx_vclo_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2956,7 +3911,7 @@ unsafe fn test_lsx_vclo_d() { let a = i64x2::new(-249299854527467825, -459308653408461862); let r = i64x2::new(6, 5); - assert_eq!(r, transmute(lsx_vclo_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2966,7 +3921,7 @@ unsafe fn test_lsx_vclz_b() { ); let r = i64x2::new(144116287587483648, 72903118479688195); - assert_eq!(r, transmute(lsx_vclz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2974,7 +3929,7 @@ unsafe fn test_lsx_vclz_h() { let a = i16x8::new(1222, 32426, 3164, -10763, 10189, -4197, -21841, -28676); let r = i64x2::new(17179934725, 2); - assert_eq!(r, transmute(lsx_vclz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2982,7 +3937,7 @@ unsafe fn test_lsx_vclz_w() { let a = i32x4::new(-490443689, -1039971379, -217310592, -1921086575); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vclz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2990,7 +3945,7 @@ unsafe fn test_lsx_vclz_d() { let a = i64x2::new(4630351532137644314, -6587611980764816064); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vclz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3000,7 +3955,10 @@ unsafe fn test_lsx_vpickve2gr_b() { ); let r: i32 = 51; - assert_eq!(r, transmute(lsx_vpickve2gr_b::<15>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_b::<15>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3008,7 +3966,7 @@ unsafe fn test_lsx_vpickve2gr_h() { let a = i16x8::new(-12924, 31013, 18171, 20404, 21226, 14128, -6255, 26521); let r: i32 = 21226; - assert_eq!(r, transmute(lsx_vpickve2gr_h::<4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_h::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3016,7 +3974,7 @@ unsafe fn test_lsx_vpickve2gr_w() { let a = i32x4::new(-1559379275, 2065542381, -1882161334, 1502157419); let r: i32 = -1882161334; - assert_eq!(r, transmute(lsx_vpickve2gr_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3024,7 +3982,7 @@ unsafe fn test_lsx_vpickve2gr_d() { let a = i64x2::new(-6941380853339482104, 8405634758774935528); let r: i64 = -6941380853339482104; - assert_eq!(r, transmute(lsx_vpickve2gr_d::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_d::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3034,7 +3992,10 @@ unsafe fn test_lsx_vpickve2gr_bu() { ); let r: u32 = 199; - assert_eq!(r, transmute(lsx_vpickve2gr_bu::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_bu::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3042,7 +4003,10 @@ unsafe fn test_lsx_vpickve2gr_hu() { let a = i16x8::new(25003, 5139, -12977, 7550, -12177, 19294, -2216, 12693); let r: u32 = 25003; - assert_eq!(r, transmute(lsx_vpickve2gr_hu::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_hu::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3050,7 +4014,10 @@ unsafe fn test_lsx_vpickve2gr_wu() { let a = i32x4::new(-295894883, 551663550, -710853968, 82692774); let r: u32 = 3999072413; - assert_eq!(r, transmute(lsx_vpickve2gr_wu::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_wu::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3058,7 +4025,10 @@ unsafe fn test_lsx_vpickve2gr_du() { let a = i64x2::new(748282319555413922, -1352335765832355666); let r: u64 = 748282319555413922; - assert_eq!(r, transmute(lsx_vpickve2gr_du::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_du::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3070,7 +4040,7 @@ unsafe fn test_lsx_vinsgr2vr_b() { assert_eq!( r, - transmute(lsx_vinsgr2vr_b::<14>(transmute(a), 1333652061)) + transmute(lsx_vinsgr2vr_b::<14>(black_box(transmute(a)), 1333652061)) ); } @@ -3079,7 +4049,10 @@ unsafe fn test_lsx_vinsgr2vr_h() { let a = i16x8::new(-20591, 7819, 25287, -11296, 4604, 28833, -1306, 6418); let r = i64x2::new(-3179432729573085295, 1806782266980897276); - assert_eq!(r, transmute(lsx_vinsgr2vr_h::<5>(transmute(a), -987420193))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_h::<5>(black_box(transmute(a)), -987420193)) + ); } #[simd_test(enable = "lsx")] @@ -3087,7 +4060,10 @@ unsafe fn test_lsx_vinsgr2vr_w() { let a = i32x4::new(1608179655, 886830932, -621638499, 2021214690); let r = i64x2::new(3808909851629379527, 8681050995079237782); - assert_eq!(r, transmute(lsx_vinsgr2vr_w::<2>(transmute(a), -960507754))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_w::<2>(black_box(transmute(a)), -960507754)) + ); } #[simd_test(enable = "lsx")] @@ -3095,7 +4071,10 @@ unsafe fn test_lsx_vinsgr2vr_d() { let a = i64x2::new(-6562091001143116290, -2425423285843953307); let r = i64x2::new(-6562091001143116290, -233659266); - assert_eq!(r, transmute(lsx_vinsgr2vr_d::<1>(transmute(a), -233659266))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_d::<1>(black_box(transmute(a)), -233659266)) + ); } #[simd_test(enable = "lsx")] @@ -3104,7 +4083,13 @@ unsafe fn test_lsx_vfadd_s() { let b = u32x4::new(1050272808, 1054022924, 1064036136, 1063113730); let r = i64x2::new(4588396142719948771, 4567018621615066847); - assert_eq!(r, transmute(lsx_vfadd_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfadd_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3113,7 +4098,13 @@ unsafe fn test_lsx_vfadd_d() { let b = u64x2::new(4605819027271079334, 4601207158507578498); let r = i64x2::new(4608685566198055604, 4608371493448991663); - assert_eq!(r, transmute(lsx_vfadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3122,7 +4113,13 @@ unsafe fn test_lsx_vfsub_s() { let b = u32x4::new(1063475462, 1045836432, 1065150677, 1042376676); let r = i64x2::new(4532926601401089072, 4475386505810184670); - assert_eq!(r, transmute(lsx_vfsub_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfsub_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3131,7 +4128,13 @@ unsafe fn test_lsx_vfsub_d() { let b = u64x2::new(4605973926398825814, 4600156145303017004); let r = i64x2::new(-4622342180736116526, 4603750919602422881); - assert_eq!(r, transmute(lsx_vfsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3140,7 +4143,13 @@ unsafe fn test_lsx_vfmul_s() { let b = u32x4::new(1065241951, 1044285812, 1050678216, 1009264512); let r = i64x2::new(4471727895898079441, 4289440988347233543); - assert_eq!(r, transmute(lsx_vfmul_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmul_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3149,7 +4158,13 @@ unsafe fn test_lsx_vfmul_d() { let b = u64x2::new(4605208047666947899, 4599634375243914522); let r = i64x2::new(4591550625791030606, 4595475933048682142); - assert_eq!(r, transmute(lsx_vfmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3158,7 +4173,13 @@ unsafe fn test_lsx_vfdiv_s() { let b = u32x4::new(1055538538, 1042248668, 1061233585, 1063649172); let r = i64x2::new(4613180427594946541, 4523223175100126088); - assert_eq!(r, transmute(lsx_vfdiv_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfdiv_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3167,7 +4188,13 @@ unsafe fn test_lsx_vfdiv_d() { let b = u64x2::new(4606326032528596062, 4601783079746725386); let r = i64x2::new(4592460108638699314, 4612120084672695832); - assert_eq!(r, transmute(lsx_vfdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3176,7 +4203,13 @@ unsafe fn test_lsx_vfcvt_h_s() { let b = u32x4::new(1049501482, 1043939972, 1042291392, 1041250232); let r = i64x2::new(3495410141992989809, 3873441386606634666); - assert_eq!(r, transmute(lsx_vfcvt_h_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcvt_h_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3185,7 +4218,13 @@ unsafe fn test_lsx_vfcvt_s_d() { let b = u64x2::new(4600251021237488420, 4593890179408150924); let r = i64x2::new(4469319308295208818, 4496796258465732597); - assert_eq!(r, transmute(lsx_vfcvt_s_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcvt_s_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3194,7 +4233,13 @@ unsafe fn test_lsx_vfmin_s() { let b = u32x4::new(1060093085, 1026130528, 1057322097, 1057646773); let r = i64x2::new(4407197060203522560, 4542558301798153756); - assert_eq!(r, transmute(lsx_vfmin_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmin_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3203,7 +4248,13 @@ unsafe fn test_lsx_vfmin_d() { let b = u64x2::new(4584808359801648672, 4602712060570539582); let r = i64x2::new(4584808359801648672, 4602712060570539582); - assert_eq!(r, transmute(lsx_vfmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3212,7 +4263,13 @@ unsafe fn test_lsx_vfmina_s() { let b = u32x4::new(1049119234, 1058336224, 1057046116, 1029386720); let r = i64x2::new(4519411155382848002, 4421182298393539560); - assert_eq!(r, transmute(lsx_vfmina_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmina_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3221,7 +4278,13 @@ unsafe fn test_lsx_vfmina_d() { let b = u64x2::new(4599088744110071826, 4598732503789588496); let r = i64x2::new(4599088744110071826, 4598732503789588496); - assert_eq!(r, transmute(lsx_vfmina_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmina_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3230,7 +4293,13 @@ unsafe fn test_lsx_vfmax_s() { let b = u32x4::new(1042175760, 1040826492, 1059132266, 1050815434); let r = i64x2::new(4557520760982391874, 4573984521684325226); - assert_eq!(r, transmute(lsx_vfmax_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmax_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3239,7 +4308,13 @@ unsafe fn test_lsx_vfmax_d() { let b = u64x2::new(4593616624275112016, 4605244843740986156); let r = i64x2::new(4606275407710467505, 4605244843740986156); - assert_eq!(r, transmute(lsx_vfmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3248,7 +4323,13 @@ unsafe fn test_lsx_vfmaxa_s() { let b = u32x4::new(1064739422, 1055122552, 1049654310, 1057411362); let r = i64x2::new(4531716855176798814, 4541547219258471462); - assert_eq!(r, transmute(lsx_vfmaxa_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmaxa_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3257,7 +4338,13 @@ unsafe fn test_lsx_vfmaxa_d() { let b = u64x2::new(4603647289310579471, 4603999027307573908); let r = i64x2::new(4603647289310579471, 4606304546706191737); - assert_eq!(r, transmute(lsx_vfmaxa_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmaxa_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3265,7 +4352,7 @@ unsafe fn test_lsx_vfclass_s() { let a = u32x4::new(1059786314, 1058231666, 1061513647, 1038650488); let r = i64x2::new(549755814016, 549755814016); - assert_eq!(r, transmute(lsx_vfclass_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfclass_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3273,7 +4360,7 @@ unsafe fn test_lsx_vfclass_d() { let a = u64x2::new(4601724705608768104, 4601126152607382566); let r = i64x2::new(128, 128); - assert_eq!(r, transmute(lsx_vfclass_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfclass_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3281,7 +4368,7 @@ unsafe fn test_lsx_vfsqrt_s() { let a = u32x4::new(1055398716, 1050305974, 995168768, 1064901995); let r = i64x2::new(4543169501430832482, 4574681629207255333); - assert_eq!(r, transmute(lsx_vfsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3289,7 +4376,7 @@ unsafe fn test_lsx_vfsqrt_d() { let a = u64x2::new(4605784293613801157, 4602267946351406890); let r = i64x2::new(4606453893731357485, 4604397310232711799); - assert_eq!(r, transmute(lsx_vfsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3297,7 +4384,7 @@ unsafe fn test_lsx_vfrecip_s() { let a = u32x4::new(1003452672, 1050811504, 1044295808, 1064402913); let r = i64x2::new(4632552602764963931, 4577820515916044016); - assert_eq!(r, transmute(lsx_vfrecip_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecip_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3305,7 +4392,7 @@ unsafe fn test_lsx_vfrecip_d() { let a = u64x2::new(4598634931235673106, 4598630619264835010); let r = i64x2::new(4615355353482170689, 4615362460048142095); - assert_eq!(r, transmute(lsx_vfrecip_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecip_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3313,7 +4400,7 @@ unsafe fn test_lsx_vfrecipe_s() { let a = u32x4::new(1057583779, 1062308847, 1060089100, 1048454688); let r = i64x2::new(4583644530211711115, 4647978179615164140); - assert_eq!(r, transmute(lsx_vfrecipe_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecipe_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3321,7 +4408,7 @@ unsafe fn test_lsx_vfrecipe_d() { let a = u64x2::new(4605515926442181274, 4605369703273365674); let r = i64x2::new(4608204937770303488, 4608317161507651584); - assert_eq!(r, transmute(lsx_vfrecipe_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecipe_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3329,7 +4416,7 @@ unsafe fn test_lsx_vfrsqrte_s() { let a = u32x4::new(1064377488, 1055815904, 1056897740, 1064016656); let r = i64x2::new(4592421282989204764, 4577184195020153336); - assert_eq!(r, transmute(lsx_vfrsqrte_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrte_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3337,7 +4424,7 @@ unsafe fn test_lsx_vfrsqrte_d() { let a = u64x2::new(4602766865443628663, 4605323203937791867); let r = i64x2::new(4608986772678901760, 4607734355383549952); - assert_eq!(r, transmute(lsx_vfrsqrte_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrte_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3345,7 +4432,7 @@ unsafe fn test_lsx_vfrint_s() { let a = u32x4::new(1062138521, 1056849108, 1034089720, 1038314384); let r = i64x2::new(1065353216, 0); - assert_eq!(r, transmute(lsx_vfrint_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrint_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3353,7 +4440,7 @@ unsafe fn test_lsx_vfrint_d() { let a = u64x2::new(4598620052333442366, 4603262362368837514); let r = i64x2::new(0, 4607182418800017408); - assert_eq!(r, transmute(lsx_vfrint_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrint_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3361,7 +4448,7 @@ unsafe fn test_lsx_vfrsqrt_s() { let a = u32x4::new(1058614029, 1050504950, 1013814976, 1062355001); let r = i64x2::new(4604601921912011494, 4579384257679777264); - assert_eq!(r, transmute(lsx_vfrsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3369,7 +4456,7 @@ unsafe fn test_lsx_vfrsqrt_d() { let a = u64x2::new(4602924191185043139, 4606088351077917251); let r = i64x2::new(4608881149202581394, 4607483676176768181); - assert_eq!(r, transmute(lsx_vfrsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3377,7 +4464,7 @@ unsafe fn test_lsx_vflogb_s() { let a = u32x4::new(1053488512, 1061429282, 1064965594, 1061326585); let r = i64x2::new(-4647714812225126400, -4647714812233515008); - assert_eq!(r, transmute(lsx_vflogb_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vflogb_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3385,7 +4472,7 @@ unsafe fn test_lsx_vflogb_d() { let a = u64x2::new(4589481276789128632, 4599408395082246526); let r = i64x2::new(-4607182418800017408, -4611686018427387904); - assert_eq!(r, transmute(lsx_vflogb_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vflogb_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3393,7 +4480,7 @@ unsafe fn test_lsx_vfcvth_s_h() { let a = i16x8::new(29550, -13884, 689, -1546, 24006, -19112, -12769, 1779); let r = i64x2::new(-4707668984349540352, 4097818267320836096); - assert_eq!(r, transmute(lsx_vfcvth_s_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvth_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3401,7 +4488,7 @@ unsafe fn test_lsx_vfcvth_d_s() { let a = u32x4::new(1051543000, 1042275304, 1038283216, 1063876621); let r = i64x2::new(4592649323212177408, 4606389677895712768); - assert_eq!(r, transmute(lsx_vfcvth_d_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvth_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3409,7 +4496,7 @@ unsafe fn test_lsx_vfcvtl_s_h() { let a = i16x8::new(-21951, -13772, -17190, 9566, -19227, 9682, 13427, -30861); let r = i64x2::new(-4519784435355738112, 4371798972740354048); - assert_eq!(r, transmute(lsx_vfcvtl_s_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvtl_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3417,7 +4504,7 @@ unsafe fn test_lsx_vfcvtl_d_s() { let a = u32x4::new(1059809930, 1051084496, 1062618346, 1058273673); let r = i64x2::new(4604206389789720576, 4599521958080544768); - assert_eq!(r, transmute(lsx_vfcvtl_d_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvtl_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3425,7 +4512,7 @@ unsafe fn test_lsx_vftint_w_s() { let a = u32x4::new(1064738153, 1040181800, 1064331056, 1050732566); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftint_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3433,7 +4520,7 @@ unsafe fn test_lsx_vftint_l_d() { let a = u64x2::new(4602244632405616462, 4606437548563176328); let r = i64x2::new(0, 1); - assert_eq!(r, transmute(lsx_vftint_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3441,7 +4528,7 @@ unsafe fn test_lsx_vftint_wu_s() { let a = u32x4::new(1051598962, 1051261298, 1059326008, 1057784192); let r = i64x2::new(0, 4294967297); - assert_eq!(r, transmute(lsx_vftint_wu_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3449,7 +4536,7 @@ unsafe fn test_lsx_vftint_lu_d() { let a = u64x2::new(4605561240422589260, 4595241299507769712); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftint_lu_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3457,7 +4544,7 @@ unsafe fn test_lsx_vftintrz_w_s() { let a = u32x4::new(1027659872, 1064207676, 1058472873, 1055740014); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3465,7 +4552,7 @@ unsafe fn test_lsx_vftintrz_l_d() { let a = u64x2::new(4605051539601556532, 4605129242354661923); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3473,7 +4560,7 @@ unsafe fn test_lsx_vftintrz_wu_s() { let a = u32x4::new(1060876751, 1053710034, 1057340881, 1055555596); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_wu_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3481,7 +4568,7 @@ unsafe fn test_lsx_vftintrz_lu_d() { let a = u64x2::new(4598711097624940956, 4598268778109474002); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_lu_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3489,7 +4576,7 @@ unsafe fn test_lsx_vffint_s_w() { let a = i32x4::new(81337967, 1396520141, 2124859806, 1655115736); let r = i64x2::new(5667351778062705614, 5676028806041521555); - assert_eq!(r, transmute(lsx_vffint_s_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_s_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3497,7 +4584,7 @@ unsafe fn test_lsx_vffint_d_l() { let a = i64x2::new(-1543454772280682525, -7672333112582708041); let r = i64x2::new(-4344448119835677720, -4333977527979901593); - assert_eq!(r, transmute(lsx_vffint_d_l(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_d_l(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3505,7 +4592,7 @@ unsafe fn test_lsx_vffint_s_wu() { let a = u32x4::new(2224947834, 194720725, 2248289069, 1131100007); let r = i64x2::new(5564675890493038082, 5658445755393114667); - assert_eq!(r, transmute(lsx_vffint_s_wu(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_s_wu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3513,7 +4600,7 @@ unsafe fn test_lsx_vffint_d_lu() { let a = u64x2::new(11793247389644223387, 1356636411353166515); let r = i64x2::new(4892164017273962878, 4878194157796724979); - assert_eq!(r, transmute(lsx_vffint_d_lu(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_d_lu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3526,7 +4613,13 @@ unsafe fn test_lsx_vandn_v() { ); let r = i64x2::new(184648152262214664, 2315143230533931624); - assert_eq!(r, transmute(lsx_vandn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vandn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3536,7 +4629,7 @@ unsafe fn test_lsx_vneg_b() { ); let r = i64x2::new(-6195839201974406282, 3566844512212398771); - assert_eq!(r, transmute(lsx_vneg_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3544,7 +4637,7 @@ unsafe fn test_lsx_vneg_h() { let a = i16x8::new(-6540, 25893, -2534, 29805, -28719, -16331, -20168, 14650); let r = i64x2::new(-8389350794815923828, -4123521786840387537); - assert_eq!(r, transmute(lsx_vneg_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3552,7 +4645,7 @@ unsafe fn test_lsx_vneg_w() { let a = i32x4::new(-927815384, -898911982, 716171852, -2025175544); let r = i64x2::new(3860797565600356056, 8698062733717804468); - assert_eq!(r, transmute(lsx_vneg_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3560,7 +4653,7 @@ unsafe fn test_lsx_vneg_d() { let a = i64x2::new(4241851098775470984, 2487122929432859927); let r = i64x2::new(-4241851098775470984, -2487122929432859927); - assert_eq!(r, transmute(lsx_vneg_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3573,7 +4666,10 @@ unsafe fn test_lsx_vmuh_b() { ); let r = i64x2::new(931993372669836524, 2017024359980467698); - assert_eq!(r, transmute(lsx_vmuh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3582,7 +4678,10 @@ unsafe fn test_lsx_vmuh_h() { let b = i16x8::new(-446, -16863, 19467, -13578, -9673, -26572, -7864, 9855); let r = i64x2::new(-1422322400225984462, -842721997477184351); - assert_eq!(r, transmute(lsx_vmuh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3591,7 +4690,10 @@ unsafe fn test_lsx_vmuh_w() { let b = i32x4::new(-1684820454, 449222301, 1106076122, 431017950); let r = i64x2::new(-950505610786872114, 420439596918869732); - assert_eq!(r, transmute(lsx_vmuh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3600,7 +4702,10 @@ unsafe fn test_lsx_vmuh_d() { let b = i64x2::new(-1208434038665242614, -6078343251861677818); let r = i64x2::new(-121343209662433286, 284995587689374477); - assert_eq!(r, transmute(lsx_vmuh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3613,7 +4718,13 @@ unsafe fn test_lsx_vmuh_bu() { ); let r = i64x2::new(8725461799780227590, -3369022092985820632); - assert_eq!(r, transmute(lsx_vmuh_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3622,7 +4733,13 @@ unsafe fn test_lsx_vmuh_hu() { let b = u16x8::new(14769, 6489, 58866, 5997, 46648, 26325, 42186, 26942); let r = i64x2::new(1572068217944938757, 4366267597274655896); - assert_eq!(r, transmute(lsx_vmuh_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3631,7 +4748,13 @@ unsafe fn test_lsx_vmuh_wu() { let b = u32x4::new(1981234883, 1290836259, 1284878577, 702668871); let r = i64x2::new(4011887256539048298, 960560772888018584); - assert_eq!(r, transmute(lsx_vmuh_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3640,7 +4763,13 @@ unsafe fn test_lsx_vmuh_du() { let b = u64x2::new(14805542397189366587, 10025341254588295994); let r = i64x2::new(-9132083796568587258, 2493261783600858707); - assert_eq!(r, transmute(lsx_vmuh_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3650,7 +4779,7 @@ unsafe fn test_lsx_vsllwil_h_b() { ); let r = i64x2::new(-990777899147527584, 126109727303143360); - assert_eq!(r, transmute(lsx_vsllwil_h_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_h_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3658,7 +4787,7 @@ unsafe fn test_lsx_vsllwil_w_h() { let a = i16x8::new(25135, -4241, 25399, -32451, 5597, -16847, 3192, -14694); let r = i64x2::new(-9326057613926912, -71360503652913664); - assert_eq!(r, transmute(lsx_vsllwil_w_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_w_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3666,7 +4795,7 @@ unsafe fn test_lsx_vsllwil_d_w() { let a = i32x4::new(1472328927, -2106442262, 379100488, -607174188); let r = i64x2::new(6030659284992, -8627987505152); - assert_eq!(r, transmute(lsx_vsllwil_d_w::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_d_w::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3676,7 +4805,10 @@ unsafe fn test_lsx_vsllwil_hu_bu() { ); let r = i64x2::new(6953679870551405312, 6809531147446388736); - assert_eq!(r, transmute(lsx_vsllwil_hu_bu::<7>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_hu_bu::<7>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3684,7 +4816,10 @@ unsafe fn test_lsx_vsllwil_wu_hu() { let a = u16x8::new(370, 47410, 29611, 6206, 10390, 34658, 65264, 5264); let r = i64x2::new(52127846272954880, 6823569169558272); - assert_eq!(r, transmute(lsx_vsllwil_wu_hu::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_wu_hu::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3692,7 +4827,10 @@ unsafe fn test_lsx_vsllwil_du_wu() { let a = u32x4::new(3249798491, 4098547305, 1101510259, 3478509641); let r = i64x2::new(13630642809995264, 17190553355550720); - assert_eq!(r, transmute(lsx_vsllwil_du_wu::<22>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_du_wu::<22>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3701,7 +4839,13 @@ unsafe fn test_lsx_vsran_b_h() { let b = i16x8::new(-12507, -16997, -17826, 5682, -298, -28572, -8117, -13478); let r = i64x2::new(-864943573596831881, 0); - assert_eq!(r, transmute(lsx_vsran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3710,7 +4854,13 @@ unsafe fn test_lsx_vsran_h_w() { let b = i32x4::new(-52337348, -677553123, -58200260, -1473338606); let r = i64x2::new(1267763303694925820, 0); - assert_eq!(r, transmute(lsx_vsran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3719,7 +4869,13 @@ unsafe fn test_lsx_vsran_w_d() { let b = i64x2::new(-8585295495893484131, -2657141976436452013); let r = i64x2::new(-5882350952887806270, 0); - assert_eq!(r, transmute(lsx_vsran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3728,7 +4884,13 @@ unsafe fn test_lsx_vssran_b_h() { let b = i16x8::new(9459, 15241, 22170, 28027, 5348, 14784, 22613, -9469); let r = i64x2::new(9187483431610086528, 0); - assert_eq!(r, transmute(lsx_vssran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3737,7 +4899,13 @@ unsafe fn test_lsx_vssran_h_w() { let b = i32x4::new(2070726003, -944816867, -160621862, -1222036466); let r = i64x2::new(-5219109151313101350, 0); - assert_eq!(r, transmute(lsx_vssran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3746,7 +4914,13 @@ unsafe fn test_lsx_vssran_w_d() { let b = i64x2::new(-7078666005882550400, -2564990402652718339); let r = i64x2::new(-15032385536, 0); - assert_eq!(r, transmute(lsx_vssran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3755,7 +4929,13 @@ unsafe fn test_lsx_vssran_bu_h() { let b = u16x8::new(2372, 26267, 4722, 47876, 44857, 55242, 45998, 51450); let r = i64x2::new(47227865344, 0); - assert_eq!(r, transmute(lsx_vssran_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3764,7 +4944,13 @@ unsafe fn test_lsx_vssran_hu_w() { let b = u32x4::new(2085279153, 2679576985, 2935643238, 3797496208); let r = i64x2::new(281470684234479, 0); - assert_eq!(r, transmute(lsx_vssran_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3773,7 +4959,13 @@ unsafe fn test_lsx_vssran_wu_d() { let b = u64x2::new(3904652404244024971, 4230656884168675704); let r = i64x2::new(536870912000, 0); - assert_eq!(r, transmute(lsx_vssran_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3782,7 +4974,13 @@ unsafe fn test_lsx_vsrarn_b_h() { let b = i16x8::new(-19071, -903, 11542, -25909, 24111, 14882, -27192, -8283); let r = i64x2::new(7076043428318610384, 0); - assert_eq!(r, transmute(lsx_vsrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3791,7 +4989,13 @@ unsafe fn test_lsx_vsrarn_h_w() { let b = i32x4::new(-1571698573, 1467958613, -1857488008, 424713310); let r = i64x2::new(498163119212, 0); - assert_eq!(r, transmute(lsx_vsrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3800,7 +5004,13 @@ unsafe fn test_lsx_vsrarn_w_d() { let b = i64x2::new(-8645668865455529235, -3129277582817496880); let r = i64x2::new(-8628090759335017621, 0); - assert_eq!(r, transmute(lsx_vsrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3809,7 +5019,13 @@ unsafe fn test_lsx_vssrarn_b_h() { let b = i16x8::new(24298, 2343, 24641, 20910, 3142, -1171, 25850, 15932); let r = i64x2::new(-148338468081139694, 0); - assert_eq!(r, transmute(lsx_vssrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3818,7 +5034,13 @@ unsafe fn test_lsx_vssrarn_h_w() { let b = i32x4::new(1911424854, -931292983, -1710824608, -1179580317); let r = i64x2::new(-9223231301513904204, 0); - assert_eq!(r, transmute(lsx_vssrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3827,7 +5049,13 @@ unsafe fn test_lsx_vssrarn_w_d() { let b = i64x2::new(2843689038926761304, -6830262024912907383); let r = i64x2::new(-9223372034707292161, 0); - assert_eq!(r, transmute(lsx_vssrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3836,7 +5064,13 @@ unsafe fn test_lsx_vssrarn_bu_h() { let b = u16x8::new(60210, 40155, 14296, 25577, 1550, 1674, 5330, 10645); let r = i64x2::new(10999415373897, 0); - assert_eq!(r, transmute(lsx_vssrarn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3845,7 +5079,13 @@ unsafe fn test_lsx_vssrarn_hu_w() { let b = u32x4::new(3570029841, 3229468238, 1070101998, 3159433736); let r = i64x2::new(281474976645120, 0); - assert_eq!(r, transmute(lsx_vssrarn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3854,7 +5094,13 @@ unsafe fn test_lsx_vssrarn_wu_d() { let b = u64x2::new(1112771813772164907, 646071836375127186); let r = i64x2::new(963446, 0); - assert_eq!(r, transmute(lsx_vssrarn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3863,7 +5109,13 @@ unsafe fn test_lsx_vsrln_b_h() { let b = i16x8::new(-11667, 13077, -23656, 5150, -23771, -31329, 20729, 15169); let r = i64x2::new(23363148983015937, 0); - assert_eq!(r, transmute(lsx_vsrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3872,7 +5124,13 @@ unsafe fn test_lsx_vsrln_h_w() { let b = i32x4::new(1775989751, -1602688801, -801213995, -1801759515); let r = i64x2::new(-7033214568759295968, 0); - assert_eq!(r, transmute(lsx_vsrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3881,7 +5139,13 @@ unsafe fn test_lsx_vsrln_w_d() { let b = i64x2::new(-1428152872702150626, 3907864416256094744); let r = i64x2::new(-8718771486483115547, 0); - assert_eq!(r, transmute(lsx_vsrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3890,7 +5154,13 @@ unsafe fn test_lsx_vssrln_bu_h() { let b = u16x8::new(41072, 41125, 44619, 49581, 20733, 905, 47558, 7801); let r = i64x2::new(8862857593125412863, 0); - assert_eq!(r, transmute(lsx_vssrln_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3899,7 +5169,13 @@ unsafe fn test_lsx_vssrln_hu_w() { let b = u32x4::new(1325069171, 1380839173, 3495604120, 2839043866); let r = i64x2::new(16889194387279379, 0); - assert_eq!(r, transmute(lsx_vssrln_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3908,7 +5184,13 @@ unsafe fn test_lsx_vssrln_wu_d() { let b = u64x2::new(3908262745817581251, 17131627096934512209); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vssrln_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3917,7 +5199,13 @@ unsafe fn test_lsx_vsrlrn_b_h() { let b = i16x8::new(22830, -27866, -24616, -9547, 11336, 320, 19908, 7056); let r = i64x2::new(-4888418841542521598, 0); - assert_eq!(r, transmute(lsx_vsrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3926,7 +5214,13 @@ unsafe fn test_lsx_vsrlrn_h_w() { let b = i32x4::new(1387862348, 119424523, 185407104, 1890720739); let r = i64x2::new(2222313691660711041, 0); - assert_eq!(r, transmute(lsx_vsrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3935,7 +5229,13 @@ unsafe fn test_lsx_vsrlrn_w_d() { let b = i64x2::new(-8550351213501194562, 7071641301481388656); let r = i64x2::new(182866822561795, 0); - assert_eq!(r, transmute(lsx_vsrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3944,7 +5244,13 @@ unsafe fn test_lsx_vssrlrn_bu_h() { let b = u16x8::new(51122, 39148, 45511, 57479, 62603, 43668, 5537, 61004); let r = i64x2::new(432344477600776959, 0); - assert_eq!(r, transmute(lsx_vssrlrn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3953,7 +5259,13 @@ unsafe fn test_lsx_vssrlrn_hu_w() { let b = u32x4::new(1618795892, 3678356443, 862445734, 2115250342); let r = i64x2::new(-4293983341, 0); - assert_eq!(r, transmute(lsx_vssrlrn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3962,7 +5274,13 @@ unsafe fn test_lsx_vssrlrn_wu_d() { let b = u64x2::new(13406765083608623828, 7214649593148131096); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vssrlrn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3977,7 +5295,10 @@ unsafe fn test_lsx_vfrstpi_b() { assert_eq!( r, - transmute(lsx_vfrstpi_b::<28>(transmute(a), transmute(b))) + transmute(lsx_vfrstpi_b::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -3987,7 +5308,13 @@ unsafe fn test_lsx_vfrstpi_h() { let b = i16x8::new(9590, -8044, 15088, 4172, 1721, 27581, -19895, -25679); let r = i64x2::new(-4160352588467724069, 5959935604366651239); - assert_eq!(r, transmute(lsx_vfrstpi_h::<1>(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfrstpi_h::<1>( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4005,7 +5332,11 @@ unsafe fn test_lsx_vfrstp_b() { assert_eq!( r, - transmute(lsx_vfrstp_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfrstp_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4018,7 +5349,11 @@ unsafe fn test_lsx_vfrstp_h() { assert_eq!( r, - transmute(lsx_vfrstp_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfrstp_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4030,7 +5365,10 @@ unsafe fn test_lsx_vshuf4i_d() { assert_eq!( r, - transmute(lsx_vshuf4i_d::<153>(transmute(a), transmute(b))) + transmute(lsx_vshuf4i_d::<153>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4041,7 +5379,7 @@ unsafe fn test_lsx_vbsrl_v() { ); let r = i64x2::new(4570595419764160432, 56); - assert_eq!(r, transmute(lsx_vbsrl_v::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbsrl_v::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4051,7 +5389,7 @@ unsafe fn test_lsx_vbsll_v() { ); let r = i64x2::new(0, -1801439850948198400); - assert_eq!(r, transmute(lsx_vbsll_v::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbsll_v::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4066,7 +5404,10 @@ unsafe fn test_lsx_vextrins_b() { assert_eq!( r, - transmute(lsx_vextrins_b::<21>(transmute(a), transmute(b))) + transmute(lsx_vextrins_b::<21>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4078,7 +5419,10 @@ unsafe fn test_lsx_vextrins_h() { assert_eq!( r, - transmute(lsx_vextrins_h::<33>(transmute(a), transmute(b))) + transmute(lsx_vextrins_h::<33>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4090,7 +5434,10 @@ unsafe fn test_lsx_vextrins_w() { assert_eq!( r, - transmute(lsx_vextrins_w::<57>(transmute(a), transmute(b))) + transmute(lsx_vextrins_w::<57>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4102,7 +5449,10 @@ unsafe fn test_lsx_vextrins_d() { assert_eq!( r, - transmute(lsx_vextrins_d::<62>(transmute(a), transmute(b))) + transmute(lsx_vextrins_d::<62>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4113,7 +5463,7 @@ unsafe fn test_lsx_vmskltz_b() { ); let r = i64x2::new(40038, 0); - assert_eq!(r, transmute(lsx_vmskltz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4121,7 +5471,7 @@ unsafe fn test_lsx_vmskltz_h() { let a = i16x8::new(16730, 29121, -23447, -8647, -22303, 21817, 30964, -27069); let r = i64x2::new(156, 0); - assert_eq!(r, transmute(lsx_vmskltz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4129,7 +5479,7 @@ unsafe fn test_lsx_vmskltz_w() { let a = i32x4::new(-657282776, -1247210048, 162595942, 949871015); let r = i64x2::new(3, 0); - assert_eq!(r, transmute(lsx_vmskltz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4137,7 +5487,7 @@ unsafe fn test_lsx_vmskltz_d() { let a = i64x2::new(7728638770319849738, 4250984610820351699); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vmskltz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4150,7 +5500,13 @@ unsafe fn test_lsx_vsigncov_b() { ); let r = i64x2::new(-9074694153930972472, 1986788453588057010); - assert_eq!(r, transmute(lsx_vsigncov_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4159,7 +5515,13 @@ unsafe fn test_lsx_vsigncov_h() { let b = i16x8::new(27367, 4727, -2962, 14937, 26207, -19075, -26630, 10708); let r = i64x2::new(-4204122973533661927, -3013866947575178847); - assert_eq!(r, transmute(lsx_vsigncov_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4168,7 +5530,13 @@ unsafe fn test_lsx_vsigncov_w() { let b = i32x4::new(-1719915889, 290419288, 202835952, -1715336967); let r = i64x2::new(-1247341342367689359, -7367316170792699888); - assert_eq!(r, transmute(lsx_vsigncov_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4177,7 +5545,13 @@ unsafe fn test_lsx_vsigncov_d() { let b = i64x2::new(-7146260093067324952, -4263419240070336957); let r = i64x2::new(-7146260093067324952, 4263419240070336957); - assert_eq!(r, transmute(lsx_vsigncov_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4189,7 +5563,11 @@ unsafe fn test_lsx_vfmadd_s() { assert_eq!( r, - transmute(lsx_vfmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4202,7 +5580,11 @@ unsafe fn test_lsx_vfmadd_d() { assert_eq!( r, - transmute(lsx_vfmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4215,7 +5597,11 @@ unsafe fn test_lsx_vfmsub_s() { assert_eq!( r, - transmute(lsx_vfmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4228,7 +5614,11 @@ unsafe fn test_lsx_vfmsub_d() { assert_eq!( r, - transmute(lsx_vfmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4241,7 +5631,11 @@ unsafe fn test_lsx_vfnmadd_s() { assert_eq!( r, - transmute(lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4254,7 +5648,11 @@ unsafe fn test_lsx_vfnmadd_d() { assert_eq!( r, - transmute(lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4267,7 +5665,11 @@ unsafe fn test_lsx_vfnmsub_s() { assert_eq!( r, - transmute(lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4280,7 +5682,11 @@ unsafe fn test_lsx_vfnmsub_d() { assert_eq!( r, - transmute(lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4289,7 +5695,7 @@ unsafe fn test_lsx_vftintrne_w_s() { let a = u32x4::new(1031214064, 1059673230, 1042813024, 1053602874); let r = i64x2::new(4294967296, 0); - assert_eq!(r, transmute(lsx_vftintrne_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrne_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4297,7 +5703,7 @@ unsafe fn test_lsx_vftintrne_l_d() { let a = u64x2::new(4606989588359571497, 4604713245380178790); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrne_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrne_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4305,7 +5711,7 @@ unsafe fn test_lsx_vftintrp_w_s() { let a = u32x4::new(1061716225, 1050491008, 1064711040, 1065018777); let r = i64x2::new(4294967297, 4294967297); - assert_eq!(r, transmute(lsx_vftintrp_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrp_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4313,7 +5719,7 @@ unsafe fn test_lsx_vftintrp_l_d() { let a = u64x2::new(4587516915944025472, 4601504548481216392); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrp_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrp_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4321,7 +5727,7 @@ unsafe fn test_lsx_vftintrm_w_s() { let a = u32x4::new(1045772456, 1065200707, 1061587478, 1035467272); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrm_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4329,7 +5735,7 @@ unsafe fn test_lsx_vftintrm_l_d() { let a = u64x2::new(4597123259408216804, 4594399417822716772); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrm_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4338,7 +5744,13 @@ unsafe fn test_lsx_vftint_w_d() { let b = u64x2::new(4606905060326467647, 4606985586417166381); let r = i64x2::new(4294967297, 0); - assert_eq!(r, transmute(lsx_vftint_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftint_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4347,7 +5759,13 @@ unsafe fn test_lsx_vffint_s_l() { let b = i64x2::new(5814449889729512723, -111756032377486319); let r = i64x2::new(-2610252963668467161, 6669016150524087533); - assert_eq!(r, transmute(lsx_vffint_s_l(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vffint_s_l( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4356,7 +5774,13 @@ unsafe fn test_lsx_vftintrz_w_d() { let b = u64x2::new(4599106720144900270, 4600531579473237336); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrz_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4365,7 +5789,13 @@ unsafe fn test_lsx_vftintrp_w_d() { let b = u64x2::new(4606104970322966899, 4595679410565085836); let r = i64x2::new(4294967297, 4294967297); - assert_eq!(r, transmute(lsx_vftintrp_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrp_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4374,7 +5804,13 @@ unsafe fn test_lsx_vftintrm_w_d() { let b = u64x2::new(4606733822200032543, 4589510164179968984); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrm_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4383,7 +5819,13 @@ unsafe fn test_lsx_vftintrne_w_d() { let b = u64x2::new(4599197176714081204, 4605745859931721980); let r = i64x2::new(4294967296, 0); - assert_eq!(r, transmute(lsx_vftintrne_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrne_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4391,7 +5833,7 @@ unsafe fn test_lsx_vftintl_l_s() { let a = u32x4::new(1058856635, 1060563398, 1061422616, 1056124918); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4399,7 +5841,7 @@ unsafe fn test_lsx_vftinth_l_s() { let a = u32x4::new(1045383680, 1040752748, 1061879518, 1054801708); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftinth_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftinth_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4407,7 +5849,7 @@ unsafe fn test_lsx_vffinth_d_w() { let a = i32x4::new(517100418, -188510766, 949226647, -87467194); let r = i64x2::new(4741245898611228672, -4497729803343888384); - assert_eq!(r, transmute(lsx_vffinth_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffinth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4415,7 +5857,7 @@ unsafe fn test_lsx_vffintl_d_w() { let a = i32x4::new(1273684401, -2137528906, -2109294912, -1646387998); let r = i64x2::new(4743129027571613696, -4476619782820462592); - assert_eq!(r, transmute(lsx_vffintl_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffintl_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4423,7 +5865,7 @@ unsafe fn test_lsx_vftintrzl_l_s() { let a = u32x4::new(1031186688, 987838976, 1034565688, 1061017371); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrzl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrzl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4431,7 +5873,7 @@ unsafe fn test_lsx_vftintrzh_l_s() { let a = u32x4::new(1049433828, 1048953580, 1060964637, 1059899586); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrzh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrzh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4439,7 +5881,7 @@ unsafe fn test_lsx_vftintrpl_l_s() { let a = u32x4::new(1061834803, 1064858941, 1060475110, 1063896216); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrpl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrpl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4447,7 +5889,7 @@ unsafe fn test_lsx_vftintrph_l_s() { let a = u32x4::new(1059691939, 1065187151, 1059017027, 1061117394); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrph_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrph_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4455,7 +5897,7 @@ unsafe fn test_lsx_vftintrml_l_s() { let a = u32x4::new(1062985651, 1065211455, 1056421466, 1057373572); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrml_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrml_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4463,7 +5905,7 @@ unsafe fn test_lsx_vftintrmh_l_s() { let a = u32x4::new(1050224290, 1063763666, 1057677270, 1063622234); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrmh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrmh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4471,7 +5913,7 @@ unsafe fn test_lsx_vftintrnel_l_s() { let a = u32x4::new(1060174609, 1050974638, 1047193308, 1062040876); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftintrnel_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrnel_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4479,7 +5921,7 @@ unsafe fn test_lsx_vftintrneh_l_s() { let a = u32x4::new(1055675382, 1036879184, 1064176794, 1063791852); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrneh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrneh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4487,7 +5929,7 @@ unsafe fn test_lsx_vfrintrne_s() { let a = u32x4::new(1054667842, 1061395025, 1062986478, 1062529334); let r = i64x2::new(4575657221408423936, 4575657222473777152); - assert_eq!(r, transmute(lsx_vfrintrne_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrne_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4495,7 +5937,7 @@ unsafe fn test_lsx_vfrintrne_d() { let a = u64x2::new(4603260356641870565, 4601614335120512898); let r = i64x2::new(4607182418800017408, 0); - assert_eq!(r, transmute(lsx_vfrintrne_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrne_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4503,7 +5945,7 @@ unsafe fn test_lsx_vfrintrz_s() { let a = u32x4::new(1063039577, 1033416832, 1052369306, 1057885024); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrz_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrz_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4511,7 +5953,7 @@ unsafe fn test_lsx_vfrintrz_d() { let a = u64x2::new(4601515428088814484, 4604735152905786794); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4519,7 +5961,7 @@ unsafe fn test_lsx_vfrintrp_s() { let a = u32x4::new(1061968959, 1056597596, 1064869916, 1058742360); let r = i64x2::new(4575657222473777152, 4575657222473777152); - assert_eq!(r, transmute(lsx_vfrintrp_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrp_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4527,7 +5969,7 @@ unsafe fn test_lsx_vfrintrp_d() { let a = u64x2::new(4603531792479663401, 4587997630530425392); let r = i64x2::new(4607182418800017408, 4607182418800017408); - assert_eq!(r, transmute(lsx_vfrintrp_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrp_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4535,7 +5977,7 @@ unsafe fn test_lsx_vfrintrm_s() { let a = u32x4::new(1058024441, 1044087184, 1059777964, 1050835426); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrm_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrm_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4543,7 +5985,7 @@ unsafe fn test_lsx_vfrintrm_d() { let a = u64x2::new(4589388034824743512, 4606800774570289382); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrm_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrm_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4556,7 +5998,7 @@ unsafe fn test_lsx_vstelm_b() { ]; let r = i64x2::new(2624488095427530938, -2742340989646681128); - lsx_vstelm_b::<0, 0>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_b::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4568,7 +6010,7 @@ unsafe fn test_lsx_vstelm_h() { ]; let r = i64x2::new(-5777879910580360821, -8010388107109560809); - lsx_vstelm_h::<0, 1>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_h::<0, 1>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4580,7 +6022,7 @@ unsafe fn test_lsx_vstelm_w() { ]; let r = i64x2::new(-7107014201697162202, -4954294907532227136); - lsx_vstelm_w::<0, 3>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_w::<0, 3>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4592,7 +6034,7 @@ unsafe fn test_lsx_vstelm_d() { ]; let r = i64x2::new(2628828971609511929, -1577551211298588582); - lsx_vstelm_d::<0, 0>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_d::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4602,7 +6044,13 @@ unsafe fn test_lsx_vaddwev_d_w() { let b = i32x4::new(-2105551735, -1478351177, 1027048582, -607110700); let r = i64x2::new(-3995454036, 2115628395); - assert_eq!(r, transmute(lsx_vaddwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4611,7 +6059,13 @@ unsafe fn test_lsx_vaddwev_w_h() { let b = i16x8::new(-17479, -32614, 24343, 25426, -14077, -12419, 10115, 23013); let r = i64x2::new(57531086920254, -11304353922851); - assert_eq!(r, transmute(lsx_vaddwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4624,7 +6078,13 @@ unsafe fn test_lsx_vaddwev_h_b() { ); let r = i64x2::new(-6191796646052051, 32369798417022969); - assert_eq!(r, transmute(lsx_vaddwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4633,7 +6093,13 @@ unsafe fn test_lsx_vaddwod_d_w() { let b = i32x4::new(420515981, 473447119, 1471756335, 1044924117); let r = i64x2::new(126219465, 3020814787); - assert_eq!(r, transmute(lsx_vaddwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4642,7 +6108,13 @@ unsafe fn test_lsx_vaddwod_w_h() { let b = i16x8::new(-26581, -22301, 18214, -3616, -24489, 12150, -10765, -24232); let r = i64x2::new(-151719719748481, -112154480997307); - assert_eq!(r, transmute(lsx_vaddwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4655,7 +6127,13 @@ unsafe fn test_lsx_vaddwod_h_b() { ); let r = i64x2::new(-18014780768845678, 14636475441676413); - assert_eq!(r, transmute(lsx_vaddwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4664,7 +6142,13 @@ unsafe fn test_lsx_vaddwev_d_wu() { let b = u32x4::new(1482213353, 1001198416, 3345983326, 2244256337); let r = i64x2::new(4022160583, 4539965521); - assert_eq!(r, transmute(lsx_vaddwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4673,7 +6157,13 @@ unsafe fn test_lsx_vaddwev_w_hu() { let b = u16x8::new(28483, 24704, 9817, 62062, 47674, 8032, 29897, 62737); let r = i64x2::new(176725019407839, 226649719257774); - assert_eq!(r, transmute(lsx_vaddwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4686,7 +6176,13 @@ unsafe fn test_lsx_vaddwev_h_bu() { ); let r = i64x2::new(85006057160704351, 47850943627526421); - assert_eq!(r, transmute(lsx_vaddwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4695,7 +6191,13 @@ unsafe fn test_lsx_vaddwod_d_wu() { let b = u32x4::new(2782520439, 2496077290, 2678772394, 196273109); let r = i64x2::new(4147231270, 2289089430); - assert_eq!(r, transmute(lsx_vaddwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4704,7 +6206,13 @@ unsafe fn test_lsx_vaddwod_w_hu() { let b = u16x8::new(20353, 34039, 21222, 4948, 58293, 4766, 51360, 37497); let r = i64x2::new(82519206727777, 206875689791292); - assert_eq!(r, transmute(lsx_vaddwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4717,7 +6225,13 @@ unsafe fn test_lsx_vaddwod_h_bu() { ); let r = i64x2::new(73466429242409013, 32932877227196635); - assert_eq!(r, transmute(lsx_vaddwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4726,7 +6240,13 @@ unsafe fn test_lsx_vaddwev_d_wu_w() { let b = i32x4::new(-1308530150, 1427930358, 1723198474, 1987356336); let r = i64x2::new(2478528121, 3014708115); - assert_eq!(r, transmute(lsx_vaddwev_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4735,7 +6255,13 @@ unsafe fn test_lsx_vaddwev_w_hu_h() { let b = i16x8::new(-11621, -6593, 7431, -1189, -12361, -15174, 16182, -32434); let r = i64x2::new(64158221463769, 194716637325930); - assert_eq!(r, transmute(lsx_vaddwev_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4748,7 +6274,13 @@ unsafe fn test_lsx_vaddwev_h_bu_b() { ); let r = i64x2::new(71776235037065355, -7880749580746636); - assert_eq!(r, transmute(lsx_vaddwev_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4757,7 +6289,13 @@ unsafe fn test_lsx_vaddwod_d_wu_w() { let b = i32x4::new(-1646368557, 586112311, 376247963, 1048800083); let r = i64x2::new(3497092601, 3306080422); - assert_eq!(r, transmute(lsx_vaddwod_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4766,7 +6304,13 @@ unsafe fn test_lsx_vaddwod_w_hu_h() { let b = i16x8::new(31700, 22725, 14068, -14860, -28839, -14513, -1195, 27082); let r = i64x2::new(-10273561712908, 369560461022726); - assert_eq!(r, transmute(lsx_vaddwod_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4779,7 +6323,13 @@ unsafe fn test_lsx_vaddwod_h_bu_b() { ); let r = i64x2::new(49259327819481212, 19140654913421439); - assert_eq!(r, transmute(lsx_vaddwod_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4788,7 +6338,13 @@ unsafe fn test_lsx_vsubwev_d_w() { let b = i32x4::new(-2090701374, 629564229, -1170676885, 1069800209); let r = i64x2::new(4070621277, 63900397); - assert_eq!(r, transmute(lsx_vsubwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4797,7 +6353,13 @@ unsafe fn test_lsx_vsubwev_w_h() { let b = i16x8::new(-23957, 9416, -29569, -13210, 5333, 8420, 18648, -24201); let r = i64x2::new(228187317494294, -105188044063209); - assert_eq!(r, transmute(lsx_vsubwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4810,7 +6372,13 @@ unsafe fn test_lsx_vsubwev_h_b() { ); let r = i64x2::new(-41939247539617653, -14355228098887689); - assert_eq!(r, transmute(lsx_vsubwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4819,7 +6387,13 @@ unsafe fn test_lsx_vsubwod_d_w() { let b = i32x4::new(1436617964, -45524609, 502994793, -2039550077); let r = i64x2::new(-1037882987, 3497647797); - assert_eq!(r, transmute(lsx_vsubwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4828,7 +6402,13 @@ unsafe fn test_lsx_vsubwod_w_h() { let b = i16x8::new(-1276, 12669, 24115, 19617, -26739, 1910, -757, 23994); let r = i64x2::new(-158286724709540, -182411556002309); - assert_eq!(r, transmute(lsx_vsubwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4841,7 +6421,13 @@ unsafe fn test_lsx_vsubwod_h_b() { ); let r = i64x2::new(23925540523802608, 562958549909362); - assert_eq!(r, transmute(lsx_vsubwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4850,7 +6436,13 @@ unsafe fn test_lsx_vsubwev_d_wu() { let b = u32x4::new(1691253880, 1939268473, 1629937431, 2921768539); let r = i64x2::new(974418830, 1402878171); - assert_eq!(r, transmute(lsx_vsubwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4859,7 +6451,13 @@ unsafe fn test_lsx_vsubwev_w_hu() { let b = u16x8::new(15957, 42770, 43138, 30319, 50823, 18089, 64120, 18054); let r = i64x2::new(-41807211666923, -194858371266981); - assert_eq!(r, transmute(lsx_vsubwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4872,7 +6470,13 @@ unsafe fn test_lsx_vsubwev_h_bu() { ); let r = i64x2::new(-1407181617889293, 47851128289689387); - assert_eq!(r, transmute(lsx_vsubwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4881,7 +6485,13 @@ unsafe fn test_lsx_vsubwod_d_wu() { let b = u32x4::new(103354715, 19070238, 1662532733, 3761231766); let r = i64x2::new(3487028338, -1512426824); - assert_eq!(r, transmute(lsx_vsubwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4890,7 +6500,13 @@ unsafe fn test_lsx_vsubwod_w_hu() { let b = u16x8::new(21739, 45406, 21733, 63910, 6659, 16020, 1211, 637); let r = i64x2::new(-93999654264447, 232211701825972); - assert_eq!(r, transmute(lsx_vsubwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4903,7 +6519,13 @@ unsafe fn test_lsx_vsubwod_h_bu() { ); let r = i64x2::new(-14355150803107815, 14636020195655765); - assert_eq!(r, transmute(lsx_vsubwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4912,7 +6534,13 @@ unsafe fn test_lsx_vaddwev_q_d() { let b = i64x2::new(6738886902337351868, -5985538541381931477); let r = i64x2::new(5606769623790009521, 0); - assert_eq!(r, transmute(lsx_vaddwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4921,7 +6549,13 @@ unsafe fn test_lsx_vaddwod_q_d() { let b = i64x2::new(-1244049724346527963, -3275029038845457041); let r = i64x2::new(-4417812606654001824, -1); - assert_eq!(r, transmute(lsx_vaddwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4930,7 +6564,13 @@ unsafe fn test_lsx_vaddwev_q_du() { let b = u64x2::new(6745766838534849346, 15041258018068294402); let r = i64x2::new(5074243625310689089, 1); - assert_eq!(r, transmute(lsx_vaddwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4939,7 +6579,13 @@ unsafe fn test_lsx_vaddwod_q_du() { let b = u64x2::new(13496765248439164553, 4640846570780442359); let r = i64x2::new(-2107214925415534967, 0); - assert_eq!(r, transmute(lsx_vaddwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4948,7 +6594,13 @@ unsafe fn test_lsx_vsubwev_q_d() { let b = i64x2::new(8029026411722387723, -2105201823388787841); let r = i64x2::new(480269655671735476, 0); - assert_eq!(r, transmute(lsx_vsubwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4957,7 +6609,13 @@ unsafe fn test_lsx_vsubwod_q_d() { let b = i64x2::new(5758437127240728961, 2933507971643343184); let r = i64x2::new(-8752278892998837291, -1); - assert_eq!(r, transmute(lsx_vsubwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4966,7 +6624,13 @@ unsafe fn test_lsx_vsubwev_q_du() { let b = u64x2::new(1574118313456291324, 7787456577305510529); let r = i64x2::new(-4672772323591679948, 0); - assert_eq!(r, transmute(lsx_vsubwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4975,7 +6639,13 @@ unsafe fn test_lsx_vsubwod_q_du() { let b = u64x2::new(5627376085113520030, 12775637764770549815); let r = i64x2::new(6257163948134922640, -1); - assert_eq!(r, transmute(lsx_vsubwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4984,7 +6654,13 @@ unsafe fn test_lsx_vaddwev_q_du_d() { let b = i64x2::new(-1159499132550683978, -4257322329662100669); let r = i64x2::new(-8502520416635627524, 0); - assert_eq!(r, transmute(lsx_vaddwev_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4993,7 +6669,13 @@ unsafe fn test_lsx_vaddwod_q_du_d() { let b = i64x2::new(-3902573037873546881, 160140233311333524); let r = i64x2::new(286209858134078253, 0); - assert_eq!(r, transmute(lsx_vaddwod_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5002,7 +6684,13 @@ unsafe fn test_lsx_vmulwev_d_w() { let b = i32x4::new(8741677, -276509855, -1214560052, -1338519080); let r = i64x2::new(11251431313755612, -2205748716678689436); - assert_eq!(r, transmute(lsx_vmulwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5011,7 +6699,13 @@ unsafe fn test_lsx_vmulwev_w_h() { let b = i16x8::new(30661, -20472, 1422, -16868, 4256, 9713, -27765, -7287); let r = i64x2::new(-178740441125036345, 469367082934888736); - assert_eq!(r, transmute(lsx_vmulwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5024,7 +6718,13 @@ unsafe fn test_lsx_vmulwev_h_b() { ); let r = i64x2::new(38855607073696482, 823864071118590255); - assert_eq!(r, transmute(lsx_vmulwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5033,7 +6733,13 @@ unsafe fn test_lsx_vmulwod_d_w() { let b = i32x4::new(63312847, -1377579771, -2054819244, -1416520586); let r = i64x2::new(1549708311038418702, 2478205834807109862); - assert_eq!(r, transmute(lsx_vmulwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5042,7 +6748,13 @@ unsafe fn test_lsx_vmulwod_w_h() { let b = i16x8::new(23748, 11912, 4946, -23048, 22372, 24702, -24875, -27771); let r = i64x2::new(3222038736804363232, 360450672278114574); - assert_eq!(r, transmute(lsx_vmulwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5055,7 +6767,13 @@ unsafe fn test_lsx_vmulwod_h_b() { ); let r = i64x2::new(-351280556043402912, 951366355207905332); - assert_eq!(r, transmute(lsx_vmulwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5064,7 +6782,13 @@ unsafe fn test_lsx_vmulwev_d_wu() { let b = u32x4::new(1769900227, 2256955703, 2342391995, 2407560006); let r = i64x2::new(3651844205567962921, 7772247680216328210); - assert_eq!(r, transmute(lsx_vmulwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5073,7 +6797,13 @@ unsafe fn test_lsx_vmulwev_w_hu() { let b = u16x8::new(20499, 45056, 20580, 12771, 53914, 60742, 45402, 40547); let r = i64x2::new(4070644332601545987, 8033224333626513014); - assert_eq!(r, transmute(lsx_vmulwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5086,7 +6816,13 @@ unsafe fn test_lsx_vmulwev_h_bu() { ); let r = i64x2::new(271910110892810861, 1947809607093856504); - assert_eq!(r, transmute(lsx_vmulwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5095,7 +6831,13 @@ unsafe fn test_lsx_vmulwod_d_wu() { let b = u32x4::new(3750239707, 1422851626, 1277923597, 1377279439); let r = i64x2::new(2821622727533716246, 3005960862740149995); - assert_eq!(r, transmute(lsx_vmulwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5104,7 +6846,13 @@ unsafe fn test_lsx_vmulwod_w_hu() { let b = u16x8::new(38950, 5357, 36233, 17707, 61077, 61518, 5789, 13317); let r = i64x2::new(2460325445475503463, 3109522059894091248); - assert_eq!(r, transmute(lsx_vmulwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5117,7 +6865,13 @@ unsafe fn test_lsx_vmulwod_h_bu() { ); let r = i64x2::new(7364114643151226902, 6612146073643521312); - assert_eq!(r, transmute(lsx_vmulwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5126,7 +6880,13 @@ unsafe fn test_lsx_vmulwev_d_wu_w() { let b = i32x4::new(1254729285, 1938836163, -1902169358, -257980375); let r = i64x2::new(2295762833698990875, -6669027432954818262); - assert_eq!(r, transmute(lsx_vmulwev_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5135,7 +6895,13 @@ unsafe fn test_lsx_vmulwev_w_hu_h() { let b = i16x8::new(-30477, -10049, 16428, -30668, 21000, 24834, -3219, -9555); let r = i64x2::new(3369342936690107644, -701630285043265176); - assert_eq!(r, transmute(lsx_vmulwev_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5148,7 +6914,13 @@ unsafe fn test_lsx_vmulwev_h_bu_b() { ); let r = i64x2::new(-1134643098233554544, -1885853116779133038); - assert_eq!(r, transmute(lsx_vmulwev_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5157,7 +6929,13 @@ unsafe fn test_lsx_vmulwod_d_wu_w() { let b = i32x4::new(1204047391, -1970001586, 608763444, -2082771896); let r = i64x2::new(-5967343163181744876, -3673352984882804288); - assert_eq!(r, transmute(lsx_vmulwod_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5166,7 +6944,13 @@ unsafe fn test_lsx_vmulwod_w_hu_h() { let b = i16x8::new(-3735, -12972, -4920, 7170, 11577, 9785, 4896, -537); let r = i64x2::new(1024392868267999948, -48053790042385565); - assert_eq!(r, transmute(lsx_vmulwod_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5179,7 +6963,13 @@ unsafe fn test_lsx_vmulwod_h_bu_b() { ); let r = i64x2::new(1905300476090387090, -3940634277386171400); - assert_eq!(r, transmute(lsx_vmulwod_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5188,7 +6978,13 @@ unsafe fn test_lsx_vmulwev_q_d() { let b = i64x2::new(7023560313675997328, 4368639658790376608); let r = i64x2::new(-1409563343912029488, -2779799970834089134); - assert_eq!(r, transmute(lsx_vmulwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5197,7 +6993,13 @@ unsafe fn test_lsx_vmulwod_q_d() { let b = i64x2::new(1734538850547798281, 6505001633960390309); let r = i64x2::new(655114704133495137, -1013080750363369114); - assert_eq!(r, transmute(lsx_vmulwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5206,7 +7008,13 @@ unsafe fn test_lsx_vmulwev_q_du() { let b = u64x2::new(15048173707940873365, 13594773395779002998); let r = i64x2::new(-4049323972691826149, 6179334620527225413); - assert_eq!(r, transmute(lsx_vmulwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5215,7 +7023,13 @@ unsafe fn test_lsx_vmulwod_q_du() { let b = u64x2::new(16172423495582959833, 11676106279348566952); let r = i64x2::new(-66293137947075128, 3694303051148166412); - assert_eq!(r, transmute(lsx_vmulwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5224,7 +7038,13 @@ unsafe fn test_lsx_vmulwev_q_du_d() { let b = i64x2::new(-7071166739782294817, 8496829998090419991); let r = i64x2::new(5234431817964974175, -5931105679667820544); - assert_eq!(r, transmute(lsx_vmulwev_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5233,7 +7053,13 @@ unsafe fn test_lsx_vmulwod_q_du_d() { let b = i64x2::new(-9085162554263782091, -3351642387065053502); let r = i64x2::new(-3119502026085414102, -1153233394465180223); - assert_eq!(r, transmute(lsx_vmulwod_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5242,7 +7068,13 @@ unsafe fn test_lsx_vhaddw_q_d() { let b = i64x2::new(9222966760421493517, -8347454331188625422); let r = i64x2::new(6438946365641244151, 0); - assert_eq!(r, transmute(lsx_vhaddw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5251,7 +7083,13 @@ unsafe fn test_lsx_vhaddw_qu_du() { let b = u64x2::new(2141387370256045519, 12417156199252644485); let r = i64x2::new(5083013417816990364, 0); - assert_eq!(r, transmute(lsx_vhaddw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5260,7 +7098,13 @@ unsafe fn test_lsx_vhsubw_q_d() { let b = i64x2::new(-3245503809142406078, 8660213762027125085); let r = i64x2::new(817818278178354941, 0); - assert_eq!(r, transmute(lsx_vhsubw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5269,7 +7113,13 @@ unsafe fn test_lsx_vhsubw_qu_du() { let b = u64x2::new(3098179646743711521, 11374525358855478565); let r = i64x2::new(-8990580109137044958, 0); - assert_eq!(r, transmute(lsx_vhsubw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5281,7 +7131,11 @@ unsafe fn test_lsx_vmaddwev_d_w() { assert_eq!( r, - transmute(lsx_vmaddwev_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5294,7 +7148,11 @@ unsafe fn test_lsx_vmaddwev_w_h() { assert_eq!( r, - transmute(lsx_vmaddwev_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5311,7 +7169,11 @@ unsafe fn test_lsx_vmaddwev_h_b() { assert_eq!( r, - transmute(lsx_vmaddwev_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5324,7 +7186,11 @@ unsafe fn test_lsx_vmaddwev_d_wu() { assert_eq!( r, - transmute(lsx_vmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5337,7 +7203,11 @@ unsafe fn test_lsx_vmaddwev_w_hu() { assert_eq!( r, - transmute(lsx_vmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5354,7 +7224,11 @@ unsafe fn test_lsx_vmaddwev_h_bu() { assert_eq!( r, - transmute(lsx_vmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5367,7 +7241,11 @@ unsafe fn test_lsx_vmaddwod_d_w() { assert_eq!( r, - transmute(lsx_vmaddwod_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5380,7 +7258,11 @@ unsafe fn test_lsx_vmaddwod_w_h() { assert_eq!( r, - transmute(lsx_vmaddwod_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5397,7 +7279,11 @@ unsafe fn test_lsx_vmaddwod_h_b() { assert_eq!( r, - transmute(lsx_vmaddwod_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5410,7 +7296,11 @@ unsafe fn test_lsx_vmaddwod_d_wu() { assert_eq!( r, - transmute(lsx_vmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5423,7 +7313,11 @@ unsafe fn test_lsx_vmaddwod_w_hu() { assert_eq!( r, - transmute(lsx_vmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5440,7 +7334,11 @@ unsafe fn test_lsx_vmaddwod_h_bu() { assert_eq!( r, - transmute(lsx_vmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5454,9 +7352,9 @@ unsafe fn test_lsx_vmaddwev_d_wu_w() { assert_eq!( r, transmute(lsx_vmaddwev_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5471,9 +7369,9 @@ unsafe fn test_lsx_vmaddwev_w_hu_h() { assert_eq!( r, transmute(lsx_vmaddwev_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5492,9 +7390,9 @@ unsafe fn test_lsx_vmaddwev_h_bu_b() { assert_eq!( r, transmute(lsx_vmaddwev_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5509,9 +7407,9 @@ unsafe fn test_lsx_vmaddwod_d_wu_w() { assert_eq!( r, transmute(lsx_vmaddwod_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5526,9 +7424,9 @@ unsafe fn test_lsx_vmaddwod_w_hu_h() { assert_eq!( r, transmute(lsx_vmaddwod_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5547,9 +7445,9 @@ unsafe fn test_lsx_vmaddwod_h_bu_b() { assert_eq!( r, transmute(lsx_vmaddwod_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5563,7 +7461,11 @@ unsafe fn test_lsx_vmaddwev_q_d() { assert_eq!( r, - transmute(lsx_vmaddwev_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5576,7 +7478,11 @@ unsafe fn test_lsx_vmaddwod_q_d() { assert_eq!( r, - transmute(lsx_vmaddwod_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5589,7 +7495,11 @@ unsafe fn test_lsx_vmaddwev_q_du() { assert_eq!( r, - transmute(lsx_vmaddwev_q_du(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5602,7 +7512,11 @@ unsafe fn test_lsx_vmaddwod_q_du() { assert_eq!( r, - transmute(lsx_vmaddwod_q_du(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5616,9 +7530,9 @@ unsafe fn test_lsx_vmaddwev_q_du_d() { assert_eq!( r, transmute(lsx_vmaddwev_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5633,9 +7547,9 @@ unsafe fn test_lsx_vmaddwod_q_du_d() { assert_eq!( r, transmute(lsx_vmaddwod_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5650,7 +7564,13 @@ unsafe fn test_lsx_vrotr_b() { ); let r = i64x2::new(2841128540244802403, -8694309599374351908); - assert_eq!(r, transmute(lsx_vrotr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5659,7 +7579,13 @@ unsafe fn test_lsx_vrotr_h() { let b = i16x8::new(-6485, 1418, 8263, -29872, -6491, 3930, -20621, 32531); let r = i64x2::new(2742461657407651598, 3308267577913279393); - assert_eq!(r, transmute(lsx_vrotr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5668,7 +7594,13 @@ unsafe fn test_lsx_vrotr_w() { let b = i32x4::new(1956224189, -1858012941, -1889446514, -2130978943); let r = i64x2::new(6458469860191573231, -8548346292466177157); - assert_eq!(r, transmute(lsx_vrotr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5677,7 +7609,13 @@ unsafe fn test_lsx_vrotr_d() { let b = i64x2::new(4553458262651691654, -5062393334123159235); let r = i64x2::new(-3594618648537251961, 7897385285240526033); - assert_eq!(r, transmute(lsx_vrotr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5686,7 +7624,10 @@ unsafe fn test_lsx_vadd_q() { let b = i64x2::new(114135477458514099, 3481307531297359399); let r = i64x2::new(2537705118259771652, 4159381110985057604); - assert_eq!(r, transmute(lsx_vadd_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_q(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -5695,7 +7636,10 @@ unsafe fn test_lsx_vsub_q() { let b = i64x2::new(-8526086848853095438, -1323481969747305966); let r = i64x2::new(-2027679534337857341, -1789445478164204527); - assert_eq!(r, transmute(lsx_vsub_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_q(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -5745,7 +7689,7 @@ unsafe fn test_lsx_vmskgez_b() { ); let r = i64x2::new(24930, 0); - assert_eq!(r, transmute(lsx_vmskgez_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskgez_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5755,7 +7699,7 @@ unsafe fn test_lsx_vmsknz_b() { ); let r = i64x2::new(65535, 0); - assert_eq!(r, transmute(lsx_vmsknz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmsknz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5765,7 +7709,7 @@ unsafe fn test_lsx_vexth_h_b() { ); let r = i64x2::new(-3377613816397739, 32088276197572514); - assert_eq!(r, transmute(lsx_vexth_h_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5773,7 +7717,7 @@ unsafe fn test_lsx_vexth_w_h() { let a = i16x8::new(14576, -26514, 14165, -15781, 10106, 1864, 23348, 30478); let r = i64x2::new(8005819049850, 130902013270836); - assert_eq!(r, transmute(lsx_vexth_w_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5781,7 +7725,7 @@ unsafe fn test_lsx_vexth_d_w() { let a = i32x4::new(863783254, 799653326, -1122161877, -652869192); let r = i64x2::new(-1122161877, -652869192); - assert_eq!(r, transmute(lsx_vexth_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5789,7 +7733,7 @@ unsafe fn test_lsx_vexth_q_d() { let a = i64x2::new(2924262436748867523, 1959694872821330818); let r = i64x2::new(1959694872821330818, 0); - assert_eq!(r, transmute(lsx_vexth_q_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5799,7 +7743,7 @@ unsafe fn test_lsx_vexth_hu_bu() { ); let r = i64x2::new(61080980486815914, 60235902725652628); - assert_eq!(r, transmute(lsx_vexth_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5807,7 +7751,7 @@ unsafe fn test_lsx_vexth_wu_hu() { let a = u16x8::new(58875, 18924, 17611, 30197, 33869, 53931, 4693, 53025); let r = i64x2::new(231631881274445, 227740640875093); - assert_eq!(r, transmute(lsx_vexth_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5815,7 +7759,7 @@ unsafe fn test_lsx_vexth_du_wu() { let a = u32x4::new(3499742961, 2840979237, 2082263829, 1096292547); let r = i64x2::new(2082263829, 1096292547); - assert_eq!(r, transmute(lsx_vexth_du_wu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5823,7 +7767,7 @@ unsafe fn test_lsx_vexth_qu_du() { let a = u64x2::new(14170556367894986991, 14238702840099699193); let r = i64x2::new(-4208041233609852423, 0); - assert_eq!(r, transmute(lsx_vexth_qu_du(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5833,7 +7777,7 @@ unsafe fn test_lsx_vrotri_b() { ); let r = i64x2::new(-2919654548887155519, -96080239582005205); - assert_eq!(r, transmute(lsx_vrotri_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5841,7 +7785,7 @@ unsafe fn test_lsx_vrotri_h() { let a = i16x8::new(-14120, -16812, -19570, -990, 24476, -7640, 20329, 8879); let r = i64x2::new(-556925602567188047, 4998607264501841720); - assert_eq!(r, transmute(lsx_vrotri_h::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_h::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5849,7 +7793,7 @@ unsafe fn test_lsx_vrotri_w() { let a = i32x4::new(-1760224525, -1644621284, 1835781046, -1487934110); let r = i64x2::new(2845787365010917052, -6209343103231659283); - assert_eq!(r, transmute(lsx_vrotri_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5857,7 +7801,7 @@ unsafe fn test_lsx_vrotri_d() { let a = i64x2::new(8884634342417174882, 244175985366916345); let r = i64x2::new(-3963790888197019724, 4020656082573561910); - assert_eq!(r, transmute(lsx_vrotri_d::<52>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_d::<52>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5865,7 +7809,7 @@ unsafe fn test_lsx_vextl_q_d() { let a = i64x2::new(-5110246490938885255, 377414780188285171); let r = i64x2::new(-5110246490938885255, -1); - assert_eq!(r, transmute(lsx_vextl_q_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vextl_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5880,7 +7824,10 @@ unsafe fn test_lsx_vsrlni_b_h() { assert_eq!( r, - transmute(lsx_vsrlni_b_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_b_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5892,7 +7839,10 @@ unsafe fn test_lsx_vsrlni_h_w() { assert_eq!( r, - transmute(lsx_vsrlni_h_w::<26>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_h_w::<26>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5904,7 +7854,10 @@ unsafe fn test_lsx_vsrlni_w_d() { assert_eq!( r, - transmute(lsx_vsrlni_w_d::<18>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_w_d::<18>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5916,7 +7869,10 @@ unsafe fn test_lsx_vsrlni_d_q() { assert_eq!( r, - transmute(lsx_vsrlni_d_q::<74>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_d_q::<74>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5932,7 +7888,10 @@ unsafe fn test_lsx_vsrlrni_b_h() { assert_eq!( r, - transmute(lsx_vsrlrni_b_h::<6>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_b_h::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5944,7 +7903,10 @@ unsafe fn test_lsx_vsrlrni_h_w() { assert_eq!( r, - transmute(lsx_vsrlrni_h_w::<6>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_h_w::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5956,7 +7918,10 @@ unsafe fn test_lsx_vsrlrni_w_d() { assert_eq!( r, - transmute(lsx_vsrlrni_w_d::<52>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_w_d::<52>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5968,7 +7933,10 @@ unsafe fn test_lsx_vsrlrni_d_q() { assert_eq!( r, - transmute(lsx_vsrlrni_d_q::<101>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_d_q::<101>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5984,7 +7952,10 @@ unsafe fn test_lsx_vssrlni_b_h() { assert_eq!( r, - transmute(lsx_vssrlni_b_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_b_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5996,7 +7967,10 @@ unsafe fn test_lsx_vssrlni_h_w() { assert_eq!( r, - transmute(lsx_vssrlni_h_w::<23>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_h_w::<23>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6008,7 +7982,10 @@ unsafe fn test_lsx_vssrlni_w_d() { assert_eq!( r, - transmute(lsx_vssrlni_w_d::<12>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_w_d::<12>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6020,7 +7997,10 @@ unsafe fn test_lsx_vssrlni_d_q() { assert_eq!( r, - transmute(lsx_vssrlni_d_q::<88>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_d_q::<88>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6036,7 +8016,10 @@ unsafe fn test_lsx_vssrlni_bu_h() { assert_eq!( r, - transmute(lsx_vssrlni_bu_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_bu_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6048,7 +8031,10 @@ unsafe fn test_lsx_vssrlni_hu_w() { assert_eq!( r, - transmute(lsx_vssrlni_hu_w::<9>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_hu_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6060,7 +8046,10 @@ unsafe fn test_lsx_vssrlni_wu_d() { assert_eq!( r, - transmute(lsx_vssrlni_wu_d::<59>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_wu_d::<59>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6072,7 +8061,10 @@ unsafe fn test_lsx_vssrlni_du_q() { assert_eq!( r, - transmute(lsx_vssrlni_du_q::<6>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_du_q::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6088,7 +8080,10 @@ unsafe fn test_lsx_vssrlrni_b_h() { assert_eq!( r, - transmute(lsx_vssrlrni_b_h::<0>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_b_h::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6100,7 +8095,10 @@ unsafe fn test_lsx_vssrlrni_h_w() { assert_eq!( r, - transmute(lsx_vssrlrni_h_w::<28>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_h_w::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6112,7 +8110,10 @@ unsafe fn test_lsx_vssrlrni_w_d() { assert_eq!( r, - transmute(lsx_vssrlrni_w_d::<1>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_w_d::<1>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6124,7 +8125,10 @@ unsafe fn test_lsx_vssrlrni_d_q() { assert_eq!( r, - transmute(lsx_vssrlrni_d_q::<60>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_d_q::<60>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6140,7 +8144,10 @@ unsafe fn test_lsx_vssrlrni_bu_h() { assert_eq!( r, - transmute(lsx_vssrlrni_bu_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_bu_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6152,7 +8159,10 @@ unsafe fn test_lsx_vssrlrni_hu_w() { assert_eq!( r, - transmute(lsx_vssrlrni_hu_w::<25>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_hu_w::<25>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6164,7 +8174,10 @@ unsafe fn test_lsx_vssrlrni_wu_d() { assert_eq!( r, - transmute(lsx_vssrlrni_wu_d::<36>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_wu_d::<36>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6176,7 +8189,10 @@ unsafe fn test_lsx_vssrlrni_du_q() { assert_eq!( r, - transmute(lsx_vssrlrni_du_q::<38>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_du_q::<38>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6192,7 +8208,10 @@ unsafe fn test_lsx_vsrani_b_h() { assert_eq!( r, - transmute(lsx_vsrani_b_h::<5>(transmute(a), transmute(b))) + transmute(lsx_vsrani_b_h::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6204,7 +8223,10 @@ unsafe fn test_lsx_vsrani_h_w() { assert_eq!( r, - transmute(lsx_vsrani_h_w::<4>(transmute(a), transmute(b))) + transmute(lsx_vsrani_h_w::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6216,7 +8238,10 @@ unsafe fn test_lsx_vsrani_w_d() { assert_eq!( r, - transmute(lsx_vsrani_w_d::<24>(transmute(a), transmute(b))) + transmute(lsx_vsrani_w_d::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6228,7 +8253,10 @@ unsafe fn test_lsx_vsrani_d_q() { assert_eq!( r, - transmute(lsx_vsrani_d_q::<81>(transmute(a), transmute(b))) + transmute(lsx_vsrani_d_q::<81>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6244,7 +8272,10 @@ unsafe fn test_lsx_vsrarni_b_h() { assert_eq!( r, - transmute(lsx_vsrarni_b_h::<3>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_b_h::<3>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6256,7 +8287,10 @@ unsafe fn test_lsx_vsrarni_h_w() { assert_eq!( r, - transmute(lsx_vsrarni_h_w::<15>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_h_w::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6268,7 +8302,10 @@ unsafe fn test_lsx_vsrarni_w_d() { assert_eq!( r, - transmute(lsx_vsrarni_w_d::<59>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_w_d::<59>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6280,7 +8317,10 @@ unsafe fn test_lsx_vsrarni_d_q() { assert_eq!( r, - transmute(lsx_vsrarni_d_q::<0>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_d_q::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6296,7 +8336,10 @@ unsafe fn test_lsx_vssrani_b_h() { assert_eq!( r, - transmute(lsx_vssrani_b_h::<0>(transmute(a), transmute(b))) + transmute(lsx_vssrani_b_h::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6308,7 +8351,10 @@ unsafe fn test_lsx_vssrani_h_w() { assert_eq!( r, - transmute(lsx_vssrani_h_w::<28>(transmute(a), transmute(b))) + transmute(lsx_vssrani_h_w::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6320,7 +8366,10 @@ unsafe fn test_lsx_vssrani_w_d() { assert_eq!( r, - transmute(lsx_vssrani_w_d::<49>(transmute(a), transmute(b))) + transmute(lsx_vssrani_w_d::<49>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6332,7 +8381,10 @@ unsafe fn test_lsx_vssrani_d_q() { assert_eq!( r, - transmute(lsx_vssrani_d_q::<80>(transmute(a), transmute(b))) + transmute(lsx_vssrani_d_q::<80>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6348,7 +8400,10 @@ unsafe fn test_lsx_vssrani_bu_h() { assert_eq!( r, - transmute(lsx_vssrani_bu_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vssrani_bu_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6360,7 +8415,10 @@ unsafe fn test_lsx_vssrani_hu_w() { assert_eq!( r, - transmute(lsx_vssrani_hu_w::<23>(transmute(a), transmute(b))) + transmute(lsx_vssrani_hu_w::<23>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6372,7 +8430,10 @@ unsafe fn test_lsx_vssrani_wu_d() { assert_eq!( r, - transmute(lsx_vssrani_wu_d::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrani_wu_d::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6384,7 +8445,10 @@ unsafe fn test_lsx_vssrani_du_q() { assert_eq!( r, - transmute(lsx_vssrani_du_q::<33>(transmute(a), transmute(b))) + transmute(lsx_vssrani_du_q::<33>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6400,7 +8464,10 @@ unsafe fn test_lsx_vssrarni_b_h() { assert_eq!( r, - transmute(lsx_vssrarni_b_h::<2>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_b_h::<2>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6412,7 +8479,10 @@ unsafe fn test_lsx_vssrarni_h_w() { assert_eq!( r, - transmute(lsx_vssrarni_h_w::<29>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_h_w::<29>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6424,7 +8494,10 @@ unsafe fn test_lsx_vssrarni_w_d() { assert_eq!( r, - transmute(lsx_vssrarni_w_d::<18>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_w_d::<18>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6436,7 +8509,10 @@ unsafe fn test_lsx_vssrarni_d_q() { assert_eq!( r, - transmute(lsx_vssrarni_d_q::<70>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_d_q::<70>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6452,7 +8528,10 @@ unsafe fn test_lsx_vssrarni_bu_h() { assert_eq!( r, - transmute(lsx_vssrarni_bu_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_bu_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6464,7 +8543,10 @@ unsafe fn test_lsx_vssrarni_hu_w() { assert_eq!( r, - transmute(lsx_vssrarni_hu_w::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_hu_w::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6476,7 +8558,10 @@ unsafe fn test_lsx_vssrarni_wu_d() { assert_eq!( r, - transmute(lsx_vssrarni_wu_d::<15>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_wu_d::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6488,7 +8573,10 @@ unsafe fn test_lsx_vssrarni_du_q() { assert_eq!( r, - transmute(lsx_vssrarni_du_q::<126>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_du_q::<126>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6500,7 +8588,10 @@ unsafe fn test_lsx_vpermi_w() { assert_eq!( r, - transmute(lsx_vpermi_w::<158>(transmute(a), transmute(b))) + transmute(lsx_vpermi_w::<158>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6524,7 +8615,7 @@ unsafe fn test_lsx_vst() { ]; let r = i64x2::new(4153633675232462821, -2083384694265299697); - lsx_vst::<0>(transmute(a), o.as_mut_ptr()); + lsx_vst::<0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -6534,7 +8625,13 @@ unsafe fn test_lsx_vssrlrn_b_h() { let b = i16x8::new(17437, 9775, -20467, -31838, 5913, 4238, -7458, 2822); let r = i64x2::new(5981906731171643399, 0); - assert_eq!(r, transmute(lsx_vssrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6543,7 +8640,13 @@ unsafe fn test_lsx_vssrlrn_h_w() { let b = i32x4::new(-2116426818, 1641049288, 712377342, -1572394121); let r = i64x2::new(31243728857268226, 0); - assert_eq!(r, transmute(lsx_vssrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6552,7 +8655,13 @@ unsafe fn test_lsx_vssrlrn_w_d() { let b = i64x2::new(-3890929847852895653, -7819301294522132056); let r = i64x2::new(66519777023098879, 0); - assert_eq!(r, transmute(lsx_vssrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6561,7 +8670,13 @@ unsafe fn test_lsx_vssrln_b_h() { let b = i16x8::new(-14062, -29610, -24609, -8884, -1818, 32133, 29934, -6498); let r = i64x2::new(140183437672319, 0); - assert_eq!(r, transmute(lsx_vssrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6570,7 +8685,13 @@ unsafe fn test_lsx_vssrln_h_w() { let b = i32x4::new(-1437891045, 1546371535, -1800954476, -1892390372); let r = i64x2::new(2820489990832156, 0); - assert_eq!(r, transmute(lsx_vssrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6579,7 +8700,13 @@ unsafe fn test_lsx_vssrln_w_d() { let b = i64x2::new(2034490755997557661, -3470252066162700534); let r = i64x2::new(9223372034707292159, 0); - assert_eq!(r, transmute(lsx_vssrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6592,7 +8719,10 @@ unsafe fn test_lsx_vorn_v() { ); let r = i64x2::new(-883973744907789059, -2901520201165080862); - assert_eq!(r, transmute(lsx_vorn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vorn_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -6615,7 +8745,11 @@ unsafe fn test_lsx_vshuf_b() { assert_eq!( r, - transmute(lsx_vshuf_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -6639,7 +8773,7 @@ unsafe fn test_lsx_vstx() { ]; let r = i64x2::new(-1493444417618012559, 7191635320606490850); - lsx_vstx(transmute(a), o.as_mut_ptr(), 0); + lsx_vstx(black_box(transmute(a)), o.as_mut_ptr(), 0); assert_eq!(r, transmute(o)); } @@ -6648,7 +8782,7 @@ unsafe fn test_lsx_vextl_qu_du() { let a = u64x2::new(14708598110732796778, 2132245682694336458); let r = i64x2::new(-3738145962976754838, 0); - assert_eq!(r, transmute(lsx_vextl_qu_du(transmute(a)))); + assert_eq!(r, transmute(lsx_vextl_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6658,7 +8792,7 @@ unsafe fn test_lsx_bnz_b() { ); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6666,7 +8800,7 @@ unsafe fn test_lsx_bnz_d() { let a = u64x2::new(2935166648440262530, 9853932033129373129); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6674,7 +8808,7 @@ unsafe fn test_lsx_bnz_h() { let a = u16x8::new(55695, 60003, 59560, 35123, 25693, 41352, 61626, 42007); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6684,7 +8818,7 @@ unsafe fn test_lsx_bnz_v() { ); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_v(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_v(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6692,7 +8826,7 @@ unsafe fn test_lsx_bnz_w() { let a = u32x4::new(1172712391, 4211490091, 1954893853, 1606462106); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6702,7 +8836,7 @@ unsafe fn test_lsx_bz_b() { ); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6710,7 +8844,7 @@ unsafe fn test_lsx_bz_d() { let a = u64x2::new(6051854163594201075, 9957257179760945130); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6718,7 +8852,7 @@ unsafe fn test_lsx_bz_h() { let a = u16x8::new(19470, 29377, 53886, 60432, 20799, 41755, 54479, 52192); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6728,7 +8862,7 @@ unsafe fn test_lsx_bz_v() { ); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_v(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_v(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6736,7 +8870,7 @@ unsafe fn test_lsx_bz_w() { let a = u32x4::new(840335855, 1404686204, 628335401, 1171808080); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6745,7 +8879,13 @@ unsafe fn test_lsx_vfcmp_caf_d() { let b = u64x2::new(4594845432849836188, 4605165420863530034); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_caf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_caf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6754,7 +8894,13 @@ unsafe fn test_lsx_vfcmp_caf_s() { let b = u32x4::new(1058412800, 1058762495, 1028487696, 1027290752); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_caf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_caf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6763,7 +8909,13 @@ unsafe fn test_lsx_vfcmp_ceq_d() { let b = u64x2::new(4605937250150464526, 4596769502461699132); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_ceq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_ceq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6772,7 +8924,13 @@ unsafe fn test_lsx_vfcmp_ceq_s() { let b = u32x4::new(1057471620, 1064008655, 1062698831, 1064822930); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_ceq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_ceq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6781,7 +8939,13 @@ unsafe fn test_lsx_vfcmp_cle_d() { let b = u64x2::new(4596931282408842596, 4592481315209481584); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vfcmp_cle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6790,7 +8954,13 @@ unsafe fn test_lsx_vfcmp_cle_s() { let b = u32x4::new(1021993344, 1043028808, 1064182329, 1054794412); let r = i64x2::new(-4294967296, -1); - assert_eq!(r, transmute(lsx_vfcmp_cle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6799,7 +8969,13 @@ unsafe fn test_lsx_vfcmp_clt_d() { let b = u64x2::new(4603056125735978454, 4595932368389116476); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_clt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_clt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6808,7 +8984,13 @@ unsafe fn test_lsx_vfcmp_clt_s() { let b = u32x4::new(1040327468, 1040072248, 1063314103, 1061361061); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_clt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_clt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6817,7 +8999,13 @@ unsafe fn test_lsx_vfcmp_cne_d() { let b = u64x2::new(4602354759349431170, 4598595124838935466); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6826,7 +9014,13 @@ unsafe fn test_lsx_vfcmp_cne_s() { let b = u32x4::new(1063262940, 1058010357, 1052721962, 1061295988); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6835,7 +9029,13 @@ unsafe fn test_lsx_vfcmp_cor_d() { let b = u64x2::new(4606863361114437050, 4600753700959452152); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6844,7 +9044,13 @@ unsafe fn test_lsx_vfcmp_cor_s() { let b = u32x4::new(1053615382, 1065255138, 1051565294, 1041776832); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6853,7 +9059,13 @@ unsafe fn test_lsx_vfcmp_cueq_d() { let b = u64x2::new(4603317345052528721, 4586734343919602352); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6862,7 +9074,13 @@ unsafe fn test_lsx_vfcmp_cueq_s() { let b = u32x4::new(1057082822, 1059761998, 1052599998, 1054369118); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6871,7 +9089,13 @@ unsafe fn test_lsx_vfcmp_cule_d() { let b = u64x2::new(4604253448175093958, 4599648167588382448); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6880,7 +9104,13 @@ unsafe fn test_lsx_vfcmp_cule_s() { let b = u32x4::new(1051100696, 1062219104, 1064568294, 1032521352); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vfcmp_cule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6889,7 +9119,13 @@ unsafe fn test_lsx_vfcmp_cult_d() { let b = u64x2::new(4602944708025910986, 4606429728449082215); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_cult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6898,7 +9134,13 @@ unsafe fn test_lsx_vfcmp_cult_s() { let b = u32x4::new(1030808384, 1044268840, 1050761328, 1037308928); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6907,7 +9149,13 @@ unsafe fn test_lsx_vfcmp_cun_d() { let b = u64x2::new(4599145506416791474, 4602762942707610466); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6916,7 +9164,13 @@ unsafe fn test_lsx_vfcmp_cune_d() { let b = u64x2::new(4602895209237804084, 4598685577984089858); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6925,7 +9179,13 @@ unsafe fn test_lsx_vfcmp_cune_s() { let b = u32x4::new(1049955876, 1032474200, 1023410112, 1050347912); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6934,7 +9194,13 @@ unsafe fn test_lsx_vfcmp_cun_s() { let b = u32x4::new(1053288920, 1059911123, 1058695573, 1062913175); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6943,7 +9209,13 @@ unsafe fn test_lsx_vfcmp_saf_d() { let b = u64x2::new(4589118818065931376, 4603302333347826011); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_saf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_saf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6952,7 +9224,13 @@ unsafe fn test_lsx_vfcmp_saf_s() { let b = u32x4::new(1044756936, 1054667546, 1059141760, 1062203553); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_saf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_saf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6961,7 +9239,13 @@ unsafe fn test_lsx_vfcmp_seq_d() { let b = u64x2::new(4594167956310606988, 4596272126122589228); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_seq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_seq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6970,7 +9254,13 @@ unsafe fn test_lsx_vfcmp_seq_s() { let b = u32x4::new(1057231588, 1051495460, 1057998997, 1049117328); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_seq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_seq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6979,7 +9269,13 @@ unsafe fn test_lsx_vfcmp_sle_d() { let b = u64x2::new(4603919005855163252, 4594682846653946884); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6988,7 +9284,13 @@ unsafe fn test_lsx_vfcmp_sle_s() { let b = u32x4::new(1045989468, 1052518900, 1046184640, 1032417352); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6997,7 +9299,13 @@ unsafe fn test_lsx_vfcmp_slt_d() { let b = u64x2::new(4600564867142526828, 4585131890265864544); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_slt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_slt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7006,7 +9314,13 @@ unsafe fn test_lsx_vfcmp_slt_s() { let b = u32x4::new(1063435026, 1062439603, 1060665555, 1059252630); let r = i64x2::new(-1, -4294967296); - assert_eq!(r, transmute(lsx_vfcmp_slt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_slt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7015,7 +9329,13 @@ unsafe fn test_lsx_vfcmp_sne_d() { let b = u64x2::new(4606789952952688555, 4605380358192261377); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7024,7 +9344,13 @@ unsafe fn test_lsx_vfcmp_sne_s() { let b = u32x4::new(1055803760, 1063372602, 1062608900, 1054634370); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7033,7 +9359,13 @@ unsafe fn test_lsx_vfcmp_sor_d() { let b = u64x2::new(4606380175568635560, 4602092067387067462); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7042,7 +9374,13 @@ unsafe fn test_lsx_vfcmp_sor_s() { let b = u32x4::new(1064534350, 1035771168, 1059142426, 1034677600); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7051,7 +9389,13 @@ unsafe fn test_lsx_vfcmp_sueq_d() { let b = u64x2::new(4602917609947054533, 4605983209212177197); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7060,7 +9404,13 @@ unsafe fn test_lsx_vfcmp_sueq_s() { let b = u32x4::new(1064871165, 1059796257, 1055456352, 1058662692); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7069,7 +9419,13 @@ unsafe fn test_lsx_vfcmp_sule_d() { let b = u64x2::new(4594044173266256632, 4601549551994738386); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_sule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7078,7 +9434,13 @@ unsafe fn test_lsx_vfcmp_sule_s() { let b = u32x4::new(1061061244, 1051874412, 1041025316, 1056018690); let r = i64x2::new(4294967295, -1); - assert_eq!(r, transmute(lsx_vfcmp_sule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7087,7 +9449,13 @@ unsafe fn test_lsx_vfcmp_sult_d() { let b = u64x2::new(4603848042095479627, 4605032971316970060); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7096,7 +9464,13 @@ unsafe fn test_lsx_vfcmp_sult_s() { let b = u32x4::new(1053631630, 1064026599, 1058029398, 1041182304); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vfcmp_sult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7105,7 +9479,13 @@ unsafe fn test_lsx_vfcmp_sun_d() { let b = u64x2::new(4560681020073292800, 4604624347352815433); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7114,7 +9494,13 @@ unsafe fn test_lsx_vfcmp_sune_d() { let b = u64x2::new(4593947987798339484, 4603656097008761637); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7123,7 +9509,13 @@ unsafe fn test_lsx_vfcmp_sune_s() { let b = u32x4::new(1049327168, 1034635272, 1042258196, 1062844003); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7132,7 +9524,13 @@ unsafe fn test_lsx_vfcmp_sun_s() { let b = u32x4::new(1057442863, 1064573466, 1058086753, 1015993248); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] diff --git a/stdarch/crates/core_arch/src/loongarch64/mod.rs b/stdarch/crates/core_arch/src/loongarch64/mod.rs index ab968aff20bbe..e8bf098a33327 100644 --- a/stdarch/crates/core_arch/src/loongarch64/mod.rs +++ b/stdarch/crates/core_arch/src/loongarch64/mod.rs @@ -2,6 +2,7 @@ mod lasx; mod lsx; +mod simd; #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub use self::lasx::*; @@ -11,7 +12,7 @@ pub use self::lsx::*; use crate::arch::asm; /// Reads the 64-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtime_d() -> (i64, isize) { let (val, tid): (i64, isize); @@ -21,8 +22,20 @@ pub fn rdtime_d() -> (i64, isize) { #[allow(improper_ctypes)] unsafe extern "unadjusted" { + #[link_name = "llvm.loongarch.crc.w.b.w"] + fn __crc_w_b_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crc.w.h.w"] + fn __crc_w_h_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crc.w.w.w"] + fn __crc_w_w_w(a: i32, b: i32) -> i32; #[link_name = "llvm.loongarch.crc.w.d.w"] fn __crc_w_d_w(a: i64, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.b.w"] + fn __crcc_w_b_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.h.w"] + fn __crcc_w_h_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.w.w"] + fn __crcc_w_w_w(a: i32, b: i32) -> i32; #[link_name = "llvm.loongarch.crcc.w.d.w"] fn __crcc_w_d_w(a: i64, b: i32) -> i32; #[link_name = "llvm.loongarch.cacop.d"] @@ -48,21 +61,63 @@ unsafe extern "unadjusted" { } /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] +#[inline(always)] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn crc_w_b_w(a: i8, b: i32) -> i32 { + unsafe { __crc_w_b_w(a as i32, b) } +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline(always)] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn crc_w_h_w(a: i16, b: i32) -> i32 { + unsafe { __crc_w_h_w(a as i32, b) } +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline(always)] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn crc_w_w_w(a: i32, b: i32) -> i32 { + unsafe { __crc_w_w_w(a, b) } +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crc_w_d_w(a: i64, b: i32) -> i32 { unsafe { __crc_w_d_w(a, b) } } /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] +#[inline(always)] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn crcc_w_b_w(a: i8, b: i32) -> i32 { + unsafe { __crcc_w_b_w(a as i32, b) } +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline(always)] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn crcc_w_h_w(a: i16, b: i32) -> i32 { + unsafe { __crcc_w_h_w(a as i32, b) } +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline(always)] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn crcc_w_w_w(a: i32, b: i32) -> i32 { + unsafe { __crcc_w_w_w(a, b) } +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crcc_w_d_w(a: i64, b: i32) -> i32 { unsafe { __crcc_w_d_w(a, b) } } /// Generates the cache operation instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn cacop(b: i64) { static_assert_uimm_bits!(IMM5, 5); @@ -71,7 +126,7 @@ pub unsafe fn cacop(b: i64) { } /// Reads the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrrd() -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -79,7 +134,7 @@ pub unsafe fn csrrd() -> i64 { } /// Writes the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrwr(a: i64) -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -87,7 +142,7 @@ pub unsafe fn csrwr(a: i64) -> i64 { } /// Exchanges the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrxchg(a: i64, b: i64) -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -95,35 +150,35 @@ pub unsafe fn csrxchg(a: i64, b: i64) -> i64 { } /// Reads the 64-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_d(a: i32) -> i64 { __iocsrrd_d(a) } /// Writes the 64-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_d(a: i64, b: i32) { __iocsrwr_d(a, b) } /// Generates the less-than-or-equal asseration instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn asrtle(a: i64, b: i64) { __asrtle(a, b); } /// Generates the greater-than asseration instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn asrtgt(a: i64, b: i64) { __asrtgt(a, b); } /// Loads the page table directory entry -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lddir(a: i64) -> i64 { @@ -132,7 +187,7 @@ pub unsafe fn lddir(a: i64) -> i64 { } /// Loads the page table entry -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn ldpte(a: i64) { diff --git a/stdarch/crates/core_arch/src/loongarch64/simd.rs b/stdarch/crates/core_arch/src/loongarch64/simd.rs new file mode 100644 index 0000000000000..24ee4874ae541 --- /dev/null +++ b/stdarch/crates/core_arch/src/loongarch64/simd.rs @@ -0,0 +1,354 @@ +//! LoongArch64 SIMD helpers + +use self as ls; +use crate::intrinsics::simd as is; + +// Internal extension trait for concrete `Simd` types. +// +// Provides a small set of helper functionality (`Elem` and `splat`) +// so generic and macro-based code can operate on different SIMD +// vector types in a uniform way. +pub(super) const trait SimdExt: Sized { + type Elem; + + unsafe fn splat(v: i64) -> Self; +} + +#[rustfmt::skip] // FIXME: https://github.com/rust-lang/stdarch/pull/2133#issuecomment-4524350350 +macro_rules! impl_simd_ext { + ($v:ident, $e:ty) => { + #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] + impl const SimdExt for crate::core_arch::simd::$v { + type Elem = $e; + + #[inline(always)] + unsafe fn splat(v: i64) -> Self { + is::simd_splat(v as Self::Elem) + } + } + }; +} + +impl_simd_ext!(i8x16, i8); +impl_simd_ext!(i8x32, i8); +impl_simd_ext!(u8x16, u8); +impl_simd_ext!(u8x32, u8); +impl_simd_ext!(i16x8, i16); +impl_simd_ext!(i16x16, i16); +impl_simd_ext!(u16x8, u16); +impl_simd_ext!(u16x16, u16); +impl_simd_ext!(i32x4, i32); +impl_simd_ext!(i32x8, i32); +impl_simd_ext!(u32x4, u32); +impl_simd_ext!(u32x8, u32); +impl_simd_ext!(i64x2, i64); +impl_simd_ext!(i64x4, i64); +impl_simd_ext!(u64x2, u64); +impl_simd_ext!(u64x4, u64); + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_abs(a: T) -> T { + let m: T = is::simd_lt(a, ls::simd_splat(0)); + is::simd_select(m, is::simd_neg(a), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_absd(a: T, b: T) -> T { + let m: T = is::simd_gt(a, b); + is::simd_select(m, is::simd_sub(a, b), is::simd_sub(b, a)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(crate) const unsafe fn simd_adda(a: T, b: T) -> T { + is::simd_add(ls::simd_abs(a), ls::simd_abs(b)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_andn(a: T, b: T) -> T { + is::simd_and(ls::simd_not(a), b) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_bitclr(a: T, b: T) -> T { + ls::simd_andn(ls::simd_shl(ls::simd_splat(1), b), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_bitrev(a: T, b: T) -> T { + is::simd_xor(ls::simd_shl(ls::simd_splat(1), b), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_bitset(a: T, b: T) -> T { + is::simd_or(ls::simd_shl(ls::simd_splat(1), b), a) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_fmsub(a: T, b: T, c: T) -> T { + is::simd_fma(a, b, is::simd_neg(c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_fnmadd(a: T, b: T, c: T) -> T { + is::simd_neg(is::simd_fma(a, b, c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_fnmsub(a: T, b: T, c: T) -> T { + is::simd_neg(ls::simd_fmsub(a, b, c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_madd(a: T, b: T, c: T) -> T { + is::simd_add(a, is::simd_mul(b, c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_msub(a: T, b: T, c: T) -> T { + is::simd_sub(a, is::simd_mul(b, c)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_nor(a: T, b: T) -> T { + ls::simd_not(is::simd_or(a, b)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_not(a: T) -> T { + is::simd_xor(a, ls::simd_splat(!0)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_orn(a: T, b: T) -> T { + is::simd_or(a, ls::simd_not(b)) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_shl(a: T, b: T) -> T { + let m = (size_of::() * 8 - 1) as i64; + is::simd_shl(a, is::simd_and(b, ls::simd_splat(m))) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_shr(a: T, b: T) -> T { + let m = (size_of::() * 8 - 1) as i64; + is::simd_shr(a, is::simd_and(b, ls::simd_splat(m))) +} + +#[inline(always)] +#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +pub(super) const unsafe fn simd_splat(a: i64) -> T { + T::splat(a) +} + +macro_rules! impl_vv { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + unsafe { + let a: $ity = transmute(a); + let r: $ity = $op(a); + transmute(r) + } + } + }; +} + +pub(super) use impl_vv; + +macro_rules! impl_gv { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $gty) -> $oty { + unsafe { + let r: $ity = $op(a.into()); + transmute(r) + } + } + }; +} + +pub(super) use impl_gv; + +macro_rules! impl_sv { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(0)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name() -> $oty { + static_assert_simm_bits!(IMM, $ibs); + unsafe { + let r: $ity = $op(IMM.into()); + transmute(r) + } + } + }; +} + +pub(super) use impl_sv; + +macro_rules! impl_vvv { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty, b: $oty) -> $oty { + unsafe { + let a: $ity = transmute(a); + let b: $ity = transmute(b); + let r: $ity = $op(a, b); + transmute(r) + } + } + }; +} + +pub(super) use impl_vvv; + +macro_rules! impl_vuv { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + static_assert_uimm_bits!(IMM, (size_of::<<$ity as SimdExt>::Elem>() * 8).ilog2()); + unsafe { + let a: $ity = transmute(a); + let b: $ity = ls::simd_splat(IMM.into()); + let r: $ity = $op(a, b); + transmute(r) + } + } + }; + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let b: $ity = ls::simd_splat(IMM.into()); + let r: $ity = $op(a, b); + transmute(r) + } + } + }; + ($ft:literal, $name:ident, $op:ident, $oty:ty, $ity:ident, $ibs:expr, const) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let r: $ity = $op::(a); + transmute(r) + } + } + }; +} + +pub(super) use impl_vuv; + +macro_rules! impl_vug { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $gty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let r: <$ity as SimdExt>::Elem = $op(a, IMM); + r as $gty + } + } + }; +} + +pub(super) use impl_vug; + +macro_rules! impl_vsv { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty) -> $oty { + static_assert_simm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let b: $ity = ls::simd_splat(IMM.into()); + let r: $ity = $op(a, b); + transmute(r) + } + } + }; +} + +pub(super) use impl_vsv; + +macro_rules! impl_vvvv { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ty) => { + #[inline] + #[target_feature(enable = $ft)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty, b: $oty, c: $oty) -> $oty { + unsafe { + let a: $ity = transmute(a); + let b: $ity = transmute(b); + let c: $ity = transmute(c); + let r: $ity = $op(a, b, c); + transmute(r) + } + } + }; +} + +pub(super) use impl_vvvv; + +macro_rules! impl_vugv { + ($ft:literal, $name:ident, $op:path, $oty:ty, $ity:ident, $gty:ty, $ibs:expr) => { + #[inline] + #[target_feature(enable = $ft)] + #[rustc_legacy_const_generics(1)] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub fn $name(a: $oty, b: $gty) -> $oty { + static_assert_uimm_bits!(IMM, $ibs); + unsafe { + let a: $ity = transmute(a); + let r: $ity = $op(a, IMM, b as <$ity as SimdExt>::Elem); + transmute(r) + } + } + }; +} + +pub(super) use impl_vugv; diff --git a/stdarch/crates/core_arch/src/loongarch_shared/mod.rs b/stdarch/crates/core_arch/src/loongarch_shared/mod.rs index 8991fe857682b..4f24ff2932210 100644 --- a/stdarch/crates/core_arch/src/loongarch_shared/mod.rs +++ b/stdarch/crates/core_arch/src/loongarch_shared/mod.rs @@ -3,7 +3,7 @@ use crate::arch::asm; /// Reads the lower 32-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtimel_w() -> (i32, isize) { let (val, tid): (i32, isize); @@ -12,7 +12,7 @@ pub fn rdtimel_w() -> (i32, isize) { } /// Reads the upper 32-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtimeh_w() -> (i32, isize) { let (val, tid): (i32, isize); @@ -22,18 +22,6 @@ pub fn rdtimeh_w() -> (i32, isize) { #[allow(improper_ctypes)] unsafe extern "unadjusted" { - #[link_name = "llvm.loongarch.crc.w.b.w"] - fn __crc_w_b_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crc.w.h.w"] - fn __crc_w_h_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crc.w.w.w"] - fn __crc_w_w_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.b.w"] - fn __crcc_w_b_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.h.w"] - fn __crcc_w_h_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.w.w"] - fn __crcc_w_w_w(a: i32, b: i32) -> i32; #[link_name = "llvm.loongarch.dbar"] fn __dbar(a: i32); #[link_name = "llvm.loongarch.ibar"] @@ -70,50 +58,8 @@ unsafe extern "unadjusted" { fn __frsqrte_d(a: f64) -> f64; } -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crc_w_b_w(a: i32, b: i32) -> i32 { - unsafe { __crc_w_b_w(a, b) } -} - -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crc_w_h_w(a: i32, b: i32) -> i32 { - unsafe { __crc_w_h_w(a, b) } -} - -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crc_w_w_w(a: i32, b: i32) -> i32 { - unsafe { __crc_w_w_w(a, b) } -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crcc_w_b_w(a: i32, b: i32) -> i32 { - unsafe { __crcc_w_b_w(a, b) } -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crcc_w_h_w(a: i32, b: i32) -> i32 { - unsafe { __crcc_w_h_w(a, b) } -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub fn crcc_w_w_w(a: i32, b: i32) -> i32 { - unsafe { __crcc_w_w_w(a, b) } -} - /// Generates the memory barrier instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn dbar() { static_assert_uimm_bits!(IMM15, 15); @@ -121,7 +67,7 @@ pub fn dbar() { } /// Generates the instruction-fetch barrier instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn ibar() { static_assert_uimm_bits!(IMM15, 15); @@ -129,7 +75,7 @@ pub fn ibar() { } /// Moves data from a GPR to the FCSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn movgr2fcsr(a: i32) { static_assert_uimm_bits!(IMM2, 2); @@ -137,7 +83,7 @@ pub unsafe fn movgr2fcsr(a: i32) { } /// Moves data from a FCSR to the GPR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn movfcsr2gr() -> i32 { static_assert_uimm_bits!(IMM2, 2); @@ -145,49 +91,49 @@ pub fn movfcsr2gr() -> i32 { } /// Reads the 8-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_b(a: i32) -> i32 { __iocsrrd_b(a) } /// Reads the 16-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_h(a: i32) -> i32 { __iocsrrd_h(a) } /// Reads the 32-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_w(a: i32) -> i32 { __iocsrrd_w(a) } /// Writes the 8-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_b(a: i32, b: i32) { __iocsrwr_b(a, b) } /// Writes the 16-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_h(a: i32, b: i32) { __iocsrwr_h(a, b) } /// Writes the 32-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_w(a: i32, b: i32) { __iocsrwr_w(a, b) } /// Generates the breakpoint instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn brk() { static_assert_uimm_bits!(IMM15, 15); @@ -195,14 +141,14 @@ pub unsafe fn brk() { } /// Reads the CPU configuration register -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn cpucfg(a: i32) -> i32 { unsafe { __cpucfg(a) } } /// Generates the syscall instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn syscall() { static_assert_uimm_bits!(IMM15, 15); diff --git a/stdarch/crates/core_arch/src/macros.rs b/stdarch/crates/core_arch/src/macros.rs index 00e92428b3e7e..def2fd682bd77 100644 --- a/stdarch/crates/core_arch/src/macros.rs +++ b/stdarch/crates/core_arch/src/macros.rs @@ -14,6 +14,22 @@ macro_rules! static_assert { }; } +#[allow(unused_macros)] +macro_rules! static_assert_range { + ($imm:ident, $min:literal..=$max:literal) => { + static_assert!( + $min <= $imm && $imm <= $max, + concat!( + stringify!($imm), + " is not in range ", + stringify!($min), + "-", + stringify!($max), + ) + ) + }; +} + #[allow(unused_macros)] macro_rules! static_assert_uimm_bits { ($imm:ident, $bits:expr) => { @@ -26,7 +42,7 @@ macro_rules! static_assert_uimm_bits { stringify!($imm), " doesn't fit in ", stringify!($bits), - " bits", + " bits (unsigned)", ) ) } @@ -42,7 +58,7 @@ macro_rules! static_assert_simm_bits { stringify!($imm), " doesn't fit in ", stringify!($bits), - " bits", + " bits (signed)", ) ) }; diff --git a/stdarch/crates/core_arch/src/mips/msa.rs b/stdarch/crates/core_arch/src/mips/msa.rs index 6246433da5585..bc601baef9e2a 100644 --- a/stdarch/crates/core_arch/src/mips/msa.rs +++ b/stdarch/crates/core_arch/src/mips/msa.rs @@ -1407,7 +1407,7 @@ pub unsafe fn __msa_addv_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.b, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.b, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_b(a: v16i8) -> v16i8 { @@ -1423,7 +1423,7 @@ pub unsafe fn __msa_addvi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.h, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.h, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_h(a: v8i16) -> v8i16 { @@ -1439,7 +1439,7 @@ pub unsafe fn __msa_addvi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.w, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.w, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_w(a: v4i32) -> v4i32 { @@ -1455,7 +1455,7 @@ pub unsafe fn __msa_addvi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.d, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.d, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_d(a: v2i64) -> v2i64 { @@ -1486,7 +1486,7 @@ pub unsafe fn __msa_and_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(andi.b, imm8 = 0b10010111))] +#[cfg_attr(test, assert_instr(andi.b, IMM8 = 0b10010111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_andi_b(a: v16u8) -> v16u8 { @@ -1938,7 +1938,7 @@ pub unsafe fn __msa_bclr_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bclri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_b(a: v16u8) -> v16u8 { @@ -1954,7 +1954,7 @@ pub unsafe fn __msa_bclri_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bclri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_h(a: v8u16) -> v8u16 { @@ -1970,7 +1970,7 @@ pub unsafe fn __msa_bclri_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bclri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_w(a: v4u32) -> v4u32 { @@ -1986,7 +1986,7 @@ pub unsafe fn __msa_bclri_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bclri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_d(a: v2u64) -> v2u64 { @@ -2062,7 +2062,7 @@ pub unsafe fn __msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(binsli.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2078,7 +2078,7 @@ pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(binsli.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16) -> v8u16 { @@ -2094,7 +2094,7 @@ pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(binsli.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32) -> v4u32 { @@ -2110,7 +2110,7 @@ pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(binsli.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_d(a: v2u64, b: v2u64) -> v2u64 { @@ -2186,7 +2186,7 @@ pub unsafe fn __msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(binsri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2202,7 +2202,7 @@ pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(binsri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16) -> v8u16 { @@ -2218,7 +2218,7 @@ pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(binsri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32) -> v4u32 { @@ -2234,7 +2234,7 @@ pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(binsri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_d(a: v2u64, b: v2u64) -> v2u64 { @@ -2265,7 +2265,7 @@ pub unsafe fn __msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bmnzi.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bmnzi.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bmnzi_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2296,7 +2296,7 @@ pub unsafe fn __msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bmzi.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bmzi.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bmzi_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2372,7 +2372,7 @@ pub unsafe fn __msa_bneg_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bnegi.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_b(a: v16u8) -> v16u8 { @@ -2388,7 +2388,7 @@ pub unsafe fn __msa_bnegi_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bnegi.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_h(a: v8u16) -> v8u16 { @@ -2404,7 +2404,7 @@ pub unsafe fn __msa_bnegi_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bnegi.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_w(a: v4u32) -> v4u32 { @@ -2420,7 +2420,7 @@ pub unsafe fn __msa_bnegi_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bnegi.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_d(a: v2u64) -> v2u64 { @@ -2512,7 +2512,7 @@ pub unsafe fn __msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseli.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bseli.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseli_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2588,7 +2588,7 @@ pub unsafe fn __msa_bset_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bseti.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_b(a: v16u8) -> v16u8 { @@ -2604,7 +2604,7 @@ pub unsafe fn __msa_bseti_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bseti.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_h(a: v8u16) -> v8u16 { @@ -2620,7 +2620,7 @@ pub unsafe fn __msa_bseti_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bseti.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_w(a: v4u32) -> v4u32 { @@ -2636,7 +2636,7 @@ pub unsafe fn __msa_bseti_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bseti.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_d(a: v2u64) -> v2u64 { @@ -2769,7 +2769,7 @@ pub unsafe fn __msa_ceq_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_b(a: v16i8) -> v16i8 { @@ -2785,7 +2785,7 @@ pub unsafe fn __msa_ceqi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_h(a: v8i16) -> v8i16 { @@ -2801,7 +2801,7 @@ pub unsafe fn __msa_ceqi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_w(a: v4i32) -> v4i32 { @@ -2817,7 +2817,7 @@ pub unsafe fn __msa_ceqi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_d(a: v2i64) -> v2i64 { @@ -2832,7 +2832,7 @@ pub unsafe fn __msa_ceqi_d(a: v2i64) -> v2i64 { /// Can not be tested in user mode #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(cfcmsa, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(cfcmsa, IMM5 = 0b11111))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_cfcmsa() -> i32 { @@ -2969,7 +2969,7 @@ pub unsafe fn __msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_b(a: v16i8) -> v16i8 { @@ -2986,7 +2986,7 @@ pub unsafe fn __msa_clei_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_h(a: v8i16) -> v8i16 { @@ -3003,7 +3003,7 @@ pub unsafe fn __msa_clei_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_w(a: v4i32) -> v4i32 { @@ -3020,7 +3020,7 @@ pub unsafe fn __msa_clei_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_d(a: v2i64) -> v2i64 { @@ -3037,7 +3037,7 @@ pub unsafe fn __msa_clei_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.b, imm5 = 0b111))] +#[cfg_attr(test, assert_instr(clei_u.b, IMM5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_b(a: v16u8) -> v16i8 { @@ -3054,7 +3054,7 @@ pub unsafe fn __msa_clei_u_b(a: v16u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_h(a: v8u16) -> v8i16 { @@ -3071,7 +3071,7 @@ pub unsafe fn __msa_clei_u_h(a: v8u16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_w(a: v4u32) -> v4i32 { @@ -3088,7 +3088,7 @@ pub unsafe fn __msa_clei_u_w(a: v4u32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_d(a: v2u64) -> v2i64 { @@ -3225,7 +3225,7 @@ pub unsafe fn __msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.b, imm_s5 = 0b111))] +#[cfg_attr(test, assert_instr(clti_s.b, IMM_S5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_b(a: v16i8) -> v16i8 { @@ -3242,7 +3242,7 @@ pub unsafe fn __msa_clti_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_h(a: v8i16) -> v8i16 { @@ -3259,7 +3259,7 @@ pub unsafe fn __msa_clti_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_w(a: v4i32) -> v4i32 { @@ -3276,7 +3276,7 @@ pub unsafe fn __msa_clti_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_d(a: v2i64) -> v2i64 { @@ -3293,7 +3293,7 @@ pub unsafe fn __msa_clti_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.b, imm5 = 0b111))] +#[cfg_attr(test, assert_instr(clti_u.b, IMM5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_b(a: v16u8) -> v16i8 { @@ -3310,7 +3310,7 @@ pub unsafe fn __msa_clti_u_b(a: v16u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_h(a: v8u16) -> v8i16 { @@ -3327,7 +3327,7 @@ pub unsafe fn __msa_clti_u_h(a: v8u16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_w(a: v4u32) -> v4i32 { @@ -3344,7 +3344,7 @@ pub unsafe fn __msa_clti_u_w(a: v4u32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_d(a: v2u64) -> v2i64 { @@ -3359,7 +3359,7 @@ pub unsafe fn __msa_clti_u_d(a: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(copy_s.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_b(a: v16i8) -> i32 { @@ -3374,7 +3374,7 @@ pub unsafe fn __msa_copy_s_b(a: v16i8) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(copy_s.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_h(a: v8i16) -> i32 { @@ -3389,7 +3389,7 @@ pub unsafe fn __msa_copy_s_h(a: v8i16) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(copy_s.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_w(a: v4i32) -> i32 { @@ -3404,7 +3404,7 @@ pub unsafe fn __msa_copy_s_w(a: v4i32) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(copy_s.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_d(a: v2i64) -> i64 { @@ -3419,7 +3419,7 @@ pub unsafe fn __msa_copy_s_d(a: v2i64) -> i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(copy_u.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_b(a: v16i8) -> u32 { @@ -3434,7 +3434,7 @@ pub unsafe fn __msa_copy_u_b(a: v16i8) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(copy_u.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_h(a: v8i16) -> u32 { @@ -3449,7 +3449,7 @@ pub unsafe fn __msa_copy_u_h(a: v8i16) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(copy_u.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_w(a: v4i32) -> u32 { @@ -3464,7 +3464,7 @@ pub unsafe fn __msa_copy_u_w(a: v4i32) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(copy_u.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_d(a: v2i64) -> u64 { @@ -3481,7 +3481,7 @@ pub unsafe fn __msa_copy_u_d(a: v2i64) -> u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ctcmsa, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(ctcmsa, IMM5 = 0b1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ctcmsa(a: i32) -> () { @@ -5855,7 +5855,7 @@ pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(insert.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_b(a: v16i8, c: i32) -> v16i8 { @@ -5871,7 +5871,7 @@ pub unsafe fn __msa_insert_b(a: v16i8, c: i32) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(insert.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_h(a: v8i16, c: i32) -> v8i16 { @@ -5887,7 +5887,7 @@ pub unsafe fn __msa_insert_h(a: v8i16, c: i32) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(insert.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_w(a: v4i32, c: i32) -> v4i32 { @@ -5903,7 +5903,7 @@ pub unsafe fn __msa_insert_w(a: v4i32, c: i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(insert.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_d(a: v2i64, c: i64) -> v2i64 { @@ -5919,7 +5919,7 @@ pub unsafe fn __msa_insert_d(a: v2i64, c: i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(insve.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_b(a: v16i8, c: v16i8) -> v16i8 { @@ -5935,7 +5935,7 @@ pub unsafe fn __msa_insve_b(a: v16i8, c: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(insve.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_h(a: v8i16, c: v8i16) -> v8i16 { @@ -5951,7 +5951,7 @@ pub unsafe fn __msa_insve_h(a: v8i16, c: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(insve.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_w(a: v4i32, c: v4i32) -> v4i32 { @@ -5967,7 +5967,7 @@ pub unsafe fn __msa_insve_w(a: v4i32, c: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(insve.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_d(a: v2i64, c: v2i64) -> v2i64 { @@ -5983,7 +5983,7 @@ pub unsafe fn __msa_insve_d(a: v2i64, c: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ld.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_b(mem_addr: *mut u8) -> v16i8 { @@ -5999,7 +5999,7 @@ pub unsafe fn __msa_ld_b(mem_addr: *mut u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.h, imm_s11 = 0b11111111111))] +#[cfg_attr(test, assert_instr(ld.h, IMM_S11 = -2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_h(mem_addr: *mut u8) -> v8i16 { @@ -6016,7 +6016,7 @@ pub unsafe fn __msa_ld_h(mem_addr: *mut u8) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.w, imm_s12 = 0b111111111111))] +#[cfg_attr(test, assert_instr(ld.w, IMM_S12 = -4))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_w(mem_addr: *mut u8) -> v4i32 { @@ -6033,7 +6033,7 @@ pub unsafe fn __msa_ld_w(mem_addr: *mut u8) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.d, imm_s13 = 0b1111111111111))] +#[cfg_attr(test, assert_instr(ld.d, IMM_S13 = -8))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_d(mem_addr: *mut u8) -> v2i64 { @@ -6050,7 +6050,7 @@ pub unsafe fn __msa_ld_d(mem_addr: *mut u8) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_b() -> v16i8 { @@ -6066,7 +6066,7 @@ pub unsafe fn __msa_ldi_b() -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.h, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.h, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_h() -> v8i16 { @@ -6082,7 +6082,7 @@ pub unsafe fn __msa_ldi_h() -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.w, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.w, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_w() -> v4i32 { @@ -6098,7 +6098,7 @@ pub unsafe fn __msa_ldi_w() -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.d, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.d, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_d() -> v2i64 { @@ -6410,7 +6410,7 @@ pub unsafe fn __msa_max_u_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_b(a: v16i8) -> v16i8 { @@ -6426,7 +6426,7 @@ pub unsafe fn __msa_maxi_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_h(a: v8i16) -> v8i16 { @@ -6442,7 +6442,7 @@ pub unsafe fn __msa_maxi_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_w(a: v4i32) -> v4i32 { @@ -6458,7 +6458,7 @@ pub unsafe fn __msa_maxi_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_d(a: v2i64) -> v2i64 { @@ -6474,7 +6474,7 @@ pub unsafe fn __msa_maxi_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.b, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_b(a: v16u8) -> v16u8 { @@ -6490,7 +6490,7 @@ pub unsafe fn __msa_maxi_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_h(a: v8u16) -> v8u16 { @@ -6506,7 +6506,7 @@ pub unsafe fn __msa_maxi_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_w(a: v4u32) -> v4u32 { @@ -6522,7 +6522,7 @@ pub unsafe fn __msa_maxi_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_d(a: v2u64) -> v2u64 { @@ -6654,7 +6654,7 @@ pub unsafe fn __msa_min_s_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_b(a: v16i8) -> v16i8 { @@ -6670,7 +6670,7 @@ pub unsafe fn __msa_mini_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_h(a: v8i16) -> v8i16 { @@ -6686,7 +6686,7 @@ pub unsafe fn __msa_mini_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_w(a: v4i32) -> v4i32 { @@ -6702,7 +6702,7 @@ pub unsafe fn __msa_mini_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_d(a: v2i64) -> v2i64 { @@ -6774,7 +6774,7 @@ pub unsafe fn __msa_min_u_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.b, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_b(a: v16u8) -> v16u8 { @@ -6790,7 +6790,7 @@ pub unsafe fn __msa_mini_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_h(a: v8u16) -> v8u16 { @@ -6806,7 +6806,7 @@ pub unsafe fn __msa_mini_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_w(a: v4u32) -> v4u32 { @@ -6822,7 +6822,7 @@ pub unsafe fn __msa_mini_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_d(a: v2u64) -> v2u64 { @@ -7343,7 +7343,7 @@ pub unsafe fn __msa_nor_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(nori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(nori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_nori_b(a: v16u8) -> v16u8 { @@ -7375,7 +7375,7 @@ pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(ori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ori_b(a: v16u8) -> v16u8 { @@ -7555,7 +7555,7 @@ pub unsafe fn __msa_pcnt_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.b, imm4 = 0b111))] +#[cfg_attr(test, assert_instr(sat_s.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_b(a: v16i8) -> v16i8 { @@ -7571,7 +7571,7 @@ pub unsafe fn __msa_sat_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.h, imm3 = 0b1111))] +#[cfg_attr(test, assert_instr(sat_s.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_h(a: v8i16) -> v8i16 { @@ -7587,7 +7587,7 @@ pub unsafe fn __msa_sat_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.w, imm2 = 0b11111))] +#[cfg_attr(test, assert_instr(sat_s.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_w(a: v4i32) -> v4i32 { @@ -7603,7 +7603,7 @@ pub unsafe fn __msa_sat_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.d, imm1 = 0b111111))] +#[cfg_attr(test, assert_instr(sat_s.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_d(a: v2i64) -> v2i64 { @@ -7619,7 +7619,7 @@ pub unsafe fn __msa_sat_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.b, imm4 = 0b111))] +#[cfg_attr(test, assert_instr(sat_u.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_b(a: v16u8) -> v16u8 { @@ -7635,7 +7635,7 @@ pub unsafe fn __msa_sat_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.h, imm3 = 0b1111))] +#[cfg_attr(test, assert_instr(sat_u.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_h(a: v8u16) -> v8u16 { @@ -7651,7 +7651,7 @@ pub unsafe fn __msa_sat_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.w, imm2 = 0b11111))] +#[cfg_attr(test, assert_instr(sat_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_w(a: v4u32) -> v4u32 { @@ -7667,7 +7667,7 @@ pub unsafe fn __msa_sat_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.d, imm1 = 0b111111))] +#[cfg_attr(test, assert_instr(sat_u.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_d(a: v2u64) -> v2u64 { @@ -7684,7 +7684,7 @@ pub unsafe fn __msa_sat_u_d(a: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_b(a: v16i8) -> v16i8 { @@ -7701,7 +7701,7 @@ pub unsafe fn __msa_shf_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.h, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.h, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_h(a: v8i16) -> v8i16 { @@ -7718,7 +7718,7 @@ pub unsafe fn __msa_shf_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.w, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.w, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_w(a: v4i32) -> v4i32 { @@ -7823,7 +7823,7 @@ pub unsafe fn __msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(sldi.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8) -> v16i8 { @@ -7844,7 +7844,7 @@ pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(sldi.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16) -> v8i16 { @@ -7865,7 +7865,7 @@ pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(sldi.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32) -> v4i32 { @@ -7886,7 +7886,7 @@ pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(sldi.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_d(a: v2i64, b: v2i64) -> v2i64 { @@ -7962,7 +7962,7 @@ pub unsafe fn __msa_sll_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(slli.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_b(a: v16i8) -> v16i8 { @@ -7978,7 +7978,7 @@ pub unsafe fn __msa_slli_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(slli.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_h(a: v8i16) -> v8i16 { @@ -7994,7 +7994,7 @@ pub unsafe fn __msa_slli_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(slli.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_w(a: v4i32) -> v4i32 { @@ -8010,7 +8010,7 @@ pub unsafe fn __msa_slli_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(slli.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_d(a: v2i64) -> v2i64 { @@ -8085,7 +8085,7 @@ pub unsafe fn __msa_splat_d(a: v2i64, b: i32) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(splati.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_b(a: v16i8) -> v16i8 { @@ -8100,7 +8100,7 @@ pub unsafe fn __msa_splati_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(splati.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_h(a: v8i16) -> v8i16 { @@ -8115,7 +8115,7 @@ pub unsafe fn __msa_splati_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(splati.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_w(a: v4i32) -> v4i32 { @@ -8130,7 +8130,7 @@ pub unsafe fn __msa_splati_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(splati.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_d(a: v2i64) -> v2i64 { @@ -8206,7 +8206,7 @@ pub unsafe fn __msa_sra_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srai.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_b(a: v16i8) -> v16i8 { @@ -8222,7 +8222,7 @@ pub unsafe fn __msa_srai_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srai.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_h(a: v8i16) -> v8i16 { @@ -8238,7 +8238,7 @@ pub unsafe fn __msa_srai_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srai.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_w(a: v4i32) -> v4i32 { @@ -8254,7 +8254,7 @@ pub unsafe fn __msa_srai_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srai.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_d(a: v2i64) -> v2i64 { @@ -8335,7 +8335,7 @@ pub unsafe fn __msa_srar_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srari.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_b(a: v16i8) -> v16i8 { @@ -8352,7 +8352,7 @@ pub unsafe fn __msa_srari_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srari.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_h(a: v8i16) -> v8i16 { @@ -8369,7 +8369,7 @@ pub unsafe fn __msa_srari_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srari.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_w(a: v4i32) -> v4i32 { @@ -8386,7 +8386,7 @@ pub unsafe fn __msa_srari_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srari.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_d(a: v2i64) -> v2i64 { @@ -8462,7 +8462,7 @@ pub unsafe fn __msa_srl_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srli.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_b(a: v16i8) -> v16i8 { @@ -8478,7 +8478,7 @@ pub unsafe fn __msa_srli_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srli.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_h(a: v8i16) -> v8i16 { @@ -8494,7 +8494,7 @@ pub unsafe fn __msa_srli_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(srli.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_w(a: v4i32) -> v4i32 { @@ -8510,7 +8510,7 @@ pub unsafe fn __msa_srli_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(srli.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_d(a: v2i64) -> v2i64 { @@ -8591,7 +8591,7 @@ pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srlri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_b(a: v16i8) -> v16i8 { @@ -8608,7 +8608,7 @@ pub unsafe fn __msa_srlri_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srlri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_h(a: v8i16) -> v8i16 { @@ -8625,7 +8625,7 @@ pub unsafe fn __msa_srlri_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srlri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_w(a: v4i32) -> v4i32 { @@ -8642,7 +8642,7 @@ pub unsafe fn __msa_srlri_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srlri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_d(a: v2i64) -> v2i64 { @@ -8658,7 +8658,7 @@ pub unsafe fn __msa_srlri_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(st.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8) -> () { @@ -8674,7 +8674,7 @@ pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.h, imm_s11 = 0b11111111111))] +#[cfg_attr(test, assert_instr(st.h, IMM_S11 = -2))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8) -> () { @@ -8691,7 +8691,7 @@ pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.w, imm_s12 = 0b111111111111))] +#[cfg_attr(test, assert_instr(st.w, IMM_S12 = -4))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8) -> () { @@ -8708,7 +8708,7 @@ pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.d, imm_s13 = 0b1111111111111))] +#[cfg_attr(test, assert_instr(st.d, IMM_S13 = -8))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_d(a: v2i64, mem_addr: *mut u8) -> () { @@ -9021,7 +9021,7 @@ pub unsafe fn __msa_subv_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.b, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.b, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_b(a: v16i8) -> v16i8 { @@ -9037,7 +9037,7 @@ pub unsafe fn __msa_subvi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.h, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.h, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_h(a: v8i16) -> v8i16 { @@ -9053,7 +9053,7 @@ pub unsafe fn __msa_subvi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.w, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.w, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_w(a: v4i32) -> v4i32 { @@ -9069,7 +9069,7 @@ pub unsafe fn __msa_subvi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.d, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.d, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_d(a: v2i64) -> v2i64 { @@ -9173,7 +9173,7 @@ pub unsafe fn __msa_xor_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(xori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(xori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_xori_b(a: v16u8) -> v16u8 { @@ -9602,7 +9602,7 @@ mod tests { 103, -126, 103, -126 ); - assert_eq!(r, mem::transmute(__msa_addvi_b(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9618,7 +9618,7 @@ mod tests { -32766, 3279, -97, -124 ); - assert_eq!(r, mem::transmute(__msa_addvi_h(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_h::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9628,7 +9628,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(103, -2147483646, 103, -2147483645); - assert_eq!(r, mem::transmute(__msa_addvi_w(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_w::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9638,7 +9638,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(117, -9223372036854775791); - assert_eq!(r, mem::transmute(__msa_addvi_d(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_addvi_d::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9688,7 +9688,7 @@ mod tests { 4, 5, 4, 5 ); - assert_eq!(r, mem::transmute(__msa_andi_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_andi_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10233,7 +10233,7 @@ mod tests { 247, 147, 55, 1 ); - assert_eq!(r, mem::transmute(__msa_bclri_b(mem::transmute(a), 3))); + assert_eq!(r, mem::transmute(__msa_bclri_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10243,7 +10243,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(107, 1155, 155, 1, 107, 1155, 155, 1); - assert_eq!(r, mem::transmute(__msa_bclri_h(mem::transmute(a), 11))); + assert_eq!(r, mem::transmute(__msa_bclri_h::<11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10253,7 +10253,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(202722547, 102722547, 2722547, 1); - assert_eq!(r, mem::transmute(__msa_bclri_w(mem::transmute(a), 23))); + assert_eq!(r, mem::transmute(__msa_bclri_w::<23>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10263,7 +10263,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(73672157683, 11110973672157683); - assert_eq!(r, mem::transmute(__msa_bclri_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_bclri_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10408,7 +10408,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsli_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_binsli_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -10432,7 +10432,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsli_h(mem::transmute(a), mem::transmute(b), 13)) + mem::transmute(__msa_binsli_h::<13>(mem::transmute(a), mem::transmute(b))) ); } @@ -10447,7 +10447,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsli_w(mem::transmute(a), mem::transmute(b), 17)) + mem::transmute(__msa_binsli_w::<17>(mem::transmute(a), mem::transmute(b))) ); } @@ -10462,7 +10462,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsli_d(mem::transmute(a), mem::transmute(b), 48)) + mem::transmute(__msa_binsli_d::<48>(mem::transmute(a), mem::transmute(b))) ); } @@ -10608,7 +10608,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsri_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_binsri_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -10632,7 +10632,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsri_h(mem::transmute(a), mem::transmute(b), 13)) + mem::transmute(__msa_binsri_h::<13>(mem::transmute(a), mem::transmute(b))) ); } @@ -10647,7 +10647,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsri_w(mem::transmute(a), mem::transmute(b), 17)) + mem::transmute(__msa_binsri_w::<17>(mem::transmute(a), mem::transmute(b))) ); } @@ -10662,7 +10662,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_binsri_d(mem::transmute(a), mem::transmute(b), 48)) + mem::transmute(__msa_binsri_d::<48>(mem::transmute(a), mem::transmute(b))) ); } @@ -10733,7 +10733,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_bmnzi_b(mem::transmute(a), mem::transmute(b), 7)) + mem::transmute(__msa_bmnzi_b::<7>(mem::transmute(a), mem::transmute(b))) ); } @@ -10804,7 +10804,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_bmzi_b(mem::transmute(a), mem::transmute(b), 7)) + mem::transmute(__msa_bmzi_b::<7>(mem::transmute(a), mem::transmute(b))) ); } @@ -10900,7 +10900,7 @@ mod tests { 34, 116, 111, 239 ); - assert_eq!(r, mem::transmute(__msa_bnegi_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_bnegi_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10916,7 +10916,7 @@ mod tests { 30719, 1228, 2148, 2175 ); - assert_eq!(r, mem::transmute(__msa_bnegi_h(mem::transmute(a), 11))); + assert_eq!(r, mem::transmute(__msa_bnegi_h::<11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10926,7 +10926,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(16777316, 2130706431, 16777316, 2164260864); - assert_eq!(r, mem::transmute(__msa_bnegi_w(mem::transmute(a), 24))); + assert_eq!(r, mem::transmute(__msa_bnegi_w::<24>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10936,7 +10936,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(4398046511204, 9223376434901286912); - assert_eq!(r, mem::transmute(__msa_bnegi_d(mem::transmute(a), 42))); + assert_eq!(r, mem::transmute(__msa_bnegi_d::<42>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11065,7 +11065,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_bseli_b(mem::transmute(a), mem::transmute(b), 121)) + mem::transmute(__msa_bseli_b::<121>(mem::transmute(a), mem::transmute(b))) ); } @@ -11161,7 +11161,7 @@ mod tests { 255, 159, 55, 5 ); - assert_eq!(r, mem::transmute(__msa_bseti_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11171,7 +11171,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(255, 159, 55, 5, 255, 159, 55, 5); - assert_eq!(r, mem::transmute(__msa_bseti_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11181,7 +11181,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(255, 159, 55, 5); - assert_eq!(r, mem::transmute(__msa_bseti_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11191,7 +11191,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(255, 159); - assert_eq!(r, mem::transmute(__msa_bseti_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11341,7 +11341,7 @@ mod tests { 0, 0, -1, 0 ); - assert_eq!(r, mem::transmute(__msa_ceqi_b(mem::transmute(a), -4))); + assert_eq!(r, mem::transmute(__msa_ceqi_b::<-4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11354,7 +11354,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1); - assert_eq!(r, mem::transmute(__msa_ceqi_h(mem::transmute(a), -11))); + assert_eq!(r, mem::transmute(__msa_ceqi_h::<-11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11364,7 +11364,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(0, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_ceqi_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_ceqi_w::<5>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11551,7 +11551,7 @@ mod tests { #[rustfmt::skip] let r = i8x16::new(-1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1); - assert_eq!(r, mem::transmute(__msa_clei_s_b(mem::transmute(a), -2))); + assert_eq!(r, mem::transmute(__msa_clei_s_b::<-2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11564,7 +11564,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1); - assert_eq!(r, mem::transmute(__msa_clei_s_h(mem::transmute(a), -1))); + assert_eq!(r, mem::transmute(__msa_clei_s_h::<-1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11574,7 +11574,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(0, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_s_w(mem::transmute(a), 6))); + assert_eq!(r, mem::transmute(__msa_clei_s_w::<6>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11607,7 +11607,7 @@ mod tests { -1, 0, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clei_u_b(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_b::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11620,7 +11620,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(-1, 0, -1, 0, -1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_h(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_h::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11630,7 +11630,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(-1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_w(mem::transmute(a), 31))); + assert_eq!(r, mem::transmute(__msa_clei_u_w::<31>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11640,7 +11640,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(-1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_d(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_d::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11810,7 +11810,7 @@ mod tests { 0, -1, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clti_s_b(mem::transmute(a), -5))); + assert_eq!(r, mem::transmute(__msa_clti_s_b::<-5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11823,7 +11823,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(-1, 0, 0, 0, -1, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_s_h(mem::transmute(a), 15))); + assert_eq!(r, mem::transmute(__msa_clti_s_h::<15>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11833,7 +11833,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(-1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clti_s_w(mem::transmute(a), -10))); + assert_eq!(r, mem::transmute(__msa_clti_s_w::<-10>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11866,7 +11866,7 @@ mod tests { -1, 0, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clti_u_b(mem::transmute(a), 50))); + assert_eq!(r, mem::transmute(__msa_clti_u_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11879,7 +11879,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_h(mem::transmute(a), 30))); + assert_eq!(r, mem::transmute(__msa_clti_u_h::<30>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11889,7 +11889,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(0, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_w(mem::transmute(a), 10))); + assert_eq!(r, mem::transmute(__msa_clti_u_w::<10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11899,7 +11899,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(-1, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_d(mem::transmute(a), 10))); + assert_eq!(r, mem::transmute(__msa_clti_u_d::<10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11914,7 +11914,7 @@ mod tests { #[rustfmt::skip] let r = -100 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_b(mem::transmute(a), 12))); + assert_eq!(r, mem::transmute(__msa_copy_s_b::<12>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11927,7 +11927,7 @@ mod tests { #[rustfmt::skip] let r = 32767 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_h(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_copy_s_h::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11936,7 +11936,7 @@ mod tests { let a = i32x4::new(100, 2147483647, 5, -2147483647); let r = 2147483647 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_w(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_s_w::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11946,7 +11946,7 @@ mod tests { #[rustfmt::skip] let r = 9223372036854775807 as i64; - assert_eq!(r, mem::transmute(__msa_copy_s_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_s_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11961,7 +11961,7 @@ mod tests { #[rustfmt::skip] let r = 100 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_b(mem::transmute(a), 12))); + assert_eq!(r, mem::transmute(__msa_copy_u_b::<12>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11974,7 +11974,7 @@ mod tests { #[rustfmt::skip] let r = 32767 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_h(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_copy_u_h::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11984,7 +11984,7 @@ mod tests { #[rustfmt::skip] let r = 2147483647 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_w(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_u_w::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11994,7 +11994,7 @@ mod tests { #[rustfmt::skip] let r = 9223372036854775807 as u64; - assert_eq!(r, mem::transmute(__msa_copy_u_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_u_d::<1>(mem::transmute(a)))); } // Can not be tested in user mode @@ -14618,7 +14618,10 @@ mod tests { 5, 127, 4, 127 ); - assert_eq!(r, mem::transmute(__msa_insert_b(mem::transmute(a), 12, 5))); + assert_eq!( + r, + mem::transmute(__msa_insert_b::<12>(mem::transmute(a), 5)) + ); } #[simd_test(enable = "msa")] @@ -14634,7 +14637,7 @@ mod tests { 5, 3276, 100, 11 ); - assert_eq!(r, mem::transmute(__msa_insert_h(mem::transmute(a), 4, 5))); + assert_eq!(r, mem::transmute(__msa_insert_h::<4>(mem::transmute(a), 5))); } #[simd_test(enable = "msa")] @@ -14644,7 +14647,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(100, 7, 5, -2147483647); - assert_eq!(r, mem::transmute(__msa_insert_w(mem::transmute(a), 1, 7))); + assert_eq!(r, mem::transmute(__msa_insert_w::<1>(mem::transmute(a), 7))); } #[simd_test(enable = "msa")] @@ -14654,7 +14657,10 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(3, 100); - assert_eq!(r, mem::transmute(__msa_insert_d(mem::transmute(a), 1, 100))); + assert_eq!( + r, + mem::transmute(__msa_insert_d::<1>(mem::transmute(a), 100)) + ); } #[simd_test(enable = "msa")] @@ -14683,7 +14689,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_insve_b(mem::transmute(a), 12, mem::transmute(b))) + mem::transmute(__msa_insve_b::<12>(mem::transmute(a), mem::transmute(b))) ); } @@ -14707,7 +14713,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_insve_h(mem::transmute(a), 4, mem::transmute(b))) + mem::transmute(__msa_insve_h::<4>(mem::transmute(a), mem::transmute(b))) ); } @@ -14722,7 +14728,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_insve_w(mem::transmute(a), 3, mem::transmute(b))) + mem::transmute(__msa_insve_w::<3>(mem::transmute(a), mem::transmute(b))) ); } @@ -14737,7 +14743,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_insve_d(mem::transmute(a), 1, mem::transmute(b))) + mem::transmute(__msa_insve_d::<1>(mem::transmute(a), mem::transmute(b))) ); } @@ -14759,7 +14765,7 @@ mod tests { 25, 26, 27, 28 ); - assert_eq!(r, mem::transmute(__msa_ld_b(p, 9))); + assert_eq!(r, mem::transmute(__msa_ld_b::<9>(p))); } #[simd_test(enable = "msa")] @@ -14773,7 +14779,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(3, 4, 5, 6, 7, 8, 9, 10); - assert_eq!(r, mem::transmute(__msa_ld_h(p, -2))); + assert_eq!(r, mem::transmute(__msa_ld_h::<-2>(p))); } #[simd_test(enable = "msa")] @@ -14784,7 +14790,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(2, 3, 4, 5); - assert_eq!(r, mem::transmute(__msa_ld_w(p, -4))); + assert_eq!(r, mem::transmute(__msa_ld_w::<-4>(p))); } #[simd_test(enable = "msa")] @@ -14795,7 +14801,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(0, 1); - assert_eq!(r, mem::transmute(__msa_ld_d(p, -32))); + assert_eq!(r, mem::transmute(__msa_ld_d::<-32>(p))); } #[simd_test(enable = "msa")] @@ -14808,7 +14814,7 @@ mod tests { -20, -20, -20, -20 ); - assert_eq!(r, mem::transmute(__msa_ldi_b(-20))); + assert_eq!(r, mem::transmute(__msa_ldi_b::<-20>())); } #[simd_test(enable = "msa")] @@ -14819,7 +14825,7 @@ mod tests { 255, 255, 255, 255 ); - assert_eq!(r, mem::transmute(__msa_ldi_h(255))); + assert_eq!(r, mem::transmute(__msa_ldi_h::<255>())); } #[simd_test(enable = "msa")] @@ -14827,7 +14833,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(-509, -509, -509, -509); - assert_eq!(r, mem::transmute(__msa_ldi_w(-509))); + assert_eq!(r, mem::transmute(__msa_ldi_w::<-509>())); } // FIXME: https://reviews.llvm.org/D59884 @@ -15288,7 +15294,7 @@ mod tests { 1, -16, -6, 8 ); - assert_eq!(r, mem::transmute(__msa_maxi_s_b(mem::transmute(a), -16))); + assert_eq!(r, mem::transmute(__msa_maxi_s_b::<-16>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15298,7 +15304,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(15, 15, 15, 15, 15, 15, 15, 15); - assert_eq!(r, mem::transmute(__msa_maxi_s_h(mem::transmute(a), 15))); + assert_eq!(r, mem::transmute(__msa_maxi_s_h::<15>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15308,7 +15314,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(1, 3, -5, -5); - assert_eq!(r, mem::transmute(__msa_maxi_s_w(mem::transmute(a), -5))); + assert_eq!(r, mem::transmute(__msa_maxi_s_w::<-5>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -15341,7 +15347,7 @@ mod tests { 5, 5, 6, 8 ); - assert_eq!(r, mem::transmute(__msa_maxi_u_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15351,7 +15357,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(5, 5, 6, 8, 5, 5, 6, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15361,7 +15367,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(5, 5, 6, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15371,7 +15377,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(5, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15541,7 +15547,7 @@ mod tests { -10, -10, -10, -10 ); - assert_eq!(r, mem::transmute(__msa_mini_s_b(mem::transmute(a), -10))); + assert_eq!(r, mem::transmute(__msa_mini_s_b::<-10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15551,7 +15557,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(-3, -3, -3, -4, -3, -3, -3, -4); - assert_eq!(r, mem::transmute(__msa_mini_s_h(mem::transmute(a), -3))); + assert_eq!(r, mem::transmute(__msa_mini_s_h::<-3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15561,7 +15567,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(-3, -3, -3, -4); - assert_eq!(r, mem::transmute(__msa_mini_s_w(mem::transmute(a), -3))); + assert_eq!(r, mem::transmute(__msa_mini_s_w::<-3>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -15669,7 +15675,7 @@ mod tests { 1, 3, 5, 5 ); - assert_eq!(r, mem::transmute(__msa_mini_u_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15679,7 +15685,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(1, 3, 5, 5, 1, 3, 5, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15689,7 +15695,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(1, 3, 5, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15699,7 +15705,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(1, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16393,7 +16399,7 @@ mod tests { 242, 241, 240, 235 ); - assert_eq!(r, mem::transmute(__msa_nori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_nori_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16443,7 +16449,7 @@ mod tests { 13, 14, 15, 20 ); - assert_eq!(r, mem::transmute(__msa_ori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_ori_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16669,7 +16675,7 @@ mod tests { 3, 3, 3, 1 ); - assert_eq!(r, mem::transmute(__msa_sat_s_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_sat_s_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16682,7 +16688,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(127, 127, 127, 1, 127, 127, 127, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_h(mem::transmute(a), 7))); + assert_eq!(r, mem::transmute(__msa_sat_s_h::<7>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16692,7 +16698,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(131071, 131071, 131071, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_w(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_sat_s_w::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16702,7 +16708,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(137438953471, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_sat_s_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16722,7 +16728,7 @@ mod tests { 7, 7, 7, 1 ); - assert_eq!(r, mem::transmute(__msa_sat_u_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_sat_u_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16735,7 +16741,7 @@ mod tests { #[rustfmt::skip] let r = u16x8::new(255, 255, 155, 1, 255, 255, 155, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_h(mem::transmute(a), 7))); + assert_eq!(r, mem::transmute(__msa_sat_u_h::<7>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16745,7 +16751,7 @@ mod tests { #[rustfmt::skip] let r = u32x4::new(262143, 262143, 262143, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_w(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_sat_u_w::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16755,7 +16761,7 @@ mod tests { #[rustfmt::skip] let r = u64x2::new(274877906943, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_sat_u_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16775,7 +16781,7 @@ mod tests { 11, 3, 4, 12 ); - assert_eq!(r, mem::transmute(__msa_shf_b(mem::transmute(a), 120))); + assert_eq!(r, mem::transmute(__msa_shf_b::<120>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16788,7 +16794,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(11, 14, 12, 13, 11, 14, 12, 13); - assert_eq!(r, mem::transmute(__msa_shf_h(mem::transmute(a), 156))); + assert_eq!(r, mem::transmute(__msa_shf_h::<156>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16798,7 +16804,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(1, 3, 2, 4); - assert_eq!(r, mem::transmute(__msa_shf_w(mem::transmute(a), 216))); + assert_eq!(r, mem::transmute(__msa_shf_w::<216>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16902,7 +16908,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_sldi_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_sldi_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -16917,7 +16923,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_sldi_h(mem::transmute(a), mem::transmute(b), 2)) + mem::transmute(__msa_sldi_h::<2>(mem::transmute(a), mem::transmute(b))) ); } @@ -16932,7 +16938,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_sldi_w(mem::transmute(a), mem::transmute(b), 4)) + mem::transmute(__msa_sldi_w::<0>(mem::transmute(a), mem::transmute(b))) ); } @@ -16947,7 +16953,7 @@ mod tests { assert_eq!( r, - mem::transmute(__msa_sldi_d(mem::transmute(a), mem::transmute(b), 2)) + mem::transmute(__msa_sldi_d::<0>(mem::transmute(a), mem::transmute(b))) ); } @@ -17043,7 +17049,7 @@ mod tests { 4, 8, 12, 16 ); - assert_eq!(r, mem::transmute(__msa_slli_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17056,7 +17062,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(4, 8, 12, 16, 4, 8, 12, 16); - assert_eq!(r, mem::transmute(__msa_slli_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17066,7 +17072,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(4, 8, 12, 16); - assert_eq!(r, mem::transmute(__msa_slli_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17076,7 +17082,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(2, 4); - assert_eq!(r, mem::transmute(__msa_slli_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_slli_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17149,7 +17155,7 @@ mod tests { 3, 3, 3, 3 ); - assert_eq!(r, mem::transmute(__msa_splati_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17162,7 +17168,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - assert_eq!(r, mem::transmute(__msa_splati_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17172,7 +17178,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(3, 3, 3, 3); - assert_eq!(r, mem::transmute(__msa_splati_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17182,7 +17188,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(2, 2); - assert_eq!(r, mem::transmute(__msa_splati_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_splati_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17286,7 +17292,7 @@ mod tests { 31, 31, 13, 0 ); - assert_eq!(r, mem::transmute(__msa_srai_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17299,7 +17305,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(8191, 31, 13, 0, 8191, 31, 13, 0); - assert_eq!(r, mem::transmute(__msa_srai_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17308,7 +17314,7 @@ mod tests { let a = i32x4::new(i32::MAX, 125, 55, 1); let r = i32x4::new(536870911, 31, 13, 0); - assert_eq!(r, mem::transmute(__msa_srai_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17318,7 +17324,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(2305843009213693951, 13); - assert_eq!(r, mem::transmute(__msa_srai_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17422,7 +17428,7 @@ mod tests { 31, 32, 14, 0 ); - assert_eq!(r, mem::transmute(__msa_srari_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17432,7 +17438,7 @@ mod tests { #[rustfmt::skip] let r = i16x8::new(539, 289, 39, 0, 539, 289, 39, 0); - assert_eq!(r, mem::transmute(__msa_srari_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17442,7 +17448,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(52777789, 27777789, 2777789, 0); - assert_eq!(r, mem::transmute(__msa_srari_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17452,7 +17458,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(52777777789, 27777777789); - assert_eq!(r, mem::transmute(__msa_srari_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17553,7 +17559,7 @@ mod tests { 6, 12, 25, 31 ); - assert_eq!(r, mem::transmute(__msa_srli_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17569,7 +17575,7 @@ mod tests { 8191, 819, 25, 31 ); - assert_eq!(r, mem::transmute(__msa_srli_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17579,7 +17585,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(25, 536870911, 25, 536870911); - assert_eq!(r, mem::transmute(__msa_srli_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17589,7 +17595,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(50, 4611686018427387903); - assert_eq!(r, mem::transmute(__msa_srli_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_srli_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17689,7 +17695,7 @@ mod tests { 6, 13, 25, 32 ); - assert_eq!(r, mem::transmute(__msa_srlri_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17701,7 +17707,7 @@ mod tests { ); let r = i16x8::new(8192, 819, 25, 32, 8192, 819, 25, 32); - assert_eq!(r, mem::transmute(__msa_srlri_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17711,7 +17717,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(25, 38, 50, 536870912); - assert_eq!(r, mem::transmute(__msa_srlri_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17721,7 +17727,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(50, 4611686018427387904); - assert_eq!(r, mem::transmute(__msa_srlri_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_srlri_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17747,7 +17753,7 @@ mod tests { 21, 22, 23, 24, 25, 26, 27, 28 ]; - __msa_st_b(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_b::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17758,7 +17764,7 @@ mod tests { let mut arr: [i16; 8] = [0, 0, 0, 0, 0, 0, 0, 0]; #[rustfmt::skip] let r : [i16; 8] = [13, 14, 15, 16, 17, 18, 19, 20]; - __msa_st_h(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_h::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17769,7 +17775,7 @@ mod tests { let mut arr: [i32; 4] = [0, 0, 0, 0]; #[rustfmt::skip] let r : [i32; 4] = [13, 14, 15, 16]; - __msa_st_w(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_w::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17780,7 +17786,7 @@ mod tests { let mut arr: [i64; 2] = [0, 0]; #[rustfmt::skip] let r : [i64; 2] = [13, 14]; - __msa_st_d(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_d::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -18194,7 +18200,7 @@ mod tests { 95, 122, 45, 123 ); - assert_eq!(r, mem::transmute(__msa_subvi_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18210,7 +18216,7 @@ mod tests { 32762, 3271, -105, 32763 ); - assert_eq!(r, mem::transmute(__msa_subvi_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18220,7 +18226,7 @@ mod tests { #[rustfmt::skip] let r = i32x4::new(95, 145, 195, 2147483642); - assert_eq!(r, mem::transmute(__msa_subvi_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18230,7 +18236,7 @@ mod tests { #[rustfmt::skip] let r = i64x2::new(95, 9223372036854775802); - assert_eq!(r, mem::transmute(__msa_subvi_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18392,6 +18398,6 @@ mod tests { 9, 10, 11, 20 ); - assert_eq!(r, mem::transmute(__msa_xori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_xori_b::<4>(mem::transmute(a)))); } } diff --git a/stdarch/crates/core_arch/src/nvptx/mod.rs b/stdarch/crates/core_arch/src/nvptx/mod.rs index 5471ef819801e..b63a5d01a7a22 100644 --- a/stdarch/crates/core_arch/src/nvptx/mod.rs +++ b/stdarch/crates/core_arch/src/nvptx/mod.rs @@ -49,6 +49,8 @@ unsafe extern "C" { } /// Synchronizes all threads in the block. +/// +#[doc = include_str!("../amdgpu/intrinsic_is_convergent.md")] #[inline] #[unstable(feature = "stdarch_nvptx", issue = "111199")] pub unsafe fn _syncthreads() -> () { diff --git a/stdarch/crates/core_arch/src/powerpc/altivec.rs b/stdarch/crates/core_arch/src/powerpc/altivec.rs index f68121ad31716..78ec39f91ff33 100644 --- a/stdarch/crates/core_arch/src/powerpc/altivec.rs +++ b/stdarch/crates/core_arch/src/powerpc/altivec.rs @@ -4700,10 +4700,10 @@ mod tests { { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] fn $name() { - let a: s_t_l!($ty) = $ty::new($($a),+).into(); - let b: s_t_l!($ty) = $ty::new($($b),+).into(); + let a: s_t_l!($ty) = $ty::from_array([$($a),+]).into(); + let b: s_t_l!($ty) = $ty::from_array([$($b),+]).into(); - let d = $ty_out::new($($d),+); + let d = $ty_out::from_array([$($d),+]); let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!(d, r); } @@ -4711,8 +4711,8 @@ mod tests { { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => { #[simd_test(enable = "altivec")] fn $name() { - let a: s_t_l!($ty) = $ty::new($($a),+).into(); - let b: s_t_l!($ty) = $ty::new($($b),+).into(); + let a: s_t_l!($ty) = $ty::from_array([$($a),+]).into(); + let b: s_t_l!($ty) = $ty::from_array([$($b),+]).into(); let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!($d, r); @@ -4728,7 +4728,7 @@ mod tests { let d = vector_float::from(f32x4::new($($d),+)); let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) }); - let e = m32x4::new(true, true, true, true); + let e = m32x4::splat(true); assert_eq!(e, r); } }; @@ -6212,10 +6212,10 @@ mod tests { [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "altivec")] fn $name() { - let a = $longtype::from($shorttype::new($($a),+)); - let b = $longtype::from($shorttype::new($($b),+)); - let c = vector_unsigned_char::from(u8x16::new($($c),+)); - let d = $shorttype::new($($d),+); + let a = $longtype::from($shorttype::from_array([$($a),+])); + let b = $longtype::from($shorttype::from_array([$($b),+])); + let c = vector_unsigned_char::from(u8x16::from_array([$($c),+])); + let d = $shorttype::from_array([$($d),+]); let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); @@ -6664,7 +6664,7 @@ mod tests { let check = |a, b| { let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); - let e = m32x4::new(true, true, true, true); + let e = m32x4::splat(true); assert_eq!(e, r); }; @@ -6720,7 +6720,7 @@ mod tests { let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); println!("{:?} {:?}", a, b); - let e = m32x4::new(true, true, true, true); + let e = m32x4::splat(true); assert_eq!(e, r); }; diff --git a/stdarch/crates/core_arch/src/powerpc/vsx.rs b/stdarch/crates/core_arch/src/powerpc/vsx.rs index 0aac236173401..4a7b561a20c55 100644 --- a/stdarch/crates/core_arch/src/powerpc/vsx.rs +++ b/stdarch/crates/core_arch/src/powerpc/vsx.rs @@ -238,14 +238,14 @@ mod tests { {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vsx")] fn $name() { - let a = $longtype::from($shorttype::new($($a),+, $($b),+)); - let b = $longtype::from($shorttype::new($($c),+, $($d),+)); + let a = $longtype::from($shorttype::from_array([$($a),+, $($b),+])); + let b = $longtype::from($shorttype::from_array([$($c),+, $($d),+])); unsafe { - assert_eq!($shorttype::new($($a),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 0>(a, b))); - assert_eq!($shorttype::new($($b),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 1>(a, b))); - assert_eq!($shorttype::new($($a),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 2>(a, b))); - assert_eq!($shorttype::new($($b),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 3>(a, b))); + assert_eq!($shorttype::from_array([$($a),+, $($c),+]), $shorttype::from(vec_xxpermdi::<_, 0>(a, b))); + assert_eq!($shorttype::from_array([$($b),+, $($c),+]), $shorttype::from(vec_xxpermdi::<_, 1>(a, b))); + assert_eq!($shorttype::from_array([$($a),+, $($d),+]), $shorttype::from(vec_xxpermdi::<_, 2>(a, b))); + assert_eq!($shorttype::from_array([$($b),+, $($d),+]), $shorttype::from(vec_xxpermdi::<_, 3>(a, b))); } } } diff --git a/stdarch/crates/core_arch/src/s390x/vector.rs b/stdarch/crates/core_arch/src/s390x/vector.rs index 376c912c04090..fc5af1b14d0cd 100644 --- a/stdarch/crates/core_arch/src/s390x/vector.rs +++ b/stdarch/crates/core_arch/src/s390x/vector.rs @@ -6463,10 +6463,10 @@ mod tests { [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vector")] fn $name() { - let a = $longtype::from($shorttype::new($($a),+)); - let b = $longtype::from($shorttype::new($($b),+)); - let c = vector_unsigned_char::from(u8x16::new($($c),+)); - let d = $shorttype::new($($d),+); + let a = $longtype::from($shorttype::from_array([$($a),+])); + let b = $longtype::from($shorttype::from_array([$($b),+])); + let c = vector_unsigned_char::from(u8x16::from_array([$($c),+])); + let d = $shorttype::from_array([$($d),+]); let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); diff --git a/stdarch/crates/core_arch/src/simd.rs b/stdarch/crates/core_arch/src/simd.rs index 313c474792036..9a756eee446d2 100644 --- a/stdarch/crates/core_arch/src/simd.rs +++ b/stdarch/crates/core_arch/src/simd.rs @@ -20,6 +20,8 @@ pub(crate) const unsafe fn simd_imin(a: T, b: T) -> T { pub(crate) unsafe trait SimdElement: Copy + const PartialEq + crate::fmt::Debug { + // SAFETY: all bits patterns of types implementing this trait must be valid + const ZERO: Self = unsafe { crate::mem::zeroed() }; } unsafe impl SimdElement for u8 {} @@ -42,8 +44,7 @@ pub(crate) struct Simd([T; N]); impl Simd { /// A value of this type where all elements are zeroed out. - // SAFETY: `T` implements `SimdElement`, so it is zeroable. - pub(crate) const ZERO: Self = unsafe { crate::mem::zeroed() }; + pub(crate) const ZERO: Self = Self::splat(T::ZERO); #[inline(always)] pub(crate) const fn from_array(elements: [T; N]) -> Self { @@ -86,6 +87,7 @@ impl Clone for Simd { } #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustfmt::skip] // FIXME: https://github.com/rust-lang/stdarch/pull/2133#issuecomment-4524350350 impl const crate::cmp::PartialEq for Simd { #[inline] fn eq(&self, other: &Self) -> bool { @@ -100,6 +102,103 @@ impl crate::fmt::Debug for Simd { } } +impl Simd { + #[inline] + pub(crate) const fn new(x0: T) -> Self { + Self([x0]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T) -> Self { + Self([x0, x1]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T, x2: T, x3: T) -> Self { + Self([x0, x1, x2, x3]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T, x2: T, x3: T, x4: T, x5: T, x6: T, x7: T) -> Self { + Self([x0, x1, x2, x3, x4, x5, x6, x7]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new( + x0: T, + x1: T, + x2: T, + x3: T, + x4: T, + x5: T, + x6: T, + x7: T, + x8: T, + x9: T, + x10: T, + x11: T, + x12: T, + x13: T, + x14: T, + x15: T, + ) -> Self { + Self([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, + ]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new( + x0: T, + x1: T, + x2: T, + x3: T, + x4: T, + x5: T, + x6: T, + x7: T, + x8: T, + x9: T, + x10: T, + x11: T, + x12: T, + x13: T, + x14: T, + x15: T, + x16: T, + x17: T, + x18: T, + x19: T, + x20: T, + x21: T, + x22: T, + x23: T, + x24: T, + x25: T, + x26: T, + x27: T, + x28: T, + x29: T, + x30: T, + x31: T, + ) -> Self { + Self([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, + x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, + ]) + } +} + impl Simd { #[inline] pub(crate) const fn to_bits(self) -> Simd { @@ -142,19 +241,6 @@ impl Simd { } } -macro_rules! simd_ty { - ($id:ident [$elem_type:ty ; $len:literal]: $($param_name:ident),*) => { - pub(crate) type $id = Simd<$elem_type, $len>; - - impl $id { - #[inline(always)] - pub(crate) const fn new($($param_name: $elem_type),*) -> Self { - Self([$($param_name),*]) - } - } - } -} - #[repr(simd)] #[derive(Copy)] pub(crate) struct SimdM([T; N]); @@ -163,7 +249,6 @@ impl SimdM { #[inline(always)] const fn bool_to_internal(x: bool) -> T { // SAFETY: `T` implements `SimdElement`, so all bit patterns are valid. - let zeros = const { unsafe { crate::mem::zeroed::() } }; let ones = const { // Ideally, this would be `transmute([0xFFu8; size_of::()])`, but // `size_of::()` is not allowed to use a generic parameter there. @@ -175,13 +260,24 @@ impl SimdM { } unsafe { r.assume_init() } }; - [zeros, ones][x as usize] + [T::ZERO, ones][x as usize] + } + + #[inline] + pub(crate) const fn from_array(elements: [bool; N]) -> Self { + let mut internal = [T::ZERO; N]; + let mut i = 0; + while i < N { + internal[i] = Self::bool_to_internal(elements[i]); + i += 1; + } + Self(internal) } #[inline] #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] pub(crate) const fn splat(value: bool) -> Self { - unsafe { crate::intrinsics::simd::simd_splat(value) } + unsafe { crate::intrinsics::simd::simd_splat(Self::bool_to_internal(value)) } } #[inline] @@ -204,6 +300,7 @@ impl Clone for SimdM { } #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustfmt::skip] // FIXME: https://github.com/rust-lang/stdarch/pull/2133#issuecomment-4524350350 impl const crate::cmp::PartialEq for SimdM { #[inline] fn eq(&self, other: &Self) -> bool { @@ -218,897 +315,98 @@ impl crate::fmt::Debug for SimdM { } } -macro_rules! simd_m_ty { - ($id:ident [$elem_type:ident ; $len:literal]: $($param_name:ident),*) => { - pub(crate) type $id = SimdM<$elem_type, $len>; - - impl $id { - #[inline(always)] - pub(crate) const fn new($($param_name: bool),*) -> Self { - Self([$(Self::bool_to_internal($param_name)),*]) - } - } - } -} - // 16-bit wide types: -simd_ty!(u8x2[u8;2]: x0, x1); -simd_ty!(i8x2[i8;2]: x0, x1); +pub(crate) type u8x2 = Simd; +pub(crate) type i8x2 = Simd; // 32-bit wide types: -simd_ty!(u8x4[u8;4]: x0, x1, x2, x3); -simd_ty!(u16x2[u16;2]: x0, x1); +pub(crate) type u8x4 = Simd; +pub(crate) type u16x2 = Simd; -simd_ty!(i8x4[i8;4]: x0, x1, x2, x3); -simd_ty!(i16x2[i16;2]: x0, x1); +pub(crate) type i8x4 = Simd; +pub(crate) type i16x2 = Simd; // 64-bit wide types: -simd_ty!( - u8x8[u8;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u16x4[u16;4]: x0, x1, x2, x3); -simd_ty!(u32x2[u32;2]: x0, x1); -simd_ty!(u64x1[u64;1]: x1); +pub(crate) type u8x8 = Simd; +pub(crate) type u16x4 = Simd; +pub(crate) type u32x2 = Simd; +pub(crate) type u64x1 = Simd; -simd_ty!( - i8x8[i8;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i16x4[i16;4]: x0, x1, x2, x3); -simd_ty!(i32x2[i32;2]: x0, x1); -simd_ty!(i64x1[i64;1]: x1); +pub(crate) type i8x8 = Simd; +pub(crate) type i16x4 = Simd; +pub(crate) type i32x2 = Simd; +pub(crate) type i64x1 = Simd; -simd_ty!(f32x2[f32;2]: x0, x1); -simd_ty!(f64x1[f64;1]: x1); +pub(crate) type f16x4 = Simd; +pub(crate) type f32x2 = Simd; +pub(crate) type f64x1 = Simd; // 128-bit wide types: -simd_ty!( - u8x16[u8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - u16x8[u16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u32x4[u32;4]: x0, x1, x2, x3); -simd_ty!(u64x2[u64;2]: x0, x1); - -simd_ty!( - i8x16[i8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - i16x8[i16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i32x4[i32;4]: x0, x1, x2, x3); -simd_ty!(i64x2[i64;2]: x0, x1); +pub(crate) type u8x16 = Simd; +pub(crate) type u16x8 = Simd; +pub(crate) type u32x4 = Simd; +pub(crate) type u64x2 = Simd; -simd_ty!(f16x4[f16;4]: x0, x1, x2, x3); +pub(crate) type i8x16 = Simd; +pub(crate) type i16x8 = Simd; +pub(crate) type i32x4 = Simd; +pub(crate) type i64x2 = Simd; -simd_ty!( - f16x8[f16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(f32x4[f32;4]: x0, x1, x2, x3); -simd_ty!(f64x2[f64;2]: x0, x1); +pub(crate) type f16x8 = Simd; +pub(crate) type f32x4 = Simd; +pub(crate) type f64x2 = Simd; -simd_m_ty!( - m8x16[i8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_m_ty!( - m16x8[i16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_m_ty!(m32x4[i32;4]: x0, x1, x2, x3); -simd_m_ty!(m64x2[i64;2]: x0, x1); +pub(crate) type m8x16 = SimdM; +pub(crate) type m16x8 = SimdM; +pub(crate) type m32x4 = SimdM; +pub(crate) type m64x2 = SimdM; // 256-bit wide types: -simd_ty!( - u8x32[u8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - u16x16[u16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - u32x8[u32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u64x4[u64;4]: x0, x1, x2, x3); +pub(crate) type u8x32 = Simd; +pub(crate) type u16x16 = Simd; +pub(crate) type u32x8 = Simd; +pub(crate) type u64x4 = Simd; -simd_ty!( - i8x32[i8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - i16x16[i16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - i32x8[i32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i64x4[i64;4]: x0, x1, x2, x3); +pub(crate) type i8x32 = Simd; +pub(crate) type i16x16 = Simd; +pub(crate) type i32x8 = Simd; +pub(crate) type i64x4 = Simd; -simd_ty!( - f16x16[f16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - f32x8[f32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(f64x4[f64;4]: x0, x1, x2, x3); +pub(crate) type f16x16 = Simd; +pub(crate) type f32x8 = Simd; +pub(crate) type f64x4 = Simd; -simd_m_ty!( - m8x32[i8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_m_ty!( - m16x16[i16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_m_ty!( - m32x8[i32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); +pub(crate) type m8x32 = SimdM; +pub(crate) type m16x16 = SimdM; +pub(crate) type m32x8 = SimdM; // 512-bit wide types: -simd_ty!( - i8x64[i8;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); - -simd_ty!( - u8x64[u8;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); +pub(crate) type u8x64 = Simd; +pub(crate) type u16x32 = Simd; +pub(crate) type u32x16 = Simd; +pub(crate) type u64x8 = Simd; -simd_ty!( - i16x32[i16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); +pub(crate) type i8x64 = Simd; +pub(crate) type i16x32 = Simd; +pub(crate) type i32x16 = Simd; +pub(crate) type i64x8 = Simd; -simd_ty!( - u16x32[u16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); +pub(crate) type f16x32 = Simd; +pub(crate) type f32x16 = Simd; +pub(crate) type f64x8 = Simd; -simd_ty!( - i32x16[i32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - u32x16[u32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - f16x32[f16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - f32x16[f32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - i64x8[i64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); - -simd_ty!( - u64x8[u64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); +// 1024-bit wide types: -simd_ty!( - f64x8[f64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); +pub(crate) type u16x64 = Simd; +pub(crate) type u32x32 = Simd; -// 1024-bit wide types: -simd_ty!( - u16x64[u16;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); -simd_ty!( - i32x32[i32;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - u32x32[u32;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); +pub(crate) type i32x32 = Simd; /// Used to continue `Debug`ging SIMD types as `MySimd(1, 2, 3, 4)`, as they /// were before moving to array-based simd. diff --git a/stdarch/crates/core_arch/src/x86/avx.rs b/stdarch/crates/core_arch/src/x86/avx.rs index 74fc2db13dcdc..ef434205b52a0 100644 --- a/stdarch/crates/core_arch/src/x86/avx.rs +++ b/stdarch/crates/core_arch/src/x86/avx.rs @@ -1097,6 +1097,9 @@ pub const fn _mm256_cvtsi256_si32(a: __m256i) -> i32 { /// Zeroes the contents of all XMM or YMM registers. /// +/// This operation is purely a performance hint for the CPU and has no effect on the Abstract +/// Machine state. +/// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_zeroall) #[inline] #[target_feature(enable = "avx")] @@ -1109,6 +1112,9 @@ pub fn _mm256_zeroall() { /// Zeroes the upper 128 bits of all YMM registers; /// the lower 128-bits of the registers are unmodified. /// +/// This operation is purely a performance hint for the CPU and has no effect on the Abstract +/// Machine state. +/// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_zeroupper) #[inline] #[target_feature(enable = "avx")] @@ -4007,13 +4013,11 @@ mod tests { } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Register-level operation not supported by Miri fn test_mm256_zeroall() { _mm256_zeroall(); } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Register-level operation not supported by Miri fn test_mm256_zeroupper() { _mm256_zeroupper(); } @@ -4484,7 +4488,7 @@ mod tests { } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm256_stream_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let mut r = _mm256_undefined_si256(); @@ -4496,7 +4500,7 @@ mod tests { } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm256_stream_pd() { #[repr(align(32))] struct Memory { @@ -4515,7 +4519,7 @@ mod tests { } #[simd_test(enable = "avx")] - #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm256_stream_ps() { #[repr(align(32))] struct Memory { diff --git a/stdarch/crates/core_arch/src/x86/avx512bf16.rs b/stdarch/crates/core_arch/src/x86/avx512bf16.rs index 66eef063eed8b..8d944f5ba817b 100644 --- a/stdarch/crates/core_arch/src/x86/avx512bf16.rs +++ b/stdarch/crates/core_arch/src/x86/avx512bf16.rs @@ -2,7 +2,6 @@ //! //! [AVX512BF16 intrinsics]: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769&avx512techs=AVX512_BF16 -use crate::arch::asm; use crate::core_arch::{simd::*, x86::*}; use crate::intrinsics::simd::*; @@ -17,6 +16,8 @@ unsafe extern "C" { fn cvtne2ps2bf16_256(a: f32x8, b: f32x8) -> i16x16; #[link_name = "llvm.x86.avx512bf16.cvtne2ps2bf16.512"] fn cvtne2ps2bf16_512(a: f32x16, b: f32x16) -> i16x32; + #[link_name = "llvm.x86.avx512bf16.mask.cvtneps2bf16.128"] + fn cvtneps2bf16_128(a: f32x4, src: i16x8, k: __mmask8) -> i16x8; #[link_name = "llvm.x86.avx512bf16.cvtneps2bf16.256"] fn cvtneps2bf16_256(a: f32x8) -> i16x8; #[link_name = "llvm.x86.avx512bf16.cvtneps2bf16.512"] @@ -519,16 +520,7 @@ pub fn _mm_cvtsbh_ss(a: bf16) -> f32 { #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtneps_pbh(a: __m128) -> __m128bh { - unsafe { - let mut dst: __m128bh; - asm!( - "vcvtneps2bf16 {dst}, {src}", - dst = lateout(xmm_reg) dst, - src = in(xmm_reg) a, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + _mm_mask_cvtneps_pbh(__m128bh::splat(0), !0, a) } /// Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) @@ -541,17 +533,7 @@ pub fn _mm_cvtneps_pbh(a: __m128) -> __m128bh { #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh { - unsafe { - let mut dst = src; - asm!( - "vcvtneps2bf16 {dst}{{{k}}},{src}", - dst = inlateout(xmm_reg) dst, - src = in(xmm_reg) a, - k = in(kreg) k, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + unsafe { cvtneps2bf16_128(a.as_f32x4(), src.as_i16x8(), k).as_m128bh() } } /// Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) @@ -564,17 +546,7 @@ pub fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh { #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtneps_pbh(k: __mmask8, a: __m128) -> __m128bh { - unsafe { - let mut dst: __m128bh; - asm!( - "vcvtneps2bf16 {dst}{{{k}}}{{z}},{src}", - dst = lateout(xmm_reg) dst, - src = in(xmm_reg) a, - k = in(kreg) k, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + _mm_mask_cvtneps_pbh(__m128bh::splat(0), k, a) } /// Converts a single-precision (32-bit) floating-point element in a to a BF16 (16-bit) floating-point diff --git a/stdarch/crates/core_arch/src/x86/avx512bitalg.rs b/stdarch/crates/core_arch/src/x86/avx512bitalg.rs index 6dd4e6b33a3ba..dd211854afbb4 100644 --- a/stdarch/crates/core_arch/src/x86/avx512bitalg.rs +++ b/stdarch/crates/core_arch/src/x86/avx512bitalg.rs @@ -28,12 +28,12 @@ use stdarch_test::assert_instr; #[allow(improper_ctypes)] unsafe extern "C" { - #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.512"] - fn bitshuffle_512(data: i8x64, indices: i8x64, mask: __mmask64) -> __mmask64; - #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.256"] - fn bitshuffle_256(data: i8x32, indices: i8x32, mask: __mmask32) -> __mmask32; - #[link_name = "llvm.x86.avx512.mask.vpshufbitqmb.128"] - fn bitshuffle_128(data: i8x16, indices: i8x16, mask: __mmask16) -> __mmask16; + #[link_name = "llvm.x86.avx512.vpshufbitqmb.512"] + fn bitshuffle_512(data: i8x64, indices: i8x64) -> __mmask64; + #[link_name = "llvm.x86.avx512.vpshufbitqmb.256"] + fn bitshuffle_256(data: i8x32, indices: i8x32) -> __mmask32; + #[link_name = "llvm.x86.avx512.vpshufbitqmb.128"] + fn bitshuffle_128(data: i8x16, indices: i8x16) -> __mmask16; } /// For each packed 16-bit integer maps the value to the number of logical 1 bits. @@ -370,7 +370,7 @@ pub const fn _mm_mask_popcnt_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm512_bitshuffle_epi64_mask(b: __m512i, c: __m512i) -> __mmask64 { - unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64(), !0) } + unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64()) } } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -386,7 +386,7 @@ pub fn _mm512_bitshuffle_epi64_mask(b: __m512i, c: __m512i) -> __mmask64 { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm512_mask_bitshuffle_epi64_mask(k: __mmask64, b: __m512i, c: __m512i) -> __mmask64 { - unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64(), k) } + _mm512_bitshuffle_epi64_mask(b, c) & k } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -399,7 +399,7 @@ pub fn _mm512_mask_bitshuffle_epi64_mask(k: __mmask64, b: __m512i, c: __m512i) - #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm256_bitshuffle_epi64_mask(b: __m256i, c: __m256i) -> __mmask32 { - unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32(), !0) } + unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32()) } } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -415,7 +415,7 @@ pub fn _mm256_bitshuffle_epi64_mask(b: __m256i, c: __m256i) -> __mmask32 { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm256_mask_bitshuffle_epi64_mask(k: __mmask32, b: __m256i, c: __m256i) -> __mmask32 { - unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32(), k) } + _mm256_bitshuffle_epi64_mask(b, c) & k } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -428,7 +428,7 @@ pub fn _mm256_mask_bitshuffle_epi64_mask(k: __mmask32, b: __m256i, c: __m256i) - #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm_bitshuffle_epi64_mask(b: __m128i, c: __m128i) -> __mmask16 { - unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16(), !0) } + unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16()) } } /// Considers the input `b` as packed 64-bit integers and `c` as packed 8-bit integers. @@ -444,7 +444,7 @@ pub fn _mm_bitshuffle_epi64_mask(b: __m128i, c: __m128i) -> __mmask16 { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm_mask_bitshuffle_epi64_mask(k: __mmask16, b: __m128i, c: __m128i) -> __mmask16 { - unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16(), k) } + _mm_bitshuffle_epi64_mask(b, c) & k } #[cfg(test)] diff --git a/stdarch/crates/core_arch/src/x86/avx512dq.rs b/stdarch/crates/core_arch/src/x86/avx512dq.rs index 9e1a4c0b29558..0b322c8b83c7b 100644 --- a/stdarch/crates/core_arch/src/x86/avx512dq.rs +++ b/stdarch/crates/core_arch/src/x86/avx512dq.rs @@ -6865,7 +6865,7 @@ pub fn _mm_maskz_reduce_ss(k: __mmask8, a: __m128, b: __m128) - #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_fpclass_pd_mask(a: __m128d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm_mask_fpclass_pd_mask::(0xff, a) + unsafe { vfpclasspd_128(a.as_f64x2(), IMM8) } } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6889,10 +6889,7 @@ pub fn _mm_fpclass_pd_mask(a: __m128d) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_fpclass_pd_mask(k1: __mmask8, a: __m128d) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclasspd_128(a.as_f64x2(), IMM8, k1)) - } + _mm_fpclass_pd_mask::(a) & k1 } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6916,7 +6913,7 @@ pub fn _mm_mask_fpclass_pd_mask(k1: __mmask8, a: __m128d) -> __ #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_fpclass_pd_mask(a: __m256d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm256_mask_fpclass_pd_mask::(0xff, a) + unsafe { vfpclasspd_256(a.as_f64x4(), IMM8) } } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6940,10 +6937,7 @@ pub fn _mm256_fpclass_pd_mask(a: __m256d) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_fpclass_pd_mask(k1: __mmask8, a: __m256d) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclasspd_256(a.as_f64x4(), IMM8, k1)) - } + _mm256_fpclass_pd_mask::(a) & k1 } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6967,7 +6961,7 @@ pub fn _mm256_mask_fpclass_pd_mask(k1: __mmask8, a: __m256d) -> #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_fpclass_pd_mask(a: __m512d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm512_mask_fpclass_pd_mask::(0xff, a) + unsafe { vfpclasspd_512(a.as_f64x8(), IMM8) } } /// Test packed double-precision (64-bit) floating-point elements in a for special categories specified @@ -6991,10 +6985,7 @@ pub fn _mm512_fpclass_pd_mask(a: __m512d) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_fpclass_pd_mask(k1: __mmask8, a: __m512d) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclasspd_512(a.as_f64x8(), IMM8, k1)) - } + _mm512_fpclass_pd_mask::(a) & k1 } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7018,7 +7009,7 @@ pub fn _mm512_mask_fpclass_pd_mask(k1: __mmask8, a: __m512d) -> #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_fpclass_ps_mask(a: __m128) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm_mask_fpclass_ps_mask::(0xff, a) + unsafe { vfpclassps_128(a.as_f32x4(), IMM8) } } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7042,10 +7033,7 @@ pub fn _mm_fpclass_ps_mask(a: __m128) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_fpclass_ps_mask(k1: __mmask8, a: __m128) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclassps_128(a.as_f32x4(), IMM8, k1)) - } + _mm_fpclass_ps_mask::(a) & k1 } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7069,7 +7057,7 @@ pub fn _mm_mask_fpclass_ps_mask(k1: __mmask8, a: __m128) -> __m #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_fpclass_ps_mask(a: __m256) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); - _mm256_mask_fpclass_ps_mask::(0xff, a) + unsafe { vfpclassps_256(a.as_f32x8(), IMM8) } } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7093,10 +7081,7 @@ pub fn _mm256_fpclass_ps_mask(a: __m256) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_fpclass_ps_mask(k1: __mmask8, a: __m256) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclassps_256(a.as_f32x8(), IMM8, k1)) - } + _mm256_fpclass_ps_mask::(a) & k1 } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7120,7 +7105,7 @@ pub fn _mm256_mask_fpclass_ps_mask(k1: __mmask8, a: __m256) -> #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_fpclass_ps_mask(a: __m512) -> __mmask16 { static_assert_uimm_bits!(IMM8, 8); - _mm512_mask_fpclass_ps_mask::(0xffff, a) + unsafe { vfpclassps_512(a.as_f32x16(), IMM8) } } /// Test packed single-precision (32-bit) floating-point elements in a for special categories specified @@ -7144,10 +7129,7 @@ pub fn _mm512_fpclass_ps_mask(a: __m512) -> __mmask16 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_fpclass_ps_mask(k1: __mmask16, a: __m512) -> __mmask16 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - transmute(vfpclassps_512(a.as_f32x16(), IMM8, k1)) - } + _mm512_fpclass_ps_mask::(a) & k1 } /// Test the lower double-precision (64-bit) floating-point element in a for special categories specified @@ -7377,19 +7359,19 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.reduce.ss"] fn vreducess(a: f32x4, b: f32x4, src: f32x4, k: __mmask8, imm8: i32, sae: i32) -> f32x4; - #[link_name = "llvm.x86.avx512.mask.fpclass.pd.128"] - fn vfpclasspd_128(a: f64x2, imm8: i32, k: __mmask8) -> __mmask8; - #[link_name = "llvm.x86.avx512.mask.fpclass.pd.256"] - fn vfpclasspd_256(a: f64x4, imm8: i32, k: __mmask8) -> __mmask8; - #[link_name = "llvm.x86.avx512.mask.fpclass.pd.512"] - fn vfpclasspd_512(a: f64x8, imm8: i32, k: __mmask8) -> __mmask8; - - #[link_name = "llvm.x86.avx512.mask.fpclass.ps.128"] - fn vfpclassps_128(a: f32x4, imm8: i32, k: __mmask8) -> __mmask8; - #[link_name = "llvm.x86.avx512.mask.fpclass.ps.256"] - fn vfpclassps_256(a: f32x8, imm8: i32, k: __mmask8) -> __mmask8; - #[link_name = "llvm.x86.avx512.mask.fpclass.ps.512"] - fn vfpclassps_512(a: f32x16, imm8: i32, k: __mmask16) -> __mmask16; + #[link_name = "llvm.x86.avx512.fpclass.pd.128"] + fn vfpclasspd_128(a: f64x2, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512.fpclass.pd.256"] + fn vfpclasspd_256(a: f64x4, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512.fpclass.pd.512"] + fn vfpclasspd_512(a: f64x8, imm8: i32) -> __mmask8; + + #[link_name = "llvm.x86.avx512.fpclass.ps.128"] + fn vfpclassps_128(a: f32x4, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512.fpclass.ps.256"] + fn vfpclassps_256(a: f32x8, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512.fpclass.ps.512"] + fn vfpclassps_512(a: f32x16, imm8: i32) -> __mmask16; #[link_name = "llvm.x86.avx512.mask.fpclass.sd"] fn vfpclasssd(a: f64x2, imm8: i32, k: __mmask8) -> __mmask8; diff --git a/stdarch/crates/core_arch/src/x86/avx512f.rs b/stdarch/crates/core_arch/src/x86/avx512f.rs index 3730496e1ec34..66ea63b674f12 100644 --- a/stdarch/crates/core_arch/src/x86/avx512f.rs +++ b/stdarch/crates/core_arch/src/x86/avx512f.rs @@ -16242,7 +16242,7 @@ pub fn _mm512_maskz_cvttps_epi32(k: __mmask16, a: __m512) -> __m512i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm256_mask_cvttps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i { - unsafe { transmute(vcvttps2dq256(a.as_f32x8(), src.as_i32x8(), k)) } + unsafe { simd_select_bitmask(k, _mm256_cvttps_epi32(a).as_i32x8(), src.as_i32x8()).as_m256i() } } /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). @@ -16253,7 +16253,7 @@ pub fn _mm256_mask_cvttps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm256_maskz_cvttps_epi32(k: __mmask8, a: __m256) -> __m256i { - unsafe { transmute(vcvttps2dq256(a.as_f32x8(), i32x8::ZERO, k)) } + _mm256_mask_cvttps_epi32(_mm256_setzero_si256(), k, a) } /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -16264,7 +16264,7 @@ pub fn _mm256_maskz_cvttps_epi32(k: __mmask8, a: __m256) -> __m256i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm_mask_cvttps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { - unsafe { transmute(vcvttps2dq128(a.as_f32x4(), src.as_i32x4(), k)) } + unsafe { simd_select_bitmask(k, _mm_cvttps_epi32(a).as_i32x4(), src.as_i32x4()).as_m128i() } } /// Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). @@ -16275,7 +16275,7 @@ pub fn _mm_mask_cvttps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm_maskz_cvttps_epi32(k: __mmask8, a: __m128) -> __m128i { - unsafe { transmute(vcvttps2dq128(a.as_f32x4(), i32x4::ZERO, k)) } + _mm_mask_cvttps_epi32(_mm_setzero_si128(), k, a) } /// Convert packed single-precision (32-bit) floating-point elements in a to packed unsigned 32-bit integers with truncation, and store the results in dst. @@ -16478,7 +16478,7 @@ pub fn _mm512_maskz_cvttpd_epi32(k: __mmask8, a: __m512d) -> __m256i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm256_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i { - unsafe { transmute(vcvttpd2dq256(a.as_f64x4(), src.as_i32x4(), k)) } + unsafe { simd_select_bitmask(k, _mm256_cvttpd_epi32(a).as_i32x4(), src.as_i32x4()).as_m128i() } } /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). @@ -16489,7 +16489,7 @@ pub fn _mm256_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm256_maskz_cvttpd_epi32(k: __mmask8, a: __m256d) -> __m128i { - unsafe { transmute(vcvttpd2dq256(a.as_f64x4(), i32x4::ZERO, k)) } + _mm256_mask_cvttpd_epi32(_mm_setzero_si128(), k, a) } /// Convert packed double-precision (64-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -16807,12 +16807,12 @@ pub const fn _mm512_set_epi8( e0: i8, ) -> __m512i { unsafe { - let r = i8x64::new( + let r = i8x64::from_array([ e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, e16, e17, e18, e19, e20, e21, e22, e23, e24, e25, e26, e27, e28, e29, e30, e31, e32, e33, e34, e35, e36, e37, e38, e39, e40, e41, e42, e43, e44, e45, e46, e47, e48, e49, e50, e51, e52, e53, e54, e55, e56, e57, e58, e59, e60, e61, e62, e63, - ); + ]); transmute(r) } } @@ -42633,7 +42633,7 @@ pub fn _mm_mask3_fnmsub_round_sd( } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_ss&expand=2517) #[inline] @@ -42649,12 +42649,12 @@ pub fn _mm_fixupimm_ss(a: __m128, b: __m128, c: __m128i) -> __m let c = c.as_i32x4(); let r = vfixupimmss(a, b, c, IMM8, 0b11111111, _MM_FROUND_CUR_DIRECTION); let fixupimm: f32 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_ss&expand=2518) #[inline] @@ -42675,12 +42675,12 @@ pub fn _mm_mask_fixupimm_ss( let c = c.as_i32x4(); let fixupimm = vfixupimmss(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION); let fixupimm: f32 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_ss&expand=2519) #[inline] @@ -42701,12 +42701,12 @@ pub fn _mm_maskz_fixupimm_ss( let c = c.as_i32x4(); let fixupimm = vfixupimmssz(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION); let fixupimm: f32 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_sd&expand=2514) #[inline] @@ -42722,12 +42722,12 @@ pub fn _mm_fixupimm_sd(a: __m128d, b: __m128d, c: __m128i) -> _ let c = c.as_i64x2(); let fixupimm = vfixupimmsd(a, b, c, IMM8, 0b11111111, _MM_FROUND_CUR_DIRECTION); let fixupimm: f64 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_sd&expand=2515) #[inline] @@ -42748,12 +42748,12 @@ pub fn _mm_mask_fixupimm_sd( let c = c.as_i64x2(); let fixupimm = vfixupimmsd(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION); let fixupimm: f64 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting. +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_sd&expand=2516) #[inline] @@ -42774,12 +42774,12 @@ pub fn _mm_maskz_fixupimm_sd( let c = c.as_i64x2(); let fixupimm = vfixupimmsdz(a, b, c, IMM8, k, _MM_FROUND_CUR_DIRECTION); let fixupimm: f64 = simd_extract!(fixupimm, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst, and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_round_ss&expand=2511) @@ -42801,12 +42801,12 @@ pub fn _mm_fixupimm_round_ss( let c = c.as_i32x4(); let r = vfixupimmss(a, b, c, IMM8, 0b11111111, SAE); let fixupimm: f32 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_round_ss&expand=2512) @@ -42829,12 +42829,12 @@ pub fn _mm_mask_fixupimm_round_ss( let c = c.as_i32x4(); let r = vfixupimmss(a, b, c, IMM8, k, SAE); let fixupimm: f32 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from a to the upper elements of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower single-precision (32-bit) floating-point elements in a and b using the lower 32-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from b to the upper elements of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_round_ss&expand=2513) @@ -42857,12 +42857,12 @@ pub fn _mm_maskz_fixupimm_round_ss( let c = c.as_i32x4(); let r = vfixupimmssz(a, b, c, IMM8, k, SAE); let fixupimm: f32 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst, and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_round_sd&expand=2508) @@ -42884,12 +42884,12 @@ pub fn _mm_fixupimm_round_sd( let c = c.as_i64x2(); let r = vfixupimmsd(a, b, c, IMM8, 0b11111111, SAE); let fixupimm: f64 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using writemask k (the element is copied from a when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_round_sd&expand=2509) @@ -42912,12 +42912,12 @@ pub fn _mm_mask_fixupimm_round_sd( let c = c.as_i64x2(); let r = vfixupimmsd(a, b, c, IMM8, k, SAE); let fixupimm: f64 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } -/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from a to the upper element of dst. imm8 is used to set the required flags reporting.\ +/// Fix up the lower double-precision (64-bit) floating-point elements in a and b using the lower 64-bit integer in c, store the result in the lower element of dst using zeromask k (the element is zeroed out when mask bit 0 is not set), and copy the upper element from b to the upper element of dst. imm8 is used to set the required flags reporting.\ /// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_round_sd&expand=2510) @@ -42940,7 +42940,7 @@ pub fn _mm_maskz_fixupimm_round_sd( let c = c.as_i64x2(); let r = vfixupimmsdz(a, b, c, IMM8, k, SAE); let fixupimm: f64 = simd_extract!(r, 0); - let r = simd_insert!(a, 0, fixupimm); + let r = simd_insert!(b, 0, fixupimm); transmute(r) } } @@ -44430,10 +44430,6 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.cvttps2dq.512"] fn vcvttps2dq(a: f32x16, src: i32x16, mask: u16, rounding: i32) -> i32x16; - #[link_name = "llvm.x86.avx512.mask.cvttps2dq.256"] - fn vcvttps2dq256(a: f32x8, src: i32x8, mask: u8) -> i32x8; - #[link_name = "llvm.x86.avx512.mask.cvttps2dq.128"] - fn vcvttps2dq128(a: f32x4, src: i32x4, mask: u8) -> i32x4; #[link_name = "llvm.x86.avx512.mask.cvttps2udq.512"] fn vcvttps2udq(a: f32x16, src: u32x16, mask: u16, rounding: i32) -> u32x16; @@ -44444,8 +44440,6 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.512"] fn vcvttpd2dq(a: f64x8, src: i32x8, mask: u8, rounding: i32) -> i32x8; - #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.256"] - fn vcvttpd2dq256(a: f64x4, src: i32x4, mask: u8) -> i32x4; #[link_name = "llvm.x86.avx512.mask.cvttpd2dq.128"] fn vcvttpd2dq128(a: f64x2, src: i32x4, mask: u8) -> i32x4; @@ -58252,7 +58246,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - #[cfg_attr(miri, ignore)] + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm512_stream_ps() { #[repr(align(64))] struct Memory { @@ -58271,7 +58265,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - #[cfg_attr(miri, ignore)] + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm512_stream_pd() { #[repr(align(64))] struct Memory { @@ -58290,7 +58284,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - #[cfg_attr(miri, ignore)] + #[cfg_attr(miri, ignore)] // Inline asm (for non-temporal store), which is not supported by Miri fn test_mm512_stream_si512() { #[repr(align(64))] struct Memory { @@ -61836,7 +61830,7 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_fixupimm_ss::<5>(a, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61846,7 +61840,7 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_mask_fixupimm_ss::<5>(a, 0b11111111, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61856,10 +61850,10 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_maskz_fixupimm_ss::<5>(0b00000000, a, b, c); - let e = _mm_set_ps(0., 0., 0., 0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, 0.0); assert_eq_m128(r, e); let r = _mm_maskz_fixupimm_ss::<5>(0b11111111, a, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61869,7 +61863,7 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_fixupimm_sd::<5>(a, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61879,7 +61873,7 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_mask_fixupimm_sd::<5>(a, 0b11111111, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61889,10 +61883,10 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_maskz_fixupimm_sd::<5>(0b00000000, a, b, c); - let e = _mm_set_pd(0., 0.0); + let e = _mm_set_pd(f64::MAX, 0.0); assert_eq_m128d(r, e); let r = _mm_maskz_fixupimm_sd::<5>(0b11111111, a, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61902,7 +61896,7 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c); - let e = _mm_set_ps(1., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61912,7 +61906,7 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_mask_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61922,10 +61916,10 @@ mod tests { let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); let r = _mm_maskz_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(0b00000000, a, b, c); - let e = _mm_set_ps(0., 0., 0., 0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, 0.0); assert_eq_m128(r, e); let r = _mm_maskz_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b, c); - let e = _mm_set_ps(0., 0., 0., -0.0); + let e = _mm_set_ps(f32::MAX, f32::MAX, f32::MAX, -0.0); assert_eq_m128(r, e); } @@ -61935,7 +61929,7 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61945,7 +61939,7 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_mask_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } @@ -61955,10 +61949,10 @@ mod tests { let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); let r = _mm_maskz_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(0b00000000, a, b, c); - let e = _mm_set_pd(0., 0.0); + let e = _mm_set_pd(f64::MAX, 0.0); assert_eq_m128d(r, e); let r = _mm_maskz_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b, c); - let e = _mm_set_pd(0., -0.0); + let e = _mm_set_pd(f64::MAX, -0.0); assert_eq_m128d(r, e); } diff --git a/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/stdarch/crates/core_arch/src/x86/avx512fp16.rs index 8ddc3d29a3a11..6523e98d0ca8d 100644 --- a/stdarch/crates/core_arch/src/x86/avx512fp16.rs +++ b/stdarch/crates/core_arch/src/x86/avx512fp16.rs @@ -695,34 +695,6 @@ pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h { } } -macro_rules! cmp_asm { // FIXME: use LLVM intrinsics - ($mask_type: ty, $reg: ident, $a: expr, $b: expr) => {{ - let dst: $mask_type; - asm!( - "vcmpph {k}, {a}, {b}, {imm8}", - k = lateout(kreg) dst, - a = in($reg) $a, - b = in($reg) $b, - imm8 = const IMM5, - options(pure, nomem, nostack) - ); - dst - }}; - ($mask_type: ty, $mask: expr, $reg: ident, $a: expr, $b: expr) => {{ - let dst: $mask_type; - asm!( - "vcmpph {k} {{ {mask} }}, {a}, {b}, {imm8}", - k = lateout(kreg) dst, - mask = in(kreg) $mask, - a = in($reg) $a, - b = in($reg) $b, - imm8 = const IMM5, - options(pure, nomem, nostack) - ); - dst - }}; -} - /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison /// operand specified by imm8, and store the results in mask vector k. /// @@ -732,10 +704,7 @@ macro_rules! cmp_asm { // FIXME: use LLVM intrinsics #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_ph_mask(a: __m128h, b: __m128h) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask8, xmm_reg, a, b) - } + _mm_mask_cmp_ph_mask::(!0, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -750,7 +719,7 @@ pub fn _mm_cmp_ph_mask(a: __m128h, b: __m128h) -> __mmask8 { pub fn _mm_mask_cmp_ph_mask(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask8, k1, xmm_reg, a, b) + vcmpph_128(a, b, IMM5, k1) } } @@ -763,10 +732,7 @@ pub fn _mm_mask_cmp_ph_mask(k1: __mmask8, a: __m128h, b: __m128 #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cmp_ph_mask(a: __m256h, b: __m256h) -> __mmask16 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask16, ymm_reg, a, b) - } + _mm256_mask_cmp_ph_mask::(!0, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -785,7 +751,7 @@ pub fn _mm256_mask_cmp_ph_mask( ) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask16, k1, ymm_reg, a, b) + vcmpph_256(a, b, IMM5, k1) } } @@ -798,10 +764,7 @@ pub fn _mm256_mask_cmp_ph_mask( #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmp_ph_mask(a: __m512h, b: __m512h) -> __mmask32 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask32, zmm_reg, a, b) - } + _mm512_mask_cmp_ph_mask::(!0, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -818,10 +781,7 @@ pub fn _mm512_mask_cmp_ph_mask( a: __m512h, b: __m512h, ) -> __mmask32 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - cmp_asm!(__mmask32, k1, zmm_reg, a, b) - } + _mm512_mask_cmp_round_ph_mask::(k1, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -838,24 +798,7 @@ pub fn _mm512_cmp_round_ph_mask( a: __m512h, b: __m512h, ) -> __mmask32 { - unsafe { - static_assert_uimm_bits!(IMM5, 5); - static_assert_sae!(SAE); - if SAE == _MM_FROUND_NO_EXC { - let dst: __mmask32; - asm!( - "vcmpph {k}, {a}, {b}, {{sae}}, {imm8}", - k = lateout(kreg) dst, - a = in(zmm_reg) a, - b = in(zmm_reg) b, - imm8 = const IMM5, - options(pure, nomem, nostack) - ); - dst - } else { - cmp_asm!(__mmask32, zmm_reg, a, b) - } - } + _mm512_mask_cmp_round_ph_mask::(!0, a, b) } /// Compare packed half-precision (16-bit) floating-point elements in a and b based on the comparison @@ -877,21 +820,7 @@ pub fn _mm512_mask_cmp_round_ph_mask( unsafe { static_assert_uimm_bits!(IMM5, 5); static_assert_sae!(SAE); - if SAE == _MM_FROUND_NO_EXC { - let dst: __mmask32; - asm!( - "vcmpph {k} {{{k1}}}, {a}, {b}, {{sae}}, {imm8}", - k = lateout(kreg) dst, - k1 = in(kreg) k1, - a = in(zmm_reg) a, - b = in(zmm_reg) b, - imm8 = const IMM5, - options(pure, nomem, nostack) - ); - dst - } else { - cmp_asm!(__mmask32, k1, zmm_reg, a, b) - } + vcmpph_512(a, b, IMM5, k1, SAE) } } @@ -11538,32 +11467,6 @@ pub fn _mm512_reduce_max_ph(a: __m512h) -> f16 { } } -macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics - ($mask_type: ty, $reg: ident, $a: expr) => {{ - let dst: $mask_type; - asm!( - "vfpclassph {k}, {src}, {imm8}", - k = lateout(kreg) dst, - src = in($reg) $a, - imm8 = const IMM8, - options(pure, nomem, nostack) - ); - dst - }}; - ($mask_type: ty, $mask: expr, $reg: ident, $a: expr) => {{ - let dst: $mask_type; - asm!( - "vfpclassph {k} {{ {mask} }}, {src}, {imm8}", - k = lateout(kreg) dst, - mask = in(kreg) $mask, - src = in($reg) $a, - imm8 = const IMM8, - options(pure, nomem, nostack) - ); - dst - }}; -} - /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified /// by imm8, and store the results in mask vector k. /// imm can be a combination of: @@ -11586,7 +11489,7 @@ macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics pub fn _mm_fpclass_ph_mask(a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask8, xmm_reg, a) + vfpclassph_128(a, IMM8) } } @@ -11611,10 +11514,7 @@ pub fn _mm_fpclass_ph_mask(a: __m128h) -> __mmask8 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fpclass_ph_mask(k1: __mmask8, a: __m128h) -> __mmask8 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask8, k1, xmm_reg, a) - } + _mm_fpclass_ph_mask::(a) & k1 } /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified @@ -11639,7 +11539,7 @@ pub fn _mm_mask_fpclass_ph_mask(k1: __mmask8, a: __m128h) -> __ pub fn _mm256_fpclass_ph_mask(a: __m256h) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask16, ymm_reg, a) + vfpclassph_256(a, IMM8) } } @@ -11664,10 +11564,7 @@ pub fn _mm256_fpclass_ph_mask(a: __m256h) -> __mmask16 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fpclass_ph_mask(k1: __mmask16, a: __m256h) -> __mmask16 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask16, k1, ymm_reg, a) - } + _mm256_fpclass_ph_mask::(a) & k1 } /// Test packed half-precision (16-bit) floating-point elements in a for special categories specified @@ -11692,7 +11589,7 @@ pub fn _mm256_mask_fpclass_ph_mask(k1: __mmask16, a: __m256h) - pub fn _mm512_fpclass_ph_mask(a: __m512h) -> __mmask32 { unsafe { static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask32, zmm_reg, a) + vfpclassph_512(a, IMM8) } } @@ -11717,10 +11614,7 @@ pub fn _mm512_fpclass_ph_mask(a: __m512h) -> __mmask32 { #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fpclass_ph_mask(k1: __mmask32, a: __m512h) -> __mmask32 { - unsafe { - static_assert_uimm_bits!(IMM8, 8); - fpclass_asm!(__mmask32, k1, zmm_reg, a) - } + _mm512_fpclass_ph_mask::(a) & k1 } /// Test the lower half-precision (16-bit) floating-point element in a for special categories specified @@ -16571,11 +16465,18 @@ pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i { } #[allow(improper_ctypes)] -unsafe extern "C" { +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.128"] + fn vcmpph_128(a: __m128h, b: __m128h, imm5: i32, mask: __mmask8) -> __mmask8; + #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.256"] + fn vcmpph_256(a: __m256h, b: __m256h, imm5: i32, mask: __mmask16) -> __mmask16; + #[link_name = "llvm.x86.avx512fp16.mask.cmp.ph.512"] + fn vcmpph_512(a: __m512h, b: __m512h, imm5: i32, mask: __mmask32, sae: i32) -> __mmask32; + #[link_name = "llvm.x86.avx512fp16.mask.cmp.sh"] - fn vcmpsh(a: __m128h, b: __m128h, imm8: i32, mask: __mmask8, sae: i32) -> __mmask8; + fn vcmpsh(a: __m128h, b: __m128h, imm5: i32, mask: __mmask8, sae: i32) -> __mmask8; #[link_name = "llvm.x86.avx512fp16.vcomi.sh"] - fn vcomish(a: __m128h, b: __m128h, imm8: i32, sae: i32) -> i32; + fn vcomish(a: __m128h, b: __m128h, imm5: i32, sae: i32) -> i32; #[link_name = "llvm.x86.avx512fp16.add.ph.512"] fn vaddph(a: __m512h, b: __m512h, rounding: i32) -> __m512h; @@ -16758,6 +16659,13 @@ unsafe extern "C" { fn vreducesh(a: __m128h, b: __m128h, src: __m128h, k: __mmask8, imm8: i32, sae: i32) -> __m128h; + #[link_name = "llvm.x86.avx512fp16.fpclass.ph.128"] + fn vfpclassph_128(a: __m128h, imm8: i32) -> __mmask8; + #[link_name = "llvm.x86.avx512fp16.fpclass.ph.256"] + fn vfpclassph_256(a: __m256h, imm8: i32) -> __mmask16; + #[link_name = "llvm.x86.avx512fp16.fpclass.ph.512"] + fn vfpclassph_512(a: __m512h, imm8: i32) -> __mmask32; + #[link_name = "llvm.x86.avx512fp16.mask.fpclass.sh"] fn vfpclasssh(a: __m128h, imm8: i32, k: __mmask8) -> __mmask8; diff --git a/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs b/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs new file mode 100644 index 0000000000000..4dd7412e9e330 --- /dev/null +++ b/stdarch/crates/core_arch/src/x86/avx512vp2intersect.rs @@ -0,0 +1,244 @@ +//! Vector Pair Intersection to a Pair of Mask Registers (VP2INTERSECT) + +use crate::core_arch::{simd::*, x86::*}; + +#[cfg(test)] +use stdarch_test::assert_instr; + +/// Compute intersection of packed 32-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi32&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512vl")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectd))] +pub unsafe fn _mm_2intersect_epi32(a: __m128i, b: __m128i, k1: *mut __mmask8, k2: *mut __mmask8) { + (*k1, *k2) = vp2intersectd_128(a.as_i32x4(), b.as_i32x4()); +} + +/// Compute intersection of packed 64-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_2intersect_epi64&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512vl")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectq))] +pub unsafe fn _mm_2intersect_epi64(a: __m128i, b: __m128i, k1: *mut __mmask8, k2: *mut __mmask8) { + (*k1, *k2) = vp2intersectq_128(a.as_i64x2(), b.as_i64x2()); +} + +/// Compute intersection of packed 32-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi32&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512vl")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectd))] +pub unsafe fn _mm256_2intersect_epi32( + a: __m256i, + b: __m256i, + k1: *mut __mmask8, + k2: *mut __mmask8, +) { + (*k1, *k2) = vp2intersectd_256(a.as_i32x8(), b.as_i32x8()); +} + +/// Compute intersection of packed 64-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_2intersect_epi64&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512vl")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectq))] +pub unsafe fn _mm256_2intersect_epi64( + a: __m256i, + b: __m256i, + k1: *mut __mmask8, + k2: *mut __mmask8, +) { + (*k1, *k2) = vp2intersectq_256(a.as_i64x4(), b.as_i64x4()); +} + +/// Compute intersection of packed 32-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi32&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512f")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectd))] +pub unsafe fn _mm512_2intersect_epi32( + a: __m512i, + b: __m512i, + k1: *mut __mmask16, + k2: *mut __mmask16, +) { + (*k1, *k2) = vp2intersectd_512(a.as_i32x16(), b.as_i32x16()); +} + +/// Compute intersection of packed 64-bit integer vectors a and b, +/// and store indication of match in the corresponding bit of two mask registers +/// specified by k1 and k2. A match in corresponding elements of a and b is +/// indicated by a set bit in the corresponding bit of the mask registers. +/// +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_2intersect_epi64&expand=0) +#[inline] +#[target_feature(enable = "avx512vp2intersect,avx512f")] +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +#[cfg_attr(test, assert_instr(vp2intersectq))] +pub unsafe fn _mm512_2intersect_epi64( + a: __m512i, + b: __m512i, + k1: *mut __mmask8, + k2: *mut __mmask8, +) { + (*k1, *k2) = vp2intersectq_512(a.as_i64x8(), b.as_i64x8()); +} + +#[allow(improper_ctypes)] +unsafe extern "C" { + #[link_name = "llvm.x86.avx512.vp2intersect.d.128"] + fn vp2intersectd_128(a: i32x4, b: i32x4) -> (u8, u8); + #[link_name = "llvm.x86.avx512.vp2intersect.q.128"] + fn vp2intersectq_128(a: i64x2, b: i64x2) -> (u8, u8); + + #[link_name = "llvm.x86.avx512.vp2intersect.d.256"] + fn vp2intersectd_256(a: i32x8, b: i32x8) -> (u8, u8); + #[link_name = "llvm.x86.avx512.vp2intersect.q.256"] + fn vp2intersectq_256(a: i64x4, b: i64x4) -> (u8, u8); + + #[link_name = "llvm.x86.avx512.vp2intersect.d.512"] + fn vp2intersectd_512(a: i32x16, b: i32x16) -> (u16, u16); + #[link_name = "llvm.x86.avx512.vp2intersect.q.512"] + fn vp2intersectq_512(a: i64x8, b: i64x8) -> (u8, u8); +} + +#[cfg(test)] +mod tests { + use crate::core_arch::x86::*; + use stdarch_test::simd_test; + + #[simd_test(enable = "avx512vp2intersect,avx512vl")] + unsafe fn test_mm_2intersect_epi32() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm_set_epi32(1, 2, 3, 4); + let b = _mm_set_epi32(3, 4, 5, 6); + _mm_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0011); + assert_eq!(k2, 0b1100); + + let a = _mm_set_epi32(1, 2, 3, 4); + let b = _mm_set_epi32(2, 3, 4, 5); + _mm_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0111); + assert_eq!(k2, 0b1110); + } + + #[simd_test(enable = "avx512vp2intersect,avx512vl")] + unsafe fn test_mm_2intersect_epi64() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm_set_epi64x(1, 2); + let b = _mm_set_epi64x(2, 3); + _mm_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b01); + assert_eq!(k2, 0b10); + + let a = _mm_set_epi64x(1, 2); + let b = _mm_set_epi64x(2, 2); + _mm_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b01); + assert_eq!(k2, 0b11); + } + + #[simd_test(enable = "avx512vp2intersect,avx512vl")] + unsafe fn test_mm256_2intersect_epi32() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8); + let b = _mm256_set_epi32(5, 6, 7, 8, 9, 10, 11, 12); + _mm256_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b00001111); + assert_eq!(k2, 0b11110000); + + let a = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8); + let b = _mm256_set_epi32(2, 3, 4, 5, 6, 7, 8, 9); + _mm256_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b01111111); + assert_eq!(k2, 0b11111110); + } + + #[simd_test(enable = "avx512vp2intersect,avx512vl")] + unsafe fn test_mm256_2intersect_epi64() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm256_set_epi64x(1, 2, 3, 4); + let b = _mm256_set_epi64x(3, 4, 5, 6); + _mm256_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0011); + assert_eq!(k2, 0b1100); + + let a = _mm256_set_epi64x(1, 2, 3, 4); + let b = _mm256_set_epi64x(2, 3, 4, 5); + _mm256_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0111); + assert_eq!(k2, 0b1110); + } + + #[simd_test(enable = "avx512vp2intersect,avx512f")] + unsafe fn test_mm512_2intersect_epi32() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); + let b = _mm512_set_epi32( + 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + ); + _mm512_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0000000011111111); + assert_eq!(k2, 0b1111111100000000); + + let a = _mm512_set_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); + let b = _mm512_set_epi32(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17); + _mm512_2intersect_epi32(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b0111111111111111); + assert_eq!(k2, 0b1111111111111110); + } + + #[simd_test(enable = "avx512vp2intersect,avx512f")] + unsafe fn test_mm512_2intersect_epi64() { + let mut k1 = 0; + let mut k2 = 0; + + let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8); + let b = _mm512_set_epi64(5, 6, 7, 8, 9, 10, 11, 12); + _mm512_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b00001111); + assert_eq!(k2, 0b11110000); + + let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8); + let b = _mm512_set_epi64(2, 3, 4, 5, 6, 7, 8, 9); + _mm512_2intersect_epi64(a, b, &mut k1, &mut k2); + assert_eq!(k1, 0b01111111); + assert_eq!(k2, 0b11111110); + } +} diff --git a/stdarch/crates/core_arch/src/x86/avxneconvert.rs b/stdarch/crates/core_arch/src/x86/avxneconvert.rs index b8a3b9473af9e..861213eb4257f 100644 --- a/stdarch/crates/core_arch/src/x86/avxneconvert.rs +++ b/stdarch/crates/core_arch/src/x86/avxneconvert.rs @@ -1,4 +1,3 @@ -use crate::arch::asm; use crate::core_arch::x86::*; #[cfg(test)] @@ -161,16 +160,7 @@ pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 { #[cfg_attr(test, assert_instr(vcvtneps2bf16))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh { - unsafe { - let mut dst: __m128bh; - asm!( - "{{vex}}vcvtneps2bf16 {dst},{src}", - dst = lateout(xmm_reg) dst, - src = in(xmm_reg) a, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + unsafe { vcvtneps2bf16_128(a) } } /// Convert packed single precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point @@ -182,16 +172,7 @@ pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh { #[cfg_attr(test, assert_instr(vcvtneps2bf16))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtneps_avx_pbh(a: __m256) -> __m128bh { - unsafe { - let mut dst: __m128bh; - asm!( - "{{vex}}vcvtneps2bf16 {dst},{src}", - dst = lateout(xmm_reg) dst, - src = in(ymm_reg) a, - options(pure, nomem, nostack, preserves_flags) - ); - dst - } + unsafe { vcvtneps2bf16_256(a) } } #[allow(improper_ctypes)] @@ -222,6 +203,11 @@ unsafe extern "C" { fn cvtneoph2ps_128(a: *const __m128h) -> __m128; #[link_name = "llvm.x86.vcvtneoph2ps256"] fn cvtneoph2ps_256(a: *const __m256h) -> __m256; + + #[link_name = "llvm.x86.vcvtneps2bf16128"] + fn vcvtneps2bf16_128(a: __m128) -> __m128bh; + #[link_name = "llvm.x86.vcvtneps2bf16256"] + fn vcvtneps2bf16_256(a: __m256) -> __m128bh; } #[cfg(test)] diff --git a/stdarch/crates/core_arch/src/x86/mod.rs b/stdarch/crates/core_arch/src/x86/mod.rs index 68a963f65b7d4..f5a8acbd8fac4 100644 --- a/stdarch/crates/core_arch/src/x86/mod.rs +++ b/stdarch/crates/core_arch/src/x86/mod.rs @@ -778,3 +778,7 @@ pub use self::kl::*; mod movrs; #[unstable(feature = "movrs_target_feature", issue = "137976")] pub use self::movrs::*; + +mod avx512vp2intersect; +#[unstable(feature = "stdarch_x86_avx512vp2intersect", issue = "111137")] +pub use self::avx512vp2intersect::*; diff --git a/stdarch/crates/core_arch/src/x86/sse.rs b/stdarch/crates/core_arch/src/x86/sse.rs index 9183eabd530ca..867387290119b 100644 --- a/stdarch/crates/core_arch/src/x86/sse.rs +++ b/stdarch/crates/core_arch/src/x86/sse.rs @@ -2997,66 +2997,87 @@ mod tests { } } + macro_rules! test_mm_cvtss_si32_impl { + ($alias:ident) => { + let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1]; + let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520]; + for i in 0..inputs.len() { + let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0); + let e = result[i]; + let r = $alias(x); + assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e); + } + }; + } + #[simd_test(enable = "sse")] fn test_mm_cvtss_si32() { - let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1]; - let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520]; - for i in 0..inputs.len() { - let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0); - let e = result[i]; - let r = _mm_cvtss_si32(x); - assert_eq!( - e, r, - "TestCase #{} _mm_cvtss_si32({:?}) = {}, expected: {}", - i, x, r, e - ); - } + test_mm_cvtss_si32_impl!(_mm_cvtss_si32); + } + + #[simd_test(enable = "sse")] + fn test_mm_cvt_ss2si() { + test_mm_cvtss_si32_impl!(_mm_cvt_ss2si); + } + + macro_rules! test_cvttss_si32_impl { + ($alias:ident) => { + let inputs = &[ + (42.0f32, 42i32), + (-31.4, -31), + (-33.5, -33), + (-34.5, -34), + (10.999, 10), + (-5.99, -5), + (4.0e10, i32::MIN), + (4.0e-10, 0), + (NAN, i32::MIN), + (2147483500.1, 2147483520), + ]; + for (i, &(xi, e)) in inputs.iter().enumerate() { + let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0); + let r = $alias(x); + assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e); + } + }; } #[simd_test(enable = "sse")] fn test_mm_cvttss_si32() { - let inputs = &[ - (42.0f32, 42i32), - (-31.4, -31), - (-33.5, -33), - (-34.5, -34), - (10.999, 10), - (-5.99, -5), - (4.0e10, i32::MIN), - (4.0e-10, 0), - (NAN, i32::MIN), - (2147483500.1, 2147483520), - ]; - for (i, &(xi, e)) in inputs.iter().enumerate() { - let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0); - let r = _mm_cvttss_si32(x); - assert_eq!( - e, r, - "TestCase #{} _mm_cvttss_si32({:?}) = {}, expected: {}", - i, x, r, e - ); - } + test_cvttss_si32_impl!(_mm_cvttss_si32); } #[simd_test(enable = "sse")] - const fn test_mm_cvtsi32_ss() { - let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0); + fn test_mm_cvtt_ss2si() { + test_cvttss_si32_impl!(_mm_cvtt_ss2si); + } - let r = _mm_cvtsi32_ss(a, 4555); - let e = _mm_setr_ps(4555.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + macro_rules! test_mm_cvtsi32_ss_impl { + ($alias:ident) => { + let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0); - let r = _mm_cvtsi32_ss(a, 322223333); - let e = _mm_setr_ps(322223333.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + let r = $alias(a, 4555); + assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r); - let r = _mm_cvtsi32_ss(a, -432); - let e = _mm_setr_ps(-432.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + let r = $alias(a, 322223333); + assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r); - let r = _mm_cvtsi32_ss(a, -322223333); - let e = _mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + let r = $alias(a, -432); + assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r); + + let r = $alias(a, -322223333); + assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r); + }; + } + + #[simd_test(enable = "sse")] + const fn test_mm_cvtsi32_ss() { + test_mm_cvtsi32_ss_impl!(_mm_cvtsi32_ss); + } + + #[simd_test(enable = "sse")] + fn test_mm_cvt_si2ss() { + test_mm_cvtsi32_ss_impl!(_mm_cvt_si2ss); } #[simd_test(enable = "sse")] @@ -3071,18 +3092,24 @@ mod tests { assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0)); } + macro_rules! test_mm_set1_ps_impl { + ($alias:ident) => { + let r = $alias(black_box(4.25)); + assert_eq!(get_m128(r, 0), 4.25); + assert_eq!(get_m128(r, 1), 4.25); + assert_eq!(get_m128(r, 2), 4.25); + assert_eq!(get_m128(r, 3), 4.25); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_set1_ps() { - let r1 = _mm_set1_ps(black_box(4.25)); - let r2 = _mm_set_ps1(black_box(4.25)); - assert_eq!(get_m128(r1, 0), 4.25); - assert_eq!(get_m128(r1, 1), 4.25); - assert_eq!(get_m128(r1, 2), 4.25); - assert_eq!(get_m128(r1, 3), 4.25); - assert_eq!(get_m128(r2, 0), 4.25); - assert_eq!(get_m128(r2, 1), 4.25); - assert_eq!(get_m128(r2, 2), 4.25); - assert_eq!(get_m128(r2, 3), 4.25); + test_mm_set1_ps_impl!(_mm_set1_ps); + } + + #[simd_test(enable = "sse")] + const fn test_mm_set_ps1() { + test_mm_set1_ps_impl!(_mm_set_ps1); } #[simd_test(enable = "sse")] @@ -3171,11 +3198,22 @@ mod tests { assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0)); } + macro_rules! test_mm_load1_ps_impl { + ($alias:ident) => { + let a = 42.0f32; + let r = unsafe { $alias(ptr::addr_of!(a)) }; + assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_load1_ps() { - let a = 42.0f32; - let r = unsafe { _mm_load1_ps(ptr::addr_of!(a)) }; - assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)); + test_mm_load1_ps_impl!(_mm_load1_ps); + } + + #[simd_test(enable = "sse")] + const fn test_mm_load_ps1() { + test_mm_load1_ps_impl!(_mm_load_ps1); } #[simd_test(enable = "sse")] @@ -3227,19 +3265,24 @@ mod tests { assert_eq!(vals[2], 0.0); } + macro_rules! test_mm_store1_ps_impl { + ($alias:ident) => { + let mut vals = Memory { data: [0.0f32; 4] }; + let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); + let p = vals.data.as_mut_ptr(); + unsafe { $alias(p, *black_box(&a)) }; + assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_store1_ps() { - let mut vals = Memory { data: [0.0f32; 4] }; - let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); - - // guaranteed to be aligned to 16 bytes - let p = vals.data.as_mut_ptr(); - - unsafe { - _mm_store1_ps(p, *black_box(&a)); - } + test_mm_store1_ps_impl!(_mm_store1_ps); + } - assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]); + #[simd_test(enable = "sse")] + const fn test_mm_store_ps1() { + test_mm_store1_ps_impl!(_mm_store_ps1); } #[simd_test(enable = "sse")] diff --git a/stdarch/crates/core_arch/src/x86_64/amx.rs b/stdarch/crates/core_arch/src/x86_64/amx.rs index 03bbe3e449258..b3b3e86750ef2 100644 --- a/stdarch/crates/core_arch/src/x86_64/amx.rs +++ b/stdarch/crates/core_arch/src/x86_64/amx.rs @@ -252,7 +252,7 @@ pub unsafe fn _tile_cmmrlfp16ps() { #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-fp8")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tdpbf8ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -271,7 +271,7 @@ pub unsafe fn _tile_dpbf8ps() { #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-fp8")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tdpbhf8ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -290,7 +290,7 @@ pub unsafe fn _tile_dpbhf8ps() { #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-fp8")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tdphbf8ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -309,7 +309,7 @@ pub unsafe fn _tile_dphbf8ps() { #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-fp8")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tdphf8ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -329,7 +329,7 @@ pub unsafe fn _tile_dphf8ps() { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-movrs")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tileloaddrs, DST = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -349,7 +349,7 @@ pub unsafe fn _tile_loaddrs(base: *const u8, stride: usize) { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-movrs")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tileloaddrst1, DST = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -372,7 +372,7 @@ pub unsafe fn _tile_stream_loaddrs(base: *const u8, stride: usiz #[rustc_legacy_const_generics(0, 1, 2)] #[target_feature(enable = "amx-tf32")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tmmultf32ps, DST = 0, A = 1, B = 2) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -389,7 +389,7 @@ pub unsafe fn _tile_mmultf32ps() { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowd2ps, TILE = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -404,7 +404,7 @@ pub unsafe fn _tile_cvtrowd2ps(row: u32) -> __m512 { #[rustc_legacy_const_generics(0, 1)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowd2ps, TILE = 0, ROW = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -421,7 +421,7 @@ pub unsafe fn _tile_cvtrowd2psi() -> __m512 { #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2phh, TILE = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -437,7 +437,7 @@ pub unsafe fn _tile_cvtrowps2phh(row: u32) -> __m512h { #[rustc_legacy_const_generics(0, 1)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2phh, TILE = 0, ROW = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -454,7 +454,7 @@ pub unsafe fn _tile_cvtrowps2phhi() -> __m512h #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2phl, TILE = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -470,7 +470,7 @@ pub unsafe fn _tile_cvtrowps2phl(row: u32) -> __m512h { #[rustc_legacy_const_generics(0, 1)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tcvtrowps2phl, TILE = 0, ROW = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -480,12 +480,78 @@ pub unsafe fn _tile_cvtrowps2phli() -> __m512h tcvtrowps2phli(TILE as i8, ROW as u32).as_m512h() } +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2bf16h, TILE = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2bf16h(row: u32) -> __m512bh { + static_assert_uimm_bits!(TILE, 3); + tcvtrowps2bf16h(TILE as i8, row).as_m512bh() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2bf16h, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2bf16hi() -> __m512bh { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowps2bf16hi(TILE as i8, ROW as u32).as_m512bh() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2bf16l, TILE = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2bf16l(row: u32) -> __m512bh { + static_assert_uimm_bits!(TILE, 3); + tcvtrowps2bf16l(TILE as i8, row).as_m512bh() +} + +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed BF16 (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, not(target_vendor = "apple")), + assert_instr(tcvtrowps2bf16l, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2bf16li() -> __m512bh { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowps2bf16li(TILE as i8, ROW as u32).as_m512bh() +} + /// Moves one row of tile data into a zmm vector register #[inline] #[rustc_legacy_const_generics(0)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tilemovrow, TILE = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -499,7 +565,7 @@ pub unsafe fn _tile_movrow(row: u32) -> __m512i { #[rustc_legacy_const_generics(0, 1)] #[target_feature(enable = "amx-avx512,avx10.2")] #[cfg_attr( - all(test, any(target_os = "linux", target_env = "msvc")), + all(test, not(target_vendor = "apple")), assert_instr(tilemovrow, TILE = 0, ROW = 0) )] #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] @@ -567,6 +633,14 @@ unsafe extern "C" { fn tcvtrowps2phl(tile: i8, row: u32) -> f16x32; #[link_name = "llvm.x86.tcvtrowps2phli"] fn tcvtrowps2phli(tile: i8, row: u32) -> f16x32; + #[link_name = "llvm.x86.tcvtrowps2bf16h"] + fn tcvtrowps2bf16h(tile: i8, row: u32) -> u16x32; + #[link_name = "llvm.x86.tcvtrowps2bf16hi"] + fn tcvtrowps2bf16hi(tile: i8, row: u32) -> u16x32; + #[link_name = "llvm.x86.tcvtrowps2bf16l"] + fn tcvtrowps2bf16l(tile: i8, row: u32) -> u16x32; + #[link_name = "llvm.x86.tcvtrowps2bf16li"] + fn tcvtrowps2bf16li(tile: i8, row: u32) -> u16x32; #[link_name = "llvm.x86.tilemovrow"] fn tilemovrow(tile: i8, row: u32) -> i32x16; #[link_name = "llvm.x86.tilemovrowi"] @@ -1276,6 +1350,110 @@ mod tests { } } + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2bf16h() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowps2bf16h::<0>(i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + 0 + } else { + _mm_cvtness_sbh(i as _).to_bits() + }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2bf16hi() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowps2bf16hi::<0>, i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + 0 + } else { + _mm_cvtness_sbh(i as _).to_bits() + }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2bf16l() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowps2bf16l::<0>(i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + _mm_cvtness_sbh(i as _).to_bits() + } else { + 0 + }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2bf16li() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowps2bf16li::<0>, i); + assert_eq!( + *row.as_u16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { + _mm_cvtness_sbh(i as _).to_bits() + } else { + 0 + }) + ); + } + } + } + #[simd_test(enable = "amx-tf32")] fn test_tile_mmultf32ps() { unsafe { diff --git a/stdarch/crates/intrinsic-test/missing_aarch64_be.txt b/stdarch/crates/intrinsic-test/missing_aarch64_be.txt deleted file mode 100644 index f3c4ffa3d0640..0000000000000 --- a/stdarch/crates/intrinsic-test/missing_aarch64_be.txt +++ /dev/null @@ -1,129 +0,0 @@ -# Bad LLVM codegen for BE in O2 in clang, and release in rust (https://github.com/llvm/llvm-project/issues/166190) -vcmla_lane_f16 -vcmla_laneq_f16 -vcmla_rot180_lane_f16 -vcmla_rot180_laneq_f16 -vcmla_rot270_lane_f16 -vcmla_rot270_laneq_f16 -vcmla_rot90_lane_f16 -vcmla_rot90_laneq_f16 -vcmlaq_lane_f16 -vcmlaq_laneq_f16 -vcmlaq_laneq_f32 -vcmlaq_rot180_lane_f16 -vcmlaq_rot180_laneq_f16 -vcmlaq_rot180_laneq_f32 -vcmlaq_rot270_lane_f16 -vcmlaq_rot270_laneq_f16 -vcmlaq_rot270_laneq_f32 -vcmlaq_rot90_lane_f16 -vcmlaq_rot90_laneq_f16 -vcmlaq_rot90_laneq_f32 -# Bad codegen for BE in O2 in clang, correct in rust. Same cause as above issue. -vdot_lane_s32 -vdot_lane_u32 -vdot_laneq_s32 -vdot_laneq_u32 -vdotq_lane_s32 -vdotq_lane_u32 -vdotq_laneq_s32 -vdotq_laneq_u32 -vsudot_lane_s32 -vsudot_laneq_s32 -vsudotq_lane_s32 -vsudotq_laneq_s32 -vusdot_lane_s32 -vusdot_laneq_s32 -vusdotq_lane_s32 -vusdotq_laneq_s32 - -# Below are in common to missing_aarch64.txt -# Not supported by qemu (will throw illegal instruction) -vamax_f16 -vamaxq_f16 -vamin_f16 -vaminq_f16 -vscale_f16 -vscale_f32 -vscaleq_f16 -vscaleq_f32 -vscaleq_f64 -vluti2_lane_p16 -vluti2_lane_p8 -vluti2_lane_s16 -vluti2_lane_s8 -vluti2_lane_u16 -vluti2_lane_u8 -vluti2q_lane_p16 -vluti2q_lane_p8 -vluti2q_lane_s16 -vluti2q_lane_s8 -vluti2q_lane_u16 -vluti2_laneq_f16 -vluti2_lane_f16 -vluti2_laneq_f16 -vluti2_laneq_p16 -vluti2_laneq_p8 -vluti2_laneq_s16 -vluti2_laneq_s8 -vluti2_laneq_u16 -vluti2_laneq_u8 -vluti2q_lane_f16 -vluti2q_laneq_f16 -vluti2q_laneq_p16 -vluti2q_laneq_p8 -vluti2q_laneq_s16 -vluti2q_laneq_s8 -vluti2q_laneq_u16 -vluti2q_laneq_u8 -vluti2q_lane_u8 - -# Not implemented in stdarch yet -vbfdot_f32 -vbfdot_lane_f32 -vbfdot_laneq_f32 -vbfdotq_f32 -vbfdotq_lane_f32 -vbfdotq_laneq_f32 -vbfmlalbq_f32 -vbfmlalbq_lane_f32 -vbfmlalbq_laneq_f32 -vbfmlaltq_f32 -vbfmlaltq_lane_f32 -vbfmlaltq_laneq_f32 -vbfmmlaq_f32 - - -# Implemented in stdarch, but missing in Clang. -vrnd32xq_f64 -vrnd32zq_f64 -vrnd64xq_f64 -vrnd64zq_f64 -vamin_f32 -vaminq_f32 -vaminq_f64 -vamax_f32 -vamaxq_f32 -vamaxq_f64 -# LLVM select error, and missing in Clang. -vrnd32x_f64 -vrnd32z_f64 -vrnd64x_f64 -vrnd64z_f64 -vluti4q_lane_f16_x2 -vluti4q_lane_p16_x2 -vluti4q_lane_p8 -vluti4q_lane_s16_x2 -vluti4q_lane_s8 -vluti4q_lane_u16_x2 -vluti4q_lane_u8 -vluti4q_laneq_f16_x2 -vluti4q_laneq_p16_x2 -vluti4q_laneq_p8 -vluti4q_laneq_s16_x2 -vluti4q_laneq_s8 -vluti4q_laneq_u16_x2 -vluti4q_laneq_u8 - -# Broken in Clang -vcvth_s16_f16 diff --git a/stdarch/crates/intrinsic-test/missing_aarch64_be_clang.txt b/stdarch/crates/intrinsic-test/missing_aarch64_be_clang.txt new file mode 100644 index 0000000000000..001538b3ea504 --- /dev/null +++ b/stdarch/crates/intrinsic-test/missing_aarch64_be_clang.txt @@ -0,0 +1,31 @@ +# Bad LLVM codegen for BE in O2 in clang, and release in rust (https://github.com/llvm/llvm-project/issues/166190) +vcmla_laneq_f16 +vcmla_rot180_laneq_f16 +vcmla_rot270_laneq_f16 +vcmla_rot90_laneq_f16 +vcmlaq_lane_f16 +vcmlaq_laneq_f16 +vcmlaq_rot180_lane_f16 +vcmlaq_rot180_laneq_f16 +vcmlaq_rot270_lane_f16 +vcmlaq_rot270_laneq_f16 +vcmlaq_rot90_lane_f16 +vcmlaq_rot90_laneq_f16 + +# Bad codegen for BE in O2 in clang, correct in rust. Same cause as above issue. +vdot_lane_s32 +vdot_lane_u32 +vdot_laneq_s32 +vdot_laneq_u32 +vdotq_lane_s32 +vdotq_lane_u32 +vdotq_laneq_s32 +vdotq_laneq_u32 +vsudot_lane_s32 +vsudot_laneq_s32 +vsudotq_lane_s32 +vsudotq_laneq_s32 +vusdot_lane_s32 +vusdot_laneq_s32 +vusdotq_lane_s32 +vusdotq_laneq_s32 diff --git a/stdarch/crates/intrinsic-test/missing_aarch64.txt b/stdarch/crates/intrinsic-test/missing_aarch64_be_common.txt similarity index 69% rename from stdarch/crates/intrinsic-test/missing_aarch64.txt rename to stdarch/crates/intrinsic-test/missing_aarch64_be_common.txt index 3c1ac59e910e9..327c8207a0ff5 100644 --- a/stdarch/crates/intrinsic-test/missing_aarch64.txt +++ b/stdarch/crates/intrinsic-test/missing_aarch64_be_common.txt @@ -1,8 +1,14 @@ # Not supported by qemu (will throw illegal instruction) -vamax_f16 -vamaxq_f16 vamin_f16 vaminq_f16 +vamin_f32 +vaminq_f32 +vaminq_f64 +vamax_f16 +vamaxq_f16 +vamax_f32 +vamaxq_f32 +vamaxq_f64 vscale_f16 vscale_f32 vscaleq_f16 @@ -37,39 +43,6 @@ vluti2q_laneq_s8 vluti2q_laneq_u16 vluti2q_laneq_u8 vluti2q_lane_u8 - -# Not implemented in stdarch yet -vbfdot_f32 -vbfdot_lane_f32 -vbfdot_laneq_f32 -vbfdotq_f32 -vbfdotq_lane_f32 -vbfdotq_laneq_f32 -vbfmlalbq_f32 -vbfmlalbq_lane_f32 -vbfmlalbq_laneq_f32 -vbfmlaltq_f32 -vbfmlaltq_lane_f32 -vbfmlaltq_laneq_f32 -vbfmmlaq_f32 - - -# Implemented in stdarch, but missing in Clang. -vrnd32xq_f64 -vrnd32zq_f64 -vrnd64xq_f64 -vrnd64zq_f64 -vamin_f32 -vaminq_f32 -vaminq_f64 -vamax_f32 -vamaxq_f32 -vamaxq_f64 -# LLVM select error, and missing in Clang. -vrnd32x_f64 -vrnd32z_f64 -vrnd64x_f64 -vrnd64z_f64 vluti4q_lane_f16_x2 vluti4q_lane_p16_x2 vluti4q_lane_p8 @@ -85,5 +58,24 @@ vluti4q_laneq_s8 vluti4q_laneq_u16_x2 vluti4q_laneq_u8 -# Broken in Clang -vcvth_s16_f16 +# Not implemented in stdarch yet +vcvtad_s32_f64 +vcvtad_u32_f64 +vcvtd_s32_f64 +vcvtd_u32_f64 +vcvtmd_s32_f64 +vcvtmd_u32_f64 +vcvtnd_s32_f64 +vcvtnd_u32_f64 +vcvtpd_s32_f64 +vcvtpd_u32_f64 +vcvts_s64_f32 +vcvts_u64_f32 +vcvtas_s64_f32 +vcvtas_u64_f32 +vcvtms_s64_f32 +vcvtms_u64_f32 +vcvtns_s64_f32 +vcvtns_u64_f32 +vcvtps_s64_f32 +vcvtps_u64_f32 diff --git a/stdarch/crates/intrinsic-test/missing_aarch64_be_gcc.txt b/stdarch/crates/intrinsic-test/missing_aarch64_be_gcc.txt new file mode 100644 index 0000000000000..eccd8a8a14dff --- /dev/null +++ b/stdarch/crates/intrinsic-test/missing_aarch64_be_gcc.txt @@ -0,0 +1,20 @@ +# Broken in LLVM llvm/llvm-project#196999 +vmull_p64 +vmull_high_p64 + +# Broken in LLVM llvm/llvm-project#197083 +vcvth_n_s32_f16 +vcvth_n_u32_f16 +vcvth_n_s64_f16 +vcvth_n_u64_f16 +vcvth_n_f16_s32 +vcvth_n_f16_u32 +vcvth_n_f16_s64 +vcvth_n_f16_u64 + +# Broken in GCC https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125279 +vmaxh_f16 +vminh_f16 + +# Rounding errors +vfms_n_f64 diff --git a/stdarch/crates/intrinsic-test/missing_aarch64_clang.txt b/stdarch/crates/intrinsic-test/missing_aarch64_clang.txt new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/stdarch/crates/intrinsic-test/missing_aarch64_common.txt b/stdarch/crates/intrinsic-test/missing_aarch64_common.txt new file mode 100644 index 0000000000000..327c8207a0ff5 --- /dev/null +++ b/stdarch/crates/intrinsic-test/missing_aarch64_common.txt @@ -0,0 +1,81 @@ +# Not supported by qemu (will throw illegal instruction) +vamin_f16 +vaminq_f16 +vamin_f32 +vaminq_f32 +vaminq_f64 +vamax_f16 +vamaxq_f16 +vamax_f32 +vamaxq_f32 +vamaxq_f64 +vscale_f16 +vscale_f32 +vscaleq_f16 +vscaleq_f32 +vscaleq_f64 +vluti2_lane_p16 +vluti2_lane_p8 +vluti2_lane_s16 +vluti2_lane_s8 +vluti2_lane_u16 +vluti2_lane_u8 +vluti2q_lane_p16 +vluti2q_lane_p8 +vluti2q_lane_s16 +vluti2q_lane_s8 +vluti2q_lane_u16 +vluti2_laneq_f16 +vluti2_lane_f16 +vluti2_laneq_f16 +vluti2_laneq_p16 +vluti2_laneq_p8 +vluti2_laneq_s16 +vluti2_laneq_s8 +vluti2_laneq_u16 +vluti2_laneq_u8 +vluti2q_lane_f16 +vluti2q_laneq_f16 +vluti2q_laneq_p16 +vluti2q_laneq_p8 +vluti2q_laneq_s16 +vluti2q_laneq_s8 +vluti2q_laneq_u16 +vluti2q_laneq_u8 +vluti2q_lane_u8 +vluti4q_lane_f16_x2 +vluti4q_lane_p16_x2 +vluti4q_lane_p8 +vluti4q_lane_s16_x2 +vluti4q_lane_s8 +vluti4q_lane_u16_x2 +vluti4q_lane_u8 +vluti4q_laneq_f16_x2 +vluti4q_laneq_p16_x2 +vluti4q_laneq_p8 +vluti4q_laneq_s16_x2 +vluti4q_laneq_s8 +vluti4q_laneq_u16_x2 +vluti4q_laneq_u8 + +# Not implemented in stdarch yet +vcvtad_s32_f64 +vcvtad_u32_f64 +vcvtd_s32_f64 +vcvtd_u32_f64 +vcvtmd_s32_f64 +vcvtmd_u32_f64 +vcvtnd_s32_f64 +vcvtnd_u32_f64 +vcvtpd_s32_f64 +vcvtpd_u32_f64 +vcvts_s64_f32 +vcvts_u64_f32 +vcvtas_s64_f32 +vcvtas_u64_f32 +vcvtms_s64_f32 +vcvtms_u64_f32 +vcvtns_s64_f32 +vcvtns_u64_f32 +vcvtps_s64_f32 +vcvtps_u64_f32 diff --git a/stdarch/crates/intrinsic-test/missing_aarch64_gcc.txt b/stdarch/crates/intrinsic-test/missing_aarch64_gcc.txt new file mode 100644 index 0000000000000..a7e90142e4bcd --- /dev/null +++ b/stdarch/crates/intrinsic-test/missing_aarch64_gcc.txt @@ -0,0 +1,19 @@ +# Broken in GCC https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123584, fixed in GCC 16 +vxarq_u64 + +# Broken in LLVM llvm/llvm-project#197083 +vcvth_n_s32_f16 +vcvth_n_u32_f16 +vcvth_n_s64_f16 +vcvth_n_u64_f16 +vcvth_n_f16_s32 +vcvth_n_f16_u32 +vcvth_n_f16_s64 +vcvth_n_f16_u64 + +# Broken in GCC https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125279 +vmaxh_f16 +vminh_f16 + +# Rounding errors +vfms_n_f64 diff --git a/stdarch/crates/intrinsic-test/missing_arm_clang.txt b/stdarch/crates/intrinsic-test/missing_arm_clang.txt new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/stdarch/crates/intrinsic-test/missing_arm.txt b/stdarch/crates/intrinsic-test/missing_arm_common.txt similarity index 95% rename from stdarch/crates/intrinsic-test/missing_arm.txt rename to stdarch/crates/intrinsic-test/missing_arm_common.txt index 04c09a27d90d4..165b45d50cf1f 100644 --- a/stdarch/crates/intrinsic-test/missing_arm.txt +++ b/stdarch/crates/intrinsic-test/missing_arm_common.txt @@ -1,18 +1,3 @@ -# Not implemented in stdarch yet -vbfdot_f32 -vbfdot_lane_f32 -vbfdot_laneq_f32 -vbfdotq_f32 -vbfdotq_lane_f32 -vbfdotq_laneq_f32 -vbfmlalbq_f32 -vbfmlalbq_lane_f32 -vbfmlalbq_laneq_f32 -vbfmlaltq_f32 -vbfmlaltq_lane_f32 -vbfmlaltq_laneq_f32 -vbfmmlaq_f32 - # Implemented in Clang and stdarch for A64 only even though CSV claims A32 support vaddq_p64 vbsl_p64 @@ -134,18 +119,6 @@ vcvth_f16_u32 vcvth_u32_f16 vcvth_n_f16_u32 vcvth_n_u32_f16 -vcvtah_s32_f16 -vcvtah_u32_f16 -vcvtmh_s32_f16 -vcvtmh_u32_f16 -vcvtpq_s16_f16 -vcvtpq_u16_f16 -vcvtp_s16_f16 -vcvtp_u16_f16 -vcvtph_s32_f16 -vcvtph_u32_f16 -vcvtnh_u32_f16 -vcvtnh_s32_f16 vfmlsl_low_f16 vfmlslq_low_f16 vfmlsl_high_f16 @@ -318,3 +291,25 @@ vcvta_s16_f16 vcvta_u16_f16 vceqz_f16 vceqzq_f16 +vcvtah_s32_f16 +vcvtah_u32_f16 +vcvtmh_s32_f16 +vcvtmh_u32_f16 +vcvtpq_s16_f16 +vcvtpq_u16_f16 +vcvtp_s16_f16 +vcvtp_u16_f16 +vcvtph_s32_f16 +vcvtph_u32_f16 +vcvtnh_u32_f16 +vcvtnh_s32_f16 + +# Missing in Clang +vusdot_laneq_s32 +vsudot_laneq_s32 +vusdotq_laneq_s32 +vsudotq_laneq_s32 +vdot_laneq_s32 +vdot_laneq_u32 +vdotq_laneq_s32 +vdotq_laneq_u32 diff --git a/stdarch/crates/intrinsic-test/missing_x86_clang.txt b/stdarch/crates/intrinsic-test/missing_x86_clang.txt new file mode 100644 index 0000000000000..b1531830c1a19 --- /dev/null +++ b/stdarch/crates/intrinsic-test/missing_x86_clang.txt @@ -0,0 +1,24 @@ +# not present in Clang +_bswap +_bswap64 +_mm_cvtsd_si64x +_mm_cvtsi128_si64x +_mm_cvtsi64x_sd +_mm_cvtsi64x_si128 +_mm_cvttsd_si64x +_popcnt32 +_popcnt64 + +# Clang bug +_mm512_mask_reduce_max_pd +_mm512_mask_reduce_max_ps +_mm512_mask_reduce_min_pd +_mm512_mask_reduce_min_ps + +# Rounding errors in release mode +_mm_maskz_fmadd_sd +_mm_maskz_fmadd_ss +_mm_maskz_fmsub_sd +_mm_maskz_fmsub_ss +_mm_maskz_fnmadd_sd +_mm_maskz_fnmadd_ss diff --git a/stdarch/crates/intrinsic-test/missing_x86.txt b/stdarch/crates/intrinsic-test/missing_x86_common.txt similarity index 52% rename from stdarch/crates/intrinsic-test/missing_x86.txt rename to stdarch/crates/intrinsic-test/missing_x86_common.txt index f88a125bfdff8..f9b71bbe8c2ca 100644 --- a/stdarch/crates/intrinsic-test/missing_x86.txt +++ b/stdarch/crates/intrinsic-test/missing_x86_common.txt @@ -1,19 +1,22 @@ -# Are defined under a similar name - -#__bswap_64 -_bswap64 - -# not present in Clang and Rust +# not present in Rust _bit_scan_forward _bit_scan_reverse _castf32_u32 _castf64_u64 _castu32_f32 _castu64_f64 +_cvtsh_ss +_cvtss_sh _lrotl _lrotr _may_i_use_cpu_feature _may_i_use_cpu_feature_ext +_mm256_set1_pch +_mm512_set1_pch +_mm_malloc +_mm_popcnt_u32 +_mm_popcnt_u64 +_mm_set1_pch _rdpmc _rotl _rotl64 @@ -21,47 +24,25 @@ _rotr _rotr64 _rotwl _rotwr -_urdmsr - -# not present in Clang -_bswap -_mm_cvtsd_si64x -_mm_cvtsi128_si64x -_mm_cvtsi64x_sd -_mm_cvtsi64x_si128 -_mm_cvttsd_si64x -_popcnt32 -_popcnt64 - -# not present in Rust -_cvtsh_ss -_cvtss_sh -_mm256_set1_pch -_mm512_set1_pch -_mm_malloc -_mm_popcnt_u32 -_mm_popcnt_u64 -_mm_set1_pch _tpause _umwait - -# IMM8 must be an even number in the range `0..=62` -_mm_sm3rnds2_epi32 +_urdmsr # SDE ERROR: Cannot execute XGETBV with ECX != 0 _xgetbv # top bits are undefined, unclear how to test these +_mm256_castph128_ph256 +_mm256_castps128_ps256 +_mm256_castpd128_pd256 _mm256_castsi128_si256 + +_mm512_castph128_ph512 +_mm512_castps128_ps512 +_mm512_castpd128_pd512 _mm512_castsi128_si512 -_mm512_castsi256_si512 -# Clang bug -_mm256_extract_epi16 -_mm256_extract_epi8 -_mm512_mask_reduce_max_pd -_mm512_mask_reduce_max_ps -_mm512_mask_reduce_min_pd -_mm512_mask_reduce_min_ps -_mm_extract_epi16 -_mm_extract_epi8 +_mm512_castph256_ph512 +_mm512_castps256_ps512 +_mm512_castpd256_pd512 +_mm512_castsi256_si512 diff --git a/stdarch/crates/intrinsic-test/missing_x86_gcc.txt b/stdarch/crates/intrinsic-test/missing_x86_gcc.txt new file mode 100644 index 0000000000000..5b71b0698eafc --- /dev/null +++ b/stdarch/crates/intrinsic-test/missing_x86_gcc.txt @@ -0,0 +1,33 @@ +# not present in GCC +_bextr2_u32 +_bextr2_u64 +_mm512_cvtepi32lo_pd +_mm512_mask_cvtepi32lo_pd +_mm512_cvtepu32lo_pd +_mm512_mask_cvtepu32lo_pd +_mm512_cvtpd_pslo +_mm512_mask_cvtpd_pslo +_mm512_cvtpslo_pd +_mm512_mask_cvtpslo_pd +_mm512_permutevar_epi32 +_mm512_mask_permutevar_epi32 +_mm_tzcnt_32 +_mm_tzcnt_64 + +# GCC bug +_mm512_reduce_max_pd +_mm512_reduce_max_ps +_mm512_reduce_min_pd +_mm512_reduce_min_ps +_mm512_mask_reduce_max_pd +_mm512_mask_reduce_max_ps +_mm512_mask_reduce_min_pd +_mm512_mask_reduce_min_ps + +# Rounding errors in release mode +_mm_maskz_fmadd_sd +_mm_maskz_fmadd_ss +_mm_maskz_fmsub_sd +_mm_maskz_fmsub_ss +_mm_maskz_fnmadd_sd +_mm_maskz_fnmadd_ss diff --git a/stdarch/crates/intrinsic-test/missing_x86_icx.txt b/stdarch/crates/intrinsic-test/missing_x86_icx.txt new file mode 100644 index 0000000000000..6d3133c85db9c --- /dev/null +++ b/stdarch/crates/intrinsic-test/missing_x86_icx.txt @@ -0,0 +1,20 @@ +# not present in ICX +_mm_cvtsd_si64x +_mm_cvtsi128_si64x +_mm_cvtsi64x_sd +_mm_cvtsi64x_si128 +_mm_cvttsd_si64x + +# ICX bug +_mm512_mask_reduce_max_pd +_mm512_mask_reduce_max_ps +_mm512_mask_reduce_min_pd +_mm512_mask_reduce_min_ps + +# Rounding errors in release mode +_mm_maskz_fmadd_sd +_mm_maskz_fmadd_ss +_mm_maskz_fmsub_sd +_mm_maskz_fmsub_ss +_mm_maskz_fnmadd_sd +_mm_maskz_fnmadd_ss diff --git a/stdarch/crates/intrinsic-test/src/arm/argument.rs b/stdarch/crates/intrinsic-test/src/arm/argument.rs deleted file mode 100644 index c43609bb2db0d..0000000000000 --- a/stdarch/crates/intrinsic-test/src/arm/argument.rs +++ /dev/null @@ -1,15 +0,0 @@ -use crate::arm::intrinsic::ArmIntrinsicType; -use crate::common::argument::Argument; - -// This functionality is present due to the nature -// of how intrinsics are defined in the JSON source -// of ARM intrinsics. -impl Argument { - pub fn type_and_name_from_c(arg: &str) -> (&str, &str) { - let split_index = arg - .rfind([' ', '*']) - .expect("Couldn't split type and argname"); - - (arg[..split_index + 1].trim_end(), &arg[split_index + 1..]) - } -} diff --git a/stdarch/crates/intrinsic-test/src/arm/compile.rs b/stdarch/crates/intrinsic-test/src/arm/compile.rs deleted file mode 100644 index 7da35f9a1114b..0000000000000 --- a/stdarch/crates/intrinsic-test/src/arm/compile.rs +++ /dev/null @@ -1,51 +0,0 @@ -use crate::common::cli::ProcessedCli; -use crate::common::compile_c::{CompilationCommandBuilder, CppCompilation}; - -pub fn build_cpp_compilation(config: &ProcessedCli) -> Option { - let cpp_compiler = config.cpp_compiler.as_ref()?; - - // -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations - let mut command = CompilationCommandBuilder::new() - .add_arch_flags(["armv8.6-a", "crypto", "crc", "dotprod", "fp16"]) - .set_compiler(cpp_compiler) - .set_target(&config.target) - .set_opt_level("2") - .set_cxx_toolchain_dir(config.cxx_toolchain_dir.as_deref()) - .set_project_root("c_programs") - .add_extra_flags(["-ffp-contract=off", "-Wno-narrowing"]); - - if !config.target.contains("v7") { - command = command.add_arch_flags(["faminmax", "lut", "sha3"]); - } - - if !cpp_compiler.contains("clang") { - command = command.add_extra_flag("-flax-vector-conversions"); - } - - let mut cpp_compiler = command.into_cpp_compilation(); - - if config.target.contains("aarch64_be") { - let Some(ref cxx_toolchain_dir) = config.cxx_toolchain_dir else { - panic!( - "target `{}` must specify `cxx_toolchain_dir`", - config.target - ) - }; - - cpp_compiler.command_mut().args([ - &format!("--sysroot={cxx_toolchain_dir}/aarch64_be-none-linux-gnu/libc"), - "--include-directory", - &format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/include/c++/14.3.1"), - "--include-directory", - &format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/include/c++/14.3.1/aarch64_be-none-linux-gnu"), - "-L", - &format!("{cxx_toolchain_dir}/lib/gcc/aarch64_be-none-linux-gnu/14.3.1"), - "-L", - &format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/libc/usr/lib"), - "-B", - &format!("{cxx_toolchain_dir}/lib/gcc/aarch64_be-none-linux-gnu/14.3.1"), - ]); - } - - Some(cpp_compiler) -} diff --git a/stdarch/crates/intrinsic-test/src/arm/config.rs b/stdarch/crates/intrinsic-test/src/arm/config.rs index 85cb21c2d6c4e..87b8ebfa183e7 100644 --- a/stdarch/crates/intrinsic-test/src/arm/config.rs +++ b/stdarch/crates/intrinsic-test/src/arm/config.rs @@ -3,51 +3,6 @@ pub const NOTICE: &str = "\ // test are derived from a JSON specification, published under the same license as the // `intrinsic-test` crate.\n"; -pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#" -#ifdef __aarch64__ -std::ostream& operator<<(std::ostream& os, poly128_t value); -#endif - -std::ostream& operator<<(std::ostream& os, float16_t value); -std::ostream& operator<<(std::ostream& os, uint8_t value); - -// T1 is the `To` type, T2 is the `From` type -template T1 cast(T2 x) { - static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same"); - T1 ret{}; - memcpy(&ret, &x, sizeof(T1)); - return ret; -} -"#; - -pub const PLATFORM_C_DEFINITIONS: &str = r#" -#ifdef __aarch64__ -std::ostream& operator<<(std::ostream& os, poly128_t value) { - std::stringstream temp; - do { - int n = value % 10; - value /= 10; - temp << n; - } while (value != 0); - std::string tempstr(temp.str()); - std::string res(tempstr.rbegin(), tempstr.rend()); - os << res; - return os; -} - -#endif - -std::ostream& operator<<(std::ostream& os, float16_t value) { - os << static_cast(value); - return os; -} - -std::ostream& operator<<(std::ostream& os, uint8_t value) { - os << (unsigned int) value; - return os; -} -"#; - pub const PLATFORM_RUST_DEFINITIONS: &str = ""; pub const PLATFORM_RUST_CFGS: &str = r#" @@ -58,8 +13,9 @@ pub const PLATFORM_RUST_CFGS: &str = r#" #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))] #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))] #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))] -#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_aarch64_jscvt))] -#![feature(fmt_helpers_for_derive)] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_feat_lut))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fp8))] +#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(faminmax))] #![feature(stdarch_neon_f16)] #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] diff --git a/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs b/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs index 29343bee4c300..a54e5857192e0 100644 --- a/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs +++ b/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs @@ -2,21 +2,18 @@ use crate::common::intrinsic_helpers::IntrinsicType; use std::ops::{Deref, DerefMut}; #[derive(Debug, Clone, PartialEq)] -pub struct ArmIntrinsicType { - pub data: IntrinsicType, - pub target: String, -} +pub struct ArmIntrinsicType(pub IntrinsicType); impl Deref for ArmIntrinsicType { type Target = IntrinsicType; fn deref(&self) -> &Self::Target { - &self.data + &self.0 } } impl DerefMut for ArmIntrinsicType { fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.data + &mut self.0 } } diff --git a/stdarch/crates/intrinsic-test/src/arm/json_parser.rs b/stdarch/crates/intrinsic-test/src/arm/json_parser.rs index 65c179ef0d083..06cf78a422285 100644 --- a/stdarch/crates/intrinsic-test/src/arm/json_parser.rs +++ b/stdarch/crates/intrinsic-test/src/arm/json_parser.rs @@ -1,8 +1,9 @@ use super::intrinsic::ArmIntrinsicType; +use crate::arm::types::parse_intrinsic_type; use crate::common::argument::{Argument, ArgumentList}; use crate::common::constraint::Constraint; use crate::common::intrinsic::Intrinsic; -use crate::common::intrinsic_helpers::IntrinsicType; +use crate::common::intrinsic_helpers::{IntrinsicType, TypeKind}; use serde::Deserialize; use serde_json::Value; use std::collections::HashMap; @@ -12,6 +13,8 @@ use std::path::Path; #[serde(deny_unknown_fields)] struct ReturnType { value: String, + #[serde(rename = "element_bit_size")] + _element_bit_size: Option, } #[derive(Deserialize, Debug)] @@ -50,11 +53,12 @@ struct JsonIntrinsic { args_prep: Option>, #[serde(rename = "Architectures")] architectures: Vec, + #[serde(rename = "instructions")] + _instructions: Option>>, } pub fn get_neon_intrinsics( filename: &Path, - target: &str, ) -> Result>, Box> { let file = std::fs::File::open(filename)?; let reader = std::io::BufReader::new(file); @@ -64,7 +68,7 @@ pub fn get_neon_intrinsics( .into_iter() .filter_map(|intr| { if intr.simd_isa == "Neon" { - Some(json_to_intrinsic(intr, target).expect("Couldn't parse JSON")) + Some(json_to_intrinsic(intr).expect("Couldn't parse JSON")) } else { None } @@ -75,32 +79,58 @@ pub fn get_neon_intrinsics( fn json_to_intrinsic( mut intr: JsonIntrinsic, - target: &str, ) -> Result, Box> { let name = intr.name.replace(['[', ']'], ""); - let results = ArmIntrinsicType::from_c(&intr.return_type.value, target)?; + let result_ty = ArmIntrinsicType(parse_intrinsic_type(&intr.return_type.value)?); let args = intr .arguments .into_iter() .enumerate() .map(|(i, arg)| { - let (type_name, arg_name) = Argument::::type_and_name_from_c(&arg); + let (type_name, arg_name) = { + let split_index = arg + .rfind([' ', '*']) + .expect("Couldn't split type and argname"); + + (arg[..split_index + 1].trim_end(), &arg[split_index + 1..]) + }; + + let arg_ty = parse_intrinsic_type(type_name) + .unwrap_or_else(|_| panic!("Failed to parse argument '{arg}'")); + let metadata = intr.args_prep.as_mut(); let metadata = metadata.and_then(|a| a.remove(arg_name)); let arg_prep: Option = metadata.and_then(|a| a.try_into().ok()); - let constraint: Option = arg_prep.and_then(|a| a.try_into().ok()); - let ty = ArmIntrinsicType::from_c(type_name, target) - .unwrap_or_else(|_| panic!("Failed to parse argument '{arg}'")); - - let mut arg = - Argument::::new(i, String::from(arg_name), ty, constraint); + let constraint: Option = + arg_prep.and_then(|a| a.try_into().ok()).or_else(|| { + if arg_ty.kind() == TypeKind::SvPattern { + Some(Constraint::SvPattern) + } else if arg_ty.kind() == TypeKind::SvPrefetchOp { + Some(Constraint::SvPrefetchOp) + } else if arg_name == "imm_rotation" { + if name.starts_with("svcadd_") || name.starts_with("svqcadd_") { + Some(Constraint::SvImmRotationAdd) + } else { + Some(Constraint::SvImmRotation) + } + } else { + None + } + }); + + let mut arg = Argument::::new( + i, + String::from(arg_name), + ArmIntrinsicType(arg_ty), + constraint, + ); // The JSON doesn't list immediates as const let IntrinsicType { ref mut constant, .. - } = arg.ty.data; + } = *arg.ty; if arg.name.starts_with("imm") { *constant = true } @@ -113,7 +143,7 @@ fn json_to_intrinsic( Ok(Intrinsic { name, arguments, - results, + results: result_ty, arch_tags: intr.architectures, }) } diff --git a/stdarch/crates/intrinsic-test/src/arm/mod.rs b/stdarch/crates/intrinsic-test/src/arm/mod.rs index 99c8da854c506..378f23ba7c361 100644 --- a/stdarch/crates/intrinsic-test/src/arm/mod.rs +++ b/stdarch/crates/intrinsic-test/src/arm/mod.rs @@ -1,13 +1,10 @@ -mod argument; -mod compile; mod config; mod intrinsic; mod json_parser; mod types; use crate::common::SupportedArchitectureTest; -use crate::common::cli::ProcessedCli; -use crate::common::compile_c::CppCompilation; +use crate::common::cli::{CcArgStyle, ProcessedCli}; use crate::common::intrinsic::Intrinsic; use crate::common::intrinsic_helpers::TypeKind; use intrinsic::ArmIntrinsicType; @@ -15,16 +12,11 @@ use json_parser::get_neon_intrinsics; pub struct ArmArchitectureTest { intrinsics: Vec>, - cli_options: ProcessedCli, } impl SupportedArchitectureTest for ArmArchitectureTest { type IntrinsicImpl = ArmIntrinsicType; - fn cli_options(&self) -> &ProcessedCli { - &self.cli_options - } - fn intrinsics(&self) -> &[Intrinsic] { &self.intrinsics } @@ -32,20 +24,22 @@ impl SupportedArchitectureTest for ArmArchitectureTest { const NOTICE: &str = config::NOTICE; const PLATFORM_C_HEADERS: &[&str] = &["arm_neon.h", "arm_acle.h", "arm_fp16.h"]; - const PLATFORM_C_DEFINITIONS: &str = config::PLATFORM_C_DEFINITIONS; - const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::PLATFORM_C_FORWARD_DECLARATIONS; const PLATFORM_RUST_DEFINITIONS: &str = config::PLATFORM_RUST_DEFINITIONS; const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS; - fn cpp_compilation(&self) -> Option { - compile::build_cpp_compilation(&self.cli_options) + fn arch_flags(&self, cli_options: &ProcessedCli) -> Vec<&str> { + // GCC uses an extra `-` in the arch name + match cli_options.cc_arg_style { + CcArgStyle::Clang => vec!["-march=armv8.6a+crypto+crc+dotprod+fp16"], + CcArgStyle::Gcc => vec!["-march=armv8.6-a+crypto+crc+dotprod+fp16+sha3+sm4"], + } } - fn create(cli_options: ProcessedCli) -> Self { - let a32 = cli_options.target.contains("v7"); - let mut intrinsics = get_neon_intrinsics(&cli_options.filename, &cli_options.target) - .expect("Error parsing input file"); + fn create(cli_options: &ProcessedCli) -> Self { + let a32 = cli_options.target.starts_with("armv7"); + let mut intrinsics = + get_neon_intrinsics(&cli_options.filename).expect("Error parsing input file"); intrinsics.sort_by(|a, b| a.name.cmp(&b.name)); intrinsics.dedup(); @@ -55,22 +49,23 @@ impl SupportedArchitectureTest for ArmArchitectureTest { let intrinsics = intrinsics .into_iter() - // Not sure how we would compare intrinsic that returns void. + // Skip intrinsics that don't return a value. .filter(|i| i.results.kind() != TypeKind::Void) + // Skip bfloat intrinsics - not currently supported .filter(|i| i.results.kind() != TypeKind::BFloat) .filter(|i| !i.arguments.iter().any(|a| a.ty.kind() == TypeKind::BFloat)) // Skip pointers for now, we would probably need to look at the return // type to work out how many elements we need to point to. .filter(|i| !i.arguments.iter().any(|a| a.is_ptr())) + // Skip intrinsics with 128-bit elements (e.g. `p128`) .filter(|i| !i.arguments.iter().any(|a| a.ty.inner_size() == 128)) + // Skip intrinsics from `--skip` .filter(|i| !cli_options.skip.contains(&i.name)) + // Skip A64-specific intrinsics on A32 .filter(|i| !(a32 && i.arch_tags == vec!["A64".to_string()])) .take(sample_size) .collect::>(); - Self { - intrinsics, - cli_options, - } + Self { intrinsics } } } diff --git a/stdarch/crates/intrinsic-test/src/arm/types.rs b/stdarch/crates/intrinsic-test/src/arm/types.rs index 4be8d1e48b49a..cd420f10678fc 100644 --- a/stdarch/crates/intrinsic-test/src/arm/types.rs +++ b/stdarch/crates/intrinsic-test/src/arm/types.rs @@ -1,19 +1,24 @@ use super::intrinsic::ArmIntrinsicType; -use crate::common::cli::Language; -use crate::common::indentation::Indentation; -use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind}; +use crate::common::intrinsic_helpers::{ + IntrinsicType, IntrinsicTypeDefinition, Sign, SimdLen, TypeKind, +}; impl IntrinsicTypeDefinition for ArmIntrinsicType { /// Gets a string containing the typename for this type in C format. fn c_type(&self) -> String { let prefix = self.kind.c_prefix(); - let const_prefix = if self.constant { "const " } else { "" }; - if let (Some(bit_len), simd_len, vec_len) = (self.bit_len, self.simd_len, self.vec_len) { - match (simd_len, vec_len) { - (None, None) => format!("{const_prefix}{prefix}{bit_len}_t"), - (Some(simd), None) => format!("{prefix}{bit_len}x{simd}_t"), - (Some(simd), Some(vec)) => format!("{prefix}{bit_len}x{simd}x{vec}_t"), + if let Some(bit_len) = self.bit_len { + match (self.simd_len, self.vec_len) { + (None, None) => format!("{prefix}{bit_len}_t"), + (Some(SimdLen::Fixed(simd)), None) => format!("{prefix}{bit_len}x{simd}_t"), + (Some(SimdLen::Fixed(simd)), Some(vec)) => { + format!("{prefix}{bit_len}x{simd}x{vec}_t") + } + (Some(SimdLen::Scalable), None) => format!("sv{prefix}{bit_len}_t"), + (Some(SimdLen::Scalable), Some(vec)) => { + format!("sv{prefix}{bit_len}x{vec}_t") + } (None, Some(_)) => todo!("{self:#?}"), // Likely an invalid case } } else { @@ -21,43 +26,46 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType { } } - fn c_single_vector_type(&self) -> String { - if let (Some(bit_len), Some(simd_len)) = (self.bit_len, self.simd_len) { - format!( - "{prefix}{bit_len}x{simd_len}_t", - prefix = self.kind.c_prefix() - ) + fn rust_type(&self) -> String { + let rust_prefix = self.kind.rust_prefix(); + let c_prefix = self.kind.c_prefix(); + + if let Some(bit_len) = self.bit_len { + match (self.simd_len, self.vec_len) { + (None, None) => format!("{rust_prefix}{bit_len}"), + (Some(SimdLen::Fixed(simd)), None) => format!("{c_prefix}{bit_len}x{simd}_t"), + (Some(SimdLen::Fixed(simd)), Some(vec)) => { + format!("{c_prefix}{bit_len}x{simd}x{vec}_t") + } + (Some(SimdLen::Scalable), None) => format!("sv{c_prefix}{bit_len}_t"), + (Some(SimdLen::Scalable), Some(vec)) => { + format!("sv{c_prefix}{bit_len}x{vec}_t") + } + (None, Some(_)) => todo!("{self:#?}"), // Likely an invalid case + } } else { - unreachable!("Shouldn't be called on this type") + todo!("{self:#?}") } } /// Determines the load function for this type. - fn get_load_function(&self, language: Language) -> String { + fn get_load_function(&self) -> String { if let IntrinsicType { kind: k, bit_len: Some(bl), - simd_len, vec_len, .. - } = &self.data + } = **self { - let quad = if simd_len.unwrap_or(1) * bl > 64 { - "q" - } else { - "" - }; + let quad = if self.num_lanes() * bl > 64 { "q" } else { "" }; - let choose_workaround = language == Language::C && self.target.contains("v7"); format!( "vld{len}{quad}_{type}{size}", type = match k { TypeKind::Int(Sign::Unsigned) => "u", TypeKind::Int(Sign::Signed) => "s", TypeKind::Float => "f", - // The ACLE doesn't support 64-bit polynomial loads on Armv7 - // if armv7 and bl == 64, use "s", else "p" - TypeKind::Poly => if choose_workaround && *bl == 64 {"s"} else {"p"}, + TypeKind::Poly => "p", x => todo!("get_load_function TypeKind: {x:#?}"), }, size = bl, @@ -68,172 +76,101 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType { todo!("get_load_function IntrinsicType: {self:#?}") } } +} - /// Determines the get lane function for this type. - fn get_lane_function(&self) -> String { - if let IntrinsicType { - kind: k, - bit_len: Some(bl), - simd_len, - .. - } = &self.data - { - let quad = if (simd_len.unwrap_or(1) * bl) > 64 { - "q" - } else { - "" - }; - format!( - "vget{quad}_lane_{type}{size}", - type = match k { - TypeKind::Int(Sign::Unsigned) => "u", - TypeKind::Int(Sign::Signed) => "s", - TypeKind::Float => "f", - TypeKind::Poly => "p", - x => todo!("get_load_function TypeKind: {x:#?}"), - }, - size = bl, - quad = quad, - ) - } else { - todo!("get_lane_function IntrinsicType: {self:#?}") - } - } +pub fn parse_intrinsic_type(s: &str) -> Result { + const CONST_STR: &str = "const"; + const ENUM_STR: &str = "enum "; - /// Generates a std::cout for the intrinsics results that will match the - /// rust debug output format for the return type. The generated line assumes - /// there is an int i in scope which is the current pass number. - fn print_result_c(&self, indentation: Indentation, additional: &str) -> String { - let lanes = if self.num_vectors() > 1 { - (0..self.num_vectors()) - .map(|vector| { - format!( - r#""{ty}(" << {lanes} << ")""#, - ty = self.c_single_vector_type(), - lanes = (0..self.num_lanes()) - .map(move |idx| -> std::string::String { - let lane_fn = self.get_lane_function(); - let final_cast = self.generate_final_type_cast(); - format!( - "{final_cast}{lane_fn}(__return_value.val[{vector}], {idx})" - ) - }) - .collect::>() - .join(r#" << ", " << "#) - ) - }) - .collect::>() - .join(r#" << ", " << "#) - } else if self.num_lanes() > 1 { - (0..self.num_lanes()) - .map(|idx| -> std::string::String { - let lane_fn = self.get_lane_function(); - let final_cast = self.generate_final_type_cast(); - format!("{final_cast}{lane_fn}(__return_value, {idx})") - }) - .collect::>() - .join(r#" << ", " << "#) - } else { - format!( - "{promote}cast<{cast}>(__return_value)", - cast = match self.kind() { - TypeKind::Float if self.inner_size() == 16 => "float16_t".to_string(), - TypeKind::Float if self.inner_size() == 32 => "float".to_string(), - TypeKind::Float if self.inner_size() == 64 => "double".to_string(), - TypeKind::Int(Sign::Signed) => format!("int{}_t", self.inner_size()), - TypeKind::Int(Sign::Unsigned) => format!("uint{}_t", self.inner_size()), - TypeKind::Poly => format!("poly{}_t", self.inner_size()), - ty => todo!("print_result_c - Unknown type: {ty:#?}"), - }, - promote = self.generate_final_type_cast(), + // Recurse to handle pointers.. + if let Some(s) = s.strip_suffix('*') { + let s = s.trim(); + let (s, constant) = if s.ends_with(CONST_STR) || s.starts_with(CONST_STR) { + ( + s.trim_start_matches(CONST_STR).trim_end_matches(CONST_STR), + true, ) + } else { + (s, false) }; - format!( - r#"{indentation}std::cout << "Result {additional}-" << i+1 << ": {ty}" << std::fixed << std::setprecision(150) << {lanes} << "{close}" << std::endl;"#, - ty = if self.is_simd() { - format!("{}(", self.c_type()) - } else { - String::from("") - }, - close = if self.is_simd() { ")" } else { "" }, - ) + let mut ty = parse_intrinsic_type(s.trim())?; + ty.ptr = true; + ty.ptr_constant = constant; + return Ok(ty); } -} -impl ArmIntrinsicType { - pub fn from_c(s: &str, target: &str) -> Result { - const CONST_STR: &str = "const"; - if let Some(s) = s.strip_suffix('*') { - let (s, constant) = match s.trim().strip_suffix(CONST_STR) { - Some(stripped) => (stripped, true), - None => (s, false), - }; - let s = s.trim_end(); - let temp_return = ArmIntrinsicType::from_c(s, target); - temp_return.map(|mut op| { - op.ptr = true; - op.ptr_constant = constant; - op - }) - } else { - // [const ]TYPE[{bitlen}[x{simdlen}[x{vec_len}]]][_t] - let (mut s, constant) = match s.strip_prefix(CONST_STR) { - Some(stripped) => (stripped.trim(), true), - None => (s, false), - }; - s = s.strip_suffix("_t").unwrap_or(s); - let mut parts = s.split('x'); // [[{bitlen}], [{simdlen}], [{vec_len}] ] - let start = parts.next().ok_or("Impossible to parse type")?; - if let Some(digit_start) = start.find(|c: char| c.is_ascii_digit()) { - let (arg_kind, bit_len) = start.split_at(digit_start); - let arg_kind = arg_kind.parse::()?; - let bit_len = bit_len.parse::().map_err(|err| err.to_string())?; - let simd_len = match parts.next() { - Some(part) => Some( - part.parse::() - .map_err(|_| "Couldn't parse simd_len: {part}")?, - ), - None => None, - }; - let vec_len = match parts.next() { - Some(part) => Some( - part.parse::() - .map_err(|_| "Couldn't parse vec_len: {part}")?, - ), - None => None, - }; - Ok(ArmIntrinsicType { - data: IntrinsicType { - ptr: false, - ptr_constant: false, - constant, - kind: arg_kind, - bit_len: Some(bit_len), - simd_len, - vec_len, - }, - target: target.to_string(), - }) - } else { - let kind = start.parse::()?; - let bit_len = match kind { - TypeKind::Int(_) => Some(32), - _ => None, - }; - Ok(ArmIntrinsicType { - data: IntrinsicType { - ptr: false, - ptr_constant: false, - constant, - kind: start.parse::()?, - bit_len, - simd_len: None, - vec_len: None, - }, - target: target.to_string(), - }) - } - } - } + // [const ][sv]TYPE[{element_bits}[x{num_lanes}[x{num_vecs}]]][_t] + // | [enum ]TYPE + let (mut s, constant) = match (s.strip_prefix(CONST_STR), s.strip_prefix(ENUM_STR)) { + (Some(const_strip), _) => (const_strip, true), + (_, Some(enum_strip)) => (enum_strip, true), + (None, None) => (s, false), + }; + s = s.trim(); + s = s.strip_suffix("_t").unwrap_or(s); + + // Consider the following types as examples: + // A) `svuint32x3_t` + // B) `float16x4x2_t` + // C) `svbool_t` + + let sve = s.starts_with("sv"); + + let mut parts = s.split('x'); + let start = parts.next().ok_or("failed to parse type")?; + + // Continuing the previous examples.. + // A) kind=TypeKind::Int(Sign::Unsigned), bit_len=Some(32) + // B) kind=TypeKind::Float, bit_len=Some(16) + // C) kind=TypeKind::Bool, bit_len=None + let (kind, bit_len) = if let Some(digit_start) = start.find(|c: char| c.is_ascii_digit()) { + let (element_kind, element_bits) = start.split_at(digit_start); + let element_kind = element_kind.parse::()?; + let element_bits = element_bits.parse::().map_err(|err| err.to_string())?; + (element_kind, Some(element_bits)) + } else { + let element_kind = start.parse::()?; + (element_kind, None) + }; + + let bit_len = match (bit_len, kind) { + (None, TypeKind::SvPattern | TypeKind::SvPrefetchOp | TypeKind::Int(_)) => Some(32), + (None, TypeKind::Bool) => Some(8), + _ => bit_len, + }; + + // Continuing the previous examples.. + // A) second_len=Some(3) + // B) second_len=Some(4) + // C) second_len=None + let second_len = parts.next().map(|part| { + part.parse::() + .expect("failed to parse second part of type") + }); + + // Continuing the previous examples.. + // A) third_len=None + // B) third_len=Some(2) + // C) third_len=None + let third_len = parts.next().map(|part| { + part.parse::() + .expect("failed to parse third part of type") + }); + + let (simd_len, vec_len) = if sve { + (Some(SimdLen::Scalable), second_len) + } else { + (second_len.map(SimdLen::Fixed), third_len) + }; + + Ok(IntrinsicType { + ptr: false, + ptr_constant: false, + constant, + kind, + bit_len, + simd_len, + vec_len, + }) } diff --git a/stdarch/crates/intrinsic-test/src/common/argument.rs b/stdarch/crates/intrinsic-test/src/common/argument.rs index 385cf32d3bff9..25207a8c458fd 100644 --- a/stdarch/crates/intrinsic-test/src/common/argument.rs +++ b/stdarch/crates/intrinsic-test/src/common/argument.rs @@ -1,6 +1,9 @@ -use super::cli::Language; +use itertools::Itertools; + +use crate::common::intrinsic_helpers::TypeKind; + use super::constraint::Constraint; -use super::indentation::Indentation; +use super::gen_rust::PASSES; use super::intrinsic_helpers::IntrinsicTypeDefinition; /// An argument for the intrinsic. @@ -30,8 +33,7 @@ where } pub fn to_c_type(&self) -> String { - let prefix = if self.ty.constant { "const " } else { "" }; - format!("{prefix}{}", self.ty.c_type()) + self.ty.c_type() } pub fn generate_name(&self) -> String { @@ -50,35 +52,26 @@ where self.constraint.is_some() } - /// The binding keyword (e.g. "const" or "let") for the array of possible test inputs. - fn rust_vals_array_binding(&self) -> impl std::fmt::Display { - if self.ty.is_rust_vals_array_const() { - "const" - } else { - "let" - } - } - - /// The name (e.g. "A_VALS" or "a_vals") for the array of possible test inputs. + /// Returns a string with the name of the static variable containing test values for intrinsic + /// arguments of this type. pub(crate) fn rust_vals_array_name(&self) -> impl std::fmt::Display { - if self.ty.is_rust_vals_array_const() { - let loads = crate::common::gen_rust::PASSES; - format!( - "{}_{ty}_{load_size}", - self.name.to_uppercase(), - ty = self.ty.rust_scalar_type(), - load_size = self.ty.num_lanes() * self.ty.num_vectors() + loads - 1, - ) - } else { - format!("{}_vals", self.name.to_lowercase()) - } + let loads = crate::common::gen_rust::PASSES; + format!( + "{ty}_{load_size}", + ty = self.ty.rust_scalar_type().to_uppercase(), + load_size = self.ty.num_lanes() * self.ty.num_vectors() + loads - 1, + ) } - fn as_call_param_c(&self) -> String { - self.ty.as_call_param_c(&self.generate_name()) + /// Should this argument be passed by reference in C wrapper function declarations? + /// + /// SIMD types and `f16` are currently passed by reference. + pub(crate) fn pass_by_ref(&self) -> bool { + self.is_simd() || (self.ty.kind() == TypeKind::Float && self.ty.inner_size() == 16) } } +/// Arguments of an intrinsic - including parameters that end up being const generics. #[derive(Debug, PartialEq, Clone)] pub struct ArgumentList { pub args: Vec>, @@ -88,131 +81,166 @@ impl ArgumentList where T: IntrinsicTypeDefinition, { - /// Converts the argument list into the call parameters for a C function call. - /// e.g. this would generate something like `a, &b, c` - pub fn as_call_param_c(&self) -> String { + /// Returns a string with the arguments in `self` as a parameter list for a wrapper fn + /// definition in C (e.g. `$ty1 $arg1, $ty2 $arg2`). + /// + /// Skips arguments with constraints - which correspond to arguments that must take immediates - + /// as a different C definition will be generated for each value of these being tested. + pub fn as_non_imm_arglist_c(&self) -> String { self.iter() - .map(|arg| arg.as_call_param_c()) - .collect::>() - .join(", ") + .filter(|arg| !arg.has_constraint()) + .format_with("", |arg, fmt| { + if arg.pass_by_ref() { + fmt(&format_args!(", const {}* {}", arg.to_c_type(), arg.name)) + } else { + fmt(&format_args!(", {} {}", arg.to_c_type(), arg.name)) + } + }) + .to_string() } - /// Converts the argument list into the call parameters for a Rust function. - /// e.g. this would generate something like `a, b, c` - pub fn as_call_param_rust(&self) -> String { + /// Returns a string with the arguments in `self` as a parameter list for a Rust declaration of + /// a C wrapper fn (e.g. `$arg1: $ty1, $arg2: $ty2`). + /// + /// Skips arguments with constraints - which correspond to arguments that must take immediates - + /// as a different C definition will be generated for each value of these being tested. + pub fn as_non_imm_arglist_rust(&self) -> String { self.iter() - .filter(|a| !a.has_constraint()) - .map(|arg| arg.generate_name() + " as _") - .collect::>() - .join(", ") + .filter(|arg| !arg.has_constraint()) + .format_with("", |arg, fmt| { + if arg.pass_by_ref() { + fmt(&format_args!( + ", {}: *const {}", + arg.name, + arg.ty.rust_type() + )) + } else { + fmt(&format_args!(", {}: {}", arg.name, arg.ty.rust_type())) + } + }) + .to_string() } - /// Creates a line for each argument that initializes an array for C from which `loads` argument - /// values can be loaded as a sliding window. - /// e.g `const int32x2_t a_vals = {0x3effffff, 0x3effffff, 0x3f7fffff}`, if loads=2. - pub fn gen_arglists_c( - &self, - w: &mut impl std::io::Write, - indentation: Indentation, - loads: u32, - ) -> std::io::Result<()> { - for arg in self.iter().filter(|&arg| !arg.has_constraint()) { - // Setting the variables on an aligned boundary to make it easier to pick - // functions (of a specific architecture) that would help load the values. - writeln!( - w, - "{indentation}alignas(64) const {ty} {name}_vals[] = {values};", - ty = arg.ty.c_scalar_type(), - name = arg.generate_name(), - values = arg.ty.populate_random(indentation, loads, &Language::C) - )? - } - - Ok(()) + /// Returns a string with the arguments in `self` being passed to an intrinsic call in C + /// (e.g. `$arg1, 2 /* imm_args[0] */, $arg3` where `$arg2` has a constraint). + pub fn as_call_params_c(&self, imm_args: &[i64]) -> String { + let mut imm_args = imm_args.iter(); + self.iter() + .format_with(", ", |arg, fmt| { + if arg.has_constraint() { + fmt(&imm_args.next().unwrap()) + } else { + if arg.pass_by_ref() { + fmt(&"*")?; + } + fmt(&arg.name) + } + }) + .to_string() } - /// Creates a line for each argument that initializes an array for Rust from which `loads` argument - /// values can be loaded as a sliding window, e.g `const A_VALS: [u32; 20] = [...];` - pub fn gen_arglists_rust( - &self, - w: &mut impl std::io::Write, - indentation: Indentation, - loads: u32, - ) -> std::io::Result<()> { - for arg in self.iter().filter(|&arg| !arg.has_constraint()) { - // Constants are defined globally. - if arg.ty.is_rust_vals_array_const() { - continue; - } - - Self::gen_arg_rust(arg, w, indentation, loads)?; - } + /// Returns a string with the arguments in `self` being passed to an intrinsic call in Rust. + /// (e.g. `$arg1, $arg3` where `$arg2` has a constraint and so corresponds to a const generic + /// parameter). + pub fn as_call_param_rust(&self) -> String { + self.iter() + .filter(|a| !a.has_constraint()) + .map(|arg| arg.generate_name()) + .join(", ") + } - Ok(()) + /// Returns a string with the arguments in `self` being passed to the declaration of a C wrapper + /// fn from Rust (e.g. `$arg1, $arg3` (where `$arg2` has a constraint and so corresponds to a + /// const generic parameter). + pub fn as_c_call_param_rust(&self) -> String { + self.iter() + .filter(|a| !a.has_constraint()) + .map(|arg| { + if arg.pass_by_ref() { + format!(", &raw const {}", arg.generate_name()) + } else { + format!(", {}", arg.generate_name()) + } + }) + .join("") } + /// Returns a string defining a static variable with test values used for all intrinsics with + /// arguments of `arg`'s type. + /// + /// e.g. + /// ```rust,ignore + /// static U8_20: [u8; 20] = [ + /// 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0xf0, + /// 0x80, 0x3b, 0xff, + /// ]; + /// ``` + /// + /// `num_lanes * num_vectors + loads - 1` elements are present in the array, which is sufficient + /// for a `loads` number of `num_lanes * num_vectors` windows into the array to be loaded: + /// + /// ```text + /// [0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0xf0, 0x80, 0x3b, 0xff] + /// ^^^^^^^^^^^^^^^^^^^ first window of `num_lanes * num_vectors` elements (e.g. four elements) + /// ^^^^^^^^^^^^^^^^^^ second window + /// `loads`th window ^^^^^^^^^^^^^^^^^^^^^^ + /// ``` pub fn gen_arg_rust( arg: &Argument, w: &mut impl std::io::Write, - indentation: Indentation, loads: u32, ) -> std::io::Result<()> { writeln!( w, - "{indentation}{bind} {name}: [{ty}; {load_size}] = {values};\n", - bind = arg.rust_vals_array_binding(), + "static {name}: [{ty}; {load_size}] = {values};\n", name = arg.rust_vals_array_name(), ty = arg.ty.rust_scalar_type(), load_size = arg.ty.num_lanes() * arg.ty.num_vectors() + loads - 1, - values = arg.ty.populate_random(indentation, loads, &Language::Rust) + values = arg.ty.populate_random(loads) ) } - /// Creates a line for each argument that initializes the argument from an array `[arg]_vals` at - /// an offset `i` using a load intrinsic, in C. - /// e.g `uint8x8_t a = vld1_u8(&a_vals[i]);` + /// Returns a string defining a local variable for each argument and loading a value into each + /// using a load intrinsic. /// - /// ARM-specific - pub fn load_values_c(&self, indentation: Indentation) -> String { - self.iter() - .filter(|&arg| !arg.has_constraint()) - .map(|arg| { - format!( - "{indentation}{ty} {name} = cast<{ty}>({load}(&{name}_vals[i]));\n", - ty = arg.to_c_type(), - name = arg.generate_name(), - load = if arg.is_simd() { - arg.ty.get_load_function(Language::C) - } else { - "*".to_string() - } - ) - }) - .collect() - } - - /// Creates a line for each argument that initializes the argument from array `[ARG]_VALS` at - /// an offset `i` using a load intrinsic, in Rust. - /// e.g `let a = vld1_u8(A_VALS.as_ptr().offset(i));` - pub fn load_values_rust(&self, indentation: Indentation) -> String { + /// e.g. + /// ```rust,ignore + /// let a = vld1_u8(I16_23.as_ptr().offset((i + 0 /* idx */) % 20 /* PASSES */)); + /// ```` + /// + /// The generator will have already generated arrays of appropriate length with values that can + /// be used for testing (see the `gen_args_rust` function). + /// + /// Each load is assumed to have a variable `i` in scope which comes from a loop which repeats + /// the testing of the intrinsic for different values - each subsequent `i` shifts the window + /// of values being loaded along the pre-prepared array. + /// + /// Each subsequent argument's first window is started one element further into the array + /// then the previous. + pub fn load_values_rust(&self) -> String { self.iter() .filter(|&arg| !arg.has_constraint()) - .map(|arg| { - let load = if arg.is_simd() { - arg.ty.get_load_function(Language::Rust) + .enumerate() + .map(|(idx, arg)| { + if arg.is_simd() { + format!( + "let {name} = {load}({vals_name}.as_ptr().add((i+{idx}) % {PASSES}) as _);\n", + name = arg.generate_name(), + vals_name = arg.rust_vals_array_name(), + load = arg.ty.get_load_function(), + ) } else { - "*".to_string() - }; - let typecast = if load.len() > 2 { "as _" } else { "" }; - format!( - "{indentation}let {name} = {load}({vals_name}.as_ptr().offset(i){typecast});\n", - name = arg.generate_name(), - vals_name = arg.rust_vals_array_name(), - ) + format!( + "let {name} = {vals_name}[(i+{idx}) % {PASSES}];\n", + name = arg.generate_name(), + vals_name = arg.rust_vals_array_name(), + ) + } }) .collect() } + /// Returns an iterator over the contained arguments pub fn iter(&self) -> std::slice::Iter<'_, Argument> { self.args.iter() } diff --git a/stdarch/crates/intrinsic-test/src/common/cli.rs b/stdarch/crates/intrinsic-test/src/common/cli.rs index bed8259de8b6d..3ea87df51fda2 100644 --- a/stdarch/crates/intrinsic-test/src/common/cli.rs +++ b/stdarch/crates/intrinsic-test/src/common/cli.rs @@ -1,12 +1,6 @@ use itertools::Itertools; use std::path::PathBuf; -#[derive(Debug, PartialEq)] -pub enum Language { - Rust, - C, -} - /// Intrinsic test tool #[derive(clap::Parser)] #[command( @@ -17,104 +11,62 @@ pub struct Cli { /// The input file containing the intrinsics pub input: PathBuf, - /// The rust toolchain to use for building the rust code - #[arg(long)] - pub toolchain: Option, - - /// The C++ compiler to use for compiling the c++ code - #[arg(long, default_value_t = String::from("clang++"))] - pub cppcompiler: String, - - /// Run the C programs under emulation with this command - #[arg(long)] - pub runner: Option, - /// Filename for a list of intrinsics to skip (one per line) #[arg(long)] - pub skip: Option, - - /// Regenerate test programs, but don't build or run them - #[arg(long)] - pub generate_only: bool, + pub skip: Vec, /// Pass a target the test suite - #[arg(long, default_value_t = String::from("armv7-unknown-linux-gnueabihf"))] + #[arg(long)] pub target: String, - /// Pass a profile (release, dev) - #[arg(long, default_value_t = String::from("release"))] - pub profile: String, - - /// Set the linker - #[arg(long)] - pub linker: Option, + /// Percentage of intrinsics to test (used to limit testing to keep CI times manageable) + #[arg(long, default_value_t = 100u8)] + pub sample_percentage: u8, - /// Set the sysroot for the C++ compiler + /// Argument style of the C compiler #[arg(long)] - pub cxx_toolchain_dir: Option, + pub cc_arg_style: CcArgStyle, +} - #[arg(long, default_value_t = 100u8)] - pub sample_percentage: u8, +#[derive(Copy, Clone, clap::ValueEnum)] +pub enum CcArgStyle { + Gcc, + Clang, } pub struct ProcessedCli { pub filename: PathBuf, - pub toolchain: Option, - pub cpp_compiler: Option, - pub runner: String, pub target: String, - pub profile: String, - pub linker: Option, - pub cxx_toolchain_dir: Option, pub skip: Vec, pub sample_percentage: u8, + pub cc_arg_style: CcArgStyle, } impl ProcessedCli { pub fn new(cli_options: Cli) -> Self { let filename = cli_options.input; - let runner = cli_options.runner.unwrap_or_default(); let target = cli_options.target; - let profile = cli_options.profile; - let linker = cli_options.linker; - let cxx_toolchain_dir = cli_options.cxx_toolchain_dir; let sample_percentage = cli_options.sample_percentage; - let skip = if let Some(filename) = cli_options.skip { - let data = std::fs::read_to_string(&filename).expect("Failed to open file"); - data.lines() - .map(str::trim) - .filter(|s| !s.contains('#')) - .map(String::from) - .collect_vec() - } else { - Default::default() - }; - - let (toolchain, cpp_compiler) = if cli_options.generate_only { - (None, None) - } else { - ( - Some( - cli_options - .toolchain - .map_or_else(String::new, |t| format!("+{t}")), - ), - Some(cli_options.cppcompiler), - ) - }; + let skip = cli_options + .skip + .iter() + .flat_map(|filename| { + std::fs::read_to_string(&filename) + .expect("Failed to open file") + .lines() + .map(|line| line.trim().to_owned()) + .filter(|line| !line.contains('#')) + .collect_vec() + }) + .collect_vec(); Self { - toolchain, - cpp_compiler, - runner, target, - profile, - linker, - cxx_toolchain_dir, skip, filename, sample_percentage, + cc_arg_style: cli_options.cc_arg_style, } } } diff --git a/stdarch/crates/intrinsic-test/src/common/compare.rs b/stdarch/crates/intrinsic-test/src/common/compare.rs deleted file mode 100644 index c22d7fd4ec0aa..0000000000000 --- a/stdarch/crates/intrinsic-test/src/common/compare.rs +++ /dev/null @@ -1,142 +0,0 @@ -use itertools::Itertools; -use rayon::prelude::*; -use std::{collections::HashMap, process::Command}; - -pub const INTRINSIC_DELIMITER: &str = "############"; -fn runner_command(runner: &str) -> Command { - let mut it = runner.split_whitespace(); - let mut cmd = Command::new(it.next().unwrap()); - cmd.args(it); - - cmd -} - -pub fn compare_outputs( - intrinsic_name_list: &Vec, - runner: &str, - target: &str, - profile: &str, -) -> bool { - let profile_dir = match profile { - "dev" => "debug", - _ => "release", - }; - - let (c, rust) = rayon::join( - || { - runner_command(runner) - .arg("./intrinsic-test-programs") - .current_dir("c_programs") - .output() - }, - || { - runner_command(runner) - .arg(format!( - "./target/{target}/{profile_dir}/intrinsic-test-programs" - )) - .current_dir("rust_programs") - .output() - }, - ); - let (c, rust) = match (c, rust) { - (Ok(c), Ok(rust)) => (c, rust), - failure => panic!("Failed to run: {failure:#?}"), - }; - - if !c.status.success() { - error!( - "Failed to run C program.\nstdout: {stdout}\nstderr: {stderr}", - stdout = std::str::from_utf8(&c.stdout).unwrap_or(""), - stderr = std::str::from_utf8(&c.stderr).unwrap_or(""), - ); - } - - if !rust.status.success() { - error!( - "Failed to run Rust program.\nstdout: {stdout}\nstderr: {stderr}", - stdout = std::str::from_utf8(&rust.stdout).unwrap_or(""), - stderr = std::str::from_utf8(&rust.stderr).unwrap_or(""), - ); - } - - info!("Completed running C++ and Rust test binaries"); - let c = std::str::from_utf8(&c.stdout) - .unwrap() - .to_lowercase() - .replace("-nan", "nan"); - let rust = std::str::from_utf8(&rust.stdout) - .unwrap() - .to_lowercase() - .replace("-nan", "nan"); - - let c_output_map = c - .split(INTRINSIC_DELIMITER) - .filter_map(|output| output.trim().split_once("\n")) - .collect::>(); - let rust_output_map = rust - .split(INTRINSIC_DELIMITER) - .filter_map(|output| output.trim().split_once("\n")) - .collect::>(); - - let intrinsics = c_output_map - .keys() - .chain(rust_output_map.keys()) - .unique() - .collect_vec(); - - info!("Comparing outputs"); - let intrinsics_diff_count = intrinsics - .par_iter() - .filter_map(|&&intrinsic| { - let c_output = c_output_map.get(intrinsic).unwrap(); - let rust_output = rust_output_map.get(intrinsic).unwrap(); - if rust_output.eq(c_output) { - None - } else { - let diff = diff::lines(c_output, rust_output); - let diffs = diff - .into_iter() - .filter_map(|diff| match diff { - diff::Result::Left(_) | diff::Result::Right(_) => Some(diff), - diff::Result::Both(_, _) => None, - }) - .collect_vec(); - if diffs.len() > 0 { - Some((intrinsic, diffs)) - } else { - None - } - } - }) - .inspect(|(intrinsic, diffs)| { - use std::io::Write; - - let stdout = std::io::stdout(); - let mut out = stdout.lock(); - - writeln!(out, "Difference for intrinsic: {intrinsic}").unwrap(); - diffs.into_iter().for_each(|diff| match diff { - diff::Result::Left(c) => { - writeln!(out, "C: {c}").unwrap(); - } - diff::Result::Right(rust) => { - writeln!(out, "Rust: {rust}").unwrap(); - } - _ => (), - }); - writeln!( - out, - "****************************************************************" - ) - .unwrap(); - }) - .count(); - - println!( - "{} differences found (tested {} intrinsics)", - intrinsics_diff_count, - intrinsic_name_list.len() - ); - - intrinsics_diff_count == 0 -} diff --git a/stdarch/crates/intrinsic-test/src/common/compile_c.rs b/stdarch/crates/intrinsic-test/src/common/compile_c.rs deleted file mode 100644 index fa78b332a7857..0000000000000 --- a/stdarch/crates/intrinsic-test/src/common/compile_c.rs +++ /dev/null @@ -1,136 +0,0 @@ -#[derive(Clone)] -pub struct CompilationCommandBuilder { - compiler: String, - target: Option, - cxx_toolchain_dir: Option, - arch_flags: Vec, - optimization: String, - project_root: Option, - extra_flags: Vec, -} - -impl CompilationCommandBuilder { - pub fn new() -> Self { - Self { - compiler: String::new(), - target: None, - cxx_toolchain_dir: None, - arch_flags: Vec::new(), - optimization: "2".to_string(), - project_root: None, - extra_flags: Vec::new(), - } - } - - pub fn set_compiler(mut self, compiler: &str) -> Self { - self.compiler = compiler.to_string(); - self - } - - pub fn set_target(mut self, target: &str) -> Self { - self.target = Some(target.to_string()); - self - } - - pub fn set_cxx_toolchain_dir(mut self, path: Option<&str>) -> Self { - self.cxx_toolchain_dir = path.map(|p| p.to_string()); - self - } - - pub fn add_arch_flags<'a>(mut self, flags: impl IntoIterator) -> Self { - self.arch_flags - .extend(flags.into_iter().map(|s| s.to_owned())); - - self - } - - pub fn set_opt_level(mut self, optimization: &str) -> Self { - self.optimization = optimization.to_string(); - self - } - - /// Sets the root path of all the generated test files. - pub fn set_project_root(mut self, path: &str) -> Self { - self.project_root = Some(path.to_string()); - self - } - - pub fn add_extra_flags<'a>(mut self, flags: impl IntoIterator) -> Self { - self.extra_flags - .extend(flags.into_iter().map(|s| s.to_owned())); - - self - } - - pub fn add_extra_flag(self, flag: &str) -> Self { - self.add_extra_flags([flag]) - } -} - -impl CompilationCommandBuilder { - pub fn into_cpp_compilation(self) -> CppCompilation { - let mut cpp_compiler = std::process::Command::new(self.compiler); - - if let Some(project_root) = self.project_root { - cpp_compiler.current_dir(project_root); - } - - let flags = std::env::var("CPPFLAGS").unwrap_or("".into()); - cpp_compiler.args(flags.split_whitespace()); - - cpp_compiler.arg(format!("-march={}", self.arch_flags.join("+"))); - - cpp_compiler.arg(format!("-O{}", self.optimization)); - - cpp_compiler.args(self.extra_flags); - - if let Some(target) = &self.target { - cpp_compiler.arg(format!("--target={target}")); - } - - CppCompilation(cpp_compiler) - } -} - -pub struct CppCompilation(std::process::Command); - -fn clone_command(command: &std::process::Command) -> std::process::Command { - let mut cmd = std::process::Command::new(command.get_program()); - if let Some(current_dir) = command.get_current_dir() { - cmd.current_dir(current_dir); - } - cmd.args(command.get_args()); - - for (key, val) in command.get_envs() { - cmd.env(key, val.unwrap_or_default()); - } - - cmd -} - -impl CppCompilation { - pub fn command_mut(&mut self) -> &mut std::process::Command { - &mut self.0 - } - - pub fn compile_object_file( - &self, - input: &str, - output: &str, - ) -> std::io::Result { - let mut cmd = clone_command(&self.0); - cmd.args([input, "-v", "-c", "-o", output]); - cmd.output() - } - - pub fn link_executable( - &self, - inputs: impl Iterator, - output: &str, - ) -> std::io::Result { - let mut cmd = clone_command(&self.0); - cmd.args(inputs); - cmd.args(["-o", output]); - cmd.output() - } -} diff --git a/stdarch/crates/intrinsic-test/src/common/constraint.rs b/stdarch/crates/intrinsic-test/src/common/constraint.rs index 5984e0fcc22f9..ab52d866ab20a 100644 --- a/stdarch/crates/intrinsic-test/src/common/constraint.rs +++ b/stdarch/crates/intrinsic-test/src/common/constraint.rs @@ -1,24 +1,43 @@ use serde::Deserialize; use std::ops::Range; -/// Describes the values to test for a const generic parameter. +/// Describes the values to test for a const generic parameter #[derive(Debug, PartialEq, Clone, Deserialize)] pub enum Constraint { - /// Test a single value. + /// Test a single value Equal(i64), /// Test a range of values, e.g. `0..16`. Range(Range), /// Test discrete values, e.g. `vec![1, 2, 4, 8]`. Set(Vec), + /// Values of `core::arch::aarch64::svpattern` + SvPattern, + /// Values of `core::arch::aarch64::svprfop` + SvPrefetchOp, + // Values of the `imm_rotation` argument in SVE intrinsics where arguments contain complex + // pairs and `imm_rotation` corresponds to the rotation. + SvImmRotation, + // Values of the `imm_rotation` argument in SVE intrinsics where arguments contain complex + // pairs and `imm_rotation` corresponds to the rotation (this variant is specifically for + // `svcadd` and `svqcadd` where only 90 and 270 are valid arguments). + SvImmRotationAdd, } impl Constraint { - /// Iterate over the values of this constraint. - pub fn iter<'a>(&'a self) -> impl Iterator + 'a { + /// Returns an iterator over the values of this constraint + pub fn iter(&self) -> Box + '_> { match self { - Constraint::Equal(i) => std::slice::Iter::default().copied().chain(*i..*i + 1), - Constraint::Range(range) => std::slice::Iter::default().copied().chain(range.clone()), - Constraint::Set(items) => items.iter().copied().chain(std::ops::Range::default()), + Constraint::Equal(i) => Box::new(std::iter::once(*i)), + Constraint::Range(range) => Box::new(range.clone()), + Constraint::Set(items) => Box::new(items.iter().copied().chain(Range::default())), + // These values are discriminants of the `svpattern` enum + Constraint::SvPattern => Box::new((0..=13).chain(29..=31)), + // These values are discriminants of the `svprfop` enum + Constraint::SvPrefetchOp => Box::new((0..=5).chain(8..=14)), + // Valid rotations for intrinsics operating on complex pairs: 0, 90, 180, 270 + Constraint::SvImmRotation => Box::new((0..=270).step_by(90)), + // Valid rotations for `svcadd` and `svqcadd`: 0, 270 + Constraint::SvImmRotationAdd => Box::new((90..=270).step_by(180)), } } } diff --git a/stdarch/crates/intrinsic-test/src/common/gen_c.rs b/stdarch/crates/intrinsic-test/src/common/gen_c.rs index a95b4c36b7bf0..24756324c48e4 100644 --- a/stdarch/crates/intrinsic-test/src/common/gen_c.rs +++ b/stdarch/crates/intrinsic-test/src/common/gen_c.rs @@ -1,166 +1,52 @@ +use itertools::Itertools; + use crate::common::intrinsic::Intrinsic; -use super::argument::Argument; -use super::compare::INTRINSIC_DELIMITER; -use super::indentation::Indentation; use super::intrinsic_helpers::IntrinsicTypeDefinition; -// The number of times each intrinsic will be called. -const PASSES: u32 = 20; -const COMMON_HEADERS: [&str; 7] = [ - "iostream", - "string", - "cstring", - "iomanip", - "sstream", - "type_traits", - "cassert", -]; - -pub fn generate_c_test_loop( - w: &mut impl std::io::Write, - intrinsic: &Intrinsic, - indentation: Indentation, - additional: &str, - passes: u32, -) -> std::io::Result<()> { - let body_indentation = indentation.nested(); - writeln!( - w, - "{indentation}for (int i=0; i<{passes}; i++) {{\n\ - {loaded_args}\ - {body_indentation}auto __return_value = {intrinsic_call}({args});\n\ - {print_result}\n\ - {indentation}}}", - loaded_args = intrinsic.arguments.load_values_c(body_indentation), - intrinsic_call = intrinsic.name, - args = intrinsic.arguments.as_call_param_c(), - print_result = intrinsic - .results - .print_result_c(body_indentation, additional) - ) -} - -pub fn generate_c_constraint_blocks<'a, T: IntrinsicTypeDefinition + 'a>( - w: &mut impl std::io::Write, - intrinsic: &Intrinsic, - indentation: Indentation, - constraints: &mut (impl Iterator> + Clone), - name: String, -) -> std::io::Result<()> { - let Some(current) = constraints.next() else { - return generate_c_test_loop(w, intrinsic, indentation, &name, PASSES); - }; - - let body_indentation = indentation.nested(); - for i in current.constraint.iter().flat_map(|c| c.iter()) { - let ty = current.ty.c_type(); - - writeln!(w, "{indentation}{{")?; - - // TODO: Move to actually specifying the enum value - // instead of typecasting integers, for better clarity - // of generated code. - writeln!( - w, - "{body_indentation}const {ty} {} = ({ty}){i};", - current.generate_name() - )?; - - generate_c_constraint_blocks( - w, - intrinsic, - body_indentation, - &mut constraints.clone(), - format!("{name}-{i}"), - )?; - - writeln!(w, "{indentation}}}")?; - } - - Ok(()) -} - -// Compiles C test programs using specified compiler -pub fn create_c_test_function( - w: &mut impl std::io::Write, - intrinsic: &Intrinsic, -) -> std::io::Result<()> { - let indentation = Indentation::default(); - - writeln!(w, "int run_{}() {{", intrinsic.name)?; - - // Define the arrays of arguments. - let arguments = &intrinsic.arguments; - arguments.gen_arglists_c(w, indentation.nested(), PASSES)?; - - generate_c_constraint_blocks( - w, - intrinsic, - indentation.nested(), - &mut arguments.iter().rev().filter(|&i| i.has_constraint()), - Default::default(), - )?; - - writeln!(w, " return 0;")?; - writeln!(w, "}}")?; - - Ok(()) -} - -pub fn write_mod_cpp( +/// Generates a C source file containing wrapper functions around each specialisation of each +/// intrinsic (that is, intrinsics with specific values for the the immediate arguments). Each +/// wrapper function is invoked via FFI from the Rust binary doing the testing. +/// +/// e.g. +/// ```c +/// void __crc32cd_wrapper(uint32_t* __dst, uint32_t a, uint64_t b) { +/// *__dst = __crc32cd(a, b); +/// } +/// ``` +pub fn write_wrapper_c( w: &mut impl std::io::Write, notice: &str, platform_headers: &[&str], - forward_declarations: &str, intrinsics: &[Intrinsic], ) -> std::io::Result<()> { write!(w, "{notice}")?; - for header in COMMON_HEADERS.iter().chain(platform_headers.iter()) { - writeln!(w, "#include <{header}>")?; - } - - writeln!(w, "{}", forward_declarations)?; - - for intrinsic in intrinsics { - create_c_test_function(w, intrinsic)?; - } - - Ok(()) -} + writeln!(w, "#include ")?; + writeln!(w, "#include ")?; -pub fn write_main_cpp<'a>( - w: &mut impl std::io::Write, - arch_specific_definitions: &str, - arch_specific_headers: &[&str], - intrinsics: impl Iterator + Clone, -) -> std::io::Result<()> { - for header in COMMON_HEADERS.iter().chain(arch_specific_headers.iter()) { + for header in platform_headers { writeln!(w, "#include <{header}>")?; } - // NOTE: It's assumed that this value contains the required `ifdef`s. - writeln!(w, "{arch_specific_definitions }")?; - - for intrinsic in intrinsics.clone() { - writeln!(w, "extern int run_{intrinsic}(void);")?; - } - - writeln!(w, "int main(int argc, char **argv) {{")?; - for intrinsic in intrinsics { - writeln!( - w, - " std::cout << \"{INTRINSIC_DELIMITER}\" << std::endl;" - )?; - writeln!(w, " std::cout << \"{intrinsic}\" << std::endl;")?; - writeln!(w, " run_{intrinsic}();\n")?; + intrinsic.iter_specializations(|imm_values| { + writeln!( + w, + " +void {name}_wrapper{imm_arglist}({return_ty}* __dst{arglist}) {{ + *__dst = {name}({params}); +}}", + return_ty = intrinsic.results.c_type(), + name = intrinsic.name, + imm_arglist = imm_values + .iter() + .format_with("", |i, fmt| fmt(&format_args!("_{i}"))), + arglist = intrinsic.arguments.as_non_imm_arglist_c(), + params = intrinsic.arguments.as_call_params_c(&imm_values) + ) + })?; } - writeln!(w, " return 0;")?; - - writeln!(w, "}}")?; - Ok(()) } diff --git a/stdarch/crates/intrinsic-test/src/common/gen_rust.rs b/stdarch/crates/intrinsic-test/src/common/gen_rust.rs index 82b97701bb14a..cb07fa600474c 100644 --- a/stdarch/crates/intrinsic-test/src/common/gen_rust.rs +++ b/stdarch/crates/intrinsic-test/src/common/gen_rust.rs @@ -1,23 +1,84 @@ -use itertools::Itertools; use std::process::Command; -use super::compare::INTRINSIC_DELIMITER; -use super::indentation::Indentation; +use itertools::Itertools; + use super::intrinsic_helpers::IntrinsicTypeDefinition; use crate::common::argument::ArgumentList; +use crate::common::cli::{CcArgStyle, ProcessedCli}; use crate::common::intrinsic::Intrinsic; +use crate::common::intrinsic_helpers::TypeKind; -// The number of times each intrinsic will be called. +// The number of times each intrinsic will be called - influences the generation of the +// test arrays to minimise repeated testing of the same test values. pub(crate) const PASSES: u32 = 20; +/// Rust definitions that are included verbatim in the generated source. In particular, defines +/// a wrapper around float types that defines `NaN`s to be equal reflexively to enable +/// comparison of results that use floats types. +const COMMON_RUST_DEFINITIONS: &str = r#" +macro_rules! wrap_partialeq { + ($($wrapper:ident ($inner:ty)),*) => {$( + #[derive(Debug, Copy, Clone)] + #[repr(transparent)] + pub struct $wrapper($inner); + + impl PartialEq for $wrapper { + fn eq(&self, other: &Self) -> bool { + self.0 == other.0 || (self.0.is_nan() && other.0.is_nan()) + } + } + + impl Eq for $wrapper {} + )*} +} + +wrap_partialeq!(NanEqF16(f16), NanEqF32(f32), NanEqF64(f64)); +"#; + macro_rules! concatln { ($($lines:expr),* $(,)?) => { concat!($( $lines, "\n" ),*) }; } -fn write_cargo_toml_header(w: &mut impl std::io::Write, name: &str) -> std::io::Result<()> { - writeln!( +/// Run rustfmt on the generated source code +pub fn run_rustfmt(source_path: &str) { + let output = Command::new("rustfmt") + .args([source_path]) + .output() + .expect("failed to run rustfmt on generated sources"); + + if !output.status.success() { + panic!( + "failed to run rustfmt on generated sources:\nstdout:{stdout}\nstderr:{stderr}", + stdout = String::from_utf8_lossy(&output.stdout), + stderr = String::from_utf8_lossy(&output.stderr) + ); + } +} + +/// Writes a `Cargo.toml` containing a workspace with `module_count` members to `w`. +/// +/// e.g. +/// ```toml +/// [workspace] +/// members = [ "mod_0", "mod_1" ] +/// ``` +pub fn write_bin_cargo_toml( + w: &mut impl std::io::Write, + module_count: usize, +) -> std::io::Result<()> { + write!(w, concatln!("[workspace]", "members = ["))?; + for i in 0..module_count { + writeln!(w, " \"mod_{i}\",")?; + } + writeln!(w, "]") +} + +/// Writes a `Cargo.toml` for a crate with name `name` to `w` that will contain a single Rust source +/// file with a subset of the testing being generated. +pub fn write_lib_cargo_toml(w: &mut impl std::io::Write, name: &str) -> std::io::Result<()> { + write!( w, concatln!( "[package]", @@ -26,6 +87,12 @@ fn write_cargo_toml_header(w: &mut impl std::io::Write, name: &str) -> std::io:: "authors = [{authors}]", "license = \"{license}\"", "edition = \"2018\"", + "", + "[dependencies]", + "core_arch = {{ path = \"../../crates/core_arch\" }}", + "", + "[build-dependencies]", + "cc = \"1\"" ), name = name, version = env!("CARGO_PKG_VERSION"), @@ -36,72 +103,14 @@ fn write_cargo_toml_header(w: &mut impl std::io::Write, name: &str) -> std::io:: ) } -pub fn write_bin_cargo_toml( - w: &mut impl std::io::Write, - module_count: usize, -) -> std::io::Result<()> { - write_cargo_toml_header(w, "intrinsic-test-programs")?; - - writeln!(w, "[dependencies]")?; - writeln!(w, "core_arch = {{ path = \"../crates/core_arch\" }}")?; - - for i in 0..module_count { - writeln!(w, "mod_{i} = {{ path = \"mod_{i}/\" }}")?; - } - - Ok(()) -} - -pub fn write_lib_cargo_toml(w: &mut impl std::io::Write, name: &str) -> std::io::Result<()> { - write_cargo_toml_header(w, name)?; - - writeln!(w, "[dependencies]")?; - writeln!(w, "core_arch = {{ path = \"../../crates/core_arch\" }}")?; - - Ok(()) -} - -pub fn write_main_rs<'a>( - w: &mut impl std::io::Write, - chunk_count: usize, - cfg: &str, - definitions: &str, - intrinsics: impl Iterator + Clone, -) -> std::io::Result<()> { - writeln!(w, "#![feature(simd_ffi)]")?; - writeln!(w, "#![feature(f16)]")?; - writeln!(w, "#![allow(unused)]")?; - - // Cargo will spam the logs if these warnings are not silenced. - writeln!(w, "#![allow(non_upper_case_globals)]")?; - writeln!(w, "#![allow(non_camel_case_types)]")?; - writeln!(w, "#![allow(non_snake_case)]")?; - - writeln!(w, "{cfg}")?; - writeln!(w, "{definitions}")?; - - for module in 0..chunk_count { - writeln!(w, "use mod_{module}::*;")?; - } - - writeln!(w, "fn main() {{")?; - - for binary in intrinsics { - writeln!(w, " println!(\"{INTRINSIC_DELIMITER}\");")?; - writeln!(w, " println!(\"{binary}\");")?; - writeln!(w, " run_{binary}();\n")?; - } - - writeln!(w, "}}")?; - - Ok(()) -} - +/// Writes a Rust source file into `w` with common definitions, static arrays with test values, +/// declarations of C wrapper functions for FFI and Rust test functions. pub fn write_lib_rs( w: &mut impl std::io::Write, notice: &str, cfg: &str, definitions: &str, + i: usize, intrinsics: &[Intrinsic], ) -> std::io::Result<()> { write!(w, "{notice}")?; @@ -117,206 +126,236 @@ pub fn write_lib_rs( writeln!(w, "{cfg}")?; + writeln!(w, "{}", COMMON_RUST_DEFINITIONS)?; + writeln!(w, "{definitions}")?; let mut seen = std::collections::HashSet::new(); for intrinsic in intrinsics { for arg in &intrinsic.arguments.args { - if !arg.has_constraint() && arg.ty.is_rust_vals_array_const() { + if !arg.has_constraint() { let name = arg.rust_vals_array_name().to_string(); if seen.insert(name) { - ArgumentList::gen_arg_rust(arg, w, Indentation::default(), PASSES)?; + ArgumentList::gen_arg_rust(arg, w, PASSES)?; } } } } + write_bindings_rust(w, i, intrinsics)?; + for intrinsic in intrinsics { - crate::common::gen_rust::create_rust_test_module(w, intrinsic)?; + create_rust_test(w, intrinsic)?; } Ok(()) } -pub fn compile_rust_programs( - toolchain: Option<&str>, - target: &str, - profile: &str, - linker: Option<&str>, -) -> bool { - /* If there has been a linker explicitly set from the command line then - * we want to set it via setting it in the RUSTFLAGS*/ - - // This is done because `toolchain` is None when - // the --generate-only flag is passed - if toolchain.is_none() { - return true; - } - - trace!("Building cargo command"); - - let mut cargo_command = Command::new("cargo"); - cargo_command.current_dir("rust_programs"); - - // Do not use the target directory of the workspace please. - cargo_command.env("CARGO_TARGET_DIR", "target"); - - if toolchain.is_some_and(|val| !val.is_empty()) { - cargo_command.arg(toolchain.unwrap()); - } - cargo_command.args(["build", "--target", target, "--profile", profile]); - - let mut rust_flags = "-Cdebuginfo=0".to_string(); - if let Some(linker) = linker { - rust_flags.push_str(" -C linker="); - rust_flags.push_str(linker); - rust_flags.push_str(" -C link-args=-static"); - - cargo_command.env("CPPFLAGS", "-fuse-ld=lld"); - } - - cargo_command.env("RUSTFLAGS", rust_flags); - - trace!("running cargo"); - - if log::log_enabled!(log::Level::Trace) { - cargo_command.stdout(std::process::Stdio::inherit()); - cargo_command.stderr(std::process::Stdio::inherit()); - } - - let output = cargo_command.output(); - trace!("cargo is done"); - - if let Ok(output) = output { - if output.status.success() { - true - } else { - error!( - "Failed to compile code for rust intrinsics\n\nstdout:\n{}\n\nstderr:\n{}", - std::str::from_utf8(&output.stdout).unwrap_or(""), - std::str::from_utf8(&output.stderr).unwrap_or("") - ); - false - } - } else { - error!("Command failed: {output:#?}"); - false - } -} - -pub fn generate_rust_test_loop( +/// Writes the body of an intrinsic test to `w` for `intrinsic`. +/// +/// Each specialisation of the intrinsic (i.e. specific instantiations of the immediate arguments +/// of the intrinsic) is added to an array of specialisations. Each specialisation is tested +/// (first loop) `PASSES` number of times (second loop). For a given iteration of a given +/// specialisation, test values are loaded for each argument and passed to the Rust intrinsic +/// and the C wrapper function, and the results are compared. +fn generate_rust_test_loop( w: &mut impl std::io::Write, intrinsic: &Intrinsic, - indentation: Indentation, - specializations: &[Vec], passes: u32, ) -> std::io::Result<()> { let intrinsic_name = &intrinsic.name; // Each function (and each specialization) has its own type. Erase that type with a cast. - let mut coerce = String::from("unsafe fn("); + let mut coerce = String::from("fn("); + let mut c_coerce = String::from("fn(_, "); for _ in intrinsic.arguments.iter().filter(|a| !a.has_constraint()) { coerce += "_, "; + c_coerce += "_, "; } coerce += ") -> _"; - - match specializations { - [] => { - writeln!(w, " let specializations = [(\"\", {intrinsic_name})];")?; - } - [const_args] if const_args.is_empty() => { - writeln!(w, " let specializations = [(\"\", {intrinsic_name})];")?; - } - _ => { - writeln!(w, " let specializations = [")?; - - for specialization in specializations { - let mut specialization: Vec<_> = - specialization.iter().map(|d| d.to_string()).collect(); - - let const_args = specialization.join(","); - - // The identifier is reversed. - specialization.reverse(); - let id = specialization.join("-"); - - writeln!( - w, - " (\"-{id}\", {intrinsic_name}::<{const_args}> as {coerce})," - )?; - } - - writeln!(w, " ];")?; - } + c_coerce += ")"; + + if intrinsic + .arguments + .iter() + .filter(|arg| arg.has_constraint()) + .count() + == 0 + { + writeln!( + w, + " let specializations = [(\"\", {intrinsic_name}, {intrinsic_name}_wrapper)];" + )?; + } else { + writeln!(w, " let specializations = [")?; + + intrinsic.iter_specializations(|imm_values| { + writeln!( + w, + " (\"{const_args}\", {intrinsic_name}::<{const_args}> as unsafe {coerce}, {intrinsic_name}_wrapper_{c_const_args} as unsafe extern \"C\" {c_coerce}),", + const_args = imm_values.iter().join(","), + c_const_args = imm_values.iter().join("_"), + ) + })?; + + writeln!(w, " ];")?; } + let (cast_prefix, cast_suffix) = if intrinsic.results.is_simd() { + ( + format!( + "std::mem::transmute::<_, [{}; {}]>(", + intrinsic.results.rust_scalar_type().replace("f", "NanEqF"), + intrinsic.results.num_lanes() * intrinsic.results.num_vectors() + ), + ")", + ) + } else if intrinsic.results.kind == TypeKind::Float { + ( + match intrinsic.results.inner_size() { + 16 => format!("NanEqF16("), + 32 => format!("NanEqF32("), + 64 => format!("NanEqF64("), + _ => unimplemented!(), + }, + ")", + ) + } else { + ("".to_string(), "") + }; + write!( w, concatln!( - " for (id, f) in specializations {{", + " for (id, rust, c) in specializations {{", " for i in 0..{passes} {{", " unsafe {{", "{loaded_args}", - " let __return_value = f({args});", - " println!(\"Result {{id}}-{{}}: {{:?}}\", i + 1, {return_value});", + " let __rust_return_value = rust({rust_args});", + "", + " let mut __c_return_value = std::mem::MaybeUninit::uninit();", + " c(__c_return_value.as_mut_ptr(){c_args});", + " let __c_return_value = __c_return_value.assume_init();", + "", + " assert_eq!({cast_prefix}__rust_return_value{cast_suffix}, {cast_prefix}__c_return_value{cast_suffix}, \"{{id}}\");", " }}", " }}", " }}", ), - loaded_args = intrinsic.arguments.load_values_rust(indentation.nest_by(4)), - args = intrinsic.arguments.as_call_param_rust(), - return_value = intrinsic.results.print_result_rust(), + loaded_args = intrinsic.arguments.load_values_rust(), + rust_args = intrinsic.arguments.as_call_param_rust(), + c_args = intrinsic.arguments.as_c_call_param_rust(), passes = passes, + cast_prefix = cast_prefix, + cast_suffix = cast_suffix, ) } -/// Generate the specializations (unique sequences of const-generic arguments) for this intrinsic. -fn generate_rust_specializations( - constraints: &mut impl Iterator>, -) -> Vec> { - let mut specializations = vec![vec![]]; - - for constraint in constraints { - specializations = constraint - .flat_map(|right| { - specializations.iter().map(move |left| { - let mut left = left.clone(); - left.push(i32::try_from(right).unwrap()); - left - }) - }) - .collect(); - } +/// Writes a test function for an given intrinsic to `w`, with a body generated by +/// `generate_rust_test_loop`. +fn create_rust_test( + w: &mut impl std::io::Write, + intrinsic: &Intrinsic, +) -> std::io::Result<()> { + trace!("generating `{}`", intrinsic.name); + + write!( + w, + concatln!("#[test]", "fn test_{intrinsic_name}() {{"), + intrinsic_name = intrinsic.name, + )?; + + generate_rust_test_loop(w, intrinsic, PASSES)?; + + writeln!(w, "}}")?; - specializations + Ok(()) } -// Top-level function to create complete test program -pub fn create_rust_test_module( +/// Writes an `extern "C"` block with function declarations for each of the C wrapper functions into +/// `w`. +pub fn write_bindings_rust( w: &mut impl std::io::Write, - intrinsic: &Intrinsic, + i: usize, + intrinsics: &[Intrinsic], ) -> std::io::Result<()> { - trace!("generating `{}`", intrinsic.name); - let indentation = Indentation::default(); + write!( + w, + concatln!( + "#[allow(improper_ctypes)]", + "#[link(name = \"wrapper_{i}\")]", + "unsafe extern \"C\" {{" + ), + i = i + )?; - writeln!(w, "pub fn run_{}() {{", intrinsic.name)?; + for intrinsic in intrinsics { + intrinsic.iter_specializations(|imm_values| { + writeln!( + w, + " fn {name}_wrapper{imm_arglist}(__dst: *mut {return_ty}{arglist});", + return_ty = intrinsic.results.rust_type(), + name = intrinsic.name, + imm_arglist = imm_values + .iter() + .format_with("", |i, fmt| fmt(&format_args!("_{i}"))), + arglist = intrinsic.arguments.as_non_imm_arglist_rust(), + ) + })?; + } - // Define the arrays of arguments. - let arguments = &intrinsic.arguments; - arguments.gen_arglists_rust(w, indentation.nested(), PASSES)?; + writeln!(w, "}}") +} - // Define any const generics as `const` items, then generate the actual test loop. - let specializations = generate_rust_specializations( - &mut arguments - .iter() - .filter_map(|i| i.constraint.as_ref().map(|v| v.iter())), - ); +/// Writes a `build.rs` into `w` for each test crate that compiles the corresponding C source code +/// with wrapper functions. +pub fn write_build_rs( + w: &mut impl std::io::Write, + i: usize, + arch_flags: &[&str], + cli_options: &ProcessedCli, +) -> std::io::Result<()> { + const COMMON_FLAGS: &[&str] = &["-ffp-contract=off", "-Wno-narrowing"]; + const CLANG_FLAGS: &[&str] = &["-ffp-model=strict"]; + const GCC_FLAGS: &[&str] = &[ + "-flax-vector-conversions", + "-fno-fast-math", + "-frounding-math", + "-fexcess-precision=standard", + "-ftrapping-math", + "-fsignaling-nans", + ]; - generate_rust_test_loop(w, intrinsic, indentation, &specializations, PASSES)?; + write!( + w, + concatln!( + "fn main() {{", + " cc::Build::new()", + " .file(\"../../c_programs/wrapper_{i}.c\")", + " .opt_level(2)", + " .flags(&[", + ), + i = i + )?; - writeln!(w, "}}")?; + let compiler_specific_flags = match cli_options.cc_arg_style { + CcArgStyle::Gcc => GCC_FLAGS, + CcArgStyle::Clang => CLANG_FLAGS, + }; - Ok(()) + for flag in COMMON_FLAGS + .iter() + .chain(compiler_specific_flags) + .chain(arch_flags) + { + writeln!(w, "\"{flag}\",")?; + } + + write!( + w, + concatln!(" ])", " .compile(\"wrapper_{i}\");", "}}"), + i = i + ) } diff --git a/stdarch/crates/intrinsic-test/src/common/indentation.rs b/stdarch/crates/intrinsic-test/src/common/indentation.rs deleted file mode 100644 index 9c2cc886e6544..0000000000000 --- a/stdarch/crates/intrinsic-test/src/common/indentation.rs +++ /dev/null @@ -1,26 +0,0 @@ -//! Basic code formatting tools. -//! -//! We don't need perfect formatting for the generated tests, but simple indentation can make -//! debugging a lot easier. - -#[derive(Copy, Clone, Debug, Default)] -pub struct Indentation(u32); - -impl Indentation { - pub fn nested(self) -> Self { - Self(self.0 + 1) - } - - pub fn nest_by(&self, additional_levels: u32) -> Self { - Self(self.0 + additional_levels) - } -} - -impl std::fmt::Display for Indentation { - fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { - for _ in 0..self.0 { - write!(f, " ")?; - } - Ok(()) - } -} diff --git a/stdarch/crates/intrinsic-test/src/common/intrinsic.rs b/stdarch/crates/intrinsic-test/src/common/intrinsic.rs index 81f6d6d8b5b2c..d69644388a830 100644 --- a/stdarch/crates/intrinsic-test/src/common/intrinsic.rs +++ b/stdarch/crates/intrinsic-test/src/common/intrinsic.rs @@ -1,3 +1,5 @@ +use crate::common::constraint::Constraint; + use super::argument::ArgumentList; use super::intrinsic_helpers::IntrinsicTypeDefinition; @@ -16,3 +18,47 @@ pub struct Intrinsic { /// Any architecture-specific tags. pub arch_tags: Vec, } + +/// Invokes `f` for each combination of the values in the constraint ranges. +/// +/// For example, given `constraints=[Equal(0), Range(1..2), Set([3, 4])]` and `imm_values=[]`, this +/// produces the four calls to `f`: `f([0, 1, 3])`, `f([0, 1, 4])`, `f([0, 2, 3])`, `f([0, 2, 4])`. +fn recurse_specializations<'a, E>( + constraints: &mut (impl Iterator + Clone), + imm_values: &mut Vec, + f: &mut impl FnMut(&[i64]) -> Result<(), E>, +) -> Result<(), E> { + if let Some(current) = constraints.next() { + for i in current.iter() { + imm_values.push(i); + recurse_specializations(&mut constraints.clone(), imm_values, f)?; + imm_values.pop(); + } + Ok(()) + } else { + f(&imm_values) + } +} + +impl Intrinsic { + /// Invokes `f` for "specialisation" of the intrinsic - a specific instantiation of the + /// constant generics of the intrinsic. `f` takes a slice where the `i`th element corresponds + /// to the value of the `i`th const generic argument of the intrinsic. + /// + /// For an intrinsic with three arguments with constraints `Equal(0)`, `Range(1..2)`, + /// `Set([3, 4])` respectively, this would produce four calls to `f`: `f(0, 1, 3)`, + /// `f(0, 1, 4)`, `f(0, 2, 3)`, `f(0, 2, 4)`. + pub fn iter_specializations( + &self, + mut f: impl FnMut(&[i64]) -> Result<(), E>, + ) -> Result<(), E> { + recurse_specializations( + &mut self + .arguments + .iter() + .filter_map(|arg| arg.constraint.as_ref()), + &mut Vec::new(), + &mut f, + ) + } +} diff --git a/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs index a14d7ef05f539..a894d5c0164e1 100644 --- a/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs +++ b/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs @@ -5,8 +5,6 @@ use std::str::FromStr; use itertools::Itertools as _; -use super::cli::Language; -use super::indentation::Indentation; use super::values::value_for_array; #[derive(Debug, PartialEq, Copy, Clone)] @@ -17,6 +15,7 @@ pub enum Sign { #[derive(Debug, PartialEq, Copy, Clone)] pub enum TypeKind { + Bool, BFloat, Float, Int(Sign), @@ -25,6 +24,8 @@ pub enum TypeKind { Void, Mask, Vector, + SvPattern, + SvPrefetchOp, } impl FromStr for TypeKind { @@ -32,17 +33,22 @@ impl FromStr for TypeKind { fn from_str(s: &str) -> Result { match s { - "bfloat" | "BF16" => Ok(Self::BFloat), - "float" | "double" | "FP16" | "FP32" | "FP64" => Ok(Self::Float), - "int" | "long" | "short" | "SI8" | "SI16" | "SI32" | "SI64" => { + "svbool" | "bool" => Ok(Self::Bool), + "svbfloat" | "bfloat" | "BF16" => Ok(Self::BFloat), + "svfloat" | "float" | "double" | "FP16" | "FP32" | "FP64" => Ok(Self::Float), + "svint" | "int" | "long" | "short" | "SI8" | "SI16" | "SI32" | "SI64" => { Ok(Self::Int(Sign::Signed)) } "poly" => Ok(Self::Poly), "char" => Ok(Self::Char(Sign::Signed)), - "uint" | "unsigned" | "UI8" | "UI16" | "UI32" | "UI64" => Ok(Self::Int(Sign::Unsigned)), + "svuint" | "uint" | "unsigned" | "UI8" | "UI16" | "UI32" | "UI64" => { + Ok(Self::Int(Sign::Unsigned)) + } "void" => Ok(Self::Void), "MASK" => Ok(Self::Mask), "M128" | "M256" | "M512" => Ok(Self::Vector), + "svpattern" => Ok(Self::SvPattern), + "svprfop" => Ok(Self::SvPrefetchOp), _ => Err(format!("Impossible to parse argument kind {s}")), } } @@ -54,6 +60,7 @@ impl fmt::Display for TypeKind { f, "{}", match self { + Self::Bool => "bool", Self::BFloat => "bfloat", Self::Float => "float", Self::Int(Sign::Signed) => "int", @@ -64,15 +71,18 @@ impl fmt::Display for TypeKind { Self::Char(Sign::Unsigned) => "unsigned char", Self::Mask => "mask", Self::Vector => "vector", + Self::SvPattern => "svpattern", + Self::SvPrefetchOp => "svprfop", } ) } } impl TypeKind { - /// Gets the type part of a c typedef for a type that's in the form of {type}{size}_t. + /// Returns the type component of a C typedef for a type of the form of `{type}{size}_t` pub fn c_prefix(&self) -> &str { match self { + Self::Bool => "bool", Self::Float => "float", Self::Int(Sign::Signed) => "int", Self::Int(Sign::Unsigned) => "uint", @@ -84,7 +94,7 @@ impl TypeKind { } } - /// Gets the rust prefix for the type kind i.e. i, u, f. + /// Returns the Rust prefix for this type kind i.e. `i`, `u`, or `f`. pub fn rust_prefix(&self) -> &str { match self { Self::BFloat => "bf", @@ -94,42 +104,66 @@ impl TypeKind { Self::Poly => "u", Self::Char(Sign::Unsigned) => "u", Self::Char(Sign::Signed) => "i", + Self::Mask => "u", _ => unreachable!("Unused type kind: {self:#?}"), } } } +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SimdLen { + Scalable, + Fixed(u32), +} + +impl std::fmt::Display for SimdLen { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Scalable => unimplemented!(), + Self::Fixed(len) => ::fmt(len, f), + } + } +} + #[derive(Debug, PartialEq, Clone)] pub struct IntrinsicType { + /// Is this an immediate? pub constant: bool, - /// whether this object is a const pointer + /// Is this is a const pointer to the type? pub ptr_constant: bool, + /// Is this is a pointer to the type? pub ptr: bool, + /// Element type (e.g. `TypeKind::Int(Sign::Unsigned)` for `uint64x2_t`). pub kind: TypeKind, - /// The bit length of this type (e.g. 32 for u32). - pub bit_len: Option, - /// Length of the SIMD vector (i.e. 4 for uint32x4_t), A value of `None` - /// means this is not a simd type. A `None` can be assumed to be 1, - /// although in some places a distinction is needed between `u64` and - /// `uint64x1_t` this signals that. - pub simd_len: Option, + /// Number of bits of this type (e.g. 32 for `u32`). + pub bit_len: Option, - /// The number of rows for SIMD matrices (i.e. 2 for uint8x8x2_t). - /// A value of `None` represents a type that does not contain any - /// rows encoded in the type (e.g. uint8x8_t). - /// A value of `None` can be assumed to be 1 though. + /// Length of a SIMD vector (i.e. `Fixed(4)` for `uint32x4_t`). + /// + /// A value of `None` means this is not a SIMD type. The number of lanes of a type with + /// `simd_len=None` can be assumed to be one, though it is important to maintain a distinction + /// between `simd_len=None` and `simd_len=Some(Fixed(1))` so as to differentiate between `u64` + /// and `uint64x1_t`. A value of `Some(Scalable)` indicates that this is a scalable vector. + pub simd_len: Option, + + /// Number of rows of a SIMD matrix (i.e. 2 for `uint8x8x2_t`). + /// + /// A value of `None` means this is not a SIMD matrix (e.g. `uint8x8_t`). The number of rows of + /// a type with `vec_len=None` can be assumed to be one. pub vec_len: Option, } impl IntrinsicType { + /// Returns the element type pub fn kind(&self) -> TypeKind { self.kind } + /// Returns the number of bits of the type (with a minimum of `8`) pub fn inner_size(&self) -> u32 { if let Some(bl) = self.bit_len { cmp::max(bl, 8) @@ -138,101 +172,54 @@ impl IntrinsicType { } } + /// Returns the number of lanes of the type pub fn num_lanes(&self) -> u32 { - self.simd_len.unwrap_or(1) + self.simd_len + .as_ref() + .map(|len| match len { + SimdLen::Scalable => unimplemented!(), + SimdLen::Fixed(len) => *len, + }) + .unwrap_or(1) } + /// Returns the number of vectors of the type pub fn num_vectors(&self) -> u32 { self.vec_len.unwrap_or(1) } + /// Returns `true` if this represents a SIMD vector pub fn is_simd(&self) -> bool { self.simd_len.is_some() || self.vec_len.is_some() } + /// Returns `true` if this is a pointer pub fn is_ptr(&self) -> bool { self.ptr } - pub fn c_scalar_type(&self) -> String { - match self.kind() { - TypeKind::Char(_) => String::from("char"), - TypeKind::Vector => String::from("int32_t"), - _ => format!( - "{prefix}{bits}_t", - prefix = self.kind().c_prefix(), - bits = self.inner_size() - ), - } - } - - pub fn c_promotion(&self) -> &str { - match *self { - IntrinsicType { - kind, - bit_len: Some(8), - .. - } => match kind { - TypeKind::Int(Sign::Signed) => "int", - TypeKind::Int(Sign::Unsigned) => "unsigned int", - TypeKind::Poly => "uint8_t", - _ => "", - }, - IntrinsicType { - kind: TypeKind::Poly, - bit_len: Some(bit_len), - .. - } => match bit_len { - 8 => unreachable!("handled above"), - 16 => "uint16_t", - 32 => "uint32_t", - 64 => "uint64_t", - 128 => "", - _ => panic!("invalid bit_len"), - }, - IntrinsicType { - kind: TypeKind::Float, - bit_len: Some(bit_len), - .. - } => match bit_len { - 16 => "float16_t", - 32 => "float", - 64 => "double", - 128 => "", - _ => panic!("invalid bit_len"), - }, - IntrinsicType { - kind: TypeKind::Char(_), - .. - } => "char", - _ => "", - } - } - - pub fn populate_random( - &self, - indentation: Indentation, - loads: u32, - language: &Language, - ) -> String { + /// Returns the elements used in the test value arrays in `gen_arg_rust`. Uses the same + /// `num_lanes * num_vectors + loads - 1` arithmetic to produce the number of values that + /// `ArgumentList::gen_arg_rust` expects and `ArgumentList::load_values_rust` needs. + /// + /// Each value in the array starts as a bit pattern from `common::values::value_from_array` + /// which is then printed as a hex value in the generated code (and if identified as a negative + /// value, with the appropriate minus and corrected hex pattern). Calls to `fN::from_bits` are + /// generated for floats. + pub fn populate_random(&self, loads: u32) -> String { match self { IntrinsicType { bit_len: Some(bit_len @ (1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 16 | 32 | 64)), kind: kind @ (TypeKind::Int(_) | TypeKind::Poly | TypeKind::Char(_) | TypeKind::Mask), - simd_len, vec_len, .. } => { - let (prefix, suffix) = match language { - Language::Rust => ('[', ']'), - Language::C => ('{', '}'), - }; - let body_indentation = indentation.nested(); format!( - "{prefix}\n{body}\n{indentation}{suffix}", - body = (0..(simd_len.unwrap_or(1) * vec_len.unwrap_or(1) + loads - 1)) - .format_with(",\n", |i, fmt| { + "[\n{body}\n]", + body = (0..(self.num_lanes() * vec_len.unwrap_or(1) + loads - 1)).format_with( + ",\n", + |i, fmt| { let src = value_for_array(*bit_len, i); assert!(src == 0 || src.ilog2() < *bit_len); if *kind == TypeKind::Int(Sign::Signed) && (src >> (*bit_len - 1)) != 0 @@ -241,62 +228,43 @@ impl IntrinsicType { let mask = !0u64 >> (64 - *bit_len); let ones_compl = src ^ mask; let twos_compl = ones_compl + 1; - if (twos_compl == src) && (language == &Language::C) { - // `src` is INT*_MIN. C requires `-0x7fffffff - 1` to avoid - // undefined literal overflow behaviour. - fmt(&format_args!("{body_indentation}-{ones_compl:#x} - 1")) - } else { - fmt(&format_args!("{body_indentation}-{twos_compl:#x}")) - } + fmt(&format_args!("-{twos_compl:#x}")) } else { - fmt(&format_args!("{body_indentation}{src:#x}")) + fmt(&format_args!("{src:#x}")) } - }) + } + ) ) } IntrinsicType { kind: TypeKind::Float, bit_len: Some(bit_len @ (16 | 32 | 64)), - simd_len, vec_len, .. } => { - let (prefix, cast_prefix, cast_suffix, suffix) = match (language, bit_len) { - (&Language::Rust, 16) => ('[', "f16::from_bits(", ")", ']'), - (&Language::Rust, 32) => ('[', "f32::from_bits(", ")", ']'), - (&Language::Rust, 64) => ('[', "f64::from_bits(", ")", ']'), - (&Language::C, 16) => ('{', "cast(", ")", '}'), - (&Language::C, 32) => ('{', "cast(", ")", '}'), - (&Language::C, 64) => ('{', "cast(", ")", '}'), - _ => unreachable!(), - }; format!( - "{prefix}\n{body}\n{indentation}{suffix}", - body = (0..(simd_len.unwrap_or(1) * vec_len.unwrap_or(1) + loads - 1)) - .format_with(",\n", |i, fmt| fmt(&format_args!( - "{indentation}{cast_prefix}{src:#x}{cast_suffix}", - indentation = indentation.nested(), + "[\n{body}\n]", + body = (0..(self.num_lanes() * vec_len.unwrap_or(1) + loads - 1)).format_with( + ",\n", + |i, fmt| fmt(&format_args!( + "f{bit_len}::from_bits({src:#x})", src = value_for_array(*bit_len, i) - ))) + )) + ) ) } IntrinsicType { kind: TypeKind::Vector, bit_len: Some(128 | 256 | 512), - simd_len, vec_len, .. } => { - let (prefix, suffix) = match language { - Language::Rust => ('[', ']'), - Language::C => ('{', '}'), - }; - let body_indentation = indentation.nested(); let effective_bit_len = 32; format!( - "{prefix}\n{body}\n{indentation}{suffix}", - body = (0..(vec_len.unwrap_or(1) * simd_len.unwrap_or(1) + loads - 1)) - .format_with(",\n", |i, fmt| { + "[\n{body}\n]", + body = (0..(vec_len.unwrap_or(1) * self.num_lanes() + loads - 1)).format_with( + ",\n", + |i, fmt| { let src = value_for_array(effective_bit_len, i); assert!(src == 0 || src.ilog2() < effective_bit_len); if (src >> (effective_bit_len - 1)) != 0 { @@ -304,89 +272,40 @@ impl IntrinsicType { let mask = !0u64 >> (64 - effective_bit_len); let ones_compl = src ^ mask; let twos_compl = ones_compl + 1; - if (twos_compl == src) && (language == &Language::C) { - // `src` is INT*_MIN. C requires `-0x7fffffff - 1` to avoid - // undefined literal overflow behaviour. - fmt(&format_args!("{body_indentation}-{ones_compl:#x} - 1")) - } else { - fmt(&format_args!("{body_indentation}-{twos_compl:#x}")) - } + fmt(&format_args!("-{twos_compl:#x}")) } else { - fmt(&format_args!("{body_indentation}{src:#x}")) + fmt(&format_args!("{src:#x}")) } - }) + } + ) ) } _ => unimplemented!("populate random: {self:#?}"), } } - - pub fn is_rust_vals_array_const(&self) -> bool { - match self { - // Floats have to be loaded at runtime for stable NaN conversion. - IntrinsicType { - kind: TypeKind::Float, - .. - } => false, - IntrinsicType { - kind: TypeKind::Int(_) | TypeKind::Poly, - .. - } => true, - _ => true, - } - } - - pub fn as_call_param_c(&self, name: &String) -> String { - if self.ptr { - format!("&{name}") - } else { - name.clone() - } - } } pub trait IntrinsicTypeDefinition: Deref { /// Determines the load function for this type. - /// can be implemented in an `impl` block - fn get_load_function(&self, _language: Language) -> String; - - /// can be implemented in an `impl` block - fn get_lane_function(&self) -> String; + fn get_load_function(&self) -> String; - /// Gets a string containing the typename for this type in C format. - /// can be directly defined in `impl` blocks + /// Gets a string containing the typename for this type in C. fn c_type(&self) -> String; - /// can be directly defined in `impl` blocks - fn c_single_vector_type(&self) -> String; - - /// Generates a std::cout for the intrinsics results that will match the - /// rust debug output format for the return type. The generated line assumes - /// there is an int i in scope which is the current pass number. - fn print_result_c(&self, indentation: Indentation, additional: &str) -> String; + /// Gets a string containing the typename for this type in Rust. + fn rust_type(&self) -> String; - /// Generates a std::cout for the intrinsics results that will match the - /// rust debug output format for the return type. The generated line assumes - /// there is an int i in scope which is the current pass number. - fn print_result_rust(&self) -> String { - String::from("format_args!(\"{__return_value:.150?}\")") - } - - /// To enable architecture-specific logic + /// Gets a string containing the name of the scalar type corresponding to this type if it is a + /// vector. fn rust_scalar_type(&self) -> String { - format!( - "{prefix}{bits}", - prefix = self.kind().rust_prefix(), - bits = self.inner_size() - ) - } - - fn generate_final_type_cast(&self) -> String { - let type_data = self.c_promotion(); - if type_data.len() > 2 { - format!("({type_data})") + if self.is_simd() { + format!( + "{prefix}{bits}", + prefix = self.kind().rust_prefix(), + bits = self.inner_size() + ) } else { - String::new() + self.rust_type() } } } diff --git a/stdarch/crates/intrinsic-test/src/common/mod.rs b/stdarch/crates/intrinsic-test/src/common/mod.rs index a1062b3a87dbc..3775e453c24b0 100644 --- a/stdarch/crates/intrinsic-test/src/common/mod.rs +++ b/stdarch/crates/intrinsic-test/src/common/mod.rs @@ -1,15 +1,13 @@ -use std::fs::File; +use std::{fs::File, io}; use rayon::prelude::*; use cli::ProcessedCli; use crate::common::{ - compile_c::CppCompilation, - gen_c::{write_main_cpp, write_mod_cpp}, + gen_c::write_wrapper_c, gen_rust::{ - compile_rust_programs, write_bin_cargo_toml, write_lib_cargo_toml, write_lib_rs, - write_main_rs, + run_rustfmt, write_bin_cargo_toml, write_build_rs, write_lib_cargo_toml, write_lib_rs, }, intrinsic::Intrinsic, intrinsic_helpers::IntrinsicTypeDefinition, @@ -17,156 +15,77 @@ use crate::common::{ pub mod argument; pub mod cli; -pub mod compare; -pub mod compile_c; pub mod constraint; -pub mod gen_c; -pub mod gen_rust; -pub mod indentation; pub mod intrinsic; pub mod intrinsic_helpers; -pub mod values; + +mod gen_c; +mod gen_rust; +mod values; /// Architectures must support this trait /// to be successfully tested. pub trait SupportedArchitectureTest { type IntrinsicImpl: IntrinsicTypeDefinition + Sync; - fn cli_options(&self) -> &ProcessedCli; fn intrinsics(&self) -> &[Intrinsic]; - fn create(cli_options: ProcessedCli) -> Self; + fn create(cli_options: &ProcessedCli) -> Self; const NOTICE: &str; const PLATFORM_C_HEADERS: &[&str]; - const PLATFORM_C_DEFINITIONS: &str; - const PLATFORM_C_FORWARD_DECLARATIONS: &str; const PLATFORM_RUST_CFGS: &str; const PLATFORM_RUST_DEFINITIONS: &str; - fn cpp_compilation(&self) -> Option; - - fn build_c_file(&self) -> bool { - let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 400); + fn arch_flags(&self, cli_options: &ProcessedCli) -> Vec<&str>; - let cpp_compiler_wrapped = self.cpp_compilation(); + fn generate_c_file(&self) { + let (max_chunk_size, _chunk_count) = manual_chunk(self.intrinsics().len()); std::fs::create_dir_all("c_programs").unwrap(); self.intrinsics() - .par_chunks(chunk_size) + .par_chunks(max_chunk_size) .enumerate() .map(|(i, chunk)| { - let c_filename = format!("c_programs/mod_{i}.cpp"); + let c_filename = format!("c_programs/wrapper_{i}.c"); let mut file = File::create(&c_filename).unwrap(); - let mod_file_write_result = write_mod_cpp( - &mut file, - Self::NOTICE, - Self::PLATFORM_C_HEADERS, - Self::PLATFORM_C_FORWARD_DECLARATIONS, - chunk, - ); - - if let Err(error) = mod_file_write_result { - return Err(format!("Error writing to mod_{i}.cpp: {error:?}")); - } - - // compile this cpp file into a .o file. - // - // This is done because `cpp_compiler_wrapped` is None when - // the --generate-only flag is passed - trace!("compiling mod_{i}.cpp"); - if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() { - let compile_output = cpp_compiler - .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o")) - .map_err(|e| format!("Error compiling mod_{i}.cpp: {e:?}"))?; - - assert!( - compile_output.status.success(), - "{}", - String::from_utf8_lossy(&compile_output.stderr) - ); - - trace!("finished compiling mod_{i}.cpp"); - } - Ok(()) + write_wrapper_c(&mut file, Self::NOTICE, Self::PLATFORM_C_HEADERS, chunk) }) - .collect::>() + .collect::>() .unwrap(); - - let mut file = File::create("c_programs/main.cpp").unwrap(); - write_main_cpp( - &mut file, - Self::PLATFORM_C_DEFINITIONS, - Self::PLATFORM_C_HEADERS, - self.intrinsics().iter().map(|i| i.name.as_str()), - ) - .unwrap(); - - // This is done because `cpp_compiler_wrapped` is None when - // the --generate-only flag is passed - if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() { - // compile this cpp file into a .o file - trace!("compiling main.cpp"); - let output = cpp_compiler - .compile_object_file("main.cpp", "intrinsic-test-programs.o") - .unwrap(); - assert!(output.status.success(), "{output:?}"); - - let object_files = (0..chunk_count) - .map(|i| format!("mod_{i}.o")) - .chain(["intrinsic-test-programs.o".to_owned()]); - - let output = cpp_compiler - .link_executable(object_files, "intrinsic-test-programs") - .unwrap(); - assert!(output.status.success(), "{output:?}"); - } - - true } - fn build_rust_file(&self) -> bool { - std::fs::create_dir_all("rust_programs/src").unwrap(); + fn generate_rust_file(&self, cli_options: &ProcessedCli) { + let arch_flags = self.arch_flags(cli_options); + + std::fs::create_dir_all("rust_programs").unwrap(); - let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 400); + let (max_chunk_size, chunk_count) = manual_chunk(self.intrinsics().len()); let mut cargo = File::create("rust_programs/Cargo.toml").unwrap(); write_bin_cargo_toml(&mut cargo, chunk_count).unwrap(); - let mut main_rs = File::create("rust_programs/src/main.rs").unwrap(); - write_main_rs( - &mut main_rs, - chunk_count, - Self::PLATFORM_RUST_CFGS, - "", - self.intrinsics().iter().map(|i| i.name.as_str()), - ) - .unwrap(); - - let target = &self.cli_options().target; - let profile = &self.cli_options().profile; - let toolchain = self.cli_options().toolchain.as_deref(); - let linker = self.cli_options().linker.as_deref(); - self.intrinsics() - .par_chunks(chunk_size) + .chunks(max_chunk_size) .enumerate() .map(|(i, chunk)| { std::fs::create_dir_all(format!("rust_programs/mod_{i}/src"))?; let rust_filename = format!("rust_programs/mod_{i}/src/lib.rs"); trace!("generating `{rust_filename}`"); - let mut file = File::create(rust_filename)?; + let mut file = File::create(&rust_filename)?; write_lib_rs( &mut file, Self::NOTICE, Self::PLATFORM_RUST_CFGS, Self::PLATFORM_RUST_DEFINITIONS, + i, chunk, )?; + run_rustfmt(&rust_filename); let toml_filename = format!("rust_programs/mod_{i}/Cargo.toml"); trace!("generating `{toml_filename}`"); @@ -174,41 +93,23 @@ pub trait SupportedArchitectureTest { write_lib_cargo_toml(&mut file, &format!("mod_{i}"))?; + let build_rs_filename = format!("rust_programs/mod_{i}/build.rs"); + trace!("generating `{build_rs_filename}`"); + let mut file = File::create(&build_rs_filename).unwrap(); + + write_build_rs(&mut file, i, &arch_flags, &cli_options).unwrap(); + run_rustfmt(&build_rs_filename); + Ok(()) }) .collect::>() .unwrap(); - - compile_rust_programs(toolchain, target, profile, linker) - } - - fn compare_outputs(&self) -> bool { - if self.cli_options().toolchain.is_some() { - let intrinsics_name_list = self - .intrinsics() - .iter() - .map(|i| i.name.clone()) - .collect::>(); - - compare::compare_outputs( - &intrinsics_name_list, - &self.cli_options().runner, - &self.cli_options().target, - &self.cli_options().profile, - ) - } else { - true - } } } -// pub fn chunk_info(intrinsic_count: usize) -> (usize, usize) { -// let available_parallelism = std::thread::available_parallelism().unwrap().get(); -// let chunk_size = intrinsic_count.div_ceil(Ord::min(available_parallelism, intrinsic_count)); - -// (chunk_size, intrinsic_count.div_ceil(chunk_size)) -// } - -pub fn manual_chunk(intrinsic_count: usize, chunk_size: usize) -> (usize, usize) { - (chunk_size, intrinsic_count.div_ceil(chunk_size)) +pub fn manual_chunk(intrinsic_count: usize) -> (usize, usize) { + let ncores = std::thread::available_parallelism().unwrap().into(); + let max_intrinsics_per_chunk = intrinsic_count.div_ceil(ncores); + let number_of_chunks = intrinsic_count.div_ceil(max_intrinsics_per_chunk); + (max_intrinsics_per_chunk, number_of_chunks) } diff --git a/stdarch/crates/intrinsic-test/src/common/values.rs b/stdarch/crates/intrinsic-test/src/common/values.rs index 6c94ef2c22e1d..01dc0713f0f00 100644 --- a/stdarch/crates/intrinsic-test/src/common/values.rs +++ b/stdarch/crates/intrinsic-test/src/common/values.rs @@ -1,6 +1,12 @@ -/// Get a single value for an argument values array in a determistic way. -/// * `bits`: The number of bits for the type, only 8, 16, 32, 64 are valid values -/// * `index`: The position in the array we are generating for +/// Returns a bit pattern for a value being output into a array of test values. Bit patterns come +/// from one of many constant arrays of test values. The specific constant array used depends on +/// the number of bits - `bits` - of the type having test values generated for it. This function +/// is called repeatedly with incrementing values of `index` to produce an entire array of test +/// values. +/// +/// Each constant array of bit patterns should ideally be at least the length of the largest array +/// of test values that will be requested (e.g. 51 for a `poly8x8x4` when `PASSES=20`: +/// `(8 * 4) + 20 - 1`), otherwise values will be repeated. pub fn value_for_array(bits: u32, index: u32) -> u64 { let index = index as usize; match bits { diff --git a/stdarch/crates/intrinsic-test/src/main.rs b/stdarch/crates/intrinsic-test/src/main.rs index e5c846877ce6d..4c0136041fc35 100644 --- a/stdarch/crates/intrinsic-test/src/main.rs +++ b/stdarch/crates/intrinsic-test/src/main.rs @@ -15,27 +15,27 @@ fn main() { let args: Cli = clap::Parser::parse(); let processed_cli_options = ProcessedCli::new(args); - match processed_cli_options.target.as_str() { - "aarch64-unknown-linux-gnu" - | "armv7-unknown-linux-gnueabihf" - | "aarch64_be-unknown-linux-gnu" => run(ArmArchitectureTest::create(processed_cli_options)), - - "x86_64-unknown-linux-gnu" => run(X86ArchitectureTest::create(processed_cli_options)), - _ => std::process::exit(0), + if processed_cli_options.target.starts_with("arm") + | processed_cli_options.target.starts_with("aarch64") + { + run( + ArmArchitectureTest::create(&processed_cli_options), + processed_cli_options, + ) + } else if processed_cli_options.target.starts_with("x86") { + run( + X86ArchitectureTest::create(&processed_cli_options), + processed_cli_options, + ) + } else { + unimplemented!("Unsupported target {}", processed_cli_options.target) } } -fn run(test_environment: impl SupportedArchitectureTest) { +fn run(test_environment: impl SupportedArchitectureTest, processed_cli_options: ProcessedCli) { info!("building C binaries"); - if !test_environment.build_c_file() { - std::process::exit(2); - } + test_environment.generate_c_file(); + info!("building Rust binaries"); - if !test_environment.build_rust_file() { - std::process::exit(3); - } - info!("Running binaries"); - if !test_environment.compare_outputs() { - std::process::exit(1); - } + test_environment.generate_rust_file(&processed_cli_options); } diff --git a/stdarch/crates/intrinsic-test/src/x86/compile.rs b/stdarch/crates/intrinsic-test/src/x86/compile.rs deleted file mode 100644 index 65cd291b1b377..0000000000000 --- a/stdarch/crates/intrinsic-test/src/x86/compile.rs +++ /dev/null @@ -1,59 +0,0 @@ -use crate::common::cli::ProcessedCli; -use crate::common::compile_c::{CompilationCommandBuilder, CppCompilation}; - -pub fn build_cpp_compilation(config: &ProcessedCli) -> Option { - let cpp_compiler = config.cpp_compiler.as_ref()?; - - // -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations - let mut command = CompilationCommandBuilder::new() - .add_arch_flags(["icelake-client"]) - .set_compiler(cpp_compiler) - .set_target(&config.target) - .set_opt_level("2") - .set_cxx_toolchain_dir(config.cxx_toolchain_dir.as_deref()) - .set_project_root("c_programs") - .add_extra_flags(vec![ - "-ffp-contract=off", - "-Wno-narrowing", - "-mavx", - "-mavx2", - "-mavx512f", - "-msse2", - "-mavx512vl", - "-mavx512bw", - "-mavx512dq", - "-mavx512cd", - "-mavx512fp16", - "-msha512", - "-msm3", - "-msm4", - "-mavxvnni", - "-mavxvnniint8", - "-mavxneconvert", - "-mavxifma", - "-mavxvnniint16", - "-mavx512bf16", - "-mavx512bitalg", - "-mavx512ifma", - "-mavx512vbmi", - "-mavx512vbmi2", - "-mavx512vnni", - "-mavx512vpopcntdq", - "-mavx512vp2intersect", - "-mbmi", - "-mbmi2", - "-mgfni", - "-mvaes", - "-mvpclmulqdq", - "-ferror-limit=1000", - "-std=c++23", - ]); - - if !cpp_compiler.contains("clang") { - command = command.add_extra_flag("-flax-vector-conversions"); - } - - let cpp_compiler = command.into_cpp_compilation(); - - Some(cpp_compiler) -} diff --git a/stdarch/crates/intrinsic-test/src/x86/config.rs b/stdarch/crates/intrinsic-test/src/x86/config.rs index 491dbb5147bbc..68737ab5ac4c8 100644 --- a/stdarch/crates/intrinsic-test/src/x86/config.rs +++ b/stdarch/crates/intrinsic-test/src/x86/config.rs @@ -3,7 +3,6 @@ pub const NOTICE: &str = "\ // test are derived from an XML specification, published under the same license as the // `intrinsic-test` crate.\n"; -// Format f16 values (and vectors containing them) in a way that is consistent with C. pub const PLATFORM_RUST_DEFINITIONS: &str = r#" use core_arch::arch::x86_64::*; @@ -129,206 +128,11 @@ unsafe fn _mm512_loadu_epi64_to___m512(mem_addr: *const i64) -> __m512 { _mm512_castsi512_ps(_mm512_loadu_epi64(mem_addr)) } -#[inline] -fn debug_simd_finish( - formatter: &mut core::fmt::Formatter<'_>, - type_name: &str, - array: &[T; N], -) -> core::fmt::Result { - core::fmt::Formatter::debug_tuple_fields_finish( - formatter, - type_name, - &core::array::from_fn::<&dyn core::fmt::Debug, N, _>(|i| &array[i]), - ) -} - -trait DebugAs { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result; -} - -impl DebugAs for T { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "{self}") - } -} - -macro_rules! impl_debug_as { - ($simd:ty, $name:expr, $bits:expr, [$($type:ty),+]) => { - $( - impl DebugAs<$type> for $simd { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - const ELEMENT_BITS: usize = core::mem::size_of::<$type>() * 8; - const NUM_ELEMENTS: usize = $bits / ELEMENT_BITS; - let array = unsafe { core::mem::transmute::<_, [$type; NUM_ELEMENTS]>(*self) }; - debug_simd_finish(f, $name, &array) - } - } - )+ - }; -} - -impl_debug_as!(__m128i, "__m128i", 128, [u8, i8, u16, i16, u32, i32, u64, i64, f16]); -impl_debug_as!(__m256i, "__m256i", 256, [u8, i8, u16, i16, u32, i32, u64, i64]); -impl_debug_as!(__m512i, "__m512i", 512, [u8, i8, u16, i16, u32, i32, u64, i64]); -impl_debug_as!(__m128h, "__m128h", 128, [f32]); -impl_debug_as!(__m256h, "__m256h", 256, [f32]); -impl_debug_as!(__m512h, "__m512h", 512, [f32]); - -fn debug_as(x: V) -> impl core::fmt::Debug -where V: DebugAs -{ - struct DebugWrapper(V, core::marker::PhantomData); - impl, T> core::fmt::Debug for DebugWrapper { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.0.fmt(f) - } - } - DebugWrapper(x, core::marker::PhantomData) -} - -"#; - -pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#" -#ifndef X86_DECLARATIONS -#define X86_DECLARATIONS - typedef _Float16 float16_t; - typedef float float32_t; - typedef double float64_t; - - #define __int64 long long - #define __int32 int - - std::ostream& operator<<(std::ostream& os, _Float16 value); - std::ostream& operator<<(std::ostream& os, __m128i value); - std::ostream& operator<<(std::ostream& os, __m256i value); - std::ostream& operator<<(std::ostream& os, __m512i value); - std::ostream& operator<<(std::ostream& os, __mmask8 value); - - #define _mm512_extract_intrinsic_test_epi8(m, lane) \ - _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16) - - #define _mm512_extract_intrinsic_test_epi16(m, lane) \ - _mm_extract_epi16(_mm512_extracti64x2_epi64((m), (lane) / 8), (lane) % 8) - - #define _mm512_extract_intrinsic_test_epi32(m, lane) \ - _mm_extract_epi32(_mm512_extracti64x2_epi64((m), (lane) / 4), (lane) % 4) - - #define _mm512_extract_intrinsic_test_epi64(m, lane) \ - _mm_extract_epi64(_mm512_extracti64x2_epi64((m), (lane) / 2), (lane) % 2) - - // Load f16 (__m128h) and cast to integer (__m128i) - #define _mm_loadu_ph_to___m128i(mem_addr) _mm_castph_si128(_mm_loadu_ph(mem_addr)) - #define _mm256_loadu_ph_to___m256i(mem_addr) _mm256_castph_si256(_mm256_loadu_ph(mem_addr)) - #define _mm512_loadu_ph_to___m512i(mem_addr) _mm512_castph_si512(_mm512_loadu_ph(mem_addr)) - - // Load f32 (__m128) and cast to f16 (__m128h) - #define _mm_loadu_ps_to___m128h(mem_addr) _mm_castps_ph(_mm_loadu_ps(mem_addr)) - #define _mm256_loadu_ps_to___m256h(mem_addr) _mm256_castps_ph(_mm256_loadu_ps(mem_addr)) - #define _mm512_loadu_ps_to___m512h(mem_addr) _mm512_castps_ph(_mm512_loadu_ps(mem_addr)) - - // Load integer types and cast to double (__m128d, __m256d, __m512d) - #define _mm_loadu_epi16_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi16_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi16_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - #define _mm_loadu_epi32_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi32_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi32_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - #define _mm_loadu_epi64_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi64_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi64_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - // Load integer types and cast to float (__m128, __m256, __m512) - #define _mm_loadu_epi16_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi16_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi16_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - #define _mm_loadu_epi32_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi32_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi32_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - #define _mm_loadu_epi64_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr))) - #define _mm256_loadu_epi64_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr))) - #define _mm512_loadu_epi64_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr))) - - // T1 is the `To` type, T2 is the `From` type - template T1 cast(T2 x) { - if constexpr ((std::is_integral_v && std::is_integral_v) || (std::is_floating_point_v && std::is_floating_point_v)) { - return x; - } else if constexpr (sizeof(T1) <= sizeof(T2)) { - T1 ret{}; - std::memcpy(&ret, &x, sizeof(T1)); - return ret; - } else { - static_assert(sizeof(T1) == sizeof(T2) || std::is_convertible_v, - "T2 must either be convertible to T1, or have the same size as T1!"); - return T1{}; - } - } -#endif -"#; -pub const PLATFORM_C_DEFINITIONS: &str = r#" - -std::ostream& operator<<(std::ostream& os, _Float16 value) { - os << static_cast(value); - return os; -} - -std::ostream& operator<<(std::ostream& os, __m128i value) { - void* temp = malloc(sizeof(__m128i)); - _mm_storeu_si128((__m128i*)temp, value); - std::stringstream ss; - - ss << "0x"; - for(int i = 0; i < 16; i++) { - ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i]; - } - os << ss.str(); - return os; -} - -std::ostream& operator<<(std::ostream& os, __m256i value) { - void* temp = malloc(sizeof(__m256i)); - _mm256_storeu_si256((__m256i*)temp, value); - std::stringstream ss; - - ss << "0x"; - for(int i = 0; i < 32; i++) { - ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i]; - } - os << ss.str(); - return os; -} - -std::ostream& operator<<(std::ostream& os, __m512i value) { - void* temp = malloc(sizeof(__m512i)); - _mm512_storeu_si512((__m512i*)temp, value); - std::stringstream ss; - - ss << "0x"; - for(int i = 0; i < 64; i++) { - ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i]; - } - os << ss.str(); - return os; -} - -std::ostream& operator<<(std::ostream& os, __mmask8 value) { - os << static_cast(value); - return os; -} "#; pub const PLATFORM_RUST_CFGS: &str = r#" -#![cfg_attr(target_arch = "x86", feature(avx))] -#![cfg_attr(target_arch = "x86", feature(sse))] -#![cfg_attr(target_arch = "x86", feature(sse2))] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_bf16))] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_f16))] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))] -#![cfg_attr(target_arch = "x86_64", feature(x86_amx_intrinsics))] -#![cfg_attr(target_arch = "x86_64", feature(stdarch_x86_avx512_f16))] -#![feature(fmt_helpers_for_derive)] +#![feature(stdarch_x86_avx512_bf16)] +#![feature(stdarch_x86_avx512_f16)] +#![feature(stdarch_x86_rtm)] +#![feature(x86_amx_intrinsics)] "#; diff --git a/stdarch/crates/intrinsic-test/src/x86/constraint.rs b/stdarch/crates/intrinsic-test/src/x86/constraint.rs index 72f5da3b3faf3..608ffdd1eed96 100644 --- a/stdarch/crates/intrinsic-test/src/x86/constraint.rs +++ b/stdarch/crates/intrinsic-test/src/x86/constraint.rs @@ -1,7 +1,10 @@ use crate::common::constraint::Constraint; -pub fn map_constraints(imm_type: &String, imm_width: u32) -> Option { +pub fn map_constraints(fn_name: &str, imm_type: &String, imm_width: u32) -> Option { if imm_width > 0 { + if fn_name == "_mm_sm3rnds2_epi32" { + return Some(Constraint::Set((0..64).step_by(2).collect())); + } let max: i64 = 2i64.pow(imm_width); return Some(Constraint::Range(0..max)); } diff --git a/stdarch/crates/intrinsic-test/src/x86/mod.rs b/stdarch/crates/intrinsic-test/src/x86/mod.rs index f2baf070714c1..288bd8bdf8961 100644 --- a/stdarch/crates/intrinsic-test/src/x86/mod.rs +++ b/stdarch/crates/intrinsic-test/src/x86/mod.rs @@ -1,4 +1,3 @@ -mod compile; mod config; mod constraint; mod intrinsic; @@ -7,7 +6,6 @@ mod xml_parser; use crate::common::SupportedArchitectureTest; use crate::common::cli::ProcessedCli; -use crate::common::compile_c::CppCompilation; use crate::common::intrinsic::Intrinsic; use crate::common::intrinsic_helpers::TypeKind; use intrinsic::X86IntrinsicType; @@ -15,34 +13,63 @@ use xml_parser::get_xml_intrinsics; pub struct X86ArchitectureTest { intrinsics: Vec>, - cli_options: ProcessedCli, } impl SupportedArchitectureTest for X86ArchitectureTest { type IntrinsicImpl = X86IntrinsicType; - fn cli_options(&self) -> &ProcessedCli { - &self.cli_options - } - fn intrinsics(&self) -> &[Intrinsic] { &self.intrinsics } - fn cpp_compilation(&self) -> Option { - compile::build_cpp_compilation(&self.cli_options) - } - const NOTICE: &str = config::NOTICE; - const PLATFORM_C_HEADERS: &[&str] = &["immintrin.h", "cstddef", "cstdint"]; - const PLATFORM_C_DEFINITIONS: &str = config::PLATFORM_C_DEFINITIONS; - const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::PLATFORM_C_FORWARD_DECLARATIONS; + const PLATFORM_C_HEADERS: &[&str] = &["immintrin.h"]; const PLATFORM_RUST_DEFINITIONS: &str = config::PLATFORM_RUST_DEFINITIONS; const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS; - fn create(cli_options: ProcessedCli) -> Self { + fn arch_flags(&self, _cli_options: &ProcessedCli) -> Vec<&str> { + vec![ + "-maes", + "-mf16c", + "-mfma", + "-mavx", + "-mavx2", + "-mavx512f", + "-msse2", + "-mavx512vl", + "-mavx512bw", + "-mavx512dq", + "-mavx512cd", + "-mavx512fp16", + "-msha", + "-msha512", + "-msm3", + "-msm4", + "-mavxvnni", + "-mavxvnniint8", + "-mavxneconvert", + "-mavxifma", + "-mavxvnniint16", + "-mavx512bf16", + "-mavx512bitalg", + "-mavx512ifma", + "-mavx512vbmi", + "-mavx512vbmi2", + "-mavx512vnni", + "-mavx512vpopcntdq", + "-mavx512vp2intersect", + "-mbmi", + "-mbmi2", + "-mgfni", + "-mvaes", + "-mvpclmulqdq", + "-mlzcnt", + ] + } + + fn create(cli_options: &ProcessedCli) -> Self { let mut intrinsics = get_xml_intrinsics(&cli_options.filename).expect("Error parsing input file"); @@ -67,9 +94,6 @@ impl SupportedArchitectureTest for X86ArchitectureTest { .take(sample_size) .collect::>(); - Self { - intrinsics: intrinsics, - cli_options: cli_options, - } + Self { intrinsics } } } diff --git a/stdarch/crates/intrinsic-test/src/x86/types.rs b/stdarch/crates/intrinsic-test/src/x86/types.rs index 2391ee9c2df49..a0e14c77d6b5e 100644 --- a/stdarch/crates/intrinsic-test/src/x86/types.rs +++ b/stdarch/crates/intrinsic-test/src/x86/types.rs @@ -1,12 +1,11 @@ use std::str::FromStr; use itertools::Itertools; -use regex::Regex; use super::intrinsic::X86IntrinsicType; -use crate::common::cli::Language; -use crate::common::indentation::Indentation; -use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind}; +use crate::common::intrinsic_helpers::{ + IntrinsicType, IntrinsicTypeDefinition, Sign, SimdLen, TypeKind, +}; use crate::x86::xml_parser::Parameter; impl IntrinsicTypeDefinition for X86IntrinsicType { @@ -26,82 +25,32 @@ impl IntrinsicTypeDefinition for X86IntrinsicType { .replace("const ", "") } - fn c_single_vector_type(&self) -> String { - // matches __m128, __m256 and similar types - let re = Regex::new(r"__m\d+").unwrap(); - if re.is_match(self.param.type_data.as_str()) { - self.param.type_data.clone() - } else { - unreachable!("Shouldn't be called on this type") + fn rust_type(&self) -> String { + let type_data = &*self.param.type_data; + if type_data.starts_with("__m") { + return type_data.to_owned(); + } + match &*type_data.replace("const ", "") { + "_Float16" => "f16", + "__bfloat16" => "bf16", + "float" => "f32", + "double" => "f64", + "__int8" | "char" => "i8", + "unsigned char" => "u8", + "__int16" | "short" => "i16", + "unsigned short" => "u16", + "__int32" | "int" => "i32", + "unsigned __int32" | "unsigned int" | "unsigned long" => "u32", + "__int64" | "long long" => "i64", + "unsigned __int64" => "u64", + "size_t" => "usize", + _ => todo!("unknown type {type_data}"), } + .to_string() } - // fn rust_type(&self) -> String { - // // handling edge cases first - // // the general handling is implemented below - // if let Some(val) = self.metadata.get("type") { - // match val.as_str() { - // "__m128 const *" => { - // return "&__m128".to_string(); - // } - // "__m128d const *" => { - // return "&__m128d".to_string(); - // } - // "const void*" => { - // return "&__m128d".to_string(); - // } - // _ => {} - // } - // } - - // if self.kind() == TypeKind::Void && self.ptr { - // // this has been handled by default settings in - // // the from_param function of X86IntrinsicType - // unreachable!() - // } - - // // general handling cases - // let core_part = if self.kind() == TypeKind::Mask { - // // all types of __mmask are handled here - // format!("__mask{}", self.bit_len.unwrap()) - // } else if self.simd_len.is_some() { - // // all types of __m vector types are handled here - // let re = Regex::new(r"\__m\d+[a-z]*").unwrap(); - // let rust_type = self - // .metadata - // .get("type") - // .map(|val| re.find(val).unwrap().as_str()); - // rust_type.unwrap().to_string() - // } else { - // format!( - // "{}{}", - // self.kind.rust_prefix().to_string(), - // self.bit_len.unwrap() - // ) - // }; - - // // extracting "memsize" so that even vector types can be involved - // let memwidth = self - // .metadata - // .get("memwidth") - // .map(|n| str::parse::(n).unwrap()); - // let prefix_part = if self.ptr && self.constant && self.bit_len.eq(&memwidth) { - // "&" - // } else if self.ptr && self.bit_len.eq(&memwidth) { - // "&mut " - // } else if self.ptr && self.constant { - // "*const " - // } else if self.ptr { - // "*mut " - // } else { - // "" - // }; - - // return prefix_part.to_string() + core_part.as_str(); - // } - /// Determines the load function for this type. - fn get_load_function(&self, _language: Language) -> String { + fn get_load_function(&self) -> String { let type_value = self.param.type_data.clone(); if type_value.len() == 0 { unimplemented!("the value for key 'type' is not present!"); @@ -168,112 +117,16 @@ impl IntrinsicTypeDefinition for X86IntrinsicType { } } - /// Generates a std::cout for the intrinsics results that will match the - /// rust debug output format for the return type. The generated line assumes - /// there is an int i in scope which is the current pass number. - fn print_result_c(&self, indentation: Indentation, additional: &str) -> String { - let lanes = if self.num_lanes() > 1 { - (0..self.num_lanes()) - .map(|idx| -> std::string::String { - let cast_type = self.c_promotion(); - let lane_fn = self.get_lane_function(); - if cast_type.len() > 2 { - format!("cast<{cast_type}>({lane_fn}(__return_value, {idx}))") - } else { - format!("{lane_fn}(__return_value, {idx})") - } - }) - .collect::>() - .join(r#" << ", " << "#) - } else { + fn rust_scalar_type(&self) -> String { + if self.is_simd() { format!( - "{promote}cast<{cast}>(__return_value)", - cast = match self.kind() { - TypeKind::Void => "void".to_string(), - TypeKind::Float if self.inner_size() == 64 => "double".to_string(), - TypeKind::Float if self.inner_size() == 32 => "float".to_string(), - TypeKind::Mask => format!( - "__mmask{}", - self.bit_len.expect(format!("self: {self:#?}").as_str()) - ), - TypeKind::Vector => format!( - "__m{}i", - self.bit_len.expect(format!("self: {self:#?}").as_str()) - ), - _ => self.c_scalar_type(), - }, - promote = self.generate_final_type_cast(), + "{prefix}{bits}", + prefix = self.kind().rust_prefix(), + bits = self.inner_size() ) - }; - - format!( - r#"{indentation}std::cout << "Result {additional}-" << i+1 << ": {ty}" << std::fixed << std::setprecision(150) << {lanes} << "{close}" << std::endl;"#, - ty = if self.is_simd() { - format!("{}(", self.c_type()) - } else { - String::from("") - }, - close = if self.is_simd() { ")" } else { "" }, - ) - } - - /// Determines the get lane function for this type. - fn get_lane_function(&self) -> String { - let total_vector_bits: Option = self - .simd_len - .zip(self.bit_len) - .and_then(|(simd_len, bit_len)| Some(simd_len * bit_len)); - - match (self.bit_len, total_vector_bits) { - (Some(8), Some(128)) => String::from("(uint8_t)_mm_extract_epi8"), - (Some(16), Some(128)) => String::from("(uint16_t)_mm_extract_epi16"), - (Some(32), Some(128)) => String::from("(uint32_t)_mm_extract_epi32"), - (Some(64), Some(128)) => String::from("(uint64_t)_mm_extract_epi64"), - (Some(8), Some(256)) => String::from("(uint8_t)_mm256_extract_epi8"), - (Some(16), Some(256)) => String::from("(uint16_t)_mm256_extract_epi16"), - (Some(32), Some(256)) => String::from("(uint32_t)_mm256_extract_epi32"), - (Some(64), Some(256)) => String::from("(uint64_t)_mm256_extract_epi64"), - (Some(8), Some(512)) => String::from("(uint8_t)_mm512_extract_intrinsic_test_epi8"), - (Some(16), Some(512)) => String::from("(uint16_t)_mm512_extract_intrinsic_test_epi16"), - (Some(32), Some(512)) => String::from("(uint32_t)_mm512_extract_intrinsic_test_epi32"), - (Some(64), Some(512)) => String::from("(uint64_t)_mm512_extract_intrinsic_test_epi64"), - _ => unreachable!( - "invalid length for vector argument: {:?}, {:?}", - self.bit_len, self.simd_len - ), - } - } - - fn rust_scalar_type(&self) -> String { - let prefix = match self.data.kind { - TypeKind::Mask => String::from("__mmask"), - TypeKind::Vector => String::from("i"), - _ => self.kind().rust_prefix().to_string(), - }; - - let bits = if self.inner_size() >= 128 { - 32 } else { - self.inner_size() - }; - format!("{prefix}{bits}") - } - - fn print_result_rust(&self) -> String { - let return_value = match self.kind() { - // `_mm{256}_cvtps_ph` has return type __m128i but contains f16 values - TypeKind::Float if self.param.type_data == "__m128i" => { - "format_args!(\"{:.150?}\", debug_as::<_, f16>(__return_value))".to_string() - } - TypeKind::Int(_) - if ["__m128i", "__m256i", "__m512i"].contains(&self.param.type_data.as_str()) => - { - format!("debug_as::<_, u{}>(__return_value)", self.inner_size()) - } - _ => "format_args!(\"{__return_value:.150?}\")".to_string(), - }; - - return_value + self.rust_type().replace("__mmask", "u") + } } } @@ -336,7 +189,7 @@ impl X86IntrinsicType { Ok(num_bits) => self .data .bit_len - .and_then(|bit_len| Some(num_bits / bit_len)), + .and_then(|bit_len| Some(SimdLen::Fixed(num_bits / bit_len))), Err(_) => None, }; } @@ -446,7 +299,7 @@ impl X86IntrinsicType { // - _mm512_conj_pch if param.type_data == "__m512h" && param.etype == "FP32" { data.bit_len = Some(16); - data.simd_len = Some(32); + data.simd_len = Some(SimdLen::Fixed(32)); } let mut result = X86IntrinsicType { diff --git a/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs b/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs index 681b1a3c52743..6006d7919f875 100644 --- a/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs +++ b/stdarch/crates/intrinsic-test/src/x86/xml_parser.rs @@ -99,7 +99,7 @@ fn xml_to_intrinsic( } else { param.imm_width }; - let constraint = map_constraints(¶m.imm_type, effective_imm_width); + let constraint = map_constraints(&name, ¶m.imm_type, effective_imm_width); let arg = Argument::::new( i, param.var_name.clone(), diff --git a/stdarch/crates/simd-test-macro/src/lib.rs b/stdarch/crates/simd-test-macro/src/lib.rs index 92bb40946e1ff..9219540a1065f 100644 --- a/stdarch/crates/simd-test-macro/src/lib.rs +++ b/stdarch/crates/simd-test-macro/src/lib.rs @@ -71,6 +71,7 @@ pub fn simd_test( "powerpc64" | "powerpc64le" => "is_powerpc64_feature_detected", "loongarch32" | "loongarch64" => "is_loongarch_feature_detected", "s390x" => "is_s390x_feature_detected", + "mips64" | "mips64el" => "is_mips64_feature_detected", t => panic!("unknown target: {t}"), }; let macro_test = Ident::new(macro_test, Span::call_site()); diff --git a/stdarch/crates/stdarch-gen-arm/README.md b/stdarch/crates/stdarch-gen-arm/README.md index 4da14bcbb6c9b..970721681c04a 100644 --- a/stdarch/crates/stdarch-gen-arm/README.md +++ b/stdarch/crates/stdarch-gen-arm/README.md @@ -1,11 +1,11 @@ # stdarch-gen-arm generator guide ## Running the generator -- Run: `cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec` -``` -$ cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec - Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.18s - Running `target/debug/stdarch-gen-arm crates/stdarch-gen-arm/spec` -``` + +Run: `cargo +nightly run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec crates/core_arch/src` + +NOTE: If you are running this from rust-lang/rust, you must be in the `library/stdarch` +working directory. + ## Input/Output ### Input files (intrinsic YAML definitions) - `crates/stdarch-gen-arm/spec//*.spec.yml` @@ -205,9 +205,6 @@ MatchKind: - `Array` - An array of expressions - Usage: `Array: [, ...]` -- `SvUndef` - - Returns the LLVM `undef` symbol - - Usage: `SvUndef` - `Multiply` - Simply `*` - Usage: `Multiply: [, ]` diff --git a/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index e88860717b6df..03fea5e0a4af3 100644 --- a/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -78,14 +78,22 @@ cfg-target-has-atomic-64: &cfg-target-has-atomic-64 neon-unstable-fp8: &neon-unstable-fp8 FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']] +# all(test, target_endian = "little") +all-test-little-endian: &all-test-little-endian + FnCall: [all, [test, 'target_endian = "little"']] + # #[cfg(target_endian = "little")] -little-endian: &little-endian +cfg-little-endian: &cfg-little-endian FnCall: [cfg, ['target_endian = "little"']] # #[cfg(target_endian = "big")] -big-endian: &big-endian +cfg-big-endian: &cfg-big-endian FnCall: [cfg, ['target_endian = "big"']] +# all(test, not(target_env = "msvc"), target_endian = "big") +cfg-test-not-msvc-little-endian: &cfg-test-not-msvc-little-endian + FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}, 'target_endian = "little"']] + intrinsics: - name: "vaddd_{type}" doc: Add @@ -174,12 +182,12 @@ intrinsics: - ['d_f64', 'f64'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vabd_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - 0 + - - 0 - name: "vabd{type[0]}" doc: "Floating-point absolute difference" @@ -195,125 +203,28 @@ intrinsics: - ['h_f16', 'f16'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vabd_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - 0 - - - name: "vabdl_high{neon_type[0].noq}" - doc: Signed Absolute difference Long - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [sabdl2] - safety: safe - types: - - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t] - compose: - - Let: - - c - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - a - - a - - [8, 9, 10, 11, 12, 13, 14, 15] - - Let: - - d - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - b - - b - - [8, 9, 10, 11, 12, 13, 14, 15] - - Let: - - e - - "{neon_type[3]}" - - FnCall: - - simd_cast - - - FnCall: - - "vabd_{neon_type[0]}" - - - c - - d - - FnCall: - - simd_cast - - - e + - - 0 - name: "vabdl_high{neon_type[0].noq}" doc: Signed Absolute difference Long arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: - - stable - - - 'feature = "neon_intrinsics"' - - 'since = "1.59.0"' - assert_instr: [sabdl2] + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]] safety: safe types: + - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t] - [int16x8_t, int32x4_t, int16x4_t, uint16x4_t] - compose: - - Let: - - c - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - a - - a - - [4, 5, 6, 7] - - Let: - - d - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - b - - b - - [4, 5, 6, 7] - - Let: - - e - - "{neon_type[3]}" - - FnCall: - - simd_cast - - - FnCall: - - "vabd_{neon_type[0]}" - - - c - - d - - FnCall: - - simd_cast - - - e - - - name: "vabdl_high{neon_type[0].noq}" - doc: Signed Absolute difference Long - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[1]}" - attr: - - FnCall: - - stable - - - 'feature = "neon_intrinsics"' - - 'since = "1.59.0"' - assert_instr: [sabdl2] - safety: safe - types: - [int32x4_t, int64x2_t, int32x2_t, uint32x2_t] compose: - - Let: - - c - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - a - - a - - [2, 3] - - Let: - - d - - "{neon_type[2]}" - - FnCall: - - simd_shuffle! - - - b - - b - - [2, 3] + - Let: [c, FnCall: ['vget_high_{neon_type[0]}', [a]]] + - Let: [d, FnCall: ['vget_high_{neon_type[0]}', [b]]] - Let: - e - "{neon_type[3]}" @@ -333,7 +244,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint64x1_t, uint64x1_t] @@ -351,7 +262,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -365,19 +276,19 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vceq_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - 0 - name: "vceq{type[0]}" @@ -394,12 +305,12 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vceq_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - 0 - name: "vceqd_{type[0]}" doc: "Compare bitwise equal" @@ -407,7 +318,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64", "s64"] @@ -426,7 +337,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] @@ -444,7 +355,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tst]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64", "s64"] @@ -463,7 +374,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_s32", "i32", "u32"] @@ -481,19 +392,19 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["b_s8", "i8", "u8", "s8"] - ["h_s16", "i16", "u16", "s16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[3]}' - - FnCall: - "vuqadd_{type[3]}" - - FnCall: ["vdup_n_{type[3]}", [a]] - FnCall: ["vdup_n_{type[2]}", [b]] - - '0' + - - '0' - name: "vabs{neon_type.no}" doc: "Floating-point absolute value" @@ -501,7 +412,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fabs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -515,7 +426,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t] @@ -529,7 +440,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - uint64x1_t @@ -543,7 +454,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -557,19 +468,19 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - "vcgt_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcgt{type[0]}" @@ -586,12 +497,12 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - "vcgt_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vclt{neon_type[0].no}" doc: "Compare signed less than" @@ -599,7 +510,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t] @@ -613,7 +524,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t] @@ -627,7 +538,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -641,19 +552,19 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcle_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcle{type[0]}" @@ -670,12 +581,12 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcle_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcge{neon_type[0].no}" doc: "Compare signed greater than or equal" @@ -683,7 +594,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, uint64x1_t] @@ -697,7 +608,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -718,7 +629,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64"] @@ -735,7 +646,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmle]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -759,7 +670,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmle]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] @@ -779,18 +690,18 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vclez_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vclez{type[0]}" doc: "Floating-point compare less than or equal to zero" @@ -806,11 +717,11 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vclez_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcltz{neon_type[0].no}" doc: "Compare signed less than zero" @@ -818,7 +729,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmlt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -842,7 +753,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmlt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] @@ -862,18 +773,18 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcltz_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcltz{type[0]}" doc: "Floating-point compare less than zero" @@ -889,11 +800,11 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcltz_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcltzd_s64" doc: "Compare less than zero" @@ -901,7 +812,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [asr]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64"] @@ -918,7 +829,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -936,7 +847,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32", i32] @@ -975,7 +886,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -993,7 +904,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32", i32] @@ -1033,7 +944,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -1047,7 +958,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] @@ -1076,7 +987,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -1090,7 +1001,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] @@ -1119,7 +1030,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int64x1_t, float64x1_t] @@ -1133,7 +1044,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "i32", "f32", s32] @@ -1147,7 +1058,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint64x1_t, float64x1_t] @@ -1161,7 +1072,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u32", "f32", "s_f32"] @@ -1176,7 +1087,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1314,7 +1225,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1340,7 +1251,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1365,7 +1276,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1389,7 +1300,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", "s_s32_f32", "32"] @@ -1403,7 +1314,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", "s_u32_f32"] @@ -1488,7 +1399,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, float64x2_t] @@ -1500,28 +1411,20 @@ intrinsics: arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtl2]]}]] + - *neon-stable safety: safe types: - [float32x4_t, float64x2_t] compose: - - Let: - - b - - float32x2_t - - FnCall: - - simd_shuffle! - - - a - - a - - '[2, 3]' - - FnCall: [simd_cast, [b]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]] - name: "vcvt_high_f16_f32" doc: "Floating-point convert to lower precision" arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn2]]}]] - *neon-stable-fp16 - *target-not-arm64ec safety: safe @@ -1538,7 +1441,7 @@ intrinsics: arguments: ["a: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtl2]]}]] - *neon-stable-fp16 - *target-not-arm64ec safety: safe @@ -1555,8 +1458,8 @@ intrinsics: arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn]]}]] + - *neon-stable safety: safe types: - [float64x2_t, float32x2_t] @@ -1568,25 +1471,24 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn2]]}]] + - *neon-stable safety: safe types: - [float32x2_t, float64x2_t, float32x4_t] compose: - FnCall: - - simd_shuffle! + - vcombine_f32 - - a - - FnCall: [simd_cast, [b]] - - '[0, 1, 2, 3]' + - FnCall: [vcvt_f32_f64, [b]] - name: "vcvtx_f32_f64" doc: "Floating-point convert to lower precision narrow, rounding to odd" arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtxn]]}]] + - *neon-stable safety: safe types: - [float64x2_t, float32x2_t] @@ -1603,34 +1505,33 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f64", "f32"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - vcvtx_f32_f64 - - FnCall: [vdupq_n_f64, [a]] - - '0' + - - '0' - name: "vcvtx_high_f32_f64" doc: "Floating-point convert to lower precision narrow, rounding to odd" arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtxn2]]}]] + - *neon-stable safety: safe types: - [float32x2_t, float64x2_t, float32x4_t] compose: - FnCall: - - simd_shuffle! + - vcombine_f32 - - a - FnCall: [vcvtx_f32_f64, [b]] - - '[0, 1, 2, 3]' - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1639,7 +1540,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1662,7 +1563,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1756,7 +1657,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1779,7 +1680,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -1801,7 +1702,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, int32x2_t, _s32_f32] @@ -1842,7 +1743,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", 's_s32_f32'] @@ -1866,9 +1767,9 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "u16", 'h_u16_f16'] - ["f16", "u32", 'h_u32_f16'] - ["f16", "u64", 'h_u64_f16'] - compose: - LLVMLink: name: "vcvta{type[2]}" @@ -1888,6 +1789,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "i16", 'h_s16_f16'] - ["f16", "i32", 'h_s32_f16'] - ["f16", "i64", 'h_s64_f16'] compose: @@ -1898,44 +1800,13 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtas.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - - name: "vcvta{type[2]}" - doc: "Floating-point convert to integer, rounding to nearest with ties to away" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "i16", 'h_s16_f16', 's32'] - compose: - - 'vcvtah_{type[3]}_f16(a) as i16' - - name: "vcvta{type[2]}" doc: "Floating-point convert to integer, rounding to nearest with ties to away" arguments: ["a: {type[0]}"] return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "u16", 'h_u16_f16', 'u32'] - compose: - - 'vcvtah_{type[3]}_f16(a) as u16' - - - name: "vcvta{type[2]}" - doc: "Floating-point convert to integer, rounding to nearest with ties to away" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", 's_u32_f32'] @@ -1953,7 +1824,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, int32x2_t] @@ -1973,7 +1844,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", 's_s32_f32'] @@ -2038,6 +1909,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "i16", 'h'] - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] compose: @@ -2048,22 +1920,6 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtns.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtn{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to integer, rounding to nearest with ties to even" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "i16", 'h', 'i32'] - compose: - - 'vcvtnh_{type[3]}_f16(a) as i16' - - - name: "vcvtn{type[2]}_{type[1]}_{type[0]}" doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to even" arguments: ["a: {type[0]}"] @@ -2075,6 +1931,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "u16", 'h'] - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] compose: @@ -2085,28 +1942,13 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtnu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtn{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to even" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "u16", 'h', 'u32'] - compose: - - 'vcvtnh_{type[3]}_f16(a) as u16' - - name: "vcvtm{neon_type[1].no}_{neon_type[0]}" doc: "Floating-point convert to signed integer, rounding toward minus infinity" arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, int32x2_t] @@ -2169,7 +2011,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", 's_s32_f32'] @@ -2187,7 +2029,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, int32x2_t] @@ -2207,7 +2049,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "i32", 's_s32_f32'] @@ -2225,7 +2067,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t] @@ -2245,7 +2087,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", 's_u32_f32'] @@ -2263,7 +2105,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t] @@ -2283,7 +2125,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", s_u32_f32] @@ -2301,7 +2143,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t] @@ -2321,7 +2163,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", s_u32_f32, 'i32'] @@ -2390,6 +2232,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "i16", 'h'] - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] compose: @@ -2400,21 +2243,6 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtps.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtp{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to integer, rounding to plus infinity" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "i16", 'h', 'i32'] - compose: - - 'vcvtph_{type[3]}_f16(a) as i16' - - name: "vcvtp{type[2]}_{type[1]}_{type[0]}" doc: "Floating-point convert to unsigned integer, rounding to plus infinity" arguments: ["a: {type[0]}"] @@ -2426,6 +2254,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "u16", 'h'] - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] compose: @@ -2436,21 +2265,6 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtpu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtp{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to unsigned integer, rounding to plus infinity" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "u16", 'h', 'u32'] - compose: - - 'vcvtph_{type[3]}_f16(a) as u16' - - name: "vdup{neon_type.laneq_nox}" doc: "Set all vector lanes to the same value" arguments: ["a: {neon_type}"] @@ -2458,8 +2272,9 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [dup, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] + big_endian_inverse: true safety: safe types: - poly64x2_t @@ -2475,8 +2290,9 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [dup, 'N = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] + big_endian_inverse: true safety: safe types: - [poly64x1_t, poly64x2_t] @@ -2492,7 +2308,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2509,7 +2325,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2518,7 +2334,7 @@ intrinsics: - [float64x1_t, "f64"] compose: - FnCall: [static_assert!, ['N == 0']] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup_laneq_{neon_type[0]}" doc: "Set all vector lanes to the same value" @@ -2527,7 +2343,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2536,8 +2352,8 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, 1]] - FnCall: - - "transmute::<{type[2]}, _>" - - - FnCall: [simd_extract!, [a, 'N as u32']] + - transmute + - - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" doc: "Set all vector lanes to the same value" @@ -2546,7 +2362,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2558,7 +2374,7 @@ intrinsics: - [float64x2_t, "f64", d_laneq_f64] compose: - FnCall: [static_assert_uimm_bits!, [N, 1]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" doc: "Set all vector lanes to the same value" @@ -2567,7 +2383,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 4']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2579,7 +2395,7 @@ intrinsics: - [poly16x8_t, "p16", h_laneq_p16] compose: - FnCall: [static_assert_uimm_bits!, [N, 3]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" @@ -2598,7 +2414,7 @@ intrinsics: - [float16x4_t, "f16", h_lane_f16] compose: - FnCall: [static_assert_uimm_bits!, [N, 2]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" @@ -2617,7 +2433,7 @@ intrinsics: - [float16x8_t, "f16", h_laneq_f16] compose: - FnCall: [static_assert_uimm_bits!, [N, 4]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" @@ -2627,7 +2443,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 8']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2636,7 +2452,7 @@ intrinsics: - [poly8x16_t, "p8", b_laneq_p8] compose: - FnCall: [static_assert_uimm_bits!, [N, 4]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - name: "vdup{type[2]}" doc: "Set all vector lanes to the same value" @@ -2645,7 +2461,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -2657,24 +2473,25 @@ intrinsics: - [float32x4_t, "f32", s_laneq_f32] compose: - FnCall: [static_assert_uimm_bits!, [N, 2]] - - FnCall: [simd_extract!, [a, 'N as u32']] + - FnCall: ['vget{neon_type[0].lane_nox}', [a], [N]] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ext, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] + big_endian_inverse: true safety: safe types: - - [poly64x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] - - [float64x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - poly64x2_t + - float64x2_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']] - name: "vmla{neon_type.no}" doc: "Floating-point multiply-add to accumulator" @@ -2682,7 +2499,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -2695,16 +2512,16 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2]]}]] + - *neon-stable safety: safe types: - - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]'] - - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]', '[2, 3]'] + - [int16x8_t, int8x16_t, int8x8_t] + - [int32x4_t, int16x8_t, int16x4_t] + - [int64x2_t, int32x4_t, int32x2_t] compose: - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] - - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}] + - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}] - FnCall: ["vmlal_{neon_type[2]}", [a, b, c]] - name: "vmlal_high_{neon_type[1]}" @@ -2712,22 +2529,16 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2]]}]] + - *neon-stable safety: safe types: - - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + - [uint16x8_t, uint8x16_t, uint8x8_t] + - [uint32x4_t, uint16x8_t, uint16x4_t] + - [uint64x2_t, uint32x4_t, uint32x2_t] compose: - - Let: - - b - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] - - Let: - - c - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}] + - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}] - FnCall: ["vmlal_{neon_type[1]}", [a, b, c]] - name: "vmlsl_high_{neon_type[1]}" @@ -2735,22 +2546,16 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2]]}]] + - *neon-stable safety: safe types: - - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]'] - - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]'] + - [int16x8_t, int8x16_t, int8x8_t] + - [int32x4_t, int16x8_t, int16x4_t] + - [int64x2_t, int32x4_t, int32x2_t] compose: - - Let: - - b - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] - - Let: - - c - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}] + - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}] - FnCall: ["vmlsl_{neon_type[1]}", [a, b, c]] - name: "vmlsl_high_{neon_type[1]}" @@ -2758,44 +2563,38 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2]]}]] + - *neon-stable safety: safe types: - - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + - [uint16x8_t, uint8x16_t, uint8x8_t] + - [uint32x4_t, uint16x8_t, uint16x4_t] + - [uint64x2_t, uint32x4_t, uint32x2_t] compose: - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] - - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[1]}', [b]]}] + - Let: [c, {FnCall: ['vget_high_{neon_type[1]}', [c]]}] - FnCall: ["vmlsl_{neon_type[1]}", [a, b, c]] - name: "vmovn_high{neon_type[1].noq}" doc: Extract narrow arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" - attr: [*neon-stable] - assert_instr: [xtn2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [xtn2]]}]] safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int32x4_t] + - [uint8x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint32x4_t] compose: - - Let: - - c - - "{neon_type[0]}" - - FnCall: - - simd_cast - - - b - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - - c - - "{type[3]}" + - FnCall: ['simd_cast', [b]] - name: "vneg{neon_type.no}" doc: Negate @@ -2873,11 +2672,11 @@ intrinsics: - [i64, 'd_s64', 's64'] compose: - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - 'vqneg_{type[2]}' - - FnCall: ['vdup_n_{type[2]}', [a]] - - 0 + - - 0 - name: "vqneg{neon_type[0].no}" doc: Signed saturating negate @@ -2954,12 +2753,12 @@ intrinsics: - "vdup_n_{type[2]}" - - b - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - "vqsub_{type[2]}" - - a - b - - "0" + - - "0" - name: "vqsub{type[3]}" doc: Saturating subtract @@ -2985,12 +2784,12 @@ intrinsics: - "vdup_n_{type[2]}" - - b - FnCall: - - 'simd_extract!' + - 'vget_lane_{type[2]}' - - FnCall: - "vqsub_{type[2]}" - - a - b - - "0" + - - "0" - name: "vrbit{neon_type.no}" doc: Reverse bit order @@ -3439,12 +3238,12 @@ intrinsics: - "vdup_n_{type[0]}" - - b - FnCall: - - simd_extract! + - 'vget_lane_{type[0]}' - - FnCall: - "vqadd_{type[0]}" - - a - b - - "0" + - - "0" - name: "vqadd{type[2]}" doc: Saturating add @@ -3470,12 +3269,12 @@ intrinsics: - "vdup_n_{type[0]}" - - b - FnCall: - - simd_extract! + - 'vget_lane_{type[0]}' - - FnCall: - "vqadd_{type[0]}" - - a - b - - "0" + - - "0" - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -3712,7 +3511,6 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [ld2] - big_endian_inverse: false safety: unsafe: [neon] types: @@ -3822,7 +3620,7 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x16x3_t, int8x16_t, i8, '3'] + - ['*const i8', int8x16x3_t, int8x16_t, i8, '4'] - ['*const i64', int64x2x3_t, int64x2_t, i64, '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] @@ -4031,17 +3829,10 @@ intrinsics: unsafe: [neon] assert_instr: [ld3] types: - - ['*const i64', int64x2x3_t, '*const int64x2_t', i64] - - ['*const f64', float64x2x3_t, '*const float64x2_t', f64] + - ['*const i64', int64x2x3_t, i64, "2"] + - ['*const f64', float64x2x3_t, f64, "2"] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -4066,7 +3857,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: [*neon-stable] - big_endian_inverse: false safety: unsafe: [neon] assert_instr: [ld3] @@ -4174,17 +3964,11 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const f64', float64x2x4_t, f64, '*const float64x2_t'] - - ['*const i64', int64x2x4_t, i64, '*const int64x2_t'] + - ['*const f64', float64x2x4_t, f64, "2"] + - ['*const i64', int64x2x4_t, i64, "2"] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] + - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers @@ -4211,7 +3995,6 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [ld4] - big_endian_inverse: false safety: unsafe: [neon] types: @@ -4259,7 +4042,7 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x16x4_t, int8x16_t, i8, '3'] + - ['*const i8', int8x16x4_t, int8x16_t, i8, '4'] - ['*const i64', int64x2x4_t, int64x2_t, i64, '1'] - ['*const f64', float64x2x4_t, float64x2_t, f64, '1'] compose: @@ -4319,7 +4102,6 @@ intrinsics: - *neon-stable static_defs: - "const LANE: i32" - big_endian_inverse: false safety: unsafe: [neon] types: @@ -4369,7 +4151,6 @@ intrinsics: - *neon-stable static_defs: - "const LANE: i32" - big_endian_inverse: false safety: unsafe: [neon] types: @@ -4472,7 +4253,9 @@ intrinsics: doc: "Store-Release a single-element structure from one lane of one register." arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] static_defs: ["const LANE: i32"] - safety: safe + safety: + unsafe: + - pointer_write: ptr attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] @@ -4491,7 +4274,7 @@ intrinsics: - Let: - "lane" - i64 - - FnCall: [simd_extract!, [val, 'LANE as u32']] + - FnCall: ['vget{neon_type[1].lane_nox}', [val], [LANE]] - MethodCall: - "(*atomic_dst)" - store @@ -4501,7 +4284,9 @@ intrinsics: doc: "Store-Release a single-element structure from one lane of one register." arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] static_defs: ["const LANE: i32"] - safety: safe + safety: + unsafe: + - pointer_write: ptr attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] @@ -5161,45 +4946,35 @@ intrinsics: - name: "vmull_high{neon_type[0].noq}" doc: Signed multiply long arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[3]}" - attr: [*neon-stable] - assert_instr: [smull2] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]] safety: safe types: - - [int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int16x8_t] - - [int16x8_t, int16x4_t, '[4, 5, 6, 7]', int32x4_t] - - [int32x4_t, int32x2_t, '[2, 3]', int64x2_t] + - [int8x16_t, int16x8_t] + - [int16x8_t, int32x4_t] + - [int32x4_t, int64x2_t] compose: - - Let: - - a - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - b - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}] - FnCall: ["vmull_{neon_type[0]}", [a, b]] - name: "vmull_high{neon_type[0].noq}" doc: "Unsigned multiply long" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[3]}" - attr: [*neon-stable] - assert_instr: [umull2] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]] safety: safe types: - - [uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint16x8_t] - - [uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', uint32x4_t] - - [uint32x4_t, uint32x2_t, '[2, 3]', uint64x2_t] + - [uint8x16_t, uint16x8_t] + - [uint16x8_t, uint32x4_t] + - [uint32x4_t, uint64x2_t] compose: - - Let: - - a - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - b - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}] - FnCall: ["vmull_{neon_type[0]}", [a, b]] - name: "vmull_p64" @@ -5225,22 +5000,16 @@ intrinsics: - name: "vmull_high{neon_type[0].noq}" doc: "Polynomial multiply long" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[3]}" + return_type: "{neon_type[1]}" attr: - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]] safety: safe - assert_instr: [pmull2] types: - - [poly8x16_t, poly8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', poly16x8_t] + - [poly8x16_t, poly16x8_t] compose: - - Let: - - a - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - b - - "{neon_type[1]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}] - FnCall: ["vmull_{neon_type[0]}", [a, b]] - name: "vmull_high{neon_type[0].noq}" @@ -5250,15 +5019,15 @@ intrinsics: attr: - *neon-aes - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]] safety: safe - assert_instr: [pmull2] types: - [poly64x2_t, "p128"] compose: - FnCall: - "vmull_{neon_type[0]}" - - - FnCall: [simd_extract!, [a, '1']] - - FnCall: [simd_extract!, [b, '1']] + - - FnCall: ['vget{neon_type[0].lane_nox}', [a], [1]] + - FnCall: ['vget{neon_type[0].lane_nox}', [b], [1]] - name: "vmulx{neon_type.no}" doc: Floating-point multiply extended @@ -5357,11 +5126,8 @@ intrinsics: - vmulx_f64 - - a - FnCall: - - 'transmute::' - - - FnCall: - - "simd_extract!" - - - b - - 'LANE as u32' + - 'transmute' + - - FnCall: ['vget{neon_type.lane_nox}', [b], [LANE]] - name: "vmulx{type[0]}" doc: Floating-point multiply extended @@ -5380,11 +5146,7 @@ intrinsics: - FnCall: - "vmulx{type[3]}" - - a - - FnCall: - - "simd_shuffle!" - - - b - - b - - "{type[4]}" + - FnCall: ['vdup{type[0]}', [b], [LANE]] - name: "vmulx{type[0]}" doc: Floating-point multiply extended @@ -5397,16 +5159,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ["d_lane_f64", "f64", float64x1_t, "d_f64", 'LANE as u32'] + - ["d_lane_f64", "f64", float64x1_t, "d_f64"] compose: - FnCall: [static_assert!, ['LANE == 0']] - FnCall: - "vmulx{type[3]}" - - a - - FnCall: - - "simd_extract!" - - - b - - "{type[4]}" + - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]] - name: "vmulx_laneq_f64" doc: Floating-point multiply extended @@ -5426,11 +5185,8 @@ intrinsics: - vmulx_f64 - - a - FnCall: - - 'transmute::' - - - FnCall: - - "simd_extract!" - - - b - - 'LANE as u32' + - 'transmute' + - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]] - name: "vmulx{type[0]}" doc: Floating-point multiply extended @@ -5443,21 +5199,17 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32; 2]'] - - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32; 2]'] - - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32', '[LANE as u32; 4]'] - - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32', '[LANE as u32; 4]'] - - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64', '[LANE as u32; 2]'] + - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32'] + - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32'] + - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32'] + - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32'] + - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - FnCall: - "vmulx{type[4]}" - - a - - FnCall: - - "simd_shuffle!" - - - b - - b - - "{type[5]}" + - FnCall: ['vdup{type[0]}', [b], [LANE]] - name: "vmulx{type[0]}" @@ -5473,20 +5225,16 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16', '[LANE as u32; 4]'] - - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16', '[LANE as u32; 4]'] - - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16', '[LANE as u32; 8]'] - - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16', '[LANE as u32; 8]'] + - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16'] + - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16'] + - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16'] + - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - FnCall: - "vmulx{type[4]}" - - a - - FnCall: - - "simd_shuffle!" - - - b - - b - - "{type[5]}" + - FnCall: ['vdup{type[0]}', [b], [LANE]] - name: "vmulx{type[0]}" @@ -5500,18 +5248,15 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ['s_lane_f32', f32, float32x2_t, '1', 's_f32', 'LANE as u32'] - - ['s_laneq_f32', f32, float32x4_t, '2', 's_f32', 'LANE as u32'] - - ['d_laneq_f64', f64, float64x2_t, '1', 'd_f64', 'LANE as u32'] + - ['s_lane_f32', f32, float32x2_t, '1', 's_f32'] + - ['s_laneq_f32', f32, float32x4_t, '2', 's_f32'] + - ['d_laneq_f64', f64, float64x2_t, '1', 'd_f64'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - FnCall: - "vmulx{type[4]}" - - a - - FnCall: - - "simd_extract!" - - - b - - "{type[5]}" + - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]] - name: "vmulx{type[0]}" @@ -5534,10 +5279,7 @@ intrinsics: - FnCall: - "vmulx{type[4]}" - - a - - FnCall: - - "simd_extract!" - - - b - - "{type[5]}" + - FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE]] - name: "vmulx{neon_type[0].N}" @@ -5831,18 +5573,18 @@ intrinsics: doc: Signed Subtract Wide arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" - attr: [*neon-stable] - assert_instr: [ssubw2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubw2]]}]] safety: safe types: - - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]'] - - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]'] + - [int16x8_t, int8x16_t] + - [int32x4_t, int16x8_t] + - [int64x2_t, int32x4_t] compose: - Let: - c - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[1]}', [b]] - FnCall: - simd_sub - - a @@ -5852,18 +5594,18 @@ intrinsics: doc: Unsigned Subtract Wide arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" - attr: [*neon-stable] - assert_instr: [usubw2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubw2]]}]] safety: safe types: - - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + - [uint16x8_t, uint8x16_t] + - [uint32x4_t, uint16x8_t] + - [uint64x2_t, uint32x4_t] compose: - Let: - c - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[1]}', [b]] - FnCall: - simd_sub - - a @@ -5873,61 +5615,47 @@ intrinsics: doc: "Signed Subtract Long" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [ssubl2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubl2]]}]] safety: safe types: - - [int8x16_t, int16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t] - - [int16x8_t, int32x4_t, '[4, 5, 6, 7]', int16x4_t] - - [int32x4_t, int64x2_t, '[2, 3]', int32x2_t] + - [int8x16_t, int16x8_t] + - [int32x4_t, int64x2_t] + - [int16x8_t, int32x4_t] compose: - Let: - c - - "{neon_type[3]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - d - "{neon_type[1]}" - - FnCall: [simd_cast, [c]] - - Let: - - e - - "{neon_type[3]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]] - Let: - - f + - d - "{neon_type[1]}" - - FnCall: [simd_cast, [e]] - - FnCall: [simd_sub, [d, f]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [b]]}]] + - FnCall: [simd_sub, [c, d]] - name: "vsubl_high{neon_type[0].noq}" doc: "Unsigned Subtract Long" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [usubl2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubl2]]}]] safety: safe types: - - [uint8x16_t, uint16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint8x8_t] - - [uint16x8_t, uint32x4_t, '[4, 5, 6, 7]', uint16x4_t] - - [uint32x4_t, uint64x2_t, '[2, 3]', uint32x2_t] + - [uint8x16_t, uint16x8_t] + - [uint16x8_t, uint32x4_t] + - [uint32x4_t, uint64x2_t] compose: - Let: - c - - "{neon_type[3]}" - - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] - - Let: - - d - "{neon_type[1]}" - - FnCall: [simd_cast, [c]] - - Let: - - e - - "{neon_type[3]}" - - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [a]]}]] - Let: - - f + - d - "{neon_type[1]}" - - FnCall: [simd_cast, [e]] - - FnCall: [simd_sub, [d, f]] + - FnCall: [simd_cast, [{FnCall: ['vget_high_{neon_type[0]}', [b]]}]] + - FnCall: [simd_sub, [c, d]] - name: "vbcax{neon_type.no}" doc: Bit clear and exclusive OR @@ -5980,6 +5708,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcadd] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6000,6 +5729,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcadd] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6022,6 +5752,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcadd] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6043,6 +5774,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcadd] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6062,6 +5794,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6084,6 +5817,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6103,6 +5837,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6125,6 +5860,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6144,6 +5880,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6167,6 +5904,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6189,14 +5927,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x4_t, ''] + - [float32x4_t, float32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] - name: "vcmla{neon_type[0].laneq_nox}" @@ -6213,14 +5950,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x8_t, ''] + - [float16x8_t, float16x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] - name: "vcmla{neon_type[0].rot90_laneq}" @@ -6235,14 +5971,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x4_t, ''] + - [float32x4_t, float32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] - name: "vcmla{neon_type[0].rot90_laneq}" @@ -6259,14 +5994,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x8_t, ''] + - [float16x8_t, float16x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] - name: "vcmla{neon_type[0].rot90_lane}" @@ -6281,14 +6015,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x2_t, ''] + - [float32x4_t, float32x2_t, 'q'] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] - name: "vcmla{neon_type[0].rot90_lane}" @@ -6305,14 +6038,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x4_t, ''] + - [float16x8_t, float16x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] - name: "vcmla{neon_type.rot180}" @@ -6324,6 +6056,7 @@ intrinsics: - *neon-unstable-fcma assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float32x2_t - float32x4_t @@ -6347,6 +6080,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fcmla] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -6370,14 +6104,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x4_t, ''] + - [float32x4_t, float32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] - name: "vcmla{neon_type[0].rot180_laneq}" @@ -6394,19 +6127,16 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x8_t, - '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]' - ] + - [float16x4_t, float16x8_t, ''] + - [float16x8_t, float16x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] - - name: "vcmla{type[3]}" + - name: "vcmla{neon_type[0].rot180_lane}" doc: Floating-point complex multiply accumulate arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" @@ -6418,17 +6148,16 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f32'] - - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', 'q_rot180_lane_f32'] + - [float32x2_t, float32x2_t, ''] + - [float32x4_t, float32x2_t, 'q'] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] - - name: "vcmla{type[3]}" + - name: "vcmla{neon_type[0].rot180_lane}" doc: Floating-point complex multiply accumulate arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" @@ -6442,16 +6171,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f16'] - - [float16x8_t, float16x4_t, - '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', 'q_rot180_lane_f16' - ] + - [float16x4_t, float16x4_t, ''] + - [float16x8_t, float16x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] - name: "vcmla{neon_type[0].rot270_laneq}" @@ -6466,14 +6192,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x4_t, ''] + - [float32x4_t, float32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - name: "vcmla{neon_type[0].rot270_laneq}" @@ -6490,14 +6215,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x8_t, ''] + - [float16x8_t, float16x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpretq_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_laneq_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - name: "vcmla{neon_type[0].lane_nox}" @@ -6512,14 +6236,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x2_t, ''] + - [float32x4_t, float32x2_t, 'q'] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] @@ -6537,14 +6260,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x4_t, ''] + - [float16x8_t, float16x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] - name: "vcmla{neon_type[0].rot270_lane}" @@ -6559,11 +6281,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x2_t, float32x2_t, ''] + - [float32x4_t, float32x2_t, 'q'] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] + - Let: [c, {FnCall: [vreinterpret_u64_f32, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u64', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f32_u64', [c]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - name: "vcmla{neon_type[0].rot270_lane}" @@ -6580,11 +6304,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float16x4_t, float16x4_t, ''] + - [float16x8_t, float16x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 1]] - - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] + - Let: [c, {FnCall: [vreinterpret_u32_f16, [c]]}] + - Let: [c, {FnCall: ['vdup{type[2]}_lane_u32', [c], [LANE]]}] + - Let: [c, {FnCall: ['vreinterpret{type[2]}_f16_u32', [c]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - name: "vmax{neon_type.no}" @@ -6878,7 +6604,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, "f32"] @@ -6896,7 +6622,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmv]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x4_t, "f32"] @@ -6911,36 +6637,36 @@ intrinsics: doc: Vector move arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [sxtl2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sxtl2]]}]] safety: safe types: - - [int8x16_t, int16x8_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]'] - - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]'] + - [int8x16_t, int16x8_t] + - [int16x8_t, int32x4_t] + - [int32x4_t, int64x2_t] compose: - Let: - a - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[0]}', [a]] - FnCall: ["vmovl{neon_type[0].noq}", [a]] - name: "vmovl_high{neon_type[0].noq}" doc: Vector move arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" - attr: [*neon-stable] - assert_instr: [uxtl2] + attr: + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uxtl2]]}]] safety: safe types: - - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint32x4_t, uint64x2_t, uint32x2_t, '[2, 3]'] + - [uint8x16_t, uint16x8_t] + - [uint16x8_t, uint32x4_t] + - [uint32x4_t, uint64x2_t] compose: - Let: - a - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[0]}', [a]] - FnCall: ["vmovl{neon_type[0].noq}", [a]] - name: "vpadd{neon_type[0].no}" @@ -6950,6 +6676,7 @@ intrinsics: attr: [*neon-stable] assert_instr: [faddp] safety: safe + big_endian_inverse: true types: - [float32x4_t, "4"] - [float64x2_t, "2"] @@ -6972,6 +6699,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [faddp] safety: safe + big_endian_inverse: true types: - [float16x8_t, "8"] compose: @@ -6993,6 +6721,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmaxp] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -7014,6 +6743,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmaxnmp] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -7035,6 +6765,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fminp] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -7056,6 +6787,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fminnmp] safety: safe + big_endian_inverse: true types: - float16x4_t - float16x8_t @@ -7081,11 +6813,11 @@ intrinsics: - Let: - a1 - "{type[2]}" - - FnCall: [simd_extract!, [a, '0']] + - FnCall: ['vget{neon_type[1].lane_nox}', [a], [0]] - Let: - a2 - "{type[2]}" - - FnCall: [simd_extract!, [a, '1']] + - FnCall: ['vget{neon_type[1].lane_nox}', [a], [1]] - Identifier: ['a1 + a2', Symbol] - name: "vpmin{type[0]}" @@ -7095,6 +6827,7 @@ intrinsics: attr: [*neon-stable] assert_instr: [fminp] safety: safe + big_endian_inverse: true types: - ["s_f32", float32x2_t, f32] - ["qd_f64", float64x2_t, f64] @@ -7111,14 +6844,14 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", "i32"] compose: - Let: [a, int16x4_t, {FnCall: [vdup_n_s16, [a]]}] - Let: [b, int16x4_t, {FnCall: [vdup_n_s16, [b]]}] - - FnCall: [simd_extract!, [{FnCall: [vqdmull_s16, [a, b]]}, '0']] + - FnCall: ['vgetq_lane_{type[1]}', [{FnCall: [vqdmull_s16, [a, b]]}], ['0']] - name: "vqdmulls_s32" doc: "Signed saturating doubling multiply long" @@ -7126,7 +6859,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i32", "i64"] @@ -7142,15 +6875,15 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2]]}]] + - *neon-stable safety: safe types: - - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]'] - - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]'] + - [int16x8_t, int32x4_t] + - [int32x4_t, int64x2_t] compose: - - Let: [a, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, '{type[3]}']]}] - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, '{type[3]}']]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [b]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull_high_n_{type[1]}" @@ -7158,15 +6891,15 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2]]}]] + - *neon-stable safety: safe types: - - [int16x8_t, "i16", int32x4_t, int16x4_t, '[4, 5, 6, 7]'] - - [int32x4_t, "i32", int64x2_t, int32x2_t, '[2, 3]'] + - [int16x8_t, "i16", int32x4_t] + - [int32x4_t, "i32", int64x2_t] compose: - - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - Let: [b, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[0].noq}", [b]]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ["vdup_n{neon_type[0].noq}", [b]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull{type[3]}" @@ -7176,7 +6909,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7184,7 +6917,7 @@ intrinsics: - ["i32", int32x4_t, "i64", 's_laneq_s32', 's_s32'] compose: - FnCall: [static_assert_uimm_bits!, [N, 2]] - - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ["vqdmull{type[4]}", [a, b]] - name: "vqdmullh_laneq_s16" @@ -7194,14 +6927,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, N = 4]]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - ["i16", int16x8_t, "i32"] compose: - FnCall: [static_assert_uimm_bits!, [N, 3]] - - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ["vqdmullh_s16", [a, b]] - name: "vqdmulls_lane_s32" @@ -7211,33 +6944,33 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - ["i32", int32x2_t, "i64"] compose: - FnCall: [static_assert_uimm_bits!, [N, 1]] - - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ["vqdmulls_s32", [a, b]] - - name: "vqdmull{type[6]}" + - name: "vqdmull{type[3]}" doc: "Signed saturating doubling multiply long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int16x8_t, int16x4_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]', '_high_lane_s16'] - - [int32x4_t, int32x4_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]', '_high_laneq_s32'] + - [int16x8_t, int16x4_t, int32x4_t, '_high_lane_s16'] + - [int32x4_t, int32x4_t, int64x2_t, '_high_laneq_s32'] compose: - FnCall: [static_assert_uimm_bits!, [N, '2']] - - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull_high_lane_s32" @@ -7245,17 +6978,17 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int32x4_t, int32x2_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]'] + - [int32x4_t, int32x2_t, int64x2_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '1']] - - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull_high_laneq_s16" @@ -7263,17 +6996,17 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int16x8_t, int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]'] + - [int16x8_t, int16x8_t, int32x4_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '3']] - - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - Let: [a, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] - name: "vqdmull_laneq_s16" @@ -7283,14 +7016,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 4']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int16x4_t, int16x8_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]'] + - [int16x4_t, int16x8_t, int32x4_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '3']] - - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: [vqdmull_s16, [a, b]] - name: "vqdmull_laneq_s32" @@ -7300,14 +7033,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int32x2_t, int32x4_t, int64x2_t, '[N as u32, N as u32]'] + - [int32x2_t, int32x4_t, int64x2_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '2']] - - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vdup_lane{neon_type[1].nox}', [b], [N]]}] - FnCall: [vqdmull_s32, [a, b]] - name: "vqdmlal{type[4]}" @@ -7315,8 +7048,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal2]]}]] + - *neon-stable safety: safe types: - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16] @@ -7331,9 +7064,9 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7350,14 +7083,14 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal]]}]] + - *neon-stable safety: safe types: - ["i32", "i16", "s16"] compose: - Let: [x, int32x4_t, {FnCall: [vqdmull_s16, [{FnCall: [vdup_n_s16, [b]]}, {FnCall: [vdup_n_s16, [c]]}]]}] - - FnCall: [vqadds_s32, [a, {FnCall: [simd_extract!, [x, 0]]}]] + - FnCall: [vqadds_s32, [a, {FnCall: ['vgetq_lane_s32', [x], [0]]}]] - name: "vqdmlals_s32" doc: "Signed saturating doubling multiply-add long" @@ -7365,7 +7098,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "i32", "i32", "i64"] @@ -7378,9 +7111,9 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -7390,16 +7123,16 @@ intrinsics: - ["i64", "i32", int32x4_t, "i64", s_laneq_s32, '2', s_s32] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - - FnCall: ["vqdmlal{type[6]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vqdmlal{type[6]}", [a, b, {FnCall: ['vget{neon_type[2].lane_nox}', [c], [LANE]]}]] - name: "vqdmlal_laneq_s16" doc: "Vector widening saturating doubling multiply accumulate with scalar" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7413,9 +7146,9 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7429,8 +7162,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl2]]}]] + - *neon-stable safety: safe types: - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16] @@ -7445,9 +7178,9 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7464,14 +7197,14 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl]]}]] + - *neon-stable safety: safe types: - ["i32", "i16"] compose: - Let: [x, int32x4_t, {FnCall: [vqdmull_s16, [{FnCall: [vdup_n_s16, [b]]}, {FnCall: [vdup_n_s16, [c]]}]]}] - - FnCall: [vqsubs_s32, [a, {FnCall: [simd_extract!, [x, '0']]}]] + - FnCall: [vqsubs_s32, [a, {FnCall: ['vgetq_lane_s32', [x], [0]]}]] - name: "vqdmlsls_s32" doc: "Signed saturating doubling multiply-subtract long" @@ -7479,7 +7212,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "i32", "i32", "i64"] @@ -7492,9 +7225,9 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -7504,16 +7237,16 @@ intrinsics: - ["i64", "i32", int32x4_t, "i64", 's_laneq_s32', '2', 's_s32'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - - FnCall: ["vqdmlsl{type[6]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vqdmlsl{type[6]}", [a, b, {FnCall: ['vget{neon_type[2].lane_nox}', [c], [LANE]]}]] - name: "vqdmlsl_laneq_s16" doc: "Vector widening saturating doubling multiply subtract with scalar" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7527,9 +7260,9 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7544,7 +7277,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", "i16", "i16", int16x4_t, 'h_s16'] @@ -7552,7 +7285,7 @@ intrinsics: compose: - Let: [a, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[3].no}", [a]]}] - Let: [b, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[3].no}", [b]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqdmulh{neon_type[3].no}", [a, b]]}, '0']] + - FnCall: ['vget{neon_type[3].lane_nox}', [{FnCall: ["vqdmulh{neon_type[3].no}", [a, b]]}], ['0']] - name: "vqdmulhh{type[3]}" doc: "Signed saturating doubling multiply returning high half" @@ -7561,7 +7294,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7569,7 +7302,7 @@ intrinsics: - ["i16", int16x8_t, "i16", '_laneq_s16', '3'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[4]}"]] - - Let: [b, 'i16', {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, 'i16', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ['vqdmulhh_s16', [a, b]] - name: "vqdmulhs{type[3]}" @@ -7579,7 +7312,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7587,7 +7320,7 @@ intrinsics: - ["i32", int32x4_t, "i32", "_laneq_s32", '2'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[4]}"]] - - Let: [b, 'i32', {FnCall: [simd_extract!, [b, 'N as u32']]}] + - Let: [b, 'i32', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [N]]}] - FnCall: ['vqdmulhs_s32', [a, b]] - name: "vqmovn_high{neon_type[1].noq}" @@ -7595,30 +7328,30 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqxtn2]]}]] + - *neon-stable safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int32x4_t] compose: - - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}, "{type[3]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}]] - name: "vqmovn_high{neon_type[1].noq}" doc: "Signed saturating extract narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqxtn2]]}]] + - *neon-stable safety: safe types: - - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint32x4_t] compose: - - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}, "{type[3]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}]] - name: "vqmovn{type[2]}" doc: "Saturating extract narrow" @@ -7626,13 +7359,13 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", "i8", 'h_s16', s16] - ["i32", "i16", 's_s32', s32] compose: - - FnCall: [simd_extract!, [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']] - name: "vqmovn{type[2]}" doc: "Saturating extract narrow" @@ -7640,13 +7373,13 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u16", "u8", 'h_u16', 'u16'] - ["u32", "u16", 's_u32', 'u32'] compose: - - FnCall: [simd_extract!, [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']] - name: "vqmovnd_s64" doc: "Saturating extract narrow" @@ -7654,7 +7387,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "i32"] @@ -7671,7 +7404,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", "u32"] @@ -7688,29 +7421,29 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", "u8", 'h_s16', s16] - ["i32", "u16", 's_s32', s32] - ["i64", "u32", 'd_s64', s64] compose: - - FnCall: [simd_extract!, [{FnCall: ["vqmovun_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqmovun_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}], ['0']] - name: "vqmovun_high_{neon_type[1]}" doc: "Signed saturating extract unsigned narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqxtun2]]}]] + - *neon-stable safety: safe types: - - [uint8x8_t, int16x8_t, uint8x16_t, s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, int32x4_t, uint16x8_t, s32, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, int64x2_t, uint32x4_t, s64, '[0, 1, 2, 3]'] + - [uint8x8_t, int16x8_t, uint8x16_t, s16] + - [uint16x4_t, int32x4_t, uint16x8_t, s32] + - [uint32x2_t, int64x2_t, uint32x4_t, s64] compose: - - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovun_{type[3]}", [b]]}, "{type[4]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqmovun_{type[3]}", [b]]}]] - name: "vqrdmulh{type[1]}" doc: "Signed saturating rounding doubling multiply returning high half" @@ -7718,13 +7451,13 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i16", 'h_s16', 's16'] - ["i32", 's_s32', 's32'] compose: - - FnCall: [simd_extract!, [{FnCall: ["vqrdmulh_{type[2]}", [{FnCall: ["vdup_n_{type[2]}", [a]]}, {FnCall: ["vdup_n_{type[2]}", [b]]}]]}, '0']] + - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrdmulh_{type[2]}", [{FnCall: ["vdup_n_{type[2]}", [a]]}, {FnCall: ["vdup_n_{type[2]}", [b]]}]]}], ['0']] - name: "vqrdmulh{type[2]}" doc: "Signed saturating rounding doubling multiply returning high half" @@ -7733,7 +7466,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh, LANE = 1]]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -7743,7 +7476,7 @@ intrinsics: - ["i32", int32x4_t, 's_laneq_s32', 's_s32', '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] - - FnCall: ["vqrdmulh{type[3]}", [a, {FnCall: [simd_extract!, [b, 'LANE as u32']]}]] + - FnCall: ["vqrdmulh{type[3]}", [a, {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}]] - name: "vqrdmlah{neon_type.no}" doc: "Signed saturating rounding doubling multiply accumulate returning high half" @@ -7782,7 +7515,7 @@ intrinsics: - Let: [a, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [a]]}] - Let: [b, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [b]]}] - Let: [c, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [c]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrdmlah_{type[2]}", [a, b, c]]}, '0']] + - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrdmlah_{type[2]}", [a, b, c]]}], ['0']] - name: "vqrdmlah{type[0]}" doc: "Signed saturating rounding doubling multiply accumulate returning high half" @@ -7796,17 +7529,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32; 4]'] - - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32; 4]'] - - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]'] - - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]'] - - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32; 2]'] - - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32; 2]'] - - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]'] - - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]'] + - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3'] + - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] - - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}] + - Let: [c, {FnCall: ['vdup{type[0]}', [c], [LANE]]}] - FnCall: ["vqrdmlah{neon_type[2].no}", [a, b, c]] - name: "vqrdmlah{type[4]}" @@ -7827,7 +7560,7 @@ intrinsics: - ["i32", int32x4_t, '2', "s_s32", s_laneq_s32, s_s32] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] - - FnCall: ["vqrdmlah{type[5]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vqrdmlah{type[5]}", [a, b, {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vqrdmlsh{neon_type.no}" doc: "Signed saturating rounding doubling multiply subtract returning high half" @@ -7866,7 +7599,7 @@ intrinsics: - Let: [a, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [a]]}] - Let: [b, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [b]]}] - Let: [c, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [c]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrdmlsh_{type[3]}", [a, b, c]]}, '0']] + - FnCall: ['vget{neon_type[2].lane_nox}', [{FnCall: ["vqrdmlsh_{type[3]}", [a, b, c]]}], ['0']] - name: "vqrdmlsh{type[0]}" doc: "Signed saturating rounding doubling multiply subtract returning high half" @@ -7880,17 +7613,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32; 4]'] - - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32; 4]'] - - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]'] - - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]'] - - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32; 2]'] - - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32; 2]'] - - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]'] - - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]'] + - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3'] + - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] - - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}] + - Let: [c, {FnCall: ['vdup{type[0]}', [c], [LANE]]}] - FnCall: ["vqrdmlsh{neon_type[2].no}", [a, b, c]] - name: "vqrdmlsh{type[3]}" @@ -7911,7 +7644,7 @@ intrinsics: - ["i32", int32x4_t, '2', s_laneq_s32, s_s32] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] - - FnCall: ["vqrdmlsh{type[4]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vqrdmlsh{type[4]}", [a, b, {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vqrshl{type[0]}" doc: "Signed saturating rounding shift left" @@ -7919,7 +7652,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ['s_s32', "i32"] @@ -7937,7 +7670,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i8", 'b_s8', int8x8_t, s8] @@ -7945,7 +7678,7 @@ intrinsics: compose: - Let: [a, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [a]]}] - Let: [b, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [b]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrshl_{type[3]}", [a, b]]}, '0']] + - FnCall: ['vget{neon_type[2].lane_nox}', [{FnCall: ["vqrshl_{type[3]}", [a, b]]}], ['0']] - name: "vqrshl{type[2]}" doc: "Unsigned signed saturating rounding shift left" @@ -7953,7 +7686,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u32", "i32", 's_u32'] @@ -7971,7 +7704,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u8", "i8", "b_u8", uint8x8_t, int8x8_t, s8] @@ -7979,7 +7712,7 @@ intrinsics: compose: - Let: [a, "{neon_type[3]}", {FnCall: ["vdup_n_{type[0]}", [a]]}] - Let: [b, "{neon_type[4]}", {FnCall: ["vdup_n_{type[5]}", [b]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrshl_{type[0]}", [a, b]]}, '0']] + - FnCall: ['vget{neon_type[3].lane_nox}', [{FnCall: ["vqrshl_{type[0]}", [a, b]]}], ['0']] - name: "vqrshrn{type[2]}" doc: "Signed saturating rounded shift right narrow" @@ -7988,7 +7721,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -7998,25 +7731,25 @@ intrinsics: compose: - FnCall: [static_assert!, ["{type[3]}"]] - Let: [a, "{neon_type[4]}", {FnCall: ["vdup{type[5]}", [a]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrshrn_n{neon_type[4].noq}::", [a]]}, '0']] + - FnCall: ['vget_lane_{type[1]}', [{FnCall: ["vqrshrn_n{neon_type[4].noq}::", [a]]}], ['0']] - name: "vqrshrn{type[3]}" doc: "Signed saturating rounded shift right narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, '_high_n_s16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', 'N >= 1 && N <= 8'] - - [int16x4_t, int32x4_t, int16x8_t, '_high_n_s32', '[0, 1, 2, 3, 4, 5, 6, 7]', 'N >= 1 && N <= 16'] - - [int32x2_t, int64x2_t, int32x4_t, '_high_n_s64', '[0, 1, 2, 3]', 'N >= 1 && N <= 32'] + - [int8x8_t, int16x8_t, int8x16_t, '_high_n_s16', 'N >= 1 && N <= 8'] + - [int16x4_t, int32x4_t, int16x8_t, '_high_n_s32', 'N >= 1 && N <= 16'] + - [int32x2_t, int64x2_t, int32x4_t, '_high_n_s64', 'N >= 1 && N <= 32'] compose: - - FnCall: [static_assert!, ["{type[5]}"]] - - FnCall: [simd_shuffle!, [a, {FnCall: ["vqrshrn_n{neon_type[1].noq}::", [b]]}, "{type[4]}"]] + - FnCall: [static_assert!, ["{type[4]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vqrshrn_n{neon_type[1].noq}::", [b]]}]] - name: "vqrshrn{type[0]}" doc: "Unsigned saturating rounded shift right narrow" @@ -8025,7 +7758,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8035,31 +7768,30 @@ intrinsics: compose: - FnCall: [static_assert!, ['{type[3]}']] - Let: [a, "{neon_type[4]}", {FnCall: ["vdup{type[5]}", [a]]}] - - FnCall: [simd_extract!, [{FnCall: ["vqrshrn{type[6]}::", [a]]}, '0']] + - FnCall: ['vget_lane_{type[2]}', [{FnCall: ["vqrshrn{type[6]}::", [a]]}], ['0']] - name: "vqrshrn_high_n{neon_type[1].noq}" doc: "Unsigned saturating rounded shift right narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ['{type[3]}']] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - FnCall: - "vqrshrn_n{neon_type[1].noq}::" - - b - - "{type[4]}" - name: "vqrshrun{type[0]}" doc: "Signed saturating rounded shift right unsigned narrow" @@ -8068,7 +7800,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8082,35 +7814,34 @@ intrinsics: - "{neon_type[4]}" - FnCall: ["vdupq_n_{type[5]}", [a]] - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vqrshrun_n_{type[5]}::" - - a - - '0' + - - '0' - name: "vqrshrun_high_n{neon_type[1].noq}" doc: "Signed saturating rounded shift right unsigned narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', s32, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32', s64, '[0, 1, 2, 3]'] + - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - FnCall: - - "vqrshrun_n_{type[4]}::" + - "vqrshrun_n_{neon_type[1]}::" - - b - - "{type[5]}" - name: "vqshld_{type}" doc: "Signed saturating shift left" @@ -8118,7 +7849,7 @@ intrinsics: return_type: "{type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - i64 @@ -8135,7 +7866,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [b_s8, "i8", int8x8_t] @@ -8149,7 +7880,7 @@ intrinsics: - "vqshl{neon_type[2].noq}" - - FnCall: ["vdup_n{neon_type[2].no}", [a]] - FnCall: ["vdup_n{neon_type[2].no}", [b]] - - FnCall: [simd_extract!, [c, '0']] + - FnCall: ['vget{neon_type[2].lane_nox}', [c], ['0']] - name: "vqshl{type[0]}" doc: "Signed saturating shift left" @@ -8158,7 +7889,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8169,11 +7900,11 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vqshl_n_{type[3]}::" - - FnCall: ["vdup_n_{type[3]}", [a]] - - '0' + - - '0' - name: "vqshld_{type[0]}" doc: "Unsigned saturating shift left" @@ -8181,7 +7912,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", "i64"] @@ -8198,7 +7929,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [b_u8, "u8", "i8", uint8x8_t, int8x8_t] @@ -8212,7 +7943,7 @@ intrinsics: - "vqshl{neon_type[3].noq}" - - FnCall: ["vdup{neon_type[3].N}", [a]] - FnCall: ["vdup{neon_type[4].N}", [b]] - - FnCall: [simd_extract!, [c, '0']] + - FnCall: ['vget{neon_type[3].lane_nox}', [c], ['0']] - name: "vqshl{type[0]}" doc: "Unsigned saturating shift left" @@ -8221,7 +7952,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8232,9 +7963,9 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: ["vqshl_n_{type[1]}::", [{FnCall: ["vdup_n_{type[1]}", [a]]}]] - - '0' + - - '0' - name: "vqshrnd_n_s64" doc: "Signed saturating shift right narrow" @@ -8243,7 +7974,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8267,7 +7998,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8276,33 +8007,32 @@ intrinsics: compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vqshrn_n_{type[4]}::" - - FnCall: ["vdupq_n_{type[4]}", [a]] - - '0' + - - '0' - name: "vqshrn{type[0]}" doc: "Signed saturating shift right narrow" arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[3]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [_high_n_s16, int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', s16] - - [_high_n_s32, int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]', s32] - - [_high_n_s64, int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]', s64] + - [_high_n_s16, int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8'] + - [_high_n_s32, int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16'] + - [_high_n_s64, int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[4]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[1]}' - - a - - FnCall: ["vqshrn_n_{type[6]}::", [b]] - - "{type[5]}" + - FnCall: ["vqshrn_n_{neon_type[2]}::", [b]] - name: "vqshrnd_n_u64" doc: "Unsigned saturating shift right narrow" @@ -8311,7 +8041,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8335,7 +8065,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8344,33 +8074,32 @@ intrinsics: compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - "simd_extract!" + - 'vget_lane_{type[2]}' - - FnCall: - "vqshrn_n_{type[1]}::" - - FnCall: ["vdupq_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vqshrn{type[0]}" doc: "Unsigned saturating shift right narrow" arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[3]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [_high_n_u16, uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [_high_n_u32, uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [_high_n_u64, uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [_high_n_u16, uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [_high_n_u32, uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [_high_n_u64, uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[4]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[1]}' - - a - FnCall: ["vqshrn_n_{neon_type[2]}::", [b]] - - "{type[5]}" - name: "vqshrun{type[0]}" doc: "Signed saturating shift right unsigned narrow" @@ -8379,7 +8108,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8389,33 +8118,32 @@ intrinsics: compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vqshrun_n_{type[4]}::" - - FnCall: ["vdupq_n_{type[4]}", [a]] - - '0' + - - '0' - name: "vqshrun_high_n_{neon_type[1]}" doc: "Signed saturating shift right unsigned narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - FnCall: ["vqshrun_n_{neon_type[1]}::", [b]] - - "{type[4]}" - name: "vsqadd{type[0]}" doc: "Unsigned saturating accumulate of signed value" @@ -8423,19 +8151,19 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [b_u8, "u8", "i8", s8] - [h_u16, "u16", "i16", s16] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vsqadd_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[2]}", [b]] - - '0' + - - '0' - name: "vsqadd{type[0]}" doc: "Unsigned saturating accumulate of signed value" @@ -8443,7 +8171,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_u32, "u32", "i32"] @@ -8461,7 +8189,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fsqrt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float32x2_t @@ -8508,7 +8236,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [_f64, float64x1_t, v1f64] @@ -8526,7 +8254,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_f32, "f32"] @@ -8565,7 +8293,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [_f64, float64x1_t, v1f64] @@ -8583,7 +8311,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_f32, "f32"] @@ -8622,7 +8350,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [_f64, float64x1_t, v1f64] @@ -8640,7 +8368,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_f32, "f32"] @@ -8679,7 +8407,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [s_f32, "f32"] @@ -8711,7 +8439,6 @@ intrinsics: - link: "llvm.aarch64.neon.frecpx.{type[1]}" arch: aarch64,arm64ec - - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" doc: Vector reinterpret cast operation arguments: ["a: {type[0]}"] @@ -8728,54 +8455,65 @@ intrinsics: - [poly64x2_t, uint64x2_t] - [int64x2_t, poly64x2_t] - [uint64x2_t, poly64x2_t] + - [float64x1_t, int64x1_t] + - [float64x2_t, int64x2_t] + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + - [float64x1_t, poly64x1_t] + - [float64x2_t, poly64x2_t] + - [int64x1_t, float64x1_t] + - [int64x2_t, float64x2_t] + - [uint64x1_t, float64x1_t] + - [uint64x2_t, float64x2_t] + - [poly64x1_t, float64x1_t] + - [poly64x2_t, float64x2_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [nop] + safety: safe + types: - [float64x1_t, int8x8_t] - [float64x1_t, int16x4_t] - [float64x1_t, int32x2_t] - - [float64x1_t, int64x1_t] - [float64x2_t, int8x16_t] - [float64x2_t, int16x8_t] - [float64x2_t, int32x4_t] - - [float64x2_t, int64x2_t] - [float64x1_t, uint8x8_t] - [float64x1_t, uint16x4_t] - [float64x1_t, uint32x2_t] - - [float64x1_t, uint64x1_t] - [float64x2_t, uint8x16_t] - [float64x2_t, uint16x8_t] - [float64x2_t, uint32x4_t] - - [float64x2_t, uint64x2_t] - [float64x1_t, poly8x8_t] - [float64x1_t, poly16x4_t] - [float32x2_t, poly64x1_t] - - [float64x1_t, poly64x1_t] - [float64x2_t, poly8x16_t] - [float64x2_t, poly16x8_t] - [float32x4_t, poly64x2_t] - - [float64x2_t, poly64x2_t] - [float64x2_t, p128] - [int8x8_t, float64x1_t] - [int16x4_t, float64x1_t] - [int32x2_t, float64x1_t] - - [int64x1_t, float64x1_t] - [int8x16_t, float64x2_t] - [int16x8_t, float64x2_t] - [int32x4_t, float64x2_t] - - [int64x2_t, float64x2_t] - [poly8x8_t, float64x1_t] - [uint16x4_t, float64x1_t] - [uint32x2_t, float64x1_t] - - [uint64x1_t, float64x1_t] - [poly8x16_t, float64x2_t] - [uint16x8_t, float64x2_t] - [uint32x4_t, float64x2_t] - - [uint64x2_t, float64x2_t] - [uint8x8_t, float64x1_t] - [poly16x4_t, float64x1_t] - - [poly64x1_t, float64x1_t] - [poly64x1_t, float32x2_t] - [uint8x16_t, float64x2_t] - [poly16x8_t, float64x2_t] - - [poly64x2_t, float64x2_t] - [poly64x2_t, float32x4_t] - [p128, float64x2_t] - [float32x2_t, float64x1_t] @@ -8811,7 +8549,7 @@ intrinsics: return_type: "{type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - "i64" @@ -8828,7 +8566,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", "i64"] @@ -8846,7 +8584,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshr, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8862,7 +8600,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshr, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -8876,197 +8614,262 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8'] + - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16'] + - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32'] + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - FnCall: ["vrshrn_n_{neon_type[1]}::", [b]] - - "{type[4]}" - name: "vrsubhn_high_{neon_type[1]}" doc: "Rounding subtract returning high narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[3]}" attr: - - *little-endian + - *cfg-little-endian - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int64x2_t, int32x4_t] + - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t] compose: - - Let: - - x - - "{neon_type[0]}" - - FnCall: ["vrsubhn_{neon_type[1]}", [b, c]] - - FnCall: [simd_shuffle!, [a, x, "{type[4]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vrsubhn_{neon_type[1]}", [b, c]]}]] - name: "vrsubhn_high_{neon_type[1]}" doc: "Rounding subtract returning high narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[3]}" attr: - - *big-endian + - *cfg-big-endian - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int64x2_t, int32x4_t] + - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t] compose: - - Let: - - x - - "{neon_type[0]}" - - FnCall: ["vrsubhn_{neon_type[1]}", [b, c]] - - FnCall: [simd_shuffle!, [a, x, "{type[4]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, {FnCall: ["vrsubhn_{neon_type[1]}", [b, c]]}]] - name: "vcopy{neon_type[0].lane_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [int8x8_t, int8x8_t, int8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int16x4_t, int16x4_t, int16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int32x2_t, int32x2_t, int32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float32x2_t, float32x2_t, float32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int8x8_t, int8x8_t, int8x8_t, '3', '3'] + - [int16x4_t, int16x4_t, int16x4_t, '2', '2'] + - [int32x2_t, int32x2_t, int32x2_t, '1', '1'] + - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3'] + - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2'] + - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1'] + - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3'] + - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2'] + - [float32x2_t, float32x2_t, float32x2_t, '1', '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] - - Identifier: ["{type[5]}", Symbol] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]] - name: "vcopy{neon_type[0].lane_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - *neon-stable + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: safe + types: + - [int8x16_t, int8x8_t, int8x16_t, '4', '3'] + - [int16x8_t, int16x4_t, int16x8_t, '3', '2'] + - [int32x4_t, int32x2_t, int32x4_t, '2', '1'] + - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3'] + - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2'] + - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1'] + - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3'] + - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] + - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] + - Let: [b, '{neon_type[2]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[2].lane_nox}', [b], [LANE2]]}, a], [LANE1]] + + - name: "vcopy_lane_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["_a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE1 = {type[1]}', 'LANE2 = {type[1]}']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - *neon-stable + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: safe + types: + - [float64x1_t, '0', 'b'] + - [poly64x1_t, '0', 'b'] + - [uint64x1_t, '0', 'b'] + - [int64x1_t, '0', 'b'] + compose: + - FnCall: [static_assert!, ['LANE1 == {type[1]}']] + - FnCall: [static_assert!, ['LANE2 == {type[1]}']] + - Identifier: ["{type[2]}", Symbol] + + - name: "vcopy_laneq_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["_a: {neon_type[1]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE1 = {type[2]}', 'LANE2 = {type[3]}']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - *neon-stable + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: safe + types: + - [float64x2_t, float64x1_t, '0', '1'] + - [poly64x2_t, poly64x1_t, '0', '1'] + - [uint64x2_t, uint64x1_t, '0', '1'] + - [int64x2_t, int64x1_t, '0', '1'] + compose: + - FnCall: [static_assert!, ['LANE1 == {type[2]}']] + - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[3]}']] + - FnCall: [transmute, [{FnCall: ['vget{neon_type[0].lane_nox}', [b], [LANE2]]}]] + + - name: "vcopy{neon_type[0].laneq_nox}" + doc: "Insert vector element from another vector element" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [int8x16_t, int8x8_t, int8x16_t, '4', '3', ' let b: int8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int16x8_t, int16x4_t, int16x8_t, '3', '2', ' let b: int16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int32x4_t, int32x2_t, int32x4_t, '2', '1', ' let b: int32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3', ' let b: uint8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2', ' let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1', ' let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3', ' let b: poly8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2', ' let b: poly16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int8x16_t, int8x16_t, int8x16_t, '4', '4'] + - [int16x8_t, int16x8_t, int16x8_t, '3', '3'] + - [int32x4_t, int32x4_t, int32x4_t, '2', '2'] + - [int64x2_t, int64x2_t, int64x2_t, '1', '1'] + - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4'] + - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3'] + - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2'] + - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1'] + - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4'] + - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3'] + - [float32x4_t, float32x4_t, float32x4_t, '2', '2'] + - [float64x2_t, float64x2_t, float64x2_t, '1', '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] - - Identifier: ["{type[5]}", Symbol] - - Identifier: ["{type[6]}", Symbol] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]] - name: "vcopy{neon_type[0].laneq_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe + big_endian_inverse: true types: - - [int8x16_t, int8x16_t, int8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int16x8_t, int16x8_t, int16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int32x4_t, int32x4_t, int32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int64x2_t, int64x2_t, int64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float32x4_t, float32x4_t, float32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float64x2_t, float64x2_t, float64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] - - Identifier: ["{type[5]}", Symbol] + - FnCall: [simd_insert!, [a, LANE1 as u32, {FnCall: [simd_extract!, [b, LANE2 as u32, p64]]}]] - name: "vcopy{neon_type[0].laneq_nox}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [int8x8_t, int8x16_t, int8x8_t, '3', '4', ' let a: int8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int16x4_t, int16x8_t, int16x4_t, '2', '3', ' let a: int16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [int32x2_t, int32x4_t, int32x2_t, '1', '2', ' let a: int32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4', ' let a: uint8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3', ' let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2', 'let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4', ' let a: poly8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3', ' let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float32x2_t, float32x4_t, float32x2_t, '1', '2', ' let a: float32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int8x8_t, int8x16_t, int8x8_t, '3', '4'] + - [int16x4_t, int16x8_t, int16x4_t, '2', '3'] + - [int32x2_t, int32x4_t, int32x2_t, '1', '2'] + - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4'] + - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3'] + - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2'] + - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4'] + - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3'] + - [float32x2_t, float32x4_t, float32x2_t, '1', '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] - - Identifier: ["{type[5]}", Symbol] - - Identifier: ["{type[6]}", Symbol] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]] - name: "vcopyq_lane_{neon_type[0]}" doc: "Insert vector element from another vector element" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - *neon-stable + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: safe + types: + - [int64x2_t, int64x1_t] + - [uint64x2_t, uint64x1_t] + - [float64x2_t, float64x1_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE1, '1']] + - FnCall: [static_assert!, ['LANE2 == 0']] + - Let: [b, '{neon_type[0]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[0].lane_nox}', [b], [LANE2]]}, a], [LANE1]] + + - name: "vcopyq_lane_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe + big_endian_inverse: true types: - - [int64x2_t, int64x1_t, ' let b: int64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [uint64x2_t, uint64x1_t, ' let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [poly64x2_t, poly64x1_t, ' let b: poly64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] - - [float64x2_t, float64x1_t, ' let b: float64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly64x2_t, poly64x1_t] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '1']] - FnCall: [static_assert!, ['LANE2 == 0']] - - Identifier: ['{type[2]}', Symbol] - - Identifier: ['{type[3]}', Symbol] + - Let: [b, '{neon_type[0]}', {FnCall: ['vcombine{neon_type[1].no}', [b, b]]}] + - FnCall: [simd_insert!, [a, LANE1 as u32, {FnCall: [simd_extract!, [b, LANE2 as u32, p64]]}]] - name: "vcopyq_lane_f32" doc: "Insert vector element from another vector element" @@ -9075,16 +8878,15 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE1: i32, const LANE2: i32'] safety: safe types: - - [float32x4_t, float32x2_t, ' let b: float32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [float32x4_t, float32x2_t] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, 2]] - FnCall: [static_assert_uimm_bits!, [LANE2, 1]] - - Identifier: ["{type[2]}", Symbol] - - Identifier: ["{type[3]}", Symbol] + - FnCall: ['vset{neon_type[0].lane_nox}', [{FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE2]]}, a], [LANE1]] - name: "vcreate_f64" doc: "Insert vector element from another vector element" @@ -9092,7 +8894,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", float64x1_t] @@ -9106,9 +8908,10 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["f64", float64x1_t, float64x1_t] compose: @@ -9122,9 +8925,10 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["f64", float64x2_t, float64x2_t] compose: @@ -9137,7 +8941,7 @@ intrinsics: return_type: "{type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - "i64" @@ -9155,7 +8959,7 @@ intrinsics: return_type: "{type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["u64", "i64"] @@ -9172,63 +8976,62 @@ intrinsics: arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int8x16_t, int16x8_t, int8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x8_t, int32x4_t, int16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]'] - - [int32x4_t, int64x2_t, int32x2_t, 'N >= 0 && N <= 32', '[2, 3]'] + - [int8x16_t, int16x8_t, int8x8_t, 'N >= 0 && N <= 8'] + - [int16x8_t, int32x4_t, int16x4_t, 'N >= 0 && N <= 16'] + - [int32x4_t, int64x2_t, int32x2_t, 'N >= 0 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - FnCall: ["vshll_n_{neon_type[2]}::", [b]] + - Let: [b, {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - FnCall: ["vshll_n_{neon_type[2]}", [b], [N]] - name: "vshll_high_n_{neon_type[0]}" doc: "Signed shift left long" arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [uint8x16_t, uint16x8_t, uint8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x8_t, uint32x4_t, uint16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]'] - - [uint32x4_t, uint64x2_t, uint32x2_t, 'N >= 0 && N <= 32', '[2, 3]'] + - [uint8x16_t, uint16x8_t, uint8x8_t, 'N >= 0 && N <= 8'] + - [uint16x8_t, uint32x4_t, uint16x4_t, 'N >= 0 && N <= 16'] + - [uint32x4_t, uint64x2_t, uint32x2_t, 'N >= 0 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] - - FnCall: ["vshll_n_{neon_type[2]}::", [b]] + - Let: [b, "{neon_type[2]}", {FnCall: ['vget_high_{neon_type[0]}', [a]]}] + - FnCall: ["vshll_n_{neon_type[2]}", [b], [N]] - name: "vshrn_high_n_{neon_type[1]}" doc: "Shift right narrow" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8'] + - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16'] + - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32'] + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32'] compose: - FnCall: [static_assert!, ["{type[3]}"]] - FnCall: - - simd_shuffle! + - 'vcombine_{neon_type[0]}' - - a - - FnCall: ["vshrn_n_{neon_type[1]}::", [b]] - - "{type[4]}" + - FnCall: ["vshrn_n_{neon_type[1]}", [b], [N]] - name: "vsm3partw1{neon_type.no}" doc: "SM3PARTW1" @@ -9239,6 +9042,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3partw1]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9257,6 +9061,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3partw2]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9275,6 +9080,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3ss1]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9293,6 +9099,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm4ekey]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9311,6 +9118,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm4e]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] safety: safe + big_endian_inverse: true types: - uint32x4_t compose: @@ -9347,6 +9155,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512h]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] safety: safe + big_endian_inverse: true types: - uint64x2_t compose: @@ -9365,6 +9174,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512h2]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] safety: safe + big_endian_inverse: true types: - uint64x2_t compose: @@ -9383,6 +9193,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512su0]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] safety: safe + big_endian_inverse: true types: - uint64x2_t compose: @@ -9401,6 +9212,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512su1]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] safety: safe + big_endian_inverse: true types: - uint64x2_t compose: @@ -9421,6 +9233,7 @@ intrinsics: - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] static_defs: ["const IMM2: i32"] safety: safe + big_endian_inverse: true types: - ['1aq_u32', uint32x4_t, 'sm3tt1a', 'SM3TT1A'] - ['1bq_u32', uint32x4_t, 'sm3tt1b', 'SM3TT1B'] @@ -9523,7 +9336,7 @@ intrinsics: - transmute - - FnCall: - _vrnd32x_f64 - - - FnCall: [simd_extract!, [a, 0]] + - - FnCall: ['vget{neon_type.lane_nox}', [a], [0]] - name: "vrnd32z{neon_type.no}" doc: "Floating-point round to 32-bit integer toward zero" @@ -9567,7 +9380,7 @@ intrinsics: arch: aarch64,arm64ec - FnCall: - transmute - - - FnCall: [_vrnd32z_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + - - FnCall: [_vrnd32z_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]] - name: "vrnd64x{neon_type.no}" doc: "Floating-point round to 64-bit integer, using current rounding mode" @@ -9611,7 +9424,7 @@ intrinsics: arch: aarch64,arm64ec - FnCall: - transmute - - - FnCall: [_vrnd64x_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + - - FnCall: [_vrnd64x_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]] - name: "vrnd64z{neon_type.no}" doc: "Floating-point round to 64-bit integer toward zero" @@ -9655,7 +9468,7 @@ intrinsics: arch: aarch64,arm64ec - FnCall: - transmute - - - FnCall: [_vrnd64z_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + - - FnCall: [_vrnd64z_f64, [{FnCall: ['vget{neon_type.lane_nox}', [a], [0]]}]] - name: "vtrn1{neon_type[0].no}" doc: Transpose vectors @@ -9663,8 +9476,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn1]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] - [int8x16_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]'] @@ -9693,8 +9507,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn1]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[0, 4, 2, 6]'] - [float16x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] @@ -9707,8 +9522,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]] safety: safe + big_endian_inverse: true types: - [int32x2_t, '[0, 2]'] - [int64x2_t, '[0, 2]'] @@ -9726,8 +9542,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn2]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] - [int8x16_t, '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] @@ -9755,8 +9572,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn2]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[1, 5, 3, 7]'] - [float16x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] @@ -9769,8 +9587,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]] safety: safe + big_endian_inverse: true types: - [int32x2_t, '[1, 3]'] - [int64x2_t, '[1, 3]'] @@ -9788,8 +9607,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] - [int8x16_t, '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] @@ -9824,8 +9644,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[2, 6, 3, 7]'] - [float16x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -9838,8 +9659,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] - [int8x16_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]'] @@ -9875,8 +9697,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[0, 4, 1, 5]'] - [float16x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] @@ -9889,8 +9712,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]] safety: safe + big_endian_inverse: true types: - [int32x2_t, '[0, 2]'] - [int64x2_t, '[0, 2]'] @@ -9908,8 +9732,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp1]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] - [int8x16_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]'] @@ -9937,8 +9762,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp1]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[0, 2, 4, 6]'] - [float16x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] @@ -9951,8 +9777,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]] safety: safe + big_endian_inverse: true types: - [int32x2_t, '[1, 3]'] - [int64x2_t, '[1, 3]'] @@ -9970,8 +9797,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp2]]}]] safety: safe + big_endian_inverse: true types: - [int8x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] - [int8x16_t, '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] @@ -10003,8 +9831,9 @@ intrinsics: - *neon-fp16 - *neon-stable-fp16 - *target-not-arm64ec - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp2]]}]] safety: safe + big_endian_inverse: true types: - [float16x4_t, '[1, 3, 5, 7]'] - [float16x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] @@ -10020,23 +9849,21 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal2]]}]] + - *neon-stable + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uabal2]]}]] safety: safe types: - - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]', '[2, 3]'] + - [uint16x8_t, uint8x16_t, uint8x8_t] + - [uint32x4_t, uint16x8_t, uint16x4_t] + - [uint64x2_t, uint32x4_t, uint32x2_t] compose: - Let: - d - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: ['vget_high_{neon_type[1]}', [b]] - Let: - e - - "{neon_type[2]}" - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] - - Let: [f, "{neon_type[2]}", {FnCall: ["vabd_{neon_type[2]}", [d, e]]}] + - FnCall: ['vget_high_{neon_type[1]}', [c]] + - Let: [f, {FnCall: ["vabd_{neon_type[2]}", [d, e]]}] - FnCall: - simd_add - - a @@ -10048,39 +9875,28 @@ intrinsics: return_type: "{neon_type[0]}" attr: - *neon-stable - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sabal2]]}]] + - FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [sabal2]]}]] safety: safe types: - - [int16x8_t, int8x16_t, int8x16_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t, uint8x8_t] - - [int32x4_t, int16x8_t, int16x8_t, '[4, 5, 6, 7]', int16x4_t, uint16x4_t] - - [int64x2_t, int32x4_t, int32x4_t, '[2, 3]', int32x2_t, uint32x2_t] + - [int16x8_t, int8x16_t, int8x16_t, int8x8_t, uint8x8_t] + - [int32x4_t, int16x8_t, int16x8_t, int16x4_t, uint16x4_t] + - [int64x2_t, int32x4_t, int32x4_t, int32x2_t, uint32x2_t] compose: - Let: - d - - "{neon_type[4]}" - - FnCall: - - simd_shuffle! - - - b - - b - - "{type[3]}" + - FnCall: ['vget_high_{neon_type[1]}', [b]] - Let: - e - - "{neon_type[4]}" - - FnCall: - - simd_shuffle! - - - c - - c - - "{type[3]}" + - FnCall: ['vget_high_{neon_type[2]}', [c]] - Let: - f - - "{neon_type[4]}" - FnCall: - - "vabd{neon_type[4].no}" + - "vabd{neon_type[3].no}" - - d - e - Let: - f - - "{neon_type[5]}" + - "{neon_type[4]}" - FnCall: - simd_cast - - f @@ -10173,8 +9989,9 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - float32x2_t - float64x2_t @@ -10191,7 +10008,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -10214,7 +10031,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -10238,7 +10055,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -10265,7 +10082,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10280,7 +10097,7 @@ intrinsics: - "vfma{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vfma{type[3]}" @@ -10306,7 +10123,7 @@ intrinsics: - "vfma{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] # vfms lane f16 @@ -10333,7 +10150,7 @@ intrinsics: - "vfms{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vfms{type[1]}" @@ -10359,7 +10176,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10370,16 +10187,16 @@ intrinsics: - "vfma{neon_type.no}" - - a - b - - FnCall: ["vdup{neon_type.N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type.N}", [{FnCall: ['vget{neon_type.lane_nox}', [c], [LANE]]}]] - name: "vfma_laneq_f64" doc: "Floating-point fused multiply-add to accumulator" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10390,7 +10207,7 @@ intrinsics: - "vfma{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vfmaq_lane_f64" doc: "Floating-point fused multiply-add to accumulator" @@ -10399,7 +10216,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10410,16 +10227,16 @@ intrinsics: - "vfma{neon_type[0].no}" - - a - b - - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]] - name: "vfma{type[2]}" doc: "Floating-point fused multiply-add to accumulator" arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10428,7 +10245,7 @@ intrinsics: - ["f64", float64x2_t, "d_laneq_f64", '1'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}] + - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}] - FnCall: ["fma{type[0]}", [b, c, a]] - name: "vfmad_lane_f64" @@ -10438,14 +10255,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - ["f64", float64x1_t] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}] + - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}] - FnCall: [fmaf64, [b, c, a]] @@ -10470,7 +10287,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[0]}", "v: {neon_type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-fp16 - *neon-unstable-f16 @@ -10482,7 +10299,7 @@ intrinsics: - ["f16", float16x8_t, 'q_f16', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [v, 'LANE as u32']]}] + - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [v], [LANE]]}] - FnCall: ["vfmah_{type[0]}", [a, b, c]] - name: "vfmsh_lane{type[2]}" @@ -10490,7 +10307,7 @@ intrinsics: arguments: ["a: {type[0]}", "b: {type[0]}", "v: {neon_type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-fp16 - *neon-unstable-f16 @@ -10502,7 +10319,7 @@ intrinsics: - ["f16", float16x8_t, 'q_f16', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [v, 'LANE as u32']]}] + - Let: [c, "{type[0]}", {FnCall: ['vget{neon_type[1].lane_nox}', [v], [LANE]]}] - FnCall: ["vfmsh_{type[0]}", [a, b, c]] - name: "vfms_f64" @@ -10511,7 +10328,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -10525,7 +10342,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x2_t @@ -10539,7 +10356,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -10554,7 +10371,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10565,7 +10382,7 @@ intrinsics: - [float64x2_t, float64x2_t, '1', q_laneq_f64] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[2]}']] - - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]] - name: "vfms_lane_f64" doc: "Floating-point fused multiply-subtract to accumulator" @@ -10574,30 +10391,30 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - float64x1_t compose: - FnCall: [static_assert!, ['LANE == 0']] - - FnCall: ["vfms{neon_type.no}", [a, b, {FnCall: ["vdup{neon_type.N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + - FnCall: ["vfms{neon_type.no}", [a, b, {FnCall: ["vdup{neon_type.N}", [{FnCall: ['vget{neon_type.lane_nox}', [c], [LANE]]}]]}]] - name: "vfms_laneq_f64" doc: "Floating-point fused multiply-subtract to accumulator" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - [float64x1_t, float64x2_t] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]] - name: "vfmsq_lane_f64" doc: "Floating-point fused multiply-subtract to accumulator" @@ -10606,23 +10423,23 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - [float64x2_t, float64x1_t] compose: - FnCall: [static_assert!, ['LANE == 0']] - - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: ['vget{neon_type[1].lane_nox}', [c], [LANE]]}]]}]] - name: "vfms{type[2]}" doc: "Floating-point fused multiply-subtract to accumulator" arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"] return_type: "{type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -10640,7 +10457,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, 'f32x2', 'f32x2::new(0.0, 0.0)'] @@ -10674,18 +10491,18 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", "s_f32"] - ["f64", "u64", "d_f64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vceqz_{type[0]}" - - FnCall: ["vdup_n_{type[0]}", [a]] - - '0' + - - '0' - name: "vceqz{type[2]}" doc: "Floating-point compare bitwise equal to zero" @@ -10701,11 +10518,11 @@ intrinsics: - ["f16", "u16", "h_f16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vceqz_{type[0]}" - - FnCall: ["vdup_n_{type[0]}", [a]] - - '0' + - - '0' - name: "vceqzd_{type[2]}" doc: "Compare bitwise equal to zero" @@ -10713,7 +10530,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64", "s64"] @@ -10731,7 +10548,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -10759,7 +10576,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint8x8_t, uint8x8_t, u8x8, 'u8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -10783,7 +10600,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - uint64x1_t @@ -10797,19 +10614,19 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcge_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcge{type[0]}" @@ -10826,12 +10643,12 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcge_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - FnCall: ["vdup_n_{type[1]}", [b]] - - '0' + - - '0' - name: "vcge{neon_type[0].no}" doc: "Floating-point compare greater than or equal" @@ -10839,7 +10656,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -10853,7 +10670,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["d_s64", "i64", "u64", s64] @@ -10872,7 +10689,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - uint64x1_t @@ -10886,7 +10703,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s64", "i64", "u64"] @@ -10905,7 +10722,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint64x1_t, u64x1, 'u64x1::new(0)'] @@ -10921,7 +10738,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] @@ -10941,18 +10758,18 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcgez_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcgez{type[0]}" @@ -10969,11 +10786,11 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vcgez_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vclezd_s64" doc: "Compare less than or equal to zero" @@ -10981,7 +10798,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64"] @@ -10996,7 +10813,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64", 's64'] @@ -11015,7 +10832,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] @@ -11039,7 +10856,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["i64", "u64"] @@ -11056,7 +10873,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] @@ -11073,18 +10890,18 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] compose: - FnCall: - - "simd_extract!" + - 'vget_lane_{type[2]}' - - FnCall: - "vcgtz_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcgtz{type[0]}" doc: "Floating-point compare greater than zero" @@ -11100,11 +10917,11 @@ intrinsics: - ["h_f16", "f16", "u16"] compose: - FnCall: - - "simd_extract!" + - 'vget_lane_{type[2]}' - - FnCall: - "vcgtz_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - '0' + - - '0' - name: "vcvt{neon_type[1].no}_{neon_type[0]}" doc: "Floating-point convert to unsigned fixed-point, rounding toward zero" @@ -11112,7 +10929,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -11130,7 +10947,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, "f64"] @@ -11148,7 +10965,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11160,7 +10977,7 @@ intrinsics: - - a - FnCall: - "transmute::" - - - FnCall: [simd_extract!, [b, 'LANE as u32']] + - - FnCall: ['vget{neon_type.lane_nox}', [b], [LANE]] - name: "vmulq_lane_f64" doc: "Floating-point multiply" @@ -11169,7 +10986,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11179,7 +10996,7 @@ intrinsics: - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [b, b, '[LANE as u32; 2]']] + - FnCall: [vdupq_lane_f64, [b], [LANE]] - name: "vmuld_lane_f64" doc: "Floating-point multiply" @@ -11188,14 +11005,14 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - ["f64", float64x1_t] compose: - FnCall: [static_assert!, ['LANE == 0']] - - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}] + - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}] - Identifier: ['a * b', Symbol] - name: "vmul_laneq_f64" @@ -11205,7 +11022,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11217,7 +11034,7 @@ intrinsics: - - a - FnCall: - "transmute::" - - - FnCall: [simd_extract!, [b, 'LANE as u32']] + - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]] - name: "vmulq_laneq_f64" doc: "Floating-point multiply" @@ -11226,7 +11043,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11236,7 +11053,7 @@ intrinsics: - FnCall: - simd_mul - - a - - FnCall: [simd_shuffle!, [b, b, '[LANE as u32; 2]']] + - FnCall: [vdupq_laneq_f64, [b], [LANE]] # vmulq_laneq_f16 @@ -11253,14 +11070,14 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float16x4_t, float16x8_t, '_lane', "[LANE as u32; 4]"] - - [float16x8_t, float16x8_t, 'q_lane', "[LANE as u32; 8]"] + - [float16x4_t, float16x8_t, '_lane'] + - [float16x8_t, float16x8_t, 'q_lane'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '3']] - FnCall: - simd_mul - - a - - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: ['vdup{neon_type[0].laneq_nox}', [b], [LANE]] - name: "vmul{type[1]}_{type[0]}" @@ -11286,7 +11103,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11295,7 +11112,7 @@ intrinsics: - ["f64", float64x2_t, "d_laneq_f64", '1'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}] + - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}] - Identifier: ['a * b', Symbol] @@ -11316,7 +11133,7 @@ intrinsics: - ["f16", float16x8_t, "h_laneq_f16", '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}] + - Let: [b, '{type[0]}', {FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]]}] - Identifier: ['a * b', Symbol] @@ -11327,7 +11144,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshr, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -11342,8 +11159,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2]]}]] + - *neon-stable safety: safe types: - [int32x4_t, int16x8_t, "i16"] @@ -11356,8 +11173,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2]]}]] + - *neon-stable safety: safe types: - [uint32x4_t, uint16x8_t, "u16"] @@ -11370,46 +11187,46 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]'] - - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]'] - - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]'] - - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]'] + - [int32x4_t, int16x8_t, int16x4_t, '2'] + - [int32x4_t, int16x8_t, int16x8_t, '3'] + - [int64x2_t, int32x4_t, int32x2_t, '1'] + - [int64x2_t, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmlsl_high_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlsl_high_lane{neon_type[2].no}" doc: "Multiply-subtract long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32; 8]'] - - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32; 8]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32; 4]'] - - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32; 4]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '2'] + - [uint32x4_t, uint16x8_t, uint16x8_t, '3'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '1'] + - [uint64x2_t, uint32x4_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmlsl_high_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]] - name: "vclt{neon_type[0].no}" doc: "Floating-point compare less than" @@ -11417,7 +11234,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, uint64x1_t] @@ -11431,19 +11248,19 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["f32", "u32", 's_f32'] - ["f64", "u64", 'd_f64'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vclt_{type[0]}" - - FnCall: ["vdup_n_{type[0]}", [a]] - FnCall: ["vdup_n_{type[0]}", [b]] - - '0' + - - '0' - name: "vclt{type[2]}" @@ -11460,29 +11277,38 @@ intrinsics: - ["f16", "u16", 'h_f16'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vclt_{type[0]}" - - FnCall: ["vdup_n_{type[0]}", [a]] - FnCall: ["vdup_n_{type[0]}", [b]] - - '0' + - - '0' - - name: "vabdl_high_{neon_type[0]}" - doc: "Unsigned Absolute difference Long" + - name: "vabdl_high{neon_type[0].noq}" + doc: Unsigned Absolute difference Long arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]] safety: safe types: - - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]'] - - [uint32x4_t, uint64x2_t, uint32x2_t, '[2, 3]'] + - [uint8x16_t, uint16x8_t] + - [uint16x8_t, uint32x4_t] + - [uint32x4_t, uint64x2_t] compose: - - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[3]}"]]}] - - Let: [d, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] - - FnCall: [simd_cast, [{FnCall: ["vabd_{neon_type[0]}", [c, d]]}]] + - Let: + - c + - FnCall: ['vget_high_{neon_type[0]}', [a]] + - Let: + - d + - FnCall: ['vget_high_{neon_type[0]}', [b]] + - FnCall: + - simd_cast + - - FnCall: + - "vabd_{neon_type[0]}" + - - c + - d - name: "vfms_n_f64" doc: "Floating-point fused Multiply-subtract to accumulator(vector)" @@ -11490,7 +11316,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, "f64"] @@ -11507,7 +11333,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x2_t, "f64"] @@ -11548,8 +11374,9 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - ['s_f32', float32x2_t, "f32"] - ['qd_f64', float64x2_t, "f64"] @@ -11566,8 +11393,9 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - ['s_f32', float32x2_t, "f32"] - ['qd_f64', float64x2_t, "f64"] @@ -11584,7 +11412,7 @@ intrinsics: return_type: "{type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s64", "i64", "u64"] @@ -11604,7 +11432,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: @@ -11619,14 +11447,14 @@ intrinsics: - - a - FnCall: - "vdup{neon_type[0].N}" - - - FnCall: [simd_extract!, [b, 'LANE as u32']] + - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]] - name: "vqabs{type[2]}" doc: "Signed saturating absolute value" arguments: ["a: {type[0]}"] return_type: "{type[0]}" attr: - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] safety: safe types: @@ -11634,16 +11462,16 @@ intrinsics: - ["i16", "s16", 'h_s16'] compose: - FnCall: - - "simd_extract!" + - 'vget_lane_{type[0]}' - - FnCall: ["vqabs_{type[1]}", [{FnCall: ["vdup_n_{type[1]}", [a]]}]] - - '0' + - - '0' - name: "vqabs{type[1]}" doc: "Signed saturating absolute value" arguments: ["a: {type[0]}"] return_type: "{type[0]}" attr: - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] safety: safe types: @@ -11661,8 +11489,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]] + - *neon-stable safety: safe types: - [int16x8_t, "i16", int32x4_t] @@ -11678,8 +11506,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]] + - *neon-stable safety: safe types: - [uint16x8_t, "u16", uint32x4_t] @@ -11695,44 +11523,44 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32; 8]'] - - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32; 8]'] - - [int32x4_t, int32x2_t, int64x2_t, '1', '[LANE as u32; 4]'] - - [int32x4_t, int32x4_t, int64x2_t, '2', '[LANE as u32; 4]'] + - [int16x8_t, int16x4_t, int32x4_t, '2'] + - [int16x8_t, int16x8_t, int32x4_t, '3'] + - [int32x4_t, int32x2_t, int64x2_t, '1'] + - [int32x4_t, int32x4_t, int64x2_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmull_high_{neon_type[0]}" - - a - - FnCall: [simd_shuffle!, [b, b, '{type[4]}']] + - FnCall: ['vdupq_lane{neon_type[1].no}', [b], [LANE]] - name: "vmull_high_lane{neon_type[1].no}" doc: "Multiply long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32; 8]'] - - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32; 8]'] - - [uint32x4_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32; 4]'] - - [uint32x4_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32; 4]'] + - [uint16x8_t, uint16x4_t, uint32x4_t, '2'] + - [uint16x8_t, uint16x8_t, uint32x4_t, '3'] + - [uint32x4_t, uint32x2_t, uint64x2_t, '1'] + - [uint32x4_t, uint32x4_t, uint64x2_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmull_high_{neon_type[0]}" - - a - - FnCall: [simd_shuffle!, [b, b, '{type[4]}']] + - FnCall: ['vdupq_lane{neon_type[1].no}', [b], [LANE]] - name: "vrsqrte{neon_type.no}" doc: "Reciprocal square-root estimate." @@ -11740,7 +11568,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - float64x1_t @@ -11758,7 +11586,7 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["s_f32", "f32"] @@ -11797,8 +11625,9 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - float32x2_t - float64x2_t @@ -11817,7 +11646,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshlu, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['1']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -11828,11 +11657,11 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: - - simd_extract! + - 'vget_lane_{type[2]}' - - FnCall: - "vqshlu_n_{type[4]}::" - - FnCall: ["vdup_n_{type[4]}", [a]] - - '0' + - - '0' - name: "vcvta{neon_type[1].no}_{neon_type[0]}" doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to away" @@ -11840,7 +11669,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float32x2_t, uint32x2_t] @@ -11882,7 +11711,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [float64x1_t, int64x1_t] @@ -11905,6 +11734,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "i16", 'h'] - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] compose: @@ -11915,22 +11745,6 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtms.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtm{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to integer, rounding towards minus infinity" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "i16", 'h', 'i32'] - compose: - - 'vcvtmh_{type[3]}_f16(a) as i16' - - - name: "vcvtm{type[2]}_{type[1]}_{type[0]}" doc: "Floating-point convert to unsigned integer, rounding towards minus infinity" arguments: ["a: {type[0]}"] @@ -11942,6 +11756,7 @@ intrinsics: - *target-not-arm64ec safety: safe types: + - ["f16", "u16", 'h'] - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] compose: @@ -11952,28 +11767,13 @@ intrinsics: - link: "llvm.aarch64.neon.fcvtmu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - name: "vcvtm{type[2]}_{type[1]}_{type[0]}" - doc: "Floating-point convert to integer, rounding towards minus infinity" - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - - *neon-fp16 - - *neon-unstable-f16 - - *target-not-arm64ec - safety: safe - types: - - ["f16", "u16", 'h', 'u32'] - compose: - - 'vcvtmh_{type[3]}_f16(a) as u16' - - name: "vmlal_high_n_{neon_type[1]}" doc: "Multiply-add long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2]]}]] + - *neon-stable safety: safe types: - [int32x4_t, int16x8_t, "i16"] @@ -11990,8 +11790,8 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2]]}]] + - *neon-stable safety: safe types: - [uint32x4_t, uint16x8_t, "u16"] @@ -12008,38 +11808,38 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]'] - - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]'] - - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]'] - - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]'] + - [int32x4_t, int16x8_t, int16x4_t, '2'] + - [int32x4_t, int16x8_t, int16x8_t, '3'] + - [int64x2_t, int32x4_t, int32x2_t, '1'] + - [int64x2_t, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]] + - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]]}]] - name: "vmlal_high_lane{neon_type[2].no}" doc: "Multiply-add long" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32; 8]'] - - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32; 8]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32; 4]'] - - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32; 4]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '2'] + - [uint32x4_t, uint16x8_t, uint16x8_t, '3'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '1'] + - [uint64x2_t, uint32x4_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]] + - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: ['vdupq_lane{neon_type[2].no}', [c], [LANE]]}]] - name: "vrsrad_n_u64" doc: "Unsigned rounding shift right and accumulate." @@ -12048,7 +11848,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshr, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable static_defs: ['const N: i32'] safety: safe types: @@ -12064,7 +11864,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - uint64x1_t @@ -12078,7 +11878,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -12101,7 +11901,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -12118,7 +11918,7 @@ intrinsics: attr: - FnCall: [target_feature, ['enable = "neon,aes"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -12134,21 +11934,29 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, int8x8x4_t] + - [int8x8_t, 'int8x8x4_t', 'int8x16x2', 'int8x8', 'i8x8::splat(32)'] compose: + - Let: + - x + - FnCall: + - '{type[2]}_t' + - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] + - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'b.3']] - FnCall: - - "vqtbx2" - - - FnCall: [transmute, [a]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].noq}", ["b.0", "b.1"]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].noq}", ["b.2", "b.3"]] - - FnCall: [transmute, [c]] + - simd_select + - - FnCall: + - "simd_lt::<{type[3]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[4]}"]] + - FnCall: + - 'vqtbx2{neon_type[0].no}' + - - a + - x + - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]] + - a - name: "vtbx4{neon_type[0].no}" doc: "Extended table look-up" @@ -12156,25 +11964,30 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable safety: safe types: - - [uint8x8_t, uint8x8x4_t, uint8x8_t] - - [poly8x8_t, poly8x8x4_t, uint8x8_t] + - [uint8x8_t, 'uint8x8x4_t', 'uint8x8_t', 'uint8x16x2', 'uint8x8', 'u8x8::splat(32)'] + - [poly8x8_t, 'poly8x8x4_t', 'uint8x8_t', 'poly8x16x2', 'uint8x8', 'u8x8::splat(32)'] compose: + - Let: + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] + - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'b.3']] - FnCall: - - transmute - - - FnCall: - - "vqtbx2" - - - FnCall: [transmute, [a]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].noq}", ["b.0", "b.1"]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].noq}", ["b.2", "b.3"]] - - c + - simd_select + - - FnCall: + - "simd_lt::<{type[4]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[5]}"]] + - FnCall: + - 'vqtbx2{neon_type[0].no}' + - - a + - x + - c + - a - name: "vtbl1{neon_type[0].no}" doc: "Table look-up" @@ -12182,7 +11995,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [int8x8_t, 'int8x8_t', 'unsafe {{ transmute(b) }}'] @@ -12197,26 +12010,21 @@ intrinsics: - 'unsafe {{ crate::mem::zeroed() }}' - Identifier: ['{type[2]}', Symbol] - - name: "vtbl2{neon_type[1].noq}" + - name: "vtbl2{neon_type[2].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[1]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8x2_t, 'int8x8_t'] + - ['int8x8x2_t', 'int8x8_t', 'int8x8_t'] compose: - FnCall: - - vqtbl1 - - - FnCall: - - transmute - - - FnCall: - - 'vcombine{neon_type[1].noq}' - - - 'a.0' - - 'a.1' - - FnCall: [transmute, [b]] + - 'vqtbl1{neon_type[2].noq}' + - - FnCall: ['vcombine{neon_type[2].noq}', ['a.0', 'a.1']] + - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]] - name: "vtbl2{neon_type[2].no}" doc: "Table look-up" @@ -12224,128 +12032,107 @@ intrinsics: return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable safety: safe types: - - [uint8x8x2_t, 'uint8x8_t', 'uint8x8_t'] - - [poly8x8x2_t, 'uint8x8_t', 'poly8x8_t'] + - ['uint8x8x2_t', 'uint8x8_t', 'uint8x8_t'] + - ['poly8x8x2_t', 'uint8x8_t', 'poly8x8_t'] compose: - FnCall: - - transmute - - - FnCall: - - vqtbl1 - - - FnCall: - - transmute - - - FnCall: - - 'vcombine{neon_type[2].noq}' - - - 'a.0' - - 'a.1' - - b + - 'vqtbl1{neon_type[2].noq}' + - - FnCall: ['vcombine{neon_type[2].noq}', ['a.0', 'a.1']] + - b - name: "vtbl3{neon_type[1].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[1]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8x3_t, 'int8x8_t', 'int8x16x2'] + - ['int8x8x3_t', 'int8x8_t', 'int8x8_t', 'int8x16x2'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']] + - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - - transmute - - - FnCall: - - vqtbl2 - - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - FnCall: [transmute, [b]] + - 'vqtbl2{neon_type[2].no}' + - - x + - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]] - - name: "vtbl3{neon_type[3].no}" + + - name: "vtbl3{neon_type[2].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[3]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - - [poly8x8x3_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: false + - [uint8x8x3_t, 'uint8x8_t', 'uint8x8_t', 'uint8x16x2'] + - [poly8x8x3_t, 'uint8x8_t', 'poly8x8_t', 'poly8x16x2'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[3].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] - - FnCall: - - transmute - - - FnCall: - - vqtbl2 - - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - b + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']] + - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] + - FnCall: + - 'vqtbl2{neon_type[2].no}' + - - x + - b - - name: "vtbl4{neon_type[1].no}" + - name: "vtbl4{neon_type[2].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[1]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8x4_t, 'int8x8_t', 'int8x16x2'] + - ['int8x8x4_t', 'int8x8_t', 'int8x8_t', 'int8x16x2'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'a.3']] + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']] + - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'a.3']] - FnCall: - - transmute - - - FnCall: - - 'vqtbl2' - - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - FnCall: [transmute, [b]] + - 'vqtbl2{neon_type[2].no}' + - - x + - FnCall: ['vreinterpret_u8{neon_type[2].noq}', [b]] - - name: "vtbl4{neon_type[3].no}" + - name: "vtbl4{neon_type[2].no}" doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] - return_type: "{neon_type[3]}" + return_type: "{neon_type[2]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8x4_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - - [poly8x8x4_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: false + - [uint8x8x4_t, 'uint8x8_t', 'uint8x8_t', 'uint8x16x2'] + - [poly8x8x4_t, 'uint8x8_t', 'poly8x8_t', 'poly8x16x2'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[3].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'a.3']] - - FnCall: - - transmute - - - FnCall: - - 'vqtbl2' - - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - b + - x + - FnCall: + - '{type[3]}_t' + - - FnCall: ['vcombine{neon_type[2].no}', ['a.0', 'a.1']] + - FnCall: ['vcombine{neon_type[2].no}', ['a.2', 'a.3']] + - FnCall: + - 'vqtbl2{neon_type[2].no}' + - - x + - b - name: "vqtbx1{neon_type[0].no}" doc: "Extended table look-up" @@ -12353,8 +12140,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - [int8x8_t, int8x16_t, uint8x8_t, vqtbx1] - [int8x16_t, int8x16_t, uint8x16_t, vqtbx1q] @@ -12367,14 +12155,14 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [uint8x8_t, "uint8x16_t", uint8x8_t, "vqtbx1", "_u8"] - [poly8x8_t, "poly8x16_t", uint8x8_t, "vqtbx1", "_p8"] - [uint8x16_t, "uint8x16_t", uint8x16_t, "vqtbx1q", "q_u8"] - [poly8x16_t, "poly8x16_t", uint8x16_t, "vqtbx1q", "q_p8"] - big_endian_inverse: false + big_endian_inverse: true compose: - FnCall: - transmute @@ -12390,29 +12178,48 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, "int8x8_t", "transmute(c)", "i8x8::splat(8)", "int8x8"] - - [uint8x8_t, "uint8x8_t", "c", "u8x8::splat(8)", "uint8x8"] - - [poly8x8_t, "uint8x8_t", "c", "u8x8::splat(8)", "uint8x8"] + - [int8x8_t, "int8x8_t", "int8x8", "i8x8::splat(8)"] compose: - FnCall: - - simd_select - - - FnCall: - - "simd_lt::<{type[4]}_t, int8x8_t>" - - - c - - FnCall: [transmute, ["{type[3]}"]] - - FnCall: - - transmute - - - FnCall: - - "vqtbx1" - - - "transmute(a)" - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].no}", [b, "crate::mem::zeroed()"]] - - "{type[2]}" - - a + - simd_select + - - FnCall: + - "simd_lt::<{type[2]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[3]}"]] + - FnCall: + - 'vqtbx1{neon_type[0].no}' + - - a + - FnCall: ['vcombine{neon_type[0].no}', [b, 'crate::mem::zeroed()']] + - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]] + - a + + - name: "vtbx1{neon_type[0].no}" + doc: "Extended table look-up" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] + - *neon-stable + safety: safe + types: + - [uint8x8_t, "uint8x8_t", "uint8x8", "u8x8::splat(8)"] + - [poly8x8_t, "uint8x8_t", "uint8x8", "u8x8::splat(8)"] + compose: + - FnCall: + - simd_select + - - FnCall: + - "simd_lt::<{type[2]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[3]}"]] + - FnCall: + - 'vqtbx1{neon_type[0].no}' + - - a + - FnCall: ['vcombine{neon_type[0].no}', [b, 'crate::mem::zeroed()']] + - c + - a - name: "vtbx2{neon_type[0].no}" doc: "Extended table look-up" @@ -12420,18 +12227,23 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, 'int8x8x2_t'] + - [int8x8_t, 'int8x8x2_t', 'int8x8', 'i8x8::splat(16)'] compose: - FnCall: - - vqtbx1 - - - FnCall: [transmute, [a]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']] - - FnCall: [transmute, [c]] + - simd_select + - - FnCall: + - "simd_lt::<{type[2]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[3]}"]] + - FnCall: + - 'vqtbx1{neon_type[0].no}' + - - a + - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']] + - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]] + - a - name: "vtbx2{neon_type[0].no}" doc: "Extended table look-up" @@ -12439,22 +12251,24 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable safety: safe types: - - [uint8x8_t, 'uint8x8x2_t', uint8x8_t] - - [poly8x8_t, 'poly8x8x2_t', uint8x8_t] + - [uint8x8_t, 'uint8x8x2_t', uint8x8_t, 'uint8x8', 'u8x8::splat(16)'] + - [poly8x8_t, 'poly8x8x2_t', uint8x8_t, 'uint8x8', 'u8x8::splat(16)'] compose: - FnCall: - - transmute - - - FnCall: - - vqtbx1 - - - FnCall: [transmute, [a]] - - FnCall: - - transmute - - - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']] - - c + - simd_select + - - FnCall: + - "simd_lt::<{type[3]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[4]}"]] + - FnCall: + - 'vqtbx1{neon_type[0].no}' + - - a + - FnCall: ["vcombine{neon_type[0].no}", ['b.0', 'b.1']] + - c + - a - name: "vtbx3{neon_type[0].no}" doc: "Extended table look-up" @@ -12462,34 +12276,29 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'i8x8::splat(24)', 'int8x8'] + - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'int8x8', 'i8x8::splat(24)'] compose: - Let: - - x - - FnCall: - - '{type[2]}_t' - - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] - - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']] + - x + - FnCall: + - '{type[2]}_t' + - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] + - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - - transmute - - - FnCall: - - simd_select - - - FnCall: - - 'simd_lt::<{type[4]}_t, int8x8_t>' - - - FnCall: [transmute, [c]] - - FnCall: [transmute, ['{type[3]}']] - - FnCall: - - transmute - - - FnCall: - - 'vqtbx2' - - - FnCall: [transmute, [a]] - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - FnCall: [transmute, [c]] - - a + - simd_select + - - FnCall: + - "simd_lt::<{type[3]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[4]}"]] + - FnCall: + - 'vqtbx2{neon_type[0].no}' + - - a + - x + - FnCall: ['vreinterpret_u8{neon_type[0].no}', [c]] + - a - name: "vtbx3{neon_type[0].no}" doc: "Extended table look-up" @@ -12497,12 +12306,11 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'u8x8::splat(24)', 'uint8x8'] - - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'u8x8::splat(24)', 'poly8x8'] - big_endian_inverse: false + - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'uint8x8', 'u8x8::splat(24)'] + - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'uint8x8', 'u8x8::splat(24)'] compose: - Let: - x @@ -12511,22 +12319,17 @@ intrinsics: - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - - transmute - - - FnCall: - - simd_select - - - FnCall: - - 'simd_lt::<{type[4]}_t, int8x8_t>' - - - FnCall: [transmute, [c]] - - FnCall: [transmute, ['{type[3]}']] - - FnCall: - - transmute - - - FnCall: - - 'vqtbx2' - - - FnCall: [transmute, [a]] - - FnCall: [transmute, ['x.0']] - - FnCall: [transmute, ['x.1']] - - c - - a + - simd_select + - - FnCall: + - "simd_lt::<{type[3]}_t, int8x8_t>" + - - c + - FnCall: [transmute, ["{type[4]}"]] + - FnCall: + - 'vqtbx2{neon_type[0].no}' + - - a + - x + - c + - a - name: "vqtbl1{neon_type[3].no}" doc: "Table look-up" @@ -12534,8 +12337,9 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - ['int8x16_t', uint8x8_t, 'vqtbl1', 'int8x8_t'] - ['int8x16_t', uint8x16_t, 'vqtbl1q', 'int8x16_t'] @@ -12548,14 +12352,14 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ['uint8x16_t', uint8x8_t, 'vqtbl1', 'uint8x8_t'] - ['poly8x16_t', uint8x8_t, 'vqtbl1', 'poly8x8_t'] - ['uint8x16_t', uint8x16_t, 'vqtbl1q', 'uint8x16_t'] - ['poly8x16_t', uint8x16_t, 'vqtbl1q', 'poly8x16_t'] - big_endian_inverse: false + big_endian_inverse: true compose: - FnCall: - transmute @@ -12570,8 +12374,9 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - ['int8x16x2_t', uint8x8_t, 'vqtbl2', 'int8x8_t'] - ['int8x16x2_t', uint8x16_t, 'vqtbl2q', 'int8x16_t'] @@ -12584,8 +12389,8 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable + big_endian_inverse: true safety: safe types: - ['uint8x16x2_t', uint8x8_t, 'vqtbl2', 'uint8x8_t'] @@ -12607,8 +12412,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - [int8x8_t, 'int8x16x2_t', uint8x8_t, 'vqtbx2'] - [int8x16_t, 'int8x16x2_t', uint8x16_t, 'vqtbx2q'] @@ -12621,8 +12427,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable + big_endian_inverse: true safety: safe types: - [uint8x8_t, 'uint8x16x2_t', uint8x8_t, 'vqtbx2'] @@ -12645,8 +12451,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable + big_endian_inverse: true safety: safe types: - ['int8x8_t', 'int8x16x3_t', uint8x8_t, 'vqtbl3'] @@ -12660,8 +12466,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable + big_endian_inverse: true safety: safe types: - ['uint8x8_t', 'uint8x16x3_t', uint8x8_t, 'vqtbl3'] @@ -12684,8 +12490,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - [int8x8_t, 'int8x16x3_t', uint8x8_t, 'vqtbx3'] - [int8x16_t, 'int8x16x3_t', uint8x16_t, 'vqtbx3q'] @@ -12698,8 +12505,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable + big_endian_inverse: true safety: safe types: - [uint8x8_t, 'uint8x16x3_t', uint8x8_t, 'vqtbx3'] @@ -12723,8 +12530,8 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable + big_endian_inverse: true safety: safe types: - ['int8x16x4_t', uint8x8_t, 'vqtbl4', 'int8x8_t'] @@ -12738,8 +12545,8 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable + big_endian_inverse: true safety: safe types: - ['uint8x16x4_t', uint8x8_t, 'vqtbl4', 'uint8x8_t'] @@ -12763,8 +12570,9 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe + big_endian_inverse: true types: - [int8x8_t, 'int8x16x4_t', uint8x8_t, 'vqtbx4'] - [int8x16_t, 'int8x16x4_t', uint8x16_t, 'vqtbx4q'] @@ -12777,8 +12585,8 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable + big_endian_inverse: true safety: safe types: - [uint8x8_t, 'uint8x16x4_t', uint8x8_t, 'vqtbx4'] @@ -12804,7 +12612,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["vqtbl1", "int8x16_t", "uint8x8_t", "int8x8_t"] @@ -12823,7 +12631,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - ["vqtbl2", "int8x16_t", "uint8x8_t", "int8x8_t"] @@ -12842,8 +12650,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable safety: safe types: - ["vqtbl3", int8x16_t, uint8x8_t, int8x8_t] @@ -12862,8 +12669,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - big_endian_inverse: false + - *neon-stable safety: safe types: - ["vqtbl4", int8x16_t, uint8x8_t, int8x8_t] @@ -12882,7 +12688,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [vqtbx1, "int8x8_t", "int8x16_t", "uint8x8_t"] @@ -12901,7 +12707,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [vqtbx2, "int8x8_t", "int8x16_t", "uint8x8_t"] @@ -12920,7 +12726,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [vqtbx3, "int8x8_t", "int8x16_t", "uint8x8_t"] @@ -12939,7 +12745,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: safe types: - [vqtbx4, "int8x8_t", "int8x16_t", "uint8x8_t"] @@ -12958,7 +12764,7 @@ intrinsics: attr: - FnCall: [target_feature, ['enable = "{type[2]}"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldr]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -13025,7 +12831,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "{type[2]}"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [str]]}]] - FnCall: [allow, ['clippy::cast_ptr_alignment']] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - *neon-stable safety: unsafe: [neon] types: @@ -13227,6 +13033,7 @@ intrinsics: - *neon-stable assert_instr: [addp] safety: safe + big_endian_inverse: true types: - [int8x16_t, "16"] - [int16x8_t, "8"] @@ -13375,7 +13182,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.saddlv.i32.{neon_type[0]}" arch: aarch64,arm64ec - - Identifier: ["unsafe {{ _vaddlv{neon_type[0].no}(a) as i16 }}", Symbol] + - Identifier: ["_vaddlv{neon_type[0].no}(a) as i16", UnsafeSymbol] - name: "vaddlv{neon_type[0].no}" doc: "Unsigned Add Long across Vector" @@ -13395,7 +13202,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.uaddlv.i32.{neon_type[0]}" arch: aarch64,arm64ec - - Identifier: ["unsafe {{ _vaddlv{neon_type[0].no}(a) as u16 }}", Symbol] + - Identifier: ["_vaddlv{neon_type[0].no}(a) as u16", UnsafeSymbol] - name: "vmaxv{neon_type[0].no}" doc: "Horizontal vector max." @@ -13515,6 +13322,7 @@ intrinsics: - *neon-stable assert_instr: ['sminp'] safety: safe + big_endian_inverse: true types: - int8x16_t - int16x8_t @@ -13534,6 +13342,7 @@ intrinsics: - *neon-stable assert_instr: ['uminp'] safety: safe + big_endian_inverse: true types: - uint8x16_t - uint16x8_t @@ -13553,6 +13362,7 @@ intrinsics: - *neon-stable assert_instr: ['fminp'] safety: safe + big_endian_inverse: true types: - float32x4_t - float64x2_t @@ -13571,6 +13381,7 @@ intrinsics: - *neon-stable assert_instr: ['smaxp'] safety: safe + big_endian_inverse: true types: - int8x16_t - int16x8_t @@ -13590,6 +13401,7 @@ intrinsics: - *neon-stable assert_instr: ['umaxp'] safety: safe + big_endian_inverse: true types: - uint8x16_t - uint16x8_t @@ -13609,6 +13421,7 @@ intrinsics: - *neon-stable assert_instr: ['fmaxp'] safety: safe + big_endian_inverse: true types: - float32x4_t - float64x2_t @@ -13763,6 +13576,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmlal2] safety: safe + big_endian_inverse: true types: - [float32x2_t, float16x4_t, '_high_'] - [float32x4_t, float16x8_t, 'q_high_'] @@ -13774,7 +13588,7 @@ intrinsics: arch: aarch64,arm64ec - - name: "vfmlal{type[3]}{neon_type[1]}" + - name: "vfmlal{type[3]}_high_{neon_type[1]}" doc: "Floating-point fused Multiply-Add Long to accumulator (by element)." arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" @@ -13788,18 +13602,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float16x4_t, float16x4_t, '_lane_high_', '_high_', '2'] - - [float32x2_t, float16x4_t, float16x8_t, '_laneq_high_', '_high_', '3'] - - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_high_', 'q_high_', '2'] - - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_high_', 'q_high_', '3'] + - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_high_', '2'] + - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_high_', '3'] + - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_high_', '2'] + - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_high_', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - FnCall: - "vfmlal{type[4]}{neon_type[1]}" - - r - a - - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]] - + - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]] - name: "vfmlal{type[2]}{neon_type[1]}" doc: "Floating-point fused Multiply-Add Long to accumulator (vector)." @@ -13812,6 +13625,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmlal] safety: safe + big_endian_inverse: true types: - [float32x2_t, float16x4_t, '_low_'] - [float32x4_t, float16x8_t, 'q_low_'] @@ -13823,7 +13637,7 @@ intrinsics: arch: aarch64,arm64ec - - name: "vfmlal{type[3]}{neon_type[1]}" + - name: "vfmlal{type[3]}_low_{neon_type[1]}" doc: "Floating-point fused Multiply-Add Long to accumulator (by element)." arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" @@ -13837,18 +13651,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float16x4_t, float16x4_t, '_lane_low_', '_low_', '2'] - - [float32x2_t, float16x4_t, float16x8_t, '_laneq_low_', '_low_', '3'] - - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_low_', 'q_low_', '2'] - - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_low_', 'q_low_', '3'] + - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_low_', '2'] + - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_low_', '3'] + - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_low_', '2'] + - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_low_', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - FnCall: - "vfmlal{type[4]}{neon_type[1]}" - - r - a - - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]] - + - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]] - name: "vfmlsl{type[2]}{neon_type[1]}" doc: "Floating-point fused Multiply-Subtract Long from accumulator (vector)." @@ -13861,6 +13674,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmlsl2] safety: safe + big_endian_inverse: true types: - [float32x2_t, float16x4_t, '_high_'] - [float32x4_t, float16x8_t, 'q_high_'] @@ -13871,7 +13685,7 @@ intrinsics: - link: "llvm.aarch64.neon.fmlsl2.{neon_type[0]}.{neon_type[1]}" arch: aarch64,arm64ec - - name: "vfmlsl{type[3]}{neon_type[1]}" + - name: "vfmlsl{type[3]}_high_{neon_type[1]}" doc: "Floating-point fused Multiply-Subtract Long from accumulator (by element)." arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" @@ -13885,18 +13699,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float16x4_t, float16x4_t, '_lane_high_', '_high_', '2'] - - [float32x2_t, float16x4_t, float16x8_t, '_laneq_high_', '_high_', '3'] - - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_high_', 'q_high_', '2'] - - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_high_', 'q_high_', '3'] + - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_high_', '2'] + - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_high_', '3'] + - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_high_', '2'] + - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_high_', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - FnCall: - "vfmlsl{type[4]}{neon_type[1]}" - - r - a - - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]] - + - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]] - name: "vfmlsl{type[2]}{neon_type[1]}" doc: "Floating-point fused Multiply-Subtract Long from accumulator (vector)." @@ -13909,6 +13722,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [fmlsl] safety: safe + big_endian_inverse: true types: - [float32x2_t, float16x4_t, '_low_'] - [float32x4_t, float16x8_t, 'q_low_'] @@ -13919,7 +13733,7 @@ intrinsics: - link: "llvm.aarch64.neon.fmlsl.{neon_type[0]}.{neon_type[1]}" arch: aarch64,arm64ec - - name: "vfmlsl{type[3]}{neon_type[1]}" + - name: "vfmlsl{type[3]}_low_{neon_type[1]}" doc: "Floating-point fused Multiply-Subtract Long from accumulator (by element)." arguments: ["r: {neon_type[0]}", "a: {neon_type[1]}", "b: {neon_type[2]}"] return_type: "{neon_type[0]}" @@ -13933,17 +13747,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float16x4_t, float16x4_t, '_lane_low_', '_low_', '2'] - - [float32x2_t, float16x4_t, float16x8_t, '_laneq_low_', '_low_', '3'] - - [float32x4_t, float16x8_t, float16x4_t, 'q_lane_low_', 'q_low_', '2'] - - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq_low_', 'q_low_', '3'] + - [float32x2_t, float16x4_t, float16x4_t, '_lane', '_low_', '2'] + - [float32x2_t, float16x4_t, float16x8_t, '_laneq', '_low_', '3'] + - [float32x4_t, float16x8_t, float16x4_t, 'q_lane', 'q_low_', '2'] + - [float32x4_t, float16x8_t, float16x8_t, 'q_laneq', 'q_low_', '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] - FnCall: - "vfmlsl{type[4]}{neon_type[1]}" - - r - a - - FnCall: ["vdup{neon_type[1].N}", [{FnCall: [simd_extract!, [b, 'LANE as u32']]}]] + - FnCall: ["vdup{type[3]}_{neon_type[2]}", [b], [LANE]] - name: "vamax{neon_type.no}" doc: "Multi-vector floating-point absolute maximum" @@ -14361,3 +14175,49 @@ intrinsics: links: - link: "llvm.aarch64.fjcvtzs" arch: aarch64,arm64ec + + - name: "{type[0]}" + doc: "Duplicate vector element to vector or scalar" + arguments: ["a: {type[1]}"] + return_type: "{neon_type[2]}" + attr: + - *neon-stable + assert_instr: ['{type[3]}'] + safety: safe + big_endian_inverse: true + types: + - ['vget_high_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 1)])'] + - ['vget_low_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 0)])'] + compose: + - Identifier: ['{type[4]}', UnsafeSymbol] + + - name: "vcombine{neon_type[0].noq}" + doc: Join two smaller vectors into a single larger vector + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + assert_instr: [mov] + safety: safe + big_endian_inverse: true + types: + - [float64x1_t, float64x2_t, '[0, 1]'] + compose: + - FnCall: [simd_shuffle!, [a, b, '{type[2]}']] + + - name: "vgetq_lane_{type[1]}" + doc: "Duplicate vector element to vector or scalar" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-stable + - FnCall: [rustc_legacy_const_generics, ['1']] + assert_instr: [['nop', 'IMM5 = 0']] + safety: safe + big_endian_inverse: true + static_defs: ["const IMM5: i32"] + types: + - ['float64x2_t', 'f64'] + compose: + - FnCall: [static_assert_uimm_bits!, [IMM5, "1"]] + - FnCall: ['simd_extract!', [a, 'IMM5 as u32'], [] , true] diff --git a/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index 56b2252c9ef0c..e8682cf45feb8 100644 --- a/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -104,6 +104,10 @@ aarch64-crc-stable: &aarch64-crc-stable neon-unstable-f16: &neon-unstable-f16 FnCall: [unstable, ['feature = "stdarch_neon_f16"', 'issue = "136306"']] +# all(target_endian = "little") +all-neon-target-aarch64-arm64ec-little-endian: &all-neon-target-aarch64-arm64ec-little-endian + FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}, 'target_endian = "little"']] + intrinsics: - name: "vand{neon_type.no}" doc: Vector bitwise and @@ -502,11 +506,11 @@ intrinsics: - ['h_f16', 'f16'] compose: - FnCall: - - simd_extract! + - 'vget_lane_{type[1]}' - - FnCall: - "vabs_{type[1]}" - - FnCall: ["vdup_n_{type[1]}", [a]] - - 0 + - - 0 - name: "vcgt{neon_type[0].no}" doc: "Compare signed greater than" @@ -1438,6 +1442,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32; 8]'] - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32; 16]'] @@ -1462,6 +1467,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32; 16]'] - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32; 8]'] @@ -1486,6 +1492,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32; 4]'] - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32; 8]'] @@ -1510,6 +1517,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32; 8]'] - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32; 4]'] @@ -1537,6 +1545,7 @@ intrinsics: - *target-not-arm64ec static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_laneq_f16, float16x8_t, float16x8_t, '3', '[N as u32; 8]'] - [_laneq_f16, float16x8_t, float16x4_t, '3', '[N as u32; 4]'] @@ -1577,6 +1586,7 @@ intrinsics: - *target-not-arm64ec static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [_lane_f16, float16x4_t, float16x4_t, '2', '[N as u32; 4]'] - [q_lane_f16, float16x4_t, float16x8_t, '2', '[N as u32; 8]'] @@ -1598,6 +1608,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [_lane_s32, int32x2_t, int32x2_t, '1', '[N as u32, N as u32]'] - [q_lane_s32, int32x2_t, int32x4_t, '1', '[N as u32, N as u32, N as u32, N as u32]'] @@ -1622,6 +1633,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - [_laneq_s32, int32x4_t, int32x2_t, '2', '[N as u32, N as u32]'] @@ -1646,6 +1658,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_laneq_s64, int64x2_t, '1', '[N as u32, N as u32]'] - [q_laneq_u64, uint64x2_t, '1', '[N as u32, N as u32]'] @@ -1666,6 +1679,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - [q_lane_s64, int64x1_t, int64x2_t] - [q_lane_u64, uint64x1_t, uint64x2_t] @@ -1712,13 +1726,13 @@ intrinsics: compose: - FnCall: [static_assert_uimm_bits!, [N, 1]] - FnCall: - - "transmute{type[3]}" - - - FnCall: [simd_extract!, [a, 'N as u32']] + - "transmute" + - - FnCall: ['vget{neon_type[1].lane_nox}', [a], [N]] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 7']]}]] @@ -1728,21 +1742,22 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [int16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [uint8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [uint16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [poly8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] - - [poly16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - int8x8_t + - int16x8_t + - uint8x8_t + - uint16x8_t + - poly8x8_t + - poly16x8_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 3]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 15']]}]] @@ -1752,18 +1767,19 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] - - [uint8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] - - [poly8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] + - int8x16_t + - uint8x16_t + - poly8x16_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 4]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7, N as u32 + 8, N as u32 + 9, N as u32 + 10, N as u32 + 11, N as u32 + 12, N as u32 + 13, N as u32 + 14, N as u32 + 15]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 3']]}]] @@ -1773,22 +1789,23 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int16x4_t, 'static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [int32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [uint16x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [uint32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [poly16x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] - - [float32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - int16x4_t + - int32x4_t + - uint16x4_t + - uint32x4_t + - poly16x4_t + - float32x4_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 2]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 3']]}]] @@ -1800,15 +1817,17 @@ intrinsics: - *target-not-arm64ec static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [float16x4_t, ' static_assert_uimm_bits!(N, 2); unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - float16x4_t compose: - - Identifier: ["{type[1]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 2]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 7']]}]] @@ -1820,17 +1839,19 @@ intrinsics: - *target-not-arm64ec static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [float16x8_t, ' static_assert_uimm_bits!(N, 3); unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - float16x8_t compose: - - Identifier: ["{type[1]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 3]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1, N as u32 + 2, N as u32 + 3, N as u32 + 4, N as u32 + 5, N as u32 + 6, N as u32 + 7]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vext.8"', 'N = 1']]}]] @@ -1840,18 +1861,19 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] - - [uint32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] - - [float32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - int32x2_t + - uint32x2_t + - float32x2_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']] - - name: "vext{neon_type[0].no}" + - name: "vext{neon_type.no}" doc: "Extract vector from pair of vectors" - arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] - return_type: "{neon_type[0]}" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmov, 'N = 1']]}]] @@ -1861,12 +1883,13 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const N: i32'] safety: safe + big_endian_inverse: true types: - - [int64x2_t, 'static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] - - [uint64x2_t, 'static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - int64x2_t + - uint64x2_t compose: - - Identifier: ["{type[1]}", Symbol] - - Identifier: ["{type[2]}", Symbol] + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: [simd_shuffle!, [a, b, '[N as u32, N as u32 + 1]']] - name: "vmla{neon_type[0].no}" doc: "Multiply-add to accumulator" @@ -1986,17 +2009,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [int64x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [int32x4_t, int16x4_t, int16x4_t, '2'] + - [int32x4_t, int16x4_t, int16x8_t, '3'] + - [int64x2_t, int32x2_t, int32x2_t, '1'] + - [int64x2_t, int32x2_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmlal_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlal_lane{neon_type[2].no}" doc: "Vector widening multiply accumulate with scalar" @@ -2012,17 +2035,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x2_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x2_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x4_t, uint16x4_t, '2'] + - [uint32x4_t, uint16x4_t, uint16x8_t, '3'] + - [uint64x2_t, uint32x2_t, uint32x2_t, '1'] + - [uint64x2_t, uint32x2_t, uint32x4_t, '2'] compose: - - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmlal_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, '{type[5]}']] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlal_{neon_type[1]}" doc: "Unsigned multiply-add long" @@ -2141,15 +2164,15 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x4_t, int16x4_t, '2'] + - [int32x4_t, int16x4_t, int16x8_t, '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmlsl_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlsl_lane{neon_type[2].no}" doc: "Vector widening multiply subtract with scalar" @@ -2165,15 +2188,15 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int64x2_t, int32x2_t, int32x2_t, '[LANE as u32, LANE as u32]', '1'] - - [int64x2_t, int32x2_t, int32x4_t, '[LANE as u32, LANE as u32]', '2'] + - [int64x2_t, int32x2_t, int32x2_t, '1'] + - [int64x2_t, int32x2_t, int32x4_t, '2'] compose: - - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmlsl_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlsl_lane{neon_type[2].no}" doc: "Vector widening multiply subtract with scalar" @@ -2189,17 +2212,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x4_t, uint16x4_t, '2'] + - [uint32x4_t, uint16x4_t, uint16x8_t, '3'] + - [uint64x2_t, uint32x2_t, uint32x2_t, '1'] + - [uint64x2_t, uint32x2_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmlsl_{neon_type[1]}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup_lane{neon_type[2].no}', [c], [LANE]] - name: "vmlsl_{neon_type[1]}" doc: "Unsigned multiply-subtract long" @@ -2679,7 +2702,6 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable - big_endian_inverse: false safety: unsafe: [neon] types: @@ -2738,7 +2760,6 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable - big_endian_inverse: false safety: unsafe: [neon] types: @@ -2976,7 +2997,6 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable - big_endian_inverse: false safety: unsafe: [neon] types: @@ -3007,7 +3027,6 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable - big_endian_inverse: false safety: unsafe: [neon] types: @@ -3104,7 +3123,6 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: - "const LANE: i32" - big_endian_inverse: false safety: unsafe: [neon] types: @@ -4093,7 +4111,6 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] - big_endian_inverse: false safety: unsafe: [neon] types: @@ -4124,7 +4141,6 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable - big_endian_inverse: false safety: unsafe: [neon] types: @@ -4488,7 +4504,6 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld4]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable - big_endian_inverse: false safety: unsafe: [neon] types: @@ -4610,7 +4625,6 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable static_defs: ["const LANE: i32"] - big_endian_inverse: false safety: unsafe: [neon] types: @@ -5368,7 +5382,7 @@ intrinsics: unsafe: [neon] types: - [f16, float16x4x2_t, '2', float16x4_t, '2'] - - [f16, float16x8x2_t, '1', float16x8_t, '2'] + - [f16, float16x8x2_t, '3', float16x8_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] - LLVMLink: @@ -5642,27 +5656,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x3_t, int8x8_t] - - [i16, int16x4x3_t, int16x4_t] - - [i32, int32x2x3_t, int32x2_t] - - [i8, int8x16x3_t, int8x16_t] - - [i16, int16x8x3_t, int16x8_t] - - [i32, int32x4x3_t, int32x4_t] - - [f32, float32x2x3_t, float32x2_t] - - [f32, float32x4x3_t, float32x4_t] + - [i8, int8x8x3_t, "8"] + - [i16, int16x4x3_t, "4"] + - [i32, int32x2x3_t, "2"] + - [i8, int8x16x3_t, "16"] + - [i16, int16x8x3_t, "8"] + - [i32, int32x4x3_t, "4"] + - [f32, float32x2x3_t, "2"] + - [f32, float32x4x3_t, "4"] compose: - - LLVMLink: - name: 'vst3.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] - + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -6148,10 +6151,11 @@ intrinsics: - *neon-i8mm - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot]]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [usdot]]}]] - *neon-unstable-i8mm - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int32x2_t, uint8x8_t, int8x8_t] - [int32x4_t, uint8x16_t, int8x16_t] @@ -6164,10 +6168,10 @@ intrinsics: - link: "llvm.arm.neon.usdot.v{neon_type[0].lane}i32.v{neon_type[1].lane}i8" arch: arm - - name: "vusdot{type[0]}" + - name: "vusdot{neon_type[0].lane_nox}" doc: "Dot product index form with unsigned and signed integers" - arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}", "c: int8x8_t"] - return_type: "{neon_type[1]}" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: int8x8_t"] + return_type: "{neon_type[0]}" attr: - *neon-i8mm - *neon-v8 @@ -6177,22 +6181,19 @@ intrinsics: - *neon-unstable-i8mm - *neon-cfg-arm-unstable static_defs: ["const LANE: i32"] - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. safety: safe types: - - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]',''] - - ['q_lane_s32', int32x4_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [int32x2_t, uint8x8_t, ''] + - [int32x4_t, uint8x16_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - Let: - c - - int32x2_t - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_s32_s8', [c]] + - FnCall: ['vreinterpret_s32_s8', [c]] - Let: - c - - "{type[1]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] - - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: [transmute, [c]]}]] #'vreinterpret{type[4]}_s8_s32' + - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]] + - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[2]}_s8_s32', [c]]}]] - name: "vsudot{neon_type[0].lane_nox}" doc: "Dot product index form with signed and unsigned integers" @@ -6202,30 +6203,27 @@ intrinsics: - *neon-i8mm - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 0']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-i8mm - *neon-cfg-arm-unstable static_defs: ["const LANE: i32"] - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. safety: safe types: - - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t,''] - - [int32x4_t, int8x16_t, uint8x8_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t,'q'] + - [int32x2_t, int8x8_t, uint8x8_t, uint32x2_t, ''] + - [int32x4_t, int8x16_t, uint8x8_t, uint32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - Let: - c - - uint32x2_t - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_u32_u8', [c]] + - FnCall: ['vreinterpret_u32_u8', [c]] - Let: - c - - "{type[4]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ['vdup{neon_type[3].lane_nox}', [c], [LANE]] - FnCall: - "vusdot{neon_type[0].no}" - - a - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret{type[5]}_u8_u32', [c]] + - FnCall: ['vreinterpret{type[4]}_u8_u32', [c]] - b - name: "vmul{neon_type[1].no}" @@ -6307,20 +6305,20 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x4_t, int16x4_t, '2'] + - [int16x8_t, int16x4_t, '2'] + - [int32x2_t, int32x2_t, '1'] + - [int32x4_t, int32x2_t, '1'] + - [uint16x4_t, uint16x4_t, '2'] + - [uint16x8_t, uint16x4_t, '2'] + - [uint32x2_t, uint32x2_t, '1'] + - [uint32x4_t, uint32x2_t, '1'] compose: - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [b, b, "{type[3]}"]] + - FnCall: ["vdup{neon_type[0].lane_nox}", [b], [LANE]] - name: "vmul{neon_type[0].lane_nox}" @@ -6339,14 +6337,14 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [float16x4_t, float16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [float16x8_t, float16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [float16x4_t, float16x4_t, '2'] + - [float16x8_t, float16x4_t, '2'] compose: - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [v, v, "{type[3]}"]] + - FnCall: ["vdup{neon_type[0].lane_nox}", [v], [LANE]] - name: "vmul{neon_type[0].laneq_nox}" @@ -6363,20 +6361,20 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x4_t, int16x8_t, '3'] + - [int16x8_t, int16x8_t, '3'] + - [int32x2_t, int32x4_t, '2'] + - [int32x4_t, int32x4_t, '2'] + - [uint16x4_t, uint16x8_t, '3'] + - [uint16x8_t, uint16x8_t, '3'] + - [uint32x2_t, uint32x4_t, '2'] + - [uint32x4_t, uint32x4_t, '2'] compose: - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [b, b, "{type[3]}"]] + - FnCall: ["vdup{neon_type[0].laneq_nox}", [b], [LANE]] - name: "vmull{neon_type[1].no}" doc: Signed multiply long @@ -6807,23 +6805,22 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vsubhn"]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [subhn2]]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [subhn2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] - - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + - [int8x8_t, int16x8_t, int8x16_t] + - [int16x4_t, int32x4_t, int16x8_t] + - [int32x2_t, int64x2_t, int32x4_t] + - [uint8x8_t, uint16x8_t, uint8x16_t] + - [uint16x4_t, uint32x4_t, uint16x8_t] + - [uint32x2_t, uint64x2_t, uint32x4_t] compose: - Let: - d - - "{neon_type[0]}" - FnCall: ["vsubhn{neon_type[1].noq}", [b, c]] - - FnCall: [simd_shuffle!, [a, d, "{type[3]}"]] + - FnCall: ['vcombine_{neon_type[0]}', [a, d]] - name: "vhsub{neon_type[1].no}" doc: "Signed halving subtract" @@ -6977,7 +6974,6 @@ intrinsics: doc: "Dot product index form with unsigned and signed integers" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. attr: - *neon-v8 - *neon-i8mm @@ -6988,14 +6984,13 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]',''] - - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [int32x2_t, uint8x8_t, int8x16_t, ''] + - [int32x4_t, uint8x16_t, int8x16_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}] - - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] - - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]] - #- FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] + - Let: [c, {FnCall: [vreinterpretq_s32_s8, [c]]}] + - Let: [c, {FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]]}] + - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[3]}_s8_s32', [c]]}]] - name: "vsudot{neon_type[0].laneq_nox}" doc: "Dot product index form with signed and unsigned integers" @@ -7005,28 +7000,26 @@ intrinsics: - *neon-v8 - *neon-i8mm - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 1']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] static_defs: ["const LANE: i32"] safety: safe types: - - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t] - - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] + - [int32x2_t, int8x8_t, uint8x16_t, uint32x2_t, ''] + - [int32x4_t, int8x16_t, uint8x16_t, uint32x4_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - Let: - c - - uint32x4_t - - FnCall: [transmute, [c]] + - FnCall: [vreinterpretq_u32_u8, [c]] - Let: - c - - "{type[4]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ['vdup{neon_type[3].laneq_nox}', [c], [LANE]] - FnCall: - "vusdot{neon_type[0].no}" - - a - - FnCall: [transmute, [c]] + - FnCall: ['vreinterpret{type[4]}_u8_u32', [c]] - b - name: "vdot{neon_type[0].laneq_nox}" @@ -7034,7 +7027,6 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" static_defs: ["const LANE: i32"] - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. attr: - *neon-v8 - FnCall: [target_feature, ['enable = "neon,dotprod"']] @@ -7044,32 +7036,27 @@ intrinsics: - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] safety: safe types: - - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', ''] - - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [int32x2_t, int8x8_t, int8x16_t, ''] + - [int32x4_t, int8x16_t, int8x16_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - Let: - c - - "{neon_type[3]}" - - FnCall: [transmute, [c]] - #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] + - FnCall: [vreinterpretq_s32_s8, [c]] - Let: - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]] - FnCall: - "vdot{neon_type[0].no}" - - a - b - - FnCall: [transmute, [c]] - #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + - FnCall: ['vreinterpret{type[3]}_s8_s32', [c]] - name: "vdot{neon_type[0].laneq_nox}" doc: Dot product arithmetic (indexed) arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" static_defs: ["const LANE: i32"] - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. attr: - *neon-v8 - FnCall: [target_feature, ['enable = "neon,dotprod"']] @@ -7079,25 +7066,21 @@ intrinsics: - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] safety: safe types: - - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]',''] - - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [uint32x2_t, uint8x8_t, uint8x16_t, ''] + - [uint32x4_t, uint8x16_t, uint8x16_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - Let: - c - - "{neon_type[3]}" - - FnCall: [transmute, [c]] - #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] + - FnCall: ['vreinterpretq_u32_u8', [c]] - Let: - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup{neon_type[0].laneq_nox}', [c], [LANE]] - FnCall: - "vdot{neon_type[0].no}" - - a - b - - FnCall: [transmute, [c]] - #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + - FnCall: ['vreinterpret{type[3]}_u8_u32', [c]] - name: "vdot{neon_type[0].no}" doc: Dot product arithmetic (vector) @@ -7111,6 +7094,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int32x2_t, int8x8_t] - [int32x4_t, int8x16_t] @@ -7135,6 +7119,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [uint32x2_t, uint8x8_t] - [uint32x4_t, uint8x16_t] @@ -7160,26 +7145,23 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] - *neon-cfg-arm-unstable - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. safety: safe types: - - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]',''] - - [int32x4_t, int8x16_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [int32x2_t, int8x8_t, int8x8_t, ''] + - [int32x4_t, int8x16_t, int8x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - Let: - c - - "{neon_type[3]}" - - FnCall: [transmute, [c]] + - FnCall: ['vreinterpret_s32_s8', [c]] - Let: - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]] - FnCall: - "vdot{neon_type[0].no}" - - a - b - - FnCall: [transmute, [c]] + - FnCall: ['vreinterpret{type[3]}_s8_s32', [c]] - name: "vdot{neon_type[0].lane_nox}" doc: Dot product arithmetic (indexed) @@ -7195,25 +7177,22 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] - *neon-cfg-arm-unstable safety: safe - big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. types: - - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]',''] - - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + - [uint32x2_t, uint8x8_t, uint8x8_t, ''] + - [uint32x4_t, uint8x16_t, uint8x8_t, 'q'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '1']] - Let: - c - - "{neon_type[3]}" - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret_{neon_type[0]}_{neon_type[1]}', [c]] + - FnCall: ['vreinterpret_u32_u8', [c]] - Let: - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: ['vdup{neon_type[0].lane_nox}', [c], [LANE]] - FnCall: - "vdot{neon_type[0].no}" - - a - b - - FnCall: [transmute, [c]] #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + - FnCall: ['vreinterpret{type[3]}_u8_u32', [c]] - name: "vmax{neon_type.no}" doc: Maximum (vector) @@ -7514,6 +7493,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - float32x2_t compose: @@ -7538,6 +7518,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - float16x4_t compose: @@ -7607,7 +7588,7 @@ intrinsics: - [int16x4_t, int16x4_t, int32x4_t, '[N as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [N, '2']] - - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vdup{neon_type[0].lane_nox}', [b], [N]]}] - FnCall: [vqdmull_s16, [a, b]] - name: "vqdmull_lane_s32" @@ -7624,10 +7605,10 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int32x2_t, int32x2_t, int64x2_t, '[N as u32; 2]'] + - [int32x2_t, int32x2_t, int64x2_t] compose: - FnCall: [static_assert_uimm_bits!, [N, '1']] - - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [b, {FnCall: ['vdup{neon_type[0].lane_nox}', [b], [N]]}] - FnCall: [vqdmull_s32, [a, b]] - name: "vqdmlal{neon_type[1].noq}" @@ -7671,7 +7652,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlal, N = 2]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-not-arm-stable - *neon-cfg-arm-unstable @@ -7690,7 +7671,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlal, N = 1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-not-arm-stable - *neon-cfg-arm-unstable @@ -7743,7 +7724,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlsl, N = 2]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-not-arm-stable - *neon-cfg-arm-unstable @@ -7762,7 +7743,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlsl, N = 1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-not-arm-stable - *neon-cfg-arm-unstable @@ -8509,32 +8490,46 @@ intrinsics: - *neon-cfg-arm-unstable safety: safe types: - - [poly64x1_t, int32x2_t] - - [poly64x1_t, uint32x2_t] - - [poly64x2_t, int32x4_t] - - [poly64x2_t, uint32x4_t] - [p128, int64x2_t] - [p128, uint64x2_t] - [p128, poly64x2_t] - - [poly8x16_t, p128] - [p128, int8x16_t] - [p128, uint8x16_t] - [p128, poly8x16_t] + - [poly64x2_t, p128] + - [p128, int32x4_t] + - [p128, uint32x4_t] + - [p128, int16x8_t] + - [p128, uint16x8_t] + - [p128, poly16x8_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-not-arm-stable + - *neon-cfg-arm-unstable + safety: safe + types: + - [poly64x1_t, int32x2_t] + - [poly64x1_t, uint32x2_t] + - [poly8x16_t, p128] - [int32x2_t, poly64x1_t] - [uint32x2_t, poly64x1_t] - [int32x4_t, poly64x2_t] - [uint32x4_t, poly64x2_t] - [int64x2_t, p128] - [uint64x2_t, p128] - - [poly64x2_t, p128] - [poly64x1_t, int16x4_t] - [poly64x1_t, uint16x4_t] - [poly64x1_t, poly16x4_t] - - [poly64x2_t, int16x8_t] - - [poly64x2_t, uint16x8_t] - [poly64x2_t, poly16x8_t] - - [p128, int32x4_t] - - [p128, uint32x4_t] - [poly16x4_t, poly64x1_t] - [int16x4_t, poly64x1_t] - [uint16x4_t, poly64x1_t] @@ -8546,12 +8541,7 @@ intrinsics: - [poly64x1_t, int8x8_t] - [poly64x1_t, uint8x8_t] - [poly64x1_t, poly8x8_t] - - [poly64x2_t, int8x16_t] - - [poly64x2_t, uint8x16_t] - [poly64x2_t, poly8x16_t] - - [p128, int16x8_t] - - [p128, uint16x8_t] - - [p128, poly16x8_t] - [poly8x8_t, poly64x1_t] - [int8x8_t, poly64x1_t] - [uint8x8_t, poly64x1_t] @@ -8563,53 +8553,12 @@ intrinsics: - [poly16x8_t, p128] - [int8x16_t, p128] - [uint8x16_t, p128] - compose: - - FnCall: [transmute, [a]] - - - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" - doc: Vector reinterpret cast operation - arguments: ["a: {type[0]}"] - return_type: "{type[1]}" - attr: - - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - - *neon-not-arm-stable - - *neon-cfg-arm-unstable - safety: safe - types: - - [uint8x8_t, int8x8_t] - - [poly8x8_t, int8x8_t] - - [poly16x4_t, int16x4_t] - - [uint16x4_t, int16x4_t] - - [uint32x2_t, int32x2_t] - - [uint64x1_t, int64x1_t] - - [uint8x16_t, int8x16_t] - - [poly8x16_t, int8x16_t] - - [poly16x8_t, int16x8_t] - - [uint16x8_t, int16x8_t] - - [uint32x4_t, int32x4_t] - - [uint64x2_t, int64x2_t] - - [poly8x8_t, uint8x8_t] - - [int8x8_t, uint8x8_t] - - [poly16x4_t, uint16x4_t] - - [int16x4_t, uint16x4_t] - - [int32x2_t, uint32x2_t] - - [int64x1_t, uint64x1_t] - - [poly8x16_t, uint8x16_t] - - [int8x16_t, uint8x16_t] - - [poly16x8_t, uint16x8_t] - - [int16x8_t, uint16x8_t] - - [int32x4_t, uint32x4_t] - - [int64x2_t, uint64x2_t] - - [int8x8_t, poly8x8_t] - - [uint8x8_t, poly8x8_t] - - [int16x4_t, poly16x4_t] - - [uint16x4_t, poly16x4_t] - - [int8x16_t, poly8x16_t] - - [uint8x16_t, poly8x16_t] - - [int16x8_t, poly16x8_t] - - [uint16x8_t, poly16x8_t] + - [poly64x2_t, int32x4_t] + - [poly64x2_t, uint32x4_t] + - [poly64x2_t, int16x8_t] + - [poly64x2_t, uint16x8_t] + - [poly64x2_t, int8x16_t] + - [poly64x2_t, uint8x16_t] - [int16x4_t, int8x8_t] - [uint16x4_t, int8x8_t] - [poly16x4_t, int8x8_t] @@ -8760,19 +8709,15 @@ intrinsics: - [uint8x16_t, uint64x2_t] - [float32x2_t, int8x8_t] - [float32x2_t, int16x4_t] - - [float32x2_t, int32x2_t] - [float32x2_t, int64x1_t] - [float32x4_t, int8x16_t] - [float32x4_t, int16x8_t] - - [float32x4_t, int32x4_t] - [float32x4_t, int64x2_t] - [float32x2_t, uint8x8_t] - [float32x2_t, uint16x4_t] - - [float32x2_t, uint32x2_t] - [float32x2_t, uint64x1_t] - [float32x4_t, uint8x16_t] - [float32x4_t, uint16x8_t] - - [float32x4_t, uint32x4_t] - [float32x4_t, uint64x2_t] - [float32x2_t, poly8x8_t] - [float32x2_t, poly16x4_t] @@ -8781,19 +8726,15 @@ intrinsics: - [float32x4_t, p128] - [int8x8_t, float32x2_t] - [int16x4_t, float32x2_t] - - [int32x2_t, float32x2_t] - [int64x1_t, float32x2_t] - [int8x16_t, float32x4_t] - [int16x8_t, float32x4_t] - - [int32x4_t, float32x4_t] - [int64x2_t, float32x4_t] - [uint8x8_t, float32x2_t] - [uint16x4_t, float32x2_t] - - [uint32x2_t, float32x2_t] - [uint64x1_t, float32x2_t] - [uint8x16_t, float32x4_t] - [uint16x8_t, float32x4_t] - - [uint32x4_t, float32x4_t] - [uint64x2_t, float32x4_t] - [poly8x8_t, float32x2_t] - [poly16x4_t, float32x2_t] @@ -8803,6 +8744,60 @@ intrinsics: compose: - FnCall: [transmute, [a]] + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-not-arm-stable + - *neon-cfg-arm-unstable + safety: safe + types: + - [uint8x8_t, int8x8_t] + - [poly8x8_t, int8x8_t] + - [poly16x4_t, int16x4_t] + - [uint16x4_t, int16x4_t] + - [uint32x2_t, int32x2_t] + - [uint64x1_t, int64x1_t] + - [uint8x16_t, int8x16_t] + - [poly8x16_t, int8x16_t] + - [poly16x8_t, int16x8_t] + - [uint16x8_t, int16x8_t] + - [uint32x4_t, int32x4_t] + - [uint64x2_t, int64x2_t] + - [poly8x8_t, uint8x8_t] + - [int8x8_t, uint8x8_t] + - [poly16x4_t, uint16x4_t] + - [int16x4_t, uint16x4_t] + - [int32x2_t, uint32x2_t] + - [int64x1_t, uint64x1_t] + - [poly8x16_t, uint8x16_t] + - [int8x16_t, uint8x16_t] + - [poly16x8_t, uint16x8_t] + - [int16x8_t, uint16x8_t] + - [int32x4_t, uint32x4_t] + - [int64x2_t, uint64x2_t] + - [int8x8_t, poly8x8_t] + - [uint8x8_t, poly8x8_t] + - [int16x4_t, poly16x4_t] + - [uint16x4_t, poly16x4_t] + - [int8x16_t, poly8x16_t] + - [uint8x16_t, poly8x16_t] + - [int16x8_t, poly16x8_t] + - [uint16x8_t, poly16x8_t] + - [float32x2_t, int32x2_t] + - [float32x4_t, int32x4_t] + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + - [int32x2_t, float32x2_t] + - [int32x4_t, float32x4_t] + - [uint32x2_t, float32x2_t] + - [uint32x4_t, float32x4_t] + compose: + - FnCall: [transmute, [a]] - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" doc: Vector reinterpret cast operation @@ -8819,54 +8814,73 @@ intrinsics: types: # non-q - [float32x2_t, float16x4_t] - - [poly16x4_t, float16x4_t] - [poly8x8_t, float16x4_t] - [int8x8_t, float16x4_t] - - [int16x4_t, float16x4_t] - [int32x2_t, float16x4_t] - [int64x1_t, float16x4_t] - [uint8x8_t, float16x4_t] - - [uint16x4_t, float16x4_t] - [uint32x2_t, float16x4_t] - [uint64x1_t, float16x4_t] - [float16x4_t, float32x2_t] - - [float16x4_t, poly16x4_t] - [float16x4_t, poly8x8_t] - [float16x4_t, int8x8_t] - - [float16x4_t, int16x4_t] - [float16x4_t, int32x2_t] - [float16x4_t, int64x1_t] - [float16x4_t, uint8x8_t] - - [float16x4_t, uint16x4_t] - [float16x4_t, uint32x2_t] - [float16x4_t, uint64x1_t] # q - [float32x4_t, float16x8_t] - - [poly16x8_t, float16x8_t] - [poly8x16_t, float16x8_t] - [int8x16_t, float16x8_t] - - [int16x8_t, float16x8_t] - [int32x4_t, float16x8_t] - [int64x2_t, float16x8_t] - [uint8x16_t, float16x8_t] - - [uint16x8_t, float16x8_t] - [uint32x4_t, float16x8_t] - [uint64x2_t, float16x8_t] - [float16x8_t, float32x4_t] - - [float16x8_t, poly16x8_t] - [float16x8_t, poly8x16_t] - [float16x8_t, int8x16_t] - - [float16x8_t, int16x8_t] - [float16x8_t, int32x4_t] - [float16x8_t, int64x2_t] - [float16x8_t, uint8x16_t] - - [float16x8_t, uint16x8_t] - [float16x8_t, uint32x4_t] - [float16x8_t, uint64x2_t] compose: - FnCall: [transmute, [a]] + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-not-arm-stable-fp16 + - *neon-cfg-arm-unstable + - *target-not-arm64ec + safety: safe + types: + # non-q + - [poly16x4_t, float16x4_t] + - [int16x4_t, float16x4_t] + - [uint16x4_t, float16x4_t] + - [float16x4_t, poly16x4_t] + - [float16x4_t, int16x4_t] + - [float16x4_t, uint16x4_t] + # q + - [poly16x8_t, float16x8_t] + - [int16x8_t, float16x8_t] + - [uint16x8_t, float16x8_t] + - [float16x8_t, poly16x8_t] + - [float16x8_t, int16x8_t] + - [float16x8_t, uint16x8_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" doc: Vector reinterpret cast operation arguments: ["a: {type[0]}"] @@ -8903,6 +8917,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - [float16x4_t, "[3, 2, 1, 0]"] - [float16x8_t, "[3, 2, 1, 0, 7, 6, 5, 4]"] @@ -9255,6 +9270,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["i8", int8x8_t, '3'] - ["i16", int16x4_t, '2'] @@ -9295,6 +9311,7 @@ intrinsics: - *target-not-arm64ec static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["f16", float16x4_t, '2'] - ["f16", float16x8_t, '3'] @@ -9316,6 +9333,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["i64", int64x1_t, int64x1_t] - ["u64", uint64x1_t, uint64x1_t] @@ -9337,6 +9355,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["p64", poly64x1_t, poly64x1_t] compose: @@ -9357,6 +9376,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - ["p64", poly64x2_t, poly64x2_t] compose: @@ -9683,6 +9703,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int8x8_t, int8x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] - [int16x4_t, int16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] @@ -9727,6 +9748,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] - [float16x8_t, float16x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] @@ -9756,6 +9778,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] @@ -9785,6 +9808,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int8x16_t, int8x16x2_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]', '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] - [int16x8_t, int16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -9820,6 +9844,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] @@ -9849,6 +9874,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int8x8_t, int8x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] - [int16x4_t, int16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] @@ -9884,6 +9910,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] - [float16x8_t, float16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -9912,6 +9939,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [int8x8_t, int8x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] - [int16x4_t, int16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] @@ -9956,6 +9984,7 @@ intrinsics: - *neon-cfg-arm-unstable - *target-not-arm64ec safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] - [float16x8_t, float16x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] @@ -9985,6 +10014,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [float32x2_t, float32x2x2_t, '[0, 2]', '[1, 3]'] - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] @@ -10918,21 +10948,21 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_u16, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_u16, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2'] + - [_laneq_u16, uint16x4_t, uint16x8_t, '3'] + - [q_lane_u16, uint16x8_t, uint16x4_t, '2'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmla{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmla{type[0]}" doc: "Vector multiply accumulate with scalar" @@ -10948,21 +10978,21 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_u32, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_u32, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s32, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2'] + - [_lane_u32, uint32x2_t, uint32x2_t, '1'] + - [_laneq_u32, uint32x2_t, uint32x4_t, '2'] + - [q_lane_u32, uint32x4_t, uint32x2_t, '1'] + - [q_laneq_u32, uint32x4_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmla{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmla{type[0]}" doc: "Vector multiply accumulate with scalar" @@ -10978,17 +11008,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_f32, float32x4_t, float32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_f32, float32x2_t, float32x2_t, '1'] + - [_laneq_f32, float32x2_t, float32x4_t, '2'] + - [q_lane_f32, float32x4_t, float32x2_t, '1'] + - [q_laneq_f32, float32x4_t, float32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmla{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmls{neon_type[0].N}" doc: "Vector multiply subtract with scalar" @@ -11067,21 +11097,21 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_u16, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_u16, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2'] + - [_laneq_u16, uint16x4_t, uint16x8_t, '3'] + - [q_lane_u16, uint16x8_t, uint16x4_t, '2'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmls{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmls{type[0]}" doc: "Vector multiply subtract with scalar" @@ -11097,21 +11127,21 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_u32, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_u32, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s32, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2'] + - [_lane_u32, uint32x2_t, uint32x2_t, '1'] + - [_laneq_u32, uint32x2_t, uint32x4_t, '2'] + - [q_lane_u32, uint32x4_t, uint32x2_t, '1'] + - [q_laneq_u32, uint32x4_t, uint32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmls{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmls{type[0]}" doc: "Vector multiply subtract with scalar" @@ -11127,17 +11157,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_f32, float32x4_t, float32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_f32, float32x2_t, float32x2_t, '1'] + - [_laneq_f32, float32x2_t, float32x4_t, '2'] + - [q_lane_f32, float32x4_t, float32x2_t, '1'] + - [q_laneq_f32, float32x4_t, float32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - "vmls{neon_type[1].no}" - - a - b - - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - FnCall: ['vdup{type[0]}', [c], [LANE]] - name: "vmul{neon_type[0].N}" doc: "Vector multiply by scalar" @@ -11222,16 +11252,16 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float32x2_t, float32x2_t, '_lane_f32', '1', '[LANE as u32, LANE as u32]'] - - [float32x2_t, float32x4_t, '_laneq_f32', '2', '[LANE as u32, LANE as u32]'] - - [float32x4_t, float32x2_t, 'q_lane_f32', '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [float32x4_t, float32x4_t, 'q_laneq_f32', '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [float32x2_t, float32x2_t, '_lane_f32', '1'] + - [float32x2_t, float32x4_t, '_laneq_f32', '2'] + - [float32x4_t, float32x2_t, 'q_lane_f32', '1'] + - [float32x4_t, float32x4_t, 'q_laneq_f32', '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: - simd_mul - - a - - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + - FnCall: ['vdup{type[2]}', [b], [LANE]] - name: "vqrdmulh{type[0]}" doc: "Vector rounding saturating doubling multiply high by scalar" @@ -11247,17 +11277,17 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, '2'] + - [_laneq_s16, int16x4_t, int16x8_t, '3'] + - [q_lane_s16, int16x8_t, int16x4_t, '2'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3'] + - [_lane_s32, int32x2_t, int32x2_t, '1'] + - [_laneq_s32, int32x2_t, int32x4_t, '2'] + - [q_lane_s32, int32x4_t, int32x2_t, '1'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - - Let: [b, "{neon_type[1]}", {FnCall: [simd_shuffle!, [b, b, '{type[4]}']]}] + - Let: [b, {FnCall: ['vdup{type[0]}', [b], [LANE]]}] - FnCall: ["vqrdmulh{neon_type[1].no}", [a, b]] - name: "vqrdmulh{neon_type[0].N}" @@ -11374,16 +11404,16 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int16x4_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int16x4_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x2_t, int32x2_t, int64x2_t, '1', '[LANE as u32, LANE as u32]'] - - [int32x2_t, int32x4_t, int64x2_t, '2', '[LANE as u32, LANE as u32]'] + - [int16x4_t, int16x4_t, int32x4_t, '2'] + - [int16x4_t, int16x8_t, int32x4_t, '3'] + - [int32x2_t, int32x2_t, int64x2_t, '1'] + - [int32x2_t, int32x4_t, int64x2_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmull_{neon_type[0]}" - - a - - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + - FnCall: ['vdup_lane{neon_type[1].nox}', [b], [LANE]] - name: "vmull_lane{neon_type[1].no}" doc: "Vector long multiply by scalar" @@ -11399,16 +11429,16 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x2_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32]'] - - [uint32x2_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32]'] + - [uint16x4_t, uint16x4_t, uint32x4_t, '2'] + - [uint16x4_t, uint16x8_t, uint32x4_t, '3'] + - [uint32x2_t, uint32x2_t, uint64x2_t, '1'] + - [uint32x2_t, uint32x4_t, uint64x2_t, '2'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: - "vmull_{neon_type[0]}" - - a - - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + - FnCall: ['vdup_lane{neon_type[1].nox}', [b], [LANE]] - name: "vfms{neon_type[0].N}" doc: "Floating-point fused Multiply-subtract to accumulator(vector)" @@ -11478,7 +11508,7 @@ intrinsics: - - a - FnCall: - "vdup{neon_type[0].N}" - - - FnCall: [simd_extract!, [b, 'LANE as u32']] + - - FnCall: ['vget{neon_type[1].lane_nox}', [b], [LANE]] - name: "vrecpe{neon_type.no}" doc: "Unsigned reciprocal estimate" @@ -12504,6 +12534,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - [float32x2_t, float32x4_t, '[0, 1, 2, 3]'] - [poly8x8_t, poly8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] @@ -12531,6 +12562,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - uint8x16_t compose: @@ -12553,6 +12585,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - uint8x16_t compose: @@ -12575,6 +12608,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint8x16_t, "aesmc"] compose: @@ -12597,6 +12631,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint8x16_t, "aesimc"] compose: @@ -12619,6 +12654,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [u32, "sha1h"] compose: @@ -12641,6 +12677,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [u32, "sha1c", "uint32x4_t"] compose: @@ -12663,6 +12700,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [u32, "sha1m", "uint32x4_t"] compose: @@ -12685,6 +12723,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [u32, "sha1p", "uint32x4_t"] compose: @@ -12707,6 +12746,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha1su0"] compose: @@ -12729,6 +12769,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha1su1"] compose: @@ -12751,6 +12792,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha256h"] compose: @@ -12773,6 +12815,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha256h2"] compose: @@ -12795,6 +12838,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha256su0"] compose: @@ -12817,6 +12861,7 @@ intrinsics: - *neon-cfg-arm-unstable - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] safety: safe + big_endian_inverse: true types: - [uint32x4_t, "sha256su1"] compose: @@ -13054,6 +13099,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - int8x8_t - int16x4_t @@ -13078,6 +13124,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - uint8x8_t - uint16x4_t @@ -13102,6 +13149,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - float32x2_t compose: @@ -13124,6 +13172,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - int8x8_t - int16x4_t @@ -13148,6 +13197,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - uint8x8_t - uint16x4_t @@ -13172,6 +13222,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - float32x2_t compose: @@ -13237,14 +13288,14 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[3]}"']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [raddhn2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - [uint8x8_t , uint16x8_t, uint8x16_t, 'vraddhn.i16', int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [uint16x4_t, uint32x4_t, uint16x8_t, 'vraddhn.i32', int32x4_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [uint32x2_t, uint64x2_t, uint32x4_t, 'vraddhn.i64', int64x2_t, '[0, 1, 2, 3]'] + - [uint8x8_t , uint16x8_t, uint8x16_t, 'vraddhn.i16', int16x8_t] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'vraddhn.i32', int32x4_t] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'vraddhn.i64', int64x2_t] compose: - Let: - x @@ -13255,7 +13306,7 @@ intrinsics: - "vraddhn{neon_type[4].noq}" - - FnCall: [transmute, [b]] - FnCall: [transmute, [c]] - - FnCall: ["simd_shuffle!", [a, x, '{type[5]}']] + - FnCall: ['vcombine_{neon_type[0]}', [a, x]] - name: "vraddhn_high{neon_type[1].noq}" doc: "Rounding Add returning High Narrow (high half)." @@ -13264,14 +13315,14 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[3]}"']]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [raddhn2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - [int8x8_t , int16x8_t, int8x16_t, 'vraddhn.i16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - [int16x4_t, int32x4_t, int16x8_t, 'vraddhn.i32', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - [int32x2_t, int64x2_t, int32x4_t, 'vraddhn.i64', '[0, 1, 2, 3]'] + - [int8x8_t , int16x8_t, int8x16_t, 'vraddhn.i16'] + - [int16x4_t, int32x4_t, int16x8_t, 'vraddhn.i32'] + - [int32x2_t, int64x2_t, int32x4_t, 'vraddhn.i64'] compose: - Let: - x @@ -13279,7 +13330,7 @@ intrinsics: - "vraddhn{neon_type[1].noq}" - - b - c - - FnCall: ["simd_shuffle!", [a, x, '{type[4]}']] + - FnCall: ['vcombine_{neon_type[0]}', [a, x]] - name: "vpadd{neon_type.no}" doc: "Add pairwise." @@ -13292,6 +13343,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - int8x8_t - int16x4_t @@ -14142,6 +14194,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [nop] safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x8_t] compose: @@ -14159,6 +14212,7 @@ intrinsics: - *target-not-arm64ec assert_instr: [nop] safety: safe + big_endian_inverse: true types: - [float16x4_t, float16x8_t, 'low', "[0, 1, 2, 3]"] - [float16x4_t, float16x8_t, 'high', "[4, 5, 6, 7]"] @@ -14179,6 +14233,7 @@ intrinsics: - *target-not-arm64ec static_defs: ['const LANE: i32'] safety: safe + big_endian_inverse: true types: - [float16x4_t, f16, '_lane_f16', '2'] - [float16x8_t, f16, 'q_lane_f16', '3'] @@ -14333,7 +14388,6 @@ intrinsics: doc: "Load one single-element structure and Replicate to all lanes (of one register)." arguments: ["ptr: {type[1]}"] return_type: "{neon_type[2]}" - big_endian_inverse: false attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['"{type[3]}"']] } ]] @@ -14489,26 +14543,26 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['{type[3]}']] } ]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['{type[4]}']]}] ] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - ['vaddl_high_s8', 'int8x16_t', 'int16x8_t', 'vaddl', 'saddl2', 'int8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddl_high_s16', 'int16x8_t', 'int32x4_t', 'vaddl', 'saddl2', 'int16x4_t', '[4, 5, 6, 7]'] - - ['vaddl_high_s32', 'int32x4_t', 'int64x2_t', 'vaddl', 'saddl2', 'int32x2_t', '[2, 3]'] - - ['vaddl_high_u8', 'uint8x16_t', 'uint16x8_t', 'vaddl', 'uaddl2', 'uint8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddl_high_u16', 'uint16x8_t', 'uint32x4_t', 'vaddl', 'uaddl2', 'uint16x4_t', '[4, 5, 6, 7]'] - - ['vaddl_high_u32', 'uint32x4_t', 'uint64x2_t', 'vaddl', 'uaddl2', 'uint32x2_t', '[2, 3]'] + - ['vaddl_high_s8', 'int8x16_t', 'int16x8_t', 'vaddl', 'saddl2', 'int8x8_t'] + - ['vaddl_high_s16', 'int16x8_t', 'int32x4_t', 'vaddl', 'saddl2', 'int16x4_t'] + - ['vaddl_high_s32', 'int32x4_t', 'int64x2_t', 'vaddl', 'saddl2', 'int32x2_t'] + - ['vaddl_high_u8', 'uint8x16_t', 'uint16x8_t', 'vaddl', 'uaddl2', 'uint8x8_t'] + - ['vaddl_high_u16', 'uint16x8_t', 'uint32x4_t', 'vaddl', 'uaddl2', 'uint16x4_t'] + - ['vaddl_high_u32', 'uint32x4_t', 'uint64x2_t', 'vaddl', 'uaddl2', 'uint32x2_t'] compose: - Let: - a - '{neon_type[5]}' - - FnCall: ['simd_shuffle!', [a, a, '{type[6]}']] + - FnCall: ['vget_high_{neon_type[1]}', [a]] - Let: - b - '{neon_type[5]}' - - FnCall: ['simd_shuffle!', [b, b, '{type[6]}']] + - FnCall: ['vget_high_{neon_type[1]}', [b]] - Let: [a, '{neon_type[2]}', {FnCall: [simd_cast, [a]]}] - Let: [b, '{neon_type[2]}', {FnCall: [simd_cast, [b]]}] - FnCall: [simd_add, [a, b]] @@ -14545,22 +14599,21 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['{type[3]}']] } ]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['{type[4]}']]}] ] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - ['vaddw_high_s8', 'int16x8_t', 'int8x16_t', 'vaddw', 'saddw2', 'int8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddw_high_s16', 'int32x4_t', 'int16x8_t', 'vaddw', 'saddw2', 'int16x4_t', '[4, 5, 6, 7]'] - - ['vaddw_high_s32', 'int64x2_t', 'int32x4_t', 'vaddw', 'saddw2', 'int32x2_t', '[2, 3]'] - - ['vaddw_high_u8', 'uint16x8_t', 'uint8x16_t', 'vaddw', 'uaddw2', 'uint8x8_t', '[8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddw_high_u16', 'uint32x4_t', 'uint16x8_t', 'vaddw', 'uaddw2', 'uint16x4_t', '[4, 5, 6, 7]'] - - ['vaddw_high_u32', 'uint64x2_t', 'uint32x4_t', 'vaddw', 'uaddw2', 'uint32x2_t', '[2, 3]'] + - ['vaddw_high_s8', 'int16x8_t', 'int8x16_t', 'vaddw', 'saddw2', 'int8x8_t'] + - ['vaddw_high_s16', 'int32x4_t', 'int16x8_t', 'vaddw', 'saddw2', 'int16x4_t'] + - ['vaddw_high_s32', 'int64x2_t', 'int32x4_t', 'vaddw', 'saddw2', 'int32x2_t'] + - ['vaddw_high_u8', 'uint16x8_t', 'uint8x16_t', 'vaddw', 'uaddw2', 'uint8x8_t'] + - ['vaddw_high_u16', 'uint32x4_t', 'uint16x8_t', 'vaddw', 'uaddw2', 'uint16x4_t'] + - ['vaddw_high_u32', 'uint64x2_t', 'uint32x4_t', 'vaddw', 'uaddw2', 'uint32x2_t'] compose: - Let: - b - - '{neon_type[5]}' - - FnCall: ['simd_shuffle!', [b, b, '{type[6]}']] + - FnCall: ['vget_high_{neon_type[2]}', [b]] - Let: - b - '{neon_type[1]}' @@ -14603,17 +14656,17 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['vaddhn']] } ]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['addhn2']]}] ] + - FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['addhn2']]}] ] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe types: - - ['vaddhn_high_s16', 'int8x8_t', 'int16x8_t', 'int8x16_t', 'int16x8_t::splat(8)', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddhn_high_s32', 'int16x4_t', 'int32x4_t', 'int16x8_t', 'int32x4_t::splat(16)', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - ['vaddhn_high_s64', 'int32x2_t', 'int64x2_t', 'int32x4_t', 'int64x2_t::splat(32)', '[0, 1, 2, 3]'] - - ['vaddhn_high_u16', 'uint8x8_t', 'uint16x8_t', 'uint8x16_t', 'uint16x8_t::splat(8)', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - - ['vaddhn_high_u32', 'uint16x4_t', 'uint32x4_t', 'uint16x8_t', 'uint32x4_t::splat(16)', '[0, 1, 2, 3, 4, 5, 6, 7]'] - - ['vaddhn_high_u64', 'uint32x2_t', 'uint64x2_t', 'uint32x4_t', 'uint64x2_t::splat(32)', '[0, 1, 2, 3]'] + - ['vaddhn_high_s16', 'int8x8_t', 'int16x8_t', 'int8x16_t', 'int16x8_t::splat(8)'] + - ['vaddhn_high_s32', 'int16x4_t', 'int32x4_t', 'int16x8_t', 'int32x4_t::splat(16)'] + - ['vaddhn_high_s64', 'int32x2_t', 'int64x2_t', 'int32x4_t', 'int64x2_t::splat(32)'] + - ['vaddhn_high_u16', 'uint8x8_t', 'uint16x8_t', 'uint8x16_t', 'uint16x8_t::splat(8)'] + - ['vaddhn_high_u32', 'uint16x4_t', 'uint32x4_t', 'uint16x8_t', 'uint32x4_t::splat(16)'] + - ['vaddhn_high_u64', 'uint32x2_t', 'uint64x2_t', 'uint32x4_t', 'uint64x2_t::splat(32)'] compose: - Let: - x @@ -14626,7 +14679,7 @@ intrinsics: - - a - b - '{type[4]}' - - FnCall: ['simd_shuffle!', [r, x, '{type[5]}']] + - FnCall: ['vcombine_{neon_type[1]}', [r, x]] - name: "{type[0]}" doc: "Vector narrow integer." @@ -14932,6 +14985,7 @@ intrinsics: arguments: ["v: {neon_type[1]}"] return_type: "{type[2]}" safety: safe + big_endian_inverse: true static_defs: ['const IMM5: i32'] attr: - *neon-v7 @@ -14970,6 +15024,7 @@ intrinsics: arguments: ["v: {neon_type[1]}"] return_type: "{type[2]}" safety: safe + big_endian_inverse: true static_defs: ['const IMM5: i32'] attr: - *neon-v7 @@ -15016,11 +15071,13 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - - ['vget_high_s64', 'int64x2_t', 'int64x1_t', 'vmov', 'ext', 'unsafe { int64x1_t([simd_extract!(a, 1)]) }'] - - ['vget_high_u64', 'uint64x2_t', 'uint64x1_t', 'vmov', 'ext', 'unsafe { uint64x1_t([simd_extract!(a, 1)]) }'] + - ['vget_high_s64', 'int64x2_t', 'int64x1_t', 'vmov', 'ext', 'int64x1_t([simd_extract!(a, 1)])'] + - ['vget_high_u64', 'uint64x2_t', 'uint64x1_t', 'vmov', 'ext', 'uint64x1_t([simd_extract!(a, 1)])'] + - ['vget_high_p64', 'poly64x2_t', 'poly64x1_t', 'vmov', 'ext', 'transmute(u64x1::new(simd_extract!(a, 1)))'] compose: - - Identifier: ['{type[5]}', Symbol] + - Identifier: ['{type[5]}', UnsafeSymbol] - name: "{type[0]}" doc: "Duplicate vector element to vector or scalar" @@ -15032,11 +15089,13 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - - ['vget_low_s64', 'int64x2_t', 'int64x1_t', 'unsafe { int64x1_t([simd_extract!(a, 0)]) }'] - - ['vget_low_u64', 'uint64x2_t', 'uint64x1_t', 'unsafe { uint64x1_t([simd_extract!(a, 0)]) }'] + - ['vget_low_s64', 'int64x2_t', 'int64x1_t', 'int64x1_t([simd_extract!(a, 0)])'] + - ['vget_low_u64', 'uint64x2_t', 'uint64x1_t', 'uint64x1_t([simd_extract!(a, 0)])'] + - ['vget_low_p64', 'poly64x2_t', 'poly64x1_t', 'transmute(u64x1::new(simd_extract!(a, 0)))'] compose: - - Identifier: ['{type[3]}', Symbol] + - Identifier: ['{type[3]}', UnsafeSymbol] - name: "{type[0]}" doc: "Duplicate vector element to vector or scalar" @@ -15049,6 +15108,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - ['vget_high_s8', 'int8x16_t', 'int8x8_t', 'vmov', 'ext', '[8, 9, 10, 11, 12, 13, 14, 15]'] - ['vget_high_u8', 'uint8x16_t', 'uint8x8_t', 'vmov', 'ext', '[8, 9, 10, 11, 12, 13, 14, 15]'] @@ -15072,6 +15132,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - ['vget_low_s8', 'int8x16_t', 'int8x8_t', '[0, 1, 2, 3, 4, 5, 6, 7]'] - ['vget_low_u8', 'uint8x16_t', 'uint8x8_t','[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -15224,6 +15285,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: safe + big_endian_inverse: true types: - ['vrev16_s8', 'int8x8_t', 'vrev16.8', 'rev16', '[1, 0, 3, 2, 5, 4, 7, 6]'] - ['vrev16q_s8', 'int8x16_t', 'vrev16.8', 'rev16', '[1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]'] diff --git a/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml b/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml new file mode 100644 index 0000000000000..29dd3a095d7e6 --- /dev/null +++ b/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml @@ -0,0 +1,5201 @@ +arch_cfgs: + - arch_name: aarch64 + target_feature: [sve] + llvm_prefix: llvm.aarch64.sve + +uses_neon_types: true +auto_llvm_sign_conversion: true +generate_load_store_tests: true + +# `#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]` +sve-unstable: &sve-unstable + FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']] + +intrinsics: + - name: svacge[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare greater than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facge] + n_variant_op: op2 + compose: + - LLVMLink: { name: "facge.{sve_type}" } + + - name: svacgt[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare greater than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facgt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "facgt.{sve_type}" } + + - name: svacle[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare less than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facge] + n_variant_op: op2 + compose: + - FnCall: ["svacge_{type}", [$pg, $op2, $op1]] + + - name: svaclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare less than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facgt] + n_variant_op: op2 + compose: + - FnCall: ["svacgt_{type}", [$pg, $op2, $op1]] + + - name: svcadd[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Complex add with rotate + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [90, 270] }] + assert_instr: [[fcadd, "IMM_ROTATION = 90"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: fcadd.{sve_type} + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$pg, $op1, $op2, $IMM_ROTATION]] + + - name: svcmla[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[fcmla, "IMM_ROTATION = 90"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: fcmla.{sve_type} + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$pg, $op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcmla_lane[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[fcmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: fcmla.lane.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.f}add"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}add.{sve_type}" } + + - name: svqsub[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating subtract + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qsub"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsub.x.{sve_type}" } + + - name: svcnt[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count nonzero bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + zeroing_method: { drop: inactive } + assert_instr: [cnt] + compose: + - LLVMLink: { name: "cnt.{sve_type[0]}" } + + - name: svcls[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count leading sign bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i8, u8], [i16, u16], [i32, u32], [i64, u64]] + zeroing_method: { drop: inactive } + assert_instr: [cls] + compose: + - LLVMLink: { name: "cls.{sve_type[0]}" } + + - name: svclz[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count leading zero bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + zeroing_method: { drop: inactive } + assert_instr: [clz] + compose: + - LLVMLink: { name: "clz.{sve_type[0]}" } + + - name: svext{size_literal[1]}[_{type[0]}]{_mxz} + attr: [*sve-unstable] + substitutions: + sign_or_zero: + match_kind: "{type[0]}" + default: Sign + unsigned: Zero + kind_literal: { match_kind: "{type[0]}", default: s, unsigned: u } + doc: "{sign_or_zero}-extend the low {size[1]} bits" + arguments: + ["inactive: {sve_type[0]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + zeroing_method: { drop: inactive } + assert_instr: ["{type_kind[0].su}xt{size_literal[1]}"] + compose: + - LLVMLink: + name: "{type_kind[0].su}xt{size_literal[1]}.{sve_type[0]}" + + - name: svsqrt[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Square root + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { drop: inactive } + assert_instr: [fsqrt] + compose: + - LLVMLink: { name: "fsqrt.{sve_type}" } + + - name: svcmpeq[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmeq, default: cmpeq }] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}cmpeq.{sve_type}" } + + - name: svcmpeq_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + assert_instr: [cmpeq] + n_variant_op: op2 + compose: + - LLVMLink: { name: "cmpeq.wide.{sve_type[0]}" } + + - name: svcmpge[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare greater than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmge, default: cmpge, unsigned: cmphs }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type}" + - default: + LLVMLink: { name: "{type_kind.f}cmpge.{sve_type}" } + unsigned: + LLVMLink: { name: "cmphs.{sve_type}" } + + - name: svcmpge_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare greater than or equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + n_variant_op: op2 + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmpge, unsigned: cmphs }] + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmpge.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmphs.wide.{sve_type[0]}" } + + - name: svcmpgt[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare greater than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmgt, default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type}" + - default: + LLVMLink: { name: "{type_kind.f}cmpgt.{sve_type}" } + unsigned: + LLVMLink: { name: "cmphi.{sve_type}" } + + - name: svcmpgt_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare greater than + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmpgt.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmphi.wide.{sve_type[0]}" } + + - name: svcmple[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare less than or equal to + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmge, default: cmpge, unsigned: cmphs }] + n_variant_op: op2 + compose: + - FnCall: ["svcmpge_{type}", [$pg, $op2, $op1]] + + - name: svcmple_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare less than or equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmple, unsigned: cmpls }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmple.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmpls.wide.{sve_type[0]}" } + + - name: svcmplt[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare less than + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmgt, default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - FnCall: ["svcmpgt_{type}", [$pg, $op2, $op1]] + + - name: svcmplt_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare less than + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmplt, unsigned: cmplo }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmplt.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmplo.wide.{sve_type[0]}" } + + - name: svcmpne[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare not equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmne, default: cmpne }] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}cmpne.{sve_type}" } + + - name: svcmpne_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare not equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: [[[i8, i16, i32], i64]] + assert_instr: [cmpne] + n_variant_op: op2 + compose: + - LLVMLink: { name: "cmpne.wide.{sve_type[0]}" } + + - name: svcmpuo[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare unordered with + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [fcmuo] + n_variant_op: op2 + compose: + - LLVMLink: { name: "fcmpuo.{sve_type}" } + + - name: svcnt{size_literal} + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + return_type: u64 + types: [i8, i16, i32, i64] + assert_instr: + - default: { byte: rdvl, halfword: cnth, default: cntw, doubleword: cntd } + compose: + - FnCall: ["svcnt{size_literal}_pat", [], ["{{ svpattern::SV_ALL }}"]] + + - name: svcnt{size_literal}_pat + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: u64 + assert_instr: + - [rdvl, "PATTERN = {{ svpattern::SV_ALL }}"] + - ["cnt{size_literal}", "PATTERN = {{ svpattern::SV_MUL4 }}"] + types: [i8] + compose: + - LLVMLink: + name: cnt{size_literal} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svcnt{size_literal}_pat + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: u64 + assert_instr: [["cnt{size_literal}", "PATTERN = {{ svpattern::SV_ALL }}"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: cnt{size_literal} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svlen[_{type}] + attr: [*sve-unstable] + doc: Count the number of elements in a full vector + arguments: ["_op: {sve_type}"] + return_type: "u64" + types: [i8, u8, i16, u16, i32, u32, f32, i64, u64, f64] + assert_instr: [{ default: { default: "cnt{size_literal}", byte: rdvl } }] + compose: + - FnCall: ["svcnt{size_literal}", []] + + - name: svdup[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["op: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [mov] + compose: + - LLVMLink: { name: "dup.x.{sve_type}" } + + - name: svdup[_n]_{type}{_mxz} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + assert_instr: [mov] + compose: + - LLVMLink: { name: "dup.{sve_type}" } + + - name: svdup[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["op: bool"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [sbfx, whilelo] + compose: + - LLVMLink: { name: "dup.x.{sve_type}" } + + - name: svdup_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["data: {sve_type[0]}", "index: {type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbl] + compose: + - FnCall: + - svtbl_{type[0]} + - - $data + - FnCall: ["svdup_n_{type[1]}", [$index]] + + - name: svdupq_lane[_{type}] + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["data: {sve_type}", "index: u64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [tbl] + compose: + - LLVMLink: { name: "dupq.lane.{sve_type}" } + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: + - "x0: {type}" + - "x1: {type}" + - "x2: {type}" + - "x3: {type}" + - "x4: {type}" + - "x5: {type}" + - "x6: {type}" + - "x7: {type}" + - "x8: {type}" + - "x9: {type}" + - "x10: {type}" + - "x11: {type}" + - "x12: {type}" + - "x13: {type}" + - "x14: {type}" + - "x15: {type}" + return_type: "{sve_type}" + types: [i8, u8] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: + - "crate::mem::transmute" + - - - $x0 + - $x1 + - $x2 + - $x3 + - $x4 + - $x5 + - $x6 + - $x7 + - $x8 + - $x9 + - $x10 + - $x11 + - $x12 + - $x13 + - $x14 + - $x15 + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b8] + arguments: + - "x0: bool" + - "x1: bool" + - "x2: bool" + - "x3: bool" + - "x4: bool" + - "x5: bool" + - "x6: bool" + - "x7: bool" + - "x8: bool" + - "x9: bool" + - "x10: bool" + - "x11: bool" + - "x12: bool" + - "x13: bool" + - "x14: bool" + - "x15: bool" + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s8 + - - CastAs: [$x0, i8] + - CastAs: [$x1, i8] + - CastAs: [$x2, i8] + - CastAs: [$x3, i8] + - CastAs: [$x4, i8] + - CastAs: [$x5, i8] + - CastAs: [$x6, i8] + - CastAs: [$x7, i8] + - CastAs: [$x8, i8] + - CastAs: [$x9, i8] + - CastAs: [$x10, i8] + - CastAs: [$x11, i8] + - CastAs: [$x12, i8] + - CastAs: [$x13, i8] + - CastAs: [$x14, i8] + - CastAs: [$x15, i8] + - FnCall: + - svcmpne_wide_s8 + - - FnCall: [svptrue_b8, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: + - "x0: {type}" + - "x1: {type}" + - "x2: {type}" + - "x3: {type}" + - "x4: {type}" + - "x5: {type}" + - "x6: {type}" + - "x7: {type}" + return_type: "{sve_type}" + types: [i16, u16] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: + - "crate::mem::transmute" + - - [$x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b16] + arguments: + - "x0: bool" + - "x1: bool" + - "x2: bool" + - "x3: bool" + - "x4: bool" + - "x5: bool" + - "x6: bool" + - "x7: bool" + return_type: svbool_t + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s16 + - - CastAs: [$x0, i16] + - CastAs: [$x1, i16] + - CastAs: [$x2, i16] + - CastAs: [$x3, i16] + - CastAs: [$x4, i16] + - CastAs: [$x5, i16] + - CastAs: [$x6, i16] + - CastAs: [$x7, i16] + - FnCall: + - svcmpne_wide_s16 + - - FnCall: [svptrue_b16, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["x0: {type}", "x1: {type}", "x2: {type}", "x3: {type}"] + return_type: "{sve_type}" + types: [f32, i32, u32] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: ["crate::mem::transmute", [[$x0, $x1, $x2, $x3]]] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b32] + arguments: ["x0: bool", "x1: bool", "x2: bool", "x3: bool"] + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s32 + - - CastAs: [$x0, i32] + - CastAs: [$x1, i32] + - CastAs: [$x2, i32] + - CastAs: [$x3, i32] + - FnCall: + - svcmpne_wide_s32 + - - FnCall: [svptrue_b32, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["x0: {type}", "x1: {type}"] + return_type: "{sve_type}" + types: [f64, i64, u64] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: ["crate::mem::transmute", [[$x0, $x1]]] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b64] + arguments: ["x0: bool", "x1: bool"] + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: [svdupq_n_s64, [CastAs: [$x0, i64], CastAs: [$x1, i64]]] + - FnCall: + - svcmpne_s64 + - - FnCall: [svptrue_b64, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svcreate2[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of two vectors + arguments: ["x0: {sve_type}", "x1: {sve_type}"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create2", [$x0, $x1], [], true] + + - name: svcreate3[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of three vectors + arguments: ["x0: {sve_type}", "x1: {sve_type}", "x2: {sve_type}"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create3", [$x0, $x1, $x2], [], true] + + - name: svcreate4[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of four vectors + arguments: + ["x0: {sve_type}", "x1: {sve_type}", "x2: {sve_type}", "x3: {sve_type}"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create4", [$x0, $x1, $x2, $x3], [], true] + + - name: svundef_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized vector + arguments: [] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized vector + arguments: [] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef2_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of two vectors + arguments: [] + return_type: "{sve_type_x2}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate2_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef2_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of two vectors + arguments: [] + return_type: "{sve_type_x2}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate2_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef3_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of three vectors + arguments: [] + return_type: "{sve_type_x3}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate3_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef3_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of three vectors + arguments: [] + return_type: "{sve_type_x3}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate3_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef4_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of four vectors + arguments: [] + return_type: "{sve_type_x4}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate4_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef4_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of four vectors + arguments: [] + return_type: "{sve_type_x4}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate4_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svindex_{type} + attr: [*sve-unstable] + doc: Create linear series + arguments: ["base: {type}", "step: {type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [index] + compose: + - LLVMLink: { name: "index.{sve_type}" } + + - name: svget2[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of two vectors + arguments: ["tuple: {sve_type_x2}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 1] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svget3[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of three vectors + arguments: ["tuple: {sve_type_x3}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 2] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svget4[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of four vectors + arguments: ["tuple: {sve_type_x4}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 3] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset2[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of two vectors + arguments: ["tuple: {sve_type_x2}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 1] }] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset3[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of three vectors + arguments: ["tuple: {sve_type_x3}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 2] }] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset4[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of four vectors + arguments: ["tuple: {sve_type_x4}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 3] }] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svzip1[_{type}] + attr: [*sve-unstable] + doc: Interleave elements from low halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip1] + compose: + - LLVMLink: { name: "zip1.{sve_type}" } + + - name: svzip1_{type} + attr: [*sve-unstable] + doc: Interleave elements from low halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [zip1] + compose: + - LLVMLink: { name: "zip1.{sve_type}" } + + - name: svzip1q[_{type}] + attr: [*sve-unstable] + doc: Interleave quadwords from low halves of two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip1] + compose: + - LLVMLink: { name: "zip1q.{sve_type}" } + + - name: svzip2[_{type}] + attr: [*sve-unstable] + doc: Interleave elements from high halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip2] + compose: + - LLVMLink: { name: "zip2.{sve_type}" } + + - name: svzip2_{type} + attr: [*sve-unstable] + doc: Interleave elements from high halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [zip2] + compose: + - LLVMLink: { name: "zip2.{sve_type}" } + + - name: svzip2q[_{type}] + attr: [*sve-unstable] + doc: Interleave quadwords from high halves of two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip2] + compose: + - LLVMLink: { name: "zip2q.{sve_type}" } + + - name: svuzp1[_{type}] + attr: [*sve-unstable] + doc: Concatenate even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp1] + compose: + - LLVMLink: { name: "uzp1.{sve_type}" } + + - name: svuzp1_{type} + attr: [*sve-unstable] + doc: Concatenate even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [uzp1] + compose: + - LLVMLink: { name: "uzp1.{sve_type}" } + + - name: svuzp1q[_{type}] + attr: [*sve-unstable] + doc: Concatenate even quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp1] + compose: + - LLVMLink: { name: "uzp1q.{sve_type}" } + + - name: svuzp2[_{type}] + attr: [*sve-unstable] + doc: Concatenate odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp2] + compose: + - LLVMLink: { name: "uzp2.{sve_type}" } + + - name: svuzp2_{type} + attr: [*sve-unstable] + doc: Concatenate odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [uzp2] + compose: + - LLVMLink: { name: "uzp2.{sve_type}" } + + - name: svuzp2q[_{type}] + attr: [*sve-unstable] + doc: Concatenate odd quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp2] + compose: + - LLVMLink: { name: "uzp2q.{sve_type}" } + + - name: svtrn1[_{type}] + attr: [*sve-unstable] + doc: Interleave even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn1] + compose: + - LLVMLink: { name: "trn1.{sve_type}" } + + - name: svtrn1_{type} + attr: [*sve-unstable] + doc: Interleave even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [trn1] + compose: + - LLVMLink: { name: "trn1.{sve_type}" } + + - name: svtrn1q[_{type}] + attr: [*sve-unstable] + doc: Interleave even quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn1] + compose: + - LLVMLink: { name: "trn1q.{sve_type}" } + + - name: svtrn2[_{type}] + attr: [*sve-unstable] + doc: Interleave odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn2] + compose: + - LLVMLink: { name: "trn2.{sve_type}" } + + - name: svtrn2_{type} + attr: [*sve-unstable] + doc: Interleave odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [trn2] + compose: + - LLVMLink: { name: "trn2.{sve_type}" } + + - name: svtrn2q[_{type}] + attr: [*sve-unstable] + doc: Interleave odd quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn2] + compose: + - LLVMLink: { name: "trn2q.{sve_type}" } + + - name: svrev[_{type}] + attr: [*sve-unstable] + doc: Reverse all elements + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [rev] + compose: + - LLVMLink: { name: "llvm.vector.reverse.{sve_type}" } + + - name: svrev_{type} + attr: [*sve-unstable] + doc: Reverse all elements + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [rev] + compose: + - LLVMLink: { name: "llvm.vector.reverse.{sve_type}" } + + - name: svrevb[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse bytes within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revb] + compose: + - LLVMLink: { name: "revb.{sve_type}" } + + - name: svrevh[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse halfwords within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i32, i64, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revh] + compose: + - LLVMLink: { name: "revh.{sve_type}" } + + - name: svrevw[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse words within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i64, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revw] + compose: + - LLVMLink: { name: "revw.{sve_type}" } + + - name: svrbit[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse bits + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [rbit] + compose: + - LLVMLink: { name: "rbit.{sve_type}" } + + - name: svext[_{type}] + attr: [*sve-unstable] + doc: Extract vector from pair of vectors + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, sve_max_elems_type: "{type}" }] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[ext, "IMM3 = 1"]] + compose: + - LLVMLink: + name: ext.{sve_type} + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svsplice[_{type}] + attr: [*sve-unstable] + doc: Splice two vectors under predicate control + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [splice] + compose: + - LLVMLink: { name: "splice.{sve_type}" } + + - name: svinsr[_n_{type}] + attr: [*sve-unstable] + doc: Insert scalar in shifted vector + arguments: ["op1: {sve_type}", "op2: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [insr] + compose: + - LLVMLink: { name: "insr.{sve_type}" } + + - name: svld1[_{type}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1.{sve_type}" } + + - name: svld1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1]}" + + - name: svld1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1]}" + + - name: svld1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svld1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svld1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], i16] + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svld1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], u16] + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svld1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldnt1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnt1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldnt1.{sve_type}" } + + - name: svldnt1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnt1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldnt1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ld1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svld1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ld1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svld1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ld1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ld1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld2[_{type}] + attr: [*sve-unstable] + doc: Load two-element tuples into two vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld2{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld2.sret.{sve_type}" } + + - name: svld2_vnum[_{type}] + attr: [*sve-unstable] + doc: Load two-element tuples into two vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld2{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld2_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld3[_{type}] + attr: [*sve-unstable] + doc: Load three-element tuples into three vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld3{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld3.sret.{sve_type}" } + + - name: svld3_vnum[_{type}] + attr: [*sve-unstable] + doc: Load three-element tuples into three vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld3{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld3_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld4[_{type}] + attr: [*sve-unstable] + doc: Load four-element tuples into four vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld4{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld4.sret.{sve_type}" } + + - name: svld4_vnum[_{type}] + attr: [*sve-unstable] + doc: Load four-element tuples into four vectors + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld4{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld4_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1rq[_{type}] + attr: [*sve-unstable] + doc: Load and replicate 128 bits of data + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1rq{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1rq.{sve_type}" } + + - name: svld1ro[_{type}] + attr: [*sve-unstable] + doc: Load and replicate 256 bits of data + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + target_features: [f64mm] + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1ro{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1ro.{sve_type}" } + + - name: svldnf1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnf1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldnf1.{sve_type}" } + + - name: svldnf1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnf1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldnf1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldnf1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldnf1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnf1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svldnf1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldnf1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnf1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svldnf1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldnf1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnf1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldnf1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldnf1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnf1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldff1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldff1.{sve_type}" } + + - name: svldff1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldff1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldff1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldff1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svldff1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldff1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svldff1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldff1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldff1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1]}" + + - name: svldff1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1]}" + + - name: svldff1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svldff1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svldff1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], i16] + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svldff1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], u16] + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svldff1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + doc: Load {size[2]}-bit data and sign-extend, first-faulting + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svrdffr_z + attr: [*sve-unstable] + doc: Read FFR, returning predicate of succesfully loaded elements + arguments: ["pg: svbool_t"] + return_type: svbool_t + assert_instr: [rdffr] + compose: + - LLVMLink: { name: "rdffr.z" } + + - name: svrdffr + attr: [*sve-unstable] + doc: Read FFR, returning predicate of succesfully loaded elements + arguments: [] + return_type: svbool_t + assert_instr: [rdffr] + compose: + - FnCall: [svrdffr_z, [FnCall: [svptrue_b8, []]]] + + - name: svsetffr + attr: [*sve-unstable] + doc: Initialize the first-fault register to all-true + arguments: [] + assert_instr: [setffr] + compose: + - LLVMLink: { name: "setffr" } + + - name: svwrffr + attr: [*sve-unstable] + doc: Write to the first-fault register + arguments: ["op: svbool_t"] + assert_instr: [wrffr] + compose: + - LLVMLink: { name: "wrffr" } + + - name: svqinc{size_literal[1]}[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - ["{type_kind[0].su}qinc{size_literal[1]}", "IMM_FACTOR = 1"] + compose: + - FnCall: + - "svqinc{size_literal[1]}_pat_n_{type[0]}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqinc{size_literal[1]}_pat[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - - "{type_kind[0].su}qinc{size_literal[1]}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind[0].su}qinc{size_literal[1]}.n{size[0]}" + arguments: ["op: {type[0]}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{type[0]}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqinc{size_literal}[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: [["{type_kind.su}qinc{size_literal}", "IMM_FACTOR = 1"]] + compose: + - FnCall: + - "svqinc{size_literal}_pat_{type}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqinc{size_literal}_pat[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: + - - "{type_kind.su}qinc{size_literal}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind.su}qinc{size_literal}.{sve_type}" + arguments: ["op: {sve_type}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{sve_type}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqdec{size_literal[1]}[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - ["{type_kind[0].su}qdec{size_literal[1]}", "IMM_FACTOR = 1"] + compose: + - FnCall: + - "svqdec{size_literal[1]}_pat_n_{type[0]}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqdec{size_literal[1]}_pat[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - - "{type_kind[0].su}qdec{size_literal[1]}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind[0].su}qdec{size_literal[1]}.n{size[0]}" + arguments: ["op: {type[0]}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{type[0]}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqdec{size_literal}[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: [["{type_kind.su}qdec{size_literal}", "IMM_FACTOR = 1"]] + compose: + - FnCall: + - "svqdec{size_literal}_pat_{type}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqdec{size_literal}_pat[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: + - - "{type_kind.su}qdec{size_literal}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind.su}qdec{size_literal}.{sve_type}" + arguments: ["op: {sve_type}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{sve_type}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svst1[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st1{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st1.{sve_type}" + arguments: + - "data: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: ["{llvm_link}", [$data, $pg, $base]] + + - name: svst1_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $indices]] + + - name: svst1_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $offsets]] + + - name: svst1_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + name: "st1.scatter.scalar.offset.{sve_type[1]}.{sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $bases, $offset]] + + - name: svst1_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svst1_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + - $data + + - name: svst1{size_literal[2]}_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], i32, i16] + - [[i32, u32], u32, u16] + - [[i64, u64], i64, [i16, i32]] + - [[i64, u64], u64, [u16, u32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $indices] + + - name: svst1{size_literal[2]}_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], i32, [i8, i16]] + - [[i32, u32], u32, [u8, u16]] + - [[i64, u64], i64, [i8, i16, i32]] + - [[i64, u64], u64, [u8, u16, u32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $offsets] + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "st1.scatter.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $bases, $offset] + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svst1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svst1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + - $data + + - name: svstnt1[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["stnt1{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "stnt1.{sve_type}" + arguments: + - "data: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: ["{llvm_link}", [$data, $pg, $base]] + + - name: svstnt1_vnum[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate}", "base: *mut {type}", "vnum: i64", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["stnt1{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svstnt1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst1{size_literal[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: Truncate to {size[1]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *mut {type[1]}", "data: {sve_type[0]}"] + types: + - [[i16, i32, i64], i8] + - [[u16, u32, u64], u8] + - [[i32, i64], i16] + - [[u32, u64], u16] + - [i64, i32] + - [u64, u32] + assert_instr: ["st1{size_literal[1]}"] + test: { store: 1 } + compose: + - LLVMLink: + name: "st1.{sve_type[0] as {type[1]}}" + arguments: + - "data: {sve_type[0] as {type[1]}}" + - "pg: {predicate[0]}" + - "ptr: *mut {type[1]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base] + + - name: svst1{size_literal[1]}_vnum[_{type[0]}] + attr: [*sve-unstable] + doc: Truncate to {size[1]} bits and store + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "vnum: i64" + - "data: {sve_type[0]}" + types: + - [[i16, i32, i64], i8] + - [[u16, u32, u64], u8] + - [[i32, i64], i16] + - [[u32, u64], u16] + - [i64, i32] + - [u64, u32] + assert_instr: ["st1{size_literal[1]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst1_vnum[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate}", "base: *mut {type}", "vnum: i64", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st1{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst2[_{type}] + attr: [*sve-unstable] + doc: Store two vectors into two-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x2}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st2{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st2.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget2_{type}", ["$data"], [0]] + - FnCall: ["svget2_{type}", ["$data"], [1]] + - "$pg" + - "$base" + + - name: svst2_vnum[_{type}] + attr: [*sve-unstable] + doc: Store two vectors into two-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st2{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst2_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst3[_{type}] + attr: [*sve-unstable] + doc: Store three vectors into three-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x3}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st3{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st3.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "data2: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget3_{type}", ["$data"], [0]] + - FnCall: ["svget3_{type}", ["$data"], [1]] + - FnCall: ["svget3_{type}", ["$data"], [2]] + - "$pg" + - "$base" + + - name: svst3_vnum[_{type}] + attr: [*sve-unstable] + doc: Store three vectors into three-element tuples + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st3{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst3_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst4[_{type}] + attr: [*sve-unstable] + doc: Store four vectors into four-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x4}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st4{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st4.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "data2: {sve_type}" + - "data3: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget4_{type}", ["$data"], [0]] + - FnCall: ["svget4_{type}", ["$data"], [1]] + - FnCall: ["svget4_{type}", ["$data"], [2]] + - FnCall: ["svget4_{type}", ["$data"], [3]] + - "$pg" + - "$base" + + - name: svst4_vnum[_{type}] + attr: [*sve-unstable] + doc: Store four vectors into four-element tuples + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st4{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst4_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svtbl[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in single-vector table + arguments: ["data: {sve_type[0]}", "indices: {sve_type[1]}"] + return_type: "{sve_type[0]}" + assert_instr: [tbl] + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + compose: + - LLVMLink: { name: "tbl.{sve_type[0]}" } + + - name: svwhilele_{type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While incrementing scalar is less than or equal to + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilele, unsigned: whilels }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilele.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilels.{sve_type[1]}.{type[0]}" } } + + - name: svwhilelt_{type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While incrementing scalar is less than + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilelt, unsigned: whilelo }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilelt.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilelo.{sve_type[1]}.{type[0]}" } } + + - name: svmax[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Maximum + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind}max"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}max.{sve_type}" } + + - name: svmaxnm[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Maximum number + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + assert_instr: [fmaxnm] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}maxnm.{sve_type}" } + + - name: svpfalse[_b] + attr: [*sve-unstable] + doc: Set all predicate elements to false + arguments: [] + return_type: "svbool_t" + # TODO: With current implementation, `pfalse` isn't generated, will need to add intrinsic to + # generate `zeroinitializer` + # assert_instr: [pfalse] + compose: + - FnCall: + - "svdupq_n_b8" + - - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + + - name: svptrue_pat_{type} + attr: [*sve-unstable] + doc: Set predicate elements to true + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [[ptrue, "PATTERN = {{svpattern::SV_ALL}}"]] + compose: + - LLVMLink: + name: ptrue.{sve_type} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svptrue_{type} + attr: [*sve-unstable] + doc: Set predicate elements to true + arguments: [] + return_type: "svbool_t" + types: [b8, b16, b32, b64] + assert_instr: [ptrue] + compose: + - FnCall: ["svptrue_pat_{type}", [], ["{{svpattern::SV_ALL}}"]] + + - name: svptest_any + attr: [*sve-unstable] + doc: Test whether any active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.any.nxv16i1" } + + - name: svptest_first + attr: [*sve-unstable] + doc: Test whether first active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.first.nxv16i1" } + + - name: svptest_last + attr: [*sve-unstable] + doc: Test whether last active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.last.nxv16i1" } + + - name: svpfirst[_b] + attr: [*sve-unstable] + doc: Set the first active predicate element to true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [pfirst] + compose: + - LLVMLink: { name: "pfirst.nxv16i1" } + + - name: svpnext_{type} + attr: [*sve-unstable] + doc: Find next active predicate + arguments: ["pg: {predicate}", "op: {predicate}"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [pnext] + compose: + - LLVMLink: { name: "pnext.{sve_type}" } + + - name: svbrkn[_b]_z + attr: [*sve-unstable] + doc: Propagate break to next partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkn] + compose: + - LLVMLink: { name: "brkn.z.nxv16i1" } + + - name: svbrkb[_b]_z + attr: [*sve-unstable] + doc: Break before first true condition + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkb] + compose: + - LLVMLink: { name: "brkb.z.nxv16i1" } + + - name: svbrkb[_b]_m + attr: [*sve-unstable] + doc: Break before first true condition + arguments: ["inactive: svbool_t", "pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkb] + compose: + - LLVMLink: { name: "brkb.nxv16i1" } + + - name: svbrkpb[_b]_z + attr: [*sve-unstable] + doc: Break before first true condition, propagating from previous partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkpb] + compose: + - LLVMLink: { name: "brkpb.z.nxv16i1" } + + - name: svbrka[_b]_z + attr: [*sve-unstable] + doc: Break after first true condition + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brka] + compose: + - LLVMLink: { name: "brka.z.nxv16i1" } + + - name: svbrka[_b]_m + attr: [*sve-unstable] + doc: Break after first true condition + arguments: ["inactive: svbool_t", "pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brka] + compose: + - LLVMLink: { name: "brka.nxv16i1" } + + - name: svbrkpa[_b]_z + attr: [*sve-unstable] + doc: Break after first true condition, propagating from previous partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkpa] + compose: + - LLVMLink: { name: "brkpa.z.nxv16i1" } + + - name: svsel[_b] + attr: [*sve-unstable] + doc: Conditionally select elements + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [sel] + compose: + - FnCall: ["simd_select", [$pg, $op1, $op2]] + + - name: svsel[_{type}] + attr: [*sve-unstable] + doc: Conditionally select elements + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [sel] + compose: + - FnCall: + - "simd_select" + - - MatchSize: + - "{type}" + - { default: { MethodCall: [$pg, sve_into, []] }, byte: $pg } + - $op1 + - $op2 + - - MatchSize: + - "{type}" + - byte: svbool_t + halfword: svbool8_t + default: svbool4_t + doubleword: svbool2_t + - _ + + - name: svsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + assert_instr: ["{type_kind.f}sub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}sub.{sve_type}" } + + - name: svsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + assert_instr: ["{type_kind.f}subr"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}subr.{sve_type}" } + + - name: svcntp_{predicate} + attr: [*sve-unstable] + doc: Count set predicate bits + arguments: ["pg: {predicate}", "op: {predicate}"] + types: [b8, b16, b32, b64] + return_type: u64 + assert_instr: [cntp] + compose: + - LLVMLink: { name: "cntp.{predicate}" } + + - name: svcompact[_{type}] + attr: [*sve-unstable] + doc: Shuffle active elements of vector to the right and fill with zero + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: [compact] + compose: + - LLVMLink: { name: "compact.{sve_type}" } + + - name: svlasta[_{type}] + attr: [*sve-unstable] + doc: Extract element after last + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [lasta] + compose: + - LLVMLink: { name: "lasta.{sve_type}" } + + - name: svclasta[_{type}] + attr: [*sve-unstable] + doc: Conditionally extract element after last + arguments: ["pg: {predicate}", "fallback: {sve_type}", "data: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clasta] + compose: + - LLVMLink: { name: "clasta.{sve_type}" } + + - name: svclasta[_n_{type}] + attr: [*sve-unstable] + doc: Conditionally extract element after last + arguments: ["pg: {predicate}", "fallback: {type}", "data: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clasta] + compose: + - LLVMLink: { name: "clasta.n.{sve_type}" } + + - name: svlastb[_{type}] + attr: [*sve-unstable] + doc: Extract last element + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [lastb] + compose: + - LLVMLink: { name: "lastb.{sve_type}" } + + - name: svclastb[_{type}] + attr: [*sve-unstable] + doc: Conditionally extract last element + arguments: ["pg: {predicate}", "fallback: {sve_type}", "data: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clastb] + compose: + - LLVMLink: { name: "clastb.{sve_type}" } + + - name: svclastb[_n_{type}] + attr: [*sve-unstable] + doc: Conditionally extract last element + arguments: ["pg: {predicate}", "fallback: {type}", "data: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clastb] + compose: + - LLVMLink: { name: "clastb.n.{sve_type}" } + + - name: svqdecp[_{type}] + attr: [*sve-unstable] + doc: Saturating decrement by active element count + arguments: ["op: {sve_type}", "pg: {predicate}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + assert_instr: ["{type_kind.su}qdecp"] + compose: + - LLVMLink: { name: "{type_kind.su}qdecp.{sve_type}" } + + - name: svqdecp[_n_{type[0]}]_{type[1]} + attr: [*sve-unstable] + doc: Saturating decrement by active element count + arguments: ["op: {type[0]}", "pg: {sve_type[1]}"] + return_type: "{type[0]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: ["{type_kind[0].su}qdecp"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qdecp.n{size[0]}.{sve_type[1]}" } + + - name: svqincp[_{type}] + attr: [*sve-unstable] + doc: Saturating increment by active element count + arguments: ["op: {sve_type}", "pg: {predicate}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + assert_instr: ["{type_kind.su}qincp"] + compose: + - LLVMLink: { name: "{type_kind.su}qincp.{sve_type}" } + + - name: svqincp[_n_{type[0]}]_{type[1]} + attr: [*sve-unstable] + doc: Saturating increment by active element count + arguments: ["op: {type[0]}", "pg: {sve_type[1]}"] + return_type: "{type[0]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: ["{type_kind[0].su}qincp"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qincp.n{size[0]}.{sve_type[1]}" } + + - name: svtmad[_{type}] + attr: [*sve-unstable] + doc: Trigonometric multiply-add coefficient + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: [0, 7] }] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [[ftmad, "IMM3 = 0"]] + compose: + - LLVMLink: + name: "ftmad.x.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: + - "{llvm_link}" + - [op1, op2, IMM3] + + - name: svtsmul[_{type[0]}] + attr: [*sve-unstable] + doc: Trigonometric starting value + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + assert_instr: [ftsmul] + compose: + - LLVMLink: + name: "ftsmul.x.{sve_type[0]}" + + - name: svtssel[_{type[0]}] + attr: [*sve-unstable] + doc: Trigonometric select coefficient + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + assert_instr: [ftssel] + compose: + - LLVMLink: + name: "ftssel.x.{sve_type[0]}" + + - name: svprf{size_literal} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + substitutions: + textual_size: + match_size: "{type}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + arguments: ["pg: {predicate}", "base: *T"] + static_defs: ["const OP: svprfop", T] + types: [b8, b16, b32, b64] + assert_instr: + - ["prf{size_literal}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf.{sve_type}" + arguments: + ["pg: {predicate}", "base: *crate::ffi::c_void", "op: svprfop"] + - FnCall: + - "{llvm_link}" + - - $pg + - CastAs: [$base, "*const crate::ffi::c_void"] + - $OP + + - name: svprf{size_literal}_vnum + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset_vnum: predicated + substitutions: + textual_size: + match_size: "{type}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + arguments: ["pg: {predicate}", "base: *T", "vnum: i64"] + static_defs: ["const OP: svprfop", T] + types: [b8, b16, b32, b64] + assert_instr: + - ["prf{size_literal}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"] + test: { load: 0 } + compose: + - FnCall: + - "svprf{size_literal}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - - $OP + - _ + + - name: svprf{size_literal[1]}_gather_[{type[0]}]{index_or_offset} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + substitutions: + index_or_offset: + { match_size: "{type[1]}", default: "index", byte: "offset" } + indices_or_offsets: + { match_size: "{type[1]}", default: "indices", byte: "offsets" } + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[i32, u32, i64, u64], [i8, i16, i32, i64]] + arguments: + ["pg: {predicate[0]}", "base: *T", "{indices_or_offsets}: {sve_type[0]}"] + static_defs: ["const OP: svprfop", T] + assert_instr: + [["prf{size_literal[1]}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"]] + test: { load: 0 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "prf{size_literal[1]}.gather.{type_kind[0].su}xtw.index.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "base: *crate::ffi::c_void" + - "{indices_or_offsets}: {sve_type[0]}" + - "op: svprfop" + doubleword: + LLVMLink: + name: "prf{size_literal[1]}.gather.index.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "base: *crate::ffi::c_void" + - "{indices_or_offsets}: {sve_type[0]}" + - "op: svprfop" + - FnCall: + - "{llvm_link}" + - - $pg + - CastAs: [$base, "*const crate::ffi::c_void"] + - "${indices_or_offsets}" + - $OP + + - name: svprf{size_literal[1]}_gather[_{type[0]}base] + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + - no_provenance: bases + substitutions: + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[u32, u64], [i8, i16, i32, i64]] + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + static_defs: ["const OP: svprfop"] + assert_instr: [["prf{size_literal[1]}", "OP = {{svprfop::SV_PLDL1KEEP}}"]] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf{size_literal[1]}.gather.scalar.offset.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "op: svprfop" + - FnCall: ["{llvm_link}", [$pg, $bases, 0, $OP]] + + - name: svprf{size_literal[1]}_gather[_{type[0]}base]_{index_or_offset} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + - no_provenance: bases + substitutions: + index_or_offset: + { match_size: "{type[1]}", default: "index", byte: "offset" } + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[u32, u64], [i8, i16, i32, i64]] + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "{index_or_offset}: i64"] + static_defs: ["const OP: svprfop"] + assert_instr: [["prfb", "OP = {{svprfop::SV_PLDL1KEEP}}"]] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf{size_literal[1]}.gather.scalar.offset.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "{index_or_offset}: i64" + - "op: svprfop" + - FnCall: + - "{llvm_link}" + - - $pg + - $bases + - MatchSize: + - "{type[1]}" + - byte: $offset + halfword: { MethodCall: [$index, unchecked_shl, [1]] } + default: { MethodCall: [$index, unchecked_shl, [2]] } + doubleword: { MethodCall: [$index, unchecked_shl, [3]] } + - $OP + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[f32, f64], [i32, u32, i64, u64]] + zeroing_method: { drop: inactive } + substitutions: + convert_from: { match_kind: "{type[1]}", default: s, unsigned: u } + assert_instr: ["{convert_from}cvtf"] + compose: + - LLVMLink: + name: "{convert_from}cvtf.{type[0]}{type[1]}" + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i32, u32, i64, u64], [f32, f64]] + zeroing_method: { drop: inactive } + substitutions: + convert_to: { match_kind: "{type[0]}", default: s, unsigned: u } + assert_instr: ["fcvtz{convert_to}"] + compose: + - LLVMLink: { name: "fcvtz{convert_to}.{type[0]}{type[1]}" } + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64], [f64, f32]] + zeroing_method: { drop: inactive } + assert_instr: [fcvt] + compose: + - LLVMLink: { name: "fcvt.{type[0]}{type[1]}" } + + - name: svreinterpret_{type[0]}[_{type[1]}] + attr: [*sve-unstable] + doc: Reinterpret vector contents + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + assert_instr: [] + types: + - - [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + - [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - FnCall: ["crate::intrinsics::transmute_unchecked", [$op], [], true] + + - name: svrinta[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round to nearest, ties away from zero + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frinta] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frinta.{sve_type}" } + + - name: svrinti[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round using current rounding mode (inexact) + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frinti] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frinti.{sve_type}" } + + - name: svrintm[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards -∞ + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintm] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintm.{sve_type}" } + + - name: svrintn[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round to nearest, ties to even + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintn] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintn.{sve_type}" } + + - name: svrintp[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards +∞ + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintp] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintp.{sve_type}" } + + - name: svrintx[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round using current rounding mode (exact) + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintx] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintx.{sve_type}" } + + - name: svrintz[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards zero + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintz] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintz.{sve_type}" } + + - name: svabd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Absolute difference + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f64, f32, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind}abd"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind}abd.{sve_type}" } + + - name: svabs[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Absolute value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64] + assert_instr: ["{type_kind.f}abs"] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "{type_kind.f}abs.{sve_type}" } + + - name: svand[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise AND + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [and] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "and.{sve_type}" } + + - name: svandv[_{type}] + attr: [*sve-unstable] + doc: Bitwise AND reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [andv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "andv.{sve_type}" } + + - name: svand[_b]_z + attr: [*sve-unstable] + doc: Bitwise AND + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [and] + compose: + - LLVMLink: { name: "and.z.nvx16i1" } + + - name: svmov[_b]_z + attr: [*sve-unstable] + doc: Move + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: svbool_t + assert_instr: [mov] + compose: + - FnCall: ["svand_b_z", [$pg, $op, $op]] + + - name: svbic[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise clear + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bic] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "bic.{sve_type}" } + + - name: svbic[_b]_z + attr: [*sve-unstable] + doc: Bitwise clear + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [bic] + compose: + - LLVMLink: { name: "bic.z.nvx16i1" } + + - name: sveor[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise exclusive OR + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eor] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "eor.{sve_type}" } + + - name: sveorv[_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [eorv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "eorv.{sve_type}" } + + - name: sveor[_b]_z + attr: [*sve-unstable] + doc: Bitwise exclusive OR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [eor] + compose: + - LLVMLink: { name: "eor.z.nvx16i1" } + + - name: svnot[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise invert + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [not] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "not.{sve_type}" } + + - name: svnot[_b]_z + attr: [*sve-unstable] + doc: Bitwise invert + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: svbool_t + assert_instr: [not] + compose: + - FnCall: ["sveor_b_z", [$pg, $op, $pg]] + + - name: svcnot[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Logically invert boolean condition + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [cnot] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "cnot.{sve_type}" } + + - name: svnand[_b]_z + attr: [*sve-unstable] + doc: Bitwise NAND + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [nand] + compose: + - LLVMLink: { name: "nand.z.nxv16i1" } + + - name: svnor[_b]_z + attr: [*sve-unstable] + doc: Bitwise NOR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [nor] + compose: + - LLVMLink: { name: "nor.z.nxv16i1" } + + - name: svorr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise inclusive OR + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [orr] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "orr.{sve_type}" } + + - name: svorv[_{type}] + attr: [*sve-unstable] + doc: Bitwise inclusive OR reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [orv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "orv.{sve_type}" } + + - name: svorr[_b]_z + attr: [*sve-unstable] + doc: Bitwise inclusive OR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [orr] + compose: + - LLVMLink: { name: "orr.z.nvx16i1" } + + - name: svorn[_b]_z + attr: [*sve-unstable] + doc: Bitwise inclusive OR, inverting second argument + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [orn] + compose: + - LLVMLink: { name: "orn.z.nvx16i1" } + + - name: svlsl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], u8] + - [[i16, u16], u16] + - [[i32, u32], u32] + - [[i64, u64], u64] + assert_instr: [lsl] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsl.{sve_type[0]}" } + + - name: svlsl_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, i16, i32, u8, u16, u32], u64] + assert_instr: [lsl] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsl.wide.{sve_type[0]}" } + + - name: svasr[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [asr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "asr.{sve_type[0]}" } + + - name: svasr_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, i16, i32], u64] + assert_instr: [asr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "asr.wide.{sve_type[0]}" } + + - name: svasrd[_n_{type}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right for divide by immediate + arguments: ["pg: {predicate}", "op1: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64] + assert_instr: [[asrd, "IMM2 = 1"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "asrd.{sve_type}" + arguments: ["pg: {predicate}", "op1: {sve_type}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svlsr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift right + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [lsr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsr.{sve_type}" } + + - name: svlsr_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[u8, u16, u32], u64] + assert_instr: [lsr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsr.wide.{sve_type[0]}" } + + - name: svadda[_{type}] + attr: [*sve-unstable] + doc: Add reduction (strictly-ordered) + arguments: ["pg: {predicate}", "initial: {type}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [fadda] + types: [f32, f64] + compose: + - LLVMLink: { name: "fadda.{sve_type}" } + + - name: svaddv[_{type}] + attr: [*sve-unstable] + doc: Add reduction + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i64, u64] + assert_instr: [{ float: faddv, default: uaddv }] + compose: + - LLVMLink: { name: "{type_kind.fsu}addv.{sve_type}" } + + - name: svaddv[_{type[0]}] + attr: [*sve-unstable] + doc: Add reduction + arguments: ["pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{type[1]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: ["{type_kind[0].su}addv"] + compose: + - LLVMLink: { name: "{type_kind[0].su}addv.{sve_type[0]}" } + + - name: svmaxv[_{type}] + attr: [*sve-unstable] + doc: Maximum reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}maxv"] + compose: + - LLVMLink: { name: "{type_kind.fsu}maxv.{sve_type}" } + + - name: svmaxnmv[_{type}] + attr: [*sve-unstable] + doc: Maximum number reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64] + assert_instr: [fmaxnmv] + compose: + - LLVMLink: { name: "fmaxnmv.{sve_type}" } + + - name: svminv[_{type}] + attr: [*sve-unstable] + doc: Minimum reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}minv"] + compose: + - LLVMLink: { name: "{type_kind.fsu}minv.{sve_type}" } + + - name: svminnmv[_{type}] + attr: [*sve-unstable] + doc: Minimum number reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64] + assert_instr: [fminnmv] + compose: + - LLVMLink: { name: "fminnmv.{sve_type}" } + + - name: svmul[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["{type_kind.f}mul"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}mul.{sve_type}" } + + - name: svmulh[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply, returning high-half + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["{type_kind.su}mulh"] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}mulh.{sve_type}" } + + - name: svmulx[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply extended (∞×0=2) + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["fmulx"] + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "fmulx.{sve_type}" } + + - name: svrecpe[_{type}] + attr: [*sve-unstable] + doc: Reciprocal estimate + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecpe] + compose: + - LLVMLink: { name: "frecpe.x.{sve_type}" } + + - name: svrecps[_{type}] + attr: [*sve-unstable] + doc: Reciprocal step + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecps] + compose: + - LLVMLink: { name: "frecps.x.{sve_type}" } + + - name: svrecpx[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal exponent + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecpx] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frecpx.x.{sve_type}" } + + - name: svrsqrte[_{type}] + attr: [*sve-unstable] + doc: Reciprocal square root estimate + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frsqrte] + compose: + - LLVMLink: { name: "frsqrte.x.{sve_type}" } + + - name: svrsqrts[_{type}] + attr: [*sve-unstable] + doc: Reciprocal square root step + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frsqrts] + compose: + - LLVMLink: { name: "frsqrts.x.{sve_type}" } + + - name: svmad[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-add, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mad"] + compose: + - LLVMLink: { name: "{type_kind.f}mad.{sve_type}" } + + - name: svmla[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mla"] + compose: + - LLVMLink: { name: "{type_kind.f}mla.{sve_type}" } + + - name: svmla_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [f32, f64] + assert_instr: [[fmla, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "fmla.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmls[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mls"] + compose: + - LLVMLink: { name: "{type_kind.f}mls.{sve_type}" } + + - name: svmls_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [f32, f64] + assert_instr: [[fmls, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "fmls.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmsb[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-subtract, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}msb"] + compose: + - LLVMLink: { name: "{type_kind.f}msb.{sve_type}" } + + - name: svnmad[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-add, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmad] + compose: + - LLVMLink: { name: "fnmad.{sve_type}" } + + - name: svnmla[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-add, addend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmla] + compose: + - LLVMLink: { name: "fnmla.{sve_type}" } + + - name: svnmls[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-subtract, minuend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmls] + compose: + - LLVMLink: { name: "fnmls.{sve_type}" } + + - name: svnmsb[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-subtract, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmsb] + compose: + - LLVMLink: { name: "fnmsb.{sve_type}" } + + - name: svneg[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64] + assert_instr: ["{type_kind.f}neg"] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "{type_kind.f}neg.{sve_type}" } + + - name: svqadd[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating add + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qadd.x.{sve_type}" } + + - name: svadr{size_literal[2]}[_{type[0]}base]_[{type[1]}]{index_or_offset} + attr: [*sve-unstable] + substitutions: + index_or_offset: { match_size: "{type[2]}", default: index, byte: offset } + indices_or_offsets: + { match_size: "{type[2]}", default: indices, byte: offsets } + doc: Compute vector addresses for {size[2]}-bit data + arguments: ["bases: {sve_type[0]}", "{indices_or_offsets}: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [u32, [i32, u32], [i8, i16, i32, i64]] + - [u64, [i64, u64], [i8, i16, i32, i64]] + assert_instr: [adr] + compose: + - LLVMLink: { name: "adr{size_literal[2]}.{sve_type[0]}" } + + - name: svdot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i8] + - [i64, i16] + - [u32, u8] + - [u64, u16] + assert_instr: ["{type_kind[0].su}dot"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}dot.{sve_type[0]}" } + + - name: svdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: + - [i32, i8] + - [i64, i16] + - [u32, u8] + - [u64, u16] + assert_instr: [["{type_kind[0].su}dot", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}dot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svusdot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, u8, i8]] + assert_instr: [usdot] + n_variant_op: op3 + compose: + - LLVMLink: { name: "usdot.{sve_type[0]}" } + + - name: svusdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: [[i32, u8, i8]] + assert_instr: [[usdot, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "usdot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[2]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svsudot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (signed × unsigned) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8, u8]] + assert_instr: [usdot] + n_variant_op: op3 + compose: + - FnCall: ["svusdot_{type[0]}", [$op1, $op3, $op2]] + + - name: svsudot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (signed × unsigned) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: [[i32, i8, u8]] + assert_instr: [[sudot, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sudot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[2]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svdiv[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Divide + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: ["{type_kind.fsu}div"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}div.{sve_type}" } + + - name: svdivr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Divide reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: ["{type_kind.fsu}divr"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}divr.{sve_type}" } + + - name: svexpa[_{type[0]}] + attr: [*sve-unstable] + doc: Floating-point exponential accelerator + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, u32], [f64, u64]] + assert_instr: [fexpa] + compose: + - LLVMLink: { name: "fexpa.x.{sve_type[0]} " } + + - name: svscale[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Adjust exponent + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, i32], [f64, i64]] + assert_instr: [fscale] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "fscale.{sve_type[0]}" } + + - name: svmmla[_{type}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [f32mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f32] + assert_instr: [fmmla] + compose: + - LLVMLink: { name: "fmmla.{sve_type}" } + + - name: svmmla[_{type}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f64] + assert_instr: [fmmla] + compose: + - LLVMLink: { name: "fmmla.{sve_type}" } + + - name: svmmla[_{type[0]}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [u32, u8]] + assert_instr: ["{type_kind[0].su}mmla"] + compose: + - LLVMLink: { name: "{type_kind[0].su}mmla.{sve_type[0]}" } + + - name: svusmmla[_{type[0]}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, u8, i8]] + assert_instr: [usmmla] + compose: + - LLVMLink: { name: "usmmla.{sve_type[0]}" } + + - name: svmin[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Minimum + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.fsu}min"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}min.{sve_type}" } + + - name: svminnm[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Minimum number + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + assert_instr: [fminnm] + n_variant_op: op2 + compose: + - LLVMLink: { name: "fminnm.{sve_type}" } diff --git a/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml b/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml new file mode 100644 index 0000000000000..269d7ff0eacbb --- /dev/null +++ b/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml @@ -0,0 +1,3206 @@ +arch_cfgs: + - arch_name: aarch64 + target_feature: [sve, sve2] + llvm_prefix: llvm.aarch64.sve + +auto_llvm_sign_conversion: true +generate_load_store_tests: true + +# `#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]` +sve-unstable: &sve-unstable + FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']] + +# `#[cfg_attr(all(test, not(target_env = "msvc"))]` +msvc-disabled: &msvc-disabled + FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]] + +intrinsics: + - name: svbext[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Gather lower bits from positions selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bext] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bext.x.{sve_type}" } + + - name: svbgrp[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Group bits to right or left as selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bgrp] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bgrp.x.{sve_type}" } + + - name: svbdep[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Scatter lower bits into positions selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bdep] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bdep.x.{sve_type}" } + + - name: svhistcnt[_{type[0]}]_z + attr: [*sve-unstable] + doc: Count matching elements + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i32, u32], [i64, u64], [u32, u32], [u64, u64]] + assert_instr: [histcnt] + compose: + - LLVMLink: { name: "histcnt.{sve_type[0]}" } + + - name: svhistseg[_{type[0]}] + attr: [*sve-unstable] + doc: Count matching elements in 128-bit segments + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i8, u8], [u8, u8]] + assert_instr: [histseg] + compose: + - LLVMLink: { name: "histseg.{sve_type[0]}" } + + - name: svmatch[_{type}] + attr: [*sve-unstable] + doc: Detect any matching elements + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [i8, i16, u8, u16] + assert_instr: [match] + compose: + - LLVMLink: { name: "match.{sve_type}" } + + - name: svnmatch[_{type}] + attr: [*sve-unstable] + doc: Detect no matching elements + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [i8, i16, u8, u16] + assert_instr: [nmatch] + compose: + - LLVMLink: { name: "nmatch.{sve_type}" } + + - name: svhadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}hadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hadd.{sve_type}" } + + - name: svrhadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Rounding halving add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}rhadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}rhadd.{sve_type}" } + + - name: svaddhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add narrow high part (bottom) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [addhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "addhnb.{sve_type[0]}" } + + - name: svaddhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add narrow high part (top) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [addhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "addhnt.{sve_type[0]}" } + + - name: svraddhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding add narrow high part (bottom) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [raddhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "raddhnb.{sve_type[0]}" } + + - name: svraddhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding add narrow high part (top) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [raddhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "raddhnt.{sve_type[0]}" } + + - name: svcadd[_{type}] + attr: [*sve-unstable] + doc: Complex add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [90, 270] }] + assert_instr: [[cadd, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cadd.x.{sve_type} + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_rotation: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_ROTATION]] + + - name: svcdot[_{type[0]}] + attr: [*sve-unstable] + doc: Complex dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [i64, i16]] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[cdot, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cdot.{sve_type[0]} + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Complex dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [i64, i16]] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - { variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[cdot, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cdot.lane.{sve_type[0]} + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svcmla[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[cmla, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cmla.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcmla_lane[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32, u16, u32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[cmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cmla.lane.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svqrdcmlah[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling complex multiply-add high with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[sqrdcmlah, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: sqrdcmlah.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svqrdcmlah_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling complex multiply-add high with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[sqrdcmlah, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: sqrdcmlah.lane.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svqcadd[_{type}] + attr: [*sve-unstable] + doc: Saturating complex add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: "IMM_ROTATION", any_values: [90, 270] }] + assert_instr: [[sqcadd, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: "sqcadd.x.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_rotation: i32"] + - FnCall: ["{llvm_link}", ["$op1", "$op2", "$IMM_ROTATION"]] + + - name: svsublb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}sublb"] + n_variant_op: op2 + compose: + - LLVMLink: + name: "{type_kind[0].su}sublb.{sve_type[0]}" + + - name: svsublbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (bottom - top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: [ssublbt] + n_variant_op: op2 + compose: + - LLVMLink: + name: "ssublbt.{sve_type[0]}" + + - name: svsublt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}sublt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}sublt.{sve_type[0]}" } + + - name: svsubltb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (top - bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: [ssubltb] + n_variant_op: op2 + compose: + - LLVMLink: + name: "ssubltb.{sve_type[0]}" + + - name: svsubwb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract wide (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}subwb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}subwb.{sve_type[0]}" } + + - name: svsubwt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract wide (top) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}subwt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}subwt.{sve_type[0]}" } + + - name: svrsubhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding subtract narrow high part (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [rsubhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "rsubhnb.{sve_type[0]}" } + + - name: svrsubhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding subtract narrow high part (top) + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [rsubhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "rsubhnt.{sve_type[0]}" } + + - name: svsubhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract narrow high part (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [subhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "subhnb.{sve_type[0]}" } + + - name: svsubhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract narrow high part (top) + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [subhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "subhnt.{sve_type[0]}" } + + - name: svsbclb[{_n}_{type}] + attr: [*sve-unstable] + doc: Subtract with borrow long (bottom) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [sbclb] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sbclb.{sve_type}" } + + - name: svsbclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Subtract with borrow long (top) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [sbclt] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sbclt.{sve_type}" } + + - name: svqsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}qsub"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsub.{sve_type}" } + + - name: svqsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}qsubr"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsubr.{sve_type}" } + + - name: svhsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}hsub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hsub.{sve_type}" } + + - name: svhsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}hsub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hsubr.{sve_type}" } + + - name: svwhilege_{sve_type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While decrementing scalar is greater than or equal to + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilege, unsigned: whilehs }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilege.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilehs.{sve_type[1]}.{type[0]}" } } + + - name: svwhilegt_{sve_type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While decrementing scalar is greater than + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilegt, unsigned: whilehi }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilegt.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilehi.{sve_type[1]}.{type[0]}" } } + + - name: svwhilerw_{size}ptr + attr: [*sve-unstable] + safety: + unsafe: [] + visibility: private + static_defs: [T] + substitutions: + size_alt: + match_size: "{type}" + byte: b + halfword: h + default: s + doubleword: d + arguments: ["op1: *T", "op2: *T"] + return_type: "{predicate}" + types: [i8, i16, i32, i64] + assert_instr: [] + compose: + - Let: [op1, CastAs: [$op1, "*const crate::ffi::c_void"]] + - Let: [op2, CastAs: [$op2, "*const crate::ffi::c_void"]] + - LLVMLink: + name: "whilerw.{size_alt}.{predicate}.p0" + arguments: ["op1: *crate::ffi::c_void", "op2: *crate::ffi::c_void"] + + - name: svwhilerw[_{type}] + attr: [*sve-unstable] + doc: While free of read-after-write conflicts + # TODO: This might be safe even with unrelated pointers, but the LLVM builtin's guarantees don't + # seem to be documented, so we conservatively keep this unsafe for now. + safety: + unsafe: + - custom: "[`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints + must be met for at least the base pointers, `op1` and `op2`." + arguments: ["op1: *{type}", "op2: *{type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [whilerw] + compose: + - FnCall: + - "svwhilerw_{size}ptr" + - - $op1 + - $op2 + - - Type: "{type}" + + - name: svwhilewr_{size}ptr + attr: [*sve-unstable] + safety: + unsafe: [] + visibility: private + static_defs: [T] + substitutions: + size_alt: + match_size: "{type}" + byte: b + halfword: h + default: s + doubleword: d + arguments: ["op1: *T", "op2: *T"] + return_type: "{predicate}" + types: [i8, i16, i32, i64] + assert_instr: [] + compose: + - Let: [op1, CastAs: [$op1, "*const crate::ffi::c_void"]] + - Let: [op2, CastAs: [$op2, "*const crate::ffi::c_void"]] + - LLVMLink: + name: "whilewr.{size_alt}.{predicate}.p0" + arguments: ["op1: *crate::ffi::c_void", "op2: *crate::ffi::c_void"] + + - name: svwhilewr[_{type}] + attr: [*sve-unstable] + doc: While free of write-after-read conflicts + # TODO: This might be safe even with unrelated pointers, but the LLVM builtin's guarantees don't + # seem to be documented, so we conservatively keep this unsafe for now. + safety: + unsafe: + - custom: "[`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints + must be met for at least the base pointers, `op1` and `op2`." + arguments: ["op1: *{type}", "op2: *{type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [whilewr] + compose: + - FnCall: + - "svwhilewr_{size}ptr" + - - $op1 + - $op2 + - - Type: "{type}" + + - name: svtbl2[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in two-vector table + arguments: ["data: {sve_type_x2[0]}", "indices: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbl] + compose: + - LLVMLink: + name: "tbl2.{sve_type[0]}" + arguments: + - "data0: {sve_type[0]}" + - "data1: {sve_type[0]}" + - "indices: {sve_type[1]}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget2_{type[0]}", ["$data"], [0]] + - FnCall: ["svget2_{type[0]}", ["$data"], [1]] + - $indices + + - name: svtbx[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in single-vector table (merging) + arguments: + - "fallback: {sve_type[0]}" + - "data: {sve_type[0]}" + - "indices: {sve_type[1]}" + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbx] + compose: + - LLVMLink: { name: "tbx.{sve_type[0]}" } + + - name: svcvtlt_{type[0]}[_{type[1]}]_m + attr: [*sve-unstable] + doc: Up convert long (top) + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f64, f32]] + assert_instr: [fcvtlt] + compose: + - LLVMLink: { name: "fcvtlt.{type[0]}{type[1]}" } + + - name: svcvtlt_{type[0]}[_{type[1]}]_x + attr: [*sve-unstable] + doc: Up convert long (top) + arguments: ["pg: svbool_t", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f64, f32]] + assert_instr: [fcvtlt] + compose: + - FnCall: + - "svcvtlt_{type[0]}_{type[1]}_m" + - - FnCall: ["crate::intrinsics::transmute_unchecked", [$op], [], true] + - $pg + - $op + + - name: svcvtnt_{type[0]}[_{type[1]}]{_mx} + attr: [*sve-unstable] + doc: Down convert and narrow (top) + arguments: + ["even: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + assert_instr: [fcvtnt] + compose: + - LLVMLink: { name: "fcvtnt.{type[0]}{type[1]}" } + + - name: svcvtx_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Down convert, rounding to odd + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + zeroing_method: { drop: inactive } + assert_instr: [fcvtx] + compose: + - LLVMLink: { name: "fcvtx.{type[0]}{type[1]}" } + + - name: svcvtxnt_{type[0]}[_{type[1]}]{_mx} + attr: [*sve-unstable] + doc: Down convert, rounding to odd (top) + arguments: + ["even: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + assert_instr: [fcvtxnt] + compose: + - LLVMLink: { name: "fcvtxnt.{type[0]}{type[1]}" } + + - name: svldnt1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: { name: "ldnt1.gather.index.{sve_type[1]}" } + + - name: svldnt1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: { name: "ldnt1.gather.uxtw.{sve_type[1]}" } + doubleword: + LLVMLink: { name: "ldnt1.gather.{sve_type[1]}" } + + - name: svldnt1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svldnt1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnt1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnt1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svldnt1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svldnt1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldnt1.gather.uxtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldnt1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svldnt1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldnt1.gather.uxtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldnt1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svstnt1_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + name: "stnt1.scatter.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $indices]] + + - name: svstnt1_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "stnt1.scatter.uxtw.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "stnt1.scatter.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $offsets]] + + - name: svstnt1_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + name: "stnt1.scatter.scalar.offset.{sve_type[1]}.{sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $bases, $offset]] + + - name: svstnt1_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svstnt1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svstnt1_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svstnt1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + - $data + + - name: svstnt1{size_literal[2]}_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i64, u64], i64, [i16, i32]] + - [[i64, u64], u64, [u16, u32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "stnt1.scatter.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $indices] + + - name: svstnt1{size_literal[2]}_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [u32, i32, [i8, i16]] + - [u32, u32, [u8, u16]] + - [[i64, u64], i64, [i8, i16, i32]] + - [[i64, u64], u64, [u8, u16, u32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "stnt1.scatter.uxtw.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "stnt1.scatter.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $offsets] + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "stnt1.scatter.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $bases, $offset] + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svstnt1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svstnt1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + - $data + + - name: svaba[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute difference and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind}aba"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind}aba.{sve_type}" } + + - name: svqabs[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating absolute value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqabs] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "sqabs.{sve_type}" } + + - name: svabdlb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abdlb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}abdlb.{sve_type[0]}" } + + - name: svabdlt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abdlt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}abdlt.{sve_type[0]}" } + + - name: svabalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}abalb.{sve_type[0]}" } + + - name: svabalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}abalt.{sve_type[0]}" } + + - name: svbcax[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise clear and exclusive OR + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bcax] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bcax.{sve_type}" } + + - name: sveorbt[{_n}_{type}] + attr: [*sve-unstable] + doc: Interleaving exclusive OR (bottom, top) + arguments: ["odd: {sve_type}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eorbt] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + compose: + - LLVMLink: { name: "eorbt.{sve_type}" } + + - name: sveortb[{_n}_{type}] + attr: [*sve-unstable] + doc: Interleaving exclusive OR (top, bottom) + arguments: ["even: {sve_type}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eortb] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + compose: + - LLVMLink: { name: "eortb.{sve_type}" } + + - name: sveor3[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR of three vectors + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eor3] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "eor3.{sve_type}" } + + - name: svbsl[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl.{sve_type}" } + + - name: svbsl1n[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select with first input inverted + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl1n] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl1n.{sve_type}" } + + - name: svbsl2n[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select with second input inverted + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl2n] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl2n.{sve_type}" } + + - name: svnbsl[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [nbsl] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "nbsl.{sve_type}" } + + - name: svxar[_n_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR and rotate right + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + assert_instr: [[xar, "IMM3 = 1"]] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: + name: "xar.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrax1[_{type}] + attr: [*sve-unstable] + doc: Bitwise rotate left by 1 and exclusive OR + target_features: [sve2-sha3] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [rax1] + types: [i64, u64] + compose: + - LLVMLink: { name: "rax1" } + + - name: svshllb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift left long (bottom) + arguments: ["op1: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}shllb", "IMM2 = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}shllb.{sve_type[0]}" + arguments: ["op1: {sve_type[1]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svshllt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift left long (top) + arguments: ["op1: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}shllt", "IMM2 = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}shllt.{sve_type[0]}" + arguments: ["op1: {sve_type[1]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svrshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Rounding shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}rshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}rshl.{sve_type[0]}" } + + - name: svqrshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating rounding shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}qrshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}qrshl.{sve_type[0]}" } + + - name: svqshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}qshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}qshl.{sve_type[0]}" } + + - name: svqshlu[_n_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating shift left unsigned + arguments: ["pg: {predicate[0]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [[sqshlu, "IMM2 = 0"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "sqshlu.{sve_type[0]}" + arguments: ["pg: {predicate[0]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svsli[_n_{type}] + attr: [*sve-unstable] + doc: Shift left and insert + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["0", "{size_minus_one}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[sli, "IMM3 = 0"]] + compose: + - LLVMLink: + name: "sli.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrshr[_n_{type}]{_mxz} + attr: [*sve-unstable] + doc: Rounding shift right + arguments: ["pg: {predicate}", "op1: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}rshr", "IMM2 = 1"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "{type_kind.su}rshr.{sve_type}" + arguments: ["pg: {predicate}", "op1: {sve_type}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svrsra[_n_{type}] + attr: [*sve-unstable] + doc: Rounding shift right and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}rsra", "IMM3 = 1"]] + compose: + - LLVMLink: + name: "{type_kind.su}rsra.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Rounding shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[rshrnb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "rshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svrshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Rounding shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[rshrnt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "rshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqrshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qrshrnb", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qrshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqrshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qrshrnt", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qrshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqrshrunb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right unsigned narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqrshrunb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqrshrunb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqrshrunt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqrshrunt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqrshrunt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qshrnb", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qshrnt", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqshrunb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right unsigned narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqshrunb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqshrunb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqshrunt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqshrunt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqshrunt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svsra[_n_{type}] + attr: [*sve-unstable] + doc: Shift right and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}sra", "IMM3 = 1"]] + compose: + - LLVMLink: + name: "{type_kind.su}sra.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svsri[_n_{type}] + attr: [*sve-unstable] + doc: Shift right and insert + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[sri, "IMM3 = 1"]] + compose: + - LLVMLink: + name: "sri.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[shrnb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "shrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[shrnt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "shrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqxtnb[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract narrow (bottom) + arguments: ["op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}qxtnb"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qxtnb.{sve_type[0]}" } + + - name: svqxtnt[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract narrow (top) + arguments: ["even: {sve_type[1]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}qxtnt"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qxtnt.{sve_type[0]}" } + + - name: svqxtunb[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract unsigned narrow (bottom) + arguments: ["op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [sqxtunb] + compose: + - LLVMLink: { name: "sqxtunb.{sve_type[0]}" } + + - name: svqxtunt[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [sqxtunt] + compose: + - LLVMLink: { name: "sqxtunt.{sve_type[0]}" } + + - name: svmovlb[_{type[0]}] + attr: [*sve-unstable] + doc: Move long (bottom) + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}shllb"] + compose: + - FnCall: ["svshllb_n_{type[0]}", [$op], [0]] + + - name: svmovlt[_{type[0]}] + attr: [*sve-unstable] + doc: Move long (top) + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}shllt"] + compose: + - FnCall: ["svshllt_n_{type[0]}", [$op], [0]] + + - name: svunpkhi[_{type[0]}] + attr: [*sve-unstable] + doc: Unpack and extend high half + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}unpkhi"] + compose: + - LLVMLink: { name: "{type_kind[0].su}unpkhi.{sve_type[0]}" } + + - name: svunpkhi[_b] + attr: [*sve-unstable] + doc: Unpack and extend high half + arguments: ["op: svbool_t"] + return_type: "svbool8_t" + assert_instr: [punpkhi] + compose: + - LLVMLink: { name: "punpkhi.nxv16i1" } + + - name: svunpklo[_{type[0]}] + attr: [*sve-unstable] + doc: Unpack and extend low half + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}unpklo"] + compose: + - LLVMLink: { name: "{type_kind[0].su}unpklo.{sve_type[0]}" } + + - name: svunpklo[_b] + attr: [*sve-unstable] + doc: Unpack and extend low half + arguments: ["op: svbool_t"] + return_type: "svbool8_t" + assert_instr: [punpklo] + compose: + - LLVMLink: { name: "punpklo.nxv16i1" } + + - name: svaddp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Add pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.f}addp"] + compose: + - LLVMLink: { name: "{type_kind.f}addp.{sve_type}" } + + - name: svadalp[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Add and accumulate long pairwise + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}adalp"] + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "{type_kind[0].su}adalp.{sve_type[0]}" } + + - name: svmaxp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Maximum pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}maxp"] + compose: + - LLVMLink: { name: "{type_kind.fsu}maxp.{sve_type}" } + + - name: svmaxnmp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Maximum number pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: ["fmaxnmp"] + compose: + - LLVMLink: { name: "fmaxnmp.{sve_type}" } + + - name: svminp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Minimum pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}minp"] + compose: + - LLVMLink: { name: "{type_kind.fsu}minp.{sve_type}" } + + - name: svminnmp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Minimum number pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: ["fminnmp"] + compose: + - LLVMLink: { name: "fminnmp.{sve_type}" } + + - name: svmul_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["{type_kind.f}mul", "IMM_INDEX = 0"]] + types: [f32, f64, i16, i32, i64, u16, u32, u64] + compose: + - LLVMLink: + name: "{type_kind.f}mul.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmulh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqdmulh] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmulh.{sve_type}" } + + - name: svqdmulh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["sqdmulh", "IMM_INDEX = 0"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: "sqdmulh.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqrdmulh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmulh] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqrdmulh.{sve_type}" } + + - name: svqrdmulh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["sqrdmulh", "IMM_INDEX = 0"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: "sqrdmulh.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: [sqdmullb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmullb.{sve_type[0]}" } + + - name: svqdmullb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + assert_instr: [["sqdmullb", "IMM_INDEX = 0"]] + types: [[i32, i16], [i64, i32]] + compose: + - LLVMLink: + name: "sqdmullb.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmullt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: [sqdmullt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmullt.{sve_type[0]}" } + + - name: svqdmullt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + assert_instr: [["sqdmullt", "IMM_INDEX = 0"]] + types: [[i32, i16], [i64, i32]] + compose: + - LLVMLink: + name: "sqdmullt.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}mullb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}mullb.{sve_type[0]}" } + + - name: svmullb_lane[_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullb` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullb", "IMM_INDEX = 0"]]}]] + doc: Multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i16] + - [i64, i32] + - [u32, u16] + - [u64, u32] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + compose: + - LLVMLink: + name: "{type_kind[0].su}mullb.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]] + + - name: svmullt[{_n}_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullt` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullt"]]}]] + doc: Multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}mullt.{sve_type[0]}" } + + - name: svmullt_lane[_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullt` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullt", "IMM_INDEX = 0"]]}]] + doc: Multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i16] + - [i64, i32] + - [u32, u16] + - [u64, u32] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + compose: + - LLVMLink: + name: "{type_kind[0].su}mullt.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]] + + - name: svrecpe[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal estimate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [urecpe] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "urecpe.{sve_type}" } + + - name: svrsqrte[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal square root estimate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [ursqrte] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "ursqrte.{sve_type}" } + + - name: svmla_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64, u16, u32, u64] + assert_instr: [[mla, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "mla.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmls_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64, u16, u32, u64] + assert_instr: [[mls, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "mls.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlalb.{sve_type[0]}" } + + - name: svmlalb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlalb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlalb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlalt.{sve_type[0]}" } + + - name: svmlalt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlalt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlalt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlslb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlslb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlslb.{sve_type[0]}" } + + - name: svmlslb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlslb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlslb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlslt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlslt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlslt.{sve_type[0]}" } + + - name: svmlslt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlslt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlslt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqrdmlah[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-add high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmlah] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqrdmlah.{sve_type}" } + + - name: svqrdmlah_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-add high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64] + assert_instr: [[sqrdmlah, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqrdmlah.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqrdmlsh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-subtract high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmlsh] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqrdmlsh.{sve_type}" } + + - name: svqrdmlsh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-subtract high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64] + assert_instr: [[sqrdmlsh, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqrdmlsh.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalb.{sve_type[0]}" } + + - name: svqdmlalb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlalb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlalb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlalbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom × top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalbt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalbt.{sve_type[0]}" } + + - name: svqdmlalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalt.{sve_type[0]}" } + + - name: svqdmlalt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlalt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlalt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlslb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslb.{sve_type[0]}" } + + - name: svqdmlslb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlslb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlslb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlslbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom × top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslbt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslbt.{sve_type[0]}" } + + - name: svqdmlslt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslt.{sve_type[0]}" } + + - name: svqdmlslt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlslt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlslt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqneg[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating negate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqneg] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "sqneg.{sve_type}" } + + - name: svadclb[{_n}_{type}] + attr: [*sve-unstable] + doc: Add with carry long (bottom) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [adclb] + n_variant_op: op3 + compose: + - LLVMLink: { name: "adclb.{sve_type}" } + + - name: svadclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Add with carry long (top) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [adclt] + n_variant_op: op3 + compose: + - LLVMLink: { name: "adclt.{sve_type}" } + + - name: svqadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qadd"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qadd.{sve_type}" } + + - name: svsqadd[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add with signed addend + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [u8, i8] + - [u16, i16] + - [u32, i32] + - [u64, i64] + assert_instr: [usqadd] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "usqadd.{sve_type[0]}" } + + - name: svuqadd[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add with unsigned addend + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [suqadd] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "suqadd.{sve_type[0]}" } + + - name: svaddlb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addlb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlb.{sve_type[0]}" } + + - name: svaddlbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (bottom + top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: ["{type_kind[0].su}addlbt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlbt.{sve_type[0]}" } + + - name: svaddlt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addlt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlt.{sve_type[0]}" } + + - name: svaddwb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add wide (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addwb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addwb.{sve_type[0]}" } + + - name: svaddwt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add wide (top) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addwt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addwt.{sve_type[0]}" } + + - name: svlogb[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Base 2 logarithm as integer + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[f32, i32], [f64, i64]] + assert_instr: [flogb] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "flogb.{sve_type[0]}" } + + - name: svpmul[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [pmul] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmul.{sve_type}" } + + - name: svpmullb_pair[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply long (bottom) + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u32, u64] + assert_instr: [pmullb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmullb.pair.{sve_type}" } + + - name: svpmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Polynomial multiply long (bottom) + target_features: [sve2-aes] + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[u16, u8], [u64, u32]] + assert_instr: [pmullb] + n_variant_op: op2 + compose: + - FnCall: + - "crate::intrinsics::transmute_unchecked" + - [FnCall: ["svpmullb_pair_{type[1]}", [$op1, $op2]]] + - [] + - true + + - name: svpmullt_pair[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply long (top) + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u32, u64] + assert_instr: [pmullt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmullt.pair.{sve_type}" } + + - name: svpmullt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Polynomial multiply long (top) + target_features: [sve2-aes] + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[u16, u8], [u64, u32]] + assert_instr: [pmullt] + n_variant_op: op2 + compose: + - FnCall: + - "crate::intrinsics::transmute_unchecked" + - [FnCall: ["svpmullt_pair_{type[1]}", [$op1, $op2]]] + - [] + - true + + - name: svaesd[_{type}] + attr: [*sve-unstable] + doc: AES single round decryption + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesd] + compose: + - LLVMLink: { name: "aesd" } + + - name: svaese[_{type}] + attr: [*sve-unstable] + doc: AES single round encryption + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aese] + compose: + - LLVMLink: { name: "aese" } + + - name: svaesmc[_{type}] + attr: [*sve-unstable] + doc: AES mix columns + target_features: [sve2-aes] + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesmc] + compose: + - LLVMLink: { name: "aesmc" } + + - name: svaesimc[_{type}] + attr: [*sve-unstable] + doc: AES inverse mix columns + target_features: [sve2-aes] + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesimc] + compose: + - LLVMLink: { name: "aesimc" } + + - name: svsm4e[_{type}] + attr: [*sve-unstable] + doc: SM4 encryption and decryption + target_features: [sve2-sm4] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [sm4e] + compose: + - LLVMLink: { name: "sm4e" } + + - name: svsm4ekey[_{type}] + attr: [*sve-unstable] + doc: SM4 key updates + target_features: [sve2-sm4] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [sm4ekey] + compose: + - LLVMLink: { name: "sm4ekey" } diff --git a/stdarch/crates/stdarch-gen-arm/src/big_endian.rs b/stdarch/crates/stdarch-gen-arm/src/big_endian.rs index b982ff53ec3d2..f024ca074eac6 100644 --- a/stdarch/crates/stdarch-gen-arm/src/big_endian.rs +++ b/stdarch/crates/stdarch-gen-arm/src/big_endian.rs @@ -15,9 +15,9 @@ fn create_single_wild_string(name: &str) -> WildString { /// Creates an Identifier with name `name` with no wildcards. This, for example, /// can be used to create variables, function names or arbitrary input. Is is /// extremely flexible. -pub fn create_symbol_identifier(arbitrary_string: &str) -> Expression { +pub fn create_symbol_identifier(arbitrary_string: &str, kind: IdentifierType) -> Expression { let identifier_name = create_single_wild_string(arbitrary_string); - Expression::Identifier(identifier_name, IdentifierType::Symbol) + Expression::Identifier(identifier_name, kind) } /// To compose the simd_shuffle! call we need: @@ -101,7 +101,6 @@ pub fn make_variable_mutable(variable_name: &str, type_kind: &TypeKind) -> Expre fn create_shuffle_internal( variable_name: &String, type_kind: &TypeKind, - fmt_tuple: fn(variable_name: &String, idx: u32, array_lanes: &String) -> String, fmt: fn(variable_name: &String, type_kind: &TypeKind, array_lanes: &String) -> String, ) -> Option { let TypeKind::Vector(vector_type) = type_kind else { @@ -120,14 +119,21 @@ fn create_shuffle_internal( /* .idx = simd_shuffle!(.idx, .idx, []) */ for idx in 0..tuple_count { - let formatted = fmt_tuple(variable_name, idx, &array_lanes); + let formatted = + create_assigned_tuple_shuffle_call_fmt(variable_name, idx, &array_lanes); string_builder += formatted.as_str(); } - Some(create_symbol_identifier(&string_builder)) + Some(create_symbol_identifier( + &string_builder, + IdentifierType::UnsafeSymbol, + )) } else { /* Generate a list of shuffles for each tuple */ let expression = fmt(variable_name, type_kind, &array_lanes); - Some(create_symbol_identifier(&expression)) + Some(create_symbol_identifier( + &expression, + IdentifierType::UnsafeSymbol, + )) } } @@ -137,7 +143,7 @@ fn create_assigned_tuple_shuffle_call_fmt( array_lanes: &String, ) -> String { format!( - "{variable_name}.{idx} = unsafe {{ simd_shuffle!({variable_name}.{idx}, {variable_name}.{idx}, {array_lanes}) }};\n" + "{variable_name}.{idx} = simd_shuffle!({variable_name}.{idx}, {variable_name}.{idx}, {array_lanes});\n" ) } @@ -147,7 +153,7 @@ fn create_assigned_shuffle_call_fmt( array_lanes: &String, ) -> String { format!( - "let {variable_name}: {type_kind} = unsafe {{ simd_shuffle!({variable_name}, {variable_name}, {array_lanes}) }}" + "let {variable_name}: {type_kind} = simd_shuffle!({variable_name}, {variable_name}, {array_lanes})" ) } @@ -165,20 +171,10 @@ pub fn create_assigned_shuffle_call( variable_name: &String, type_kind: &TypeKind, ) -> Option { - create_shuffle_internal( - variable_name, - type_kind, - create_assigned_tuple_shuffle_call_fmt, - create_assigned_shuffle_call_fmt, - ) + create_shuffle_internal(variable_name, type_kind, create_assigned_shuffle_call_fmt) } /// Create a `simd_shuffle!(<...>, [...])` call pub fn create_shuffle_call(variable_name: &String, type_kind: &TypeKind) -> Option { - create_shuffle_internal( - variable_name, - type_kind, - create_assigned_tuple_shuffle_call_fmt, - create_shuffle_call_fmt, - ) + create_shuffle_internal(variable_name, type_kind, create_shuffle_call_fmt) } diff --git a/stdarch/crates/stdarch-gen-arm/src/context.rs b/stdarch/crates/stdarch-gen-arm/src/context.rs index 9b8eb8e8b9bfe..85342a1804854 100644 --- a/stdarch/crates/stdarch-gen-arm/src/context.rs +++ b/stdarch/crates/stdarch-gen-arm/src/context.rs @@ -43,6 +43,10 @@ pub struct GlobalContext { /// Should all LLVM wrappers convert their arguments to a signed type #[serde(default)] pub auto_llvm_sign_conversion: bool, + + /// Should SVE load/store tests be generated? + #[serde(default)] + pub generate_load_store_tests: bool, } /// Context of an intrinsic group @@ -218,7 +222,7 @@ impl LocalContext { } => Ok(Expression::MacroCall( "static_assert_range".to_string(), format!( - "{variable}, {min}, {max}", + "{variable}, {min}..={max}", min = range.start(), max = range.end() ), @@ -246,7 +250,7 @@ impl LocalContext { |bitsize| Ok(higher_limit / bitsize - 1))?; Ok(Expression::MacroCall( "static_assert_range".to_string(), - format!("{variable}, 0, {max}"), + format!("{variable}, 0..={max}"), )) } else { Err(format!( diff --git a/stdarch/crates/stdarch-gen-arm/src/expression.rs b/stdarch/crates/stdarch-gen-arm/src/expression.rs index bf48f0dab7498..daaf7ee6897bd 100644 --- a/stdarch/crates/stdarch-gen-arm/src/expression.rs +++ b/stdarch/crates/stdarch-gen-arm/src/expression.rs @@ -23,6 +23,7 @@ use crate::{ pub enum IdentifierType { Variable, Symbol, + UnsafeSymbol, } #[derive(Debug, Clone, Serialize, Deserialize)] @@ -65,7 +66,11 @@ impl FnCall { } pub fn is_expected_call(&self, fn_call_name: &str) -> bool { - if let Expression::Identifier(fn_name, IdentifierType::Symbol) = self.0.as_ref() { + if let Expression::Identifier( + fn_name, + IdentifierType::Symbol | IdentifierType::UnsafeSymbol, + ) = self.0.as_ref() + { fn_name.to_string() == fn_call_name } else { false @@ -143,8 +148,6 @@ pub enum Expression { LLVMLink(LLVMLink), /// Casts the given expression to the specified (unchecked) type CastAs(Box, String), - /// Returns the LLVM `undef` symbol - SvUndef, /// Multiplication Multiply(Box, Box), /// Xor @@ -295,18 +298,20 @@ impl Expression { /// - An unnecessary `unsafe` is a warning, made into an error by the CI's `-D warnings`. /// /// This **panics** if it encounters an expression that shouldn't appear in a safe function at - /// all (such as `SvUndef`). + /// all. pub fn requires_unsafe_wrapper(&self, ctx_fn: &str) -> bool { match self { // The call will need to be unsafe, but the declaration does not. Self::LLVMLink(..) => false, - // Identifiers, literals and type names are never unsafe. - Self::Identifier(..) => false, + // literals and type names are never unsafe. Self::IntConstant(..) => false, Self::FloatConstant(..) => false, Self::BoolConstant(..) => false, Self::Type(..) => false, Self::ConvertConst(..) => false, + // Only unsafe `Symbol` identifiers are unsafe + Self::Identifier(_, IdentifierType::UnsafeSymbol) => true, + Self::Identifier(..) => false, // Nested structures that aren't inherently unsafe, but could contain other expressions // that might be. Self::Assign(_var, exp) => exp.requires_unsafe_wrapper(ctx_fn), @@ -347,9 +352,6 @@ impl Expression { }, // We only use macros to check const generics (using static assertions). Self::MacroCall(_name, _args) => false, - // Materialising uninitialised values is always unsafe, and we avoid it in safe - // functions. - Self::SvUndef => panic!("Refusing to wrap unsafe SvUndef in safe function '{ctx_fn}'."), // Variants that aren't tokenised. We shouldn't encounter these here. Self::MatchKind(..) => { unimplemented!("The unsafety of {self:?} cannot be determined in '{ctx_fn}'.") @@ -390,9 +392,7 @@ impl FromStr for Expression { static MACRO_RE: LazyLock = LazyLock::new(|| Regex::new(r"^(?P[\w\d_]+)!\((?P.*?)\);?$").unwrap()); - if s == "SvUndef" { - Ok(Expression::SvUndef) - } else if MACRO_RE.is_match(s) { + if MACRO_RE.is_match(s) { let c = MACRO_RE.captures(s).unwrap(); let ex = c["ex"].to_string(); let _: TokenStream = ex @@ -533,7 +533,6 @@ impl ToTokens for Expression { let ty: TokenStream = ty.parse().expect("invalid syntax"); tokens.append_all(quote! { #ex as #ty }) } - Self::SvUndef => tokens.append_all(quote! { simd_reinterpret(()) }), Self::Multiply(lhs, rhs) => tokens.append_all(quote! { #lhs * #rhs }), Self::Xor(lhs, rhs) => tokens.append_all(quote! { #lhs ^ #rhs }), Self::Type(ty) => ty.to_tokens(tokens), diff --git a/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs b/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs index 26c156ae178aa..6fba3dc74476e 100644 --- a/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs +++ b/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs @@ -188,7 +188,7 @@ impl FromStr for SuffixKind { "rot90_lane" => Ok(SuffixKind::Rot90Lane), "rot90_laneq" => Ok(SuffixKind::Rot90LaneQ), "rot180" => Ok(SuffixKind::Rot180), - "rot180_lane" => Ok(SuffixKind::Rot180LaneQ), + "rot180_lane" => Ok(SuffixKind::Rot180Lane), "rot180_laneq" => Ok(SuffixKind::Rot180LaneQ), "u" => Ok(SuffixKind::Unsigned), "nox" => Ok(SuffixKind::NoX), diff --git a/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs b/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs index ce427d54b3552..72fb97fee1f08 100644 --- a/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs +++ b/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs @@ -550,7 +550,7 @@ impl LLVMLink { /// Alters all the unsigned types from the signature. This is required where /// a signed and unsigned variant require the same binding to an exposed - /// LLVM instrinsic. + /// LLVM intrinsic. pub fn sanitise_uints(&mut self) { let transform = |tk: &mut TypeKind| { if let Some(BaseType::Sized(BaseTypeKind::UInt, size)) = tk.base_type() { @@ -630,7 +630,7 @@ impl LLVMLink { match (scope, kind.base_type()) { (Argument, Some(Sized(Bool, bitsize))) if *bitsize != 8 => { - Ok(convert("into", arg)) + Ok(convert("sve_into", arg)) } (Argument, Some(Sized(UInt, _) | Unsized(UInt))) => { if ctx.global.auto_llvm_sign_conversion { @@ -647,27 +647,26 @@ impl LLVMLink { }) .try_collect()?; - let return_type_conversion = if !ctx.global.auto_llvm_sign_conversion { - None - } else { - self.signature - .as_ref() - .and_then(|sig| sig.return_type.as_ref()) - .and_then(|ty| { - if let Some(Sized(Bool, bitsize)) = ty.base_type() { - (*bitsize != 8).then_some(Bool) - } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() { - Some(UInt) - } else { - None - } - }) - }; + let return_type_conversion = self + .signature + .as_ref() + .and_then(|sig| sig.return_type.as_ref()) + .and_then(|ty| { + if let Some(Sized(Bool, bitsize)) = ty.base_type() { + (*bitsize != 8).then_some(Bool) + } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() { + Some(UInt) + } else { + None + } + }); let fn_call = Expression::FnCall(fn_call); match return_type_conversion { - Some(Bool) => Ok(convert("into", fn_call)), - Some(UInt) => Ok(convert("as_unsigned", fn_call)), + Some(Bool) => Ok(convert("sve_into", fn_call)), + Some(UInt) if ctx.global.auto_llvm_sign_conversion => { + Ok(convert("as_unsigned", fn_call)) + } _ => Ok(fn_call), } } @@ -807,6 +806,7 @@ pub enum UnsafetyComment { NonTemporal, Neon, NoProvenance(String), + PointerWrite(String), } #[derive(Debug, Clone, Default, Serialize, Deserialize)] @@ -872,8 +872,12 @@ impl fmt::Display for UnsafetyComment { Self::NoProvenance(arg) => write!( f, "Addresses passed in `{arg}` lack provenance, so this is similar to using a \ - `usize as ptr` cast (or [`core::ptr::from_exposed_addr`]) on each lane before \ - using it." + `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane \ + before using it." + ), + Self::PointerWrite(arg) => write!( + f, + "The pointer in `{arg}` must satisfy the requirements of [`core::ptr::write`]." ), Self::UnpredictableOnFault => write!( f, @@ -1055,23 +1059,8 @@ impl Intrinsic { /// Add a big endian implementation fn generate_big_endian(&self, variant: &mut Intrinsic) { - /* We can't always blindly reverse the bits only in certain conditions - * do we need a different order - thus this allows us to have the - * ability to do so without having to play codegolf with the yaml AST */ - let should_reverse = { - if let Some(should_reverse) = variant.big_endian_inverse { - should_reverse - } else if variant.compose.len() == 1 { - match &variant.compose[0] { - Expression::FnCall(fn_call) => fn_call.0.to_string() == "transmute", - _ => false, - } - } else { - false - } - }; - - if !should_reverse { + // We only reverse if it was specifically requested + if !variant.big_endian_inverse.unwrap_or(false) { return; } @@ -1139,7 +1128,7 @@ impl Intrinsic { } else { /* If we do not need to reorder anything then immediately add * the expressions from the big_endian_expressions and - * concatinate the compose vector */ + * concatenate the compose vector */ variant.big_endian_compose.extend(big_endian_expressions); variant .big_endian_compose @@ -1157,11 +1146,11 @@ impl Intrinsic { /* If we do not create a shuffle call we do not need modify the * return value and append to the big endian ast array. A bit confusing - * as in code we are making the final call before caputuring the return + * as in code we are making the final call before capturing the return * value of the intrinsic that has been called.*/ let ret_val_name = "ret_val".to_string(); if let Some(simd_shuffle_call) = create_shuffle_call(&ret_val_name, return_type) { - /* There is a possibility that the funcion arguments did not + /* There is a possibility that the function arguments did not * require big endian treatment, thus we need to now add the * original function body before appending the return value.*/ if variant.big_endian_compose.is_empty() { @@ -1187,9 +1176,10 @@ impl Intrinsic { * re-assigning each tuple however those generated calls do * not make the parent function return. So we add the return * value here */ - variant - .big_endian_compose - .push(create_symbol_identifier(&ret_val_name)); + variant.big_endian_compose.push(create_symbol_identifier( + &ret_val_name, + IdentifierType::Symbol, + )); } } } @@ -1695,8 +1685,8 @@ enum Endianness { NA, } -/// Based on the endianess will create the appropriate intrinsic, or simply -/// create the desired intrinsic without any endianess +/// Based on the endianness will create the appropriate intrinsic, or simply +/// create the desired intrinsic without any endianness fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut TokenStream) { let signature = &intrinsic.signature; let fn_name = signature.fn_name().to_string(); @@ -1736,7 +1726,7 @@ fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut Tok ); } - tokens.append_all(quote! { #[inline(always)] }); + tokens.append_all(quote! { #[inline] }); match endianness { Endianness::Little => tokens.append_all(quote! { #[cfg(target_endian = "little")] }), diff --git a/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs b/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs index 0f4de83dacb4a..cbd5df50de5b6 100644 --- a/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs +++ b/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs @@ -141,13 +141,6 @@ fn generate_single_test( } } - if fn_name.starts_with("svldff1") && fn_name.contains("gather") { - // TODO: We can remove this check when first-faulting gathers are fixed in CI's QEMU - // https://gitlab.com/qemu-project/qemu/-/issues/1612 - println!("Skipping test for {fn_name}"); - return Ok(quote!()); - } - let fn_ident = format_ident!("{fn_name}"); let test_name = format_ident!( "test_{fn_name}{}", diff --git a/stdarch/crates/stdarch-gen-arm/src/main.rs b/stdarch/crates/stdarch-gen-arm/src/main.rs index e14e2782485b9..b7e2aa416fb59 100644 --- a/stdarch/crates/stdarch-gen-arm/src/main.rs +++ b/stdarch/crates/stdarch-gen-arm/src/main.rs @@ -54,7 +54,7 @@ fn main() -> Result<(), String> { vv.into_iter().flatten().collect_vec() })?; - if filepath.ends_with("sve.spec.yml") || filepath.ends_with("sve2.spec.yml") { + if input.ctx.generate_load_store_tests { let loads = intrinsics.iter() .filter_map(|i| { if matches!(i.test, Test::Load(..)) { diff --git a/stdarch/crates/stdarch-gen-arm/src/typekinds.rs b/stdarch/crates/stdarch-gen-arm/src/typekinds.rs index bd47ff2bd1557..c3aa22294d9fc 100644 --- a/stdarch/crates/stdarch-gen-arm/src/typekinds.rs +++ b/stdarch/crates/stdarch-gen-arm/src/typekinds.rs @@ -289,9 +289,9 @@ impl TypeKind { ( BaseType::Sized(Float | Int | UInt, _), BaseType::Sized(Float | Int | UInt, _), - ) => Some(FnCall::new_expression( + ) => Some(FnCall::new_unsafe_expression( // Conversions between float and (u)int, or where the lane size changes. - "simd_reinterpret".parse().unwrap(), + "transmute_unchecked".parse().unwrap(), vec![expr.into()], )), _ => None, diff --git a/stdarch/crates/stdarch-gen-hexagon-scalar/Cargo.toml b/stdarch/crates/stdarch-gen-hexagon-scalar/Cargo.toml new file mode 100644 index 0000000000000..04bee944f4a91 --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon-scalar/Cargo.toml @@ -0,0 +1,9 @@ +[package] +name = "stdarch-gen-hexagon-scalar" +version = "0.1.0" +authors = ["The Rust Project Developers"] +license = "MIT OR Apache-2.0" +edition = "2021" + +[dependencies] +regex = "1.10" diff --git a/stdarch/crates/stdarch-gen-hexagon-scalar/hexagon_protos.h b/stdarch/crates/stdarch-gen-hexagon-scalar/hexagon_protos.h new file mode 100644 index 0000000000000..2642f3c8428d8 --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon-scalar/hexagon_protos.h @@ -0,0 +1,8439 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Automatically generated file, do not edit! +//===----------------------------------------------------------------------===// + + + +#ifndef __HEXAGON_PROTOS_H_ +#define __HEXAGON_PROTOS_H_ 1 + +/* ========================================================================== + Assembly Syntax: Rd32=abs(Rs32) + C Intrinsic Prototype: Word32 Q6_R_abs_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_abs_R __builtin_HEXAGON_A2_abs + +/* ========================================================================== + Assembly Syntax: Rdd32=abs(Rss32) + C Intrinsic Prototype: Word64 Q6_P_abs_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_abs_P __builtin_HEXAGON_A2_absp + +/* ========================================================================== + Assembly Syntax: Rd32=abs(Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_abs_R_sat(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_abs_R_sat __builtin_HEXAGON_A2_abssat + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_add_RR __builtin_HEXAGON_A2_add + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.h,Rs32.h):<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RhRh_s16 __builtin_HEXAGON_A2_addh_h16_hh + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.h,Rs32.l):<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RhRl_s16 __builtin_HEXAGON_A2_addh_h16_hl + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRh_s16 __builtin_HEXAGON_A2_addh_h16_lh + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRl_s16 __builtin_HEXAGON_A2_addh_h16_ll + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.h,Rs32.h):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RhRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hh + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.h,Rs32.l):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RhRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hl + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_lh + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_ll + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.h) + C Intrinsic Prototype: Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRh __builtin_HEXAGON_A2_addh_l16_hl + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.l) + C Intrinsic Prototype: Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRl __builtin_HEXAGON_A2_addh_l16_ll + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):sat + C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRh_sat __builtin_HEXAGON_A2_addh_l16_sat_hl + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):sat + C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_RlRl_sat __builtin_HEXAGON_A2_addh_l16_sat_ll + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,#s16) + C Intrinsic Prototype: Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16) + Instruction Type: ALU32_ADDI + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_add_RI __builtin_HEXAGON_A2_addi + +/* ========================================================================== + Assembly Syntax: Rdd32=add(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_add_PP __builtin_HEXAGON_A2_addp + +/* ========================================================================== + Assembly Syntax: Rdd32=add(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_add_PP_sat __builtin_HEXAGON_A2_addpsat + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_add_RR_sat __builtin_HEXAGON_A2_addsat + +/* ========================================================================== + Assembly Syntax: Rdd32=add(Rs32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_add_RP __builtin_HEXAGON_A2_addsp + +/* ========================================================================== + Assembly Syntax: Rd32=and(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_and_RR __builtin_HEXAGON_A2_and + +/* ========================================================================== + Assembly Syntax: Rd32=and(Rs32,#s10) + C Intrinsic Prototype: Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_and_RI __builtin_HEXAGON_A2_andir + +/* ========================================================================== + Assembly Syntax: Rdd32=and(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_and_PP __builtin_HEXAGON_A2_andp + +/* ========================================================================== + Assembly Syntax: Rd32=aslh(Rs32) + C Intrinsic Prototype: Word32 Q6_R_aslh_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_aslh_R __builtin_HEXAGON_A2_aslh + +/* ========================================================================== + Assembly Syntax: Rd32=asrh(Rs32) + C Intrinsic Prototype: Word32 Q6_R_asrh_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_asrh_R __builtin_HEXAGON_A2_asrh + +/* ========================================================================== + Assembly Syntax: Rd32=combine(Rt32.h,Rs32.h) + C Intrinsic Prototype: Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_combine_RhRh __builtin_HEXAGON_A2_combine_hh + +/* ========================================================================== + Assembly Syntax: Rd32=combine(Rt32.h,Rs32.l) + C Intrinsic Prototype: Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_combine_RhRl __builtin_HEXAGON_A2_combine_hl + +/* ========================================================================== + Assembly Syntax: Rd32=combine(Rt32.l,Rs32.h) + C Intrinsic Prototype: Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_combine_RlRh __builtin_HEXAGON_A2_combine_lh + +/* ========================================================================== + Assembly Syntax: Rd32=combine(Rt32.l,Rs32.l) + C Intrinsic Prototype: Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_combine_RlRl __builtin_HEXAGON_A2_combine_ll + +/* ========================================================================== + Assembly Syntax: Rdd32=combine(#s8,#S8) + C Intrinsic Prototype: Word64 Q6_P_combine_II(Word32 Is8, Word32 IS8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_combine_II __builtin_HEXAGON_A2_combineii + +/* ========================================================================== + Assembly Syntax: Rdd32=combine(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_combine_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_combine_RR __builtin_HEXAGON_A2_combinew + +/* ========================================================================== + Assembly Syntax: Rd32=max(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_max_RR __builtin_HEXAGON_A2_max + +/* ========================================================================== + Assembly Syntax: Rdd32=max(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_max_PP __builtin_HEXAGON_A2_maxp + +/* ========================================================================== + Assembly Syntax: Rd32=maxu(Rs32,Rt32) + C Intrinsic Prototype: UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_maxu_RR __builtin_HEXAGON_A2_maxu + +/* ========================================================================== + Assembly Syntax: Rdd32=maxu(Rss32,Rtt32) + C Intrinsic Prototype: UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_maxu_PP __builtin_HEXAGON_A2_maxup + +/* ========================================================================== + Assembly Syntax: Rd32=min(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_min_RR __builtin_HEXAGON_A2_min + +/* ========================================================================== + Assembly Syntax: Rdd32=min(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_min_PP __builtin_HEXAGON_A2_minp + +/* ========================================================================== + Assembly Syntax: Rd32=minu(Rt32,Rs32) + C Intrinsic Prototype: UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_minu_RR __builtin_HEXAGON_A2_minu + +/* ========================================================================== + Assembly Syntax: Rdd32=minu(Rtt32,Rss32) + C Intrinsic Prototype: UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_minu_PP __builtin_HEXAGON_A2_minup + +/* ========================================================================== + Assembly Syntax: Rd32=neg(Rs32) + C Intrinsic Prototype: Word32 Q6_R_neg_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_neg_R __builtin_HEXAGON_A2_neg + +/* ========================================================================== + Assembly Syntax: Rdd32=neg(Rss32) + C Intrinsic Prototype: Word64 Q6_P_neg_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_neg_P __builtin_HEXAGON_A2_negp + +/* ========================================================================== + Assembly Syntax: Rd32=neg(Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_neg_R_sat(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_neg_R_sat __builtin_HEXAGON_A2_negsat + +/* ========================================================================== + Assembly Syntax: Rd32=not(Rs32) + C Intrinsic Prototype: Word32 Q6_R_not_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_not_R __builtin_HEXAGON_A2_not + +/* ========================================================================== + Assembly Syntax: Rdd32=not(Rss32) + C Intrinsic Prototype: Word64 Q6_P_not_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_not_P __builtin_HEXAGON_A2_notp + +/* ========================================================================== + Assembly Syntax: Rd32=or(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_or_RR __builtin_HEXAGON_A2_or + +/* ========================================================================== + Assembly Syntax: Rd32=or(Rs32,#s10) + C Intrinsic Prototype: Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_or_RI __builtin_HEXAGON_A2_orir + +/* ========================================================================== + Assembly Syntax: Rdd32=or(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_or_PP __builtin_HEXAGON_A2_orp + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rss32):sat + C Intrinsic Prototype: Word32 Q6_R_round_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_P_sat __builtin_HEXAGON_A2_roundsat + +/* ========================================================================== + Assembly Syntax: Rd32=sat(Rss32) + C Intrinsic Prototype: Word32 Q6_R_sat_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sat_P __builtin_HEXAGON_A2_sat + +/* ========================================================================== + Assembly Syntax: Rd32=satb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_satb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_satb_R __builtin_HEXAGON_A2_satb + +/* ========================================================================== + Assembly Syntax: Rd32=sath(Rs32) + C Intrinsic Prototype: Word32 Q6_R_sath_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sath_R __builtin_HEXAGON_A2_sath + +/* ========================================================================== + Assembly Syntax: Rd32=satub(Rs32) + C Intrinsic Prototype: Word32 Q6_R_satub_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_satub_R __builtin_HEXAGON_A2_satub + +/* ========================================================================== + Assembly Syntax: Rd32=satuh(Rs32) + C Intrinsic Prototype: Word32 Q6_R_satuh_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_satuh_R __builtin_HEXAGON_A2_satuh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sub_RR __builtin_HEXAGON_A2_sub + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.h,Rs32.h):<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RhRh_s16 __builtin_HEXAGON_A2_subh_h16_hh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.h,Rs32.l):<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RhRl_s16 __builtin_HEXAGON_A2_subh_h16_hl + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRh_s16 __builtin_HEXAGON_A2_subh_h16_lh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRl_s16 __builtin_HEXAGON_A2_subh_h16_ll + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.h,Rs32.h):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RhRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.h,Rs32.l):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RhRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hl + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_lh + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):sat:<<16 + C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_ll + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h) + C Intrinsic Prototype: Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRh __builtin_HEXAGON_A2_subh_l16_hl + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l) + C Intrinsic Prototype: Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRl __builtin_HEXAGON_A2_subh_l16_ll + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):sat + C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRh_sat __builtin_HEXAGON_A2_subh_l16_sat_hl + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):sat + C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_RlRl_sat __builtin_HEXAGON_A2_subh_l16_sat_ll + +/* ========================================================================== + Assembly Syntax: Rdd32=sub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_sub_PP __builtin_HEXAGON_A2_subp + +/* ========================================================================== + Assembly Syntax: Rd32=sub(#s10,Rs32) + C Intrinsic Prototype: Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sub_IR __builtin_HEXAGON_A2_subri + +/* ========================================================================== + Assembly Syntax: Rd32=sub(Rt32,Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sub_RR_sat __builtin_HEXAGON_A2_subsat + +/* ========================================================================== + Assembly Syntax: Rd32=vaddh(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vaddh_RR __builtin_HEXAGON_A2_svaddh + +/* ========================================================================== + Assembly Syntax: Rd32=vaddh(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vaddh_RR_sat __builtin_HEXAGON_A2_svaddhs + +/* ========================================================================== + Assembly Syntax: Rd32=vadduh(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vadduh_RR_sat __builtin_HEXAGON_A2_svadduhs + +/* ========================================================================== + Assembly Syntax: Rd32=vavgh(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vavgh_RR __builtin_HEXAGON_A2_svavgh + +/* ========================================================================== + Assembly Syntax: Rd32=vavgh(Rs32,Rt32):rnd + C Intrinsic Prototype: Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vavgh_RR_rnd __builtin_HEXAGON_A2_svavghs + +/* ========================================================================== + Assembly Syntax: Rd32=vnavgh(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vnavgh_RR __builtin_HEXAGON_A2_svnavgh + +/* ========================================================================== + Assembly Syntax: Rd32=vsubh(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vsubh_RR __builtin_HEXAGON_A2_svsubh + +/* ========================================================================== + Assembly Syntax: Rd32=vsubh(Rt32,Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vsubh_RR_sat __builtin_HEXAGON_A2_svsubhs + +/* ========================================================================== + Assembly Syntax: Rd32=vsubuh(Rt32,Rs32):sat + C Intrinsic Prototype: Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vsubuh_RR_sat __builtin_HEXAGON_A2_svsubuhs + +/* ========================================================================== + Assembly Syntax: Rd32=swiz(Rs32) + C Intrinsic Prototype: Word32 Q6_R_swiz_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_swiz_R __builtin_HEXAGON_A2_swiz + +/* ========================================================================== + Assembly Syntax: Rd32=sxtb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_sxtb_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sxtb_R __builtin_HEXAGON_A2_sxtb + +/* ========================================================================== + Assembly Syntax: Rd32=sxth(Rs32) + C Intrinsic Prototype: Word32 Q6_R_sxth_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_sxth_R __builtin_HEXAGON_A2_sxth + +/* ========================================================================== + Assembly Syntax: Rdd32=sxtw(Rs32) + C Intrinsic Prototype: Word64 Q6_P_sxtw_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_sxtw_R __builtin_HEXAGON_A2_sxtw + +/* ========================================================================== + Assembly Syntax: Rd32=Rs32 + C Intrinsic Prototype: Word32 Q6_R_equals_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_equals_R __builtin_HEXAGON_A2_tfr + +/* ========================================================================== + Assembly Syntax: Rx32.h=#u16 + C Intrinsic Prototype: Word32 Q6_Rh_equals_I(Word32 Rx, Word32 Iu16) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Rh_equals_I __builtin_HEXAGON_A2_tfrih + +/* ========================================================================== + Assembly Syntax: Rx32.l=#u16 + C Intrinsic Prototype: Word32 Q6_Rl_equals_I(Word32 Rx, Word32 Iu16) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Rl_equals_I __builtin_HEXAGON_A2_tfril + +/* ========================================================================== + Assembly Syntax: Rdd32=Rss32 + C Intrinsic Prototype: Word64 Q6_P_equals_P(Word64 Rss) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_equals_P __builtin_HEXAGON_A2_tfrp + +/* ========================================================================== + Assembly Syntax: Rdd32=#s8 + C Intrinsic Prototype: Word64 Q6_P_equals_I(Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_equals_I __builtin_HEXAGON_A2_tfrpi + +/* ========================================================================== + Assembly Syntax: Rd32=#s16 + C Intrinsic Prototype: Word32 Q6_R_equals_I(Word32 Is16) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_equals_I __builtin_HEXAGON_A2_tfrsi + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsh(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsh_P __builtin_HEXAGON_A2_vabsh + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsh(Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vabsh_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsh_P_sat __builtin_HEXAGON_A2_vabshsat + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsw(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsw_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsw_P __builtin_HEXAGON_A2_vabsw + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsw(Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vabsw_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsw_P_sat __builtin_HEXAGON_A2_vabswsat + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vaddb_PP __builtin_HEXAGON_A2_vaddb_map + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddh_PP __builtin_HEXAGON_A2_vaddh + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddh_PP_sat __builtin_HEXAGON_A2_vaddhs + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddub_PP __builtin_HEXAGON_A2_vaddub + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddub(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vaddub_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddub_PP_sat __builtin_HEXAGON_A2_vaddubs + +/* ========================================================================== + Assembly Syntax: Rdd32=vadduh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vadduh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vadduh_PP_sat __builtin_HEXAGON_A2_vadduhs + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddw_PP __builtin_HEXAGON_A2_vaddw + +/* ========================================================================== + Assembly Syntax: Rdd32=vaddw(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaddw_PP_sat __builtin_HEXAGON_A2_vaddws + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgh_PP __builtin_HEXAGON_A2_vavgh + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32):crnd + C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgh_PP_crnd __builtin_HEXAGON_A2_vavghcr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgh_PP_rnd __builtin_HEXAGON_A2_vavghr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgub_PP __builtin_HEXAGON_A2_vavgub + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgub(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgub_PP_rnd __builtin_HEXAGON_A2_vavgubr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavguh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavguh_PP __builtin_HEXAGON_A2_vavguh + +/* ========================================================================== + Assembly Syntax: Rdd32=vavguh(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavguh_PP_rnd __builtin_HEXAGON_A2_vavguhr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavguw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavguw_PP __builtin_HEXAGON_A2_vavguw + +/* ========================================================================== + Assembly Syntax: Rdd32=vavguw(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavguw_PP_rnd __builtin_HEXAGON_A2_vavguwr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgw_PP __builtin_HEXAGON_A2_vavgw + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32):crnd + C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgw_PP_crnd __builtin_HEXAGON_A2_vavgwcr + +/* ========================================================================== + Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32):rnd + C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vavgw_PP_rnd __builtin_HEXAGON_A2_vavgwr + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_eq_PP __builtin_HEXAGON_A2_vcmpbeq + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.gtu(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_gtu_PP __builtin_HEXAGON_A2_vcmpbgtu + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_eq_PP __builtin_HEXAGON_A2_vcmpheq + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_gt_PP __builtin_HEXAGON_A2_vcmphgt + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.gtu(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_gtu_PP __builtin_HEXAGON_A2_vcmphgtu + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_eq_PP __builtin_HEXAGON_A2_vcmpweq + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_gt_PP __builtin_HEXAGON_A2_vcmpwgt + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.gtu(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_gtu_PP __builtin_HEXAGON_A2_vcmpwgtu + +/* ========================================================================== + Assembly Syntax: Rdd32=vconj(Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vconj_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vconj_P_sat __builtin_HEXAGON_A2_vconj + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxb(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxb_PP __builtin_HEXAGON_A2_vmaxb + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxh_PP __builtin_HEXAGON_A2_vmaxh + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxub_PP __builtin_HEXAGON_A2_vmaxub + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxuh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxuh_PP __builtin_HEXAGON_A2_vmaxuh + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxuw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxuw_PP __builtin_HEXAGON_A2_vmaxuw + +/* ========================================================================== + Assembly Syntax: Rdd32=vmaxw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmaxw_PP __builtin_HEXAGON_A2_vmaxw + +/* ========================================================================== + Assembly Syntax: Rdd32=vminb(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminb_PP __builtin_HEXAGON_A2_vminb + +/* ========================================================================== + Assembly Syntax: Rdd32=vminh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminh_PP __builtin_HEXAGON_A2_vminh + +/* ========================================================================== + Assembly Syntax: Rdd32=vminub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminub_PP __builtin_HEXAGON_A2_vminub + +/* ========================================================================== + Assembly Syntax: Rdd32=vminuh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminuh_PP __builtin_HEXAGON_A2_vminuh + +/* ========================================================================== + Assembly Syntax: Rdd32=vminuw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminuw_PP __builtin_HEXAGON_A2_vminuw + +/* ========================================================================== + Assembly Syntax: Rdd32=vminw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vminw_PP __builtin_HEXAGON_A2_vminw + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgh_PP __builtin_HEXAGON_A2_vnavgh + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32):crnd:sat + C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgh_PP_crnd_sat __builtin_HEXAGON_A2_vnavghcr + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgh_PP_rnd_sat __builtin_HEXAGON_A2_vnavghr + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgw_PP __builtin_HEXAGON_A2_vnavgw + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32):crnd:sat + C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgw_PP_crnd_sat __builtin_HEXAGON_A2_vnavgwcr + +/* ========================================================================== + Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vnavgw_PP_rnd_sat __builtin_HEXAGON_A2_vnavgwr + +/* ========================================================================== + Assembly Syntax: Rdd32=vraddub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vraddub_PP __builtin_HEXAGON_A2_vraddub + +/* ========================================================================== + Assembly Syntax: Rxx32+=vraddub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vraddubacc_PP __builtin_HEXAGON_A2_vraddub_acc + +/* ========================================================================== + Assembly Syntax: Rdd32=vrsadub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrsadub_PP __builtin_HEXAGON_A2_vrsadub + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrsadub(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrsadubacc_PP __builtin_HEXAGON_A2_vrsadub_acc + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vsubb_PP __builtin_HEXAGON_A2_vsubb_map + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubh_PP __builtin_HEXAGON_A2_vsubh + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubh(Rtt32,Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubh_PP_sat __builtin_HEXAGON_A2_vsubhs + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubub_PP __builtin_HEXAGON_A2_vsubub + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubub(Rtt32,Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubub_PP_sat __builtin_HEXAGON_A2_vsububs + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubuh(Rtt32,Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubuh_PP_sat __builtin_HEXAGON_A2_vsubuhs + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubw_PP __builtin_HEXAGON_A2_vsubw + +/* ========================================================================== + Assembly Syntax: Rdd32=vsubw(Rtt32,Rss32):sat + C Intrinsic Prototype: Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsubw_PP_sat __builtin_HEXAGON_A2_vsubws + +/* ========================================================================== + Assembly Syntax: Rd32=xor(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_xor_RR __builtin_HEXAGON_A2_xor + +/* ========================================================================== + Assembly Syntax: Rdd32=xor(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_xor_PP __builtin_HEXAGON_A2_xorp + +/* ========================================================================== + Assembly Syntax: Rd32=zxtb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_zxtb_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_zxtb_R __builtin_HEXAGON_A2_zxtb + +/* ========================================================================== + Assembly Syntax: Rd32=zxth(Rs32) + C Intrinsic Prototype: Word32 Q6_R_zxth_R(Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_zxth_R __builtin_HEXAGON_A2_zxth + +/* ========================================================================== + Assembly Syntax: Rd32=and(Rt32,~Rs32) + C Intrinsic Prototype: Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_and_RnR __builtin_HEXAGON_A4_andn + +/* ========================================================================== + Assembly Syntax: Rdd32=and(Rtt32,~Rss32) + C Intrinsic Prototype: Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_and_PnP __builtin_HEXAGON_A4_andnp + +/* ========================================================================== + Assembly Syntax: Rdd32=bitsplit(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_bitsplit_RR __builtin_HEXAGON_A4_bitsplit + +/* ========================================================================== + Assembly Syntax: Rdd32=bitsplit(Rs32,#u5) + C Intrinsic Prototype: Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_bitsplit_RI __builtin_HEXAGON_A4_bitspliti + +/* ========================================================================== + Assembly Syntax: Pd4=boundscheck(Rs32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_boundscheck_RP __builtin_HEXAGON_A4_boundscheck + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_eq_RR __builtin_HEXAGON_A4_cmpbeq + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.eq(Rs32,#u8) + C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_eq_RI __builtin_HEXAGON_A4_cmpbeqi + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_gt_RR __builtin_HEXAGON_A4_cmpbgt + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.gt(Rs32,#s8) + C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_gt_RI __builtin_HEXAGON_A4_cmpbgti + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.gtu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_gtu_RR __builtin_HEXAGON_A4_cmpbgtu + +/* ========================================================================== + Assembly Syntax: Pd4=cmpb.gtu(Rs32,#u7) + C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmpb_gtu_RI __builtin_HEXAGON_A4_cmpbgtui + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_eq_RR __builtin_HEXAGON_A4_cmpheq + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.eq(Rs32,#s8) + C Intrinsic Prototype: Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_eq_RI __builtin_HEXAGON_A4_cmpheqi + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_gt_RR __builtin_HEXAGON_A4_cmphgt + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.gt(Rs32,#s8) + C Intrinsic Prototype: Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_gt_RI __builtin_HEXAGON_A4_cmphgti + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.gtu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_gtu_RR __builtin_HEXAGON_A4_cmphgtu + +/* ========================================================================== + Assembly Syntax: Pd4=cmph.gtu(Rs32,#u7) + C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmph_gtu_RI __builtin_HEXAGON_A4_cmphgtui + +/* ========================================================================== + Assembly Syntax: Rdd32=combine(#s8,Rs32) + C Intrinsic Prototype: Word64 Q6_P_combine_IR(Word32 Is8, Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_combine_IR __builtin_HEXAGON_A4_combineir + +/* ========================================================================== + Assembly Syntax: Rdd32=combine(Rs32,#s8) + C Intrinsic Prototype: Word64 Q6_P_combine_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_combine_RI __builtin_HEXAGON_A4_combineri + +/* ========================================================================== + Assembly Syntax: Rd32=cround(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_cround_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cround_RI __builtin_HEXAGON_A4_cround_ri + +/* ========================================================================== + Assembly Syntax: Rd32=cround(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cround_RR __builtin_HEXAGON_A4_cround_rr + +/* ========================================================================== + Assembly Syntax: Rd32=modwrap(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_modwrap_RR __builtin_HEXAGON_A4_modwrapu + +/* ========================================================================== + Assembly Syntax: Rd32=or(Rt32,~Rs32) + C Intrinsic Prototype: Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_or_RnR __builtin_HEXAGON_A4_orn + +/* ========================================================================== + Assembly Syntax: Rdd32=or(Rtt32,~Rss32) + C Intrinsic Prototype: Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_or_PnP __builtin_HEXAGON_A4_ornp + +/* ========================================================================== + Assembly Syntax: Rd32=cmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_cmp_eq_RR __builtin_HEXAGON_A4_rcmpeq + +/* ========================================================================== + Assembly Syntax: Rd32=cmp.eq(Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_cmp_eq_RI __builtin_HEXAGON_A4_rcmpeqi + +/* ========================================================================== + Assembly Syntax: Rd32=!cmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_not_cmp_eq_RR __builtin_HEXAGON_A4_rcmpneq + +/* ========================================================================== + Assembly Syntax: Rd32=!cmp.eq(Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_not_cmp_eq_RI __builtin_HEXAGON_A4_rcmpneqi + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_RI __builtin_HEXAGON_A4_round_ri + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rs32,#u5):sat + C Intrinsic Prototype: Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_RI_sat __builtin_HEXAGON_A4_round_ri_sat + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_RR __builtin_HEXAGON_A4_round_rr + +/* ========================================================================== + Assembly Syntax: Rd32=round(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_round_RR_sat __builtin_HEXAGON_A4_round_rr_sat + +/* ========================================================================== + Assembly Syntax: Pd4=tlbmatch(Rss32,Rt32) + C Intrinsic Prototype: Byte Q6_p_tlbmatch_PR(Word64 Rss, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_tlbmatch_PR __builtin_HEXAGON_A4_tlbmatch + +/* ========================================================================== + Assembly Syntax: Pd4=any8(vcmpb.eq(Rss32,Rtt32)) + C Intrinsic Prototype: Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_any8_vcmpb_eq_PP __builtin_HEXAGON_A4_vcmpbeq_any + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.eq(Rss32,#u8) + C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 Iu8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_eq_PI __builtin_HEXAGON_A4_vcmpbeqi + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_gt_PP __builtin_HEXAGON_A4_vcmpbgt + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.gt(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_gt_PI __builtin_HEXAGON_A4_vcmpbgti + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpb.gtu(Rss32,#u7) + C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpb_gtu_PI __builtin_HEXAGON_A4_vcmpbgtui + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.eq(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_eq_PI __builtin_HEXAGON_A4_vcmpheqi + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.gt(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_gt_PI __builtin_HEXAGON_A4_vcmphgti + +/* ========================================================================== + Assembly Syntax: Pd4=vcmph.gtu(Rss32,#u7) + C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmph_gtu_PI __builtin_HEXAGON_A4_vcmphgtui + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.eq(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_eq_PI __builtin_HEXAGON_A4_vcmpweqi + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.gt(Rss32,#s8) + C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 Is8) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_gt_PI __builtin_HEXAGON_A4_vcmpwgti + +/* ========================================================================== + Assembly Syntax: Pd4=vcmpw.gtu(Rss32,#u7) + C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 Iu7) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_vcmpw_gtu_PI __builtin_HEXAGON_A4_vcmpwgtui + +/* ========================================================================== + Assembly Syntax: Rxx32=vrmaxh(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmaxh_PR __builtin_HEXAGON_A4_vrmaxh + +/* ========================================================================== + Assembly Syntax: Rxx32=vrmaxuh(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmaxuh_PR __builtin_HEXAGON_A4_vrmaxuh + +/* ========================================================================== + Assembly Syntax: Rxx32=vrmaxuw(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmaxuw_PR __builtin_HEXAGON_A4_vrmaxuw + +/* ========================================================================== + Assembly Syntax: Rxx32=vrmaxw(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmaxw_PR __builtin_HEXAGON_A4_vrmaxw + +/* ========================================================================== + Assembly Syntax: Rxx32=vrminh(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrminh_PR __builtin_HEXAGON_A4_vrminh + +/* ========================================================================== + Assembly Syntax: Rxx32=vrminuh(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrminuh_PR __builtin_HEXAGON_A4_vrminuh + +/* ========================================================================== + Assembly Syntax: Rxx32=vrminuw(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrminuw_PR __builtin_HEXAGON_A4_vrminuw + +/* ========================================================================== + Assembly Syntax: Rxx32=vrminw(Rss32,Ru32) + C Intrinsic Prototype: Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrminw_PR __builtin_HEXAGON_A4_vrminw + +/* ========================================================================== + Assembly Syntax: Rd32=vaddhub(Rss32,Rtt32):sat + C Intrinsic Prototype: Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vaddhub_PP_sat __builtin_HEXAGON_A5_vaddhubs + +/* ========================================================================== + Assembly Syntax: Pd4=all8(Ps4) + C Intrinsic Prototype: Byte Q6_p_all8_p(Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_all8_p __builtin_HEXAGON_C2_all8 + +/* ========================================================================== + Assembly Syntax: Pd4=and(Pt4,Ps4) + C Intrinsic Prototype: Byte Q6_p_and_pp(Byte Pt, Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_pp __builtin_HEXAGON_C2_and + +/* ========================================================================== + Assembly Syntax: Pd4=and(Pt4,!Ps4) + C Intrinsic Prototype: Byte Q6_p_and_pnp(Byte Pt, Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_pnp __builtin_HEXAGON_C2_andn + +/* ========================================================================== + Assembly Syntax: Pd4=any8(Ps4) + C Intrinsic Prototype: Byte Q6_p_any8_p(Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_any8_p __builtin_HEXAGON_C2_any8 + +/* ========================================================================== + Assembly Syntax: Pd4=bitsclr(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_bitsclr_RR __builtin_HEXAGON_C2_bitsclr + +/* ========================================================================== + Assembly Syntax: Pd4=bitsclr(Rs32,#u6) + C Intrinsic Prototype: Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_bitsclr_RI __builtin_HEXAGON_C2_bitsclri + +/* ========================================================================== + Assembly Syntax: Pd4=bitsset(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_bitsset_RR __builtin_HEXAGON_C2_bitsset + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_eq_RR __builtin_HEXAGON_C2_cmpeq + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.eq(Rs32,#s10) + C Intrinsic Prototype: Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_eq_RI __builtin_HEXAGON_C2_cmpeqi + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmp_eq_PP __builtin_HEXAGON_C2_cmpeqp + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.ge(Rs32,#s8) + C Intrinsic Prototype: Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_ge_RI __builtin_HEXAGON_C2_cmpgei + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.geu(Rs32,#u8) + C Intrinsic Prototype: Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_geu_RI __builtin_HEXAGON_C2_cmpgeui + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_gt_RR __builtin_HEXAGON_C2_cmpgt + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gt(Rs32,#s10) + C Intrinsic Prototype: Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_gt_RI __builtin_HEXAGON_C2_cmpgti + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmp_gt_PP __builtin_HEXAGON_C2_cmpgtp + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gtu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_gtu_RR __builtin_HEXAGON_C2_cmpgtu + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gtu(Rs32,#u9) + C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_gtu_RI __builtin_HEXAGON_C2_cmpgtui + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.gtu(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_cmp_gtu_PP __builtin_HEXAGON_C2_cmpgtup + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.lt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_lt_RR __builtin_HEXAGON_C2_cmplt + +/* ========================================================================== + Assembly Syntax: Pd4=cmp.ltu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_cmp_ltu_RR __builtin_HEXAGON_C2_cmpltu + +/* ========================================================================== + Assembly Syntax: Rdd32=mask(Pt4) + C Intrinsic Prototype: Word64 Q6_P_mask_p(Byte Pt) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mask_p __builtin_HEXAGON_C2_mask + +/* ========================================================================== + Assembly Syntax: Rd32=mux(Pu4,Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mux_pRR __builtin_HEXAGON_C2_mux + +/* ========================================================================== + Assembly Syntax: Rd32=mux(Pu4,#s8,#S8) + C Intrinsic Prototype: Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, Word32 IS8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mux_pII __builtin_HEXAGON_C2_muxii + +/* ========================================================================== + Assembly Syntax: Rd32=mux(Pu4,Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, Word32 Is8) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mux_pRI __builtin_HEXAGON_C2_muxir + +/* ========================================================================== + Assembly Syntax: Rd32=mux(Pu4,#s8,Rs32) + C Intrinsic Prototype: Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, Word32 Rs) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mux_pIR __builtin_HEXAGON_C2_muxri + +/* ========================================================================== + Assembly Syntax: Pd4=not(Ps4) + C Intrinsic Prototype: Byte Q6_p_not_p(Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_p __builtin_HEXAGON_C2_not + +/* ========================================================================== + Assembly Syntax: Pd4=or(Pt4,Ps4) + C Intrinsic Prototype: Byte Q6_p_or_pp(Byte Pt, Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_pp __builtin_HEXAGON_C2_or + +/* ========================================================================== + Assembly Syntax: Pd4=or(Pt4,!Ps4) + C Intrinsic Prototype: Byte Q6_p_or_pnp(Byte Pt, Byte Ps) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_pnp __builtin_HEXAGON_C2_orn + +/* ========================================================================== + Assembly Syntax: Pd4=Ps4 + C Intrinsic Prototype: Byte Q6_p_equals_p(Byte Ps) + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_equals_p __builtin_HEXAGON_C2_pxfer_map + +/* ========================================================================== + Assembly Syntax: Rd32=Ps4 + C Intrinsic Prototype: Word32 Q6_R_equals_p(Byte Ps) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_equals_p __builtin_HEXAGON_C2_tfrpr + +/* ========================================================================== + Assembly Syntax: Pd4=Rs32 + C Intrinsic Prototype: Byte Q6_p_equals_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_equals_R __builtin_HEXAGON_C2_tfrrp + +/* ========================================================================== + Assembly Syntax: Rd32=vitpack(Ps4,Pt4) + C Intrinsic Prototype: Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vitpack_pp __builtin_HEXAGON_C2_vitpack + +/* ========================================================================== + Assembly Syntax: Rdd32=vmux(Pu4,Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vmux_pPP(Byte Pu, Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmux_pPP __builtin_HEXAGON_C2_vmux + +/* ========================================================================== + Assembly Syntax: Pd4=xor(Ps4,Pt4) + C Intrinsic Prototype: Byte Q6_p_xor_pp(Byte Ps, Byte Pt) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_xor_pp __builtin_HEXAGON_C2_xor + +/* ========================================================================== + Assembly Syntax: Pd4=and(Ps4,and(Pt4,Pu4)) + C Intrinsic Prototype: Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_and_ppp __builtin_HEXAGON_C4_and_and + +/* ========================================================================== + Assembly Syntax: Pd4=and(Ps4,and(Pt4,!Pu4)) + C Intrinsic Prototype: Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_and_ppnp __builtin_HEXAGON_C4_and_andn + +/* ========================================================================== + Assembly Syntax: Pd4=and(Ps4,or(Pt4,Pu4)) + C Intrinsic Prototype: Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_or_ppp __builtin_HEXAGON_C4_and_or + +/* ========================================================================== + Assembly Syntax: Pd4=and(Ps4,or(Pt4,!Pu4)) + C Intrinsic Prototype: Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_and_or_ppnp __builtin_HEXAGON_C4_and_orn + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_gt_RR __builtin_HEXAGON_C4_cmplte + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.gt(Rs32,#s10) + C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_gt_RI __builtin_HEXAGON_C4_cmpltei + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.gtu(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_gtu_RR __builtin_HEXAGON_C4_cmplteu + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.gtu(Rs32,#u9) + C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 Iu9) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_gtu_RI __builtin_HEXAGON_C4_cmplteui + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_eq_RR __builtin_HEXAGON_C4_cmpneq + +/* ========================================================================== + Assembly Syntax: Pd4=!cmp.eq(Rs32,#s10) + C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 Is10) + Instruction Type: ALU32_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_p_not_cmp_eq_RI __builtin_HEXAGON_C4_cmpneqi + +/* ========================================================================== + Assembly Syntax: Pd4=fastcorner9(Ps4,Pt4) + C Intrinsic Prototype: Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9 + +/* ========================================================================== + Assembly Syntax: Pd4=!fastcorner9(Ps4,Pt4) + C Intrinsic Prototype: Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte Pt) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9_not + +/* ========================================================================== + Assembly Syntax: Pd4=!bitsclr(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_bitsclr_RR __builtin_HEXAGON_C4_nbitsclr + +/* ========================================================================== + Assembly Syntax: Pd4=!bitsclr(Rs32,#u6) + C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_bitsclr_RI __builtin_HEXAGON_C4_nbitsclri + +/* ========================================================================== + Assembly Syntax: Pd4=!bitsset(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_bitsset_RR __builtin_HEXAGON_C4_nbitsset + +/* ========================================================================== + Assembly Syntax: Pd4=or(Ps4,and(Pt4,Pu4)) + C Intrinsic Prototype: Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_and_ppp __builtin_HEXAGON_C4_or_and + +/* ========================================================================== + Assembly Syntax: Pd4=or(Ps4,and(Pt4,!Pu4)) + C Intrinsic Prototype: Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_and_ppnp __builtin_HEXAGON_C4_or_andn + +/* ========================================================================== + Assembly Syntax: Pd4=or(Ps4,or(Pt4,Pu4)) + C Intrinsic Prototype: Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_or_ppp __builtin_HEXAGON_C4_or_or + +/* ========================================================================== + Assembly Syntax: Pd4=or(Ps4,or(Pt4,!Pu4)) + C Intrinsic Prototype: Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte Pu) + Instruction Type: CR + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_or_or_ppnp __builtin_HEXAGON_C4_or_orn + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_d2df(Rss32) + C Intrinsic Prototype: Float64 Q6_P_convert_d2df_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_d2df_P __builtin_HEXAGON_F2_conv_d2df + +/* ========================================================================== + Assembly Syntax: Rd32=convert_d2sf(Rss32) + C Intrinsic Prototype: Float32 Q6_R_convert_d2sf_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_d2sf_P __builtin_HEXAGON_F2_conv_d2sf + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_df2d(Rss32) + C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_df2d_P __builtin_HEXAGON_F2_conv_df2d + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_df2d(Rss32):chop + C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P_chop(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_df2d_P_chop __builtin_HEXAGON_F2_conv_df2d_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2sf(Rss32) + C Intrinsic Prototype: Float32 Q6_R_convert_df2sf_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2sf_P __builtin_HEXAGON_F2_conv_df2sf + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_df2ud(Rss32) + C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_df2ud_P __builtin_HEXAGON_F2_conv_df2ud + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_df2ud(Rss32):chop + C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P_chop(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_df2ud_P_chop __builtin_HEXAGON_F2_conv_df2ud_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2uw(Rss32) + C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2uw_P __builtin_HEXAGON_F2_conv_df2uw + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2uw(Rss32):chop + C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P_chop(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2uw_P_chop __builtin_HEXAGON_F2_conv_df2uw_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2w(Rss32) + C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2w_P __builtin_HEXAGON_F2_conv_df2w + +/* ========================================================================== + Assembly Syntax: Rd32=convert_df2w(Rss32):chop + C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P_chop(Float64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_df2w_P_chop __builtin_HEXAGON_F2_conv_df2w_chop + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2d(Rs32) + C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2d_R __builtin_HEXAGON_F2_conv_sf2d + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2d(Rs32):chop + C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R_chop(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2d_R_chop __builtin_HEXAGON_F2_conv_sf2d_chop + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2df(Rs32) + C Intrinsic Prototype: Float64 Q6_P_convert_sf2df_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2df_R __builtin_HEXAGON_F2_conv_sf2df + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2ud(Rs32) + C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2ud_R __builtin_HEXAGON_F2_conv_sf2ud + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_sf2ud(Rs32):chop + C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R_chop(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_sf2ud_R_chop __builtin_HEXAGON_F2_conv_sf2ud_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_sf2uw(Rs32) + C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_sf2uw_R __builtin_HEXAGON_F2_conv_sf2uw + +/* ========================================================================== + Assembly Syntax: Rd32=convert_sf2uw(Rs32):chop + C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R_chop(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_sf2uw_R_chop __builtin_HEXAGON_F2_conv_sf2uw_chop + +/* ========================================================================== + Assembly Syntax: Rd32=convert_sf2w(Rs32) + C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_sf2w_R __builtin_HEXAGON_F2_conv_sf2w + +/* ========================================================================== + Assembly Syntax: Rd32=convert_sf2w(Rs32):chop + C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R_chop(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_sf2w_R_chop __builtin_HEXAGON_F2_conv_sf2w_chop + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_ud2df(Rss32) + C Intrinsic Prototype: Float64 Q6_P_convert_ud2df_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_ud2df_P __builtin_HEXAGON_F2_conv_ud2df + +/* ========================================================================== + Assembly Syntax: Rd32=convert_ud2sf(Rss32) + C Intrinsic Prototype: Float32 Q6_R_convert_ud2sf_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_ud2sf_P __builtin_HEXAGON_F2_conv_ud2sf + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_uw2df(Rs32) + C Intrinsic Prototype: Float64 Q6_P_convert_uw2df_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_uw2df_R __builtin_HEXAGON_F2_conv_uw2df + +/* ========================================================================== + Assembly Syntax: Rd32=convert_uw2sf(Rs32) + C Intrinsic Prototype: Float32 Q6_R_convert_uw2sf_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_uw2sf_R __builtin_HEXAGON_F2_conv_uw2sf + +/* ========================================================================== + Assembly Syntax: Rdd32=convert_w2df(Rs32) + C Intrinsic Prototype: Float64 Q6_P_convert_w2df_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_convert_w2df_R __builtin_HEXAGON_F2_conv_w2df + +/* ========================================================================== + Assembly Syntax: Rd32=convert_w2sf(Rs32) + C Intrinsic Prototype: Float32 Q6_R_convert_w2sf_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_convert_w2sf_R __builtin_HEXAGON_F2_conv_w2sf + +/* ========================================================================== + Assembly Syntax: Pd4=dfclass(Rss32,#u5) + C Intrinsic Prototype: Byte Q6_p_dfclass_PI(Float64 Rss, Word32 Iu5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfclass_PI __builtin_HEXAGON_F2_dfclass + +/* ========================================================================== + Assembly Syntax: Pd4=dfcmp.eq(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_dfcmp_eq_PP(Float64 Rss, Float64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfcmp_eq_PP __builtin_HEXAGON_F2_dfcmpeq + +/* ========================================================================== + Assembly Syntax: Pd4=dfcmp.ge(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_dfcmp_ge_PP(Float64 Rss, Float64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfcmp_ge_PP __builtin_HEXAGON_F2_dfcmpge + +/* ========================================================================== + Assembly Syntax: Pd4=dfcmp.gt(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_dfcmp_gt_PP(Float64 Rss, Float64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfcmp_gt_PP __builtin_HEXAGON_F2_dfcmpgt + +/* ========================================================================== + Assembly Syntax: Pd4=dfcmp.uo(Rss32,Rtt32) + C Intrinsic Prototype: Byte Q6_p_dfcmp_uo_PP(Float64 Rss, Float64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_dfcmp_uo_PP __builtin_HEXAGON_F2_dfcmpuo + +/* ========================================================================== + Assembly Syntax: Rdd32=dfmake(#u10):neg + C Intrinsic Prototype: Float64 Q6_P_dfmake_I_neg(Word32 Iu10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmake_I_neg __builtin_HEXAGON_F2_dfimm_n + +/* ========================================================================== + Assembly Syntax: Rdd32=dfmake(#u10):pos + C Intrinsic Prototype: Float64 Q6_P_dfmake_I_pos(Word32 Iu10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmake_I_pos __builtin_HEXAGON_F2_dfimm_p + +/* ========================================================================== + Assembly Syntax: Rd32=sfadd(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfadd_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfadd_RR __builtin_HEXAGON_F2_sfadd + +/* ========================================================================== + Assembly Syntax: Pd4=sfclass(Rs32,#u5) + C Intrinsic Prototype: Byte Q6_p_sfclass_RI(Float32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfclass_RI __builtin_HEXAGON_F2_sfclass + +/* ========================================================================== + Assembly Syntax: Pd4=sfcmp.eq(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_sfcmp_eq_RR(Float32 Rs, Float32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfcmp_eq_RR __builtin_HEXAGON_F2_sfcmpeq + +/* ========================================================================== + Assembly Syntax: Pd4=sfcmp.ge(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_sfcmp_ge_RR(Float32 Rs, Float32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfcmp_ge_RR __builtin_HEXAGON_F2_sfcmpge + +/* ========================================================================== + Assembly Syntax: Pd4=sfcmp.gt(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_sfcmp_gt_RR(Float32 Rs, Float32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfcmp_gt_RR __builtin_HEXAGON_F2_sfcmpgt + +/* ========================================================================== + Assembly Syntax: Pd4=sfcmp.uo(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_sfcmp_uo_RR(Float32 Rs, Float32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_sfcmp_uo_RR __builtin_HEXAGON_F2_sfcmpuo + +/* ========================================================================== + Assembly Syntax: Rd32=sffixupd(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sffixupd_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sffixupd_RR __builtin_HEXAGON_F2_sffixupd + +/* ========================================================================== + Assembly Syntax: Rd32=sffixupn(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sffixupn_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sffixupn_RR __builtin_HEXAGON_F2_sffixupn + +/* ========================================================================== + Assembly Syntax: Rd32=sffixupr(Rs32) + C Intrinsic Prototype: Float32 Q6_R_sffixupr_R(Float32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sffixupr_R __builtin_HEXAGON_F2_sffixupr + +/* ========================================================================== + Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR(Float32 Rx, Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpyacc_RR __builtin_HEXAGON_F2_sffma + +/* ========================================================================== + Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32):lib + C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpyacc_RR_lib __builtin_HEXAGON_F2_sffma_lib + +/* ========================================================================== + Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32,Pu4):scale + C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RRp_scale(Float32 Rx, Float32 Rs, Float32 Rt, Byte Pu) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpyacc_RRp_scale __builtin_HEXAGON_F2_sffma_sc + +/* ========================================================================== + Assembly Syntax: Rx32-=sfmpy(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR(Float32 Rx, Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpynac_RR __builtin_HEXAGON_F2_sffms + +/* ========================================================================== + Assembly Syntax: Rx32-=sfmpy(Rs32,Rt32):lib + C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpynac_RR_lib __builtin_HEXAGON_F2_sffms_lib + +/* ========================================================================== + Assembly Syntax: Rd32=sfmake(#u10):neg + C Intrinsic Prototype: Float32 Q6_R_sfmake_I_neg(Word32 Iu10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmake_I_neg __builtin_HEXAGON_F2_sfimm_n + +/* ========================================================================== + Assembly Syntax: Rd32=sfmake(#u10):pos + C Intrinsic Prototype: Float32 Q6_R_sfmake_I_pos(Word32 Iu10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmake_I_pos __builtin_HEXAGON_F2_sfimm_p + +/* ========================================================================== + Assembly Syntax: Rd32=sfmax(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmax_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmax_RR __builtin_HEXAGON_F2_sfmax + +/* ========================================================================== + Assembly Syntax: Rd32=sfmin(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmin_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmin_RR __builtin_HEXAGON_F2_sfmin + +/* ========================================================================== + Assembly Syntax: Rd32=sfmpy(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfmpy_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfmpy_RR __builtin_HEXAGON_F2_sfmpy + +/* ========================================================================== + Assembly Syntax: Rd32=sfsub(Rs32,Rt32) + C Intrinsic Prototype: Float32 Q6_R_sfsub_RR(Float32 Rs, Float32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sfsub_RR __builtin_HEXAGON_F2_sfsub + +/* ========================================================================== + Assembly Syntax: Rd32=memb(Rx32++#s4:0:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memb_IM_circ __builtin_HEXAGON_L2_loadrb_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memb(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memb_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memb_M_circ __builtin_HEXAGON_L2_loadrb_pcr + +/* ========================================================================== + Assembly Syntax: Rdd32=memd(Rx32++#s4:3:circ(Mu2)) + C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ(void** Rx, Word32 Is4_3, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_P_memd_IM_circ __builtin_HEXAGON_L2_loadrd_pci + +/* ========================================================================== + Assembly Syntax: Rdd32=memd(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word64 Q6_P_memd_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_P_memd_M_circ __builtin_HEXAGON_L2_loadrd_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=memh(Rx32++#s4:1:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memh_IM_circ __builtin_HEXAGON_L2_loadrh_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memh(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memh_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memh_M_circ __builtin_HEXAGON_L2_loadrh_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=memw(Rx32++#s4:2:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ(void** Rx, Word32 Is4_2, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memw_IM_circ __builtin_HEXAGON_L2_loadri_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memw(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memw_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memw_M_circ __builtin_HEXAGON_L2_loadri_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=memub(Rx32++#s4:0:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memub_IM_circ __builtin_HEXAGON_L2_loadrub_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memub(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memub_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memub_M_circ __builtin_HEXAGON_L2_loadrub_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=memuh(Rx32++#s4:1:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memuh_IM_circ __builtin_HEXAGON_L2_loadruh_pci + +/* ========================================================================== + Assembly Syntax: Rd32=memuh(Rx32++I:circ(Mu2)) + C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ(void** Rx, Word32 Mu, void* BaseAddress) + Instruction Type: LD + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_R_memuh_M_circ __builtin_HEXAGON_L2_loadruh_pcr + +/* ========================================================================== + Assembly Syntax: Rx32+=add(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addacc_RR __builtin_HEXAGON_M2_acci + +/* ========================================================================== + Assembly Syntax: Rx32+=add(Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addacc_RI __builtin_HEXAGON_M2_accii + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyi(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyiacc_RR __builtin_HEXAGON_M2_cmaci_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyr(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyracc_RR __builtin_HEXAGON_M2_cmacr_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyacc_RR_sat __builtin_HEXAGON_M2_cmacs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyacc_RR_s1_sat __builtin_HEXAGON_M2_cmacs_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32*):sat + C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyacc_RR_conj_sat __builtin_HEXAGON_M2_cmacsc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32*):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyacc_RR_conj_s1_sat __builtin_HEXAGON_M2_cmacsc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyi(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyi_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyi_RR __builtin_HEXAGON_M2_cmpyi_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyr(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyr_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpyr_RR __builtin_HEXAGON_M2_cmpyr_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=cmpy(Rs32,Rt32):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpy_RR_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpy_RR_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=cmpy(Rs32,Rt32*):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpy_RR_conj_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpy_RR_conj_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpy(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpy_RR_sat __builtin_HEXAGON_M2_cmpys_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpy_RR_s1_sat __builtin_HEXAGON_M2_cmpys_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpy(Rs32,Rt32*):sat + C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpy_RR_conj_sat __builtin_HEXAGON_M2_cmpysc_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=cmpy(Rs32,Rt32*):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpy_RR_conj_s1_sat __builtin_HEXAGON_M2_cmpysc_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpynac_RR_sat __builtin_HEXAGON_M2_cnacs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpynac_RR_s1_sat __builtin_HEXAGON_M2_cnacs_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32*):sat + C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpynac_RR_conj_sat __builtin_HEXAGON_M2_cnacsc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32*):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cmpynac_RR_conj_s1_sat __builtin_HEXAGON_M2_cnacsc_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RR __builtin_HEXAGON_M2_dpmpyss_acc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RR __builtin_HEXAGON_M2_dpmpyss_nac_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RR_rnd __builtin_HEXAGON_M2_dpmpyss_rnd_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpy_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RR __builtin_HEXAGON_M2_dpmpyss_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RR __builtin_HEXAGON_M2_dpmpyuu_acc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RR __builtin_HEXAGON_M2_dpmpyuu_nac_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32,Rt32) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RR __builtin_HEXAGON_M2_dpmpyuu_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RRh_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyh_rs1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RRh_s1_sat __builtin_HEXAGON_M2_hmmpyh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RRl_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyl_rs1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RRl_s1_sat __builtin_HEXAGON_M2_hmmpyl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyi(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyiacc_RR __builtin_HEXAGON_M2_maci + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyi(Rs32,#u8) + C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyinac_RI __builtin_HEXAGON_M2_macsin + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyi(Rs32,#u8) + C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyiacc_RI __builtin_HEXAGON_M2_macsip + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywohacc_PP_rnd_sat __builtin_HEXAGON_M2_mmachs_rs0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywohacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmachs_rs1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywohacc_PP_sat __builtin_HEXAGON_M2_mmachs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywohacc_PP_s1_sat __builtin_HEXAGON_M2_mmachs_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywehacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacls_rs0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywehacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacls_rs1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywehacc_PP_sat __builtin_HEXAGON_M2_mmacls_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywehacc_PP_s1_sat __builtin_HEXAGON_M2_mmacls_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouhacc_PP_sat __builtin_HEXAGON_M2_mmacuhs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouhacc_PP_s1_sat __builtin_HEXAGON_M2_mmacuhs_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuhacc_PP_sat __builtin_HEXAGON_M2_mmaculs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuhacc_PP_s1_sat __builtin_HEXAGON_M2_mmaculs_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywoh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywoh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywoh_PP_sat __builtin_HEXAGON_M2_mmpyh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywoh_PP_s1_sat __builtin_HEXAGON_M2_mmpyh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweh_PP_sat __builtin_HEXAGON_M2_mmpyl_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweh_PP_s1_sat __builtin_HEXAGON_M2_mmpyl_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouh_PP_sat __builtin_HEXAGON_M2_mmpyuh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpywouh_PP_s1_sat __builtin_HEXAGON_M2_mmpyuh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuh_PP_sat __builtin_HEXAGON_M2_mmpyul_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyweuh_PP_s1_sat __builtin_HEXAGON_M2_mmpyul_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRh __builtin_HEXAGON_M2_mpy_acc_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpy_acc_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRl __builtin_HEXAGON_M2_mpy_acc_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpy_acc_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRh __builtin_HEXAGON_M2_mpy_acc_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpy_acc_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRl __builtin_HEXAGON_M2_mpy_acc_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpy_acc_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh __builtin_HEXAGON_M2_mpy_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpy_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl __builtin_HEXAGON_M2_mpy_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpy_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh __builtin_HEXAGON_M2_mpy_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpy_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl __builtin_HEXAGON_M2_mpy_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpy_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRh __builtin_HEXAGON_M2_mpy_nac_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpy_nac_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRl __builtin_HEXAGON_M2_mpy_nac_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpy_nac_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRh __builtin_HEXAGON_M2_mpy_nac_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpy_nac_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRl __builtin_HEXAGON_M2_mpy_nac_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpy_nac_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_sat __builtin_HEXAGON_M2_mpy_sat_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_sat __builtin_HEXAGON_M2_mpy_sat_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_sat __builtin_HEXAGON_M2_mpy_sat_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_sat __builtin_HEXAGON_M2_mpy_sat_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RhRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RlRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RR __builtin_HEXAGON_M2_mpy_up + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RR_s1 __builtin_HEXAGON_M2_mpy_up_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpy_RR_s1_sat __builtin_HEXAGON_M2_mpy_up_s1_sat + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RhRh __builtin_HEXAGON_M2_mpyd_acc_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpyd_acc_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RhRl __builtin_HEXAGON_M2_mpyd_acc_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpyd_acc_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RlRh __builtin_HEXAGON_M2_mpyd_acc_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpyd_acc_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RlRl __builtin_HEXAGON_M2_mpyd_acc_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpyd_acc_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRh __builtin_HEXAGON_M2_mpyd_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpyd_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRl __builtin_HEXAGON_M2_mpyd_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpyd_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRh __builtin_HEXAGON_M2_mpyd_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpyd_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRl __builtin_HEXAGON_M2_mpyd_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpyd_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RhRh __builtin_HEXAGON_M2_mpyd_nac_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpyd_nac_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RhRl __builtin_HEXAGON_M2_mpyd_nac_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpyd_nac_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RlRh __builtin_HEXAGON_M2_mpyd_nac_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpyd_nac_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RlRl __builtin_HEXAGON_M2_mpyd_nac_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpyd_nac_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd + C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyi(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyi_RR __builtin_HEXAGON_M2_mpyi + +/* ========================================================================== + Assembly Syntax: Rd32=mpyi(Rs32,#m9) + C Intrinsic Prototype: Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mpyi_RI __builtin_HEXAGON_M2_mpysmi + +/* ========================================================================== + Assembly Syntax: Rd32=mpysu(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpysu_RR __builtin_HEXAGON_M2_mpysu_up + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyu_acc_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyu_acc_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyu_acc_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyu_acc_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyu_acc_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyu_acc_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyu_acc_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyu_acc_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RhRh __builtin_HEXAGON_M2_mpyu_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyu_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RhRl __builtin_HEXAGON_M2_mpyu_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyu_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RlRh __builtin_HEXAGON_M2_mpyu_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyu_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RlRl __builtin_HEXAGON_M2_mpyu_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyu_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RhRh __builtin_HEXAGON_M2_mpyu_nac_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyu_nac_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RhRl __builtin_HEXAGON_M2_mpyu_nac_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyu_nac_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RlRh __builtin_HEXAGON_M2_mpyu_nac_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyu_nac_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RlRl __builtin_HEXAGON_M2_mpyu_nac_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyu_nac_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyu(Rs32,Rt32) + C Intrinsic Prototype: UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyu_RR __builtin_HEXAGON_M2_mpyu_up + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyud_acc_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyud_acc_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyud_acc_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyud_acc_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyud_acc_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyud_acc_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyud_acc_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyud_acc_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RhRh __builtin_HEXAGON_M2_mpyud_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyud_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RhRl __builtin_HEXAGON_M2_mpyud_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyud_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RlRh __builtin_HEXAGON_M2_mpyud_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyud_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RlRl __builtin_HEXAGON_M2_mpyud_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl_s1(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyud_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RhRh __builtin_HEXAGON_M2_mpyud_nac_hh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyud_nac_hh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RhRl __builtin_HEXAGON_M2_mpyud_nac_hl_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyud_nac_hl_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.h) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RlRh __builtin_HEXAGON_M2_mpyud_nac_lh_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.h):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyud_nac_lh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.l) + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RlRl __builtin_HEXAGON_M2_mpyud_nac_ll_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.l):<<1 + C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyud_nac_ll_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=mpyui(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_mpyui_RR __builtin_HEXAGON_M2_mpyui + +/* ========================================================================== + Assembly Syntax: Rx32-=add(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addnac_RR __builtin_HEXAGON_M2_nacci + +/* ========================================================================== + Assembly Syntax: Rx32-=add(Rs32,#s8) + C Intrinsic Prototype: Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addnac_RI __builtin_HEXAGON_M2_naccii + +/* ========================================================================== + Assembly Syntax: Rx32+=sub(Rt32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, Word32 Rs) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_subacc_RR __builtin_HEXAGON_M2_subacc + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsdiffh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsdiffh_PP __builtin_HEXAGON_M2_vabsdiffh + +/* ========================================================================== + Assembly Syntax: Rdd32=vabsdiffw(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 Rss) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsdiffw_PP __builtin_HEXAGON_M2_vabsdiffw + +/* ========================================================================== + Assembly Syntax: Rxx32+=vcmpyi(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyiacc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_i + +/* ========================================================================== + Assembly Syntax: Rxx32+=vcmpyr(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyracc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_r + +/* ========================================================================== + Assembly Syntax: Rdd32=vcmpyi(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyi_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_i + +/* ========================================================================== + Assembly Syntax: Rdd32=vcmpyr(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyr_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_r + +/* ========================================================================== + Assembly Syntax: Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyi_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_i + +/* ========================================================================== + Assembly Syntax: Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcmpyr_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_r + +/* ========================================================================== + Assembly Syntax: Rxx32+=vdmpy(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpyacc_PP_sat __builtin_HEXAGON_M2_vdmacs_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpyacc_PP_s1_sat __builtin_HEXAGON_M2_vdmacs_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=vdmpy(Rss32,Rtt32):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vdmpy_PP_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vdmpy_PP_s1_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vdmpy(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpy_PP_sat __builtin_HEXAGON_M2_vdmpys_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vdmpy(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpy_PP_s1_sat __builtin_HEXAGON_M2_vdmpys_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhacc_RR __builtin_HEXAGON_M2_vmac2 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyehacc_PP __builtin_HEXAGON_M2_vmac2es + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyehacc_PP_sat __builtin_HEXAGON_M2_vmac2es_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyehacc_PP_s1_sat __builtin_HEXAGON_M2_vmac2es_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhacc_RR_sat __builtin_HEXAGON_M2_vmac2s_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2s_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyhsu(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhsuacc_RR_sat __builtin_HEXAGON_M2_vmac2su_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhsuacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2su_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyeh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyeh_PP_sat __builtin_HEXAGON_M2_vmpy2es_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyeh_PP_s1_sat __builtin_HEXAGON_M2_vmpy2es_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyh(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyh_RR_sat __builtin_HEXAGON_M2_vmpy2s_s0 + +/* ========================================================================== + Assembly Syntax: Rd32=vmpyh(Rs32,Rt32):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vmpyh_RR_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s0pack + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyh(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyh_RR_s1_sat __builtin_HEXAGON_M2_vmpy2s_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_s1_rnd_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vmpyh_RR_s1_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s1pack + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyhsu(Rs32,Rt32):sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhsu_RR_sat __builtin_HEXAGON_M2_vmpy2su_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_s1_sat(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpyhsu_RR_s1_sat __builtin_HEXAGON_M2_vmpy2su_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=vraddh(Rss32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vraddh_PP __builtin_HEXAGON_M2_vraddh + +/* ========================================================================== + Assembly Syntax: Rd32=vradduh(Rss32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vradduh_PP __builtin_HEXAGON_M2_vradduh + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpyi(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyiacc_PP __builtin_HEXAGON_M2_vrcmaci_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpyi(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyiacc_PP_conj __builtin_HEXAGON_M2_vrcmaci_s0c + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpyr(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyracc_PP __builtin_HEXAGON_M2_vrcmacr_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpyr(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyracc_PP_conj __builtin_HEXAGON_M2_vrcmacr_s0c + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpyi(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyi_PP __builtin_HEXAGON_M2_vrcmpyi_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpyi(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP_conj(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyi_PP_conj __builtin_HEXAGON_M2_vrcmpyi_s0c + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpyr(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyr_PP __builtin_HEXAGON_M2_vrcmpyr_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpyr(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP_conj(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcmpyr_PP_conj __builtin_HEXAGON_M2_vrcmpyr_s0c + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vrcmpysacc_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_acc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcmpys(Rss32,Rt32):<<1:sat + C Intrinsic Prototype: Word64 Q6_P_vrcmpys_PR_s1_sat(Word64 Rss, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vrcmpys_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_s1 + +/* ========================================================================== + Assembly Syntax: Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vrcmpys_PR_s1_rnd_sat __builtin_HEXAGON_M2_vrcmpys_s1rp + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpyh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpyhacc_PP __builtin_HEXAGON_M2_vrmac_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpyh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpyh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpyh_PP __builtin_HEXAGON_M2_vrmpy_s0 + +/* ========================================================================== + Assembly Syntax: Rx32^=xor(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_xorxacc_RR __builtin_HEXAGON_M2_xor_xacc + +/* ========================================================================== + Assembly Syntax: Rx32&=and(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andand_RR __builtin_HEXAGON_M4_and_and + +/* ========================================================================== + Assembly Syntax: Rx32&=and(Rs32,~Rt32) + C Intrinsic Prototype: Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andand_RnR __builtin_HEXAGON_M4_and_andn + +/* ========================================================================== + Assembly Syntax: Rx32&=or(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_orand_RR __builtin_HEXAGON_M4_and_or + +/* ========================================================================== + Assembly Syntax: Rx32&=xor(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_xorand_RR __builtin_HEXAGON_M4_and_xor + +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpyiwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_wh + +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpyiwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_whc + +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpyrwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_wh + +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cmpyrwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_whc + +/* ========================================================================== + Assembly Syntax: Rx32+=mpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyacc_RR_s1_sat __builtin_HEXAGON_M4_mac_up_s1_sat + +/* ========================================================================== + Assembly Syntax: Rd32=add(#u6,mpyi(Rs32,#U6)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_IRI __builtin_HEXAGON_M4_mpyri_addi + +/* ========================================================================== + Assembly Syntax: Rd32=add(Ru32,mpyi(Rs32,#u6)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_RRI __builtin_HEXAGON_M4_mpyri_addr + +/* ========================================================================== + Assembly Syntax: Rd32=add(Ru32,mpyi(#u6:2,Rs32)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_RIR __builtin_HEXAGON_M4_mpyri_addr_u2 + +/* ========================================================================== + Assembly Syntax: Rd32=add(#u6,mpyi(Rs32,Rt32)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_IRR __builtin_HEXAGON_M4_mpyrr_addi + +/* ========================================================================== + Assembly Syntax: Ry32=add(Ru32,mpyi(Ry32,Rs32)) + C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_mpyi_RRR __builtin_HEXAGON_M4_mpyrr_addr + +/* ========================================================================== + Assembly Syntax: Rx32-=mpy(Rs32,Rt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpynac_RR_s1_sat __builtin_HEXAGON_M4_nac_up_s1_sat + +/* ========================================================================== + Assembly Syntax: Rx32|=and(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andor_RR __builtin_HEXAGON_M4_or_and + +/* ========================================================================== + Assembly Syntax: Rx32|=and(Rs32,~Rt32) + C Intrinsic Prototype: Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andor_RnR __builtin_HEXAGON_M4_or_andn + +/* ========================================================================== + Assembly Syntax: Rx32|=or(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_oror_RR __builtin_HEXAGON_M4_or_or + +/* ========================================================================== + Assembly Syntax: Rx32|=xor(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_xoror_RR __builtin_HEXAGON_M4_or_xor + +/* ========================================================================== + Assembly Syntax: Rdd32=pmpyw(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_pmpyw_RR __builtin_HEXAGON_M4_pmpyw + +/* ========================================================================== + Assembly Syntax: Rxx32^=pmpyw(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_pmpywxacc_RR __builtin_HEXAGON_M4_pmpyw_acc + +/* ========================================================================== + Assembly Syntax: Rdd32=vpmpyh(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vpmpyh_RR __builtin_HEXAGON_M4_vpmpyh + +/* ========================================================================== + Assembly Syntax: Rxx32^=vpmpyh(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vpmpyhxacc_RR __builtin_HEXAGON_M4_vpmpyh_acc + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpyweh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywehacc_PP __builtin_HEXAGON_M4_vrmpyeh_acc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpyweh(Rss32,Rtt32):<<1 + C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywehacc_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_acc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpyweh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpyweh_PP __builtin_HEXAGON_M4_vrmpyeh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpyweh(Rss32,Rtt32):<<1 + C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpyweh_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_s1 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpywoh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywohacc_PP __builtin_HEXAGON_M4_vrmpyoh_acc_s0 + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpywoh(Rss32,Rtt32):<<1 + C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywohacc_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_acc_s1 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpywoh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywoh_PP __builtin_HEXAGON_M4_vrmpyoh_s0 + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpywoh(Rss32,Rtt32):<<1 + C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpywoh_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_s1 + +/* ========================================================================== + Assembly Syntax: Rx32^=and(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andxacc_RR __builtin_HEXAGON_M4_xor_and + +/* ========================================================================== + Assembly Syntax: Rx32^=and(Rs32,~Rt32) + C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andxacc_RnR __builtin_HEXAGON_M4_xor_andn + +/* ========================================================================== + Assembly Syntax: Rx32^=or(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_orxacc_RR __builtin_HEXAGON_M4_xor_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=xor(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_xorxacc_PP __builtin_HEXAGON_M4_xor_xacc + +/* ========================================================================== + Assembly Syntax: Rxx32+=vdmpybsu(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpybsuacc_PP_sat __builtin_HEXAGON_M5_vdmacbsu + +/* ========================================================================== + Assembly Syntax: Rdd32=vdmpybsu(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vdmpybsu_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vdmpybsu_PP_sat __builtin_HEXAGON_M5_vdmpybsu + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpybsu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpybsuacc_RR __builtin_HEXAGON_M5_vmacbsu + +/* ========================================================================== + Assembly Syntax: Rxx32+=vmpybu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpybuacc_RR __builtin_HEXAGON_M5_vmacbuu + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpybsu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpybsu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpybsu_RR __builtin_HEXAGON_M5_vmpybsu + +/* ========================================================================== + Assembly Syntax: Rdd32=vmpybu(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vmpybu_RR(Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vmpybu_RR __builtin_HEXAGON_M5_vmpybuu + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpybsu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpybsuacc_PP __builtin_HEXAGON_M5_vrmacbsu + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrmpybu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpybuacc_PP __builtin_HEXAGON_M5_vrmacbuu + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpybsu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpybsu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpybsu_PP __builtin_HEXAGON_M5_vrmpybsu + +/* ========================================================================== + Assembly Syntax: Rdd32=vrmpybu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vrmpybu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrmpybu_PP __builtin_HEXAGON_M5_vrmpybuu + +/* ========================================================================== + Assembly Syntax: Rd32=addasl(Rt32,Rs32,#u3) + C Intrinsic Prototype: Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32 Iu3) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_addasl_RRI __builtin_HEXAGON_S2_addasl_rrri + +/* ========================================================================== + Assembly Syntax: Rdd32=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asl_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asl_PI __builtin_HEXAGON_S2_asl_i_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslacc_PI __builtin_HEXAGON_S2_asl_i_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asland_PI __builtin_HEXAGON_S2_asl_i_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslnac_PI __builtin_HEXAGON_S2_asl_i_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslor_PI __builtin_HEXAGON_S2_asl_i_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=asl(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslxacc_PI __builtin_HEXAGON_S2_asl_i_p_xacc + +/* ========================================================================== + Assembly Syntax: Rd32=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asl_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asl_RI __builtin_HEXAGON_S2_asl_i_r + +/* ========================================================================== + Assembly Syntax: Rx32+=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslacc_RI __builtin_HEXAGON_S2_asl_i_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asland_RI __builtin_HEXAGON_S2_asl_i_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslnac_RI __builtin_HEXAGON_S2_asl_i_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_aslor_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslor_RI __builtin_HEXAGON_S2_asl_i_r_or + +/* ========================================================================== + Assembly Syntax: Rd32=asl(Rs32,#u5):sat + C Intrinsic Prototype: Word32 Q6_R_asl_RI_sat(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asl_RI_sat __builtin_HEXAGON_S2_asl_i_r_sat + +/* ========================================================================== + Assembly Syntax: Rx32^=asl(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslxacc_RI __builtin_HEXAGON_S2_asl_i_r_xacc + +/* ========================================================================== + Assembly Syntax: Rdd32=vaslh(Rss32,#u4) + C Intrinsic Prototype: Word64 Q6_P_vaslh_PI(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaslh_PI __builtin_HEXAGON_S2_asl_i_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vaslw(Rss32,#u5) + C Intrinsic Prototype: Word64 Q6_P_vaslw_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaslw_PI __builtin_HEXAGON_S2_asl_i_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asl_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asl_PR __builtin_HEXAGON_S2_asl_r_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslacc_PR __builtin_HEXAGON_S2_asl_r_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asland_PR __builtin_HEXAGON_S2_asl_r_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslnac_PR __builtin_HEXAGON_S2_asl_r_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslor_PR __builtin_HEXAGON_S2_asl_r_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=asl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_aslxacc_PR __builtin_HEXAGON_S2_asl_r_p_xor + +/* ========================================================================== + Assembly Syntax: Rd32=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asl_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asl_RR __builtin_HEXAGON_S2_asl_r_r + +/* ========================================================================== + Assembly Syntax: Rx32+=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_aslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslacc_RR __builtin_HEXAGON_S2_asl_r_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asland_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asland_RR __builtin_HEXAGON_S2_asl_r_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_aslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslnac_RR __builtin_HEXAGON_S2_asl_r_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=asl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_aslor_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_aslor_RR __builtin_HEXAGON_S2_asl_r_r_or + +/* ========================================================================== + Assembly Syntax: Rd32=asl(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_asl_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asl_RR_sat __builtin_HEXAGON_S2_asl_r_r_sat + +/* ========================================================================== + Assembly Syntax: Rdd32=vaslh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vaslh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaslh_PR __builtin_HEXAGON_S2_asl_r_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vaslw(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vaslw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vaslw_PR __builtin_HEXAGON_S2_asl_r_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asr_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asr_PI __builtin_HEXAGON_S2_asr_i_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asracc_PI __builtin_HEXAGON_S2_asr_i_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrand_PI __builtin_HEXAGON_S2_asr_i_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrnac_PI __builtin_HEXAGON_S2_asr_i_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=asr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asror_PI __builtin_HEXAGON_S2_asr_i_p_or + +/* ========================================================================== + Assembly Syntax: Rdd32=asr(Rss32,#u6):rnd + C Intrinsic Prototype: Word64 Q6_P_asr_PI_rnd(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asr_PI_rnd __builtin_HEXAGON_S2_asr_i_p_rnd + +/* ========================================================================== + Assembly Syntax: Rdd32=asrrnd(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_asrrnd_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_asrrnd_PI __builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rd32=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asr_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asr_RI __builtin_HEXAGON_S2_asr_i_r + +/* ========================================================================== + Assembly Syntax: Rx32+=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asracc_RI __builtin_HEXAGON_S2_asr_i_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asrand_RI __builtin_HEXAGON_S2_asr_i_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asrnac_RI __builtin_HEXAGON_S2_asr_i_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=asr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asror_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asror_RI __builtin_HEXAGON_S2_asr_i_r_or + +/* ========================================================================== + Assembly Syntax: Rd32=asr(Rs32,#u5):rnd + C Intrinsic Prototype: Word32 Q6_R_asr_RI_rnd(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asr_RI_rnd __builtin_HEXAGON_S2_asr_i_r_rnd + +/* ========================================================================== + Assembly Syntax: Rd32=asrrnd(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_asrrnd_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_asrrnd_RI __builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rd32=vasrw(Rss32,#u5) + C Intrinsic Prototype: Word32 Q6_R_vasrw_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vasrw_PI __builtin_HEXAGON_S2_asr_i_svw_trun + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrh(Rss32,#u4) + C Intrinsic Prototype: Word64 Q6_P_vasrh_PI(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vasrh_PI __builtin_HEXAGON_S2_asr_i_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrw(Rss32,#u5) + C Intrinsic Prototype: Word64 Q6_P_vasrw_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vasrw_PI __builtin_HEXAGON_S2_asr_i_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asr_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asr_PR __builtin_HEXAGON_S2_asr_r_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asracc_PR __builtin_HEXAGON_S2_asr_r_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrand_PR __builtin_HEXAGON_S2_asr_r_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrnac_PR __builtin_HEXAGON_S2_asr_r_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asror_PR __builtin_HEXAGON_S2_asr_r_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=asr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_asrxacc_PR __builtin_HEXAGON_S2_asr_r_p_xor + +/* ========================================================================== + Assembly Syntax: Rd32=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asr_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asr_RR __builtin_HEXAGON_S2_asr_r_r + +/* ========================================================================== + Assembly Syntax: Rx32+=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asracc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asracc_RR __builtin_HEXAGON_S2_asr_r_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asrand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asrand_RR __builtin_HEXAGON_S2_asr_r_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asrnac_RR __builtin_HEXAGON_S2_asr_r_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=asr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_asror_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asror_RR __builtin_HEXAGON_S2_asr_r_r_or + +/* ========================================================================== + Assembly Syntax: Rd32=asr(Rs32,Rt32):sat + C Intrinsic Prototype: Word32 Q6_R_asr_RR_sat(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_asr_RR_sat __builtin_HEXAGON_S2_asr_r_r_sat + +/* ========================================================================== + Assembly Syntax: Rd32=vasrw(Rss32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_vasrw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vasrw_PR __builtin_HEXAGON_S2_asr_r_svw_trun + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vasrh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vasrh_PR __builtin_HEXAGON_S2_asr_r_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrw(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vasrw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vasrw_PR __builtin_HEXAGON_S2_asr_r_vw + +/* ========================================================================== + Assembly Syntax: Rd32=brev(Rs32) + C Intrinsic Prototype: Word32 Q6_R_brev_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_brev_R __builtin_HEXAGON_S2_brev + +/* ========================================================================== + Assembly Syntax: Rdd32=brev(Rss32) + C Intrinsic Prototype: Word64 Q6_P_brev_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_brev_P __builtin_HEXAGON_S2_brevp + +/* ========================================================================== + Assembly Syntax: Rd32=cl0(Rs32) + C Intrinsic Prototype: Word32 Q6_R_cl0_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cl0_R __builtin_HEXAGON_S2_cl0 + +/* ========================================================================== + Assembly Syntax: Rd32=cl0(Rss32) + C Intrinsic Prototype: Word32 Q6_R_cl0_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cl0_P __builtin_HEXAGON_S2_cl0p + +/* ========================================================================== + Assembly Syntax: Rd32=cl1(Rs32) + C Intrinsic Prototype: Word32 Q6_R_cl1_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cl1_R __builtin_HEXAGON_S2_cl1 + +/* ========================================================================== + Assembly Syntax: Rd32=cl1(Rss32) + C Intrinsic Prototype: Word32 Q6_R_cl1_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_cl1_P __builtin_HEXAGON_S2_cl1p + +/* ========================================================================== + Assembly Syntax: Rd32=clb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_clb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clb_R __builtin_HEXAGON_S2_clb + +/* ========================================================================== + Assembly Syntax: Rd32=normamt(Rs32) + C Intrinsic Prototype: Word32 Q6_R_normamt_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_normamt_R __builtin_HEXAGON_S2_clbnorm + +/* ========================================================================== + Assembly Syntax: Rd32=clb(Rss32) + C Intrinsic Prototype: Word32 Q6_R_clb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clb_P __builtin_HEXAGON_S2_clbp + +/* ========================================================================== + Assembly Syntax: Rd32=clrbit(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clrbit_RI __builtin_HEXAGON_S2_clrbit_i + +/* ========================================================================== + Assembly Syntax: Rd32=clrbit(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clrbit_RR __builtin_HEXAGON_S2_clrbit_r + +/* ========================================================================== + Assembly Syntax: Rd32=ct0(Rs32) + C Intrinsic Prototype: Word32 Q6_R_ct0_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_ct0_R __builtin_HEXAGON_S2_ct0 + +/* ========================================================================== + Assembly Syntax: Rd32=ct0(Rss32) + C Intrinsic Prototype: Word32 Q6_R_ct0_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_ct0_P __builtin_HEXAGON_S2_ct0p + +/* ========================================================================== + Assembly Syntax: Rd32=ct1(Rs32) + C Intrinsic Prototype: Word32 Q6_R_ct1_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_ct1_R __builtin_HEXAGON_S2_ct1 + +/* ========================================================================== + Assembly Syntax: Rd32=ct1(Rss32) + C Intrinsic Prototype: Word32 Q6_R_ct1_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_ct1_P __builtin_HEXAGON_S2_ct1p + +/* ========================================================================== + Assembly Syntax: Rdd32=deinterleave(Rss32) + C Intrinsic Prototype: Word64 Q6_P_deinterleave_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_deinterleave_P __builtin_HEXAGON_S2_deinterleave + +/* ========================================================================== + Assembly Syntax: Rd32=extractu(Rs32,#u5,#U5) + C Intrinsic Prototype: Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_extractu_RII __builtin_HEXAGON_S2_extractu + +/* ========================================================================== + Assembly Syntax: Rd32=extractu(Rs32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_extractu_RP(Word32 Rs, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_extractu_RP __builtin_HEXAGON_S2_extractu_rp + +/* ========================================================================== + Assembly Syntax: Rdd32=extractu(Rss32,#u6,#U6) + C Intrinsic Prototype: Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_extractu_PII __builtin_HEXAGON_S2_extractup + +/* ========================================================================== + Assembly Syntax: Rdd32=extractu(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_extractu_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_extractu_PP __builtin_HEXAGON_S2_extractup_rp + +/* ========================================================================== + Assembly Syntax: Rx32=insert(Rs32,#u5,#U5) + C Intrinsic Prototype: Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_insert_RII __builtin_HEXAGON_S2_insert + +/* ========================================================================== + Assembly Syntax: Rx32=insert(Rs32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_insert_RP __builtin_HEXAGON_S2_insert_rp + +/* ========================================================================== + Assembly Syntax: Rxx32=insert(Rss32,#u6,#U6) + C Intrinsic Prototype: Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_insert_PII __builtin_HEXAGON_S2_insertp + +/* ========================================================================== + Assembly Syntax: Rxx32=insert(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_insert_PP __builtin_HEXAGON_S2_insertp_rp + +/* ========================================================================== + Assembly Syntax: Rdd32=interleave(Rss32) + C Intrinsic Prototype: Word64 Q6_P_interleave_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_interleave_P __builtin_HEXAGON_S2_interleave + +/* ========================================================================== + Assembly Syntax: Rdd32=lfs(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lfs_PP __builtin_HEXAGON_S2_lfsp + +/* ========================================================================== + Assembly Syntax: Rdd32=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsl_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsl_PR __builtin_HEXAGON_S2_lsl_r_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lslacc_PR __builtin_HEXAGON_S2_lsl_r_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsland_PR __builtin_HEXAGON_S2_lsl_r_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lslnac_PR __builtin_HEXAGON_S2_lsl_r_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lslor_PR __builtin_HEXAGON_S2_lsl_r_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=lsl(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lslxacc_PR __builtin_HEXAGON_S2_lsl_r_p_xor + +/* ========================================================================== + Assembly Syntax: Rd32=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsl_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsl_RR __builtin_HEXAGON_S2_lsl_r_r + +/* ========================================================================== + Assembly Syntax: Rx32+=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lslacc_RR __builtin_HEXAGON_S2_lsl_r_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsland_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsland_RR __builtin_HEXAGON_S2_lsl_r_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lslnac_RR __builtin_HEXAGON_S2_lsl_r_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=lsl(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lslor_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lslor_RR __builtin_HEXAGON_S2_lsl_r_r_or + +/* ========================================================================== + Assembly Syntax: Rdd32=vlslh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vlslh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlslh_PR __builtin_HEXAGON_S2_lsl_r_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vlslw(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vlslw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlslw_PR __builtin_HEXAGON_S2_lsl_r_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsr_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsr_PI __builtin_HEXAGON_S2_lsr_i_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsracc_PI __builtin_HEXAGON_S2_lsr_i_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrand_PI __builtin_HEXAGON_S2_lsr_i_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrnac_PI __builtin_HEXAGON_S2_lsr_i_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsror_PI __builtin_HEXAGON_S2_lsr_i_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=lsr(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrxacc_PI __builtin_HEXAGON_S2_lsr_i_p_xacc + +/* ========================================================================== + Assembly Syntax: Rd32=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsr_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsr_RI __builtin_HEXAGON_S2_lsr_i_r + +/* ========================================================================== + Assembly Syntax: Rx32+=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsracc_RI __builtin_HEXAGON_S2_lsr_i_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrand_RI __builtin_HEXAGON_S2_lsr_i_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrnac_RI __builtin_HEXAGON_S2_lsr_i_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsror_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsror_RI __builtin_HEXAGON_S2_lsr_i_r_or + +/* ========================================================================== + Assembly Syntax: Rx32^=lsr(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrxacc_RI __builtin_HEXAGON_S2_lsr_i_r_xacc + +/* ========================================================================== + Assembly Syntax: Rdd32=vlsrh(Rss32,#u4) + C Intrinsic Prototype: Word64 Q6_P_vlsrh_PI(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlsrh_PI __builtin_HEXAGON_S2_lsr_i_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vlsrw(Rss32,#u5) + C Intrinsic Prototype: Word64 Q6_P_vlsrw_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlsrw_PI __builtin_HEXAGON_S2_lsr_i_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsr_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsr_PR __builtin_HEXAGON_S2_lsr_r_p + +/* ========================================================================== + Assembly Syntax: Rxx32+=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsracc_PR __builtin_HEXAGON_S2_lsr_r_p_acc + +/* ========================================================================== + Assembly Syntax: Rxx32&=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrand_PR __builtin_HEXAGON_S2_lsr_r_p_and + +/* ========================================================================== + Assembly Syntax: Rxx32-=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrnac_PR __builtin_HEXAGON_S2_lsr_r_p_nac + +/* ========================================================================== + Assembly Syntax: Rxx32|=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsror_PR __builtin_HEXAGON_S2_lsr_r_p_or + +/* ========================================================================== + Assembly Syntax: Rxx32^=lsr(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_lsrxacc_PR __builtin_HEXAGON_S2_lsr_r_p_xor + +/* ========================================================================== + Assembly Syntax: Rd32=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsr_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsr_RR __builtin_HEXAGON_S2_lsr_r_r + +/* ========================================================================== + Assembly Syntax: Rx32+=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsracc_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsracc_RR __builtin_HEXAGON_S2_lsr_r_r_acc + +/* ========================================================================== + Assembly Syntax: Rx32&=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsrand_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrand_RR __builtin_HEXAGON_S2_lsr_r_r_and + +/* ========================================================================== + Assembly Syntax: Rx32-=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsrnac_RR __builtin_HEXAGON_S2_lsr_r_r_nac + +/* ========================================================================== + Assembly Syntax: Rx32|=lsr(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsror_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsror_RR __builtin_HEXAGON_S2_lsr_r_r_or + +/* ========================================================================== + Assembly Syntax: Rdd32=vlsrh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vlsrh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlsrh_PR __builtin_HEXAGON_S2_lsr_r_vh + +/* ========================================================================== + Assembly Syntax: Rdd32=vlsrw(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vlsrw_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vlsrw_PR __builtin_HEXAGON_S2_lsr_r_vw + +/* ========================================================================== + Assembly Syntax: Rdd32=packhl(Rs32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU32_3op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_packhl_RR __builtin_HEXAGON_S2_packhl + +/* ========================================================================== + Assembly Syntax: Rd32=parity(Rss32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_parity_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_parity_PP __builtin_HEXAGON_S2_parityp + +/* ========================================================================== + Assembly Syntax: Rd32=setbit(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_setbit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_setbit_RI __builtin_HEXAGON_S2_setbit_i + +/* ========================================================================== + Assembly Syntax: Rd32=setbit(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_setbit_RR __builtin_HEXAGON_S2_setbit_r + +/* ========================================================================== + Assembly Syntax: Rdd32=shuffeb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_shuffeb_PP __builtin_HEXAGON_S2_shuffeb + +/* ========================================================================== + Assembly Syntax: Rdd32=shuffeh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_shuffeh_PP __builtin_HEXAGON_S2_shuffeh + +/* ========================================================================== + Assembly Syntax: Rdd32=shuffob(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 Rss) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_shuffob_PP __builtin_HEXAGON_S2_shuffob + +/* ========================================================================== + Assembly Syntax: Rdd32=shuffoh(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 Rss) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_shuffoh_PP __builtin_HEXAGON_S2_shuffoh + +/* ========================================================================== + Assembly Syntax: memb(Rx32++#s4:0:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memb_IMR_circ(void** Rx, Word32 Is4_0, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memb_IMR_circ __builtin_HEXAGON_S2_storerb_pci + +/* ========================================================================== + Assembly Syntax: memb(Rx32++I:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memb_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memb_MR_circ __builtin_HEXAGON_S2_storerb_pcr + +/* ========================================================================== + Assembly Syntax: memd(Rx32++#s4:3:circ(Mu2))=Rtt32 + C Intrinsic Prototype: void Q6_memd_IMP_circ(void** Rx, Word32 Is4_3, Word32 Mu, Word64 Rtt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memd_IMP_circ __builtin_HEXAGON_S2_storerd_pci + +/* ========================================================================== + Assembly Syntax: memd(Rx32++I:circ(Mu2))=Rtt32 + C Intrinsic Prototype: void Q6_memd_MP_circ(void** Rx, Word32 Mu, Word64 Rtt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memd_MP_circ __builtin_HEXAGON_S2_storerd_pcr + +/* ========================================================================== + Assembly Syntax: memh(Rx32++#s4:1:circ(Mu2))=Rt32.h + C Intrinsic Prototype: void Q6_memh_IMRh_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memh_IMRh_circ __builtin_HEXAGON_S2_storerf_pci + +/* ========================================================================== + Assembly Syntax: memh(Rx32++I:circ(Mu2))=Rt32.h + C Intrinsic Prototype: void Q6_memh_MRh_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memh_MRh_circ __builtin_HEXAGON_S2_storerf_pcr + +/* ========================================================================== + Assembly Syntax: memh(Rx32++#s4:1:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memh_IMR_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memh_IMR_circ __builtin_HEXAGON_S2_storerh_pci + +/* ========================================================================== + Assembly Syntax: memh(Rx32++I:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memh_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memh_MR_circ __builtin_HEXAGON_S2_storerh_pcr + +/* ========================================================================== + Assembly Syntax: memw(Rx32++#s4:2:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memw_IMR_circ(void** Rx, Word32 Is4_2, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memw_IMR_circ __builtin_HEXAGON_S2_storeri_pci + +/* ========================================================================== + Assembly Syntax: memw(Rx32++I:circ(Mu2))=Rt32 + C Intrinsic Prototype: void Q6_memw_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) + Instruction Type: ST + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_memw_MR_circ __builtin_HEXAGON_S2_storeri_pcr + +/* ========================================================================== + Assembly Syntax: Rd32=vsathb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_vsathb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsathb_R __builtin_HEXAGON_S2_svsathb + +/* ========================================================================== + Assembly Syntax: Rd32=vsathub(Rs32) + C Intrinsic Prototype: Word32 Q6_R_vsathub_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsathub_R __builtin_HEXAGON_S2_svsathub + +/* ========================================================================== + Assembly Syntax: Rx32=tableidxb(Rs32,#u4,#U5) + C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_tableidxb_RII __builtin_HEXAGON_S2_tableidxb_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rx32=tableidxd(Rs32,#u4,#U5) + C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_tableidxd_RII __builtin_HEXAGON_S2_tableidxd_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rx32=tableidxh(Rs32,#u4,#U5) + C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_tableidxh_RII __builtin_HEXAGON_S2_tableidxh_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rx32=tableidxw(Rs32,#u4,#U5) + C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_tableidxw_RII __builtin_HEXAGON_S2_tableidxw_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rd32=togglebit(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_togglebit_RI __builtin_HEXAGON_S2_togglebit_i + +/* ========================================================================== + Assembly Syntax: Rd32=togglebit(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_togglebit_RR __builtin_HEXAGON_S2_togglebit_r + +/* ========================================================================== + Assembly Syntax: Pd4=tstbit(Rs32,#u5) + C Intrinsic Prototype: Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_tstbit_RI __builtin_HEXAGON_S2_tstbit_i + +/* ========================================================================== + Assembly Syntax: Pd4=tstbit(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_tstbit_RR __builtin_HEXAGON_S2_tstbit_r + +/* ========================================================================== + Assembly Syntax: Rdd32=valignb(Rtt32,Rss32,#u3) + C Intrinsic Prototype: Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_valignb_PPI __builtin_HEXAGON_S2_valignib + +/* ========================================================================== + Assembly Syntax: Rdd32=valignb(Rtt32,Rss32,Pu4) + C Intrinsic Prototype: Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_valignb_PPp __builtin_HEXAGON_S2_valignrb + +/* ========================================================================== + Assembly Syntax: Rdd32=vcnegh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcnegh_PR __builtin_HEXAGON_S2_vcnegh + +/* ========================================================================== + Assembly Syntax: Rdd32=vcrotate(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vcrotate_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vcrotate_PR __builtin_HEXAGON_S2_vcrotate + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcnegh(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcneghacc_PR __builtin_HEXAGON_S2_vrcnegh + +/* ========================================================================== + Assembly Syntax: Rd32=vrndwh(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vrndwh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vrndwh_P __builtin_HEXAGON_S2_vrndpackwh + +/* ========================================================================== + Assembly Syntax: Rd32=vrndwh(Rss32):sat + C Intrinsic Prototype: Word32 Q6_R_vrndwh_P_sat(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vrndwh_P_sat __builtin_HEXAGON_S2_vrndpackwhs + +/* ========================================================================== + Assembly Syntax: Rd32=vsathb(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vsathb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsathb_P __builtin_HEXAGON_S2_vsathb + +/* ========================================================================== + Assembly Syntax: Rdd32=vsathb(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsathb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsathb_P __builtin_HEXAGON_S2_vsathb_nopack + +/* ========================================================================== + Assembly Syntax: Rd32=vsathub(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vsathub_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsathub_P __builtin_HEXAGON_S2_vsathub + +/* ========================================================================== + Assembly Syntax: Rdd32=vsathub(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsathub_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsathub_P __builtin_HEXAGON_S2_vsathub_nopack + +/* ========================================================================== + Assembly Syntax: Rd32=vsatwh(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vsatwh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsatwh_P __builtin_HEXAGON_S2_vsatwh + +/* ========================================================================== + Assembly Syntax: Rdd32=vsatwh(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsatwh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsatwh_P __builtin_HEXAGON_S2_vsatwh_nopack + +/* ========================================================================== + Assembly Syntax: Rd32=vsatwuh(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vsatwuh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh + +/* ========================================================================== + Assembly Syntax: Rdd32=vsatwuh(Rss32) + C Intrinsic Prototype: Word64 Q6_P_vsatwuh_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh_nopack + +/* ========================================================================== + Assembly Syntax: Rd32=vsplatb(Rs32) + C Intrinsic Prototype: Word32 Q6_R_vsplatb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vsplatb_R __builtin_HEXAGON_S2_vsplatrb + +/* ========================================================================== + Assembly Syntax: Rdd32=vsplath(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vsplath_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsplath_R __builtin_HEXAGON_S2_vsplatrh + +/* ========================================================================== + Assembly Syntax: Rdd32=vspliceb(Rss32,Rtt32,#u3) + C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vspliceb_PPI __builtin_HEXAGON_S2_vspliceib + +/* ========================================================================== + Assembly Syntax: Rdd32=vspliceb(Rss32,Rtt32,Pu4) + C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vspliceb_PPp __builtin_HEXAGON_S2_vsplicerb + +/* ========================================================================== + Assembly Syntax: Rdd32=vsxtbh(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vsxtbh_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsxtbh_R __builtin_HEXAGON_S2_vsxtbh + +/* ========================================================================== + Assembly Syntax: Rdd32=vsxthw(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vsxthw_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsxthw_R __builtin_HEXAGON_S2_vsxthw + +/* ========================================================================== + Assembly Syntax: Rd32=vtrunehb(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vtrunehb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vtrunehb_P __builtin_HEXAGON_S2_vtrunehb + +/* ========================================================================== + Assembly Syntax: Rdd32=vtrunewh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vtrunewh_PP __builtin_HEXAGON_S2_vtrunewh + +/* ========================================================================== + Assembly Syntax: Rd32=vtrunohb(Rss32) + C Intrinsic Prototype: Word32 Q6_R_vtrunohb_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vtrunohb_P __builtin_HEXAGON_S2_vtrunohb + +/* ========================================================================== + Assembly Syntax: Rdd32=vtrunowh(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vtrunowh_PP __builtin_HEXAGON_S2_vtrunowh + +/* ========================================================================== + Assembly Syntax: Rdd32=vzxtbh(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vzxtbh_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vzxtbh_R __builtin_HEXAGON_S2_vzxtbh + +/* ========================================================================== + Assembly Syntax: Rdd32=vzxthw(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vzxthw_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vzxthw_R __builtin_HEXAGON_S2_vzxthw + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,add(Ru32,#s6)) + C Intrinsic Prototype: Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_add_RRI __builtin_HEXAGON_S4_addaddi + +/* ========================================================================== + Assembly Syntax: Rx32=add(#u8,asl(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_asl_IRI __builtin_HEXAGON_S4_addi_asl_ri + +/* ========================================================================== + Assembly Syntax: Rx32=add(#u8,lsr(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_lsr_IRI __builtin_HEXAGON_S4_addi_lsr_ri + +/* ========================================================================== + Assembly Syntax: Rx32=and(#u8,asl(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_and_asl_IRI __builtin_HEXAGON_S4_andi_asl_ri + +/* ========================================================================== + Assembly Syntax: Rx32=and(#u8,lsr(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_and_lsr_IRI __builtin_HEXAGON_S4_andi_lsr_ri + +/* ========================================================================== + Assembly Syntax: Rd32=add(clb(Rs32),#s6) + C Intrinsic Prototype: Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 Is6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_clb_RI __builtin_HEXAGON_S4_clbaddi + +/* ========================================================================== + Assembly Syntax: Rd32=add(clb(Rss32),#s6) + C Intrinsic Prototype: Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 Is6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_clb_PI __builtin_HEXAGON_S4_clbpaddi + +/* ========================================================================== + Assembly Syntax: Rd32=normamt(Rss32) + C Intrinsic Prototype: Word32 Q6_R_normamt_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_normamt_P __builtin_HEXAGON_S4_clbpnorm + +/* ========================================================================== + Assembly Syntax: Rd32=extract(Rs32,#u5,#U5) + C Intrinsic Prototype: Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_extract_RII __builtin_HEXAGON_S4_extract + +/* ========================================================================== + Assembly Syntax: Rd32=extract(Rs32,Rtt32) + C Intrinsic Prototype: Word32 Q6_R_extract_RP(Word32 Rs, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_extract_RP __builtin_HEXAGON_S4_extract_rp + +/* ========================================================================== + Assembly Syntax: Rdd32=extract(Rss32,#u6,#U6) + C Intrinsic Prototype: Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_extract_PII __builtin_HEXAGON_S4_extractp + +/* ========================================================================== + Assembly Syntax: Rdd32=extract(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_extract_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_extract_PP __builtin_HEXAGON_S4_extractp_rp + +/* ========================================================================== + Assembly Syntax: Rd32=lsl(#s6,Rt32) + C Intrinsic Prototype: Word32 Q6_R_lsl_IR(Word32 Is6, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_lsl_IR __builtin_HEXAGON_S4_lsli + +/* ========================================================================== + Assembly Syntax: Pd4=!tstbit(Rs32,#u5) + C Intrinsic Prototype: Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_tstbit_RI __builtin_HEXAGON_S4_ntstbit_i + +/* ========================================================================== + Assembly Syntax: Pd4=!tstbit(Rs32,Rt32) + C Intrinsic Prototype: Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_tstbit_RR __builtin_HEXAGON_S4_ntstbit_r + +/* ========================================================================== + Assembly Syntax: Rx32|=and(Rs32,#s10) + C Intrinsic Prototype: Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_andor_RI __builtin_HEXAGON_S4_or_andi + +/* ========================================================================== + Assembly Syntax: Rx32=or(Ru32,and(Rx32,#s10)) + C Intrinsic Prototype: Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_or_and_RRI __builtin_HEXAGON_S4_or_andix + +/* ========================================================================== + Assembly Syntax: Rx32|=or(Rs32,#s10) + C Intrinsic Prototype: Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, Word32 Is10) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_oror_RI __builtin_HEXAGON_S4_or_ori + +/* ========================================================================== + Assembly Syntax: Rx32=or(#u8,asl(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_or_asl_IRI __builtin_HEXAGON_S4_ori_asl_ri + +/* ========================================================================== + Assembly Syntax: Rx32=or(#u8,lsr(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_or_lsr_IRI __builtin_HEXAGON_S4_ori_lsr_ri + +/* ========================================================================== + Assembly Syntax: Rd32=parity(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_parity_RR __builtin_HEXAGON_S4_parity + +/* ========================================================================== + Assembly Syntax: Rd32=add(Rs32,sub(#s6,Ru32)) + C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_add_sub_RIR __builtin_HEXAGON_S4_subaddi + +/* ========================================================================== + Assembly Syntax: Rx32=sub(#u8,asl(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_asl_IRI __builtin_HEXAGON_S4_subi_asl_ri + +/* ========================================================================== + Assembly Syntax: Rx32=sub(#u8,lsr(Rx32,#U5)) + C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_sub_lsr_IRI __builtin_HEXAGON_S4_subi_lsr_ri + +/* ========================================================================== + Assembly Syntax: Rdd32=vrcrotate(Rss32,Rt32,#u2) + C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcrotate_PRI __builtin_HEXAGON_S4_vrcrotate + +/* ========================================================================== + Assembly Syntax: Rxx32+=vrcrotate(Rss32,Rt32,#u2) + C Intrinsic Prototype: Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vrcrotateacc_PRI __builtin_HEXAGON_S4_vrcrotate_acc + +/* ========================================================================== + Assembly Syntax: Rdd32=vxaddsubh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxaddsubh_PP_sat __builtin_HEXAGON_S4_vxaddsubh + +/* ========================================================================== + Assembly Syntax: Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat + C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxaddsubh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxaddsubhr + +/* ========================================================================== + Assembly Syntax: Rdd32=vxaddsubw(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxaddsubw_PP_sat __builtin_HEXAGON_S4_vxaddsubw + +/* ========================================================================== + Assembly Syntax: Rdd32=vxsubaddh(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxsubaddh_PP_sat __builtin_HEXAGON_S4_vxsubaddh + +/* ========================================================================== + Assembly Syntax: Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat + C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxsubaddh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxsubaddhr + +/* ========================================================================== + Assembly Syntax: Rdd32=vxsubaddw(Rss32,Rtt32):sat + C Intrinsic Prototype: Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vxsubaddw_PP_sat __builtin_HEXAGON_S4_vxsubaddw + +/* ========================================================================== + Assembly Syntax: Rd32=vasrhub(Rss32,#u4):rnd:sat + C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_rnd_sat(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_R_vasrhub_PI_rnd_sat __builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax + +/* ========================================================================== + Assembly Syntax: Rd32=vasrhub(Rss32,#u4):sat + C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_sat(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_vasrhub_PI_sat __builtin_HEXAGON_S5_asrhub_sat + +/* ========================================================================== + Assembly Syntax: Rd32=popcount(Rss32) + C Intrinsic Prototype: Word32 Q6_R_popcount_P(Word64 Rss) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_popcount_P __builtin_HEXAGON_S5_popcountp + +/* ========================================================================== + Assembly Syntax: Rdd32=vasrh(Rss32,#u4):rnd + C Intrinsic Prototype: Word64 Q6_P_vasrh_PI_rnd(Word64 Rss, Word32 Iu4) + Instruction Type: S_2op + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_P_vasrh_PI_rnd __builtin_HEXAGON_S5_vasrhrnd_goodsyntax + +/* ========================================================================== + Assembly Syntax: dccleana(Rs32) + C Intrinsic Prototype: void Q6_dccleana_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dccleana_A __builtin_HEXAGON_Y2_dccleana + +/* ========================================================================== + Assembly Syntax: dccleaninva(Rs32) + C Intrinsic Prototype: void Q6_dccleaninva_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dccleaninva_A __builtin_HEXAGON_Y2_dccleaninva + +/* ========================================================================== + Assembly Syntax: dcfetch(Rs32) + C Intrinsic Prototype: void Q6_dcfetch_A(Address Rs) + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_dcfetch_A __builtin_HEXAGON_Y2_dcfetch + +/* ========================================================================== + Assembly Syntax: dcinva(Rs32) + C Intrinsic Prototype: void Q6_dcinva_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dcinva_A __builtin_HEXAGON_Y2_dcinva + +/* ========================================================================== + Assembly Syntax: dczeroa(Rs32) + C Intrinsic Prototype: void Q6_dczeroa_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dczeroa_A __builtin_HEXAGON_Y2_dczeroa + +/* ========================================================================== + Assembly Syntax: l2fetch(Rs32,Rt32) + C Intrinsic Prototype: void Q6_l2fetch_AR(Address Rs, Word32 Rt) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_l2fetch_AR __builtin_HEXAGON_Y4_l2fetch + +/* ========================================================================== + Assembly Syntax: l2fetch(Rs32,Rtt32) + C Intrinsic Prototype: void Q6_l2fetch_AP(Address Rs, Word64 Rtt) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_l2fetch_AP __builtin_HEXAGON_Y5_l2fetch + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rdd32=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rol_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rol_PI __builtin_HEXAGON_S6_rol_i_p +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32+=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rolacc_PI __builtin_HEXAGON_S6_rol_i_p_acc +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32&=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_roland_PI __builtin_HEXAGON_S6_rol_i_p_and +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32-=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rolnac_PI __builtin_HEXAGON_S6_rol_i_p_nac +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32|=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rolor_PI __builtin_HEXAGON_S6_rol_i_p_or +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rxx32^=rol(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_rolxacc_PI __builtin_HEXAGON_S6_rol_i_p_xacc +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rd32=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rol_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rol_RI __builtin_HEXAGON_S6_rol_i_r +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32+=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rolacc_RI __builtin_HEXAGON_S6_rol_i_r_acc +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32&=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_roland_RI __builtin_HEXAGON_S6_rol_i_r_and +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32-=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rolnac_RI __builtin_HEXAGON_S6_rol_i_r_nac +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32|=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rolor_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rolor_RI __builtin_HEXAGON_S6_rol_i_r_or +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rx32^=rol(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_rolxacc_RI __builtin_HEXAGON_S6_rol_i_r_xacc +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vabsdiffb(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 Rss) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsdiffb_PP __builtin_HEXAGON_M6_vabsdiffb +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vabsdiffub(Rtt32,Rss32) + C Intrinsic Prototype: Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, Word64 Rss) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vabsdiffub_PP __builtin_HEXAGON_M6_vabsdiffub +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vsplatb(Rs32) + C Intrinsic Prototype: Word64 Q6_P_vsplatb_R(Word32 Rs) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vsplatb_R __builtin_HEXAGON_S6_vsplatrbp +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vtrunehb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vtrunehb_PP __builtin_HEXAGON_S6_vtrunehb_ppp +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Rdd32=vtrunohb(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 Rtt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vtrunohb_PP __builtin_HEXAGON_S6_vtrunohb_ppp +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HEXAGON_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Pd4=!any8(vcmpb.eq(Rss32,Rtt32)) + C Intrinsic Prototype: Byte Q6_p_not_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) + Instruction Type: ALU64 + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_p_not_any8_vcmpb_eq_PP __builtin_HEXAGON_A6_vcmpbeq_notany +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HEXAGON_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Rdd32=dfadd(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfadd_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfadd_PP __builtin_HEXAGON_F2_dfadd +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HEXAGON_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Rdd32=dfsub(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfsub_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfsub_PP __builtin_HEXAGON_F2_dfsub +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HEXAGON_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Rx32-=mpyi(Rs32,Rt32) + C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32 Rt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mpyinac_RR __builtin_HEXAGON_M2_mnaci +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HEXAGON_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Rd32=mask(#u5,#U5) + C Intrinsic Prototype: Word32 Q6_R_mask_II(Word32 Iu5, Word32 IU5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_mask_II __builtin_HEXAGON_S2_mask +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=clip(Rs32,#u5) + C Intrinsic Prototype: Word32 Q6_R_clip_RI(Word32 Rs, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_R_clip_RI __builtin_HEXAGON_A7_clip +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cround(Rss32,#u6) + C Intrinsic Prototype: Word64 Q6_P_cround_PI(Word64 Rss, Word32 Iu6) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cround_PI __builtin_HEXAGON_A7_croundd_ri +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cround(Rss32,Rt32) + C Intrinsic Prototype: Word64 Q6_P_cround_PR(Word64 Rss, Word32 Rt) + Instruction Type: S_3op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_cround_PR __builtin_HEXAGON_A7_croundd_rr +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=vclip(Rss32,#u5) + C Intrinsic Prototype: Word64 Q6_P_vclip_PI(Word64 Rss, Word32 Iu5) + Instruction Type: S_2op + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_vclip_PI __builtin_HEXAGON_A7_vclip +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rdd32=dfmax(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmax_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmax_PP __builtin_HEXAGON_F2_dfmax +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rdd32=dfmin(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmin_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmin_PP __builtin_HEXAGON_F2_dfmin +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rdd32=dfmpyfix(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmpyfix_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmpyfix_PP __builtin_HEXAGON_F2_dfmpyfix +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rxx32+=dfmpyhh(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmpyhhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmpyhhacc_PP __builtin_HEXAGON_F2_dfmpyhh +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rxx32+=dfmpylh(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmpylhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmpylhacc_PP __builtin_HEXAGON_F2_dfmpylh +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 +/* ========================================================================== + Assembly Syntax: Rdd32=dfmpyll(Rss32,Rtt32) + C Intrinsic Prototype: Float64 Q6_P_dfmpyll_PP(Float64 Rss, Float64 Rtt) + Instruction Type: M + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_P_dfmpyll_PP __builtin_HEXAGON_F2_dfmpyll +#endif /* __HEXAGON_ARCH___ >= 67 */ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyiw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyiw_PP __builtin_HEXAGON_M7_dcmpyiw +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyiw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyiwacc_PP __builtin_HEXAGON_M7_dcmpyiw_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyiw(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP_conj(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyiw_PP_conj __builtin_HEXAGON_M7_dcmpyiwc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyiw(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyiwacc_PP_conj __builtin_HEXAGON_M7_dcmpyiwc_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyrw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyrw_PP __builtin_HEXAGON_M7_dcmpyrw +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyrw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyrwacc_PP __builtin_HEXAGON_M7_dcmpyrw_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=cmpyrw(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP_conj(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyrw_PP_conj __builtin_HEXAGON_M7_dcmpyrwc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=cmpyrw(Rss32,Rtt32*) + C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_cmpyrwacc_PP_conj __builtin_HEXAGON_M7_dcmpyrwc_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rdd32=vdmpyw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vdmpyw_PP(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_vdmpyw_PP __builtin_HEXAGON_M7_vdmpy +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rxx32+=vdmpyw(Rss32,Rtt32) + C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_P_vdmpywacc_PP __builtin_HEXAGON_M7_vdmpy_acc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyiw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyiw +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyiw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiw_rnd +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyiw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyiwc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyiw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiwc_rnd +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyrw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyrw +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyrw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrw_rnd +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyrw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyrwc +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ +/* ========================================================================== + Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat + C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt) + Instruction Type: M + Execution Slots: SLOT3 + ========================================================================== */ + +#define Q6_R_cmpyrw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrwc_rnd +#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: dmlink(Rs32,Rt32) + C Intrinsic Prototype: void Q6_dmlink_AA(Address Rs, Address Rt) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dmlink_AA __builtin_HEXAGON_Y6_dmlink +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Rd32=dmpause + C Intrinsic Prototype: Word32 Q6_R_dmpause() + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_dmpause __builtin_HEXAGON_Y6_dmpause +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Rd32=dmpoll + C Intrinsic Prototype: Word32 Q6_R_dmpoll() + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_dmpoll __builtin_HEXAGON_Y6_dmpoll +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: dmresume(Rs32) + C Intrinsic Prototype: void Q6_dmresume_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dmresume_A __builtin_HEXAGON_Y6_dmresume +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: dmstart(Rs32) + C Intrinsic Prototype: void Q6_dmstart_A(Address Rs) + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_dmstart_A __builtin_HEXAGON_Y6_dmstart +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HEXAGON_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Rd32=dmwait + C Intrinsic Prototype: Word32 Q6_R_dmwait() + Instruction Type: ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_dmwait __builtin_HEXAGON_Y6_dmwait +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#include +#ifdef __HVX__ +#include +#endif /* __HVX__ */ +#endif diff --git a/stdarch/crates/stdarch-gen-hexagon-scalar/src/main.rs b/stdarch/crates/stdarch-gen-hexagon-scalar/src/main.rs new file mode 100644 index 0000000000000..934c7e28fe374 --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon-scalar/src/main.rs @@ -0,0 +1,678 @@ +//! Hexagon Scalar Code Generator +//! +//! This generator creates scalar.rs from the LLVM `hexagon_protos.h` header file. +//! It parses the C intrinsic prototypes and generates Rust wrapper functions +//! with appropriate attributes for all scalar (non-HVX) Hexagon intrinsics. +//! +//! The generated module provides ~901 scalar intrinsic wrappers covering: +//! - Arithmetic, multiply, shift, saturate operations +//! - Compare, floating-point, and other scalar operations +//! +//! Intrinsics with `void*`/`void**` parameters (circular-addressing) are skipped +//! because they have no corresponding LLVM intrinsic. +//! +//! Usage: +//! cd crates/stdarch-gen-hexagon-scalar +//! cargo run +//! # Output is written to ../core_arch/src/hexagon/scalar.rs + +use regex::Regex; +use std::collections::HashMap; +use std::fs::File; +use std::io::Write; +use std::path::Path; + +/// Extract the instruction mnemonic from the assembly syntax string. +/// +/// Examples: +/// - `Rd32=abs(Rs32)` → Some("abs") +/// - `Rd32=add(Rs32,Rt32):sat` → Some("add") +/// - `Rx32+=mpy(Rs32,Rt32)` → Some("mpy") +/// - `Rd32=dmpause` → Some("dmpause") +/// - `dmlink(Rs32,Rt32)` → Some("dmlink") +/// - `Rd32=Rs32` → None (simple transfer) +/// - `Rx32.h=#u16` → None (immediate load) +/// - `Rdd32=#s8` → None (immediate load) +fn extract_instr_name(asm_syntax: &str) -> Option { + // Find the operator: +=, -=, or = + let after_op = if let Some(pos) = asm_syntax.find("+=") { + &asm_syntax[pos + 2..] + } else if let Some(pos) = asm_syntax.find("-=") { + &asm_syntax[pos + 2..] + } else if let Some(pos) = asm_syntax.find('=') { + &asm_syntax[pos + 1..] + } else { + // No assignment operator: try function-call-style syntax like "dmlink(Rs32,Rt32)". + // The mnemonic is the leading lowercase identifier. + return extract_leading_mnemonic(asm_syntax); + }; + + // After the operator, we expect a lowercase letter starting the mnemonic. + // Skip if it starts with uppercase (register name like Rs32) or # (immediate). + extract_leading_mnemonic(after_op) +} + +/// Extract a leading lowercase mnemonic from the given string. +/// +/// Returns `Some(mnemonic)` if the string starts with a lowercase ASCII letter, +/// collecting all subsequent alphanumeric/underscore characters. Returns `None` +/// if the string is empty or starts with an uppercase letter, `#`, etc. +fn extract_leading_mnemonic(s: &str) -> Option { + let first_char = s.chars().next()?; + if !first_char.is_ascii_lowercase() { + return None; + } + let mnemonic: String = s + .chars() + .take_while(|c| c.is_ascii_alphanumeric() || *c == '_') + .collect(); + if mnemonic.is_empty() { + None + } else { + Some(mnemonic) + } +} + +/// The tracking issue number for the stdarch_hexagon feature +const TRACKING_ISSUE: &str = "151523"; + +/// LLVM version the header file is from (for reference) +const LLVM_VERSION: &str = "22.1.0"; + +/// Local header file path (checked into the repository) +const HEADER_FILE: &str = "hexagon_protos.h"; + +/// Rust type representation for scalar intrinsics +#[derive(Debug, Clone, PartialEq)] +enum RustType { + I32, + I64, + F32, + F64, + Unit, +} + +impl RustType { + fn from_c_type(c_type: &str) -> Option { + match c_type.trim() { + "Word32" | "UWord32" | "Byte" | "Address" => Some(RustType::I32), + "Word64" | "UWord64" => Some(RustType::I64), + "Float32" => Some(RustType::F32), + "Float64" => Some(RustType::F64), + "void" => Some(RustType::Unit), + _ => None, + } + } + + fn to_rust_str(&self) -> &'static str { + match self { + RustType::I32 => "i32", + RustType::I64 => "i64", + RustType::F32 => "f32", + RustType::F64 => "f64", + RustType::Unit => "()", + } + } +} + +/// Information about an immediate operand parameter. +/// +/// Detected from C prototype parameter names like `Is16` (signed 16-bit), +/// `Iu5` (unsigned 5-bit), `IU5` (unsigned 5-bit secondary), `Iu6_2` +/// (unsigned 6-bit with 2-bit alignment). +#[derive(Debug, Clone)] +struct ImmediateInfo { + /// Whether this is a signed immediate + signed: bool, + /// Number of bits in the immediate field + bits: u32, +} + +/// Arch guard for an intrinsic +#[derive(Debug, Clone, PartialEq)] +enum ArchGuard { + /// No guard (base v5/v55 intrinsics) + None, + /// `#if __HEXAGON_ARCH__ >= N` + Arch(u32), + /// `#if __HEXAGON_ARCH__ >= N && defined __HEXAGON_AUDIO__` + ArchAudio(u32), +} + +impl ArchGuard { + /// Returns a doc comment describing the required architecture version, + /// or None if no specific version is needed. + fn requires_doc(&self) -> Option { + match self { + ArchGuard::None => Option::None, + ArchGuard::Arch(ver) => Some(format!("Requires: V{}", ver)), + ArchGuard::ArchAudio(ver) => Some(format!("Requires: V{}, Audio", ver)), + } + } + + /// Returns a `#[cfg_attr(target_arch = "hexagon", target_feature(enable = "..."))]` + /// attribute string, or None for base intrinsics that have no user-facing feature gate. + fn target_feature_attr(&self) -> Option { + match self { + ArchGuard::None => None, + ArchGuard::Arch(ver) => Some(format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"v{}\"))]", + ver + )), + ArchGuard::ArchAudio(ver) => Some(format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"v{},audio\"))]", + ver + )), + } + } +} + +/// Parsed scalar intrinsic information +#[derive(Debug, Clone)] +struct ScalarIntrinsic { + /// Q6 name (e.g., "Q6_R_add_RR") + q6_name: String, + /// Builtin suffix (e.g., "A2_add") - from __builtin_HEXAGON_A2_add + builtin_name: String, + /// Assembly syntax + asm_syntax: String, + /// Instruction type + instr_type: String, + /// Execution slots + exec_slots: String, + /// Return type + return_type: RustType, + /// Parameters (name, type, optional immediate info) + params: Vec<(String, RustType, Option)>, + /// Architecture guard + arch_guard: ArchGuard, +} + +impl ScalarIntrinsic { + /// Generate the LLVM link name: A2_add -> llvm.hexagon.A2.add + fn llvm_link_name(&self) -> String { + format!("llvm.hexagon.{}", self.builtin_name.replace('_', ".")) + } + + /// Generate the Rust function name: Q6_R_add_RR -> Q6_R_add_RR + /// + /// We preserve the original case because the Q6 naming convention uses + /// case to distinguish register types: + /// - `P` (uppercase) = 64-bit register pair (Word64) + /// - `p` (lowercase) = predicate register (Byte) + fn rust_fn_name(&self) -> String { + self.q6_name.clone() + } + + /// Generate the extern function name: A2_add -> hexagon_A2_add + fn extern_fn_name(&self) -> String { + format!("hexagon_{}", self.builtin_name) + } +} + +/// Read the local header file +fn read_header(crate_dir: &Path) -> Result { + let header_path = crate_dir.join(HEADER_FILE); + println!("Reading scalar header from: {}", header_path.display()); + println!(" (LLVM version: {})", LLVM_VERSION); + + std::fs::read_to_string(&header_path).map_err(|e| { + format!( + "Failed to read header file {}: {}", + header_path.display(), + e + ) + }) +} + +/// Detect whether a C parameter name represents an immediate operand. +/// +/// C prototype parameter names follow the pattern `I[usUS]\d+` for immediates: +/// - `Is16` → signed 16-bit +/// - `Iu5` → unsigned 5-bit +/// - `IS8` → signed 8-bit (secondary) +/// - `IU5` → unsigned 5-bit (secondary) +/// - `Iu6_2` → unsigned 6-bit (with alignment suffix) +fn detect_immediate(original_name: &str, imm_re: &Regex) -> Option { + imm_re.captures(original_name).map(|caps| { + let sign_char = &caps[1]; + let bits: u32 = caps[2].parse().unwrap(); + ImmediateInfo { + signed: sign_char == "s" || sign_char == "S", + bits, + } + }) +} + +/// Parse a C function prototype to extract return type and parameters +fn parse_prototype( + prototype: &str, + proto_re: &Regex, + param_re: &Regex, + imm_re: &Regex, +) -> Option<(RustType, Vec<(String, RustType, Option)>)> { + if let Some(caps) = proto_re.captures(prototype) { + let return_type_str = caps[1].trim(); + let params_str = &caps[2]; + + // Skip if return type is unknown + let return_type = RustType::from_c_type(return_type_str)?; + + let mut params = Vec::new(); + if !params_str.trim().is_empty() { + let mut name_counts: HashMap = HashMap::new(); + for param in params_str.split(',') { + let param = param.trim(); + if let Some(pcaps) = param_re.captures(param) { + let ptype_str = &pcaps[1]; + let original_name = &pcaps[2]; + let base_name = original_name.to_lowercase(); + + // Skip intrinsics with void* or void** params + if ptype_str.contains("void") { + return None; + } + + if let Some(ptype) = RustType::from_c_type(ptype_str) { + // Detect immediate operands from the original C name + let imm_info = detect_immediate(original_name, imm_re); + + // De-duplicate parameter names by appending a suffix + let count = name_counts.entry(base_name.clone()).or_insert(0); + *count += 1; + let pname = if *count > 1 { + format!("{}_{}", base_name, count) + } else { + base_name + }; + params.push((pname, ptype, imm_info)); + } else { + return None; // Unknown type + } + } + } + } + + Some((return_type, params)) + } else { + None + } +} + +/// Parse the header file to extract all scalar intrinsics +fn parse_header(content: &str) -> Vec { + let mut intrinsics = Vec::new(); + + // Pre-compile all regexes once + let arch_guard_re = Regex::new(r"#if __HEXAGON_ARCH__ >= (\d+)(.*)").unwrap(); + let q6_define_re = Regex::new(r"#define\s+(Q6_\w+)\s+__builtin_HEXAGON_(\w+)").unwrap(); + let proto_re = Regex::new(r"(\w+)\s+Q6_\w+\(([^)]*)\)").unwrap(); + let param_re = Regex::new(r"(\w+\*{0,2})\s+(\w+)").unwrap(); + let imm_re = Regex::new(r"^I([uUsS])(\d+)").unwrap(); + + let lines: Vec<&str> = content.lines().collect(); + let mut current_guard = ArchGuard::None; + let mut i = 0; + + while i < lines.len() { + let line = lines[i].trim(); + + // Track #if guards + if let Some(caps) = arch_guard_re.captures(line) { + let arch_ver: u32 = caps[1].parse().unwrap_or(0); + let rest = &caps[2]; + if rest.contains("__HEXAGON_AUDIO__") { + current_guard = ArchGuard::ArchAudio(arch_ver); + } else { + current_guard = ArchGuard::Arch(arch_ver); + } + i += 1; + continue; + } + + // Track #endif to reset guard + if line.starts_with("#endif") + && !line.contains("__HEXAGON_PROTOS_H_") + && !line.contains("__HVX__") + { + current_guard = ArchGuard::None; + i += 1; + continue; + } + + // Look for comment blocks with Assembly Syntax + if line.contains("Assembly Syntax:") { + let mut asm_syntax = String::new(); + let mut prototype = String::new(); + let mut instr_type = String::new(); + let mut exec_slots = String::new(); + + // Parse the comment block + let mut j = i; + while j < lines.len() && !lines[j].trim().starts_with("#define") { + let cline = lines[j]; + if cline.contains("Assembly Syntax:") { + if let Some(pos) = cline.find("Assembly Syntax:") { + asm_syntax = cline[pos + 16..].trim().to_string(); + } + } else if cline.contains("C Intrinsic Prototype:") { + if let Some(pos) = cline.find("C Intrinsic Prototype:") { + prototype = cline[pos + 22..].trim().to_string(); + } + } else if cline.contains("Instruction Type:") { + if let Some(pos) = cline.find("Instruction Type:") { + instr_type = cline[pos + 17..].trim().to_string(); + } + } else if cline.contains("Execution Slots:") { + if let Some(pos) = cline.find("Execution Slots:") { + exec_slots = cline[pos + 16..].trim().to_string(); + } + } + j += 1; + } + + // Find the #define line + while j < lines.len() && !lines[j].trim().starts_with("#define") { + j += 1; + } + + if j < lines.len() { + let define_line = lines[j]; + + if let Some(caps) = q6_define_re.captures(define_line) { + let q6_name = caps[1].to_string(); + let builtin_name = caps[2].to_string(); + + // Parse the C prototype + if let Some((return_type, params)) = + parse_prototype(&prototype, &proto_re, ¶m_re, &imm_re) + { + intrinsics.push(ScalarIntrinsic { + q6_name, + builtin_name, + asm_syntax, + instr_type, + exec_slots, + return_type, + params, + arch_guard: current_guard.clone(), + }); + } + } + } + i = j + 1; + continue; + } + + i += 1; + } + + intrinsics +} + +/// Generate the module documentation +fn generate_module_doc() -> String { + r#"//! Hexagon scalar intrinsics +//! +//! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations, +//! including arithmetic, multiply, shift, saturate, compare, and floating-point +//! operations. +//! +//! [Hexagon V68 Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-45) +//! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `P` (uppercase) = 64-bit register pair (`Word64`) +//! - `p` (lowercase) = predicate register (`Byte`) +//! +//! For example, `Q6_P_and_PP` operates on 64-bit pairs while `Q6_p_and_pp` +//! operates on predicate registers. +//! +//! ## Architecture Versions +//! +//! Most scalar intrinsics are available on all Hexagon architectures. +//! Some intrinsics require specific architecture versions (v60, v62, v65, +//! v66, v67, v68, or v67+audio) and carry +//! `#[target_feature(enable = "v68")]` (or the appropriate version). +//! Enable these with `-C target-feature=+v68` or by setting the target CPU +//! via `-C target-cpu=hexagonv68`. +//! +//! Each version includes all features from previous versions. + +#![allow(non_snake_case)] + +#[cfg(test)] +use stdarch_test::assert_instr; +"# + .to_string() +} + +/// Generate the extern block with LLVM intrinsic declarations +fn generate_extern_block(intrinsics: &[ScalarIntrinsic]) -> String { + let mut output = String::new(); + + output.push_str("// LLVM intrinsic declarations for Hexagon scalar operations\n"); + output.push_str("#[allow(improper_ctypes)]\n"); + output.push_str("unsafe extern \"unadjusted\" {\n"); + + for info in intrinsics { + let link_name = info.llvm_link_name(); + let fn_name = info.extern_fn_name(); + + let params_str = if info.params.is_empty() { + String::new() + } else { + info.params + .iter() + .map(|(_, t, _)| format!("_: {}", t.to_rust_str())) + .collect::>() + .join(", ") + }; + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + output.push_str(&format!( + " #[link_name = \"{}\"]\n fn {}({}){return_str};\n", + link_name, fn_name, params_str + )); + } + + output.push_str("}\n"); + output +} + +/// Generate wrapper functions for all intrinsics +fn generate_functions(intrinsics: &[ScalarIntrinsic]) -> String { + let mut output = String::new(); + + for info in intrinsics { + let rust_name = info.rust_fn_name(); + let extern_name = info.extern_fn_name(); + + // Collect immediate parameter info: (original_index, const_name, ImmediateInfo) + let imm_params: Vec<(usize, String, &ImmediateInfo)> = info + .params + .iter() + .enumerate() + .filter_map(|(i, (name, _, imm))| imm.as_ref().map(|im| (i, name.to_uppercase(), im))) + .collect(); + + // Doc comment + output.push_str(&format!("/// `{}`\n", info.asm_syntax)); + output.push_str("///\n"); + output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type)); + output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); + if let Some(req) = info.arch_guard.requires_doc() { + output.push_str(&format!("/// {}\n", req)); + } + + // Attributes + if let Some(tf_attr) = info.arch_guard.target_feature_attr() { + output.push_str("#[inline]\n"); // https://github.com/rust-lang/rust/issues/145574 + output.push_str(&format!("{}\n", tf_attr)); + } else { + output.push_str("#[inline(always)]\n"); + } + + // Immediate parameters become const generics but are passed as positional + // arguments at the call site: Q6_R_add_RI(rs, 42) rather than Q6_R_add_RI::<42>(rs). + // This matches the assembly syntax where the immediate is an operand. + if !imm_params.is_empty() { + let indices: Vec = imm_params.iter().map(|(i, _, _)| i.to_string()).collect(); + output.push_str(&format!( + "#[rustc_legacy_const_generics({})]\n", + indices.join(", ") + )); + } + + if let Some(instr) = extract_instr_name(&info.asm_syntax) { + if imm_params.is_empty() { + output.push_str(&format!("#[cfg_attr(test, assert_instr({}))]\n", instr)); + } else { + // Provide default values for const generics in assert_instr + let defaults: Vec = imm_params + .iter() + .map(|(_, name, _)| format!("{} = 0", name)) + .collect(); + output.push_str(&format!( + "#[cfg_attr(test, assert_instr({}, {}))]\n", + instr, + defaults.join(", ") + )); + } + } + + output.push_str(&format!( + "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n", + TRACKING_ISSUE + )); + + // Function signature: regular params exclude immediates, const generics added + let regular_params_str = info + .params + .iter() + .filter(|(_, _, imm)| imm.is_none()) + .map(|(name, ty, _)| format!("{}: {}", name, ty.to_rust_str())) + .collect::>() + .join(", "); + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + if imm_params.is_empty() { + output.push_str(&format!( + "pub unsafe fn {}({}){} {{\n", + rust_name, regular_params_str, return_str + )); + } else { + let const_generics: Vec = imm_params + .iter() + .map(|(_, name, imm)| { + let ty = if imm.signed { "i32" } else { "u32" }; + format!("const {}: {}", name, ty) + }) + .collect(); + output.push_str(&format!( + "pub unsafe fn {}<{}>({}){} {{\n", + rust_name, + const_generics.join(", "), + regular_params_str, + return_str + )); + } + + // Function body: static assertions then call + for (_, const_name, imm_info) in &imm_params { + if imm_info.signed { + output.push_str(&format!( + " static_assert_simm_bits!({}, {});\n", + const_name, imm_info.bits + )); + } else { + output.push_str(&format!( + " static_assert_uimm_bits!({}, {});\n", + const_name, imm_info.bits + )); + } + } + + // Call args: use original order, using const generic names for immediates. + // Unsigned const generics (u32) need a cast to i32 for the extern call. + let args_str = info + .params + .iter() + .map(|(name, _, imm)| match imm { + Some(info) if !info.signed => format!("{} as i32", name.to_uppercase()), + Some(_) => name.to_uppercase(), + None => name.clone(), + }) + .collect::>() + .join(", "); + + output.push_str(&format!(" {}({})\n", extern_name, args_str)); + output.push_str("}\n\n"); + } + + output +} + +/// Generate the complete scalar.rs file +fn generate_scalar_file(intrinsics: &[ScalarIntrinsic], output_path: &Path) -> Result<(), String> { + let mut output = + File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?; + + writeln!(output, "{}", generate_module_doc()).map_err(|e| e.to_string())?; + writeln!(output, "").map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_extern_block(intrinsics)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_functions(intrinsics)).map_err(|e| e.to_string())?; + + // Flush before running rustfmt + drop(output); + + // Run rustfmt on the generated file + let status = std::process::Command::new("rustfmt") + .arg(output_path) + .status() + .map_err(|e| format!("Failed to run rustfmt: {}", e))?; + + if !status.success() { + return Err("rustfmt failed".to_string()); + } + + Ok(()) +} + +fn main() -> Result<(), String> { + println!("=== Hexagon Scalar Code Generator ===\n"); + + let crate_dir = std::env::var("CARGO_MANIFEST_DIR") + .map(std::path::PathBuf::from) + .unwrap_or_else(|_| std::env::current_dir().unwrap()); + + let header_content = read_header(&crate_dir)?; + println!("Read {} bytes", header_content.len()); + + let intrinsics = parse_header(&header_content); + println!("Parsed {} scalar intrinsics", intrinsics.len()); + + let hexagon_dir = std::env::args() + .nth(1) + .map(std::path::PathBuf::from) + .unwrap_or_else(|| crate_dir.join("../core_arch/src/hexagon")); + std::fs::create_dir_all(&hexagon_dir).map_err(|e| e.to_string())?; + let scalar_path = hexagon_dir.join("scalar.rs"); + + generate_scalar_file(&intrinsics, &scalar_path)?; + println!("Generated scalar.rs at {}", scalar_path.display()); + + Ok(()) +} diff --git a/stdarch/crates/stdarch-gen-hexagon/src/main.rs b/stdarch/crates/stdarch-gen-hexagon/src/main.rs index 3cfbabfe0ab28..7a1c3030c0042 100644 --- a/stdarch/crates/stdarch-gen-hexagon/src/main.rs +++ b/stdarch/crates/stdarch-gen-hexagon/src/main.rs @@ -515,12 +515,6 @@ fn parse_header(content: &str) -> Vec { intrinsics } -/// Convert Q6 name to Rust function name (lowercase with underscores) -fn q6_to_rust_name(q6_name: &str) -> String { - // Q6_V_hi_W -> q6_v_hi_w - q6_name.to_lowercase() -} - /// Generate the module documentation fn generate_module_doc(mode: VectorMode) -> String { format!( @@ -541,6 +535,18 @@ fn generate_module_doc(mode: VectorMode) -> String { //! //! To use this module, compile with `-C target-feature=+{target_feature}`. //! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! //! ## Architecture Versions //! //! Different intrinsics require different HVX architecture versions. Use the @@ -577,6 +583,7 @@ fn generate_types(mode: VectorMode) -> String { format!( r#" #![allow(non_camel_case_types)] +#![allow(non_snake_case)] #[cfg(test)] use stdarch_test::assert_instr; @@ -1433,7 +1440,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { // Generate simple intrinsics for info in intrinsics.iter().filter(|i| !i.is_compound) { - let rust_name = q6_to_rust_name(&info.q6_name); + let rust_name = &info.q6_name; // Generate doc comment output.push_str(&format!("/// `{}`\n", info.asm_syntax)); @@ -1442,7 +1449,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); // Generate attributes - output.push_str("#[inline(always)]\n"); + output.push_str("#[inline]\n"); output.push_str(&format!( "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n", info.min_arch @@ -1505,7 +1512,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { let overrides = get_compound_overrides(); for info in intrinsics.iter().filter(|i| i.is_compound) { if let Some(ref compound_expr) = info.compound_expr { - let rust_name = q6_to_rust_name(&info.q6_name); + let rust_name = &info.q6_name; // Get the primary instruction for assert_instr let _primary_instr = get_compound_primary_instr(compound_expr) @@ -1525,7 +1532,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { } // Generate attributes - output.push_str("#[inline(always)]\n"); + output.push_str("#[inline]\n"); output.push_str(&format!( "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n", info.min_arch @@ -1684,7 +1691,11 @@ fn main() -> Result<(), String> { } // Generate output files - let hexagon_dir = crate_dir.join("../core_arch/src/hexagon"); + let hexagon_dir = std::env::args() + .nth(1) + .map(std::path::PathBuf::from) + .unwrap_or_else(|| crate_dir.join("../core_arch/src/hexagon")); + std::fs::create_dir_all(&hexagon_dir).map_err(|e| e.to_string())?; // Generate v64.rs (64-byte vector mode) let v64_path = hexagon_dir.join("v64.rs"); diff --git a/stdarch/crates/stdarch-gen-loongarch/lasx.spec b/stdarch/crates/stdarch-gen-loongarch/lasx.spec index ac4203a03f207..c74199c6a6e4c 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lasx.spec +++ b/stdarch/crates/stdarch-gen-loongarch/lasx.spec @@ -4,81 +4,97 @@ // ``` /// lasx_xvsll_b +impl = portable name = lasx_xvsll_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsll_h +impl = portable name = lasx_xvsll_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsll_w +impl = portable name = lasx_xvsll_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsll_d +impl = portable name = lasx_xvsll_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvslli_b +impl = portable name = lasx_xvslli_b asm-fmts = xd, xj, ui3 data-types = V32QI, V32QI, UQI /// lasx_xvslli_h +impl = portable name = lasx_xvslli_h asm-fmts = xd, xj, ui4 data-types = V16HI, V16HI, UQI /// lasx_xvslli_w +impl = portable name = lasx_xvslli_w asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvslli_d +impl = portable name = lasx_xvslli_d asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI /// lasx_xvsra_b +impl = portable name = lasx_xvsra_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsra_h +impl = portable name = lasx_xvsra_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsra_w +impl = portable name = lasx_xvsra_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsra_d +impl = portable name = lasx_xvsra_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvsrai_b +impl = portable name = lasx_xvsrai_b asm-fmts = xd, xj, ui3 data-types = V32QI, V32QI, UQI /// lasx_xvsrai_h +impl = portable name = lasx_xvsrai_h asm-fmts = xd, xj, ui4 data-types = V16HI, V16HI, UQI /// lasx_xvsrai_w +impl = portable name = lasx_xvsrai_w asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvsrai_d +impl = portable name = lasx_xvsrai_d asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI @@ -124,41 +140,49 @@ asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI /// lasx_xvsrl_b +impl = portable name = lasx_xvsrl_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsrl_h +impl = portable name = lasx_xvsrl_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsrl_w +impl = portable name = lasx_xvsrl_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsrl_d +impl = portable name = lasx_xvsrl_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvsrli_b +impl = portable name = lasx_xvsrli_b asm-fmts = xd, xj, ui3 data-types = V32QI, V32QI, UQI /// lasx_xvsrli_h +impl = portable name = lasx_xvsrli_h asm-fmts = xd, xj, ui4 data-types = V16HI, V16HI, UQI /// lasx_xvsrli_w +impl = portable name = lasx_xvsrli_w asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvsrli_d +impl = portable name = lasx_xvsrli_d asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI @@ -204,21 +228,25 @@ asm-fmts = xd, xj, ui6 data-types = V4DI, V4DI, UQI /// lasx_xvbitclr_b +impl = portable name = lasx_xvbitclr_b asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvbitclr_h +impl = portable name = lasx_xvbitclr_h asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvbitclr_w +impl = portable name = lasx_xvbitclr_w asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvbitclr_d +impl = portable name = lasx_xvbitclr_d asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -244,21 +272,25 @@ asm-fmts = xd, xj, ui6 data-types = UV4DI, UV4DI, UQI /// lasx_xvbitset_b +impl = portable name = lasx_xvbitset_b asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvbitset_h +impl = portable name = lasx_xvbitset_h asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvbitset_w +impl = portable name = lasx_xvbitset_w asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvbitset_d +impl = portable name = lasx_xvbitset_d asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -284,21 +316,25 @@ asm-fmts = xd, xj, ui6 data-types = UV4DI, UV4DI, UQI /// lasx_xvbitrev_b +impl = portable name = lasx_xvbitrev_b asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvbitrev_h +impl = portable name = lasx_xvbitrev_h asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvbitrev_w +impl = portable name = lasx_xvbitrev_w asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvbitrev_d +impl = portable name = lasx_xvbitrev_d asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -324,61 +360,73 @@ asm-fmts = xd, xj, ui6 data-types = UV4DI, UV4DI, UQI /// lasx_xvadd_b +impl = portable name = lasx_xvadd_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvadd_h +impl = portable name = lasx_xvadd_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvadd_w +impl = portable name = lasx_xvadd_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvadd_d +impl = portable name = lasx_xvadd_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvaddi_bu +impl = portable name = lasx_xvaddi_bu asm-fmts = xd, xj, ui5 data-types = V32QI, V32QI, UQI /// lasx_xvaddi_hu +impl = portable name = lasx_xvaddi_hu asm-fmts = xd, xj, ui5 data-types = V16HI, V16HI, UQI /// lasx_xvaddi_wu +impl = portable name = lasx_xvaddi_wu asm-fmts = xd, xj, ui5 data-types = V8SI, V8SI, UQI /// lasx_xvaddi_du +impl = portable name = lasx_xvaddi_du asm-fmts = xd, xj, ui5 data-types = V4DI, V4DI, UQI /// lasx_xvsub_b +impl = portable name = lasx_xvsub_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsub_h +impl = portable name = lasx_xvsub_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsub_w +impl = portable name = lasx_xvsub_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsub_d +impl = portable name = lasx_xvsub_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI @@ -404,361 +452,433 @@ asm-fmts = xd, xj, ui5 data-types = V4DI, V4DI, UQI /// lasx_xvmax_b +impl = portable name = lasx_xvmax_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmax_h +impl = portable name = lasx_xvmax_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmax_w +impl = portable name = lasx_xvmax_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmax_d +impl = portable name = lasx_xvmax_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmaxi_b +impl = portable name = lasx_xvmaxi_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvmaxi_h +impl = portable name = lasx_xvmaxi_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvmaxi_w +impl = portable name = lasx_xvmaxi_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvmaxi_d +impl = portable name = lasx_xvmaxi_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvmax_bu +impl = portable name = lasx_xvmax_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvmax_hu +impl = portable name = lasx_xvmax_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvmax_wu +impl = portable name = lasx_xvmax_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvmax_du +impl = portable name = lasx_xvmax_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvmaxi_bu +impl = portable name = lasx_xvmaxi_bu asm-fmts = xd, xj, ui5 data-types = UV32QI, UV32QI, UQI /// lasx_xvmaxi_hu +impl = portable name = lasx_xvmaxi_hu asm-fmts = xd, xj, ui5 data-types = UV16HI, UV16HI, UQI /// lasx_xvmaxi_wu +impl = portable name = lasx_xvmaxi_wu asm-fmts = xd, xj, ui5 data-types = UV8SI, UV8SI, UQI /// lasx_xvmaxi_du +impl = portable name = lasx_xvmaxi_du asm-fmts = xd, xj, ui5 data-types = UV4DI, UV4DI, UQI /// lasx_xvmin_b +impl = portable name = lasx_xvmin_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmin_h +impl = portable name = lasx_xvmin_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmin_w +impl = portable name = lasx_xvmin_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmin_d +impl = portable name = lasx_xvmin_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmini_b +impl = portable name = lasx_xvmini_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvmini_h +impl = portable name = lasx_xvmini_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvmini_w +impl = portable name = lasx_xvmini_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvmini_d +impl = portable name = lasx_xvmini_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvmin_bu +impl = portable name = lasx_xvmin_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvmin_hu +impl = portable name = lasx_xvmin_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvmin_wu +impl = portable name = lasx_xvmin_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvmin_du +impl = portable name = lasx_xvmin_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvmini_bu +impl = portable name = lasx_xvmini_bu asm-fmts = xd, xj, ui5 data-types = UV32QI, UV32QI, UQI /// lasx_xvmini_hu +impl = portable name = lasx_xvmini_hu asm-fmts = xd, xj, ui5 data-types = UV16HI, UV16HI, UQI /// lasx_xvmini_wu +impl = portable name = lasx_xvmini_wu asm-fmts = xd, xj, ui5 data-types = UV8SI, UV8SI, UQI /// lasx_xvmini_du +impl = portable name = lasx_xvmini_du asm-fmts = xd, xj, ui5 data-types = UV4DI, UV4DI, UQI /// lasx_xvseq_b +impl = portable name = lasx_xvseq_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvseq_h +impl = portable name = lasx_xvseq_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvseq_w +impl = portable name = lasx_xvseq_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvseq_d +impl = portable name = lasx_xvseq_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvseqi_b +impl = portable name = lasx_xvseqi_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvseqi_h +impl = portable name = lasx_xvseqi_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvseqi_w +impl = portable name = lasx_xvseqi_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvseqi_d +impl = portable name = lasx_xvseqi_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvslt_b +impl = portable name = lasx_xvslt_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvslt_h +impl = portable name = lasx_xvslt_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvslt_w +impl = portable name = lasx_xvslt_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvslt_d +impl = portable name = lasx_xvslt_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvslti_b +impl = portable name = lasx_xvslti_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvslti_h +impl = portable name = lasx_xvslti_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvslti_w +impl = portable name = lasx_xvslti_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvslti_d +impl = portable name = lasx_xvslti_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvslt_bu +impl = portable name = lasx_xvslt_bu asm-fmts = xd, xj, xk data-types = V32QI, UV32QI, UV32QI /// lasx_xvslt_hu +impl = portable name = lasx_xvslt_hu asm-fmts = xd, xj, xk data-types = V16HI, UV16HI, UV16HI /// lasx_xvslt_wu +impl = portable name = lasx_xvslt_wu asm-fmts = xd, xj, xk data-types = V8SI, UV8SI, UV8SI /// lasx_xvslt_du +impl = portable name = lasx_xvslt_du asm-fmts = xd, xj, xk data-types = V4DI, UV4DI, UV4DI /// lasx_xvslti_bu +impl = portable name = lasx_xvslti_bu asm-fmts = xd, xj, ui5 data-types = V32QI, UV32QI, UQI /// lasx_xvslti_hu +impl = portable name = lasx_xvslti_hu asm-fmts = xd, xj, ui5 data-types = V16HI, UV16HI, UQI /// lasx_xvslti_wu +impl = portable name = lasx_xvslti_wu asm-fmts = xd, xj, ui5 data-types = V8SI, UV8SI, UQI /// lasx_xvslti_du +impl = portable name = lasx_xvslti_du asm-fmts = xd, xj, ui5 data-types = V4DI, UV4DI, UQI /// lasx_xvsle_b +impl = portable name = lasx_xvsle_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsle_h +impl = portable name = lasx_xvsle_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsle_w +impl = portable name = lasx_xvsle_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsle_d +impl = portable name = lasx_xvsle_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvslei_b +impl = portable name = lasx_xvslei_b asm-fmts = xd, xj, si5 data-types = V32QI, V32QI, QI /// lasx_xvslei_h +impl = portable name = lasx_xvslei_h asm-fmts = xd, xj, si5 data-types = V16HI, V16HI, QI /// lasx_xvslei_w +impl = portable name = lasx_xvslei_w asm-fmts = xd, xj, si5 data-types = V8SI, V8SI, QI /// lasx_xvslei_d +impl = portable name = lasx_xvslei_d asm-fmts = xd, xj, si5 data-types = V4DI, V4DI, QI /// lasx_xvsle_bu +impl = portable name = lasx_xvsle_bu asm-fmts = xd, xj, xk data-types = V32QI, UV32QI, UV32QI /// lasx_xvsle_hu +impl = portable name = lasx_xvsle_hu asm-fmts = xd, xj, xk data-types = V16HI, UV16HI, UV16HI /// lasx_xvsle_wu +impl = portable name = lasx_xvsle_wu asm-fmts = xd, xj, xk data-types = V8SI, UV8SI, UV8SI /// lasx_xvsle_du +impl = portable name = lasx_xvsle_du asm-fmts = xd, xj, xk data-types = V4DI, UV4DI, UV4DI /// lasx_xvslei_bu +impl = portable name = lasx_xvslei_bu asm-fmts = xd, xj, ui5 data-types = V32QI, UV32QI, UQI /// lasx_xvslei_hu +impl = portable name = lasx_xvslei_hu asm-fmts = xd, xj, ui5 data-types = V16HI, UV16HI, UQI /// lasx_xvslei_wu +impl = portable name = lasx_xvslei_wu asm-fmts = xd, xj, ui5 data-types = V8SI, UV8SI, UQI /// lasx_xvslei_du +impl = portable name = lasx_xvslei_du asm-fmts = xd, xj, ui5 data-types = V4DI, UV4DI, UQI @@ -804,61 +924,73 @@ asm-fmts = xd, xj, ui6 data-types = UV4DI, UV4DI, UQI /// lasx_xvadda_b +impl = portable name = lasx_xvadda_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvadda_h +impl = portable name = lasx_xvadda_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvadda_w +impl = portable name = lasx_xvadda_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvadda_d +impl = portable name = lasx_xvadda_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvsadd_b +impl = portable name = lasx_xvsadd_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvsadd_h +impl = portable name = lasx_xvsadd_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvsadd_w +impl = portable name = lasx_xvsadd_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvsadd_d +impl = portable name = lasx_xvsadd_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvsadd_bu +impl = portable name = lasx_xvsadd_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvsadd_hu +impl = portable name = lasx_xvsadd_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvsadd_wu +impl = portable name = lasx_xvsadd_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvsadd_du +impl = portable name = lasx_xvsadd_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -944,181 +1076,217 @@ asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvssub_b +impl = portable name = lasx_xvssub_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvssub_h +impl = portable name = lasx_xvssub_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvssub_w +impl = portable name = lasx_xvssub_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvssub_d +impl = portable name = lasx_xvssub_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvssub_bu +impl = portable name = lasx_xvssub_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvssub_hu +impl = portable name = lasx_xvssub_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvssub_wu +impl = portable name = lasx_xvssub_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvssub_du +impl = portable name = lasx_xvssub_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvabsd_b +impl = portable name = lasx_xvabsd_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvabsd_h +impl = portable name = lasx_xvabsd_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvabsd_w +impl = portable name = lasx_xvabsd_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvabsd_d +impl = portable name = lasx_xvabsd_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvabsd_bu +impl = portable name = lasx_xvabsd_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvabsd_hu +impl = portable name = lasx_xvabsd_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvabsd_wu +impl = portable name = lasx_xvabsd_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvabsd_du +impl = portable name = lasx_xvabsd_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvmul_b +impl = portable name = lasx_xvmul_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmul_h +impl = portable name = lasx_xvmul_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmul_w +impl = portable name = lasx_xvmul_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmul_d +impl = portable name = lasx_xvmul_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmadd_b +impl = portable name = lasx_xvmadd_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI, V32QI /// lasx_xvmadd_h +impl = portable name = lasx_xvmadd_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI, V16HI /// lasx_xvmadd_w +impl = portable name = lasx_xvmadd_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI, V8SI /// lasx_xvmadd_d +impl = portable name = lasx_xvmadd_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI, V4DI /// lasx_xvmsub_b +impl = portable name = lasx_xvmsub_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI, V32QI /// lasx_xvmsub_h +impl = portable name = lasx_xvmsub_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI, V16HI /// lasx_xvmsub_w +impl = portable name = lasx_xvmsub_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI, V8SI /// lasx_xvmsub_d +impl = portable name = lasx_xvmsub_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI, V4DI /// lasx_xvdiv_b +impl = portable name = lasx_xvdiv_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvdiv_h +impl = portable name = lasx_xvdiv_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvdiv_w +impl = portable name = lasx_xvdiv_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvdiv_d +impl = portable name = lasx_xvdiv_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvdiv_bu +impl = portable name = lasx_xvdiv_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvdiv_hu +impl = portable name = lasx_xvdiv_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvdiv_wu +impl = portable name = lasx_xvdiv_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvdiv_du +impl = portable name = lasx_xvdiv_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI @@ -1184,141 +1352,169 @@ asm-fmts = xd, xj, xk data-types = V4DI, UV8SI, UV8SI /// lasx_xvmod_b +impl = portable name = lasx_xvmod_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvmod_h +impl = portable name = lasx_xvmod_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvmod_w +impl = portable name = lasx_xvmod_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvmod_d +impl = portable name = lasx_xvmod_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvmod_bu +impl = portable name = lasx_xvmod_bu asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvmod_hu +impl = portable name = lasx_xvmod_hu asm-fmts = xd, xj, xk data-types = UV16HI, UV16HI, UV16HI /// lasx_xvmod_wu +impl = portable name = lasx_xvmod_wu asm-fmts = xd, xj, xk data-types = UV8SI, UV8SI, UV8SI /// lasx_xvmod_du +impl = portable name = lasx_xvmod_du asm-fmts = xd, xj, xk data-types = UV4DI, UV4DI, UV4DI /// lasx_xvrepl128vei_b +impl = portable name = lasx_xvrepl128vei_b asm-fmts = xd, xj, ui4 data-types = V32QI, V32QI, UQI /// lasx_xvrepl128vei_h +impl = portable name = lasx_xvrepl128vei_h asm-fmts = xd, xj, ui3 data-types = V16HI, V16HI, UQI /// lasx_xvrepl128vei_w +impl = portable name = lasx_xvrepl128vei_w asm-fmts = xd, xj, ui2 data-types = V8SI, V8SI, UQI /// lasx_xvrepl128vei_d +impl = portable name = lasx_xvrepl128vei_d asm-fmts = xd, xj, ui1 data-types = V4DI, V4DI, UQI /// lasx_xvpickev_b +impl = portable name = lasx_xvpickev_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvpickev_h +impl = portable name = lasx_xvpickev_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvpickev_w +impl = portable name = lasx_xvpickev_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvpickev_d +impl = portable name = lasx_xvpickev_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvpickod_b +impl = portable name = lasx_xvpickod_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvpickod_h +impl = portable name = lasx_xvpickod_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvpickod_w +impl = portable name = lasx_xvpickod_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvpickod_d +impl = portable name = lasx_xvpickod_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvilvh_b +impl = portable name = lasx_xvilvh_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvilvh_h +impl = portable name = lasx_xvilvh_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvilvh_w +impl = portable name = lasx_xvilvh_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvilvh_d +impl = portable name = lasx_xvilvh_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvilvl_b +impl = portable name = lasx_xvilvl_b asm-fmts = xd, xj, xk data-types = V32QI, V32QI, V32QI /// lasx_xvilvl_h +impl = portable name = lasx_xvilvl_h asm-fmts = xd, xj, xk data-types = V16HI, V16HI, V16HI /// lasx_xvilvl_w +impl = portable name = lasx_xvilvl_w asm-fmts = xd, xj, xk data-types = V8SI, V8SI, V8SI /// lasx_xvilvl_d +impl = portable name = lasx_xvilvl_d asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI @@ -1384,6 +1580,7 @@ asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI, V4DI /// lasx_xvand_v +impl = portable name = lasx_xvand_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -1394,6 +1591,7 @@ asm-fmts = xd, xj, ui8 data-types = UV32QI, UV32QI, UQI /// lasx_xvor_v +impl = portable name = lasx_xvor_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -1404,6 +1602,7 @@ asm-fmts = xd, xj, ui8 data-types = UV32QI, UV32QI, UQI /// lasx_xvnor_v +impl = portable name = lasx_xvnor_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -1414,6 +1613,7 @@ asm-fmts = xd, xj, ui8 data-types = UV32QI, UV32QI, UQI /// lasx_xvxor_v +impl = portable name = lasx_xvxor_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -1449,41 +1649,49 @@ asm-fmts = xd, xj, ui8 data-types = V8SI, V8SI, USI /// lasx_xvreplgr2vr_b +impl = portable name = lasx_xvreplgr2vr_b asm-fmts = xd, rj data-types = V32QI, SI /// lasx_xvreplgr2vr_h +impl = portable name = lasx_xvreplgr2vr_h asm-fmts = xd, rj data-types = V16HI, SI /// lasx_xvreplgr2vr_w +impl = portable name = lasx_xvreplgr2vr_w asm-fmts = xd, rj data-types = V8SI, SI /// lasx_xvreplgr2vr_d +impl = portable name = lasx_xvreplgr2vr_d asm-fmts = xd, rj data-types = V4DI, DI /// lasx_xvpcnt_b +impl = portable name = lasx_xvpcnt_b asm-fmts = xd, xj data-types = V32QI, V32QI /// lasx_xvpcnt_h +impl = portable name = lasx_xvpcnt_h asm-fmts = xd, xj data-types = V16HI, V16HI /// lasx_xvpcnt_w +impl = portable name = lasx_xvpcnt_w asm-fmts = xd, xj data-types = V8SI, V8SI /// lasx_xvpcnt_d +impl = portable name = lasx_xvpcnt_d asm-fmts = xd, xj data-types = V4DI, V4DI @@ -1509,61 +1717,73 @@ asm-fmts = xd, xj data-types = V4DI, V4DI /// lasx_xvclz_b +impl = portable name = lasx_xvclz_b asm-fmts = xd, xj data-types = V32QI, V32QI /// lasx_xvclz_h +impl = portable name = lasx_xvclz_h asm-fmts = xd, xj data-types = V16HI, V16HI /// lasx_xvclz_w +impl = portable name = lasx_xvclz_w asm-fmts = xd, xj data-types = V8SI, V8SI /// lasx_xvclz_d +impl = portable name = lasx_xvclz_d asm-fmts = xd, xj data-types = V4DI, V4DI /// lasx_xvfadd_s +impl = portable name = lasx_xvfadd_s asm-fmts = xd, xj, xk data-types = V8SF, V8SF, V8SF /// lasx_xvfadd_d +impl = portable name = lasx_xvfadd_d asm-fmts = xd, xj, xk data-types = V4DF, V4DF, V4DF /// lasx_xvfsub_s +impl = portable name = lasx_xvfsub_s asm-fmts = xd, xj, xk data-types = V8SF, V8SF, V8SF /// lasx_xvfsub_d +impl = portable name = lasx_xvfsub_d asm-fmts = xd, xj, xk data-types = V4DF, V4DF, V4DF /// lasx_xvfmul_s +impl = portable name = lasx_xvfmul_s asm-fmts = xd, xj, xk data-types = V8SF, V8SF, V8SF /// lasx_xvfmul_d +impl = portable name = lasx_xvfmul_d asm-fmts = xd, xj, xk data-types = V4DF, V4DF, V4DF /// lasx_xvfdiv_s +impl = portable name = lasx_xvfdiv_s asm-fmts = xd, xj, xk data-types = V8SF, V8SF, V8SF /// lasx_xvfdiv_d +impl = portable name = lasx_xvfdiv_d asm-fmts = xd, xj, xk data-types = V4DF, V4DF, V4DF @@ -1629,11 +1849,13 @@ asm-fmts = xd, xj data-types = V4DI, V4DF /// lasx_xvfsqrt_s +impl = portable name = lasx_xvfsqrt_s asm-fmts = xd, xj data-types = V8SF, V8SF /// lasx_xvfsqrt_d +impl = portable name = lasx_xvfsqrt_d asm-fmts = xd, xj data-types = V4DF, V4DF @@ -1804,26 +2026,31 @@ asm-fmts = xd, xj, ui8 data-types = V8SI, V8SI, V8SI, USI /// lasx_xvandn_v +impl = portable name = lasx_xvandn_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI /// lasx_xvneg_b +impl = portable name = lasx_xvneg_b asm-fmts = xd, xj data-types = V32QI, V32QI /// lasx_xvneg_h +impl = portable name = lasx_xvneg_h asm-fmts = xd, xj data-types = V16HI, V16HI /// lasx_xvneg_w +impl = portable name = lasx_xvneg_w asm-fmts = xd, xj data-types = V8SI, V8SI /// lasx_xvneg_d +impl = portable name = lasx_xvneg_d asm-fmts = xd, xj data-types = V4DI, V4DI @@ -2144,41 +2371,49 @@ asm-fmts = xd, xj, xk data-types = V4DI, V4DI, V4DI /// lasx_xvfmadd_s +impl = portable name = lasx_xvfmadd_s asm-fmts = xd, xj, xk, xa data-types = V8SF, V8SF, V8SF, V8SF /// lasx_xvfmadd_d +impl = portable name = lasx_xvfmadd_d asm-fmts = xd, xj, xk, xa data-types = V4DF, V4DF, V4DF, V4DF /// lasx_xvfmsub_s +impl = portable name = lasx_xvfmsub_s asm-fmts = xd, xj, xk, xa data-types = V8SF, V8SF, V8SF, V8SF /// lasx_xvfmsub_d +impl = portable name = lasx_xvfmsub_d asm-fmts = xd, xj, xk, xa data-types = V4DF, V4DF, V4DF, V4DF /// lasx_xvfnmadd_s +impl = portable name = lasx_xvfnmadd_s asm-fmts = xd, xj, xk, xa data-types = V8SF, V8SF, V8SF, V8SF /// lasx_xvfnmadd_d +impl = portable name = lasx_xvfnmadd_d asm-fmts = xd, xj, xk, xa data-types = V4DF, V4DF, V4DF, V4DF /// lasx_xvfnmsub_s +impl = portable name = lasx_xvfnmsub_s asm-fmts = xd, xj, xk, xa data-types = V8SF, V8SF, V8SF, V8SF /// lasx_xvfnmsub_d +impl = portable name = lasx_xvfnmsub_d asm-fmts = xd, xj, xk, xa data-types = V4DF, V4DF, V4DF, V4DF @@ -2424,6 +2659,7 @@ asm-fmts = xd, xj, xk data-types = V8SI, V4DI, V4DI /// lasx_xvorn_v +impl = portable name = lasx_xvorn_v asm-fmts = xd, xj, xk data-types = UV32QI, UV32QI, UV32QI @@ -2449,36 +2685,43 @@ asm-fmts = xd, xj data-types = UV4DI, UV4DI /// lasx_xvinsgr2vr_w +impl = portable name = lasx_xvinsgr2vr_w asm-fmts = xd, rj, ui3 data-types = V8SI, V8SI, SI, UQI /// lasx_xvinsgr2vr_d +impl = portable name = lasx_xvinsgr2vr_d asm-fmts = xd, rj, ui2 data-types = V4DI, V4DI, DI, UQI /// lasx_xvreplve0_b +impl = portable name = lasx_xvreplve0_b asm-fmts = xd, xj data-types = V32QI, V32QI /// lasx_xvreplve0_h +impl = portable name = lasx_xvreplve0_h asm-fmts = xd, xj data-types = V16HI, V16HI /// lasx_xvreplve0_w +impl = portable name = lasx_xvreplve0_w asm-fmts = xd, xj data-types = V8SI, V8SI /// lasx_xvreplve0_d +impl = portable name = lasx_xvreplve0_d asm-fmts = xd, xj data-types = V4DI, V4DI /// lasx_xvreplve0_q +impl = portable name = lasx_xvreplve0_q asm-fmts = xd, xj data-types = V32QI, V32QI @@ -2579,21 +2822,25 @@ asm-fmts = xd, rj, si9 data-types = V4DI, CVPOINTER, SI /// lasx_xvpickve2gr_w +impl = portable name = lasx_xvpickve2gr_w asm-fmts = rd, xj, ui3 data-types = SI, V8SI, UQI /// lasx_xvpickve2gr_wu +impl = portable name = lasx_xvpickve2gr_wu asm-fmts = rd, xj, ui3 data-types = USI, V8SI, UQI /// lasx_xvpickve2gr_d +impl = portable name = lasx_xvpickve2gr_d asm-fmts = rd, xj, ui2 data-types = DI, V4DI, UQI /// lasx_xvpickve2gr_du +impl = portable name = lasx_xvpickve2gr_du asm-fmts = rd, xj, ui2 data-types = UDI, V4DI, UQI @@ -3684,21 +3931,25 @@ asm-fmts = xd, xj, ui3 data-types = V8SF, V8SF, UQI /// lasx_xvrepli_b +impl = portable name = lasx_xvrepli_b asm-fmts = xd, si10 data-types = V32QI, HI /// lasx_xvrepli_d +impl = portable name = lasx_xvrepli_d asm-fmts = xd, si10 data-types = V4DI, HI /// lasx_xvrepli_h +impl = portable name = lasx_xvrepli_h asm-fmts = xd, si10 data-types = V16HI, HI /// lasx_xvrepli_w +impl = portable name = lasx_xvrepli_w asm-fmts = xd, si10 data-types = V8SI, HI diff --git a/stdarch/crates/stdarch-gen-loongarch/lsx.spec b/stdarch/crates/stdarch-gen-loongarch/lsx.spec index b5497b6e6207e..c59f56a902d13 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lsx.spec +++ b/stdarch/crates/stdarch-gen-loongarch/lsx.spec @@ -4,81 +4,97 @@ // ``` /// lsx_vsll_b +impl = portable name = lsx_vsll_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsll_h +impl = portable name = lsx_vsll_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsll_w +impl = portable name = lsx_vsll_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsll_d +impl = portable name = lsx_vsll_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vslli_b +impl = portable name = lsx_vslli_b asm-fmts = vd, vj, ui3 data-types = V16QI, V16QI, UQI /// lsx_vslli_h +impl = portable name = lsx_vslli_h asm-fmts = vd, vj, ui4 data-types = V8HI, V8HI, UQI /// lsx_vslli_w +impl = portable name = lsx_vslli_w asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vslli_d +impl = portable name = lsx_vslli_d asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI /// lsx_vsra_b +impl = portable name = lsx_vsra_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsra_h +impl = portable name = lsx_vsra_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsra_w +impl = portable name = lsx_vsra_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsra_d +impl = portable name = lsx_vsra_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vsrai_b +impl = portable name = lsx_vsrai_b asm-fmts = vd, vj, ui3 data-types = V16QI, V16QI, UQI /// lsx_vsrai_h +impl = portable name = lsx_vsrai_h asm-fmts = vd, vj, ui4 data-types = V8HI, V8HI, UQI /// lsx_vsrai_w +impl = portable name = lsx_vsrai_w asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vsrai_d +impl = portable name = lsx_vsrai_d asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI @@ -124,41 +140,49 @@ asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI /// lsx_vsrl_b +impl = portable name = lsx_vsrl_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsrl_h +impl = portable name = lsx_vsrl_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsrl_w +impl = portable name = lsx_vsrl_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsrl_d +impl = portable name = lsx_vsrl_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vsrli_b +impl = portable name = lsx_vsrli_b asm-fmts = vd, vj, ui3 data-types = V16QI, V16QI, UQI /// lsx_vsrli_h +impl = portable name = lsx_vsrli_h asm-fmts = vd, vj, ui4 data-types = V8HI, V8HI, UQI /// lsx_vsrli_w +impl = portable name = lsx_vsrli_w asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vsrli_d +impl = portable name = lsx_vsrli_d asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI @@ -204,21 +228,25 @@ asm-fmts = vd, vj, ui6 data-types = V2DI, V2DI, UQI /// lsx_vbitclr_b +impl = portable name = lsx_vbitclr_b asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vbitclr_h +impl = portable name = lsx_vbitclr_h asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vbitclr_w +impl = portable name = lsx_vbitclr_w asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vbitclr_d +impl = portable name = lsx_vbitclr_d asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -244,21 +272,25 @@ asm-fmts = vd, vj, ui6 data-types = UV2DI, UV2DI, UQI /// lsx_vbitset_b +impl = portable name = lsx_vbitset_b asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vbitset_h +impl = portable name = lsx_vbitset_h asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vbitset_w +impl = portable name = lsx_vbitset_w asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vbitset_d +impl = portable name = lsx_vbitset_d asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -284,21 +316,25 @@ asm-fmts = vd, vj, ui6 data-types = UV2DI, UV2DI, UQI /// lsx_vbitrev_b +impl = portable name = lsx_vbitrev_b asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vbitrev_h +impl = portable name = lsx_vbitrev_h asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vbitrev_w +impl = portable name = lsx_vbitrev_w asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vbitrev_d +impl = portable name = lsx_vbitrev_d asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -324,61 +360,73 @@ asm-fmts = vd, vj, ui6 data-types = UV2DI, UV2DI, UQI /// lsx_vadd_b +impl = portable name = lsx_vadd_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vadd_h +impl = portable name = lsx_vadd_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vadd_w +impl = portable name = lsx_vadd_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vadd_d +impl = portable name = lsx_vadd_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vaddi_bu +impl = portable name = lsx_vaddi_bu asm-fmts = vd, vj, ui5 data-types = V16QI, V16QI, UQI /// lsx_vaddi_hu +impl = portable name = lsx_vaddi_hu asm-fmts = vd, vj, ui5 data-types = V8HI, V8HI, UQI /// lsx_vaddi_wu +impl = portable name = lsx_vaddi_wu asm-fmts = vd, vj, ui5 data-types = V4SI, V4SI, UQI /// lsx_vaddi_du +impl = portable name = lsx_vaddi_du asm-fmts = vd, vj, ui5 data-types = V2DI, V2DI, UQI /// lsx_vsub_b +impl = portable name = lsx_vsub_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsub_h +impl = portable name = lsx_vsub_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsub_w +impl = portable name = lsx_vsub_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsub_d +impl = portable name = lsx_vsub_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI @@ -404,361 +452,433 @@ asm-fmts = vd, vj, ui5 data-types = V2DI, V2DI, UQI /// lsx_vmax_b +impl = portable name = lsx_vmax_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmax_h +impl = portable name = lsx_vmax_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmax_w +impl = portable name = lsx_vmax_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmax_d +impl = portable name = lsx_vmax_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmaxi_b +impl = portable name = lsx_vmaxi_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vmaxi_h +impl = portable name = lsx_vmaxi_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vmaxi_w +impl = portable name = lsx_vmaxi_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vmaxi_d +impl = portable name = lsx_vmaxi_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vmax_bu +impl = portable name = lsx_vmax_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vmax_hu +impl = portable name = lsx_vmax_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vmax_wu +impl = portable name = lsx_vmax_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vmax_du +impl = portable name = lsx_vmax_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vmaxi_bu +impl = portable name = lsx_vmaxi_bu asm-fmts = vd, vj, ui5 data-types = UV16QI, UV16QI, UQI /// lsx_vmaxi_hu +impl = portable name = lsx_vmaxi_hu asm-fmts = vd, vj, ui5 data-types = UV8HI, UV8HI, UQI /// lsx_vmaxi_wu +impl = portable name = lsx_vmaxi_wu asm-fmts = vd, vj, ui5 data-types = UV4SI, UV4SI, UQI /// lsx_vmaxi_du +impl = portable name = lsx_vmaxi_du asm-fmts = vd, vj, ui5 data-types = UV2DI, UV2DI, UQI /// lsx_vmin_b +impl = portable name = lsx_vmin_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmin_h +impl = portable name = lsx_vmin_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmin_w +impl = portable name = lsx_vmin_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmin_d +impl = portable name = lsx_vmin_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmini_b +impl = portable name = lsx_vmini_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vmini_h +impl = portable name = lsx_vmini_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vmini_w +impl = portable name = lsx_vmini_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vmini_d +impl = portable name = lsx_vmini_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vmin_bu +impl = portable name = lsx_vmin_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vmin_hu +impl = portable name = lsx_vmin_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vmin_wu +impl = portable name = lsx_vmin_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vmin_du +impl = portable name = lsx_vmin_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vmini_bu +impl = portable name = lsx_vmini_bu asm-fmts = vd, vj, ui5 data-types = UV16QI, UV16QI, UQI /// lsx_vmini_hu +impl = portable name = lsx_vmini_hu asm-fmts = vd, vj, ui5 data-types = UV8HI, UV8HI, UQI /// lsx_vmini_wu +impl = portable name = lsx_vmini_wu asm-fmts = vd, vj, ui5 data-types = UV4SI, UV4SI, UQI /// lsx_vmini_du +impl = portable name = lsx_vmini_du asm-fmts = vd, vj, ui5 data-types = UV2DI, UV2DI, UQI /// lsx_vseq_b +impl = portable name = lsx_vseq_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vseq_h +impl = portable name = lsx_vseq_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vseq_w +impl = portable name = lsx_vseq_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vseq_d +impl = portable name = lsx_vseq_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vseqi_b +impl = portable name = lsx_vseqi_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vseqi_h +impl = portable name = lsx_vseqi_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vseqi_w +impl = portable name = lsx_vseqi_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vseqi_d +impl = portable name = lsx_vseqi_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vslti_b +impl = portable name = lsx_vslti_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vslt_b +impl = portable name = lsx_vslt_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vslt_h +impl = portable name = lsx_vslt_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vslt_w +impl = portable name = lsx_vslt_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vslt_d +impl = portable name = lsx_vslt_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vslti_h +impl = portable name = lsx_vslti_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vslti_w +impl = portable name = lsx_vslti_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vslti_d +impl = portable name = lsx_vslti_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vslt_bu +impl = portable name = lsx_vslt_bu asm-fmts = vd, vj, vk data-types = V16QI, UV16QI, UV16QI /// lsx_vslt_hu +impl = portable name = lsx_vslt_hu asm-fmts = vd, vj, vk data-types = V8HI, UV8HI, UV8HI /// lsx_vslt_wu +impl = portable name = lsx_vslt_wu asm-fmts = vd, vj, vk data-types = V4SI, UV4SI, UV4SI /// lsx_vslt_du +impl = portable name = lsx_vslt_du asm-fmts = vd, vj, vk data-types = V2DI, UV2DI, UV2DI /// lsx_vslti_bu +impl = portable name = lsx_vslti_bu asm-fmts = vd, vj, ui5 data-types = V16QI, UV16QI, UQI /// lsx_vslti_hu +impl = portable name = lsx_vslti_hu asm-fmts = vd, vj, ui5 data-types = V8HI, UV8HI, UQI /// lsx_vslti_wu +impl = portable name = lsx_vslti_wu asm-fmts = vd, vj, ui5 data-types = V4SI, UV4SI, UQI /// lsx_vslti_du +impl = portable name = lsx_vslti_du asm-fmts = vd, vj, ui5 data-types = V2DI, UV2DI, UQI /// lsx_vsle_b +impl = portable name = lsx_vsle_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsle_h +impl = portable name = lsx_vsle_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsle_w +impl = portable name = lsx_vsle_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsle_d +impl = portable name = lsx_vsle_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vslei_b +impl = portable name = lsx_vslei_b asm-fmts = vd, vj, si5 data-types = V16QI, V16QI, QI /// lsx_vslei_h +impl = portable name = lsx_vslei_h asm-fmts = vd, vj, si5 data-types = V8HI, V8HI, QI /// lsx_vslei_w +impl = portable name = lsx_vslei_w asm-fmts = vd, vj, si5 data-types = V4SI, V4SI, QI /// lsx_vslei_d +impl = portable name = lsx_vslei_d asm-fmts = vd, vj, si5 data-types = V2DI, V2DI, QI /// lsx_vsle_bu +impl = portable name = lsx_vsle_bu asm-fmts = vd, vj, vk data-types = V16QI, UV16QI, UV16QI /// lsx_vsle_hu +impl = portable name = lsx_vsle_hu asm-fmts = vd, vj, vk data-types = V8HI, UV8HI, UV8HI /// lsx_vsle_wu +impl = portable name = lsx_vsle_wu asm-fmts = vd, vj, vk data-types = V4SI, UV4SI, UV4SI /// lsx_vsle_du +impl = portable name = lsx_vsle_du asm-fmts = vd, vj, vk data-types = V2DI, UV2DI, UV2DI /// lsx_vslei_bu +impl = portable name = lsx_vslei_bu asm-fmts = vd, vj, ui5 data-types = V16QI, UV16QI, UQI /// lsx_vslei_hu +impl = portable name = lsx_vslei_hu asm-fmts = vd, vj, ui5 data-types = V8HI, UV8HI, UQI /// lsx_vslei_wu +impl = portable name = lsx_vslei_wu asm-fmts = vd, vj, ui5 data-types = V4SI, UV4SI, UQI /// lsx_vslei_du +impl = portable name = lsx_vslei_du asm-fmts = vd, vj, ui5 data-types = V2DI, UV2DI, UQI @@ -804,61 +924,73 @@ asm-fmts = vd, vj, ui6 data-types = UV2DI, UV2DI, UQI /// lsx_vadda_b +impl = portable name = lsx_vadda_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vadda_h +impl = portable name = lsx_vadda_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vadda_w +impl = portable name = lsx_vadda_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vadda_d +impl = portable name = lsx_vadda_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vsadd_b +impl = portable name = lsx_vsadd_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vsadd_h +impl = portable name = lsx_vsadd_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vsadd_w +impl = portable name = lsx_vsadd_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vsadd_d +impl = portable name = lsx_vsadd_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vsadd_bu +impl = portable name = lsx_vsadd_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vsadd_hu +impl = portable name = lsx_vsadd_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vsadd_wu +impl = portable name = lsx_vsadd_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vsadd_du +impl = portable name = lsx_vsadd_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -944,181 +1076,217 @@ asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vssub_b +impl = portable name = lsx_vssub_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vssub_h +impl = portable name = lsx_vssub_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vssub_w +impl = portable name = lsx_vssub_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vssub_d +impl = portable name = lsx_vssub_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vssub_bu +impl = portable name = lsx_vssub_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vssub_hu +impl = portable name = lsx_vssub_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vssub_wu +impl = portable name = lsx_vssub_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vssub_du +impl = portable name = lsx_vssub_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vabsd_b +impl = portable name = lsx_vabsd_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vabsd_h +impl = portable name = lsx_vabsd_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vabsd_w +impl = portable name = lsx_vabsd_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vabsd_d +impl = portable name = lsx_vabsd_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vabsd_bu +impl = portable name = lsx_vabsd_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vabsd_hu +impl = portable name = lsx_vabsd_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vabsd_wu +impl = portable name = lsx_vabsd_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vabsd_du +impl = portable name = lsx_vabsd_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI /// lsx_vmul_b +impl = portable name = lsx_vmul_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmul_h +impl = portable name = lsx_vmul_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmul_w +impl = portable name = lsx_vmul_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmul_d +impl = portable name = lsx_vmul_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmadd_b +impl = portable name = lsx_vmadd_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI, V16QI /// lsx_vmadd_h +impl = portable name = lsx_vmadd_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI, V8HI /// lsx_vmadd_w +impl = portable name = lsx_vmadd_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI, V4SI /// lsx_vmadd_d +impl = portable name = lsx_vmadd_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI, V2DI /// lsx_vmsub_b +impl = portable name = lsx_vmsub_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI, V16QI /// lsx_vmsub_h +impl = portable name = lsx_vmsub_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI, V8HI /// lsx_vmsub_w +impl = portable name = lsx_vmsub_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI, V4SI /// lsx_vmsub_d +impl = portable name = lsx_vmsub_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI, V2DI /// lsx_vdiv_b +impl = portable name = lsx_vdiv_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vdiv_h +impl = portable name = lsx_vdiv_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vdiv_w +impl = portable name = lsx_vdiv_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vdiv_d +impl = portable name = lsx_vdiv_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vdiv_bu +impl = portable name = lsx_vdiv_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vdiv_hu +impl = portable name = lsx_vdiv_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vdiv_wu +impl = portable name = lsx_vdiv_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vdiv_du +impl = portable name = lsx_vdiv_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -1184,41 +1352,49 @@ asm-fmts = vd, vj, vk data-types = V2DI, UV4SI, UV4SI /// lsx_vmod_b +impl = portable name = lsx_vmod_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vmod_h +impl = portable name = lsx_vmod_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vmod_w +impl = portable name = lsx_vmod_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vmod_d +impl = portable name = lsx_vmod_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vmod_bu +impl = portable name = lsx_vmod_bu asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vmod_hu +impl = portable name = lsx_vmod_hu asm-fmts = vd, vj, vk data-types = UV8HI, UV8HI, UV8HI /// lsx_vmod_wu +impl = portable name = lsx_vmod_wu asm-fmts = vd, vj, vk data-types = UV4SI, UV4SI, UV4SI /// lsx_vmod_du +impl = portable name = lsx_vmod_du asm-fmts = vd, vj, vk data-types = UV2DI, UV2DI, UV2DI @@ -1244,101 +1420,121 @@ asm-fmts = vd, vj, rk data-types = V2DI, V2DI, SI /// lsx_vreplvei_b +impl = portable name = lsx_vreplvei_b asm-fmts = vd, vj, ui4 data-types = V16QI, V16QI, UQI /// lsx_vreplvei_h +impl = portable name = lsx_vreplvei_h asm-fmts = vd, vj, ui3 data-types = V8HI, V8HI, UQI /// lsx_vreplvei_w +impl = portable name = lsx_vreplvei_w asm-fmts = vd, vj, ui2 data-types = V4SI, V4SI, UQI /// lsx_vreplvei_d +impl = portable name = lsx_vreplvei_d asm-fmts = vd, vj, ui1 data-types = V2DI, V2DI, UQI /// lsx_vpickev_b +impl = portable name = lsx_vpickev_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vpickev_h +impl = portable name = lsx_vpickev_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vpickev_w +impl = portable name = lsx_vpickev_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vpickev_d +impl = portable name = lsx_vpickev_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vpickod_b +impl = portable name = lsx_vpickod_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vpickod_h +impl = portable name = lsx_vpickod_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vpickod_w +impl = portable name = lsx_vpickod_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vpickod_d +impl = portable name = lsx_vpickod_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vilvh_b +impl = portable name = lsx_vilvh_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vilvh_h +impl = portable name = lsx_vilvh_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vilvh_w +impl = portable name = lsx_vilvh_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vilvh_d +impl = portable name = lsx_vilvh_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vilvl_b +impl = portable name = lsx_vilvl_b asm-fmts = vd, vj, vk data-types = V16QI, V16QI, V16QI /// lsx_vilvl_h +impl = portable name = lsx_vilvl_h asm-fmts = vd, vj, vk data-types = V8HI, V8HI, V8HI /// lsx_vilvl_w +impl = portable name = lsx_vilvl_w asm-fmts = vd, vj, vk data-types = V4SI, V4SI, V4SI /// lsx_vilvl_d +impl = portable name = lsx_vilvl_d asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI @@ -1399,6 +1595,7 @@ asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI, V2DI /// lsx_vand_v +impl = portable name = lsx_vand_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -1409,6 +1606,7 @@ asm-fmts = vd, vj, ui8 data-types = UV16QI, UV16QI, UQI /// lsx_vor_v +impl = portable name = lsx_vor_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -1419,6 +1617,7 @@ asm-fmts = vd, vj, ui8 data-types = UV16QI, UV16QI, UQI /// lsx_vnor_v +impl = portable name = lsx_vnor_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -1429,6 +1628,7 @@ asm-fmts = vd, vj, ui8 data-types = UV16QI, UV16QI, UQI /// lsx_vxor_v +impl = portable name = lsx_vxor_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -1464,41 +1664,49 @@ asm-fmts = vd, vj, ui8 data-types = V4SI, V4SI, USI /// lsx_vreplgr2vr_b +impl = portable name = lsx_vreplgr2vr_b asm-fmts = vd, rj data-types = V16QI, SI /// lsx_vreplgr2vr_h +impl = portable name = lsx_vreplgr2vr_h asm-fmts = vd, rj data-types = V8HI, SI /// lsx_vreplgr2vr_w +impl = portable name = lsx_vreplgr2vr_w asm-fmts = vd, rj data-types = V4SI, SI /// lsx_vreplgr2vr_d +impl = portable name = lsx_vreplgr2vr_d asm-fmts = vd, rj data-types = V2DI, DI /// lsx_vpcnt_b +impl = portable name = lsx_vpcnt_b asm-fmts = vd, vj data-types = V16QI, V16QI /// lsx_vpcnt_h +impl = portable name = lsx_vpcnt_h asm-fmts = vd, vj data-types = V8HI, V8HI /// lsx_vpcnt_w +impl = portable name = lsx_vpcnt_w asm-fmts = vd, vj data-types = V4SI, V4SI /// lsx_vpcnt_d +impl = portable name = lsx_vpcnt_d asm-fmts = vd, vj data-types = V2DI, V2DI @@ -1524,121 +1732,145 @@ asm-fmts = vd, vj data-types = V2DI, V2DI /// lsx_vclz_b +impl = portable name = lsx_vclz_b asm-fmts = vd, vj data-types = V16QI, V16QI /// lsx_vclz_h +impl = portable name = lsx_vclz_h asm-fmts = vd, vj data-types = V8HI, V8HI /// lsx_vclz_w +impl = portable name = lsx_vclz_w asm-fmts = vd, vj data-types = V4SI, V4SI /// lsx_vclz_d +impl = portable name = lsx_vclz_d asm-fmts = vd, vj data-types = V2DI, V2DI /// lsx_vpickve2gr_b +impl = portable name = lsx_vpickve2gr_b asm-fmts = rd, vj, ui4 data-types = SI, V16QI, UQI /// lsx_vpickve2gr_h +impl = portable name = lsx_vpickve2gr_h asm-fmts = rd, vj, ui3 data-types = SI, V8HI, UQI /// lsx_vpickve2gr_w +impl = portable name = lsx_vpickve2gr_w asm-fmts = rd, vj, ui2 data-types = SI, V4SI, UQI /// lsx_vpickve2gr_d +impl = portable name = lsx_vpickve2gr_d asm-fmts = rd, vj, ui1 data-types = DI, V2DI, UQI /// lsx_vpickve2gr_bu +impl = portable name = lsx_vpickve2gr_bu asm-fmts = rd, vj, ui4 data-types = USI, V16QI, UQI /// lsx_vpickve2gr_hu +impl = portable name = lsx_vpickve2gr_hu asm-fmts = rd, vj, ui3 data-types = USI, V8HI, UQI /// lsx_vpickve2gr_wu +impl = portable name = lsx_vpickve2gr_wu asm-fmts = rd, vj, ui2 data-types = USI, V4SI, UQI /// lsx_vpickve2gr_du +impl = portable name = lsx_vpickve2gr_du asm-fmts = rd, vj, ui1 data-types = UDI, V2DI, UQI /// lsx_vinsgr2vr_b +impl = portable name = lsx_vinsgr2vr_b asm-fmts = vd, rj, ui4 data-types = V16QI, V16QI, SI, UQI /// lsx_vinsgr2vr_h +impl = portable name = lsx_vinsgr2vr_h asm-fmts = vd, rj, ui3 data-types = V8HI, V8HI, SI, UQI /// lsx_vinsgr2vr_w +impl = portable name = lsx_vinsgr2vr_w asm-fmts = vd, rj, ui2 data-types = V4SI, V4SI, SI, UQI /// lsx_vinsgr2vr_d +impl = portable name = lsx_vinsgr2vr_d asm-fmts = vd, rj, ui1 data-types = V2DI, V2DI, DI, UQI /// lsx_vfadd_s +impl = portable name = lsx_vfadd_s asm-fmts = vd, vj, vk data-types = V4SF, V4SF, V4SF /// lsx_vfadd_d +impl = portable name = lsx_vfadd_d asm-fmts = vd, vj, vk data-types = V2DF, V2DF, V2DF /// lsx_vfsub_s +impl = portable name = lsx_vfsub_s asm-fmts = vd, vj, vk data-types = V4SF, V4SF, V4SF /// lsx_vfsub_d +impl = portable name = lsx_vfsub_d asm-fmts = vd, vj, vk data-types = V2DF, V2DF, V2DF /// lsx_vfmul_s +impl = portable name = lsx_vfmul_s asm-fmts = vd, vj, vk data-types = V4SF, V4SF, V4SF /// lsx_vfmul_d +impl = portable name = lsx_vfmul_d asm-fmts = vd, vj, vk data-types = V2DF, V2DF, V2DF /// lsx_vfdiv_s +impl = portable name = lsx_vfdiv_s asm-fmts = vd, vj, vk data-types = V4SF, V4SF, V4SF /// lsx_vfdiv_d +impl = portable name = lsx_vfdiv_d asm-fmts = vd, vj, vk data-types = V2DF, V2DF, V2DF @@ -1704,11 +1936,13 @@ asm-fmts = vd, vj data-types = V2DI, V2DF /// lsx_vfsqrt_s +impl = portable name = lsx_vfsqrt_s asm-fmts = vd, vj data-types = V4SF, V4SF /// lsx_vfsqrt_d +impl = portable name = lsx_vfsqrt_d asm-fmts = vd, vj data-types = V2DF, V2DF @@ -1854,26 +2088,31 @@ asm-fmts = vd, vj data-types = V2DF, UV2DI /// lsx_vandn_v +impl = portable name = lsx_vandn_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI /// lsx_vneg_b +impl = portable name = lsx_vneg_b asm-fmts = vd, vj data-types = V16QI, V16QI /// lsx_vneg_h +impl = portable name = lsx_vneg_h asm-fmts = vd, vj data-types = V8HI, V8HI /// lsx_vneg_w +impl = portable name = lsx_vneg_w asm-fmts = vd, vj data-types = V4SI, V4SI /// lsx_vneg_d +impl = portable name = lsx_vneg_d asm-fmts = vd, vj data-types = V2DI, V2DI @@ -2194,41 +2433,49 @@ asm-fmts = vd, vj, vk data-types = V2DI, V2DI, V2DI /// lsx_vfmadd_s +impl = portable name = lsx_vfmadd_s asm-fmts = vd, vj, vk, va data-types = V4SF, V4SF, V4SF, V4SF /// lsx_vfmadd_d +impl = portable name = lsx_vfmadd_d asm-fmts = vd, vj, vk, va data-types = V2DF, V2DF, V2DF, V2DF /// lsx_vfmsub_s +impl = portable name = lsx_vfmsub_s asm-fmts = vd, vj, vk, va data-types = V4SF, V4SF, V4SF, V4SF /// lsx_vfmsub_d +impl = portable name = lsx_vfmsub_d asm-fmts = vd, vj, vk, va data-types = V2DF, V2DF, V2DF, V2DF /// lsx_vfnmadd_s +impl = portable name = lsx_vfnmadd_s asm-fmts = vd, vj, vk, va data-types = V4SF, V4SF, V4SF, V4SF /// lsx_vfnmadd_d +impl = portable name = lsx_vfnmadd_d asm-fmts = vd, vj, vk, va data-types = V2DF, V2DF, V2DF, V2DF /// lsx_vfnmsub_s +impl = portable name = lsx_vfnmsub_s asm-fmts = vd, vj, vk, va data-types = V4SF, V4SF, V4SF, V4SF /// lsx_vfnmsub_d +impl = portable name = lsx_vfnmsub_d asm-fmts = vd, vj, vk, va data-types = V2DF, V2DF, V2DF, V2DF @@ -3284,6 +3531,7 @@ asm-fmts = vd, vj, vk data-types = V4SI, V2DI, V2DI /// lsx_vorn_v +impl = portable name = lsx_vorn_v asm-fmts = vd, vj, vk data-types = UV16QI, UV16QI, UV16QI @@ -3584,21 +3832,25 @@ asm-fmts = vd, vj, vk data-types = V4SI, V4SF, V4SF /// lsx_vrepli_b +impl = portable name = lsx_vrepli_b asm-fmts = vd, si10 data-types = V16QI, HI /// lsx_vrepli_d +impl = portable name = lsx_vrepli_d asm-fmts = vd, si10 data-types = V2DI, HI /// lsx_vrepli_h +impl = portable name = lsx_vrepli_h asm-fmts = vd, si10 data-types = V8HI, HI /// lsx_vrepli_w +impl = portable name = lsx_vrepli_w asm-fmts = vd, si10 data-types = V4SI, HI diff --git a/stdarch/crates/stdarch-gen-loongarch/src/main.rs b/stdarch/crates/stdarch-gen-loongarch/src/main.rs index 10b87c70e9ede..8c4d4e13ec15a 100644 --- a/stdarch/crates/stdarch-gen-loongarch/src/main.rs +++ b/stdarch/crates/stdarch-gen-loongarch/src/main.rs @@ -1,3 +1,4 @@ +use std::collections::HashSet; use std::env; use std::fmt; use std::fs::File; @@ -90,6 +91,14 @@ impl TargetFeature { } } +fn portable_intrinsics() -> HashSet<&'static str> { + include_str!("portable-intrinsics.txt") + .lines() + .map(str::trim) + .filter(|line| !line.is_empty() && !line.starts_with('#')) + .collect() +} + fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> { let f = File::open(in_file.clone()).unwrap_or_else(|_| panic!("Failed to open {in_file}")); let f = BufReader::new(f); @@ -105,6 +114,7 @@ fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> { let mut asm_fmts = String::new(); let mut data_types = String::new(); let fn_pat = format!("__{ext_name}_"); + let portable_intrinsics = portable_intrinsics(); for line in f.lines() { let line = line.unwrap(); if line.is_empty() { @@ -121,6 +131,9 @@ fn gen_spec(in_file: String, ext_name: &str) -> io::Result<()> { let e = line.find('(').unwrap(); let name = line.get(s + 2..e).unwrap().trim().to_string(); out.push_str(&format!("/// {name}\n")); + if portable_intrinsics.contains(name.as_str()) { + out.push_str("impl = portable\n"); + } out.push_str(&format!("name = {name}\n")); out.push_str(&format!("asm-fmts = {asm_fmts}\n")); out.push_str(&format!("data-types = {data_types}\n")); @@ -146,6 +159,7 @@ fn gen_bind(in_file: String, ext_name: &str) -> io::Result<()> { let mut link_function_str = String::new(); let mut function_str = String::new(); let mut out = String::new(); + let mut skip = false; out.push_str(&format!( r#"// This code is automatically generated. DO NOT MODIFY. @@ -173,7 +187,9 @@ unsafe extern "unadjusted" { if line.is_empty() { continue; } - if let Some(name) = line.strip_prefix("name = ") { + if line.starts_with("impl = portable") { + skip = true; + } else if let Some(name) = line.strip_prefix("name = ") { current_name = Some(String::from(name)); } else if line.starts_with("asm-fmts = ") { asm_fmts = line[10..] @@ -210,6 +226,11 @@ unsafe extern "unadjusted" { panic!("DEBUG: line: {0} len: {1}", line, data_types.len()); } + if skip { + skip = false; + continue; + } + let (link_function, function) = gen_bind_body(¤t_name, &asm_fmts, &in_t, out_t, para_num, target); link_function_str.push_str(&link_function); @@ -571,21 +592,21 @@ fn gen_bind_body( } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "SI" { call_params = match asm_fmts[2].as_str() { "si12" => format!( - "static_assert_simm_bits!(IMM_S12, 12);\n {unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, IMM_S12)){unsafe_end}" + "static_assert_simm_bits!(IMM_S12, 12);\n {unsafe_start}__{current_name}(transmute(a), mem_addr, IMM_S12){unsafe_end}" ), _ => panic!("unsupported assembly format: {}", asm_fmts[2]), }; } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "DI" { call_params = match asm_fmts[2].as_str() { "rk" => format!( - "{unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, transmute(b))){unsafe_end}" + "{unsafe_start}__{current_name}(transmute(a), mem_addr, transmute(b)){unsafe_end}" ), _ => panic!("unsupported assembly format: {}", asm_fmts[2]), }; } else if para_num == 4 { call_params = match (asm_fmts[2].as_str(), current_name.chars().last().unwrap()) { ("si8", t) => format!( - "static_assert_simm_bits!(IMM_S8, 8);\n static_assert_uimm_bits!(IMM{0}, {0});\n {unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, IMM_S8, IMM{0})){unsafe_end}", + "static_assert_simm_bits!(IMM_S8, 8);\n static_assert_uimm_bits!(IMM{0}, {0});\n {unsafe_start}__{current_name}(transmute(a), mem_addr, IMM_S8, IMM{0}){unsafe_end}", type_to_imm(t) ), (_, _) => panic!( @@ -847,6 +868,7 @@ union v4df out.push_str(" printf(\" core_arch::{loongarch64::*, simd::*},\\n\");\n"); out.push_str(" printf(\" mem::transmute,\\n\");\n"); out.push_str(" printf(\"};\\n\");\n"); + out.push_str(" printf(\"use std::hint::black_box;\\n\");\n"); out.push_str(" printf(\"use stdarch_test::simd_test;\\n\");\n"); out.push_str(&call_function_str); out.push_str(" return 0;\n"); @@ -1323,10 +1345,10 @@ fn gen_test_body( _ => "unsupported parameter number".to_string(), }; let mut as_params = match para_num { - 1 => "(transmute(a))".to_string(), - 2 => "(transmute(a), transmute(b))".to_string(), - 3 => "(transmute(a), transmute(b), transmute(c))".to_string(), - 4 => "(transmute(a), transmute(b), transmute(c), transmute(d))".to_string(), + 1 => "(black_box(transmute(a)))".to_string(), + 2 => "(black_box(transmute(a)), black_box(transmute(b)))".to_string(), + 3 => "(black_box(transmute(a)), black_box(transmute(b)), black_box(transmute(c)))".to_string(), + 4 => "(black_box(transmute(a)), black_box(transmute(b)), black_box(transmute(c)), black_box(transmute(d)))".to_string(), _ => panic!("unsupported parameter number"), }; let mut as_args = String::new(); @@ -1356,9 +1378,9 @@ fn gen_test_body( { fn_params = "(a)".to_string(); if in_t[0] == "SI" { - as_params = "(%d)".to_string(); + as_params = "(black_box(%d))".to_string(); } else { - as_params = "(%ld)".to_string(); + as_params = "(black_box(%ld))".to_string(); } as_args = ", a".to_string(); } else if para_num == 2 && (in_t[1] == "UQI" || in_t[1] == "USI") { @@ -1370,7 +1392,7 @@ fn gen_test_body( ); let val = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {val})"); - as_params = format!("::<{val}>(transmute(a))"); + as_params = format!("::<{val}>(black_box(transmute(a)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1383,13 +1405,13 @@ fn gen_test_body( ); let val = rand_i32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {val})"); - as_params = format!("::<{val}>(transmute(a))"); + as_params = format!("::<{val}>(black_box(transmute(a)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } } else if para_num == 2 && in_t[1] == "SI" && asm_fmts[2].starts_with("rk") { fn_params = "(a.v, b)".to_string(); - as_params = "(transmute(a), %d)".to_string(); + as_params = "(black_box(transmute(a)), %d)".to_string(); as_args = ", b".to_string(); } else if para_num == 2 && in_t[0] == "CVPOINTER" && in_t[1] == "SI" { if asm_fmts[2].starts_with("si") { @@ -1441,7 +1463,7 @@ fn gen_test_body( let ival = rand_i32(32); let uval = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {ival}, {uval})"); - as_params = format!("::<{uval}>(transmute(a), {ival})"); + as_params = format!("::<{uval}>(black_box(transmute(a)), {ival})"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1456,7 +1478,7 @@ fn gen_test_body( ); let val = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, b.v, {val})"); - as_params = format!("::<{val}>(transmute(a), transmute(b))"); + as_params = format!("::<{val}>(black_box(transmute(a)), black_box(transmute(b)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1478,7 +1500,7 @@ fn gen_test_body( type_to_ct(in_t[1]) ); fn_params = "(a.v, b, 0)".to_string(); - as_params = "::<0>(transmute(a), o.as_mut_ptr())".to_string(); + as_params = "::<0>(black_box(transmute(a)), o.as_mut_ptr())".to_string(); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1500,7 +1522,7 @@ fn gen_test_body( type_to_ct(in_t[1]) ); fn_params = "(a.v, b, 0)".to_string(); - as_params = "(transmute(a), o.as_mut_ptr(), 0)".to_string(); + as_params = "(black_box(transmute(a)), o.as_mut_ptr(), 0)".to_string(); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1524,7 +1546,7 @@ fn gen_test_body( ); let val = rand_u32(type_to_imm(t).try_into().unwrap()); fn_params = format!("(a.v, b, 0, {val})"); - as_params = format!("::<0, {val}>(transmute(a), o.as_mut_ptr())"); + as_params = format!("::<0, {val}>(black_box(transmute(a)), o.as_mut_ptr())"); } (_, _) => panic!( "unsupported assembly format: {} for {}", diff --git a/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt b/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt new file mode 100644 index 0000000000000..228c9140fc6aa --- /dev/null +++ b/stdarch/crates/stdarch-gen-loongarch/src/portable-intrinsics.txt @@ -0,0 +1,506 @@ +# LSX intrinsics +lsx_vsll_b +lsx_vsll_h +lsx_vsll_w +lsx_vsll_d +lsx_vslli_b +lsx_vslli_h +lsx_vslli_w +lsx_vslli_d +lsx_vsra_b +lsx_vsra_h +lsx_vsra_w +lsx_vsra_d +lsx_vsrai_b +lsx_vsrai_h +lsx_vsrai_w +lsx_vsrai_d +lsx_vsrl_b +lsx_vsrl_h +lsx_vsrl_w +lsx_vsrl_d +lsx_vsrli_b +lsx_vsrli_h +lsx_vsrli_w +lsx_vsrli_d +lsx_vadd_b +lsx_vadd_h +lsx_vadd_w +lsx_vadd_d +lsx_vaddi_bu +lsx_vaddi_hu +lsx_vaddi_wu +lsx_vaddi_du +lsx_vsub_b +lsx_vsub_h +lsx_vsub_w +lsx_vsub_d +lsx_vmax_b +lsx_vmax_h +lsx_vmax_w +lsx_vmax_d +lsx_vmaxi_b +lsx_vmaxi_h +lsx_vmaxi_w +lsx_vmaxi_d +lsx_vmax_bu +lsx_vmax_hu +lsx_vmax_wu +lsx_vmax_du +lsx_vmaxi_bu +lsx_vmaxi_hu +lsx_vmaxi_wu +lsx_vmaxi_du +lsx_vmin_b +lsx_vmin_h +lsx_vmin_w +lsx_vmin_d +lsx_vmini_b +lsx_vmini_h +lsx_vmini_w +lsx_vmini_d +lsx_vmin_bu +lsx_vmin_hu +lsx_vmin_wu +lsx_vmin_du +lsx_vmini_bu +lsx_vmini_hu +lsx_vmini_wu +lsx_vmini_du +lsx_vseq_b +lsx_vseq_h +lsx_vseq_w +lsx_vseq_d +lsx_vseqi_b +lsx_vseqi_h +lsx_vseqi_w +lsx_vseqi_d +lsx_vslt_b +lsx_vslt_h +lsx_vslt_w +lsx_vslt_d +lsx_vslti_b +lsx_vslti_h +lsx_vslti_w +lsx_vslti_d +lsx_vslt_bu +lsx_vslt_hu +lsx_vslt_wu +lsx_vslt_du +lsx_vslti_bu +lsx_vslti_hu +lsx_vslti_wu +lsx_vslti_du +lsx_vsle_b +lsx_vsle_h +lsx_vsle_w +lsx_vsle_d +lsx_vslei_b +lsx_vslei_h +lsx_vslei_w +lsx_vslei_d +lsx_vsle_bu +lsx_vsle_hu +lsx_vsle_wu +lsx_vsle_du +lsx_vslei_bu +lsx_vslei_hu +lsx_vslei_wu +lsx_vslei_du +lsx_vmul_b +lsx_vmul_h +lsx_vmul_w +lsx_vmul_d +lsx_vdiv_b +lsx_vdiv_h +lsx_vdiv_w +lsx_vdiv_d +lsx_vdiv_bu +lsx_vdiv_hu +lsx_vdiv_wu +lsx_vdiv_du +lsx_vmod_b +lsx_vmod_h +lsx_vmod_w +lsx_vmod_d +lsx_vmod_bu +lsx_vmod_hu +lsx_vmod_wu +lsx_vmod_du +lsx_vmadd_b +lsx_vmadd_h +lsx_vmadd_w +lsx_vmadd_d +lsx_vmsub_b +lsx_vmsub_h +lsx_vmsub_w +lsx_vmsub_d +lsx_vand_v +lsx_vor_v +lsx_vnor_v +lsx_vxor_v +lsx_vpcnt_b +lsx_vpcnt_h +lsx_vpcnt_w +lsx_vpcnt_d +lsx_vclz_b +lsx_vclz_h +lsx_vclz_w +lsx_vclz_d +lsx_vreplgr2vr_b +lsx_vreplgr2vr_h +lsx_vreplgr2vr_w +lsx_vreplgr2vr_d +lsx_vpickve2gr_b +lsx_vpickve2gr_h +lsx_vpickve2gr_w +lsx_vpickve2gr_d +lsx_vpickve2gr_bu +lsx_vpickve2gr_hu +lsx_vpickve2gr_wu +lsx_vpickve2gr_du +lsx_vinsgr2vr_b +lsx_vinsgr2vr_h +lsx_vinsgr2vr_w +lsx_vinsgr2vr_d +lsx_vfadd_s +lsx_vfadd_d +lsx_vfsub_s +lsx_vfsub_d +lsx_vfmul_s +lsx_vfmul_d +lsx_vfdiv_s +lsx_vfdiv_d +lsx_vfsqrt_s +lsx_vfsqrt_d +lsx_vandn_v +lsx_vneg_b +lsx_vneg_h +lsx_vneg_w +lsx_vneg_d +lsx_vfmadd_s +lsx_vfmadd_d +lsx_vfmsub_s +lsx_vfmsub_d +lsx_vfnmadd_s +lsx_vfnmadd_d +lsx_vfnmsub_s +lsx_vfnmsub_d +lsx_vorn_v +lsx_vrepli_b +lsx_vrepli_h +lsx_vrepli_w +lsx_vrepli_d +lsx_vbitclr_b +lsx_vbitclr_h +lsx_vbitclr_w +lsx_vbitclr_d +lsx_vbitset_b +lsx_vbitset_h +lsx_vbitset_w +lsx_vbitset_d +lsx_vbitrev_b +lsx_vbitrev_h +lsx_vbitrev_w +lsx_vbitrev_d +lsx_vsadd_b +lsx_vsadd_h +lsx_vsadd_w +lsx_vsadd_d +lsx_vsadd_bu +lsx_vsadd_hu +lsx_vsadd_wu +lsx_vsadd_du +lsx_vssub_b +lsx_vssub_h +lsx_vssub_w +lsx_vssub_d +lsx_vssub_bu +lsx_vssub_hu +lsx_vssub_wu +lsx_vssub_du +lsx_vadda_b +lsx_vadda_h +lsx_vadda_w +lsx_vadda_d +lsx_vabsd_b +lsx_vabsd_h +lsx_vabsd_w +lsx_vabsd_d +lsx_vabsd_bu +lsx_vabsd_hu +lsx_vabsd_wu +lsx_vabsd_du +lsx_vpickev_b +lsx_vpickev_h +lsx_vpickev_w +lsx_vpickev_d +lsx_vpickod_b +lsx_vpickod_h +lsx_vpickod_w +lsx_vpickod_d +lsx_vilvh_b +lsx_vilvh_h +lsx_vilvh_w +lsx_vilvh_d +lsx_vilvl_b +lsx_vilvl_h +lsx_vilvl_w +lsx_vilvl_d +lsx_vreplvei_b +lsx_vreplvei_h +lsx_vreplvei_w +lsx_vreplvei_d + +# LASX intrinsics +lasx_xvsll_b +lasx_xvsll_h +lasx_xvsll_w +lasx_xvsll_d +lasx_xvslli_b +lasx_xvslli_h +lasx_xvslli_w +lasx_xvslli_d +lasx_xvsra_b +lasx_xvsra_h +lasx_xvsra_w +lasx_xvsra_d +lasx_xvsrai_b +lasx_xvsrai_h +lasx_xvsrai_w +lasx_xvsrai_d +lasx_xvsrl_b +lasx_xvsrl_h +lasx_xvsrl_w +lasx_xvsrl_d +lasx_xvsrli_b +lasx_xvsrli_h +lasx_xvsrli_w +lasx_xvsrli_d +lasx_xvadd_b +lasx_xvadd_h +lasx_xvadd_w +lasx_xvadd_d +lasx_xvaddi_bu +lasx_xvaddi_hu +lasx_xvaddi_wu +lasx_xvaddi_du +lasx_xvsub_b +lasx_xvsub_h +lasx_xvsub_w +lasx_xvsub_d +lasx_xvmax_b +lasx_xvmax_h +lasx_xvmax_w +lasx_xvmax_d +lasx_xvmaxi_b +lasx_xvmaxi_h +lasx_xvmaxi_w +lasx_xvmaxi_d +lasx_xvmax_bu +lasx_xvmax_hu +lasx_xvmax_wu +lasx_xvmax_du +lasx_xvmaxi_bu +lasx_xvmaxi_hu +lasx_xvmaxi_wu +lasx_xvmaxi_du +lasx_xvmin_b +lasx_xvmin_h +lasx_xvmin_w +lasx_xvmin_d +lasx_xvmini_b +lasx_xvmini_h +lasx_xvmini_w +lasx_xvmini_d +lasx_xvmin_bu +lasx_xvmin_hu +lasx_xvmin_wu +lasx_xvmin_du +lasx_xvmini_bu +lasx_xvmini_hu +lasx_xvmini_wu +lasx_xvmini_du +lasx_xvseq_b +lasx_xvseq_h +lasx_xvseq_w +lasx_xvseq_d +lasx_xvseqi_b +lasx_xvseqi_h +lasx_xvseqi_w +lasx_xvseqi_d +lasx_xvslt_b +lasx_xvslt_h +lasx_xvslt_w +lasx_xvslt_d +lasx_xvslti_b +lasx_xvslti_h +lasx_xvslti_w +lasx_xvslti_d +lasx_xvslt_bu +lasx_xvslt_hu +lasx_xvslt_wu +lasx_xvslt_du +lasx_xvslti_bu +lasx_xvslti_hu +lasx_xvslti_wu +lasx_xvslti_du +lasx_xvsle_b +lasx_xvsle_h +lasx_xvsle_w +lasx_xvsle_d +lasx_xvslei_b +lasx_xvslei_h +lasx_xvslei_w +lasx_xvslei_d +lasx_xvsle_bu +lasx_xvsle_hu +lasx_xvsle_wu +lasx_xvsle_du +lasx_xvslei_bu +lasx_xvslei_hu +lasx_xvslei_wu +lasx_xvslei_du +lasx_xvmul_b +lasx_xvmul_h +lasx_xvmul_w +lasx_xvmul_d +lasx_xvdiv_b +lasx_xvdiv_h +lasx_xvdiv_w +lasx_xvdiv_d +lasx_xvdiv_bu +lasx_xvdiv_hu +lasx_xvdiv_wu +lasx_xvdiv_du +lasx_xvmod_b +lasx_xvmod_h +lasx_xvmod_w +lasx_xvmod_d +lasx_xvmod_bu +lasx_xvmod_hu +lasx_xvmod_wu +lasx_xvmod_du +lasx_xvmadd_b +lasx_xvmadd_h +lasx_xvmadd_w +lasx_xvmadd_d +lasx_xvmsub_b +lasx_xvmsub_h +lasx_xvmsub_w +lasx_xvmsub_d +lasx_xvand_v +lasx_xvor_v +lasx_xvnor_v +lasx_xvxor_v +lasx_xvpcnt_b +lasx_xvpcnt_h +lasx_xvpcnt_w +lasx_xvpcnt_d +lasx_xvclz_b +lasx_xvclz_h +lasx_xvclz_w +lasx_xvclz_d +lasx_xvreplgr2vr_b +lasx_xvreplgr2vr_h +lasx_xvreplgr2vr_w +lasx_xvreplgr2vr_d +lasx_xvpickve2gr_w +lasx_xvpickve2gr_d +lasx_xvpickve2gr_wu +lasx_xvpickve2gr_du +lasx_xvinsgr2vr_w +lasx_xvinsgr2vr_d +lasx_xvfadd_s +lasx_xvfadd_d +lasx_xvfsub_s +lasx_xvfsub_d +lasx_xvfmul_s +lasx_xvfmul_d +lasx_xvfdiv_s +lasx_xvfdiv_d +lasx_xvfsqrt_s +lasx_xvfsqrt_d +lasx_xvandn_v +lasx_xvneg_b +lasx_xvneg_h +lasx_xvneg_w +lasx_xvneg_d +lasx_xvfmadd_s +lasx_xvfmadd_d +lasx_xvfmsub_s +lasx_xvfmsub_d +lasx_xvfnmadd_s +lasx_xvfnmadd_d +lasx_xvfnmsub_s +lasx_xvfnmsub_d +lasx_xvorn_v +lasx_xvrepli_b +lasx_xvrepli_h +lasx_xvrepli_w +lasx_xvrepli_d +lasx_xvbitclr_b +lasx_xvbitclr_h +lasx_xvbitclr_w +lasx_xvbitclr_d +lasx_xvbitset_b +lasx_xvbitset_h +lasx_xvbitset_w +lasx_xvbitset_d +lasx_xvbitrev_b +lasx_xvbitrev_h +lasx_xvbitrev_w +lasx_xvbitrev_d +lasx_xvsadd_b +lasx_xvsadd_h +lasx_xvsadd_w +lasx_xvsadd_d +lasx_xvsadd_bu +lasx_xvsadd_hu +lasx_xvsadd_wu +lasx_xvsadd_du +lasx_xvssub_b +lasx_xvssub_h +lasx_xvssub_w +lasx_xvssub_d +lasx_xvssub_bu +lasx_xvssub_hu +lasx_xvssub_wu +lasx_xvssub_du +lasx_xvadda_b +lasx_xvadda_h +lasx_xvadda_w +lasx_xvadda_d +lasx_xvabsd_b +lasx_xvabsd_h +lasx_xvabsd_w +lasx_xvabsd_d +lasx_xvabsd_bu +lasx_xvabsd_hu +lasx_xvabsd_wu +lasx_xvabsd_du +lasx_xvpickev_b +lasx_xvpickev_h +lasx_xvpickev_w +lasx_xvpickev_d +lasx_xvpickod_b +lasx_xvpickod_h +lasx_xvpickod_w +lasx_xvpickod_d +lasx_xvilvh_b +lasx_xvilvh_h +lasx_xvilvh_w +lasx_xvilvh_d +lasx_xvilvl_b +lasx_xvilvl_h +lasx_xvilvl_w +lasx_xvilvl_d +lasx_xvrepl128vei_b +lasx_xvrepl128vei_h +lasx_xvrepl128vei_w +lasx_xvrepl128vei_d +lasx_xvreplve0_b +lasx_xvreplve0_h +lasx_xvreplve0_w +lasx_xvreplve0_d +lasx_xvreplve0_q diff --git a/stdarch/crates/stdarch-test/src/disassembly.rs b/stdarch/crates/stdarch-test/src/disassembly.rs index 237e8d2dc28a0..7cf657baa0d71 100644 --- a/stdarch/crates/stdarch-test/src/disassembly.rs +++ b/stdarch/crates/stdarch-test/src/disassembly.rs @@ -158,16 +158,26 @@ fn parse(output: &str) -> HashSet { }; if cfg!(any(target_arch = "aarch64", target_arch = "arm64ec")) { - // Normalize [us]shll.* ..., #0 instructions to the preferred form: [us]xtl.* ... - // as neither LLVM objdump nor dumpbin does that. - // See https://developer.arm.com/documentation/ddi0602/latest/SIMD-FP-Instructions/UXTL--UXTL2--Unsigned-extend-Long--an-alias-of-USHLL--USHLL2- - // and https://developer.arm.com/documentation/ddi0602/latest/SIMD-FP-Instructions/SXTL--SXTL2--Signed-extend-Long--an-alias-of-SSHLL--SSHLL2- - // for details. + // Normalize `[us]shll{2}.* ..., #0` instructions to the preferred + // form: `[us]xtl{2}.* ...` as neither LLVM objdump nor dumpbin does that. + // + // SVE has `[us]shll[tb]` instructions that don't have an equivalent alias. + // + // See Arm documentation for details: + // + // - https://developer.arm.com/documentation/ddi0602/2026-03/SIMD-FP-Instructions/UXTL--UXTL2--Unsigned-extend-long--an-alias-of-USHLL--USHLL2-?lang=en + // - https://developer.arm.com/documentation/ddi0602/2026-03/SIMD-FP-Instructions/SXTL--SXTL2--Signed-extend-long--an-alias-of-SSHLL--SSHLL2-?lang=en fn is_shll(instr: &str) -> bool { if cfg!(target_env = "msvc") { - instr.starts_with("ushll") || instr.starts_with("sshll") + instr == "ushll" + || instr == "ushll2" + || instr == "sshll" + || instr == "sshll2" } else { - instr.starts_with("ushll.") || instr.starts_with("sshll.") + instr == "ushll." + || instr == "ushll2." + || instr == "sshll." + || instr == "sshll2." } } match (parts.first(), parts.last()) { diff --git a/stdarch/crates/stdarch-verify/src/lib.rs b/stdarch/crates/stdarch-verify/src/lib.rs index c81f5f45bcce4..f7304ab326858 100644 --- a/stdarch/crates/stdarch-verify/src/lib.rs +++ b/stdarch/crates/stdarch-verify/src/lib.rs @@ -120,6 +120,13 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { ); } + // Newer intrinsics don't have `rustc_legacy_const_generics` - assume they belong at + // the end of the argument list + if required_const.is_empty() && legacy_const_generics.is_empty() { + legacy_const_generics = + (arguments.len()..(arguments.len() + const_arguments.len())).collect(); + } + // The list of required consts, used to verify the arguments, comes from either the // `rustc_args_required_const` or the `rustc_legacy_const_generics` attribute. let required_const = if required_const.is_empty() { @@ -136,14 +143,14 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { arguments.insert(idx, ty); } - // strip leading underscore from fn name when building a test - // _mm_foo -> mm_foo such that the test name is test_mm_foo. - let test_name_string = format!("{name}"); - let mut test_name_id = test_name_string.as_str(); - while test_name_id.starts_with('_') { - test_name_id = &test_name_id[1..]; - } - let has_test = tests.contains(&format!("test_{test_name_id}")); + // Strip leading underscore from fn name when building a test + // `_mm_foo` -> `mm_foo` such that the test name is `test_mm_foo`. + let test_name = name.to_string(); + let test_name = test_name.trim_start_matches('_'); + let has_test = tests.contains(&format!("test_{test_name}")) + // SVE load/store tests start with `test` or `_with_` + || tests.iter().any(|t| t.starts_with(&format!("test_{test_name}")) + || t.ends_with(&format!("_with_{test_name}"))); let doc = find_doc(&f.attrs); @@ -347,6 +354,50 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream { "v4f32" => quote! { &v4f32 }, "v2f64" => quote! { &v2f64 }, + "svbool_t" => quote! { &SVBOOL }, + "svint8_t" => quote! { &SVI8 }, + "svint8x2_t" => quote! { &SVI8X2 }, + "svint8x3_t" => quote! { &SVI8X3 }, + "svint8x4_t" => quote! { &SVI8X4 }, + "svint16_t" => quote! { &SVI16 }, + "svint16x2_t" => quote! { &SVI16X2 }, + "svint16x3_t" => quote! { &SVI16X3 }, + "svint16x4_t" => quote! { &SVI16X4 }, + "svint32_t" => quote! { &SVI32 }, + "svint32x2_t" => quote! { &SVI32X2 }, + "svint32x3_t" => quote! { &SVI32X3 }, + "svint32x4_t" => quote! { &SVI32X4 }, + "svint64_t" => quote! { &SVI64 }, + "svint64x2_t" => quote! { &SVI64X2 }, + "svint64x3_t" => quote! { &SVI64X3 }, + "svint64x4_t" => quote! { &SVI64X4 }, + "svuint8_t" => quote! { &SVU8 }, + "svuint8x2_t" => quote! { &SVU8X2 }, + "svuint8x3_t" => quote! { &SVU8X3 }, + "svuint8x4_t" => quote! { &SVU8X4 }, + "svuint16_t" => quote! { &SVU16 }, + "svuint16x2_t" => quote! { &SVU16X2 }, + "svuint16x3_t" => quote! { &SVU16X3 }, + "svuint16x4_t" => quote! { &SVU16X4 }, + "svuint32_t" => quote! { &SVU32 }, + "svuint32x2_t" => quote! { &SVU32X2 }, + "svuint32x3_t" => quote! { &SVU32X3 }, + "svuint32x4_t" => quote! { &SVU32X4 }, + "svuint64_t" => quote! { &SVU64 }, + "svuint64x2_t" => quote! { &SVU64X2 }, + "svuint64x3_t" => quote! { &SVU64X3 }, + "svuint64x4_t" => quote! { &SVU64X4 }, + "svfloat32_t" => quote! { &SVF32 }, + "svfloat32x2_t" => quote! { &SVF32X2 }, + "svfloat32x3_t" => quote! { &SVF32X3 }, + "svfloat32x4_t" => quote! { &SVF32X4 }, + "svfloat64_t" => quote! { &SVF64 }, + "svfloat64x2_t" => quote! { &SVF64X2 }, + "svfloat64x3_t" => quote! { &SVF64X3 }, + "svfloat64x4_t" => quote! { &SVF64X4 }, + "svprfop" => quote! { &SVPRFOP }, + "svpattern" => quote! { &SVPATTERN }, + // Generic types "T" => quote! { &GENERICT }, "U" => quote! { &GENERICU }, diff --git a/stdarch/crates/stdarch-verify/tests/arm.rs b/stdarch/crates/stdarch-verify/tests/arm.rs index 3ef9ce2a38b69..6ba9c17c4804c 100644 --- a/stdarch/crates/stdarch-verify/tests/arm.rs +++ b/stdarch/crates/stdarch-verify/tests/arm.rs @@ -16,6 +16,7 @@ struct Function { doc: &'static str, } +static BOOL: Type = Type::PrimBool; static F16: Type = Type::PrimFloat(16); static F32: Type = Type::PrimFloat(32); static F64: Type = Type::PrimFloat(64); @@ -28,6 +29,7 @@ static U32: Type = Type::PrimUnsigned(32); static U64: Type = Type::PrimUnsigned(64); static U8: Type = Type::PrimUnsigned(8); static NEVER: Type = Type::Never; +static VOID: Type = Type::Void; static GENERICT: Type = Type::GenericParam("T"); static GENERICU: Type = Type::GenericParam("U"); @@ -151,19 +153,78 @@ static U8X8X2: Type = Type::U(8, 8, 2); static U8X8X3: Type = Type::U(8, 8, 3); static U8X8X4: Type = Type::U(8, 8, 4); +static SVBOOL: Type = Type::Pred(1); +static SVBOOLX2: Type = Type::Pred(2); +static SVBOOLX3: Type = Type::Pred(3); +static SVBOOLX4: Type = Type::Pred(4); +static SVCOUNT: Type = Type::Pred(1); +static SVF16: Type = Type::SVF(16, 1); +static SVF16X2: Type = Type::SVF(16, 2); +static SVF16X3: Type = Type::SVF(16, 3); +static SVF16X4: Type = Type::SVF(16, 4); +static SVF32: Type = Type::SVF(32, 1); +static SVF32X2: Type = Type::SVF(32, 2); +static SVF32X3: Type = Type::SVF(32, 3); +static SVF32X4: Type = Type::SVF(32, 4); +static SVF64: Type = Type::SVF(64, 1); +static SVF64X2: Type = Type::SVF(64, 2); +static SVF64X3: Type = Type::SVF(64, 3); +static SVF64X4: Type = Type::SVF(64, 4); +static SVI8: Type = Type::SVI(8, 1); +static SVI8X2: Type = Type::SVI(8, 2); +static SVI8X3: Type = Type::SVI(8, 3); +static SVI8X4: Type = Type::SVI(8, 4); +static SVI16: Type = Type::SVI(16, 1); +static SVI16X2: Type = Type::SVI(16, 2); +static SVI16X3: Type = Type::SVI(16, 3); +static SVI16X4: Type = Type::SVI(16, 4); +static SVI32: Type = Type::SVI(32, 1); +static SVI32X2: Type = Type::SVI(32, 2); +static SVI32X3: Type = Type::SVI(32, 3); +static SVI32X4: Type = Type::SVI(32, 4); +static SVI64: Type = Type::SVI(64, 1); +static SVI64X2: Type = Type::SVI(64, 2); +static SVI64X3: Type = Type::SVI(64, 3); +static SVI64X4: Type = Type::SVI(64, 4); +static SVU8: Type = Type::SVU(8, 1); +static SVU8X2: Type = Type::SVU(8, 2); +static SVU8X3: Type = Type::SVU(8, 3); +static SVU8X4: Type = Type::SVU(8, 4); +static SVU16: Type = Type::SVU(16, 1); +static SVU16X2: Type = Type::SVU(16, 2); +static SVU16X3: Type = Type::SVU(16, 3); +static SVU16X4: Type = Type::SVU(16, 4); +static SVU32: Type = Type::SVU(32, 1); +static SVU32X2: Type = Type::SVU(32, 2); +static SVU32X3: Type = Type::SVU(32, 3); +static SVU32X4: Type = Type::SVU(32, 4); +static SVU64: Type = Type::SVU(64, 1); +static SVU64X2: Type = Type::SVU(64, 2); +static SVU64X3: Type = Type::SVU(64, 3); +static SVU64X4: Type = Type::SVU(64, 4); +static SVPRFOP: Type = Type::Enum("svprfop"); +static SVPATTERN: Type = Type::Enum("svpattern"); + #[derive(Debug, Copy, Clone, PartialEq)] enum Type { + Void, + PrimBool, PrimFloat(u8), PrimSigned(u8), PrimUnsigned(u8), PrimPoly(u8), MutPtr(&'static Type), ConstPtr(&'static Type), + Enum(&'static str), GenericParam(&'static str), I(u8, u8, u8), U(u8, u8, u8), P(u8, u8, u8), F(u8, u8, u8), + Pred(u8), + SVI(u8, u8), + SVU(u8, u8), + SVF(u8, u8), Never, } @@ -182,231 +243,20 @@ fn verify_all_signatures() { let mut all_valid = true; for rust in FUNCTIONS { + // Most SVE intrinsics just rely on the intrinsics test tool for validation if !rust.has_test { - let skip = [ - "vaddq_s64", - "vaddq_u64", - "vrsqrte_f32", - "vtbl1_s8", - "vtbl1_u8", - "vtbl1_p8", - "vtbl2_s8", - "vtbl2_u8", - "vtbl2_p8", - "vtbl3_s8", - "vtbl3_u8", - "vtbl3_p8", - "vtbl4_s8", - "vtbl4_u8", - "vtbl4_p8", - "vtbx1_s8", - "vtbx1_u8", - "vtbx1_p8", - "vtbx2_s8", - "vtbx2_u8", - "vtbx2_p8", - "vtbx3_s8", - "vtbx3_u8", - "vtbx3_p8", - "vtbx4_s8", - "vtbx4_u8", - "vtbx4_p8", - "udf", - "_clz_u8", - "_clz_u16", - "_clz_u32", - "_rbit_u32", - "_rev_u16", - "_rev_u32", - "__breakpoint", - "vpminq_f32", - "vpminq_f64", - "vpmaxq_f32", - "vpmaxq_f64", - "vcombine_s8", - "vcombine_s16", - "vcombine_s32", - "vcombine_s64", - "vcombine_u8", - "vcombine_u16", - "vcombine_u32", - "vcombine_u64", - "vcombine_p64", - "vcombine_f32", - "vcombine_p8", - "vcombine_p16", - "vcombine_f64", - "vtbl1_s8", - "vtbl1_u8", - "vtbl1_p8", - "vtbl2_s8", - "vtbl2_u8", - "vtbl2_p8", - "vtbl3_s8", - "vtbl3_u8", - "vtbl3_p8", - "vtbl4_s8", - "vtbl4_u8", - "vtbl4_p8", - "vtbx1_s8", - "vtbx1_u8", - "vtbx1_p8", - "vtbx2_s8", - "vtbx2_u8", - "vtbx2_p8", - "vtbx3_s8", - "vtbx3_u8", - "vtbx3_p8", - "vtbx4_s8", - "vtbx4_u8", - "vtbx4_p8", - "vqtbl1_s8", - "vqtbl1q_s8", - "vqtbl1_u8", - "vqtbl1q_u8", - "vqtbl1_p8", - "vqtbl1q_p8", - "vqtbx1_s8", - "vqtbx1q_s8", - "vqtbx1_u8", - "vqtbx1q_u8", - "vqtbx1_p8", - "vqtbx1q_p8", - "vqtbl2_s8", - "vqtbl2q_s8", - "vqtbl2_u8", - "vqtbl2q_u8", - "vqtbl2_p8", - "vqtbl2q_p8", - "vqtbx2_s8", - "vqtbx2q_s8", - "vqtbx2_u8", - "vqtbx2q_u8", - "vqtbx2_p8", - "vqtbx2q_p8", - "vqtbl3_s8", - "vqtbl3q_s8", - "vqtbl3_u8", - "vqtbl3q_u8", - "vqtbl3_p8", - "vqtbl3q_p8", - "vqtbx3_s8", - "vqtbx3q_s8", - "vqtbx3_u8", - "vqtbx3q_u8", - "vqtbx3_p8", - "vqtbx3q_p8", - "vqtbl4_s8", - "vqtbl4q_s8", - "vqtbl4_u8", - "vqtbl4q_u8", - "vqtbl4_p8", - "vqtbl4q_p8", - "vqtbx4_s8", - "vqtbx4q_s8", - "vqtbx4_u8", - "vqtbx4q_u8", - "vqtbx4_p8", - "vqtbx4q_p8", - "brk", - "_rev_u64", - "_clz_u64", - "_rbit_u64", - "_cls_u32", - "_cls_u64", - "_prefetch", - "vsli_n_s8", - "vsliq_n_s8", - "vsli_n_s16", - "vsliq_n_s16", - "vsli_n_s32", - "vsliq_n_s32", - "vsli_n_s64", - "vsliq_n_s64", - "vsli_n_u8", - "vsliq_n_u8", - "vsli_n_u16", - "vsliq_n_u16", - "vsli_n_u32", - "vsliq_n_u32", - "vsli_n_u64", - "vsliq_n_u64", - "vsli_n_p8", - "vsliq_n_p8", - "vsli_n_p16", - "vsliq_n_p16", - "vsli_n_p64", - "vsliq_n_p64", - "vsri_n_s8", - "vsriq_n_s8", - "vsri_n_s16", - "vsriq_n_s16", - "vsri_n_s32", - "vsriq_n_s32", - "vsri_n_s64", - "vsriq_n_s64", - "vsri_n_u8", - "vsriq_n_u8", - "vsri_n_u16", - "vsriq_n_u16", - "vsri_n_u32", - "vsriq_n_u32", - "vsri_n_u64", - "vsriq_n_u64", - "vsri_n_p8", - "vsriq_n_p8", - "vsri_n_p16", - "vsriq_n_p16", - "vsri_n_p64", - "vsriq_n_p64", - "__smulbb", - "__smultb", - "__smulbt", - "__smultt", - "__smulwb", - "__smulwt", - "__qadd", - "__qsub", - "__qdbl", - "__smlabb", - "__smlabt", - "__smlatb", - "__smlatt", - "__smlawb", - "__smlawt", - "__qadd8", - "__qsub8", - "__qsub16", - "__qadd16", - "__qasx", - "__qsax", - "__sadd16", - "__sadd8", - "__smlad", - "__smlsd", - "__sasx", - "__sel", - "__shadd8", - "__shadd16", - "__shsub8", - "__usub8", - "__ssub8", - "__shsub16", - "__smuad", - "__smuadx", - "__smusd", - "__smusdx", - "__usad8", - "__usada8", - "__ldrex", - "__strex", - "__ldrexb", - "__strexb", - "__ldrexh", - "__strexh", - "__clrex", - "__dbg", - ]; + if !SKIP_RUNTIME_TESTS.contains(&rust.name) + // Most run-time tests are handled by the intrinsic-test tool, except for + // load/stores (which have generated tests) + && (!rust.name.starts_with("sv") || rust.name.starts_with("svld") + || rust.name.starts_with("svst")) + // The load/store test generator can't handle these cases yet + && (!rust.name.contains("_u32base_") || rust.name.contains("index") || rust.name.contains("offset")) + && !(rust.name.starts_with("svldff1") && rust.name.contains("gather")) + { + println!("missing run-time test for `{}`", rust.name); + all_valid = false; + } } // Skip some intrinsics that aren't NEON and are located in different @@ -479,12 +329,21 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { let mut nconst = 0; let iter = rust.arguments.iter().zip(&arm.arguments).enumerate(); for (i, (rust_ty, (arm, arm_const))) in iter { - if *rust_ty != arm { - bail!("mismatched arguments: {rust_ty:?} != {arm:?}") + match (*rust_ty, arm) { + // SVE uses generic type parameters to handle void pointers + (Type::ConstPtr(Type::GenericParam("T")), Type::ConstPtr(Type::Void)) => (), + // SVE const generics use i32 over u64 for usability reasons + (Type::PrimSigned(32), Type::PrimUnsigned(64)) if rust.required_const.contains(&i) => { + () + } + // svset doesn't have its const argument last as we assumed when building the Function + _ if rust.name.starts_with("svset") => (), + (x, y) if x == y => (), + _ => bail!("mismatched arguments: {rust_ty:?} != {arm:?}"), } if *arm_const { nconst += 1; - if !rust.required_const.contains(&i) { + if !rust.required_const.contains(&i) && !rust.name.starts_with("svset") { bail!("argument const mismatch"); } } @@ -493,7 +352,10 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { bail!("wrong number of const arguments"); } - if rust.instrs.is_empty() { + if rust.instrs.is_empty() + && arm.instruction != "" + && !SKIP_ASSERT_INSTR_TESTS.contains(&rust.name) + { bail!( "instruction not listed for `{}`, but arm lists {:?}", rust.name, @@ -532,7 +394,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { Ok(()) } -#[derive(PartialEq)] +#[derive(Debug, PartialEq)] struct Intrinsic { name: String, ret: Option, @@ -547,7 +409,7 @@ struct JsonIntrinsic { arguments: Vec, return_type: ReturnType, #[serde(default)] - instructions: Vec>, + instructions: Option>>, } #[derive(Deserialize, Debug)] @@ -566,6 +428,8 @@ fn parse_intrinsics(intrinsics: Vec) -> HashMap Intrinsic { let name = intr.name; + // Remove '[' and ']' so that intrinsics of the form `svwhilerw[_s16]` becomes `svwhilerw_s16`. + let name = name.replace('[', "").replace(']', ""); let ret = if intr.return_type.value == "void" { None } else { @@ -574,18 +438,24 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { // This ignores multiple instructions and different optional sequences for now to mimic // the old HTML scraping behaviour - let instruction = intr.instructions.swap_remove(0).swap_remove(0); + let instruction = intr + .instructions + .map_or(String::new(), |mut i| i.swap_remove(0).swap_remove(0)); let arguments = intr .arguments .iter() .map(|s| { - let (ty, konst) = match s.strip_prefix("const") { - Some(stripped) => (stripped.trim_start(), true), - None => (s.as_str(), false), + let ty = if let Some(i) = s.find('*') { + &s[..i + 1] + } else { + s.rsplit_once(' ').unwrap().0.trim_start_matches("const ") }; - let ty = ty.rsplit_once(' ').unwrap().0; - (parse_ty(ty), konst) + let ty = parse_ty(ty); + let konst = s.contains("const") && !matches!(ty, Type::ConstPtr(_)) + || s.starts_with("enum") + || s.rsplit_once(" ").unwrap().1.starts_with("imm"); + (ty, konst) }) .collect::>(); @@ -598,18 +468,27 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { } fn parse_ty(s: &str) -> Type { - let suffix = " const *"; - if let Some(base) = s.strip_suffix(suffix) { - Type::ConstPtr(parse_ty_base(base)) - } else if let Some(base) = s.strip_suffix(" *") { - Type::MutPtr(parse_ty_base(base)) + if let Some(ty) = s.strip_suffix("*") { + let ty = ty.trim(); + if let Some(ty) = ty.strip_prefix("const") { + // SVE intrinsics are west-const (`const int8_t *`) + Type::ConstPtr(parse_ty_base(ty)) + } else if let Some(ty) = ty.strip_suffix("const") { + // Neon intrinsics are east-const (`int8_t const *`) + Type::ConstPtr(parse_ty_base(ty)) + } else { + Type::MutPtr(parse_ty_base(ty)) + } } else { *parse_ty_base(s) } } fn parse_ty_base(s: &str) -> &'static Type { + let s = s.trim(); match s { + "bool" => &BOOL, + "void" => &VOID, "float16_t" => &F16, "float16x4_t" => &F16X4, "float16x4x2_t" => &F16X4X2, @@ -739,7 +618,4655 @@ fn parse_ty_base(s: &str) -> &'static Type { "uint8x8x2_t" => &U8X8X2, "uint8x8x3_t" => &U8X8X3, "uint8x8x4_t" => &U8X8X4, + "svbool_t" => &SVBOOL, + "svboolx2_t" => &SVBOOLX2, + "svboolx3_t" => &SVBOOLX3, + "svboolx4_t" => &SVBOOLX4, + "svcount_t" => &SVCOUNT, + "svfloat16_t" => &SVF16, + "svfloat16x2_t" => &SVF16X2, + "svfloat16x3_t" => &SVF16X3, + "svfloat16x4_t" => &SVF16X4, + "svfloat32_t" => &SVF32, + "svfloat32x2_t" => &SVF32X2, + "svfloat32x3_t" => &SVF32X3, + "svfloat32x4_t" => &SVF32X4, + "svfloat64_t" => &SVF64, + "svfloat64x2_t" => &SVF64X2, + "svfloat64x3_t" => &SVF64X3, + "svfloat64x4_t" => &SVF64X4, + "svint8_t" => &SVI8, + "svint8x2_t" => &SVI8X2, + "svint8x3_t" => &SVI8X3, + "svint8x4_t" => &SVI8X4, + "svint16_t" => &SVI16, + "svint16x2_t" => &SVI16X2, + "svint16x3_t" => &SVI16X3, + "svint16x4_t" => &SVI16X4, + "svint32_t" => &SVI32, + "svint32x2_t" => &SVI32X2, + "svint32x3_t" => &SVI32X3, + "svint32x4_t" => &SVI32X4, + "svint64_t" => &SVI64, + "svint64x2_t" => &SVI64X2, + "svint64x3_t" => &SVI64X3, + "svint64x4_t" => &SVI64X4, + "svuint8_t" => &SVU8, + "svuint8x2_t" => &SVU8X2, + "svuint8x3_t" => &SVU8X3, + "svuint8x4_t" => &SVU8X4, + "svuint16_t" => &SVU16, + "svuint16x2_t" => &SVU16X2, + "svuint16x3_t" => &SVU16X3, + "svuint16x4_t" => &SVU16X4, + "svuint32_t" => &SVU32, + "svuint32x2_t" => &SVU32X2, + "svuint32x3_t" => &SVU32X3, + "svuint32x4_t" => &SVU32X4, + "svuint64_t" => &SVU64, + "svuint64x2_t" => &SVU64X2, + "svuint64x3_t" => &SVU64X3, + "svuint64x4_t" => &SVU64X4, + "enum svprfop" => &SVPRFOP, + "enum svpattern" => &SVPATTERN, _ => panic!("failed to parse json type {s:?}"), } } + +// FIXME(arm-maintainers): Some tests require new rustc intrinsics in order to generate +// the appropriate instruction, though they do have the correct behaviour - these will be fixed +// but are disabled for now. +static SKIP_ASSERT_INSTR_TESTS: &'static [&'static str] = &["svpfalse_b"]; + +// FIXME(arm-maintainers): With the advent of the `intrinsic-test` tool, new tests of this kind +// are no longer being added and just adding to this list indefinitely isn't the best solution for +// dealing with that. +static SKIP_RUNTIME_TESTS: &'static [&'static str] = &[ + "vaddq_s64", + "vaddq_u64", + "vrsqrte_f32", + "vtbl1_s8", + "vtbl1_u8", + "vtbl1_p8", + "vtbl2_s8", + "vtbl2_u8", + "vtbl2_p8", + "vtbl3_s8", + "vtbl3_u8", + "vtbl3_p8", + "vtbl4_s8", + "vtbl4_u8", + "vtbl4_p8", + "vtbx1_s8", + "vtbx1_u8", + "vtbx1_p8", + "vtbx2_s8", + "vtbx2_u8", + "vtbx2_p8", + "vtbx3_s8", + "vtbx3_u8", + "vtbx3_p8", + "vtbx4_s8", + "vtbx4_u8", + "vtbx4_p8", + "udf", + "_clz_u8", + "_clz_u16", + "_clz_u32", + "_rbit_u32", + "_rev_u16", + "_rev_u32", + "__breakpoint", + "vpminq_f32", + "vpminq_f64", + "vpmaxq_f32", + "vpmaxq_f64", + "vcombine_s8", + "vcombine_s16", + "vcombine_s32", + "vcombine_s64", + "vcombine_u8", + "vcombine_u16", + "vcombine_u32", + "vcombine_u64", + "vcombine_p64", + "vcombine_f32", + "vcombine_p8", + "vcombine_p16", + "vcombine_f64", + "vtbl1_s8", + "vtbl1_u8", + "vtbl1_p8", + "vtbl2_s8", + "vtbl2_u8", + "vtbl2_p8", + "vtbl3_s8", + "vtbl3_u8", + "vtbl3_p8", + "vtbl4_s8", + "vtbl4_u8", + "vtbl4_p8", + "vtbx1_s8", + "vtbx1_u8", + "vtbx1_p8", + "vtbx2_s8", + "vtbx2_u8", + "vtbx2_p8", + "vtbx3_s8", + "vtbx3_u8", + "vtbx3_p8", + "vtbx4_s8", + "vtbx4_u8", + "vtbx4_p8", + "vqtbl1_s8", + "vqtbl1q_s8", + "vqtbl1_u8", + "vqtbl1q_u8", + "vqtbl1_p8", + "vqtbl1q_p8", + "vqtbx1_s8", + "vqtbx1q_s8", + "vqtbx1_u8", + "vqtbx1q_u8", + "vqtbx1_p8", + "vqtbx1q_p8", + "vqtbl2_s8", + "vqtbl2q_s8", + "vqtbl2_u8", + "vqtbl2q_u8", + "vqtbl2_p8", + "vqtbl2q_p8", + "vqtbx2_s8", + "vqtbx2q_s8", + "vqtbx2_u8", + "vqtbx2q_u8", + "vqtbx2_p8", + "vqtbx2q_p8", + "vqtbl3_s8", + "vqtbl3q_s8", + "vqtbl3_u8", + "vqtbl3q_u8", + "vqtbl3_p8", + "vqtbl3q_p8", + "vqtbx3_s8", + "vqtbx3q_s8", + "vqtbx3_u8", + "vqtbx3q_u8", + "vqtbx3_p8", + "vqtbx3q_p8", + "vqtbl4_s8", + "vqtbl4q_s8", + "vqtbl4_u8", + "vqtbl4q_u8", + "vqtbl4_p8", + "vqtbl4q_p8", + "vqtbx4_s8", + "vqtbx4q_s8", + "vqtbx4_u8", + "vqtbx4q_u8", + "vqtbx4_p8", + "vqtbx4q_p8", + "brk", + "_rev_u64", + "_clz_u64", + "_rbit_u64", + "_cls_u32", + "_cls_u64", + "_prefetch", + "vsli_n_s8", + "vsliq_n_s8", + "vsli_n_s16", + "vsliq_n_s16", + "vsli_n_s32", + "vsliq_n_s32", + "vsli_n_s64", + "vsliq_n_s64", + "vsli_n_u8", + "vsliq_n_u8", + "vsli_n_u16", + "vsliq_n_u16", + "vsli_n_u32", + "vsliq_n_u32", + "vsli_n_u64", + "vsliq_n_u64", + "vsli_n_p8", + "vsliq_n_p8", + "vsli_n_p16", + "vsliq_n_p16", + "vsli_n_p64", + "vsliq_n_p64", + "vsri_n_s8", + "vsriq_n_s8", + "vsri_n_s16", + "vsriq_n_s16", + "vsri_n_s32", + "vsriq_n_s32", + "vsri_n_s64", + "vsriq_n_s64", + "vsri_n_u8", + "vsriq_n_u8", + "vsri_n_u16", + "vsriq_n_u16", + "vsri_n_u32", + "vsriq_n_u32", + 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"vextq_p64", + "vfma_f64", + "vfma_lane_f16", + "vfma_laneq_f16", + "vfmaq_lane_f16", + "vfmaq_laneq_f16", + "vfma_lane_f32", + "vfma_laneq_f32", + "vfmaq_lane_f32", + "vfmaq_laneq_f32", + "vfmaq_laneq_f64", + "vfma_lane_f64", + "vfma_laneq_f64", + "vfma_n_f16", + "vfmaq_n_f16", + "vfma_n_f64", + "vfmad_lane_f64", + "vfmah_f16", + "vfmah_lane_f16", + "vfmah_laneq_f16", + "vfmaq_f64", + "vfmaq_lane_f64", + "vfmaq_n_f64", + "vfmas_lane_f32", + "vfmas_laneq_f32", + "vfmad_laneq_f64", + "vfmlal_high_f16", + "vfmlalq_high_f16", + "vfmlal_lane_high_f16", + "vfmlal_laneq_high_f16", + "vfmlalq_lane_high_f16", + "vfmlalq_laneq_high_f16", + "vfmlal_lane_low_f16", + "vfmlal_laneq_low_f16", + "vfmlalq_lane_low_f16", + "vfmlalq_laneq_low_f16", + "vfmlal_low_f16", + "vfmlalq_low_f16", + "vfmlsl_high_f16", + "vfmlslq_high_f16", + "vfmlsl_lane_high_f16", + "vfmlsl_laneq_high_f16", + "vfmlslq_lane_high_f16", + "vfmlslq_laneq_high_f16", + "vfmlsl_lane_low_f16", + "vfmlsl_laneq_low_f16", + "vfmlslq_lane_low_f16", + "vfmlslq_laneq_low_f16", + "vfmlsl_low_f16", + "vfmlslq_low_f16", + "vfms_f64", + "vfms_lane_f16", + "vfms_laneq_f16", + "vfmsq_lane_f16", + "vfmsq_laneq_f16", + "vfms_lane_f32", + "vfms_laneq_f32", + "vfmsq_lane_f32", + "vfmsq_laneq_f32", + "vfmsq_laneq_f64", + "vfms_lane_f64", + "vfms_laneq_f64", + "vfms_n_f16", + "vfmsq_n_f16", + "vfms_n_f64", + "vfmsh_f16", + "vfmsh_lane_f16", + "vfmsh_laneq_f16", + "vfmsq_f64", + "vfmsq_lane_f64", + "vfmsq_n_f64", + "vfmss_lane_f32", + "vfmss_laneq_f32", + "vfmsd_lane_f64", + "vfmsd_laneq_f64", + "vld1_f16", + "vld1q_f16", + "vld1_f64_x2", + "vld1_f64_x3", + "vld1_f64_x4", + "vld1q_f64_x2", + "vld1q_f64_x3", + "vld1q_f64_x4", + "vld2_dup_f64", + "vld2q_dup_f64", + "vld2q_dup_s64", + "vld2_f64", + "vld2_lane_f64", + "vld2_lane_s64", + "vld2_lane_p64", + "vld2_lane_u64", + "vld2q_dup_p64", + "vld2q_dup_p64", + "vld2q_dup_u64", + "vld2q_dup_u64", + "vld2q_f64", + "vld2q_s64", + "vld2q_lane_f64", + "vld2q_lane_s8", + "vld2q_lane_s64", + "vld2q_lane_p64", + "vld2q_lane_u8", + "vld2q_lane_u64", + "vld2q_lane_p8", + "vld2q_p64", + "vld2q_p64", + "vld2q_u64", + "vld3_dup_f64", + "vld3q_dup_f64", + "vld3q_dup_s64", + "vld3_f64", + "vld3_lane_f64", + "vld3_lane_p64", + "vld3_lane_s64", + "vld3_lane_u64", + "vld3q_dup_p64", + "vld3q_dup_p64", + "vld3q_dup_u64", + "vld3q_dup_u64", + "vld3q_f64", + "vld3q_s64", + "vld3q_lane_f64", + "vld3q_lane_p64", + "vld3q_lane_s8", + "vld3q_lane_s64", + "vld3q_lane_u8", + "vld3q_lane_u64", + "vld3q_lane_p8", + "vld3q_p64", + "vld3q_p64", + "vld3q_u64", + "vld4_dup_f64", + "vld4q_dup_f64", + "vld4q_dup_s64", + "vld4_f64", + "vld4_lane_f64", + "vld4_lane_s64", + "vld4_lane_p64", + "vld4_lane_u64", + "vld4q_dup_p64", + "vld4q_dup_p64", + "vld4q_dup_u64", + "vld4q_dup_u64", + "vld4q_f64", + "vld4q_s64", + "vld4q_lane_f64", + "vld4q_lane_s8", + "vld4q_lane_s64", + "vld4q_lane_p64", + "vld4q_lane_u8", + "vld4q_lane_u64", + "vld4q_lane_p8", + "vld4q_p64", + "vld4q_p64", + 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+ "vmla_f64", + "vmlaq_f64", + "vmlal_high_lane_s16", + "vmlal_high_laneq_s16", + "vmlal_high_lane_s32", + "vmlal_high_laneq_s32", + "vmlal_high_lane_u16", + "vmlal_high_laneq_u16", + "vmlal_high_lane_u32", + "vmlal_high_laneq_u32", + "vmlal_high_n_s16", + "vmlal_high_n_s32", + "vmlal_high_n_u16", + "vmlal_high_n_u32", + "vmlal_high_s8", + "vmlal_high_s16", + "vmlal_high_s32", + "vmlal_high_u8", + "vmlal_high_u16", + "vmlal_high_u32", + "vmls_f64", + "vmlsq_f64", + "vmlsl_high_lane_s16", + "vmlsl_high_laneq_s16", + "vmlsl_high_lane_s32", + "vmlsl_high_laneq_s32", + "vmlsl_high_lane_u16", + "vmlsl_high_laneq_u16", + "vmlsl_high_lane_u32", + "vmlsl_high_laneq_u32", + "vmlsl_high_n_s16", + "vmlsl_high_n_s32", + "vmlsl_high_n_u16", + "vmlsl_high_n_u32", + "vmlsl_high_s8", + "vmlsl_high_s16", + "vmlsl_high_s32", + "vmlsl_high_u8", + "vmlsl_high_u16", + "vmlsl_high_u32", + "vmovl_high_s8", + "vmovl_high_s16", + "vmovl_high_s32", + "vmovl_high_u8", + "vmovl_high_u16", + "vmovl_high_u32", + "vmovn_high_s16", + "vmovn_high_s32", + "vmovn_high_s64", + "vmovn_high_u16", + "vmovn_high_u32", + "vmovn_high_u64", + "vmul_f64", + "vmulq_f64", + "vmul_lane_f64", + "vmul_laneq_f16", + "vmulq_laneq_f16", + "vmul_laneq_f64", + "vmul_n_f64", + "vmulq_n_f64", + "vmuld_lane_f64", + "vmulh_f16", + "vmulh_lane_f16", + "vmulh_laneq_f16", + "vmull_high_lane_s16", + "vmull_high_laneq_s16", + "vmull_high_lane_s32", + "vmull_high_laneq_s32", + "vmull_high_lane_u16", + "vmull_high_laneq_u16", + "vmull_high_lane_u32", + "vmull_high_laneq_u32", + "vmull_high_n_s16", + "vmull_high_n_s32", + "vmull_high_n_u16", + "vmull_high_n_u32", + "vmull_high_p64", + "vmull_high_p8", + "vmull_high_s8", + "vmull_high_s16", + "vmull_high_s32", + "vmull_high_u8", + "vmull_high_u16", + "vmull_high_u32", + "vmull_p64", + "vmulq_lane_f64", + "vmulq_laneq_f64", + "vmuls_lane_f32", + "vmuls_laneq_f32", + "vmuld_laneq_f64", + "vmulx_f16", + "vmulxq_f16", + "vmulx_f32", + "vmulxq_f32", + "vmulx_f64", + "vmulxq_f64", + "vmulx_lane_f16", + "vmulx_laneq_f16", + "vmulxq_lane_f16", + "vmulxq_laneq_f16", + "vmulx_lane_f32", + "vmulx_laneq_f32", + "vmulxq_lane_f32", + "vmulxq_laneq_f32", + "vmulxq_laneq_f64", + "vmulx_lane_f64", + "vmulx_laneq_f64", + "vmulx_n_f16", + "vmulxq_n_f16", + "vmulxd_f64", + "vmulxs_f32", + "vmulxd_lane_f64", + "vmulxd_laneq_f64", + "vmulxs_lane_f32", + "vmulxs_laneq_f32", + "vmulxh_f16", + "vmulxh_lane_f16", + "vmulxh_laneq_f16", + "vmulxq_lane_f64", + "vneg_f64", + "vnegq_f64", + "vneg_s64", + "vnegq_s64", + "vnegd_s64", + "vnegh_f16", + "vpaddd_f64", + "vpadds_f32", + "vpaddd_s64", + "vpaddd_u64", + "vpaddq_f16", + "vpaddq_f32", + "vpaddq_f64", + "vpaddq_s8", + "vpaddq_s16", + "vpaddq_s32", + "vpaddq_s64", + "vpaddq_u8", + "vpaddq_u16", + "vpaddq_u32", + "vpaddq_u64", + "vpmax_f16", + "vpmaxq_f16", + "vpmaxnm_f16", + "vpmaxnmq_f16", + "vpmaxnm_f32", + "vpmaxnmq_f32", + "vpmaxnmq_f64", + "vpmaxnmqd_f64", + "vpmaxnms_f32", + "vpmaxq_s8", + "vpmaxq_s16", + "vpmaxq_s32", + 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"vaddhn_high_s16", + "vaddhn_high_s32", + "vaddhn_high_s64", + "vaddhn_high_u16", + "vaddhn_high_u32", + "vaddhn_high_u64", + "vaddhn_s16", + "vaddhn_s32", + "vaddhn_s64", + "vaddhn_u16", + "vaddhn_u32", + "vaddhn_u64", + "vaddq_p128", + "vaesdq_u8", + "vaeseq_u8", + "vaesimcq_u8", + "vaesmcq_u8", + "vbsl_f16", + "vbslq_f16", + "vcage_f16", + "vcageq_f16", + "vcage_f32", + "vcageq_f32", + "vcagt_f16", + "vcagtq_f16", + "vcagt_f32", + "vcagtq_f32", + "vcale_f16", + "vcaleq_f16", + "vcale_f32", + "vcaleq_f32", + "vcalt_f16", + "vcaltq_f16", + "vcalt_f32", + "vcaltq_f32", + "vceq_f16", + "vceqq_f16", + "vceq_p8", + "vceqq_p8", + "vcge_f16", + "vcgeq_f16", + "vcgez_f16", + "vcgezq_f16", + "vcgt_f16", + "vcgtq_f16", + "vcgtz_f16", + "vcgtzq_f16", + "vcle_f16", + "vcleq_f16", + "vclez_f16", + "vclezq_f16", + "vcls_s8", + "vclsq_s8", + "vcls_s16", + "vclsq_s16", + "vcls_s32", + "vclsq_s32", + "vcls_u8", + "vclsq_u8", + "vcls_u16", + "vclsq_u16", + "vcls_u32", + "vclsq_u32", + "vclt_f16", + "vcltq_f16", + "vcltz_f16", + "vcltzq_f16", + "vclz_s8", + "vclzq_s8", + "vclz_s16", + "vclzq_s16", + "vclz_s32", + "vclzq_s32", + "vclz_u16", + "vclz_u16", + "vclzq_u16", + "vclzq_u16", + "vclz_u32", + "vclz_u32", + "vclzq_u32", + "vclzq_u32", + "vclz_u8", + "vclz_u8", + "vclzq_u8", + "vclzq_u8", + "vcnt_s8", + "vcntq_s8", + "vcnt_u8", + "vcnt_u8", + "vcntq_u8", + "vcntq_u8", + "vcnt_p8", + "vcnt_p8", + "vcntq_p8", + "vcntq_p8", + "vcombine_f16", + "vcreate_f16", + "vcreate_f16", + "vcreate_f32", + "vcreate_f32", + "vcreate_s8", + "vcreate_s8", + "vcreate_s16", + "vcreate_s16", + "vcreate_s32", + "vcreate_s32", + "vcreate_s64", + "vcreate_u8", + "vcreate_u8", + "vcreate_u16", + "vcreate_u16", + "vcreate_u32", + "vcreate_u32", + "vcreate_u64", + "vcreate_p8", + "vcreate_p8", + "vcreate_p16", + "vcreate_p16", + "vcreate_p64", + "vcvt_f16_f32", + "vcvt_f16_s16", + "vcvtq_f16_s16", + "vcvt_f16_u16", + "vcvtq_f16_u16", + "vcvt_f32_f16", + "vcvt_f32_s32", + "vcvtq_f32_s32", + "vcvt_f32_u32", + "vcvtq_f32_u32", + "vcvt_n_f16_s16", + "vcvtq_n_f16_s16", + "vcvt_n_f16_u16", + "vcvtq_n_f16_u16", + "vcvt_n_f32_s32", + "vcvtq_n_f32_s32", + "vcvt_n_f32_s32", + "vcvtq_n_f32_s32", + "vcvt_n_f32_u32", + "vcvtq_n_f32_u32", + "vcvt_n_f32_u32", + "vcvtq_n_f32_u32", + "vcvt_n_s16_f16", + "vcvtq_n_s16_f16", + "vcvt_n_s32_f32", + "vcvtq_n_s32_f32", + "vcvt_n_s32_f32", + "vcvtq_n_s32_f32", + "vcvt_n_u16_f16", + "vcvtq_n_u16_f16", + "vcvt_n_u32_f32", + "vcvtq_n_u32_f32", + "vcvt_n_u32_f32", + "vcvtq_n_u32_f32", + "vcvt_s16_f16", + "vcvtq_s16_f16", + "vcvt_s32_f32", + "vcvtq_s32_f32", + "vcvt_u16_f16", + "vcvtq_u16_f16", + "vcvt_u32_f32", + "vcvtq_u32_f32", + "vdot_lane_s32", + "vdot_lane_s32", + "vdotq_lane_s32", + "vdotq_lane_s32", + "vdot_lane_u32", + "vdot_lane_u32", + "vdotq_lane_u32", + "vdotq_lane_u32", + "vdot_laneq_s32", + "vdot_laneq_s32", + "vdotq_laneq_s32", + "vdotq_laneq_s32", + "vdot_laneq_u32", + "vdot_laneq_u32", + "vdotq_laneq_u32", + "vdotq_laneq_u32", + "vdot_s32", + "vdotq_s32", + "vdot_u32", + "vdotq_u32", + "vdup_lane_f16", + "vdupq_lane_f16", + "vdup_lane_f32", + "vdup_lane_s32", + "vdup_lane_u32", + "vdupq_lane_f32", + "vdupq_lane_s32", + "vdupq_lane_u32", + "vdup_lane_p16", + "vdup_lane_s16", + "vdup_lane_u16", + "vdupq_lane_p16", + "vdupq_lane_s16", + "vdupq_lane_u16", + "vdup_lane_p8", + "vdup_lane_s8", + "vdup_lane_u8", + "vdupq_lane_p8", + "vdupq_lane_s8", + "vdupq_lane_u8", + "vdup_lane_s64", + "vdup_lane_u64", + "vdup_laneq_f16", + "vdupq_laneq_f16", + "vdup_laneq_f32", + "vdup_laneq_s32", + "vdup_laneq_u32", + "vdupq_laneq_f32", + "vdupq_laneq_s32", + "vdupq_laneq_u32", + "vdup_laneq_p16", + "vdup_laneq_s16", + "vdup_laneq_u16", + "vdupq_laneq_p16", + "vdupq_laneq_s16", + "vdupq_laneq_u16", + "vdup_laneq_p8", + "vdup_laneq_s8", + "vdup_laneq_u8", + "vdupq_laneq_p8", + "vdupq_laneq_s8", + "vdupq_laneq_u8", + "vdup_laneq_s64", + "vdup_laneq_u64", + "vdup_n_f16", + "vdupq_n_f16", + "vdupq_lane_s64", + "vdupq_lane_u64", + "vdupq_laneq_s64", + "vdupq_laneq_u64", + "vext_f16", + "vext_f32", + "vext_s32", + "vext_u32", + "vext_s8", + "vextq_s16", + "vext_u8", + "vextq_u16", + "vext_p8", + "vextq_p16", + "vextq_f16", + "vextq_f32", + "vext_s16", + "vextq_s32", + "vext_u16", + "vextq_u32", + "vext_p16", + "vextq_s64", + "vextq_u64", + "vextq_s8", + "vextq_u8", + "vextq_p8", + "vfma_f16", + "vfmaq_f16", + "vfma_f32", + "vfmaq_f32", + "vfma_n_f32", + "vfmaq_n_f32", + "vfms_f16", + "vfmsq_f16", + "vfms_f32", + "vfmsq_f32", + "vfms_n_f32", + "vfmsq_n_f32", + "vget_high_f16", + "vget_low_f16", + "vget_lane_f16", + "vgetq_lane_f16", + "vld1_dup_f16", + "vld1q_dup_f16", + "vld1_f16", + "vld1_f16", + "vld1q_f16", + "vld1q_f16", + "vld1_f16_x2", + "vld1_f16_x3", + "vld1_f16_x4", + "vld1q_f16_x2", + "vld1q_f16_x3", + "vld1q_f16_x4", + "vld1_f32_x2", + "vld1_f32_x3", + "vld1_f32_x4", + "vld1q_f32_x2", + "vld1q_f32_x3", + "vld1q_f32_x4", + "vld1_lane_f16", + "vld1q_lane_f16", + "vld1_p64_x2", + "vld1_p64_x3", + "vld1_p64_x4", + "vld1q_p64_x2", + "vld1q_p64_x3", + "vld1q_p64_x4", + "vld1_s8_x2", + "vld1_s8_x3", + "vld1_s8_x4", + "vld1q_s8_x2", + "vld1q_s8_x3", + "vld1q_s8_x4", + "vld1_s16_x2", + "vld1_s16_x3", + "vld1_s16_x4", + "vld1q_s16_x2", + "vld1q_s16_x3", + "vld1q_s16_x4", + "vld1_s32_x2", + "vld1_s32_x3", + "vld1_s32_x4", + "vld1q_s32_x2", + "vld1q_s32_x3", + "vld1q_s32_x4", + "vld1_s64_x2", + "vld1_s64_x3", + "vld1_s64_x4", + "vld1q_s64_x2", + "vld1q_s64_x3", + "vld1q_s64_x4", + "vld1_u8_x2", + "vld1_u8_x3", + "vld1_u8_x4", + "vld1q_u8_x2", + "vld1q_u8_x3", + "vld1q_u8_x4", + "vld1_u16_x2", + "vld1_u16_x3", + "vld1_u16_x4", + "vld1q_u16_x2", + "vld1q_u16_x3", + "vld1q_u16_x4", + "vld1_u32_x2", + "vld1_u32_x3", + "vld1_u32_x4", + "vld1q_u32_x2", + "vld1q_u32_x3", + "vld1q_u32_x4", + "vld1_u64_x2", + "vld1_u64_x3", + "vld1_u64_x4", + "vld1q_u64_x2", + "vld1q_u64_x3", + "vld1q_u64_x4", + "vld1_p8_x2", + "vld1_p8_x3", + "vld1_p8_x4", + "vld1q_p8_x2", + "vld1q_p8_x3", + "vld1q_p8_x4", + "vld1_p16_x2", + "vld1_p16_x3", + "vld1_p16_x4", + "vld1q_p16_x2", + "vld1q_p16_x3", + "vld1q_p16_x4", + "vld2_dup_f16", + "vld2q_dup_f16", + "vld2_dup_f16", + "vld2q_dup_f16", + "vld2_dup_f32", + "vld2q_dup_f32", + "vld2_dup_s8", + "vld2q_dup_s8", + "vld2_dup_s16", + "vld2q_dup_s16", + "vld2_dup_s32", + "vld2q_dup_s32", + "vld2_dup_f32", + "vld2q_dup_f32", + "vld2_dup_s8", + "vld2q_dup_s8", + "vld2_dup_s16", + "vld2q_dup_s16", + "vld2_dup_s32", + "vld2q_dup_s32", + "vld2_dup_p64", + "vld2_dup_s64", + "vld2_dup_s64", + "vld2_dup_u64", + "vld2_dup_u8", + "vld2_dup_u8", + "vld2q_dup_u8", + "vld2q_dup_u8", + "vld2_dup_u16", + "vld2_dup_u16", + "vld2q_dup_u16", + "vld2q_dup_u16", + "vld2_dup_u32", + "vld2_dup_u32", + "vld2q_dup_u32", + "vld2q_dup_u32", + "vld2_dup_p8", + "vld2_dup_p8", + "vld2q_dup_p8", + "vld2q_dup_p8", + "vld2_dup_p16", + "vld2_dup_p16", + "vld2q_dup_p16", + "vld2q_dup_p16", + "vld2_f16", + "vld2q_f16", + "vld2_f16", + "vld2q_f16", + "vld2_f32", + "vld2q_f32", + "vld2_s8", + "vld2q_s8", + "vld2_s16", + "vld2q_s16", + "vld2_s32", + "vld2q_s32", + "vld2_f32", + "vld2q_f32", + "vld2_s8", + "vld2q_s8", + "vld2_s16", + "vld2q_s16", + "vld2_s32", + "vld2q_s32", + "vld2_lane_f16", + "vld2q_lane_f16", + "vld2_lane_f16", + "vld2q_lane_f16", + "vld2_lane_f32", + "vld2q_lane_f32", + "vld2_lane_s8", + "vld2_lane_s16", + "vld2q_lane_s16", + "vld2_lane_s32", + "vld2q_lane_s32", + "vld2_lane_f32", + "vld2q_lane_f32", + "vld2q_lane_s16", + "vld2q_lane_s32", + "vld2_lane_s8", + "vld2_lane_s16", + "vld2_lane_s32", + "vld2_lane_u8", + "vld2_lane_u16", + "vld2q_lane_u16", + "vld2_lane_u32", + "vld2q_lane_u32", + "vld2_lane_p8", + "vld2_lane_p16", + "vld2q_lane_p16", + "vld2_p64", + "vld2_s64", + "vld2_s64", + "vld2_u64", + "vld2_u8", + "vld2q_u8", + "vld2_u16", + "vld2q_u16", + "vld2_u32", + "vld2q_u32", + "vld2_p8", + "vld2q_p8", + "vld2_p16", + "vld2q_p16", + "vld3_dup_f16", + "vld3q_dup_f16", + "vld3_dup_f16", + "vld3q_dup_f16", + "vld3_dup_f32", + "vld3q_dup_f32", + "vld3_dup_s8", + "vld3q_dup_s8", + "vld3_dup_s16", + "vld3q_dup_s16", + "vld3_dup_s32", + "vld3q_dup_s32", + "vld3_dup_s64", + "vld3_dup_f32", + "vld3q_dup_f32", + "vld3_dup_s8", + "vld3q_dup_s8", + "vld3_dup_s16", + "vld3q_dup_s16", + "vld3_dup_s32", + "vld3q_dup_s32", + "vld3_dup_p64", + "vld3_dup_s64", + "vld3_dup_u64", + "vld3_dup_u8", + "vld3_dup_u8", + "vld3q_dup_u8", + "vld3q_dup_u8", + "vld3_dup_u16", + "vld3_dup_u16", + "vld3q_dup_u16", + "vld3q_dup_u16", + "vld3_dup_u32", + "vld3_dup_u32", + "vld3q_dup_u32", + "vld3q_dup_u32", + "vld3_dup_p8", + "vld3_dup_p8", + "vld3q_dup_p8", + "vld3q_dup_p8", + "vld3_dup_p16", + "vld3_dup_p16", + "vld3q_dup_p16", + "vld3q_dup_p16", + "vld3_f16", + "vld3q_f16", + "vld3_f16", + "vld3q_f16", + "vld3_f32", + "vld3q_f32", + "vld3_s8", + "vld3q_s8", + "vld3_s16", + "vld3q_s16", + "vld3_s32", + "vld3q_s32", + "vld3_f32", + "vld3q_f32", + "vld3_s8", + "vld3q_s8", + "vld3_s16", + "vld3q_s16", + "vld3_s32", + "vld3q_s32", + "vld3_lane_f16", + "vld3q_lane_f16", + "vld3_lane_f16", + "vld3q_lane_f16", + "vld3_lane_f32", + "vld3q_lane_f32", + "vld3_lane_f32", + "vld3_lane_s8", + "vld3_lane_s16", + "vld3q_lane_s16", + "vld3_lane_s32", + "vld3q_lane_s32", + "vld3_lane_s8", + "vld3_lane_s16", + "vld3q_lane_s16", + "vld3_lane_s32", + "vld3q_lane_s32", + "vld3_lane_u8", + "vld3_lane_u16", + "vld3q_lane_u16", + "vld3_lane_u32", + "vld3q_lane_u32", + "vld3_lane_p8", + "vld3_lane_p16", + "vld3q_lane_p16", + "vld3_p64", + "vld3_s64", + "vld3_s64", + "vld3_u64", + "vld3_u8", + "vld3q_u8", + "vld3_u16", + "vld3q_u16", + "vld3_u32", + "vld3q_u32", + "vld3_p8", + "vld3q_p8", + "vld3_p16", + "vld3q_p16", + "vld3q_lane_f32", + "vld4_dup_f16", + "vld4q_dup_f16", + "vld4_dup_f16", + "vld4q_dup_f16", + "vld4_dup_f32", + "vld4q_dup_f32", + "vld4_dup_s8", + "vld4q_dup_s8", + "vld4_dup_s16", + "vld4q_dup_s16", + "vld4_dup_s32", + "vld4q_dup_s32", + "vld4_dup_f32", + "vld4q_dup_f32", + "vld4_dup_s8", + "vld4q_dup_s8", + "vld4_dup_s16", + "vld4q_dup_s16", + "vld4_dup_s32", + "vld4q_dup_s32", + "vld4_dup_s64", + "vld4_dup_p64", + "vld4_dup_s64", + "vld4_dup_u64", + "vld4_dup_u8", + "vld4_dup_u8", + "vld4q_dup_u8", + "vld4q_dup_u8", + "vld4_dup_u16", + "vld4_dup_u16", + "vld4q_dup_u16", + "vld4q_dup_u16", + "vld4_dup_u32", + "vld4_dup_u32", + "vld4q_dup_u32", + "vld4q_dup_u32", + "vld4_dup_p8", + "vld4_dup_p8", + "vld4q_dup_p8", + "vld4q_dup_p8", + "vld4_dup_p16", + "vld4_dup_p16", + "vld4q_dup_p16", + "vld4q_dup_p16", + "vld4_f16", + "vld4q_f16", + "vld4_f16", + "vld4q_f16", + "vld4_f32", + "vld4q_f32", + "vld4_s8", + "vld4q_s8", + "vld4_s16", + "vld4q_s16", + "vld4_s32", + "vld4q_s32", + "vld4_f32", + "vld4q_f32", + "vld4_s8", + "vld4q_s8", + "vld4_s16", + "vld4q_s16", + "vld4_s32", + "vld4q_s32", + "vld4_lane_f16", + "vld4q_lane_f16", + "vld4_lane_f16", + "vld4q_lane_f16", + "vld4_lane_f32", + "vld4q_lane_f32", + "vld4_lane_s8", + "vld4_lane_s16", + "vld4q_lane_s16", + "vld4_lane_s32", + "vld4q_lane_s32", + "vld4_lane_f32", + "vld4q_lane_f32", + "vld4_lane_s8", + "vld4_lane_s16", + "vld4q_lane_s16", + "vld4_lane_s32", + "vld4q_lane_s32", + "vld4_lane_u8", + "vld4_lane_u16", + "vld4q_lane_u16", + "vld4_lane_u32", + "vld4q_lane_u32", + "vld4_lane_p8", + "vld4_lane_p16", + "vld4q_lane_p16", + "vld4_p64", + "vld4_s64", + "vld4_s64", + "vld4_u64", + "vld4_u8", + "vld4q_u8", + "vld4_u16", + "vld4q_u16", + "vld4_u32", + "vld4q_u32", + "vld4_p8", + "vld4q_p8", + "vld4_p16", + "vld4q_p16", + "vmax_f16", + "vmaxq_f16", + "vmax_f32", + "vmaxq_f32", + "vmax_s8", + "vmaxq_s8", + "vmax_s16", + "vmaxq_s16", + "vmax_s32", + "vmaxq_s32", + "vmax_u8", + "vmaxq_u8", + "vmax_u16", + "vmaxq_u16", + "vmax_u32", + "vmaxq_u32", + "vmaxnm_f16", + "vmaxnmq_f16", + "vmaxnm_f32", + "vmaxnmq_f32", + "vmin_f16", + "vminq_f16", + "vmin_f32", + "vminq_f32", + "vmin_s8", + "vminq_s8", + "vmin_s16", + "vminq_s16", + "vmin_s32", + "vminq_s32", + "vmin_u8", + "vminq_u8", + "vmin_u16", + "vminq_u16", + "vmin_u32", + "vminq_u32", + "vminnm_f16", + "vminnmq_f16", + "vminnm_f32", + "vminnmq_f32", + "vmla_f32", + "vmlaq_f32", + "vmla_lane_f32", + "vmla_laneq_f32", + "vmlaq_lane_f32", + "vmlaq_laneq_f32", + "vmla_lane_s16", + "vmla_lane_u16", + "vmla_laneq_s16", + "vmla_laneq_u16", + "vmlaq_lane_s16", + "vmlaq_lane_u16", + "vmlaq_laneq_s16", + "vmlaq_laneq_u16", + "vmla_lane_s32", + "vmla_lane_u32", + "vmla_laneq_s32", + "vmla_laneq_u32", + "vmlaq_lane_s32", + "vmlaq_lane_u32", + "vmlaq_laneq_s32", + "vmlaq_laneq_u32", + "vmla_n_f32", + "vmlaq_n_f32", + "vmla_n_s16", + "vmlaq_n_s16", + "vmla_n_u16", + "vmlaq_n_u16", + "vmla_n_s32", + "vmlaq_n_s32", + "vmla_n_u32", + "vmlaq_n_u32", + "vmla_s8", + "vmlaq_s8", + "vmla_s16", + "vmlaq_s16", + "vmla_s32", + "vmlaq_s32", + "vmla_u8", + "vmlaq_u8", + "vmla_u16", + "vmlaq_u16", + "vmla_u32", + "vmlaq_u32", + "vmlal_lane_s16", + "vmlal_laneq_s16", + "vmlal_lane_s32", + "vmlal_laneq_s32", + "vmlal_lane_u16", + "vmlal_laneq_u16", + "vmlal_lane_u32", + "vmlal_laneq_u32", + "vmlal_n_s16", + "vmlal_n_s32", + "vmlal_n_u16", + "vmlal_n_u32", + "vmlal_s8", + "vmlal_s16", + "vmlal_s32", + "vmlal_u8", + "vmlal_u16", + "vmlal_u32", + "vmls_f32", + "vmlsq_f32", + "vmls_lane_f32", + "vmls_laneq_f32", + "vmlsq_lane_f32", + "vmlsq_laneq_f32", + "vmls_lane_s16", + "vmls_lane_u16", + "vmls_laneq_s16", + "vmls_laneq_u16", + "vmlsq_lane_s16", + "vmlsq_lane_u16", + "vmlsq_laneq_s16", + "vmlsq_laneq_u16", + "vmls_lane_s32", + "vmls_lane_u32", + "vmls_laneq_s32", + "vmls_laneq_u32", + "vmlsq_lane_s32", + "vmlsq_lane_u32", + "vmlsq_laneq_s32", + "vmlsq_laneq_u32", + "vmls_n_f32", + "vmlsq_n_f32", + "vmls_n_s16", + "vmlsq_n_s16", + "vmls_n_u16", + "vmlsq_n_u16", + "vmls_n_s32", + "vmlsq_n_s32", + "vmls_n_u32", + "vmlsq_n_u32", + "vmls_s8", + "vmlsq_s8", + "vmls_s16", + "vmlsq_s16", + "vmls_s32", + "vmlsq_s32", + "vmls_u8", + "vmlsq_u8", + "vmls_u16", + "vmlsq_u16", + "vmls_u32", + "vmlsq_u32", + "vmlsl_lane_s16", + "vmlsl_laneq_s16", + "vmlsl_lane_s32", + "vmlsl_laneq_s32", + "vmlsl_lane_u16", + "vmlsl_laneq_u16", + "vmlsl_lane_u32", + "vmlsl_laneq_u32", + "vmlsl_n_s16", + "vmlsl_n_s32", + "vmlsl_n_u16", + "vmlsl_n_u32", + "vmlsl_s8", + "vmlsl_s16", + "vmlsl_s32", + "vmlsl_u8", + "vmlsl_u16", + "vmlsl_u32", + "vmmlaq_s32", + "vmmlaq_u32", + "vmov_n_f16", + "vmovq_n_f16", + "vmul_f16", + "vmulq_f16", + "vmul_lane_f16", + "vmulq_lane_f16", + "vmul_lane_f32", + "vmul_laneq_f32", + "vmulq_lane_f32", + "vmulq_laneq_f32", + "vmul_lane_s16", + "vmulq_lane_s16", + "vmul_lane_s32", + "vmulq_lane_s32", + "vmul_lane_u16", + "vmulq_lane_u16", + "vmul_lane_u32", + "vmulq_lane_u32", + "vmul_laneq_s16", + "vmulq_laneq_s16", + "vmul_laneq_s32", + "vmulq_laneq_s32", + "vmul_laneq_u16", + "vmulq_laneq_u16", + "vmul_laneq_u32", + "vmulq_laneq_u32", + "vmul_n_f16", + "vmulq_n_f16", + "vmul_n_f32", + "vmulq_n_f32", + "vmul_n_s16", + "vmulq_n_s16", + "vmul_n_s32", + "vmulq_n_s32", + "vmul_n_u16", + "vmulq_n_u16", + "vmul_n_u32", + "vmulq_n_u32", + "vmul_p8", + "vmulq_p8", + "vmull_lane_s16", + "vmull_laneq_s16", + "vmull_lane_s32", + "vmull_laneq_s32", + "vmull_lane_u16", + "vmull_laneq_u16", + "vmull_lane_u32", + "vmull_laneq_u32", + "vmull_n_s16", + "vmull_n_s32", + "vmull_n_u16", + "vmull_n_u32", + "vmull_p8", + "vmull_s16", + "vmull_s32", + "vmull_s8", + "vmull_u8", + "vmull_u16", + "vmull_u32", + "vneg_f16", + "vnegq_f16", + "vneg_f32", + "vnegq_f32", + "vneg_s8", + "vnegq_s8", + "vneg_s16", + "vnegq_s16", + "vneg_s32", + "vnegq_s32", + "vpadal_s8", + "vpadalq_s8", + "vpadal_s16", + "vpadalq_s16", + "vpadal_s32", + "vpadalq_s32", + "vpadal_u8", + "vpadalq_u8", + "vpadal_u16", + "vpadalq_u16", + "vpadal_u32", + "vpadalq_u32", + "vpadd_f16", + "vpadd_f32", + "vpadd_s8", + "vpadd_s16", + "vpadd_s32", + "vpadd_u8", + "vpadd_u8", + "vpadd_u16", + "vpadd_u16", + "vpadd_u32", + "vpadd_u32", + "vpaddl_s8", + "vpaddlq_s8", + "vpaddl_s16", + "vpaddlq_s16", + "vpaddl_s32", + "vpaddlq_s32", + "vpaddl_u8", + "vpaddlq_u8", + "vpaddl_u16", + "vpaddlq_u16", + "vpaddl_u32", + "vpaddlq_u32", + "vpmax_f32", + "vpmax_s8", + "vpmax_s16", + "vpmax_s32", + "vpmax_u8", + "vpmax_u16", + "vpmax_u32", + "vpmin_f32", + "vpmin_s8", + "vpmin_s16", + "vpmin_s32", + "vpmin_u8", + "vpmin_u16", + "vpmin_u32", + "vqabs_s8", + "vqabsq_s8", + "vqabs_s16", + "vqabsq_s16", + "vqabs_s32", + "vqabsq_s32", + "vqadd_s64", + "vqaddq_s64", + "vqadd_u64", + "vqaddq_u64", + "vqdmlal_lane_s16", + "vqdmlal_lane_s32", + "vqdmlal_n_s16", + "vqdmlal_n_s32", + "vqdmlal_s16", + "vqdmlal_s32", + "vqdmlsl_lane_s16", + "vqdmlsl_lane_s32", + "vqdmlsl_n_s16", + "vqdmlsl_n_s32", + "vqdmlsl_s16", + "vqdmlsl_s32", + "vqdmulh_laneq_s16", + "vqdmulhq_laneq_s16", + "vqdmulh_laneq_s32", + "vqdmulhq_laneq_s32", + "vqdmulh_n_s16", + "vqdmulhq_n_s16", + "vqdmulh_n_s32", + "vqdmulhq_n_s32", + "vqdmulh_s16", + "vqdmulhq_s16", + "vqdmulh_s32", + "vqdmulhq_s32", + "vqdmull_lane_s16", + "vqdmull_lane_s32", + "vqdmull_n_s16", + "vqdmull_n_s32", + "vqdmull_s16", + "vqdmull_s32", + "vqmovn_s16", + "vqmovn_s32", + "vqmovn_s64", + "vqmovn_u16", + "vqmovn_u32", + "vqmovn_u64", + "vqmovun_s16", + "vqmovun_s32", + "vqmovun_s64", + "vqneg_s8", + "vqnegq_s8", + "vqneg_s16", + "vqnegq_s16", + "vqneg_s32", + "vqnegq_s32", + "vqrdmulh_lane_s16", + "vqrdmulh_lane_s32", + "vqrdmulh_laneq_s16", + "vqrdmulh_laneq_s32", + "vqrdmulhq_lane_s16", + "vqrdmulhq_lane_s32", + "vqrdmulhq_laneq_s16", + "vqrdmulhq_laneq_s32", + "vqrdmulh_n_s16", + "vqrdmulhq_n_s16", + "vqrdmulh_n_s32", + "vqrdmulhq_n_s32", + "vqrdmulh_s16", + "vqrdmulhq_s16", + "vqrdmulh_s32", + "vqrdmulhq_s32", + "vqrshl_s8", + "vqrshlq_s8", + "vqrshl_s16", + "vqrshlq_s16", + "vqrshl_s32", + "vqrshlq_s32", + "vqrshl_s64", + "vqrshlq_s64", + "vqrshl_u8", + "vqrshlq_u8", + "vqrshl_u16", + "vqrshlq_u16", + "vqrshl_u32", + "vqrshlq_u32", + "vqrshl_u64", + "vqrshlq_u64", + "vqrshrn_n_s16", + "vqrshrn_n_s32", + "vqrshrn_n_s64", + "vqrshrn_n_s16", + "vqrshrn_n_s32", + "vqrshrn_n_s64", + "vqrshrn_n_u16", + "vqrshrn_n_u32", + "vqrshrn_n_u64", + "vqrshrn_n_u16", + "vqrshrn_n_u32", + "vqrshrn_n_u64", + "vqrshrun_n_s16", + "vqrshrun_n_s32", + "vqrshrun_n_s64", + "vqrshrun_n_s16", + "vqrshrun_n_s32", + "vqrshrun_n_s64", + "vqshl_n_s8", + "vqshlq_n_s8", + "vqshl_n_s16", + "vqshlq_n_s16", + "vqshl_n_s32", + "vqshlq_n_s32", + "vqshl_n_s64", + "vqshlq_n_s64", + "vqshl_n_u8", + "vqshlq_n_u8", + "vqshl_n_u16", + "vqshlq_n_u16", + "vqshl_n_u32", + "vqshlq_n_u32", + "vqshl_n_u64", + "vqshlq_n_u64", + "vqshl_s8", + "vqshlq_s8", + "vqshl_s16", + "vqshlq_s16", + "vqshl_s32", + "vqshlq_s32", + "vqshl_s64", + "vqshlq_s64", + "vqshl_u8", + "vqshlq_u8", + "vqshl_u16", + "vqshlq_u16", + "vqshl_u32", + "vqshlq_u32", + "vqshl_u64", + "vqshlq_u64", + "vqshlu_n_s8", + "vqshluq_n_s8", + "vqshlu_n_s16", + "vqshluq_n_s16", + "vqshlu_n_s32", + "vqshluq_n_s32", + "vqshlu_n_s64", + "vqshluq_n_s64", + "vqshlu_n_s8", + "vqshluq_n_s8", + "vqshlu_n_s16", + "vqshluq_n_s16", + "vqshlu_n_s32", + "vqshluq_n_s32", + "vqshlu_n_s64", + "vqshluq_n_s64", + "vqshrn_n_s16", + "vqshrn_n_s32", + "vqshrn_n_s64", + "vqshrn_n_s16", + "vqshrn_n_s32", + "vqshrn_n_s64", + "vqshrn_n_u16", + "vqshrn_n_u32", + "vqshrn_n_u64", + "vqshrn_n_u16", + "vqshrn_n_u32", + "vqshrn_n_u64", + "vqshrun_n_s16", + "vqshrun_n_s32", + "vqshrun_n_s64", + "vqshrun_n_s16", + "vqshrun_n_s32", + "vqshrun_n_s64", + "vqsub_s64", + "vqsubq_s64", + "vqsub_u64", + "vqsubq_u64", + "vraddhn_high_s16", + "vraddhn_high_s32", + "vraddhn_high_s64", + "vraddhn_high_u16", + "vraddhn_high_u32", + "vraddhn_high_u64", + "vraddhn_s16", + "vraddhn_s32", + "vraddhn_s64", + "vraddhn_u16", + "vraddhn_u16", + "vraddhn_u32", + "vraddhn_u32", + "vraddhn_u64", + "vraddhn_u64", + "vrecpe_f16", + "vrecpeq_f16", + "vrecpe_f32", + "vrecpeq_f32", + "vrecpe_u32", + "vrecpeq_u32", + "vrecps_f16", + "vrecpsq_f16", + "vrecps_f32", + "vrecpsq_f32", + "vreinterpret_f32_f16", + "vreinterpret_f32_f16", + "vreinterpret_s8_f16", + "vreinterpret_s8_f16", + "vreinterpret_s16_f16", + "vreinterpret_s16_f16", + "vreinterpret_s32_f16", + "vreinterpret_s32_f16", + "vreinterpret_s64_f16", + "vreinterpret_s64_f16", + "vreinterpret_u8_f16", + "vreinterpret_u8_f16", + "vreinterpret_u16_f16", + "vreinterpret_u16_f16", + "vreinterpret_u32_f16", + "vreinterpret_u32_f16", + "vreinterpret_u64_f16", + "vreinterpret_u64_f16", + "vreinterpret_p8_f16", + "vreinterpret_p8_f16", + "vreinterpret_p16_f16", + "vreinterpret_p16_f16", + "vreinterpretq_f32_f16", + "vreinterpretq_f32_f16", + "vreinterpretq_s8_f16", + "vreinterpretq_s8_f16", + "vreinterpretq_s16_f16", + "vreinterpretq_s16_f16", + "vreinterpretq_s32_f16", + "vreinterpretq_s32_f16", + "vreinterpretq_s64_f16", + "vreinterpretq_s64_f16", + "vreinterpretq_u8_f16", + "vreinterpretq_u8_f16", + "vreinterpretq_u16_f16", + "vreinterpretq_u16_f16", + "vreinterpretq_u32_f16", + "vreinterpretq_u32_f16", + "vreinterpretq_u64_f16", + "vreinterpretq_u64_f16", + "vreinterpretq_p8_f16", + "vreinterpretq_p8_f16", + "vreinterpretq_p16_f16", + "vreinterpretq_p16_f16", + "vreinterpret_f16_f32", + "vreinterpret_f16_f32", + "vreinterpretq_f16_f32", + "vreinterpretq_f16_f32", + "vreinterpret_f16_s8", + "vreinterpret_f16_s8", + "vreinterpretq_f16_s8", + "vreinterpretq_f16_s8", + "vreinterpret_f16_s16", + "vreinterpret_f16_s16", + "vreinterpretq_f16_s16", + "vreinterpretq_f16_s16", + "vreinterpret_f16_s32", + "vreinterpret_f16_s32", + "vreinterpretq_f16_s32", + "vreinterpretq_f16_s32", + "vreinterpret_f16_s64", + "vreinterpret_f16_s64", + "vreinterpretq_f16_s64", + "vreinterpretq_f16_s64", + "vreinterpret_f16_u8", + "vreinterpret_f16_u8", + "vreinterpretq_f16_u8", + "vreinterpretq_f16_u8", + "vreinterpret_f16_u16", + "vreinterpret_f16_u16", + "vreinterpretq_f16_u16", + "vreinterpretq_f16_u16", + "vreinterpret_f16_u32", + "vreinterpret_f16_u32", + "vreinterpretq_f16_u32", + "vreinterpretq_f16_u32", + "vreinterpret_f16_u64", + "vreinterpret_f16_u64", + "vreinterpretq_f16_u64", + "vreinterpretq_f16_u64", + "vreinterpret_f16_p8", + "vreinterpret_f16_p8", + "vreinterpretq_f16_p8", + "vreinterpretq_f16_p8", + "vreinterpret_f16_p16", + "vreinterpret_f16_p16", + "vreinterpretq_f16_p16", + "vreinterpretq_f16_p16", + "vreinterpretq_f16_p128", + "vreinterpretq_f16_p128", + "vreinterpret_p64_f16", + "vreinterpret_p64_f16", + "vreinterpretq_p128_f16", + "vreinterpretq_p128_f16", + "vreinterpretq_p64_f16", + "vreinterpretq_p64_f16", + "vreinterpret_f16_p64", + "vreinterpret_f16_p64", + "vreinterpretq_f16_p64", + "vreinterpretq_f16_p64", + "vreinterpretq_f32_p128", + "vreinterpretq_f32_p128", + "vreinterpret_s8_f32", + "vreinterpret_s8_f32", + "vreinterpret_s16_f32", + "vreinterpret_s16_f32", + "vreinterpret_s32_f32", + "vreinterpret_s32_f32", + "vreinterpret_s64_f32", + "vreinterpret_s64_f32", + "vreinterpret_u8_f32", + "vreinterpret_u8_f32", + "vreinterpret_u16_f32", + "vreinterpret_u16_f32", + "vreinterpret_u32_f32", + "vreinterpret_u32_f32", + "vreinterpret_u64_f32", + "vreinterpret_u64_f32", + "vreinterpret_p8_f32", + "vreinterpret_p8_f32", + "vreinterpret_p16_f32", + "vreinterpret_p16_f32", + "vreinterpretq_p128_f32", + "vreinterpretq_p128_f32", + "vreinterpretq_s8_f32", + "vreinterpretq_s8_f32", + "vreinterpretq_s16_f32", + "vreinterpretq_s16_f32", + "vreinterpretq_s32_f32", + "vreinterpretq_s32_f32", + "vreinterpretq_s64_f32", + "vreinterpretq_s64_f32", + "vreinterpretq_u8_f32", + "vreinterpretq_u8_f32", + "vreinterpretq_u16_f32", + "vreinterpretq_u16_f32", + "vreinterpretq_u32_f32", + "vreinterpretq_u32_f32", + "vreinterpretq_u64_f32", + "vreinterpretq_u64_f32", + "vreinterpretq_p8_f32", + "vreinterpretq_p8_f32", + "vreinterpretq_p16_f32", + "vreinterpretq_p16_f32", + "vreinterpret_f32_s8", + "vreinterpret_f32_s8", + "vreinterpret_s16_s8", + "vreinterpret_s16_s8", + "vreinterpret_s32_s8", + "vreinterpret_s32_s8", + "vreinterpret_s64_s8", + "vreinterpret_s64_s8", + "vreinterpret_u8_s8", + "vreinterpret_u8_s8", + "vreinterpret_u16_s8", + "vreinterpret_u16_s8", + "vreinterpret_u32_s8", + "vreinterpret_u32_s8", + "vreinterpret_u64_s8", + "vreinterpret_u64_s8", + "vreinterpret_p8_s8", + "vreinterpret_p8_s8", + "vreinterpret_p16_s8", + "vreinterpret_p16_s8", + "vreinterpretq_f32_s8", + "vreinterpretq_f32_s8", + "vreinterpretq_s16_s8", + "vreinterpretq_s16_s8", + "vreinterpretq_s32_s8", + "vreinterpretq_s32_s8", + "vreinterpretq_s64_s8", + "vreinterpretq_s64_s8", + "vreinterpretq_u8_s8", + "vreinterpretq_u8_s8", + "vreinterpretq_u16_s8", + "vreinterpretq_u16_s8", + "vreinterpretq_u32_s8", + "vreinterpretq_u32_s8", + "vreinterpretq_u64_s8", + "vreinterpretq_u64_s8", + "vreinterpretq_p8_s8", + "vreinterpretq_p8_s8", + "vreinterpretq_p16_s8", + "vreinterpretq_p16_s8", + "vreinterpret_f32_s16", + "vreinterpret_f32_s16", + "vreinterpret_s8_s16", + "vreinterpret_s8_s16", + "vreinterpret_s32_s16", + "vreinterpret_s32_s16", + "vreinterpret_s64_s16", + "vreinterpret_s64_s16", + "vreinterpret_u8_s16", + "vreinterpret_u8_s16", + "vreinterpret_u16_s16", + "vreinterpret_u16_s16", + "vreinterpret_u32_s16", + "vreinterpret_u32_s16", + "vreinterpret_u64_s16", + "vreinterpret_u64_s16", + "vreinterpret_p8_s16", + "vreinterpret_p8_s16", + "vreinterpret_p16_s16", + "vreinterpret_p16_s16", + "vreinterpretq_f32_s16", + "vreinterpretq_f32_s16", + "vreinterpretq_s8_s16", + "vreinterpretq_s8_s16", + "vreinterpretq_s32_s16", + "vreinterpretq_s32_s16", + "vreinterpretq_s64_s16", + "vreinterpretq_s64_s16", + "vreinterpretq_u8_s16", + "vreinterpretq_u8_s16", + "vreinterpretq_u16_s16", + "vreinterpretq_u16_s16", + "vreinterpretq_u32_s16", + "vreinterpretq_u32_s16", + "vreinterpretq_u64_s16", + "vreinterpretq_u64_s16", + "vreinterpretq_p8_s16", + "vreinterpretq_p8_s16", + "vreinterpretq_p16_s16", + "vreinterpretq_p16_s16", + "vreinterpret_f32_s32", + "vreinterpret_f32_s32", + "vreinterpret_s8_s32", + "vreinterpret_s8_s32", + "vreinterpret_s16_s32", + "vreinterpret_s16_s32", + "vreinterpret_s64_s32", + "vreinterpret_s64_s32", + "vreinterpret_u8_s32", + "vreinterpret_u8_s32", + "vreinterpret_u16_s32", + "vreinterpret_u16_s32", + "vreinterpret_u32_s32", + "vreinterpret_u32_s32", + "vreinterpret_u64_s32", + "vreinterpret_u64_s32", + "vreinterpret_p8_s32", + "vreinterpret_p8_s32", + "vreinterpret_p16_s32", + "vreinterpret_p16_s32", + "vreinterpretq_f32_s32", + "vreinterpretq_f32_s32", + "vreinterpretq_s8_s32", + "vreinterpretq_s8_s32", + "vreinterpretq_s16_s32", + "vreinterpretq_s16_s32", + "vreinterpretq_s64_s32", + "vreinterpretq_s64_s32", + "vreinterpretq_u8_s32", + "vreinterpretq_u8_s32", + "vreinterpretq_u16_s32", + "vreinterpretq_u16_s32", + "vreinterpretq_u32_s32", + "vreinterpretq_u32_s32", + "vreinterpretq_u64_s32", + "vreinterpretq_u64_s32", + "vreinterpretq_p8_s32", + "vreinterpretq_p8_s32", + "vreinterpretq_p16_s32", + "vreinterpretq_p16_s32", + "vreinterpret_f32_s64", + "vreinterpret_f32_s64", + "vreinterpret_s8_s64", + "vreinterpret_s8_s64", + "vreinterpret_s16_s64", + "vreinterpret_s16_s64", + "vreinterpret_s32_s64", + "vreinterpret_s32_s64", + "vreinterpret_u8_s64", + "vreinterpret_u8_s64", + "vreinterpret_u16_s64", + "vreinterpret_u16_s64", + "vreinterpret_u32_s64", + "vreinterpret_u32_s64", + "vreinterpret_u64_s64", + "vreinterpret_p8_s64", + "vreinterpret_p8_s64", + "vreinterpret_p16_s64", + "vreinterpret_p16_s64", + "vreinterpretq_f32_s64", + "vreinterpretq_f32_s64", + "vreinterpretq_s8_s64", + "vreinterpretq_s8_s64", + "vreinterpretq_s16_s64", + "vreinterpretq_s16_s64", + "vreinterpretq_s32_s64", + "vreinterpretq_s32_s64", + "vreinterpretq_u8_s64", + "vreinterpretq_u8_s64", + "vreinterpretq_u16_s64", + "vreinterpretq_u16_s64", + "vreinterpretq_u32_s64", + "vreinterpretq_u32_s64", + "vreinterpretq_u64_s64", + "vreinterpretq_u64_s64", + "vreinterpretq_p8_s64", + "vreinterpretq_p8_s64", + "vreinterpretq_p16_s64", + "vreinterpretq_p16_s64", + "vreinterpret_f32_u8", + "vreinterpret_f32_u8", + "vreinterpret_s8_u8", + "vreinterpret_s8_u8", + "vreinterpret_s16_u8", + "vreinterpret_s16_u8", + "vreinterpret_s32_u8", + "vreinterpret_s32_u8", + "vreinterpret_s64_u8", + "vreinterpret_s64_u8", + "vreinterpret_u16_u8", + "vreinterpret_u16_u8", + "vreinterpret_u32_u8", + "vreinterpret_u32_u8", + "vreinterpret_u64_u8", + "vreinterpret_u64_u8", + "vreinterpret_p8_u8", + "vreinterpret_p8_u8", + "vreinterpret_p16_u8", + "vreinterpret_p16_u8", + "vreinterpretq_f32_u8", + "vreinterpretq_f32_u8", + "vreinterpretq_s8_u8", + "vreinterpretq_s8_u8", + "vreinterpretq_s16_u8", + "vreinterpretq_s16_u8", + "vreinterpretq_s32_u8", + "vreinterpretq_s32_u8", + "vreinterpretq_s64_u8", + "vreinterpretq_s64_u8", + "vreinterpretq_u16_u8", + "vreinterpretq_u16_u8", + "vreinterpretq_u32_u8", + "vreinterpretq_u32_u8", + "vreinterpretq_u64_u8", + "vreinterpretq_u64_u8", + "vreinterpretq_p8_u8", + "vreinterpretq_p8_u8", + "vreinterpretq_p16_u8", + "vreinterpretq_p16_u8", + "vreinterpret_f32_u16", + "vreinterpret_f32_u16", + "vreinterpret_s8_u16", + "vreinterpret_s8_u16", + "vreinterpret_s16_u16", + "vreinterpret_s16_u16", + "vreinterpret_s32_u16", + "vreinterpret_s32_u16", + "vreinterpret_s64_u16", + "vreinterpret_s64_u16", + "vreinterpret_u8_u16", + "vreinterpret_u8_u16", + "vreinterpret_u32_u16", + "vreinterpret_u32_u16", + "vreinterpret_u64_u16", + "vreinterpret_u64_u16", + "vreinterpret_p8_u16", + "vreinterpret_p8_u16", + "vreinterpret_p16_u16", + "vreinterpret_p16_u16", + "vreinterpretq_f32_u16", + "vreinterpretq_f32_u16", + "vreinterpretq_s8_u16", + "vreinterpretq_s8_u16", + "vreinterpretq_s16_u16", + "vreinterpretq_s16_u16", + "vreinterpretq_s32_u16", + "vreinterpretq_s32_u16", + "vreinterpretq_s64_u16", + "vreinterpretq_s64_u16", + "vreinterpretq_u8_u16", + "vreinterpretq_u8_u16", + "vreinterpretq_u32_u16", + "vreinterpretq_u32_u16", + "vreinterpretq_u64_u16", + "vreinterpretq_u64_u16", + "vreinterpretq_p8_u16", + "vreinterpretq_p8_u16", + "vreinterpretq_p16_u16", + "vreinterpretq_p16_u16", + "vreinterpret_f32_u32", + "vreinterpret_f32_u32", + "vreinterpret_s8_u32", + "vreinterpret_s8_u32", + "vreinterpret_s16_u32", + "vreinterpret_s16_u32", + "vreinterpret_s32_u32", + "vreinterpret_s32_u32", + "vreinterpret_s64_u32", + "vreinterpret_s64_u32", + "vreinterpret_u8_u32", + "vreinterpret_u8_u32", + "vreinterpret_u16_u32", + "vreinterpret_u16_u32", + "vreinterpret_u64_u32", + "vreinterpret_u64_u32", + "vreinterpret_p8_u32", + "vreinterpret_p8_u32", + "vreinterpret_p16_u32", + "vreinterpret_p16_u32", + "vreinterpretq_f32_u32", + "vreinterpretq_f32_u32", + "vreinterpretq_s8_u32", + "vreinterpretq_s8_u32", + "vreinterpretq_s16_u32", + "vreinterpretq_s16_u32", + "vreinterpretq_s32_u32", + "vreinterpretq_s32_u32", + "vreinterpretq_s64_u32", + "vreinterpretq_s64_u32", + "vreinterpretq_u8_u32", + "vreinterpretq_u8_u32", + "vreinterpretq_u16_u32", + "vreinterpretq_u16_u32", + "vreinterpretq_u64_u32", + "vreinterpretq_u64_u32", + "vreinterpretq_p8_u32", + "vreinterpretq_p8_u32", + "vreinterpretq_p16_u32", + "vreinterpretq_p16_u32", + "vreinterpret_f32_u64", + "vreinterpret_f32_u64", + "vreinterpret_s8_u64", + "vreinterpret_s8_u64", + "vreinterpret_s16_u64", + "vreinterpret_s16_u64", + "vreinterpret_s32_u64", + "vreinterpret_s32_u64", + "vreinterpret_s64_u64", + "vreinterpret_u8_u64", + "vreinterpret_u8_u64", + "vreinterpret_u16_u64", + "vreinterpret_u16_u64", + "vreinterpret_u32_u64", + "vreinterpret_u32_u64", + "vreinterpret_p8_u64", + "vreinterpret_p8_u64", + "vreinterpret_p16_u64", + "vreinterpret_p16_u64", + "vreinterpretq_f32_u64", + "vreinterpretq_f32_u64", + "vreinterpretq_s8_u64", + "vreinterpretq_s8_u64", + "vreinterpretq_s16_u64", + "vreinterpretq_s16_u64", + "vreinterpretq_s32_u64", + "vreinterpretq_s32_u64", + "vreinterpretq_s64_u64", + "vreinterpretq_s64_u64", + "vreinterpretq_u8_u64", + "vreinterpretq_u8_u64", + "vreinterpretq_u16_u64", + "vreinterpretq_u16_u64", + "vreinterpretq_u32_u64", + "vreinterpretq_u32_u64", + "vreinterpretq_p8_u64", + "vreinterpretq_p8_u64", + "vreinterpretq_p16_u64", + "vreinterpretq_p16_u64", + "vreinterpret_f32_p8", + "vreinterpret_f32_p8", + "vreinterpret_s8_p8", + "vreinterpret_s8_p8", + "vreinterpret_s16_p8", + "vreinterpret_s16_p8", + "vreinterpret_s32_p8", + "vreinterpret_s32_p8", + "vreinterpret_s64_p8", + "vreinterpret_s64_p8", + "vreinterpret_u8_p8", + "vreinterpret_u8_p8", + "vreinterpret_u16_p8", + "vreinterpret_u16_p8", + "vreinterpret_u32_p8", + "vreinterpret_u32_p8", + "vreinterpret_u64_p8", + "vreinterpret_u64_p8", + "vreinterpret_p16_p8", + "vreinterpret_p16_p8", + "vreinterpretq_f32_p8", + "vreinterpretq_f32_p8", + "vreinterpretq_s8_p8", + "vreinterpretq_s8_p8", + "vreinterpretq_s16_p8", + "vreinterpretq_s16_p8", + "vreinterpretq_s32_p8", + "vreinterpretq_s32_p8", + "vreinterpretq_s64_p8", + "vreinterpretq_s64_p8", + "vreinterpretq_u8_p8", + "vreinterpretq_u8_p8", + "vreinterpretq_u16_p8", + "vreinterpretq_u16_p8", + "vreinterpretq_u32_p8", + "vreinterpretq_u32_p8", + "vreinterpretq_u64_p8", + "vreinterpretq_u64_p8", + "vreinterpretq_p16_p8", + "vreinterpretq_p16_p8", + "vreinterpret_f32_p16", + "vreinterpret_f32_p16", + "vreinterpret_s8_p16", + "vreinterpret_s8_p16", + "vreinterpret_s16_p16", + "vreinterpret_s16_p16", + "vreinterpret_s32_p16", + "vreinterpret_s32_p16", + "vreinterpret_s64_p16", + "vreinterpret_s64_p16", + "vreinterpret_u8_p16", + "vreinterpret_u8_p16", + "vreinterpret_u16_p16", + "vreinterpret_u16_p16", + "vreinterpret_u32_p16", + "vreinterpret_u32_p16", + "vreinterpret_u64_p16", + "vreinterpret_u64_p16", + "vreinterpret_p8_p16", + "vreinterpret_p8_p16", + "vreinterpretq_f32_p16", + "vreinterpretq_f32_p16", + "vreinterpretq_s8_p16", + "vreinterpretq_s8_p16", + "vreinterpretq_s16_p16", + "vreinterpretq_s16_p16", + "vreinterpretq_s32_p16", + "vreinterpretq_s32_p16", + "vreinterpretq_s64_p16", + "vreinterpretq_s64_p16", + "vreinterpretq_u8_p16", + "vreinterpretq_u8_p16", + "vreinterpretq_u16_p16", + "vreinterpretq_u16_p16", + "vreinterpretq_u32_p16", + "vreinterpretq_u32_p16", + "vreinterpretq_u64_p16", + "vreinterpretq_u64_p16", + "vreinterpretq_p8_p16", + "vreinterpretq_p8_p16", + "vreinterpretq_s8_p128", + "vreinterpretq_s8_p128", + "vreinterpretq_s16_p128", + "vreinterpretq_s16_p128", + "vreinterpretq_s32_p128", + "vreinterpretq_s32_p128", + "vreinterpretq_s64_p128", + "vreinterpretq_s64_p128", + "vreinterpretq_u8_p128", + "vreinterpretq_u8_p128", + "vreinterpretq_u16_p128", + "vreinterpretq_u16_p128", + "vreinterpretq_u32_p128", + "vreinterpretq_u32_p128", + "vreinterpretq_u64_p128", + "vreinterpretq_u64_p128", + "vreinterpretq_p8_p128", + "vreinterpretq_p8_p128", + "vreinterpretq_p16_p128", + "vreinterpretq_p16_p128", + "vreinterpretq_p64_p128", + "vreinterpretq_p64_p128", + "vreinterpret_p64_s8", + "vreinterpret_p64_s8", + "vreinterpretq_p128_s8", + "vreinterpretq_p128_s8", + "vreinterpretq_p64_s8", + "vreinterpretq_p64_s8", + "vreinterpret_p64_s16", + "vreinterpret_p64_s16", + "vreinterpretq_p128_s16", + "vreinterpretq_p128_s16", + "vreinterpretq_p64_s16", + "vreinterpretq_p64_s16", + "vreinterpret_p64_s32", + "vreinterpret_p64_s32", + "vreinterpretq_p128_s32", + "vreinterpretq_p128_s32", + "vreinterpretq_p64_s32", + "vreinterpretq_p64_s32", + "vreinterpretq_p128_s64", + "vreinterpretq_p128_s64", + "vreinterpret_p64_u8", + "vreinterpret_p64_u8", + "vreinterpretq_p128_u8", + "vreinterpretq_p128_u8", + "vreinterpretq_p64_u8", + "vreinterpretq_p64_u8", + "vreinterpret_p64_u16", + "vreinterpret_p64_u16", + "vreinterpretq_p128_u16", + "vreinterpretq_p128_u16", + "vreinterpretq_p64_u16", + "vreinterpretq_p64_u16", + "vreinterpret_p64_u32", + "vreinterpret_p64_u32", + "vreinterpretq_p128_u32", + "vreinterpretq_p128_u32", + "vreinterpretq_p64_u32", + "vreinterpretq_p64_u32", + "vreinterpretq_p128_u64", + "vreinterpretq_p128_u64", + "vreinterpret_p64_p8", + "vreinterpret_p64_p8", + "vreinterpretq_p128_p8", + "vreinterpretq_p128_p8", + "vreinterpretq_p64_p8", + "vreinterpretq_p64_p8", + "vreinterpret_p64_p16", + "vreinterpret_p64_p16", + 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"vusdotq_laneq_s32", + "vusdotq_laneq_s32", + "vusdot_s32", + "vusdotq_s32", + "vusmmlaq_s32", + "vuzp_f16", + "vuzpq_f16", + "vuzp_f32", + "vuzp_s32", + "vuzp_u32", + "vuzpq_f32", + "vuzp_s8", + "vuzpq_s8", + "vuzp_s16", + "vuzpq_s16", + "vuzpq_s32", + "vuzp_u8", + "vuzpq_u8", + "vuzp_u16", + "vuzpq_u16", + "vuzpq_u32", + "vuzp_p8", + "vuzpq_p8", + "vuzp_p16", + "vuzpq_p16", + "vzip_f16", + "vzipq_f16", + "vzip_f32", + "vzip_s32", + "vzip_u32", + "vzip_s8", + "vzip_s16", + "vzip_u8", + "vzip_u16", + "vzip_p8", + "vzip_p16", + "vzipq_f32", + "vzipq_s8", + "vzipq_s16", + "vzipq_s32", + "vzipq_u8", + "vzipq_u16", + "vzipq_u32", + "vzipq_p8", + "vzipq_p16", + "__rndr", + "__rndrrs", + "vcopy_laneq_f64", + "vcopy_laneq_f64", + "vcopy_laneq_s64", + "vcopy_laneq_s64", + "vcopy_laneq_u64", + "vcopy_laneq_u64", + "vcopy_laneq_p64", + "vcopy_laneq_p64", + "vget_high_f64", + "vget_high_f64", + "vget_high_p64", + "vget_high_p64", + "vget_low_f64", + "vget_low_f64", + "vget_low_p64", + "vget_low_p64", + "vgetq_lane_f64", + "vgetq_lane_f64", + "vaddl_high_s16", + "vaddl_high_s16", + "vaddl_high_s32", + "vaddl_high_s32", + "vaddl_high_s8", + "vaddl_high_s8", + "vaddl_high_u16", + "vaddl_high_u16", + "vaddl_high_u32", + "vaddl_high_u32", + "vaddl_high_u8", + "vaddl_high_u8", + "vget_high_f32", + "vget_high_f32", + "vget_high_p16", + "vget_high_p16", + "vget_high_p8", + "vget_high_p8", + "vget_high_s16", + "vget_high_s16", + "vget_high_s32", + "vget_high_s32", + "vget_high_s8", + "vget_high_s8", + "vget_high_u16", + "vget_high_u16", + "vget_high_u32", + "vget_high_u32", + "vget_high_u8", + "vget_high_u8", + "vget_high_s64", + "vget_high_s64", + "vget_high_u64", + "vget_high_u64", + "vget_lane_f32", + "vget_lane_f32", + "vget_lane_p16", + "vget_lane_p16", + "vget_lane_p8", + "vget_lane_p8", + "vget_lane_s16", + "vget_lane_s16", + "vget_lane_s32", + "vget_lane_s32", + "vget_lane_s8", + "vget_lane_s8", + "vget_lane_u16", + "vget_lane_u16", + "vget_lane_u32", + "vget_lane_u32", + "vget_lane_u8", + "vget_lane_u8", + "vgetq_lane_f32", + "vgetq_lane_f32", + "vgetq_lane_p16", + "vgetq_lane_p16", + "vgetq_lane_p64", + "vgetq_lane_p64", + "vgetq_lane_p8", + "vgetq_lane_p8", + "vgetq_lane_s16", + "vgetq_lane_s16", + "vgetq_lane_s32", + "vgetq_lane_s32", + "vgetq_lane_s64", + "vgetq_lane_s64", + "vgetq_lane_s8", + "vgetq_lane_s8", + "vgetq_lane_u16", + "vgetq_lane_u16", + "vgetq_lane_u32", + "vgetq_lane_u32", + "vgetq_lane_u8", + "vgetq_lane_u8", + "vget_lane_p64", + "vget_lane_s64", + "vget_lane_u64", + "vget_low_f32", + "vget_low_f32", + "vget_low_p16", + "vget_low_p16", + "vget_low_p8", + "vget_low_p8", + "vget_low_s16", + "vget_low_s16", + "vget_low_s32", + "vget_low_s32", + "vget_low_s8", + "vget_low_s8", + "vget_low_u16", + "vget_low_u16", + "vget_low_u32", + "vget_low_u32", + "vget_low_u8", + "vget_low_u8", + "vget_low_s64", + "vget_low_s64", + "vget_low_u64", + "vget_low_u64", + "vaddw_high_s16", + "vaddw_high_s32", + "vaddw_high_s8", + "vaddw_high_u16", + "vaddw_high_u32", + "vaddw_high_u8", + "vgetq_lane_u64", +]; diff --git a/stdarch/crates/stdarch-verify/tests/x86-intel.rs b/stdarch/crates/stdarch-verify/tests/x86-intel.rs index 7fc47be42e14b..024a873de16e4 100644 --- a/stdarch/crates/stdarch-verify/tests/x86-intel.rs +++ b/stdarch/crates/stdarch-verify/tests/x86-intel.rs @@ -214,7 +214,7 @@ fn verify_all_signatures() { "_m_prefetchrs", // CMPXCHG "cmpxchg16b", - // Undefined + // Undefined, "_mm_undefined_ps", "_mm_undefined_pd", "_mm_undefined_si128", @@ -250,9 +250,6 @@ fn verify_all_signatures() { "_mm_cvt_ss2si", "_mm_cvtt_ss2si", "_mm_cvt_si2ss", - "_mm_set_ps1", - "_mm_load_ps1", - "_mm_store_ps1", "_mm_bslli_si128", "_mm_bsrli_si128", "_bextr2_u32", diff --git a/stdarch/examples/gaussian.rs b/stdarch/examples/gaussian.rs index dea16f797aca6..f41f7539860b0 100644 --- a/stdarch/examples/gaussian.rs +++ b/stdarch/examples/gaussian.rs @@ -95,30 +95,30 @@ mod hvx { let below = *inp2.add(i); // Widen above + below to 16-bit using HvxVectorPair - // q6_wh_vadd_vubvub: adds two u8 vectors, producing u16 results in a pair - let above_plus_below: HvxVectorPair = q6_wh_vadd_vubvub(above, below); + // Q6_Wh_vadd_VubVub: adds two u8 vectors, producing u16 results in a pair + let above_plus_below: HvxVectorPair = Q6_Wh_vadd_VubVub(above, below); // Widen center * 2 (add center to itself) - let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(center, center); + let center_x2: HvxVectorPair = Q6_Wh_vadd_VubVub(center, center); // Add them: (above + below) + (center * 2) = above + 2*center + below - let sum: HvxVectorPair = q6_wh_vadd_whwh(above_plus_below, center_x2); + let sum: HvxVectorPair = Q6_Wh_vadd_WhWh(above_plus_below, center_x2); // Extract high and low vectors from the pair (each contains u16 values) - let sum_lo = q6_v_lo_w(sum); // Lower 64 elements as i16 - let sum_hi = q6_v_hi_w(sum); // Upper 64 elements as i16 + let sum_lo = Q6_V_lo_W(sum); // Lower 64 elements as i16 + let sum_hi = Q6_V_hi_W(sum); // Upper 64 elements as i16 // Arithmetic right shift by 2 (divide by 4) with rounding // Add 2 for rounding before shift: (sum + 2) >> 2 - let two = q6_vh_vsplat_r(2); - let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two); - let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two); - let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two); - let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two); + let two = Q6_Vh_vsplat_R(2); + let sum_lo_rounded = Q6_Vh_vadd_VhVh(sum_lo, two); + let sum_hi_rounded = Q6_Vh_vadd_VhVh(sum_hi, two); + let shifted_lo = Q6_Vh_vasr_VhVh(sum_lo_rounded, two); + let shifted_hi = Q6_Vh_vasr_VhVh(sum_hi_rounded, two); // Pack back to u8 with saturation: takes hi and lo halfword vectors, // saturates to u8, and interleaves them back to original order - let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo); + let result = Q6_Vub_vsat_VhVh(shifted_hi, shifted_lo); *outp.add(i) = result; } @@ -142,44 +142,44 @@ mod hvx { let outp = dst as *mut HvxVector; let n_chunks = width / VLEN; - let mut prev = q6_v_vzero(); + let mut prev = Q6_V_vzero(); for i in 0..n_chunks { let curr = *inp.add(i); let next = if i + 1 < n_chunks { *inp.add(i + 1) } else { - q6_v_vzero() + Q6_V_vzero() }; // Left neighbor (x-1): shift curr right by 1 byte, filling from prev - let left = q6_v_vlalign_vvr(curr, prev, 1); + let left = Q6_V_vlalign_VVR(curr, prev, 1); // Right neighbor (x+1): shift curr left by 1 byte, filling from next - let right = q6_v_valign_vvr(next, curr, 1); + let right = Q6_V_valign_VVR(next, curr, 1); // Widen left + right to 16-bit - let left_plus_right: HvxVectorPair = q6_wh_vadd_vubvub(left, right); + let left_plus_right: HvxVectorPair = Q6_Wh_vadd_VubVub(left, right); // Widen center * 2 - let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(curr, curr); + let center_x2: HvxVectorPair = Q6_Wh_vadd_VubVub(curr, curr); // Add: left + 2*center + right - let sum: HvxVectorPair = q6_wh_vadd_whwh(left_plus_right, center_x2); + let sum: HvxVectorPair = Q6_Wh_vadd_WhWh(left_plus_right, center_x2); // Extract high and low vectors - let sum_lo = q6_v_lo_w(sum); - let sum_hi = q6_v_hi_w(sum); + let sum_lo = Q6_V_lo_W(sum); + let sum_hi = Q6_V_hi_W(sum); // Arithmetic right shift by 2 with rounding - let two = q6_vh_vsplat_r(2); - let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two); - let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two); - let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two); - let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two); + let two = Q6_Vh_vsplat_R(2); + let sum_lo_rounded = Q6_Vh_vadd_VhVh(sum_lo, two); + let sum_hi_rounded = Q6_Vh_vadd_VhVh(sum_hi, two); + let shifted_lo = Q6_Vh_vasr_VhVh(sum_lo_rounded, two); + let shifted_hi = Q6_Vh_vasr_VhVh(sum_hi_rounded, two); // Pack back to u8 with saturation - let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo); + let result = Q6_Vub_vsat_VhVh(shifted_hi, shifted_lo); *outp.add(i) = result; @@ -296,13 +296,14 @@ fn main() { // Run reference gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref); - // Verify HVX matches reference (allowing small rounding differences) + // Verify HVX matches reference (allowing small rounding differences). + use core_arch::arch::hexagon::scalar::{Q6_R_abs_R, Q6_R_max_RR}; let mut max_diff = 0i32; for y in 1..HEIGHT - 1 { for x in 1..WIDTH - 1 { let idx = y * WIDTH + x; - let diff = (dst_hvx.0[idx] as i32 - dst_ref[idx] as i32).abs(); - max_diff = max_diff.max(diff); + let diff = unsafe { Q6_R_abs_R(dst_hvx.0[idx] as i32 - dst_ref[idx] as i32) }; + max_diff = unsafe { Q6_R_max_RR(max_diff, diff) }; // Allow up to 1 LSB difference due to rounding assert!( diff <= 1, diff --git a/stdarch/intrinsics_data/arm_intrinsics.json b/stdarch/intrinsics_data/arm_intrinsics.json index bce85d19a10f1..fab6da7f2c16c 100644 --- a/stdarch/intrinsics_data/arm_intrinsics.json +++ b/stdarch/intrinsics_data/arm_intrinsics.json @@ -224,21 +224,25 @@ ] }, { - "SIMD_ISA": "Neon", - "name": "vscale_f16", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s16]", "arguments": [ - "float16x4_t a", - "int16x4_t b" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "float16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -246,26 +250,34 @@ ], "instructions": [ [ - "FSCALE" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f16", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s32]", "arguments": [ - "float16x8_t a", - "int16x8_t b" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "float16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ @@ -273,26 +285,34 @@ ], "instructions": [ [ - "FSCALE" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscale_f32", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s64]", "arguments": [ - "float32x2_t a", - "int32x2_t b" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "float32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ @@ -300,26 +320,34 @@ ], "instructions": [ [ - "FSCALE" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f32", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s8]", "arguments": [ - "float32x4_t a", - "int32x4_t b" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "float32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -327,26 +355,34 @@ ], "instructions": [ [ - "FSCALE" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f64", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u16]", "arguments": [ - "float64x2_t a", - "int64x2_t b" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "float64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -354,228 +390,244 @@ ], "instructions": [ [ - "FSCALE" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_s16", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u32]", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x4_t c" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "int16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.4H" + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_s32", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u64]", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x2_t c" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "int32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.D" }, - "c": { - "register": "Vm.2S" + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_s8", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u8]", "arguments": [ - "int8x8_t a", - "int8x8_t b", - "int8x8_t c" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.8B" + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_u16", + "SIMD_ISA": "SVE2", + "name": "svaba[_s16]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.4H" + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_u32", + "SIMD_ISA": "SVE2", + "name": "svaba[_s32]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.2S" + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaba_u8", + "SIMD_ISA": "SVE2", + "name": "svaba[_s64]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" }, - "c": { - "register": "Vm.8B" + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_s16", + "SIMD_ISA": "SVE2", + "name": "svaba[_s8]", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t c" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "int32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.8H" + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -583,30 +635,34 @@ ], "instructions": [ [ - "SABAL2" + "SABA" + ], + [ + "MOVPRFX", + "SABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_s32", + "SIMD_ISA": "SVE2", + "name": "svaba[_u16]", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t c" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "int64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.4S" + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -614,30 +670,34 @@ ], "instructions": [ [ - "SABAL2" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_s8", + "SIMD_ISA": "SVE2", + "name": "svaba[_u32]", "arguments": [ - "int16x8_t a", - "int8x16_t b", - "int8x16_t c" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "int16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.16B" + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -645,30 +705,34 @@ ], "instructions": [ [ - "SABAL2" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_u16", + "SIMD_ISA": "SVE2", + "name": "svaba[_u64]", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16x8_t c" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" }, - "c": { - "register": "Vm.8H" + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -676,30 +740,34 @@ ], "instructions": [ [ - "UABAL2" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_u32", + "SIMD_ISA": "SVE2", + "name": "svaba[_u8]", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32x4_t c" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.4S" + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -707,30 +775,34 @@ ], "instructions": [ [ - "UABAL2" + "UABA" + ], + [ + "MOVPRFX", + "UABA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_high_u8", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s16]", "arguments": [ - "uint16x8_t a", - "uint8x16_t b", - "uint8x16_t c" + "svint16_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.16B" + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -738,479 +810,524 @@ ], "instructions": [ [ - "UABAL2" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_s16", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s32]", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t c" + "svint32_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "int32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.4H" + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABAL" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_s32", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s64]", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t c" + "svint64_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "int64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.2S" + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABAL" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_s8", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u16]", "arguments": [ - "int16x8_t a", - "int8x8_t b", - "int8x8_t c" + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.8B" + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABAL" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_u16", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u32]", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.4H" + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABAL" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_u32", + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u64]", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.2S" + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABAL" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabal_u8", + "SIMD_ISA": "SVE2", + "name": "svabalb[_s16]", "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.8B" + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABAL" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_s16", + "SIMD_ISA": "SVE2", + "name": "svabalb[_s32]", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "int16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.8H" + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_s32", + "SIMD_ISA": "SVE2", + "name": "svabalb[_s64]", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "int32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.4S" + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_s8", + "SIMD_ISA": "SVE2", + "name": "svabalb[_u16]", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "int8x16_t c" + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "int8x16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.16B" + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABA" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_u16", + "SIMD_ISA": "SVE2", + "name": "svabalb[_u32]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.8H" + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_u32", + "SIMD_ISA": "SVE2", + "name": "svabalb[_u64]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.4S" + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabaq_u8", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s16]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "uint8x16_t c" + "svint16_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" }, - "c": { - "register": "Vm.16B" + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABA" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_f16", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s32]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svint32_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "float16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_f32", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s64]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svint64_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "float32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_f64", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u16]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "float64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -1218,200 +1335,244 @@ ], "instructions": [ [ - "FABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_s16", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u32]", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "int16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_s32", + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u64]", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "int32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_s8", + "SIMD_ISA": "SVE2", + "name": "svabalt[_s16]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_u16", + "SIMD_ISA": "SVE2", + "name": "svabalt[_s32]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_u32", + "SIMD_ISA": "SVE2", + "name": "svabalt[_s64]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabd_u8", + "SIMD_ISA": "SVE2", + "name": "svabalt[_u16]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdd_f64", + "SIMD_ISA": "SVE2", + "name": "svabalt[_u32]", "arguments": [ - "float64_t a", - "float64_t b" + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "float64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -1419,26 +1580,34 @@ ], "instructions": [ [ - "FABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdh_f16", + "SIMD_ISA": "SVE2", + "name": "svabalt[_u64]", "arguments": [ - "float16_t a", - "float16_t b" + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "float16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -1446,26 +1615,34 @@ ], "instructions": [ [ - "FABD" + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_m", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -1473,26 +1650,34 @@ ], "instructions": [ [ - "SABDL2" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_x", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -1500,26 +1685,37 @@ ], "instructions": [ [ - "SABDL2" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_z", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -1527,26 +1723,35 @@ ], "instructions": [ [ - "SABDL2" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -1554,26 +1759,34 @@ ], "instructions": [ [ - "UABDL2" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -1581,26 +1794,37 @@ ], "instructions": [ [ - "UABDL2" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_high_u8", + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_z", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -1608,257 +1832,326 @@ ], "instructions": [ [ - "UABDL2" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_m", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABDL" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_x", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABDL" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_z", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABDL" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_m", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABDL" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_x", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABDL" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdl_u8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_z", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABDL" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_m", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_x", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_f64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_z", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -1866,200 +2159,253 @@ ], "instructions": [ [ + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_m", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_x", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_z", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SABD" + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabdq_u8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_z", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UABD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabds_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_m", "arguments": [ - "float32_t a", - "float32_t b" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "float32_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -2067,71 +2413,108 @@ ], "instructions": [ [ - "FABD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_x", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FABS" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_z", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FABS" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_f64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_m", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -2139,72 +2522,108 @@ ], "instructions": [ [ - "FABS" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_x", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_z", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" - ] - ] + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_m", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2212,47 +2631,72 @@ ], "instructions": [ [ - "ABS" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabs_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_x", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsd_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_z", "arguments": [ - "int64_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2260,95 +2704,144 @@ ], "instructions": [ [ - "ABS" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsh_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_m", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FABS" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_x", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FABS" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_z", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FABS" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_f64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_m", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -2356,72 +2849,108 @@ ], "instructions": [ [ - "FABS" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_x", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_z", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_m", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -2429,108 +2958,143 @@ ], "instructions": [ [ - "ABS" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vabsq_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_x", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ABS" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_z", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FADD" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_f32", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_m", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FADD" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_f64", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_x", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2538,345 +3102,435 @@ ], "instructions": [ [ - "FADD" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_p16", + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_z", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_p64", + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_m", "arguments": [ - "poly64x1_t a", - "poly64x1_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_p8", + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_x", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_z", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_m", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_x", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_s8", + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_z", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_m", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_x", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_u64", + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_z", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vadd_u8", + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_m", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddd_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_x", "arguments": [ - "int64_t a", - "int64_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "int64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2884,26 +3538,37 @@ ], "instructions": [ [ - "ADD" + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddd_u64", + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_z", "arguments": [ - "uint64_t a", - "uint64_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -2911,58 +3576,70 @@ ], "instructions": [ [ - "ADD" + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddh_f16", + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_m", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FADD" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_x", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H|Ztied2.H" }, - "r": { - "register": "Vd.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -2970,30 +3647,37 @@ ], "instructions": [ [ - "ADDHN2" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_z", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H" }, - "r": { - "register": "Vd.4H" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -3001,30 +3685,35 @@ ], "instructions": [ [ - "ADDHN2" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_m", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -3032,30 +3721,34 @@ ], "instructions": [ [ - "ADDHN2" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_x", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S|Ztied2.S" }, - "r": { - "register": "Vd.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -3063,30 +3756,37 @@ ], "instructions": [ [ - "ADDHN2" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_z", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" }, - "r": { - "register": "Vd.4H" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -3094,30 +3794,35 @@ ], "instructions": [ [ - "ADDHN2" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_high_u64", + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_m", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -3125,200 +3830,240 @@ ], "instructions": [ [ - "ADDHN2" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_s16", + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_x", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_s32", + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_z", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_s64", + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_m", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_u16", + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_x", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_u32", + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_z", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddhn_u64", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s16]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDHN" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_s16", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s32]", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -3326,26 +4071,26 @@ ], "instructions": [ [ - "SADDL2" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_s32", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s64]", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -3353,26 +4098,26 @@ ], "instructions": [ [ - "SADDL2" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_s8", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u16]", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -3380,26 +4125,26 @@ ], "instructions": [ [ - "SADDL2" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_u16", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u32]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -3407,26 +4152,26 @@ ], "instructions": [ [ - "UADDL2" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_u32", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u64]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -3434,26 +4179,26 @@ ], "instructions": [ [ - "UADDL2" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_high_u8", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s16]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -3461,196 +4206,188 @@ ], "instructions": [ [ - "UADDL2" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_s16", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s32]", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDL" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_s32", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s64]", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDL" + "SABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_s8", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u16]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDL" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_u16", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u32]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDL" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_u32", + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u64]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDL" + "UABDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddl_u8", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s16]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDL" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_s16", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s32]", "arguments": [ - "int16x4_t a" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -3658,22 +4395,26 @@ ], "instructions": [ [ - "SADDLV" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_s32", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s64]", "arguments": [ - "int32x2_t a" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "int64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -3681,22 +4422,26 @@ ], "instructions": [ [ - "SADDLP" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_s8", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u16]", "arguments": [ - "int8x8_t a" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -3704,22 +4449,26 @@ ], "instructions": [ [ - "SADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_u16", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u32]", "arguments": [ - "uint16x4_t a" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -3727,22 +4476,26 @@ ], "instructions": [ [ - "UADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_u32", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u64]", "arguments": [ - "uint32x2_t a" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -3750,22 +4503,26 @@ ], "instructions": [ [ - "UADDLP" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlv_u8", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s16]", "arguments": [ - "uint8x8_t a" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -3773,22 +4530,26 @@ ], "instructions": [ [ - "UADDLV" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_s16", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s32]", "arguments": [ - "int16x8_t a" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int32_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -3796,22 +4557,26 @@ ], "instructions": [ [ - "SADDLV" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_s32", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s64]", "arguments": [ - "int32x4_t a" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -3819,22 +4584,26 @@ ], "instructions": [ [ - "SADDLV" + "SABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_s8", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u16]", "arguments": [ - "int8x16_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "int16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -3842,22 +4611,26 @@ ], "instructions": [ [ - "SADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_u16", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u32]", "arguments": [ - "uint16x8_t a" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -3865,22 +4638,26 @@ ], "instructions": [ [ - "UADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_u32", + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u64]", "arguments": [ - "uint32x4_t a" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -3888,22 +4665,30 @@ ], "instructions": [ [ - "UADDLV" + "UABDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddlvq_u8", + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_m", "arguments": [ - "uint8x16_t a" + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "uint16_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -3911,83 +4696,93 @@ ], "instructions": [ [ - "UADDLV" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_f16", + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_x", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "float16x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.H|Ztied.H" }, - "b": { - "register": "Vm.8H" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FADD" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_f32", + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_z", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "float32x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Vm.4S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FADD" + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_f64", + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_m", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "inactive": { + "register": "Zinactive.S|Ztied.S" }, - "b": { - "register": "Vm.2D" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -3995,370 +4790,406 @@ ], "instructions": [ [ - "FADD" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_p128", + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_x", "arguments": [ - "poly128_t a", - "poly128_t b" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "poly128_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.S|Ztied.S" }, - "b": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_p16", + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_z", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "poly16x8_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.S" }, - "b": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_p64", + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_m", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "poly64x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.D|Ztied.D" }, - "b": { - "register": "Vm.16B" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_p8", + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_x", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "poly8x16_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.D|Ztied.D" }, - "b": { - "register": "Vm.16B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "FABS" + ], + [ + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_s16", + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_z", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Vm.8H" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "FABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_s32", + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_m", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "inactive": { + "register": "Zinactive.H|Ztied.H" }, - "b": { - "register": "Vm.4S" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_s64", + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_x", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.H|Ztied.H" }, - "b": { - "register": "Vm.2D" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_s8", + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_z", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_u16", + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "inactive": { + "register": "Zinactive.S|Ztied.S" }, - "b": { - "register": "Vm.8H" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_u32", + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op": { + "register": "Zop.S|Ztied.S" }, - "b": { - "register": "Vm.4S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_u64", + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_z", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.S" }, - "b": { - "register": "Vm.2D" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddq_u8", + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_m", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.D|Ztied.D" }, - "b": { - "register": "Vm.16B" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADD" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_f32", + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_x", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "float32_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4366,22 +5197,30 @@ ], "instructions": [ [ - "FADDP" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_s16", + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_z", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "int16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4389,22 +5228,31 @@ ], "instructions": [ [ - "ADDV" + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_s32", + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_m", "arguments": [ - "int32x2_t a" + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int32_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -4412,22 +5260,30 @@ ], "instructions": [ [ - "ADDP" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_s8", + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_x", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -4435,22 +5291,30 @@ ], "instructions": [ [ - "ADDV" + "ABS" + ], + [ + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_u16", + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_z", "arguments": [ - "uint16x4_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -4458,22 +5322,31 @@ ], "instructions": [ [ - "ADDV" + "MOVPRFX", + "ABS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_u32", + "SIMD_ISA": "SVE", + "name": "svacge[_f16]", "arguments": [ - "uint32x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4481,22 +5354,30 @@ ], "instructions": [ [ - "ADDP" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddv_u8", + "SIMD_ISA": "SVE", + "name": "svacge[_f32]", "arguments": [ - "uint8x8_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4504,22 +5385,30 @@ ], "instructions": [ [ - "ADDV" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_f32", + "SIMD_ISA": "SVE", + "name": "svacge[_f64]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4527,23 +5416,30 @@ ], "instructions": [ [ - "FADDP", - "FADDP" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_f64", + "SIMD_ISA": "SVE", + "name": "svacge[_n_f16]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "float64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4551,22 +5447,30 @@ ], "instructions": [ [ - "FADDP" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_s16", + "SIMD_ISA": "SVE", + "name": "svacge[_n_f32]", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4574,22 +5478,30 @@ ], "instructions": [ [ - "ADDV" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_s32", + "SIMD_ISA": "SVE", + "name": "svacge[_n_f64]", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4597,22 +5509,30 @@ ], "instructions": [ [ - "ADDV" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_s64", + "SIMD_ISA": "SVE", + "name": "svacgt[_f16]", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4620,22 +5540,30 @@ ], "instructions": [ [ - "ADDP" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_s8", + "SIMD_ISA": "SVE", + "name": "svacgt[_f32]", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4643,22 +5571,30 @@ ], "instructions": [ [ - "ADDV" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_u16", + "SIMD_ISA": "SVE", + "name": "svacgt[_f64]", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4666,22 +5602,30 @@ ], "instructions": [ [ - "ADDV" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_u32", + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f16]", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4689,22 +5633,30 @@ ], "instructions": [ [ - "ADDV" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_u64", + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f32]", "arguments": [ - "uint64x2_t a" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4712,22 +5664,30 @@ ], "instructions": [ [ - "ADDP" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddvq_u8", + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f64]", "arguments": [ - "uint8x16_t a" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4735,26 +5695,30 @@ ], "instructions": [ [ - "ADDV" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_s16", + "SIMD_ISA": "SVE", + "name": "svacle[_f16]", "arguments": [ - "int32x4_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4762,26 +5726,30 @@ ], "instructions": [ [ - "SADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_s32", + "SIMD_ISA": "SVE", + "name": "svacle[_f32]", "arguments": [ - "int64x2_t a", - "int32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4789,26 +5757,30 @@ ], "instructions": [ [ - "SADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_s8", + "SIMD_ISA": "SVE", + "name": "svacle[_f64]", "arguments": [ - "int16x8_t a", - "int8x16_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4816,26 +5788,30 @@ ], "instructions": [ [ - "SADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_u16", + "SIMD_ISA": "SVE", + "name": "svacle[_n_f16]", "arguments": [ - "uint32x4_t a", - "uint16x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -4843,26 +5819,30 @@ ], "instructions": [ [ - "UADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_u32", + "SIMD_ISA": "SVE", + "name": "svacle[_n_f32]", "arguments": [ - "uint64x2_t a", - "uint32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -4870,26 +5850,30 @@ ], "instructions": [ [ - "UADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_high_u8", + "SIMD_ISA": "SVE", + "name": "svacle[_n_f64]", "arguments": [ - "uint16x8_t a", - "uint8x16_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -4897,1518 +5881,1906 @@ ], "instructions": [ [ - "UADDW2" + "FACGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_s16", + "SIMD_ISA": "SVE", + "name": "svaclt[_f16]", "arguments": [ - "int32x4_t a", - "int16x4_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_s32", + "SIMD_ISA": "SVE", + "name": "svaclt[_f32]", "arguments": [ - "int64x2_t a", - "int32x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_s8", + "SIMD_ISA": "SVE", + "name": "svaclt[_f64]", "arguments": [ - "int16x8_t a", - "int8x8_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_u16", + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f16]", "arguments": [ - "uint32x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_u32", + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f32]", "arguments": [ - "uint64x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaddw_u8", + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f64]", "arguments": [ - "uint16x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDW" + "FACGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaesdq_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_m", "arguments": [ - "uint8x16_t data", - "uint8x16_t key" + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "data": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "key": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "AESD" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaeseq_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_x", "arguments": [ - "uint8x16_t data", - "uint8x16_t key" + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "data": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "key": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "AESE" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaesimcq_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_z", "arguments": [ - "uint8x16_t data" + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "data": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "AESIMC" + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vaesmcq_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_m", "arguments": [ - "uint8x16_t data" + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "data": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "AESMC" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_s16", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_x", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_s32", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_z", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_s64", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_m", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_s8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_x", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_u16", + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_z", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "SADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_u32", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_m", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_u64", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_x", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vand_u8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_z", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_s16", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_m", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_s32", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_x", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_s64", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_z", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_s8", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u64]_m", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vandq_u16", + "SIMD_ISA": "SVE2", + "name": "svadalp[_u64]_x", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "AND" + "UADALP" + ], + [ + "MOVPRFX", + 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"MOVPRFX", + "FADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbicq_s64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_f32]_m", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Ztied1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BIC" + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbicq_s8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_f32]_x", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": 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"FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f64]_m", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Ztied1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BIC" + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbicq_u64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_f64]_x", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BIC" + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbicq_u8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_f64]_z", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BIC" + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_m", "arguments": [ - "uint16x4_t a", - "float16x4_t b", - "float16x4_t c" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_x", "arguments": [ - "uint32x2_t a", - "float32x2_t b", - "float32x2_t c" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_z", "arguments": [ - "uint64x1_t a", - "float64x1_t b", - "float64x1_t c" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -6416,458 +7788,526 @@ ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_p16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_m", "arguments": [ - "uint16x4_t a", - "poly16x4_t b", - "poly16x4_t c" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_p64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_x", "arguments": [ - "poly64x1_t a", - "poly64x1_t b", - "poly64x1_t c" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_p8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_z", "arguments": [ - "uint8x8_t a", - "poly8x8_t b", - "poly8x8_t c" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_s16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_m", "arguments": [ - "uint16x4_t a", - "int16x4_t b", - "int16x4_t c" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_s32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_x", "arguments": [ - "uint32x2_t a", - "int32x2_t b", - "int32x2_t c" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_s64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_z", "arguments": [ - "uint64x1_t a", - "int64x1_t b", - "int64x1_t c" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_s8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_m", "arguments": [ - "uint8x8_t a", - "int8x8_t b", - "int8x8_t c" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_u16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_x", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_u32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_z", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_u64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_m", "arguments": [ - "uint64x1_t a", - "uint64x1_t b", - "uint64x1_t c" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbsl_u8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_x", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" }, - "c": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_z", "arguments": [ - "uint16x8_t a", - "float16x8_t b", - "float16x8_t c" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.H[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_m", "arguments": [ - "uint32x4_t a", - "float32x4_t b", - "float32x4_t c" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_x", "arguments": [ - "uint64x2_t a", - "float64x2_t b", - "float64x2_t c" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -6875,556 +8315,665 @@ ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_p16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_z", "arguments": [ - "uint16x8_t a", - "poly16x8_t b", - "poly16x8_t c" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "poly16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_p64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_m", "arguments": [ - "poly64x2_t a", - "poly64x2_t b", - "poly64x2_t c" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "poly64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_p8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_x", "arguments": [ - "uint8x16_t a", - "poly8x16_t b", - "poly8x16_t c" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "poly8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_s16", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_z", "arguments": [ - "uint16x8_t a", - "int16x8_t b", - "int16x8_t c" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_s32", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_m", "arguments": [ - "uint32x4_t a", - "int32x4_t b", - "int32x4_t c" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_s64", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_x", "arguments": [ - "uint64x2_t a", - "int64x2_t b", - "int64x2_t c" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_s8", + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_z", "arguments": [ - "uint8x16_t a", - "int8x16_t b", - "int8x16_t c" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B[*]" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_u16", + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_u32", + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.H|Ztied2.H" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_u64", + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_z", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "uint64x2_t c" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.H" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vbslq_u8", + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_m", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "uint8x16_t c" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S" }, - "c": { - "register": "Vm.16B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "BSL" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcadd_rot270_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_x", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H " + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcadd_rot270_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_z", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S " + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcadd_rot90_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_m", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H " + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcadd_rot90_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_x", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S " + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot270_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_z", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H " + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot270_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_m", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S " + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot270_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_x", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D " + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -7432,82 +8981,107 @@ ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot90_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_z", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H " + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot90_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_m", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S " + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaddq_rot90_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_x", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D " + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -7515,83 +9089,107 @@ ], "instructions": [ [ - "FCADD" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcage_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_z", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGE" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcage_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_m", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcage_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_x", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -7599,26 +9197,36 @@ ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaged_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_z", "arguments": [ - "float64_t a", - "float64_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -7626,26 +9234,35 @@ ], "instructions": [ [ - "FACGE" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcageh_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_m", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -7653,83 +9270,107 @@ ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcageq_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_x", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcageq_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_z", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGE" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcageq_f64", + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_m", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -7737,26 +9378,34 @@ ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcages_f32", + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_x", "arguments": [ - "float32_t a", - "float32_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -7764,83 +9413,103 @@ ], "instructions": [ [ - "FACGE" + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagt_f16", + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_z", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGT" + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagt_f32", + "SIMD_ISA": "SVE", + "name": "svadda[_f16]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "float16_t initial", + "svfloat16_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "initial": { + "register": "Htied" }, - "b": { - "register": "Vm.2S" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGT" + "FADDA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagt_f64", + "SIMD_ISA": "SVE", + "name": "svadda[_f32]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "float32_t initial", + "svfloat32_t op" ], "return_type": { - "value": "uint64x1_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "initial": { + "register": "Stied" }, - "b": { - "register": "Dm" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -7848,26 +9517,30 @@ ], "instructions": [ [ - "FACGT" + "FADDA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagtd_f64", + "SIMD_ISA": "SVE", + "name": "svadda[_f64]", "arguments": [ - "float64_t a", - "float64_t b" + "svbool_t pg", + "float64_t initial", + "svfloat64_t op" ], "return_type": { - "value": "uint64_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "initial": { + "register": "Dtied" }, - "b": { - "register": "Dm" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -7875,26 +9548,26 @@ ], "instructions": [ [ - "FACGT" + "FADDA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagth_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s16]", "arguments": [ - "float16_t a", - "float16_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -7902,83 +9575,80 @@ ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagtq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagtq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagtq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -7986,26 +9656,26 @@ ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcagts_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u32]", "arguments": [ - "float32_t a", - "float32_t b" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -8013,83 +9683,80 @@ ], "instructions": [ [ - "FACGT" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcale_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u64]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcale_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s16]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcale_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s32]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -8097,26 +9764,26 @@ ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaled_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s64]", "arguments": [ - "float64_t a", - "float64_t b" + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -8124,26 +9791,26 @@ ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaleh_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u16]", "arguments": [ - "float16_t a", - "float16_t b" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -8151,83 +9818,84 @@ ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaleq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaleq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGE" + "ADDHNB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaleq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svint8_t even", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "even": { + "register": "Ztied.B" }, - "b": { - "register": "Vm.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -8235,26 +9903,30 @@ ], "instructions": [ [ - "FACGE" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcales_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s32]", "arguments": [ - "float32_t a", - "float32_t b" + "svint16_t even", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "even": { + "register": "Ztied.H" }, - "b": { - "register": "Sm" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -8262,83 +9934,92 @@ ], "instructions": [ [ - "FACGE" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalt_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s64]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svint32_t even", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "even": { + "register": "Ztied.S" }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalt_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u16]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svuint8_t even", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "even": { + "register": "Ztied.B" }, - "b": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalt_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u32]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svuint16_t even", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "even": { + "register": "Ztied.H" }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -8346,26 +10027,30 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaltd_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u64]", "arguments": [ - "float64_t a", - "float64_t b" + "svuint32_t even", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "even": { + "register": "Ztied.S" }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ @@ -8373,26 +10058,30 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalth_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s16]", "arguments": [ - "float16_t a", - "float16_t b" + "svint8_t even", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "even": { + "register": "Ztied.B" }, - "b": { - "register": "Hm" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -8400,83 +10089,92 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaltq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svint16_t even", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "even": { + "register": "Ztied.H" }, - "b": { - "register": "Vm.8H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaltq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svint32_t even", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "even": { + "register": "Ztied.S" }, - "b": { - "register": "Vm.4S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcaltq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svuint8_t even", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "even": { + "register": "Ztied.B" }, - "b": { - "register": "Vm.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -8484,26 +10182,30 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcalts_f32", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u32]", "arguments": [ - "float32_t a", - "float32_t b" + "svuint16_t even", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "even": { + "register": "Ztied.H" }, - "b": { - "register": "Sm" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -8511,83 +10213,84 @@ ], "instructions": [ [ - "FACGT" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u64]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svuint32_t even", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "even": { + "register": "Ztied.S" }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "ADDHNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s16]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s32]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -8595,141 +10298,134 @@ ], "instructions": [ [ - "FCMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_p64", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s64]", "arguments": [ - "poly64x1_t a", - "poly64x1_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_p8", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u16]", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_s16", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u32]", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_s32", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u64]", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_s64", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s16]", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -8737,113 +10433,107 @@ ], "instructions": [ [ - "CMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_s8", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s32]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_u16", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s64]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_u32", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u16]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_u64", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u32]", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -8851,55 +10541,53 @@ ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceq_u8", + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u64]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqd_f64", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s16]", "arguments": [ - "float64_t a", - "float64_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -8907,26 +10595,26 @@ ], "instructions": [ [ - "FCMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqd_s64", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s32]", "arguments": [ - "int64_t a", - "int64_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -8934,26 +10622,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqd_u64", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s64]", "arguments": [ - "uint64_t a", - "uint64_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -8961,26 +10649,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqh_f16", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s16]", "arguments": [ - "float16_t a", - "float16_t b" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -8988,83 +10676,80 @@ ], "instructions": [ [ - "FCMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "SADDLBT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -9072,141 +10757,134 @@ ], "instructions": [ [ - "FCMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_p64", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s32]", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_p8", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s64]", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_s16", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u16]", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_s32", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u32]", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_s64", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u64]", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -9214,113 +10892,107 @@ ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_s8", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s16]", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_u16", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s32]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_u32", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s64]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "SADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_u64", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u16]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -9328,55 +11000,53 @@ ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqq_u8", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u32]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqs_f32", + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u64]", "arguments": [ - "float32_t a", - "float32_t b" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -9384,46 +11054,65 @@ ], "instructions": [ [ - "FCMEQ" + "UADDLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_f16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f16]_m", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_f32", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f16]_x", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9431,22 +11120,34 @@ ], "instructions": [ [ - "FCMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_f64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f32]_m", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9454,46 +11155,69 @@ ], "instructions": [ [ - "FCMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_p64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f32]_x", "arguments": [ - "poly64x1_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_p8", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f64]_m", "arguments": [ - "poly8x8_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9501,22 +11225,34 @@ ], "instructions": [ [ - "CMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_s16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_f64]_x", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9524,22 +11260,34 @@ ], "instructions": [ [ - "CMEQ" + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_s32", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s16]_m", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9547,22 +11295,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_s64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s16]_x", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9570,22 +11330,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_s8", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s32]_m", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9593,22 +11365,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_u16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s32]_x", "arguments": [ - "uint16x4_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9616,22 +11400,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_u32", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s64]_m", "arguments": [ - "uint32x2_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9639,22 +11435,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_u64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s64]_x", "arguments": [ - "uint64x1_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9662,22 +11470,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqz_u8", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s8]_m", "arguments": [ - "uint8x8_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -9685,22 +11505,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzd_f64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_s8]_x", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -9708,22 +11540,34 @@ ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzd_s64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u16]_m", "arguments": [ - "int64_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9731,22 +11575,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzd_u64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u16]_x", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9754,22 +11610,34 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzh_f16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u32]_m", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9777,46 +11645,69 @@ ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u32]_x", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u64]_m", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9824,22 +11715,34 @@ ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u64]_x", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9847,46 +11750,69 @@ ], "instructions": [ [ - "FCMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_p64", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u8]_m", "arguments": [ - "poly64x2_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_p8", + "SIMD_ISA": "SVE2", + "name": "svaddp[_u8]_x", "arguments": [ - "poly8x16_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -9894,22 +11820,30 @@ ], "instructions": [ [ - "CMEQ" + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_s16", + "SIMD_ISA": "SVE", + "name": "svaddv[_f16]", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9917,22 +11851,26 @@ ], "instructions": [ [ - "CMEQ" + "FADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_s32", + "SIMD_ISA": "SVE", + "name": "svaddv[_f32]", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -9940,22 +11878,26 @@ ], "instructions": [ [ - "CMEQ" + "FADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_s64", + "SIMD_ISA": "SVE", + "name": "svaddv[_f64]", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -9963,22 +11905,26 @@ ], "instructions": [ [ - "CMEQ" + "FADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_s8", + "SIMD_ISA": "SVE", + "name": "svaddv[_s16]", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -9986,22 +11932,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_u16", + "SIMD_ISA": "SVE", + "name": "svaddv[_s32]", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -10009,22 +11959,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_u32", + "SIMD_ISA": "SVE", + "name": "svaddv[_s64]", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -10032,22 +11986,26 @@ ], "instructions": [ [ - "CMEQ" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_u64", + "SIMD_ISA": "SVE", + "name": "svaddv[_s8]", "arguments": [ - "uint64x2_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -10055,22 +12013,26 @@ ], "instructions": [ [ - "CMEQ" + "SADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzq_u8", + "SIMD_ISA": "SVE", + "name": "svaddv[_u16]", "arguments": [ - "uint8x16_t a" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -10078,22 +12040,26 @@ ], "instructions": [ [ - "CMEQ" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vceqzs_f32", + "SIMD_ISA": "SVE", + "name": "svaddv[_u32]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint32_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -10101,83 +12067,80 @@ ], "instructions": [ [ - "FCMEQ" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_f16", + "SIMD_ISA": "SVE", + "name": "svaddv[_u64]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Vm.4H" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_f32", + "SIMD_ISA": "SVE", + "name": "svaddv[_u8]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op": { + "register": "Zop.B" }, - "b": { - "register": "Vm.2S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "UADDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_f64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s16]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svint16_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -10185,84 +12148,80 @@ ], "instructions": [ [ - "FCMGE" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_s16", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s32]", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svint32_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_s32", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s64]", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svint64_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_s64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u16]", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svuint16_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -10270,113 +12229,107 @@ ], "instructions": [ [ - "CMGE" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_s8", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u32]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svuint32_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_u16", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u64]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svuint64_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_u32", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s16]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_u64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s32]", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -10384,55 +12337,53 @@ ], "instructions": [ [ - "CMHS" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcge_u8", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s64]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "SADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcged_f64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u16]", "arguments": [ - "float64_t a", - "float64_t b" + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -10440,26 +12391,26 @@ ], "instructions": [ [ - "FCMGE" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcged_s64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u32]", "arguments": [ - "int64_t a", - "int64_t b" + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -10467,26 +12418,26 @@ ], "instructions": [ [ - "CMGE" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcged_u64", + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u64]", "arguments": [ - "uint64_t a", - "uint64_t b" + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -10494,26 +12445,26 @@ ], "instructions": [ [ - "CMHS" + "UADDWB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeh_f16", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s16]", "arguments": [ - "float16_t a", - "float16_t b" + "svint16_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -10521,83 +12472,80 @@ ], "instructions": [ [ - "FCMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_f16", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svint32_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_f32", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svint64_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_f64", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svuint16_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -10605,84 +12553,80 @@ ], "instructions": [ [ - "FCMGE" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_s16", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u32]", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svuint32_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_s32", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u64]", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svuint64_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_s64", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s16]", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svint16_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -10690,113 +12634,107 @@ ], "instructions": [ [ - "CMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_s8", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s32]", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svint32_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_u16", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s64]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svint64_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "SADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_u32", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u16]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svuint16_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_u64", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u32]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svuint32_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -10804,55 +12742,53 @@ ], "instructions": [ [ - "CMHS" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgeq_u8", + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u64]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svuint64_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "UADDWT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcges_f32", + "SIMD_ISA": "SVE", + "name": "svadrb[_u32base]_[s32]offset", "arguments": [ - "float32_t a", - "float32_t b" + "svuint32_t bases", + "svint32_t offsets" ], "return_type": { - "value": "uint32_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "bases": { + "register": "Zbases.S" }, - "b": { - "register": "Sm" + "offsets": { + "register": "Zoffsets.S" } }, "Architectures": [ @@ -10860,46 +12796,53 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_f16", + "SIMD_ISA": "SVE", + "name": "svadrb[_u32base]_[u32]offset", "arguments": [ - "float16x4_t a" + "svuint32_t bases", + "svuint32_t offsets" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "bases": { + "register": "Zbases.S" + }, + "offsets": { + "register": "Zoffsets.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_f32", + "SIMD_ISA": "SVE", + "name": "svadrb[_u64base]_[s64]offset", "arguments": [ - "float32x2_t a" + "svuint64_t bases", + "svint64_t offsets" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "bases": { + "register": "Zbases.D" + }, + "offsets": { + "register": "Zoffsets.D" } }, "Architectures": [ @@ -10907,22 +12850,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_f64", + "SIMD_ISA": "SVE", + "name": "svadrb[_u64base]_[u64]offset", "arguments": [ - "float64x1_t a" + "svuint64_t bases", + "svuint64_t offsets" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "bases": { + "register": "Zbases.D" + }, + "offsets": { + "register": "Zoffsets.D" } }, "Architectures": [ @@ -10930,22 +12877,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_s16", + "SIMD_ISA": "SVE", + "name": "svadrd[_u32base]_[s32]index", "arguments": [ - "int16x4_t a" + "svuint32_t bases", + "svint32_t indices" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -10953,22 +12904,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_s32", + "SIMD_ISA": "SVE", + "name": "svadrd[_u32base]_[u32]index", "arguments": [ - "int32x2_t a" + "svuint32_t bases", + "svuint32_t indices" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -10976,22 +12931,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_s64", + "SIMD_ISA": "SVE", + "name": "svadrd[_u64base]_[s64]index", "arguments": [ - "int64x1_t a" + "svuint64_t bases", + "svint64_t indices" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -10999,22 +12958,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgez_s8", + "SIMD_ISA": "SVE", + "name": "svadrd[_u64base]_[u64]index", "arguments": [ - "int8x8_t a" + "svuint64_t bases", + "svuint64_t indices" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -11022,22 +12985,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezd_f64", + "SIMD_ISA": "SVE", + "name": "svadrh[_u32base]_[s32]index", "arguments": [ - "float64_t a" + "svuint32_t bases", + "svint32_t indices" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -11045,22 +13012,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezd_s64", + "SIMD_ISA": "SVE", + "name": "svadrh[_u32base]_[u32]index", "arguments": [ - "int64_t a" + "svuint32_t bases", + "svuint32_t indices" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -11068,22 +13039,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezh_f16", + "SIMD_ISA": "SVE", + "name": "svadrh[_u64base]_[s64]index", "arguments": [ - "float16_t a" + "svuint64_t bases", + "svint64_t indices" ], "return_type": { - "value": "uint16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -11091,46 +13066,53 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_f16", + "SIMD_ISA": "SVE", + "name": "svadrh[_u64base]_[u64]index", "arguments": [ - "float16x8_t a" + "svuint64_t bases", + "svuint64_t indices" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_f32", + "SIMD_ISA": "SVE", + "name": "svadrw[_u32base]_[s32]index", "arguments": [ - "float32x4_t a" + "svuint32_t bases", + "svint32_t indices" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -11138,22 +13120,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_f64", + "SIMD_ISA": "SVE", + "name": "svadrw[_u32base]_[u32]index", "arguments": [ - "float64x2_t a" + "svuint32_t bases", + "svuint32_t indices" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" } }, "Architectures": [ @@ -11161,22 +13147,26 @@ ], "instructions": [ [ - "FCMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_s16", + "SIMD_ISA": "SVE", + "name": "svadrw[_u64base]_[s64]index", "arguments": [ - "int16x8_t a" + "svuint64_t bases", + "svint64_t indices" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -11184,22 +13174,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_s32", + "SIMD_ISA": "SVE", + "name": "svadrw[_u64base]_[u64]index", "arguments": [ - "int32x4_t a" + "svuint64_t bases", + "svuint64_t indices" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" } }, "Architectures": [ @@ -11207,22 +13201,26 @@ ], "instructions": [ [ - "CMGE" + "ADR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_s64", + "SIMD_ISA": "SVE2", + "name": "svaesd[_u8]", "arguments": [ - "int64x2_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" } }, "Architectures": [ @@ -11230,22 +13228,29 @@ ], "instructions": [ [ - "CMGE" + "AESD" + ], + [ + "AESD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezq_s8", + "SIMD_ISA": "SVE2", + "name": "svaese[_u8]", "arguments": [ - "int8x16_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" } }, "Architectures": [ @@ -11253,22 +13258,25 @@ ], "instructions": [ [ - "CMGE" + "AESE" + ], + [ + "AESE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgezs_f32", + "SIMD_ISA": "SVE2", + "name": "svaesimc[_u8]", "arguments": [ - "float32_t a" + "svuint8_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op": { + "register": "Ztied.B" } }, "Architectures": [ @@ -11276,83 +13284,84 @@ ], "instructions": [ [ - "FCMGE" + "AESIMC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_f16", + "SIMD_ISA": "SVE2", + "name": "svaesmc[_u8]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svuint8_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "op": { + "register": "Ztied.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "AESMC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_f32", + "SIMD_ISA": "SVE", + "name": "svand[_b]_z", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Pop1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_f64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_m", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Ztied1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -11360,84 +13369,113 @@ ], "instructions": [ [ - "FCMGT" + "UXTB" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_s16", + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_x", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_s32", + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_z", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_s64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_m", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -11445,113 +13483,160 @@ ], "instructions": [ [ - "CMGT" + "UXTB" + ], + [ + "UXTH" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_s8", + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_x", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_u16", + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_z", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_u32", + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_m", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Ztied1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "UXTB" + ], + [ + "UXTH" + ], + [ + "UXTW" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_u64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_x", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -11559,55 +13644,87 @@ ], "instructions": [ [ - "CMHI" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgt_u8", + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_z", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "UXTW" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtd_f64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_m", "arguments": [ - "float64_t a", - "float64_t b" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -11615,26 +13732,34 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtd_s64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_x", "arguments": [ - "int64_t a", - "int64_t b" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -11642,26 +13767,39 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtd_u64", + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_z", "arguments": [ - "uint64_t a", - "uint64_t b" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -11669,26 +13807,35 @@ ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgth_f16", + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_m", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Ztied1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -11696,83 +13843,113 @@ ], "instructions": [ [ - "FCMGT" + "UXTB" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_f16", + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_x", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_f32", + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_z", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_f64", + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_m", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Ztied1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -11780,84 +13957,120 @@ ], "instructions": [ [ - "FCMGT" + "UXTB" + ], + [ + "UXTH" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_s16", + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_x", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_s32", + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_z", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_s64", + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_m", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -11865,113 +14078,162 @@ ], "instructions": [ [ - "CMGT" + "UXTB" + ], + [ + "UXTH" + ], + [ + "UXTW" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_s8", + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_x", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_u16", + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_z", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "UXTW" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_u32", + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_m", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_u64", + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_x", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -11979,55 +14241,75 @@ ], "instructions": [ [ - "CMHI" + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtq_u8", + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_z", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgts_f32", + "SIMD_ISA": "SVE", + "name": "svand[_s16]_m", "arguments": [ - "float32_t a", - "float32_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12035,46 +14317,71 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_f16", + "SIMD_ISA": "SVE", + "name": "svand[_s16]_x", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_f32", + "SIMD_ISA": "SVE", + "name": "svand[_s16]_z", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12082,22 +14389,35 @@ ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_f64", + "SIMD_ISA": "SVE", + "name": "svand[_s32]_m", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12105,22 +14425,34 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_s16", + "SIMD_ISA": "SVE", + "name": "svand[_s32]_x", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12128,22 +14460,36 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_s32", + "SIMD_ISA": "SVE", + "name": "svand[_s32]_z", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12151,22 +14497,35 @@ ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_s64", + "SIMD_ISA": "SVE", + "name": "svand[_s64]_m", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12174,22 +14533,34 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtz_s8", + "SIMD_ISA": "SVE", + "name": "svand[_s64]_x", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12197,22 +14568,36 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzd_f64", + "SIMD_ISA": "SVE", + "name": "svand[_s64]_z", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12220,22 +14605,35 @@ ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzd_s64", + "SIMD_ISA": "SVE", + "name": "svand[_s8]_m", "arguments": [ - "int64_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -12243,22 +14641,34 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzh_f16", + "SIMD_ISA": "SVE", + "name": "svand[_s8]_x", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -12266,46 +14676,72 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_f16", + "SIMD_ISA": "SVE", + "name": "svand[_s8]_z", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_f32", + "SIMD_ISA": "SVE", + "name": "svand[_u16]_m", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12313,22 +14749,34 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_f64", + "SIMD_ISA": "SVE", + "name": "svand[_u16]_x", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12336,22 +14784,36 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_s16", + "SIMD_ISA": "SVE", + "name": "svand[_u16]_z", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12359,22 +14821,35 @@ ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_s32", + "SIMD_ISA": "SVE", + "name": "svand[_u32]_m", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12382,22 +14857,34 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_s64", + "SIMD_ISA": "SVE", + "name": "svand[_u32]_x", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12405,22 +14892,36 @@ ], "instructions": [ [ - "CMGT" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzq_s8", + "SIMD_ISA": "SVE", + "name": "svand[_u32]_z", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12428,22 +14929,35 @@ ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcgtzs_f32", + "SIMD_ISA": "SVE", + "name": "svand[_u64]_m", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12451,83 +14965,107 @@ ], "instructions": [ [ - "FCMGT" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_f16", + "SIMD_ISA": "SVE", + "name": "svand[_u64]_x", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_f32", + "SIMD_ISA": "SVE", + "name": "svand[_u64]_z", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGE" - ] - ] + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_f64", + "SIMD_ISA": "SVE", + "name": "svand[_u8]_m", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -12535,84 +15073,103 @@ ], "instructions": [ [ - "FCMGE" + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_s16", + "SIMD_ISA": "SVE", + "name": "svand[_u8]_x", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "AND" + ], + [ + "AND" + ], + [ + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_s32", + "SIMD_ISA": "SVE", + "name": "svand[_u8]_z", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_s64", + "SIMD_ISA": "SVE", + "name": "svandv[_s16]", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint64x1_t" + "value": "int16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Dm" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12620,113 +15177,107 @@ ], "instructions": [ [ - "CMGE" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_s8", + "SIMD_ISA": "SVE", + "name": "svandv[_s32]", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.S" }, - "b": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_u16", + "SIMD_ISA": "SVE", + "name": "svandv[_s64]", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Vm.4H" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_u32", + "SIMD_ISA": "SVE", + "name": "svandv[_s8]", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "int8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op": { + "register": "Zop.B" }, - "b": { - "register": "Vm.2S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_u64", + "SIMD_ISA": "SVE", + "name": "svandv[_u16]", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint64x1_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Dm" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12734,55 +15285,53 @@ ], "instructions": [ [ - "CMHS" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcle_u8", + "SIMD_ISA": "SVE", + "name": "svandv[_u32]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.S" }, - "b": { - "register": "Vm.8B" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcled_f64", + "SIMD_ISA": "SVE", + "name": "svandv[_u64]", "arguments": [ - "float64_t a", - "float64_t b" + "svbool_t pg", + "svuint64_t op" ], "return_type": { "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Dm" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -12790,26 +15339,26 @@ ], "instructions": [ [ - "FCMGE" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcled_s64", + "SIMD_ISA": "SVE", + "name": "svandv[_u8]", "arguments": [ - "int64_t a", - "int64_t b" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "uint64_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.B" }, - "b": { - "register": "Dm" + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -12817,26 +15366,30 @@ ], "instructions": [ [ - "CMGE" + "ANDV" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcled_u64", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_m", "arguments": [ - "uint64_t a", - "uint64_t b" + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Ztied1.H" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12844,26 +15397,33 @@ ], "instructions": [ [ - "CMHS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleh_f16", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_x", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -12871,83 +15431,114 @@ ], "instructions": [ [ - "FCMGE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_f16", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_z", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_f32", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_m", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_f64", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_x", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -12955,84 +15546,114 @@ ], "instructions": [ [ - "FCMGE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_s16", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_z", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_s32", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_m", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Ztied1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_s64", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_x", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -13040,113 +15661,155 @@ ], "instructions": [ [ - "CMGE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_s8", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_z", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_u16", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_m", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Ztied1.B" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_u32", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_x", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_u64", + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_z", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13154,55 +15817,74 @@ ], "instructions": [ [ - "CMHS" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcleq_u8", + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_m", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHS" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcles_f32", + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_x", "arguments": [ - "float32_t a", - "float32_t b" + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -13210,46 +15892,73 @@ ], "instructions": [ [ - "FCMGE" + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_f16", + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_z", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_f32", + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_m", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13257,22 +15966,34 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_f64", + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_x", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13280,22 +16001,37 @@ ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_s16", + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_z", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13303,22 +16039,35 @@ ], "instructions": [ [ - "CMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_s32", + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_m", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -13326,22 +16075,34 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_s64", + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_x", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -13349,22 +16110,37 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclez_s8", + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_z", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -13372,22 +16148,35 @@ ], "instructions": [ [ - "CMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezd_f64", + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_m", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13395,22 +16184,34 @@ ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezd_s64", + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_x", "arguments": [ - "int64_t a" + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13418,22 +16219,37 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezh_f16", + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_z", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13441,46 +16257,69 @@ ], "instructions": [ [ - "FCMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_f16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_m", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_f32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_x", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -13488,22 +16327,36 @@ ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_f64", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_z", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -13511,22 +16364,35 @@ ], "instructions": [ [ - "FCMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_s16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_m", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13534,22 +16400,33 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_s32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_x", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13557,22 +16434,36 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_s64", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_z", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -13580,22 +16471,35 @@ ], "instructions": [ [ - "CMLE" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezq_s8", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_m", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13603,22 +16507,33 @@ ], "instructions": [ [ - "CMLE" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclezs_f32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_x", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -13626,383 +16541,517 @@ ], "instructions": [ [ - "FCMLE" + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_s16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_z", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_s32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_m", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_s8", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_x", "arguments": [ - "int8x8_t a" + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_u16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_z", "arguments": [ - "uint16x4_t a" + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_u32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_m", "arguments": [ - "uint32x2_t a" + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcls_u8", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_x", "arguments": [ - "uint8x8_t a" + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_s16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_z", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_s32", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_m", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_s8", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_x", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASR" + ], + [ + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_u16", + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_z", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "MOVPRFX", + "ASR" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_u32", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_m", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" ], "return_type": { - "value": "int32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclsq_u8", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_x", "arguments": [ - "uint8x16_t a" + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" ], "return_type": { - "value": "int8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLS" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_f16", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_z", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "imm2": { + "minimum": 1, + "maximum": 16 }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_f32", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_m", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "imm2": { + "minimum": 1, + "maximum": 32 }, - "b": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_f64", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_x", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm2": { + "minimum": 1, + "maximum": 32 }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -14010,84 +17059,104 @@ ], "instructions": [ [ - "FCMGT" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_s16", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_z", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "imm2": { + "minimum": 1, + "maximum": 32 }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_s32", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_m", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "imm2": { + "minimum": 1, + "maximum": 64 }, - "b": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_s64", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_x", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm2": { + "minimum": 1, + "maximum": 64 }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -14095,113 +17164,140 @@ ], "instructions": [ [ - "CMGT" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_s8", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_z", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint8x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "imm2": { + "minimum": 1, + "maximum": 64 }, - "b": { - "register": "Vm.8B" + "op1": { + "register": "Zop1.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_u16", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_m", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "imm2": { + "minimum": 1, + "maximum": 8 }, - "b": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_u32", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_x", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "imm2": { + "minimum": 1, + "maximum": 8 }, - "b": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_u64", + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_z", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" ], "return_type": { - "value": "uint64x1_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm2": { + "minimum": 1, + "maximum": 8 }, - "b": { - "register": "Dm" + "op1": { + "register": "Zop1.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -14209,55 +17305,66 @@ ], "instructions": [ [ - "CMHI" + "MOVPRFX", + "ASRD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclt_u8", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s16]", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltd_f64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s32]", "arguments": [ - "float64_t a", - "float64_t b" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "uint64_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ @@ -14265,26 +17372,34 @@ ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltd_s64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s64]", "arguments": [ - "int64_t a", - "int64_t b" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "uint64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ @@ -14292,26 +17407,34 @@ ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltd_u64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s8]", "arguments": [ - "uint64_t a", - "uint64_t b" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint64_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -14319,26 +17442,34 @@ ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclth_f16", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u16]", "arguments": [ - "float16_t a", - "float16_t b" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "uint16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -14346,83 +17477,104 @@ ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_f16", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_f32", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_f64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u8]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -14430,84 +17582,104 @@ ], "instructions": [ [ - "FCMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_s16", + "SIMD_ISA": "SVE2", + "name": "svbcax[_s16]", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_s32", + "SIMD_ISA": "SVE2", + "name": "svbcax[_s32]", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_s64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_s64]", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -14515,113 +17687,139 @@ ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_s8", + "SIMD_ISA": "SVE2", + "name": "svbcax[_s8]", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMGT" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_u16", + "SIMD_ISA": "SVE2", + "name": "svbcax[_u16]", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_u32", + "SIMD_ISA": "SVE2", + "name": "svbcax[_u32]", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_u64", + "SIMD_ISA": "SVE2", + "name": "svbcax[_u64]", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -14629,55 +17827,65 @@ ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltq_u8", + "SIMD_ISA": "SVE2", + "name": "svbcax[_u8]", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMHI" + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclts_f32", + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u16]", "arguments": [ - "float32_t a", - "float32_t b" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Sm" + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -14685,46 +17893,53 @@ ], "instructions": [ [ - "FCMGT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_f16", + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u32]", "arguments": [ - "float16x4_t a" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_f32", + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u64]", "arguments": [ - "float32x2_t a" + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ @@ -14732,22 +17947,26 @@ ], "instructions": [ [ - "FCMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_f64", + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u8]", "arguments": [ - "float64x1_t a" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ @@ -14755,22 +17974,26 @@ ], "instructions": [ [ - "FCMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_s16", + "SIMD_ISA": "SVE2", + "name": "svbdep[_u16]", "arguments": [ - "int16x4_t a" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -14778,22 +18001,26 @@ ], "instructions": [ [ - "CMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_s32", + "SIMD_ISA": "SVE2", + "name": "svbdep[_u32]", "arguments": [ - "int32x2_t a" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -14801,22 +18028,26 @@ ], "instructions": [ [ - "CMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_s64", + "SIMD_ISA": "SVE2", + "name": "svbdep[_u64]", "arguments": [ - "int64x1_t a" + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -14824,22 +18055,26 @@ ], "instructions": [ [ - "CMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltz_s8", + "SIMD_ISA": "SVE2", + "name": "svbdep[_u8]", "arguments": [ - "int8x8_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -14847,22 +18082,26 @@ ], "instructions": [ [ - "CMLT" + "BDEP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzd_f64", + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u16]", "arguments": [ - "float64_t a" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -14870,22 +18109,26 @@ ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzd_s64", + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u32]", "arguments": [ - "int64_t a" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -14893,22 +18136,26 @@ ], "instructions": [ [ - "CMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzh_f16", + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u64]", "arguments": [ - "float16_t a" + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ @@ -14916,46 +18163,53 @@ ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_f16", + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u8]", "arguments": [ - "float16x8_t a" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_f32", + "SIMD_ISA": "SVE2", + "name": "svbext[_u16]", "arguments": [ - "float32x4_t a" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -14963,22 +18217,26 @@ ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_f64", + "SIMD_ISA": "SVE2", + "name": "svbext[_u32]", "arguments": [ - "float64x2_t a" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -14986,22 +18244,26 @@ ], "instructions": [ [ - "FCMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_s16", + "SIMD_ISA": "SVE2", + "name": "svbext[_u64]", "arguments": [ - "int16x8_t a" + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -15009,22 +18271,26 @@ ], "instructions": [ [ - "CMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_s32", + "SIMD_ISA": "SVE2", + "name": "svbext[_u8]", "arguments": [ - "int32x4_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -15032,22 +18298,26 @@ ], "instructions": [ [ - "CMLT" + "BEXT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_s64", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u16]", "arguments": [ - "int64x2_t a" + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" } }, "Architectures": [ @@ -15055,22 +18325,26 @@ ], "instructions": [ [ - "CMLT" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzq_s8", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u32]", "arguments": [ - "int8x16_t a" + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" } }, "Architectures": [ @@ -15078,22 +18352,26 @@ ], "instructions": [ [ - "CMLT" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcltzs_f32", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u64]", "arguments": [ - "float32_t a" + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" } }, "Architectures": [ @@ -15101,1138 +18379,1299 @@ ], "instructions": [ [ - "FCMLT" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_s16", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u8]", "arguments": [ - "int16x4_t a" + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_s32", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u16]", "arguments": [ - "int32x2_t a" + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_s8", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u32]", "arguments": [ - "int8x8_t a" + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_u16", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u64]", "arguments": [ - "uint16x4_t a" + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_u32", + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u8]", "arguments": [ - "uint32x2_t a" + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BGRP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclz_u8", + "SIMD_ISA": "SVE", + "name": "svbic[_b]_z", "arguments": [ - "uint8x8_t a" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_s16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_m", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_s32", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_x", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "AND" + ], + [ + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_s8", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_z", "arguments": [ - "int8x16_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_u16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_m", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_u32", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_x", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "AND" + ], + [ + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vclzq_u8", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_z", "arguments": [ - "uint8x16_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CLZ" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_m", "arguments": [ - "float16x4_t r", - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_x", "arguments": [ - "float32x2_t r", - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "AND" + ], + [ + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_lane_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_z", "arguments": [ - "float16x4_t r", - "float16x4_t a", - "float16x4_t b", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.D" }, - "r": { - "register": "Vd.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmla_lane_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_n_s8]_m", "arguments": [ - "float32x2_t r", - "float32x2_t a", - "float32x2_t b", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": 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"lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.B" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u16]_m", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u16]_x", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u16]_z", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_f64", + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_m", "arguments": [ - "float64x2_t r", - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -16455,214 +19913,236 @@ ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_lane_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_x", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_lane_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_z", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x2_t b", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.S" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_m", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot180_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_x", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.8H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_f32", + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_m", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_f64", + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_x", "arguments": [ - "float64x2_t r", - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -16670,214 +20150,212 @@ ], "instructions": [ [ - "FCMLA" + "BIC" + ], + [ + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_lane_f16", + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "MOVPRFX", + "BIC" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_lane_f32", + "SIMD_ISA": "SVE", + "name": "svbrka[_b]_m", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x2_t b", - "const int lane" + "svbool_t inactive", + "svbool_t pg", + "svbool_t op" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 0 + "inactive": { + "register": "Ptied.B" }, - "r": { - "register": "Vd.4S" + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svbrka[_b]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "svbool_t pg", + "svbool_t op" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Pop.B" }, - "r": { - "register": "Vd.8H" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot270_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svbrkb[_b]_m", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b", - "const int lane" + "svbool_t inactive", + "svbool_t pg", + "svbool_t op" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "inactive": { + "register": "Ptied.B" }, - "r": { - "register": "Vd.4S" + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_f16", + "SIMD_ISA": "SVE", + "name": "svbrkb[_b]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svbool_t op" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.8H" + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_f32", + "SIMD_ISA": "SVE", + "name": "svbrkn[_b]_z", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.4S" + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Ptied2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKN" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_f64", + "SIMD_ISA": "SVE", + "name": "svbrkpa[_b]_z", "arguments": [ - "float64x2_t r", - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "r": { - "register": "Vd.2D" + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -16885,368 +20363,446 @@ ], "instructions": [ [ - "FCMLA" + "BRKPA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_lane_f16", + "SIMD_ISA": "SVE", + "name": "svbrkpb[_b]_z", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x4_t b", - "const int lane" + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Pop1.B" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BRKPB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_lane_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s16]", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x2_t b", - "const int lane" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "float32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_laneq_f16", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s32]", "arguments": [ - "float16x8_t r", - "float16x8_t a", - "float16x8_t b", - "const int lane" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "float16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "r": { - "register": "Vd.8H" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcmlaq_rot90_laneq_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s64]", "arguments": [ - "float32x4_t r", - "float32x4_t a", - "float32x4_t b", - "const int lane" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "float32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "r": { - "register": "Vd.4S" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCMLA" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcnt_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s8]", "arguments": [ - "poly8x8_t a" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "poly8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcnt_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u16]", "arguments": [ - "int8x8_t a" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcnt_u8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u32]", "arguments": [ - "uint8x8_t a" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcntq_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u64]", "arguments": [ - "poly8x16_t a" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "poly8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcntq_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u8]", "arguments": [ - "int8x16_t a" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "int8x16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcntq_u8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s16]", "arguments": [ - "uint8x16_t a" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CNT" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_f16", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s32]", "arguments": [ - "float16x4_t low", - "float16x4_t high" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "float16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "low": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s64]", "arguments": [ - "float32x2_t low", - "float32x2_t high" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "float32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "low": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_f64", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s8]", "arguments": [ - "float64x1_t low", - "float64x1_t high" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "float64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.1D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "low": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -17254,366 +20810,419 @@ ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_p16", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u16]", "arguments": [ - "poly16x4_t low", - "poly16x4_t high" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "poly16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "low": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_p64", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u32]", "arguments": [ - "poly64x1_t low", - "poly64x1_t high" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "poly64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.1D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "low": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u64]", "arguments": [ - "poly8x8_t low", - "poly8x8_t high" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "poly8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "low": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_s16", + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u8]", "arguments": [ - "int16x4_t low", - "int16x4_t high" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "int16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "low": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_s32", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s16]", "arguments": [ - "int32x2_t low", - "int32x2_t high" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "int32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "low": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_s64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s32]", "arguments": [ - "int64x1_t low", - "int64x1_t high" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "int64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.1D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "low": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s64]", "arguments": [ - "int8x8_t low", - "int8x8_t high" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "int8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "low": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_u16", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s8]", "arguments": [ - "uint16x4_t low", - "uint16x4_t high" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.4H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "low": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_u32", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u16]", "arguments": [ - "uint32x2_t low", - "uint32x2_t high" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "low": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_u64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u32]", "arguments": [ - "uint64x1_t low", - "uint64x1_t high" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.1D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "low": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcombine_u8", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u64]", "arguments": [ - "uint8x8_t low", - "uint8x8_t high" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "high": { - "register": "Vm.8B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "low": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP", - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u8]", "arguments": [ - "float32x2_t a", - "const int lane1", - "float32x2_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "float32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -17621,36 +21230,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_f64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s16]", "arguments": [ - "float64x1_t a", - "const int lane1", - "float64x1_t b", - "const int lane2" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "float64x1_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -17658,36 +21265,34 @@ ], "instructions": [ [ - "DUP" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_p16", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s32]", "arguments": [ - "poly16x4_t a", - "const int lane1", - "poly16x4_t b", - "const int lane2" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "poly16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -17695,74 +21300,69 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_p64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s64]", "arguments": [ - "poly64x1_t a", - "const int lane1", - "poly64x1_t b", - "const int lane2" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "poly64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s8]", "arguments": [ - "poly8x8_t a", - "const int lane1", - "poly8x8_t b", - "const int lane2" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "poly8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" - }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -17770,36 +21370,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_s16", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u16]", "arguments": [ - "int16x4_t a", - "const int lane1", - "int16x4_t b", - "const int lane2" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "int16x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4H" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -17807,36 +21405,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_s32", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u32]", "arguments": [ - "int32x2_t a", - "const int lane1", - "int32x2_t b", - "const int lane2" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "int32x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vn.2S" - }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -17844,36 +21440,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_s64", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u64]", "arguments": [ - "int64x1_t a", - "const int lane1", - "int64x1_t b", - "const int lane2" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "int64x1_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.1D" - }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -17881,36 +21475,34 @@ ], "instructions": [ [ - "DUP" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u8]", "arguments": [ - "int8x8_t a", - "const int lane1", - "int8x8_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "b": { - "register": "Vn.8B" - }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -17918,36 +21510,34 @@ ], "instructions": [ [ - "INS" + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_u16", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s16]", "arguments": [ - "uint16x4_t a", - "const int lane1", - "uint16x4_t b", - "const int lane2" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "uint16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4H" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -17955,36 +21545,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_u32", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s32]", "arguments": [ - "uint32x2_t a", - "const int lane1", - "uint32x2_t b", - "const int lane2" + "svint32_t op1", + "svint32_t op2", + "int32_t op3" ], "return_type": { - "value": "uint32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ @@ -17992,36 +21580,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_u64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s64]", "arguments": [ - "uint64x1_t a", - "const int lane1", - "uint64x1_t b", - "const int lane2" + "svint64_t op1", + "svint64_t op2", + "int64_t op3" ], "return_type": { - "value": "uint64x1_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.1D" - }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ @@ -18029,36 +21615,34 @@ ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_lane_u8", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s8]", "arguments": [ - "uint8x8_t a", - "const int lane1", - "uint8x8_t b", - "const int lane2" + "svint8_t op1", + "svint8_t op2", + "int8_t op3" ], "return_type": { - "value": "uint8x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ @@ -18066,36 +21650,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_f32", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u16]", "arguments": [ - "float32x2_t a", - "const int lane1", - "float32x4_t b", - "const int lane2" + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" ], "return_type": { - "value": "float32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vn.4S" - }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -18103,36 +21685,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_f64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u32]", "arguments": [ - "float64x1_t a", - "const int lane1", - "float64x2_t b", - "const int lane2" + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" ], "return_type": { - "value": "float64x1_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.S[*]" } }, "Architectures": [ @@ -18140,36 +21720,34 @@ ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_p16", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u64]", "arguments": [ - "poly16x4_t a", - "const int lane1", - "poly16x8_t b", - "const int lane2" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" ], "return_type": { - "value": "poly16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.8H" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.D[*]" } }, "Architectures": [ @@ -18177,74 +21755,69 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_p64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u8]", "arguments": [ - "poly64x1_t a", - "const int lane1", - "poly64x2_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" ], "return_type": { - "value": "poly64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B[*]" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_p8", + "SIMD_ISA": "SVE2", + "name": "svbsl[_s16]", "arguments": [ - "poly8x8_t a", - "const int lane1", - "poly8x16_t b", - "const int lane2" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" ], "return_type": { - "value": "poly8x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -18252,36 +21825,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_s16", + "SIMD_ISA": "SVE2", + "name": "svbsl[_s32]", "arguments": [ - "int16x4_t a", - "const int lane1", - "int16x8_t b", - "const int lane2" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" ], "return_type": { - "value": "int16x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -18289,36 +21860,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_s32", + "SIMD_ISA": "SVE2", + "name": "svbsl[_s64]", "arguments": [ - "int32x2_t a", - "const int lane1", - "int32x4_t b", - "const int lane2" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" ], "return_type": { - "value": "int32x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -18326,36 +21895,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_s64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_s8]", "arguments": [ - "int64x1_t a", - "const int lane1", - "int64x2_t b", - "const int lane2" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" ], "return_type": { - "value": "int64x1_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -18363,36 +21930,34 @@ ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_s8", + "SIMD_ISA": "SVE2", + "name": "svbsl[_u16]", "arguments": [ - "int8x8_t a", - "const int lane1", - "int8x16_t b", - "const int lane2" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" ], "return_type": { - "value": "int8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -18400,36 +21965,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_u16", + "SIMD_ISA": "SVE2", + "name": "svbsl[_u32]", "arguments": [ - "uint16x4_t a", - "const int lane1", - "uint16x8_t b", - "const int lane2" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -18437,36 +22000,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_u32", + "SIMD_ISA": "SVE2", + "name": "svbsl[_u64]", "arguments": [ - "uint32x2_t a", - "const int lane1", - "uint32x4_t b", - "const int lane2" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -18474,36 +22035,34 @@ ], "instructions": [ [ - "INS" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_u64", + "SIMD_ISA": "SVE2", + "name": "svbsl[_u8]", "arguments": [ - "uint64x1_t a", - "const int lane1", - "uint64x2_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "UNUSED" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -18511,36 +22070,35 @@ ], "instructions": [ [ - "DUP" + "BSL" + ], + [ + "MOVPRFX", + "BSL" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopy_laneq_u8", + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_m", "arguments": [ - "uint8x8_t a", - "const int lane1", - "uint8x16_t b", - "const int lane2" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint8x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -18548,36 +22106,35 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_f32", + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_x", "arguments": [ - "float32x4_t a", - "const int lane1", - "float32x2_t b", - "const int lane2" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "float32x4_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -18585,36 +22142,35 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_f64", + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_z", "arguments": [ - "float64x2_t a", - "const int lane1", - "float64x1_t b", - "const int lane2" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.H" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -18622,36 +22178,32 @@ ], "instructions": [ [ - "INS" + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_p16", + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_m", "arguments": [ - "poly16x8_t a", - "const int lane1", - "poly16x4_t b", - "const int lane2" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly16x8_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -18659,74 +22211,71 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_p64", + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_x", "arguments": [ - "poly64x2_t a", - "const int lane1", - "poly64x1_t b", - "const int lane2" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_p8", + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_z", "arguments": [ - "poly8x16_t a", - "const int lane1", - "poly8x8_t b", - "const int lane2" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly8x16_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.S" }, - "lane1": { - "minimum": 0, - "maximum": 15 + "op2": { + "register": "Zop2.S" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -18734,36 +22283,32 @@ ], "instructions": [ [ - "INS" + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_s16", + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_m", "arguments": [ - "int16x8_t a", - "const int lane1", - "int16x4_t b", - "const int lane2" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -18771,36 +22316,35 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_x", "arguments": [ - "int32x4_t a", - "const int lane1", - "int32x2_t b", - "const int lane2" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2S" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -18808,36 +22352,35 @@ ], "instructions": [ [ - "INS" + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_s64", + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_z", "arguments": [ - "int64x2_t a", - "const int lane1", - "int64x1_t b", - "const int lane2" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.1D" + "op1": { + "register": "Zop1.D" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -18845,36 +22388,28 @@ ], "instructions": [ [ - "INS" + "MOVPRFX", + "FCADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_s8", + "SIMD_ISA": "SVE2", + "name": "svcadd[_s16]", "arguments": [ - "int8x16_t a", - "const int lane1", - "int8x8_t b", - "const int lane2" + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "int8x16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.8B" - }, - "lane1": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -18882,36 +22417,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_u16", + "SIMD_ISA": "SVE2", + "name": "svcadd[_s32]", "arguments": [ - "uint16x8_t a", - "const int lane1", - "uint16x4_t b", - "const int lane2" + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.4H" - }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -18919,36 +22449,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_u32", + "SIMD_ISA": "SVE2", + "name": "svcadd[_s64]", "arguments": [ - "uint32x4_t a", - "const int lane1", - "uint32x2_t b", - "const int lane2" + "svint64_t op1", + "svint64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.2S" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -18956,36 +22481,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_u64", + "SIMD_ISA": "SVE2", + "name": "svcadd[_s8]", "arguments": [ - "uint64x2_t a", - "const int lane1", - "uint64x1_t b", - "const int lane2" + "svint8_t op1", + "svint8_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.1D" - }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane2": { - "minimum": 0, - "maximum": 0 + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -18993,36 +22513,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_lane_u8", + "SIMD_ISA": "SVE2", + "name": "svcadd[_u16]", "arguments": [ - "uint8x16_t a", - "const int lane1", - "uint8x8_t b", - "const int lane2" + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.8B" - }, - "lane1": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.H" } }, "Architectures": [ @@ -19030,36 +22545,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_f32", + "SIMD_ISA": "SVE2", + "name": "svcadd[_u32]", "arguments": [ - "float32x4_t a", - "const int lane1", - "float32x4_t b", - "const int lane2" + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "float32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S" } }, "Architectures": [ @@ -19067,36 +22577,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_f64", + "SIMD_ISA": "SVE2", + "name": "svcadd[_u64]", "arguments": [ - "float64x2_t a", - "const int lane1", - "float64x2_t b", - "const int lane2" + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "float64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "b": { - "register": "Vn.2D" - }, - "lane1": { - "minimum": 0, - "maximum": 1 - }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D" } }, "Architectures": [ @@ -19104,36 +22609,31 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_p16", + "SIMD_ISA": "SVE2", + "name": "svcadd[_u8]", "arguments": [ - "poly16x8_t a", - "const int lane1", - "poly16x8_t b", - "const int lane2" + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B|Ztied1.B" }, - "lane1": { - "minimum": 0, - "maximum": 7 - }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" } }, "Architectures": [ @@ -19141,74 +22641,71 @@ ], "instructions": [ [ - "INS" + "CADD" + ], + [ + "MOVPRFX", + "CADD" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_p64", + "SIMD_ISA": "SVE2", + "name": "svcdot[_s32]", "arguments": [ - "poly64x2_t a", - "const int lane1", - "poly64x2_t b", - "const int lane2" + "svint32_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "INS" + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_p8", + "SIMD_ISA": "SVE2", + "name": "svcdot[_s64]", "arguments": [ - "poly8x16_t a", - "const int lane1", - "poly8x16_t b", - "const int lane2" + "svint64_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "poly8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 15 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -19216,36 +22713,40 @@ ], "instructions": [ [ - "INS" + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_s16", + "SIMD_ISA": "SVE2", + "name": "svcdot_lane[_s32]", "arguments": [ - "int16x8_t a", - "const int lane1", - "int16x8_t b", - "const int lane2" + "svint32_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" + "imm_index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "op2": { + "register": "Zop2.B" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -19253,36 +22754,40 @@ ], "instructions": [ [ - "INS" + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_s32", + "SIMD_ISA": "SVE2", + "name": "svcdot_lane[_s64]", "arguments": [ - "int32x4_t a", - "const int lane1", - "int32x4_t b", - "const int lane2" + "svint64_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" + "imm_index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -19290,36 +22795,34 @@ ], "instructions": [ [ - "INS" + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_s64", + "SIMD_ISA": "SVE2", + "name": "svclamp[_f16]", "arguments": [ - "int64x2_t a", - "const int lane1", - "int64x2_t b", - "const int lane2" + "svfloat16_t op", + "svfloat16_t min", + "svfloat16_t max" ], "return_type": { - "value": "int64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" + "max": { + "register": "Zreg3.H" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "min": { + "register": "Zreg2.H" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zreg1.H" } }, "Architectures": [ @@ -19327,36 +22830,30 @@ ], "instructions": [ [ - "INS" + "FCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_s8", + "SIMD_ISA": "SVE2", + "name": "svclamp[_f32]", "arguments": [ - "int8x16_t a", - "const int lane1", - "int8x16_t b", - "const int lane2" + "svfloat32_t op", + "svfloat32_t min", + "svfloat32_t max" ], "return_type": { - "value": "int8x16_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "max": { + "register": "Zreg3.S" }, - "b": { - "register": "Vn.16B" - }, - "lane1": { - "minimum": 0, - "maximum": 15 + "min": { + "register": "Zreg2.S" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op": { + "register": "Zreg1.S" } }, "Architectures": [ @@ -19364,36 +22861,30 @@ ], "instructions": [ [ - "INS" + "FCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_u16", + "SIMD_ISA": "SVE2", + "name": "svclamp[_f64]", "arguments": [ - "uint16x8_t a", - "const int lane1", - "uint16x8_t b", - "const int lane2" + "svfloat64_t op", + "svfloat64_t min", + "svfloat64_t max" ], "return_type": { - "value": "uint16x8_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "max": { + "register": "Zreg3.D" }, - "lane1": { - "minimum": 0, - "maximum": 7 + "min": { + "register": "Zreg2.D" }, - "lane2": { - "minimum": 0, - "maximum": 7 + "op": { + "register": "Zreg1.D" } }, "Architectures": [ @@ -19401,36 +22892,30 @@ ], "instructions": [ [ - "INS" + "FCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_u32", + "SIMD_ISA": "SVE2", + "name": "svclamp[_s16]", "arguments": [ - "uint32x4_t a", - "const int lane1", - "uint32x4_t b", - "const int lane2" + "svint16_t op", + "svint16_t min", + "svint16_t max" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" + "max": { + "register": "Zreg3.H" }, - "lane1": { - "minimum": 0, - "maximum": 3 + "min": { + "register": "Zreg2.H" }, - "lane2": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Zreg1.H" } }, "Architectures": [ @@ -19438,36 +22923,30 @@ ], "instructions": [ [ - "INS" + "SCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_u64", + "SIMD_ISA": "SVE2", + "name": "svclamp[_s32]", "arguments": [ - "uint64x2_t a", - "const int lane1", - "uint64x2_t b", - "const int lane2" + "svint32_t op", + "svint32_t min", + "svint32_t max" ], "return_type": { - "value": "uint64x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" + "max": { + "register": "Zreg3.S" }, - "lane1": { - "minimum": 0, - "maximum": 1 + "min": { + "register": "Zreg2.S" }, - "lane2": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zreg1.S" } }, "Architectures": [ @@ -19475,36 +22954,30 @@ ], "instructions": [ [ - "INS" + "SCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcopyq_laneq_u8", + "SIMD_ISA": "SVE2", + "name": "svclamp[_s64]", "arguments": [ - "uint8x16_t a", - "const int lane1", - "uint8x16_t b", - "const int lane2" + "svint64_t op", + "svint64_t min", + "svint64_t max" ], "return_type": { - "value": "uint8x16_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.16B" + "max": { + "register": "Zreg3.D" }, - "b": { - "register": "Vn.16B" - }, - "lane1": { - "minimum": 0, - "maximum": 15 + "min": { + "register": "Zreg2.D" }, - "lane2": { - "minimum": 0, - "maximum": 15 + "op": { + "register": "Zreg1.D" } }, "Architectures": [ @@ -19512,72 +22985,92 @@ ], "instructions": [ [ - "INS" + "SCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_f16", + "SIMD_ISA": "SVE2", + "name": "svclamp[_s8]", "arguments": [ - "uint64_t a" + "svint8_t op", + "svint8_t min", + "svint8_t max" ], "return_type": { - "value": "float16x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.B" + }, + "min": { + "register": "Zreg2.B" + }, + "op": { + "register": "Zreg1.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "SCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_f32", + "SIMD_ISA": "SVE2", + "name": "svclamp[_u16]", "arguments": [ - "uint64_t a" + "svuint16_t op", + "svuint16_t min", + "svuint16_t max" ], "return_type": { - "value": "float32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.H" + }, + "min": { + "register": "Zreg2.H" + }, + "op": { + "register": "Zreg1.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "UCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_f64", + "SIMD_ISA": "SVE2", + "name": "svclamp[_u32]", "arguments": [ - "uint64_t a" + "svuint32_t op", + "svuint32_t min", + "svuint32_t max" ], "return_type": { - "value": "float64x1_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.S" + }, + "min": { + "register": "Zreg2.S" + }, + "op": { + "register": "Zreg1.S" } }, "Architectures": [ @@ -19585,394 +23078,537 @@ ], "instructions": [ [ - "INS" + "UCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_p16", + "SIMD_ISA": "SVE2", + "name": "svclamp[_u64]", "arguments": [ - "uint64_t a" + "svuint64_t op", + "svuint64_t min", + "svuint64_t max" ], "return_type": { - "value": "poly16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.D" + }, + "min": { + "register": "Zreg2.D" + }, + "op": { + "register": "Zreg1.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "UCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_p64", + "SIMD_ISA": "SVE2", + "name": "svclamp[_u8]", "arguments": [ - "uint64_t a" + "svuint8_t op", + "svuint8_t min", + "svuint8_t max" ], "return_type": { - "value": "poly64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "max": { + "register": "Zreg3.B" + }, + "min": { + "register": "Zreg2.B" + }, + "op": { + "register": "Zreg1.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "INS" + "UCLAMP" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_p8", + "SIMD_ISA": "SVE", + "name": "svclasta[_f16]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svfloat16_t fallback", + "svfloat16_t data" ], "return_type": { - "value": "poly8x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_s16", + "SIMD_ISA": "SVE", + "name": "svclasta[_f32]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svfloat32_t fallback", + "svfloat32_t data" ], "return_type": { - "value": "int16x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_s32", + "SIMD_ISA": "SVE", + "name": "svclasta[_f64]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svfloat64_t fallback", + "svfloat64_t data" ], "return_type": { - "value": "int32x2_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_s64", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f16]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "float16_t fallback", + "svfloat16_t data" ], "return_type": { - "value": "int64x1_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_s8", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f32]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "float32_t fallback", + "svfloat32_t data" ], "return_type": { - "value": "int8x8_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_u16", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f64]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "float64_t fallback", + "svfloat64_t data" ], "return_type": { - "value": "uint16x4_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_u32", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s16]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "int16_t fallback", + "svint16_t data" ], "return_type": { - "value": "uint32x2_t" + "value": "int16_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_u64", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s32]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "int32_t fallback", + "svint32_t data" ], "return_type": { - "value": "uint64x1_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcreate_u8", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s64]", "arguments": [ - "uint64_t a" + "svbool_t pg", + "int64_t fallback", + "svint64_t data" ], "return_type": { - "value": "uint8x8_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Xn" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f16_f32", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s8]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "int8_t fallback", + "svint8_t data" ], "return_type": { - "value": "float16x4_t" + "value": "int8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTN" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f16_s16", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u16]", "arguments": [ - "int16x4_t a" + "svbool_t pg", + "uint16_t fallback", + "svuint16_t data" ], "return_type": { - "value": "float16x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f16_u16", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u32]", "arguments": [ - "uint16x4_t a" + "svbool_t pg", + "uint32_t fallback", + "svuint32_t data" ], "return_type": { - "value": "float16x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f32_f16", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u64]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "uint64_t fallback", + "svuint64_t data" ], "return_type": { - "value": "float32x4_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTL" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f32_f64", + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u8]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "uint8_t fallback", + "svuint8_t data" ], "return_type": { - "value": "float32x2_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -19980,72 +23616,103 @@ ], "instructions": [ [ - "FCVTN" + "CLASTA" + ], + [ + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f32_s32", + "SIMD_ISA": "SVE", + "name": "svclasta[_s16]", "arguments": [ - "int32x2_t a" + "svbool_t pg", + "svint16_t fallback", + "svint16_t data" ], "return_type": { - "value": "float32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f32_u32", + "SIMD_ISA": "SVE", + "name": "svclasta[_s32]", "arguments": [ - "uint32x2_t a" + "svbool_t pg", + "svint32_t fallback", + "svint32_t data" ], "return_type": { - "value": "float32x2_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f64_f32", + "SIMD_ISA": "SVE", + "name": "svclasta[_s64]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint64_t fallback", + "svint64_t data" ], "return_type": { - "value": "float64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20053,22 +23720,34 @@ ], "instructions": [ [ - "FCVTL" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f64_s64", + "SIMD_ISA": "SVE", + "name": "svclasta[_s8]", "arguments": [ - "int64x1_t a" + "svbool_t pg", + "svint8_t fallback", + "svint8_t data" ], "return_type": { - "value": "float64x1_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -20076,22 +23755,34 @@ ], "instructions": [ [ - "SCVTF" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_f64_u64", + "SIMD_ISA": "SVE", + "name": "svclasta[_u16]", "arguments": [ - "uint64x1_t a" + "svbool_t pg", + "svuint16_t fallback", + "svuint16_t data" ], "return_type": { - "value": "float64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20099,26 +23790,34 @@ ], "instructions": [ [ - "UCVTF" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_high_f16_f32", + "SIMD_ISA": "SVE", + "name": "svclasta[_u32]", "arguments": [ - "float16x4_t r", - "float32x4_t a" + "svbool_t pg", + "svuint32_t fallback", + "svuint32_t data" ], "return_type": { - "value": "float16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "data": { + "register": "Zdata.S" }, - "r": { - "register": "Vd.4H" + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20126,22 +23825,34 @@ ], "instructions": [ [ - "FCVTN2" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_high_f32_f16", + "SIMD_ISA": "SVE", + "name": "svclasta[_u64]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svuint64_t fallback", + "svuint64_t data" ], "return_type": { - "value": "float32x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20149,26 +23860,34 @@ ], "instructions": [ [ - "FCVTL2" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_high_f32_f64", + "SIMD_ISA": "SVE", + "name": "svclasta[_u8]", "arguments": [ - "float32x2_t r", - "float64x2_t a" + "svbool_t pg", + "svuint8_t fallback", + "svuint8_t data" ], "return_type": { - "value": "float32x4_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "data": { + "register": "Zdata.B" }, - "r": { - "register": "Vd.2S" + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -20176,22 +23895,34 @@ ], "instructions": [ [ - "FCVTN2" + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_high_f64_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_f16]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svfloat16_t fallback", + "svfloat16_t data" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20199,145 +23930,172 @@ ], "instructions": [ [ - "FCVTL2" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f16_s16", + "SIMD_ISA": "SVE", + "name": "svclastb[_f32]", "arguments": [ - "int16x4_t a", - "const int n" + "svbool_t pg", + "svfloat32_t fallback", + "svfloat32_t data" ], "return_type": { - "value": "float16x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f16_u16", + "SIMD_ISA": "SVE", + "name": "svclastb[_f64]", "arguments": [ - "uint16x4_t a", - "const int n" + "svbool_t pg", + "svfloat64_t fallback", + "svfloat64_t data" ], "return_type": { - "value": "float16x4_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f32_s32", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f16]", "arguments": [ - "int32x2_t a", - "const int n" + "svbool_t pg", + "float16_t fallback", + "svfloat16_t data" ], "return_type": { - "value": "float32x2_t" + "value": "float16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.H" }, - "n": { - "minimum": 1, - "maximum": 32 + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f32_u32", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f32]", "arguments": [ - "uint32x2_t a", - "const int n" + "svbool_t pg", + "float32_t fallback", + "svfloat32_t data" ], "return_type": { - "value": "float32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.S" }, - "n": { - "minimum": 1, - "maximum": 32 + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f64_s64", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f64]", "arguments": [ - "int64x1_t a", - "const int n" + "svbool_t pg", + "float64_t fallback", + "svfloat64_t data" ], "return_type": { - "value": "float64x1_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.D" }, - "n": { - "minimum": 1, - "maximum": 64 + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20345,27 +24103,33 @@ ], "instructions": [ [ - "SCVTF" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_f64_u64", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s16]", "arguments": [ - "uint64x1_t a", - "const int n" + "svbool_t pg", + "int16_t fallback", + "svint16_t data" ], "return_type": { - "value": "float64x1_t" + "value": "int16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.H" }, - "n": { - "minimum": 1, - "maximum": 64 + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20373,86 +24137,101 @@ ], "instructions": [ [ - "UCVTF" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_s16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s32]", "arguments": [ - "float16x4_t a", - "const int n" + "svbool_t pg", + "int32_t fallback", + "svint32_t data" ], "return_type": { - "value": "int16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s64]", "arguments": [ - "float32x2_t a", - "const int n" + "svbool_t pg", + "int64_t fallback", + "svint64_t data" ], "return_type": { - "value": "int32x2_t" + "value": "int64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.D" }, - "n": { - "minimum": 1, - "maximum": 32 + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s8]", "arguments": [ - "float64x1_t a", - "const int n" + "svbool_t pg", + "int8_t fallback", + "svint8_t data" ], "return_type": { - "value": "int64x1_t" + "value": "int8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -20460,86 +24239,101 @@ ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_u16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u16]", "arguments": [ - "float16x4_t a", - "const int n" + "svbool_t pg", + "uint16_t fallback", + "svuint16_t data" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_u32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u32]", "arguments": [ - "float32x2_t a", - "const int n" + "svbool_t pg", + "uint32_t fallback", + "svuint32_t data" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.S" }, - "n": { - "minimum": 1, - "maximum": 32 + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_n_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u64]", "arguments": [ - "float64x1_t a", - "const int n" + "svbool_t pg", + "uint64_t fallback", + "svuint64_t data" ], "return_type": { - "value": "uint64x1_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.D" }, - "n": { - "minimum": 1, - "maximum": 64 + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20547,71 +24341,102 @@ ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_s16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u8]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "uint8_t fallback", + "svuint8_t data" ], "return_type": { - "value": "int16x4_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_s16]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint16_t fallback", + "svint16_t data" ], "return_type": { - "value": "int32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_s32]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint32_t fallback", + "svint32_t data" ], "return_type": { - "value": "int64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20619,71 +24444,104 @@ ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_u16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_s64]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint64_t fallback", + "svint64_t data" ], "return_type": { - "value": "uint16x4_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_u32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_s8]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint8_t fallback", + "svint8_t data" ], "return_type": { - "value": "uint32x2_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvt_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_u16]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint16_t fallback", + "svuint16_t data" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20691,70 +24549,104 @@ ], "instructions": [ [ - "FCVTZU" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_s16_f16", + "SIMD_ISA": "SVE", + "name": "svclastb[_u32]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svuint32_t fallback", + "svuint32_t data" ], "return_type": { - "value": "int16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclastb[_u64]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svuint64_t fallback", + "svuint64_t data" ], "return_type": { - "value": "int32x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclastb[_u8]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint8_t fallback", + "svuint8_t data" ], "return_type": { - "value": "int64x1_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -20762,70 +24654,96 @@ ], "instructions": [ [ - "FCVTAS" + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_m", "arguments": [ - "float16x4_t a" + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_x", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvta_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_z", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -20833,22 +24751,31 @@ ], "instructions": [ [ - "FCVTAU" + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtad_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_m", "arguments": [ - "float64_t a" + "svuint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "int64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20856,22 +24783,30 @@ ], "instructions": [ [ - "FCVTAS" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtad_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_x", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20879,22 +24814,30 @@ ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_z", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "int16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -20902,46 +24845,62 @@ ], "instructions": [ [ - "FCVTAS" + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_m", "arguments": [ - "float16_t a" + "svuint64_t inactive", + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "int32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_x", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "int64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20949,22 +24908,30 @@ ], "instructions": [ [ - "FCVTAS" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_z", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -20972,46 +24939,62 @@ ], "instructions": [ [ - "FCVTAU" + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_m", "arguments": [ - "float16_t a" + "svuint8_t inactive", + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtah_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_x", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "uint64_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21019,70 +25002,93 @@ ], "instructions": [ [ - "FCVTAU" + "CLS" + ], + [ + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_z", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int16x8_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "MOVPRFX", + "CLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_m", "arguments": [ - "float32x4_t a" + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAS" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_x", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21090,70 +25096,93 @@ ], "instructions": [ [ - "FCVTAS" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_z", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_m", "arguments": [ - "float32x4_t a" + "svuint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTAU" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtaq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_x", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21161,22 +25190,30 @@ ], "instructions": [ [ - "FCVTAU" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtas_s32_f32", + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_z", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "int32_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21184,22 +25221,31 @@ ], "instructions": [ [ - "FCVTAS" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtas_u32_f32", + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_m", "arguments": [ - "float32_t a" + "svuint64_t inactive", + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21207,22 +25253,30 @@ ], "instructions": [ [ - "FCVTAU" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_f64_s64", + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_x", "arguments": [ - "int64_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "float64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21230,22 +25284,30 @@ ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_f64_u64", + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_z", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "float64_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21253,27 +25315,31 @@ ], "instructions": [ [ - "UCVTF" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_n_f64_s64", + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_m", "arguments": [ - "int64_t a", - "const int n" + "svuint8_t inactive", + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "float64_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "inactive": { + "register": "Zinactive.B|Ztied.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21281,27 +25347,30 @@ ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_n_f64_u64", + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_x", "arguments": [ - "uint64_t a", - "const int n" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "float64_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.B|Ztied.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21309,27 +25378,30 @@ ], "instructions": [ [ - "UCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_n_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_z", "arguments": [ - "float64_t a", - "const int n" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int64_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21337,27 +25409,31 @@ ], "instructions": [ [ - "FCVTZS" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_n_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_m", "arguments": [ - "float64_t a", - "const int n" + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "inactive": { + "register": "Zinactive.H|Ztied.H" }, - "n": { - "minimum": 1, - "maximum": 64 + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21365,22 +25441,30 @@ ], "instructions": [ [ - "FCVTZU" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_s64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_x", "arguments": [ - "float64_t a" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "int64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21388,22 +25472,30 @@ ], "instructions": [ [ - "FCVTZS" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtd_u64_f64", + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_z", "arguments": [ - "float64_t a" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21411,22 +25503,31 @@ ], "instructions": [ [ - "FCVTZU" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_s16", + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_m", "arguments": [ - "int16_t a" + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21434,46 +25535,61 @@ ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_s32", + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_x", "arguments": [ - "int32_t a" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_s64", + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_z", "arguments": [ - "int64_t a" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21481,22 +25597,31 @@ ], "instructions": [ [ - "SCVTF" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_u16", + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_m", "arguments": [ - "uint16_t a" + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21504,46 +25629,61 @@ ], "instructions": [ [ - "UCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_u32", + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_x", "arguments": [ - "uint32_t a" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_f16_u64", + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_z", "arguments": [ - "uint64_t a" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21551,27 +25691,31 @@ ], "instructions": [ [ - "UCVTF" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_s16", + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_m", "arguments": [ - "int16_t a", - "const int n" + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "inactive": { + "register": "Zinactive.B|Ztied.B" }, - "n": { - "minimum": 1, - "maximum": 16 + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21579,56 +25723,61 @@ ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_s32", + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_x", "arguments": [ - "int32_t a", - "const int n" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.B|Ztied.B" }, - "n": { - "minimum": 1, - "maximum": 16 + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_s64", + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_z", "arguments": [ - "int64_t a", - "const int n" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "float16_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op": { + "register": "Zop.B" }, - "n": { - "minimum": 1, - "maximum": 16 + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -21636,27 +25785,36 @@ ], "instructions": [ [ - "SCVTF" + "MOVPRFX", + "CLZ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_u16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_m", "arguments": [ - "uint16_t a", - "const int n" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "float16_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21664,56 +25822,79 @@ ], "instructions": [ [ - "UCVTF" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_u32", + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_x", "arguments": [ - "uint32_t a", - "const int n" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "float16_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_f16_u64", + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_z", "arguments": [ - "uint64_t a", - "const int n" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "float16_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -21721,27 +25902,36 @@ ], "instructions": [ [ - "UCVTF" + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_m", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21749,56 +25939,79 @@ ], "instructions": [ [ - "FCVTZS" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_x", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_z", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -21806,27 +26019,36 @@ ], "instructions": [ [ - "FCVTZS" + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_m", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint16_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21834,56 +26056,79 @@ ], "instructions": [ [ - "FCVTZU" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_x", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint32_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_n_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_z", "arguments": [ - "float16_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64_t" + "value": "svfloat64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -21891,22 +26136,32 @@ ], "instructions": [ [ - "FCVTZU" + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_s16_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_s16]", "arguments": [ - "float16_t a" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -21914,46 +26169,71 @@ ], "instructions": [ [ - "FCVTZS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_s32_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_s32]", "arguments": [ - "float16_t a" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_s64_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_s64]", "arguments": [ - "float16_t a" + "svint64_t op1", + "svint64_t op2", + "svint64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ @@ -21961,22 +26241,35 @@ ], "instructions": [ [ - "FCVTZS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_u16_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_s8]", "arguments": [ - "float16_t a" + "svint8_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ @@ -21984,46 +26277,71 @@ ], "instructions": [ [ - "FCVTZU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_u32_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_u16]", "arguments": [ - "float16_t a" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint32_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvth_u64_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_u32]", "arguments": [ - "float16_t a" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -22031,70 +26349,112 @@ ], "instructions": [ [ - "FCVTZU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_s16_f16", + "SIMD_ISA": "SVE2", + "name": "svcmla[_u64]", "arguments": [ - "float16x4_t a" + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_s32_f32", + "SIMD_ISA": "SVE2", + "name": "svcmla[_u8]", "arguments": [ - "float32x2_t a" + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3", + "uint64_t imm_rotation" ], "return_type": { - "value": "int32x2_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmla_lane[_f16]", "arguments": [ - "float64x1_t a" + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64x1_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -22102,70 +26462,122 @@ ], "instructions": [ [ - "FCVTMS" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmla_lane[_f32]", "arguments": [ - "float16x4_t a" + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint16x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_u32_f32", + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_s16]", "arguments": [ - "float32x2_t a" + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint32x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtm_u64_f64", + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_s32]", "arguments": [ - "float64x1_t a" + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64x1_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -22173,22 +26585,40 @@ ], "instructions": [ [ - "FCVTMU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmd_s64_f64", + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_u16]", "arguments": [ - "float64_t a" + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "int64_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" } }, "Architectures": [ @@ -22196,22 +26626,40 @@ ], "instructions": [ [ - "FCVTMS" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmd_u64_f64", + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_u32]", "arguments": [ - "float64_t a" + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" ], "return_type": { - "value": "uint64_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" } }, "Architectures": [ @@ -22219,22 +26667,34 @@ ], "instructions": [ [ - "FCVTMU" + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -22242,46 +26702,61 @@ ], "instructions": [ [ - "FCVTMS" + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f64]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22289,22 +26764,30 @@ ], "instructions": [ [ - "FCVTMS" + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -22312,46 +26795,67 @@ ], "instructions": [ [ - "FCVTMU" + "FCMEQ" + ], + [ + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "FCMEQ" + ], + [ + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmh_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f64]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22359,70 +26863,101 @@ ], "instructions": [ [ - "FCVTMU" + "FCMEQ" + ], + [ + "FCMEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s64]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22430,70 +26965,101 @@ ], "instructions": [ [ - "FCVTMS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s8]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u16]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTMU" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtmq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u32]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -22501,22 +27067,33 @@ ], "instructions": [ [ - "FCVTMU" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtms_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u64]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22524,22 +27101,33 @@ ], "instructions": [ [ - "FCVTMS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtms_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u8]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -22547,70 +27135,95 @@ ], "instructions": [ [ - "FCVTMU" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s16]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s32]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s64]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22618,70 +27231,92 @@ ], "instructions": [ [ - "FCVTNS" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s8]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u16]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtn_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u32]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -22689,22 +27324,30 @@ ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnd_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u64]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22712,22 +27355,30 @@ ], "instructions": [ [ - "FCVTNS" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnd_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u8]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -22735,22 +27386,30 @@ ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -22758,46 +27417,67 @@ ], "instructions": [ [ - "FCVTNS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s8]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -22805,22 +27485,33 @@ ], "instructions": [ [ - "FCVTNS" + "CMPEQ" + ], + [ + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -22828,46 +27519,61 @@ ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnh_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s8]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -22875,70 +27581,92 @@ ], "instructions": [ [ - "FCVTNU" + "CMPEQ" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_f16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_f32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNS" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_f64]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -22946,70 +27674,98 @@ ], "instructions": [ [ - "FCVTNS" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "FCMGE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTNU" + "FCMGE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtnq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f64]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -23017,22 +27773,33 @@ ], "instructions": [ [ - "FCVTNU" + "FCMGE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtns_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s16]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23040,22 +27807,33 @@ ], "instructions": [ [ - "FCVTNS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtns_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s32]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23063,70 +27841,101 @@ ], "instructions": [ [ - "FCVTNU" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s64]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s8]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u16]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23134,70 +27943,101 @@ ], "instructions": [ [ - "FCVTPS" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u32]", "arguments": [ - "float16x4_t a" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u64]", "arguments": [ - "float32x2_t a" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtp_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u8]", "arguments": [ - "float64x1_t a" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -23205,22 +28045,33 @@ ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpd_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_s16]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23228,22 +28079,30 @@ ], "instructions": [ [ - "FCVTPS" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpd_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge[_s32]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23251,22 +28110,30 @@ ], "instructions": [ [ - "FCVTPU" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_s64]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -23274,46 +28141,61 @@ ], "instructions": [ [ - "FCVTPS" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_s32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_s8]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_s64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_u16]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23321,22 +28203,30 @@ ], "instructions": [ [ - "FCVTPS" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_u32]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23344,46 +28234,61 @@ ], "instructions": [ [ - "FCVTPU" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_u32_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_u64]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtph_u64_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge[_u8]", "arguments": [ - "float16_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -23391,70 +28296,98 @@ ], "instructions": [ [ - "FCVTPU" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s8]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -23462,70 +28395,101 @@ ], "instructions": [ [ - "FCVTPS" + "CMPGE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtpq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u8]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -23533,22 +28497,33 @@ ], "instructions": [ [ - "FCVTPU" + "CMPHS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtps_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s16]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23556,22 +28531,30 @@ ], "instructions": [ [ - "FCVTPS" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtps_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s32]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23579,120 +28562,154 @@ ], "instructions": [ [ - "FCVTPU" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f16_s16", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s8]", "arguments": [ - "int16x8_t a" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f16_u16", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u16]", "arguments": [ - "uint16x8_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f32_s32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u32]", "arguments": [ - "int32x4_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f32_u32", + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u8]", "arguments": [ - "uint32x4_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f64_s64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f16]", "arguments": [ - "int64x2_t a" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23700,22 +28717,30 @@ ], "instructions": [ [ - "SCVTF" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_f64_u64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f32]", "arguments": [ - "uint64x2_t a" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23723,145 +28748,163 @@ ], "instructions": [ [ - "UCVTF" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f16_s16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f64]", "arguments": [ - "int16x8_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f16_u16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f16]", "arguments": [ - "uint16x8_t a", - "const int n" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "FCMGT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f32_s32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f32]", "arguments": [ - "int32x4_t a", - "const int n" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SCVTF" + "FCMGT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f32_u32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f64]", "arguments": [ - "uint32x4_t a", - "const int n" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UCVTF" + "FCMGT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f64_s64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s16]", "arguments": [ - "int64x2_t a", - "const int n" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 64 + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23869,27 +28912,33 @@ ], "instructions": [ [ - "SCVTF" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_f64_u64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s32]", "arguments": [ - "uint64x2_t a", - "const int n" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 64 + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -23897,86 +28946,101 @@ ], "instructions": [ [ - "UCVTF" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s64]", "arguments": [ - "float16x8_t a", - "const int n" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s8]", "arguments": [ - "float32x4_t a", - "const int n" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.B" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u16]", "arguments": [ - "float64x2_t a", - "const int n" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 64 + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -23984,86 +29048,101 @@ ], "instructions": [ [ - "FCVTZS" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u32]", "arguments": [ - "float16x8_t a", - "const int n" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 16 + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u64]", "arguments": [ - "float32x4_t a", - "const int n" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_n_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u8]", "arguments": [ - "float64x2_t a", - "const int n" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.B" }, - "n": { - "minimum": 1, - "maximum": 64 + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24071,71 +29150,95 @@ ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_s16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s16]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s32]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_s64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s64]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -24143,71 +29246,92 @@ ], "instructions": [ [ - "FCVTZS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_u16_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s8]", "arguments": [ - "float16x8_t a" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FCVTZS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u16]", "arguments": [ - "float32x4_t a" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FCVTZU" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtq_u64_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u32]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24215,22 +29339,30 @@ ], "instructions": [ [ - "FCVTZU" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_f32_s32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u64]", "arguments": [ - "int32_t a" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -24238,22 +29370,30 @@ ], "instructions": [ [ - "SCVTF" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_f32_u32", + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u8]", "arguments": [ - "uint32_t a" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24261,27 +29401,30 @@ ], "instructions": [ [ - "UCVTF" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_n_f32_s32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s16]", "arguments": [ - "int32_t a", - "const int n" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24289,27 +29432,33 @@ ], "instructions": [ [ - "SCVTF" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_n_f32_u32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s32]", "arguments": [ - "uint32_t a", - "const int n" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24317,27 +29466,33 @@ ], "instructions": [ [ - "UCVTF" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_n_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s8]", "arguments": [ - "float32_t a", - "const int n" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24345,27 +29500,33 @@ ], "instructions": [ [ - "FCVTZS" + "CMPGT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_n_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u16]", "arguments": [ - "float32_t a", - "const int n" + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.H" }, - "n": { - "minimum": 1, - "maximum": 32 + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24373,22 +29534,33 @@ ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_s32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u32]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "int32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24396,22 +29568,33 @@ ], "instructions": [ [ - "FCVTZS" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvts_u32_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u8]", "arguments": [ - "float32_t a" + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24419,22 +29602,33 @@ ], "instructions": [ [ - "FCVTZU" + "CMPHI" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtx_f32_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s16]", "arguments": [ - "float64x2_t a" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24442,26 +29636,30 @@ ], "instructions": [ [ - "FCVTXN" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtx_high_f32_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s32]", "arguments": [ - "float32x2_t r", - "float64x2_t a" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S" }, - "r": { - "register": "Vd.2S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24469,22 +29667,30 @@ ], "instructions": [ [ - "FCVTXN2" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vcvtxd_f32_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s8]", "arguments": [ - "float64_t a" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24492,26 +29698,30 @@ ], "instructions": [ [ - "FCVTXN" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdiv_f16", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u16]", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24519,26 +29729,30 @@ ], "instructions": [ [ - "FDIV" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdiv_f32", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u32]", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24546,26 +29760,30 @@ ], "instructions": [ [ - "FDIV" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdiv_f64", + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u8]", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Dm" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -24573,54 +29791,61 @@ ], "instructions": [ [ - "FDIV" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdivh_f16", + "SIMD_ISA": "SVE", + "name": "svcmple[_f16]", "arguments": [ - "float16_t a", - "float16_t b" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "float16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Hm" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FDIV" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdivq_f16", + "SIMD_ISA": "SVE", + "name": "svcmple[_f32]", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24628,26 +29853,30 @@ ], "instructions": [ [ - "FDIV" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdivq_f32", + "SIMD_ISA": "SVE", + "name": "svcmple[_f64]", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -24655,26 +29884,30 @@ ], "instructions": [ [ - "FDIV" + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdivq_f64", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f16]", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24682,109 +29915,101 @@ ], "instructions": [ [ - "FDIV" + "FCMLE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f32]", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "int8x8_t b", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SDOT" + "FCMLE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f64]", "arguments": [ - "uint32x2_t r", - "uint8x8_t a", - "uint8x8_t b", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.D[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UDOT" + "FCMLE" + ], + [ + "FCMGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s16]", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "int8x16_t b", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.H" }, - "lane": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.H[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -24792,35 +30017,33 @@ ], "instructions": [ [ - "SDOT" + "CMPLE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s32]", "arguments": [ - "uint32x2_t r", - "uint8x8_t a", - "uint8x16_t b", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.S[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -24828,173 +30051,169 @@ ], "instructions": [ [ - "UDOT" + "CMPLE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s64]", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.D" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.D[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SDOT" + "CMPLE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdot_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s8]", "arguments": [ - "uint32x2_t r", - "uint8x8_t a", - "uint8x8_t b" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op1": { + "register": "Zop1.B" }, - "b": { - "register": "Vm.8B" + "op2": { + "register": "Zop2.B[*]" }, - "r": { - "register": "Vd.2S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UDOT" + "CMPLE" + ], + [ + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u16]", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "int8x8_t b", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.H" }, - "lane": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.H[*]" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SDOT" + "CMPLS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u32]", "arguments": [ - "uint32x4_t r", - "uint8x16_t a", - "uint8x8_t b", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "op2": { + "register": "Zop2.S[*]" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UDOT" + "CMPLS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u64]", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "int8x16_t b", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.D" }, - "lane": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.D[*]" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25002,35 +30221,33 @@ ], "instructions": [ [ - "SDOT" + "CMPLS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u8]", "arguments": [ - "uint32x4_t r", - "uint8x16_t a", - "uint8x16_t b", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.4B" + "op1": { + "register": "Zop1.B" }, - "lane": { - "minimum": 0, - "maximum": 3 + "op2": { + "register": "Zop2.B[*]" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -25038,151 +30255,157 @@ ], "instructions": [ [ - "UDOT" + "CMPLS" + ], + [ + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_s32", + "SIMD_ISA": "SVE", + "name": "svcmple[_s16]", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "int8x16_t b" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.H" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SDOT" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdotq_u32", + "SIMD_ISA": "SVE", + "name": "svcmple[_s32]", "arguments": [ - "uint32x4_t r", - "uint8x16_t a", - "uint8x16_t b" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op1": { + "register": "Zop1.S" }, - "b": { - "register": "Vm.16B" + "op2": { + "register": "Zop2.S" }, - "r": { - "register": "Vd.4S" + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "UDOT" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_f16", + "SIMD_ISA": "SVE", + "name": "svcmple[_s64]", "arguments": [ - "float16x4_t vec", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_f32", + "SIMD_ISA": "SVE", + "name": "svcmple[_s8]", "arguments": [ - "float32x2_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_f64", + "SIMD_ISA": "SVE", + "name": "svcmple[_u16]", "arguments": [ - "float64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25190,356 +30413,389 @@ ], "instructions": [ [ - "DUP" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_p16", + "SIMD_ISA": "SVE", + "name": "svcmple[_u32]", "arguments": [ - "poly16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_p64", + "SIMD_ISA": "SVE", + "name": "svcmple[_u64]", "arguments": [ - "poly64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_p8", + "SIMD_ISA": "SVE", + "name": "svcmple[_u8]", "arguments": [ - "poly8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_s16", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s16]", "arguments": [ - "int16x4_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" + ], + [ + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s32]", "arguments": [ - "int32x2_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" + ], + [ + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_s64", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s8]", "arguments": [ - "int64x1_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" + ], + [ + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_s8", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u16]", "arguments": [ - "int8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLS" + ], + [ + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_u16", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u32]", "arguments": [ - "uint16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLS" + ], + [ + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u8]", "arguments": [ - "uint32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLS" + ], + [ + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_u64", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s16]", "arguments": [ - "uint64x1_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_lane_u8", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s32]", "arguments": [ - "uint8x8_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s8]", "arguments": [ - "float16x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -25547,27 +30803,30 @@ ], "instructions": [ [ - "DUP" + "CMPLE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u16]", "arguments": [ - "float32x4_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25575,27 +30834,30 @@ ], "instructions": [ [ - "DUP" + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_f64", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u32]", "arguments": [ - "float64x2_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -25603,27 +30865,30 @@ ], "instructions": [ [ - "DUP" + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_p16", + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u8]", "arguments": [ - "poly16x8_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -25631,27 +30896,30 @@ ], "instructions": [ [ - "DUP" + "CMPLS" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_p64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_f16]", "arguments": [ - "poly64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25659,27 +30927,30 @@ ], "instructions": [ [ - "DUP" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_p8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_f32]", "arguments": [ - "poly8x16_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -25687,27 +30958,30 @@ ], "instructions": [ [ - "DUP" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_s16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_f64]", "arguments": [ - "int16x8_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25715,27 +30989,30 @@ ], "instructions": [ [ - "DUP" + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f16]", "arguments": [ - "int32x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25743,27 +31020,33 @@ ], "instructions": [ [ - "DUP" + "FCMLT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_s64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f32]", "arguments": [ - "int64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -25771,27 +31054,33 @@ ], "instructions": [ [ - "DUP" + "FCMLT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_s8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f64]", "arguments": [ - "int8x16_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25799,27 +31088,33 @@ ], "instructions": [ [ - "DUP" + "FCMLT" + ], + [ + "FCMGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_u16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s16]", "arguments": [ - "uint16x8_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -25827,27 +31122,33 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s32]", "arguments": [ - "uint32x4_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -25855,27 +31156,33 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_u64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s64]", "arguments": [ - "uint64x2_t vec", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25883,27 +31190,33 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_laneq_u8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s8]", "arguments": [ - "uint8x16_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -25911,72 +31224,101 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_f16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u16]", "arguments": [ - "float16_t value" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_f32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u32]", "arguments": [ - "float32_t value" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_f64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u64]", "arguments": [ - "float64_t value" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "float64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -25984,301 +31326,383 @@ ], "instructions": [ [ - "INS" + "CMPLO" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_p16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u8]", "arguments": [ - "poly16_t value" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "poly16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_p64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_s16]", "arguments": [ - "poly64_t value" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "poly64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "INS" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_p8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_s32]", "arguments": [ - "poly8_t value" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "poly8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_s16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_s64]", "arguments": [ - "int16_t value" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_s32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_s8]", "arguments": [ - "int32_t value" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "int32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPGT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_s64", + "SIMD_ISA": "SVE", + "name": "svcmplt[_u16]", "arguments": [ - "int64_t value" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_s8", + "SIMD_ISA": "SVE", + "name": "svcmplt[_u32]", "arguments": [ - "int8_t value" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_u16", + "SIMD_ISA": "SVE", + "name": "svcmplt[_u64]", "arguments": [ - "uint16_t value" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_u32", + "SIMD_ISA": "SVE", + "name": "svcmplt[_u8]", "arguments": [ - "uint32_t value" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPHI" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_u64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s16]", "arguments": [ - "uint64_t value" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "uint64x1_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "INS" + "CMPLT" + ], + [ + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdup_n_u8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s32]", "arguments": [ - "uint8_t value" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "uint8x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_lane_p8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s8]", "arguments": [ - "poly8x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "poly8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26286,27 +31710,33 @@ ], "instructions": [ [ - "DUP" + "CMPLT" + ], + [ + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_lane_s8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u16]", "arguments": [ - "int8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" ], "return_type": { - "value": "int8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26314,27 +31744,33 @@ ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_lane_u8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u32]", "arguments": [ - "uint8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" ], "return_type": { - "value": "uint8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26342,27 +31778,33 @@ ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_laneq_p8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u8]", "arguments": [ - "poly8x16_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" ], "return_type": { - "value": "poly8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26370,27 +31812,33 @@ ], "instructions": [ [ - "DUP" + "CMPLO" + ], + [ + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_laneq_s8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s16]", "arguments": [ - "int8x16_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "int8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26398,27 +31846,30 @@ ], "instructions": [ [ - "DUP" + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupb_laneq_u8", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s32]", "arguments": [ - "uint8x16_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "uint8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26426,27 +31877,30 @@ ], "instructions": [ [ - "DUP" + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_lane_f64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s8]", "arguments": [ - "float64x1_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "float64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26454,27 +31908,30 @@ ], "instructions": [ [ - "DUP" + "CMPLT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_lane_s64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u16]", "arguments": [ - "int64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26482,27 +31939,30 @@ ], "instructions": [ [ - "DUP" + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_lane_u64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u32]", "arguments": [ - "uint64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26510,27 +31970,30 @@ ], "instructions": [ [ - "DUP" + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_laneq_f64", + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u8]", "arguments": [ - "float64x2_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" ], "return_type": { - "value": "float64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26538,27 +32001,30 @@ ], "instructions": [ [ - "DUP" + "CMPLO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_laneq_s64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_f16]", "arguments": [ - "int64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "int64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26566,27 +32032,30 @@ ], "instructions": [ [ - "DUP" + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupd_laneq_u64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_f32]", "arguments": [ - "uint64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "uint64_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26594,27 +32063,30 @@ ], "instructions": [ [ - "DUP" + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_lane_f16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_f64]", "arguments": [ - "float16x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "float16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -26622,27 +32094,30 @@ ], "instructions": [ [ - "DUP" + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_lane_p16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f16]", "arguments": [ - "poly16x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "poly16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26650,27 +32125,33 @@ ], "instructions": [ [ - "DUP" + "FCMNE" + ], + [ + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_lane_s16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f32]", "arguments": [ - "int16x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26678,27 +32159,33 @@ ], "instructions": [ [ - "DUP" + "FCMNE" + ], + [ + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_lane_u16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f64]", "arguments": [ - "uint16x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -26706,27 +32193,33 @@ ], "instructions": [ [ - "DUP" + "FCMNE" + ], + [ + "FCMNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s16]", "arguments": [ - "float16x8_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int16_t op2" ], "return_type": { - "value": "float16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -26734,27 +32227,33 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_laneq_p16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s32]", "arguments": [ - "poly16x8_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int32_t op2" ], "return_type": { - "value": "poly16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -26762,27 +32261,33 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_laneq_s16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s64]", "arguments": [ - "int16x8_t vec", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "int64_t op2" ], "return_type": { - "value": "int16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -26790,27 +32295,33 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vduph_laneq_u16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s8]", "arguments": [ - "uint16x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int8_t op2" ], "return_type": { - "value": "uint16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -26818,87 +32329,101 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_f16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u16]", "arguments": [ - "float16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_f32", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u32]", "arguments": [ - "float32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_f64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u64]", "arguments": [ - "float64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -26906,356 +32431,383 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_p16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u8]", "arguments": [ - "poly16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" ], "return_type": { - "value": "poly16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_p64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_s16]", "arguments": [ - "poly64x1_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" ], "return_type": { - "value": "poly64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_p8", + "SIMD_ISA": "SVE", + "name": "svcmpne[_s32]", "arguments": [ - "poly8x8_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" ], "return_type": { - "value": "poly8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_s16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_s64]", "arguments": [ - "int16x4_t vec", - "const int lane" + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcmpne[_s8]", "arguments": [ - "int32x2_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_s64", + "SIMD_ISA": "SVE", + "name": "svcmpne[_u16]", "arguments": [ - "int64x1_t vec", - "const int lane" + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_s8", + "SIMD_ISA": "SVE", + "name": "svcmpne[_u32]", "arguments": [ - "int8x8_t vec", - "const int lane" + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_u16", + "SIMD_ISA": "SVE", + "name": "svcmpne[_u64]", "arguments": [ - "uint16x4_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" ], "return_type": { - "value": "uint16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.4H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcmpne[_u8]", "arguments": [ - "uint32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" ], "return_type": { - "value": "uint32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.2S" + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_u64", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s16]", "arguments": [ - "uint64x1_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "int64_t op2" ], "return_type": { - "value": "uint64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.1D" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_lane_u8", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s32]", "arguments": [ - "uint8x8_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "int64_t op2" ], "return_type": { - "value": "uint8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.8B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_f16", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s8]", "arguments": [ - "float16x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "int64_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -27263,27 +32815,33 @@ ], "instructions": [ [ - "DUP" + "CMPNE" + ], + [ + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s16]", "arguments": [ - "float32x4_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27291,27 +32849,30 @@ ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_f64", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s32]", "arguments": [ - "float64x2_t vec", - "const int lane" + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -27319,27 +32880,30 @@ ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_p16", + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s8]", "arguments": [ - "poly16x8_t vec", - "const int lane" + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" ], "return_type": { - "value": "poly16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.B" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -27347,27 +32911,30 @@ ], "instructions": [ [ - "DUP" + "CMPNE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_p64", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f16]", "arguments": [ - "poly64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" ], "return_type": { - "value": "poly64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27375,27 +32942,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_p8", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f32]", "arguments": [ - "poly8x16_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" ], "return_type": { - "value": "poly8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -27403,27 +32973,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_s16", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f64]", "arguments": [ - "int16x8_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" ], "return_type": { - "value": "int16x8_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.8H" + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -27431,27 +33004,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f16]", "arguments": [ - "int32x4_t vec", - "const int lane" + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" ], "return_type": { - "value": "int32x4_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op1": { + "register": "Zop1.H" }, - "vec": { - "register": "Vn.4S" + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27459,27 +33035,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_s64", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f32]", "arguments": [ - "int64x2_t vec", - "const int lane" + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" ], "return_type": { - "value": "int64x2_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op1": { + "register": "Zop1.S" }, - "vec": { - "register": "Vn.2D" + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -27487,27 +33066,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_s8", + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f64]", "arguments": [ - "int8x16_t vec", - "const int lane" + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" ], "return_type": { - "value": "int8x16_t" + "value": "svbool_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "op1": { + "register": "Zop1.D" }, - "vec": { - "register": "Vn.16B" + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -27515,27 +33097,30 @@ ], "instructions": [ [ - "DUP" + "FCMUO" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_u16", + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_m", "arguments": [ - "uint16x8_t vec", - "const int lane" + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "inactive": { + "register": "Zinactive.H|Ztied.H" }, - "vec": { - "register": "Vn.8H" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27543,27 +33128,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_x", "arguments": [ - "uint32x4_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Zop.H|Ztied.H" }, - "vec": { - "register": "Vn.4S" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27571,27 +33159,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_u64", + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_z", "arguments": [ - "uint64x2_t vec", - "const int lane" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zop.H" }, - "vec": { - "register": "Vn.2D" + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -27599,27 +33190,31 @@ ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_laneq_u8", + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_m", "arguments": [ - "uint8x16_t vec", - "const int lane" + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 + "inactive": { + "register": "Zinactive.S|Ztied.S" }, - "vec": { - "register": "Vn.16B" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -27627,72 +33222,93 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_f16", + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_x", "arguments": [ - "float16_t value" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "float16x8_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_f32", + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_z", "arguments": [ - "float32_t value" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "float32x4_t" + "value": "svint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_f64", + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_m", "arguments": [ - "float64_t value" + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "float64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -27700,301 +33316,375 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_p16", + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_x", "arguments": [ - "poly16_t value" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "poly16x8_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_p64", + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_z", "arguments": [ - "poly64_t value" + "svbool_t pg", + "svint64_t op" ], "return_type": { - "value": "poly64x2_t" + "value": "svint64_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_p8", + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_m", "arguments": [ - "poly8_t value" + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "poly8x16_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_s16", + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_x", "arguments": [ - "int16_t value" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int16x8_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_s32", + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_z", "arguments": [ - "int32_t value" + "svbool_t pg", + "svint8_t op" ], "return_type": { - "value": "int32x4_t" + "value": "svint8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_s64", + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_m", "arguments": [ - "int64_t value" + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "int64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_s8", + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_x", "arguments": [ - "int8_t value" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "int8x16_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_u16", + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_z", "arguments": [ - "uint16_t value" + "svbool_t pg", + "svuint16_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_u32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_m", "arguments": [ - "uint32_t value" + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_u64", + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_x", "arguments": [ - "uint64_t value" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdupq_n_u8", + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_z", "arguments": [ - "uint8_t value" + "svbool_t pg", + "svuint32_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_lane_f32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_m", "arguments": [ - "float32x2_t vec", - "const int lane" + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "float32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "inactive": { + "register": "Zinactive.D|Ztied.D" }, - "vec": { - "register": "Vn.2S" + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -28002,27 +33692,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_lane_s32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_x", "arguments": [ - "int32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "int32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zop.D|Ztied.D" }, - "vec": { - "register": "Vn.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -28030,27 +33723,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_lane_u32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_z", "arguments": [ - "uint32x2_t vec", - "const int lane" + "svbool_t pg", + "svuint64_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "op": { + "register": "Zop.D" }, - "vec": { - "register": "Vn.2S" + "pg": { + "register": "Pg.D" } }, "Architectures": [ @@ -28058,27 +33754,31 @@ ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_laneq_f32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_m", "arguments": [ - "float32x4_t vec", - "const int lane" + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "float32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "inactive": { + "register": "Zinactive.B|Ztied.B" }, - "vec": { - "register": "Vn.4S" + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -28086,27 +33786,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_laneq_s32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_x", "arguments": [ - "int32x4_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "int32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Zop.B|Ztied.B" }, - "vec": { - "register": "Vn.4S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -28114,27 +33817,30 @@ ], "instructions": [ [ - "DUP" + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vdups_laneq_u32", + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_z", "arguments": [ - "uint32x4_t vec", - "const int lane" + "svbool_t pg", + "svuint8_t op" ], "return_type": { - "value": "uint32_t" + "value": "svuint8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "op": { + "register": "Zop.B" }, - "vec": { - "register": "Vn.4S" + "pg": { + "register": "Pg.B" } }, "Architectures": [ @@ -28142,779 +33848,845 @@ ], "instructions": [ [ - "DUP" + "MOVPRFX", + "CNOT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_s16", + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_m", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "svuint16_t inactive", + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "int16x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.H" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_s32", + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_x", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "int32x4_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H|Ztied.H" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.H" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_s64", + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_z", "arguments": [ - "int64x2_t a", - "int64x2_t b", - "int64x2_t c" + "svbool_t pg", + "svfloat16_t op" ], "return_type": { - "value": "int64x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.H" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.H" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_s8", + "SIMD_ISA": "SVE", + "name": "svcnt[_f32]_m", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "int8x16_t c" + "svuint32_t inactive", + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "int8x16_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.S" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_u16", + "SIMD_ISA": "SVE", + "name": "svcnt[_f32]_x", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "uint16x8_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.S|Ztied.S" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.S" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_u32", + "SIMD_ISA": "SVE", + "name": "svcnt[_f32]_z", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "svbool_t pg", + "svfloat32_t op" ], "return_type": { - "value": "uint32x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.S" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.S" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_u64", + "SIMD_ISA": "SVE", + "name": "svcnt[_f64]_m", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "uint64x2_t c" + "svuint64_t inactive", + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "uint64x2_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.D" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor3q_u8", + "SIMD_ISA": "SVE", + "name": "svcnt[_f64]_x", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "uint8x16_t c" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "uint8x16_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "op": { + "register": "Zop.D|Ztied.D" }, - "b": {}, - "c": {} + "pg": { + "register": "Pg.D" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "EOR3" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor_s16", + "SIMD_ISA": "SVE", + "name": "svcnt[_f64]_z", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "svbool_t pg", + "svfloat64_t op" ], "return_type": { - "value": "int16x4_t" + "value": "svuint64_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.D" }, - "b": { - "register": "Vm.8B" + "pg": { + "register": "Pg.D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor_s32", + "SIMD_ISA": "SVE", + "name": "svcnt[_s16]_m", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int32x2_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "inactive": { + "register": "Zinactive.H|Ztied.H" }, - "b": { - "register": "Vm.8B" + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor_s64", + "SIMD_ISA": "SVE", + "name": "svcnt[_s16]_x", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int64x1_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.H|Ztied.H" }, - "b": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor_s8", + "SIMD_ISA": "SVE", + "name": "svcnt[_s16]_z", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "svbool_t pg", + "svint16_t op" ], "return_type": { - "value": "int8x8_t" + "value": "svuint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "op": { + "register": "Zop.H" }, - "b": { - "register": "Vm.8B" + "pg": { + "register": "Pg.H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor_u16", + "SIMD_ISA": "SVE", + "name": "svcnt[_s32]_m", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "svuint32_t inactive", + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint16x4_t" + "value": "svuint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "inactive": { + "register": "Zinactive.S|Ztied.S" }, - "b": { - "register": "Vm.8B" + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "EOR" + "CNT" + ], + [ + "MOVPRFX", + "CNT" ] ] }, { - "SIMD_ISA": "Neon", - "name": "veor_u32", + "SIMD_ISA": "SVE", + "name": "svcnt[_s32]_x", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "svbool_t pg", + "svint32_t op" ], "return_type": { - "value": "uint32x2_t" + "value": "svuint32_t" }, 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"register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 3 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "EXT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vext_s32", + "arguments": [ + "int32x2_t a", + "int32x2_t b", + "const int n" + ], + "return_type": { + "value": "int32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 1 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "EXT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vext_s64", + "arguments": [ + "int64x1_t a", + "int64x1_t b", + "const int n" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 0 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "EXT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vext_s8", + "arguments": [ + "int8x8_t a", + "int8x8_t b", + "const int n" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "EXT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vext_u16", + "arguments": [ + "uint16x4_t a", + "uint16x4_t b", + "const int n" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + }, + "n": { "minimum": 0, "maximum": 3 } @@ -30097,7 +225653,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H " + "register": "Vd.4H" }, "b": { "register": "Vn.4H" @@ -30680,7 +226236,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H " + "register": "Vd.8H" }, "b": { "register": "Vn.8H" @@ -30846,8 +226402,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -30875,8 +226435,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -30908,8 +226472,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -30941,8 +226509,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -30974,8 +226546,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31006,8 +226582,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31034,8 +226614,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31063,8 +226647,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31096,8 +226684,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31129,8 +226721,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31162,8 +226758,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31194,8 +226794,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31222,8 +226826,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31251,8 +226859,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31284,8 +226896,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31317,8 +226933,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31350,8 +226970,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31382,8 +227006,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31410,8 +227038,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31439,8 +227071,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31472,8 +227108,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31505,8 +227145,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31538,8 +227182,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31570,8 +227218,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31911,7 +227563,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H " + "register": "Vd.4H" }, "b": { "register": "Vn.4H" @@ -32492,7 +228144,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H " + "register": "Vd.8H" }, "b": { "register": "Vn.8H" @@ -34868,230 +230520,6 @@ ] ] }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_u64", - "arguments": [ - "uint64_t const * ptr", - "uint64x1_t src", - "const int lane" - ], - "return_type": { - "value": "uint64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_s64", - "arguments": [ - "int64_t const * ptr", - "int64x1_t src", - "const int lane" - ], - "return_type": { - "value": "int64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_u64", - "arguments": [ - "uint64_t const * ptr", - "uint64x2_t src", - "const int lane" - ], - "return_type": { - "value": "uint64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_s64", - "arguments": [ - "int64_t const * ptr", - "int64x2_t src", - "const int lane" - ], - "return_type": { - "value": "int64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_p64", - "arguments": [ - "poly64_t const * ptr", - "poly64x1_t src", - "const int lane" - ], - "return_type": { - "value": "poly64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_p64", - "arguments": [ - "poly64_t const * ptr", - "poly64x2_t src", - "const int lane" - ], - "return_type": { - "value": "poly64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_f64", - "arguments": [ - "float64_t const * ptr", - "float64x2_t src", - "const int lane" - ], - "return_type": { - "value": "float64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, { "SIMD_ISA": "Neon", "name": "vld1_dup_f16", @@ -39947,7 +235375,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -39981,7 +235412,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40015,7 +235449,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40047,7 +235484,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40081,7 +235521,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40113,7 +235556,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -40147,7 +235593,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40181,7 +235630,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40215,7 +235667,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40247,7 +235702,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -40281,7 +235739,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40315,7 +235776,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40349,7 +235813,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40381,7 +235848,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -41104,7 +236574,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41138,7 +236611,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41172,7 +236648,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41204,7 +236683,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41238,7 +236720,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41270,7 +236755,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -41302,7 +236790,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41336,7 +236827,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41370,7 +236864,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41402,7 +236899,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -41434,7 +236934,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41468,7 +236971,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41502,7 +237008,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41534,7 +237043,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -42255,7 +237767,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42289,7 +237807,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42323,7 +237847,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42355,7 +237885,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42389,7 +237925,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42421,7 +237963,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -42455,7 +238003,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42489,7 +238043,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42523,7 +238083,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42555,7 +238121,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -42589,7 +238161,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42623,7 +238201,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42657,7 +238241,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42689,7 +238279,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -43412,7 +239008,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43446,7 +239048,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43480,7 +239088,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43512,7 +239126,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43546,7 +239166,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43578,7 +239204,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -43610,7 +239242,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43644,7 +239282,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43678,7 +239322,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43710,7 +239360,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -43742,7 +239398,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43776,7 +239438,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43810,7 +239478,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43842,7 +239516,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -44563,7 +240243,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44597,7 +240286,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44631,7 +240329,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44663,7 +240370,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44697,7 +240413,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44729,7 +240454,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -44763,7 +240497,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44797,7 +240540,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44831,7 +240583,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44863,7 +240624,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -44897,7 +240667,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44931,7 +240710,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44965,7 +240753,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44997,7 +240794,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -45023,842 +240829,12 @@ }, "Arguments_Preparation": { "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_p64", - "arguments": [ - "poly64_t const * ptr" - ], - "return_type": { - "value": "poly64x1x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "A32", - "A64" - ], - "instructions": [ - [ - "LD1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_p8", - "arguments": [ - "poly8_t const * ptr" - ], - "return_type": { - "value": "poly8x8x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_s16", - "arguments": [ - "int16_t const * ptr" - ], - "return_type": { - "value": "int16x4x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_s32", - "arguments": [ - "int32_t const * ptr" - ], - "return_type": { - "value": "int32x2x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_s64", - "arguments": [ - "int64_t const * ptr" - ], - "return_type": { - "value": "int64x1x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_s8", - "arguments": [ - "int8_t const * ptr" - ], - "return_type": { - "value": "int8x8x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_u16", - "arguments": [ - "uint16_t const * ptr" - ], - "return_type": { - "value": "uint16x4x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_u32", - "arguments": [ - "uint32_t const * ptr" - ], - "return_type": { - "value": "uint32x2x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_u64", - "arguments": [ - "uint64_t const * ptr" - ], - "return_type": { - "value": "uint64x1x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4_u8", - "arguments": [ - "uint8_t const * ptr" - ], - "return_type": { - "value": "uint8x8x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_f16", - "arguments": [ - "float16_t const * ptr" - ], - "return_type": { - "value": "float16x8x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_f32", - "arguments": [ - "float32_t const * ptr" - ], - "return_type": { - "value": "float32x4x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_f64", - "arguments": [ - "float64_t const * ptr" - ], - "return_type": { - "value": "float64x2x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_p16", - "arguments": [ - "poly16_t const * ptr" - ], - "return_type": { - "value": "poly16x8x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_p64", - "arguments": [ - "poly64_t const * ptr" - ], - "return_type": { - "value": "poly64x2x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_p8", - "arguments": [ - "poly8_t const * ptr" - ], - "return_type": { - "value": "poly8x16x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_s16", - "arguments": [ - "int16_t const * ptr" - ], - "return_type": { - "value": "int16x8x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_s32", - "arguments": [ - "int32_t const * ptr" - ], - "return_type": { - "value": "int32x4x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_s64", - "arguments": [ - "int64_t const * ptr" - ], - "return_type": { - "value": "int64x2x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_s8", - "arguments": [ - "int8_t const * ptr" - ], - "return_type": { - "value": "int8x16x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_u16", - "arguments": [ - "uint16_t const * ptr" - ], - "return_type": { - "value": "uint16x8x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_u32", - "arguments": [ - "uint32_t const * ptr" - ], - "return_type": { - "value": "uint32x4x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_u64", - "arguments": [ - "uint64_t const * ptr" - ], - "return_type": { - "value": "uint64x2x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_dup_u8", - "arguments": [ - "uint8_t const * ptr" - ], - "return_type": { - "value": "uint8x16x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4R" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_f16", - "arguments": [ - "float16_t const * ptr" - ], - "return_type": { - "value": "float16x8x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_f32", - "arguments": [ - "float32_t const * ptr" - ], - "return_type": { - "value": "float32x4x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_f64", - "arguments": [ - "float64_t const * ptr" - ], - "return_type": { - "value": "float64x2x4_t" - }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_lane_f16", - "arguments": [ - "float16_t const * ptr", - "float16x8x4_t src", - "const int lane" - ], - "return_type": { - "value": "float16x8x4_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt4.8H" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_lane_f32", - "arguments": [ - "float32_t const * ptr", - "float32x4x4_t src", - "const int lane" - ], - "return_type": { - "value": "float32x4x4_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt4.4S" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_lane_f64", - "arguments": [ - "float64_t const * ptr", - "float64x2x4_t src", - "const int lane" - ], - "return_type": { - "value": "float64x2x4_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt4.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_lane_p16", - "arguments": [ - "poly16_t const * ptr", - "poly16x8x4_t src", - "const int lane" - ], - "return_type": { - "value": "poly16x8x4_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt4.8H" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "LD4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vld4q_lane_p64", - "arguments": [ - "poly64_t const * ptr", - "poly64x2x4_t src", - "const int lane" - ], - "return_type": { - "value": "poly64x2x4_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt4.2D" + "register": "Xn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -45869,57 +240845,40 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_p8", + "name": "vld4_p64", "arguments": [ - "poly8_t const * ptr", - "poly8x16x4_t src", - "const int lane" + "poly64_t const * ptr" ], "return_type": { - "value": "poly8x16x4_t" + "value": "poly64x1x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.16B" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "LD4" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_s16", + "name": "vld4_p8", "arguments": [ - "int16_t const * ptr", - "int16x8x4_t src", - "const int lane" + "poly8_t const * ptr" ], "return_type": { - "value": "int16x8x4_t" + "value": "poly8x8x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.8H" } }, "Architectures": [ @@ -45935,25 +240894,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_s32", + "name": "vld4_s16", "arguments": [ - "int32_t const * ptr", - "int32x4x4_t src", - "const int lane" + "int16_t const * ptr" ], "return_type": { - "value": "int32x4x4_t" + "value": "int16x4x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.4S" } }, "Architectures": [ @@ -45969,28 +240919,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_s64", + "name": "vld4_s32", "arguments": [ - "int64_t const * ptr", - "int64x2x4_t src", - "const int lane" + "int32_t const * ptr" ], "return_type": { - "value": "int64x2x4_t" + "value": "int32x2x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -46001,57 +240944,41 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_s8", + "name": "vld4_s64", "arguments": [ - "int8_t const * ptr", - "int8x16x4_t src", - "const int lane" + "int64_t const * ptr" ], "return_type": { - "value": "int8x16x4_t" + "value": "int64x1x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD4" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_u16", + "name": "vld4_s8", "arguments": [ - "uint16_t const * ptr", - "uint16x8x4_t src", - "const int lane" + "int8_t const * ptr" ], "return_type": { - "value": "uint16x8x4_t" + "value": "int8x8x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.8H" } }, "Architectures": [ @@ -46067,25 +240994,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_u32", + "name": "vld4_u16", "arguments": [ - "uint32_t const * ptr", - "uint32x4x4_t src", - "const int lane" + "uint16_t const * ptr" ], "return_type": { - "value": "uint32x4x4_t" + "value": "uint16x4x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.4S" } }, "Architectures": [ @@ -46101,28 +241019,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_u64", + "name": "vld4_u32", "arguments": [ - "uint64_t const * ptr", - "uint64x2x4_t src", - "const int lane" + "uint32_t const * ptr" ], "return_type": { - "value": "uint64x2x4_t" + "value": "uint32x2x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -46133,44 +241044,37 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_lane_u8", + "name": "vld4_u64", "arguments": [ - "uint8_t const * ptr", - "uint8x16x4_t src", - "const int lane" + "uint64_t const * ptr" ], "return_type": { - "value": "uint8x16x4_t" + "value": "uint64x1x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" - }, - "src": { - "register": "Vt4.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD4" + "LD1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_p16", + "name": "vld4_u8", "arguments": [ - "poly16_t const * ptr" + "uint8_t const * ptr" ], "return_type": { - "value": "poly16x8x4_t" + "value": "uint8x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46190,12 +241094,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vld4q_p64", + "name": "vld4q_dup_f16", "arguments": [ - "poly64_t const * ptr" + "float16_t const * ptr" ], "return_type": { - "value": "poly64x2x4_t" + "value": "float16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46203,22 +241107,24 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_p8", + "name": "vld4q_dup_f32", "arguments": [ - "poly8_t const * ptr" + "float32_t const * ptr" ], "return_type": { - "value": "poly8x16x4_t" + "value": "float32x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46232,18 +241138,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_s16", + "name": "vld4q_dup_f64", "arguments": [ - "int16_t const * ptr" + "float64_t const * ptr" ], "return_type": { - "value": "int16x8x4_t" + "value": "float64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46251,24 +241157,22 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_s32", + "name": "vld4q_dup_p16", "arguments": [ - "int32_t const * ptr" + "poly16_t const * ptr" ], "return_type": { - "value": "int32x4x4_t" + "value": "poly16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46282,18 +241186,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_s64", + "name": "vld4q_dup_p64", "arguments": [ - "int64_t const * ptr" + "poly64_t const * ptr" ], "return_type": { - "value": "int64x2x4_t" + "value": "poly64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46305,18 +241209,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_s8", + "name": "vld4q_dup_p8", "arguments": [ - "int8_t const * ptr" + "poly8_t const * ptr" ], "return_type": { - "value": "int8x16x4_t" + "value": "poly8x16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46330,18 +241234,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_u16", + "name": "vld4q_dup_s16", "arguments": [ - "uint16_t const * ptr" + "int16_t const * ptr" ], "return_type": { - "value": "uint16x8x4_t" + "value": "int16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46355,18 +241259,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_u32", + "name": "vld4q_dup_s32", "arguments": [ - "uint32_t const * ptr" + "int32_t const * ptr" ], "return_type": { - "value": "uint32x4x4_t" + "value": "int32x4x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46380,18 +241284,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_u64", + "name": "vld4q_dup_s64", "arguments": [ - "uint64_t const * ptr" + "int64_t const * ptr" ], "return_type": { - "value": "uint64x2x4_t" + "value": "int64x2x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46403,18 +241307,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vld4q_u8", + "name": "vld4q_dup_s8", "arguments": [ - "uint8_t const * ptr" + "int8_t const * ptr" ], "return_type": { - "value": "uint8x16x4_t" + "value": "int8x16x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46428,18 +241332,18 @@ ], "instructions": [ [ - "LD4" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vldrq_p128", + "name": "vld4q_dup_u16", "arguments": [ - "poly128_t const * ptr" + "uint16_t const * ptr" ], "return_type": { - "value": "poly128_t" + "value": "uint16x8x4_t" }, "Arguments_Preparation": { "ptr": { @@ -46447,115 +241351,101 @@ } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "LDR" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_f16", + "name": "vld4q_dup_u32", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "uint32_t const * ptr" ], "return_type": { - "value": "float16x4_t" + "value": "uint32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_f32", + "name": "vld4q_dup_u64", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint64_t const * ptr" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_f64", + "name": "vld4q_dup_u8", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "uint8_t const * ptr" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4R" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_s16", + "name": "vld4q_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float16_t const * ptr" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -46565,26 +241455,22 @@ ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_s32", + "name": "vld4q_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float32_t const * ptr" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -46594,55 +241480,63 @@ ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_s8", + "name": "vld4q_f64", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "float64_t const * ptr" ], "return_type": { - "value": "int8x8_t" + "value": "float64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_u16", + "name": "vld4q_lane_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float16_t const * ptr", + "float16x8x4_t src", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -46652,26 +241546,40 @@ ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_u32", + "name": "vld4q_lane_f32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "float32_t const * ptr", + "float32x4x4_t src", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -46681,295 +241589,460 @@ ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmax_u8", + "name": "vld4q_lane_f64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float64_t const * ptr", + "float64x2x4_t src", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "float64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxh_f16", + "name": "vld4q_lane_p16", "arguments": [ - "float16_t a", - "float16_t b" + "poly16_t const * ptr", + "poly16x8x4_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "poly16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Hm" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnm_f16", + "name": "vld4q_lane_p64", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly64_t const * ptr", + "poly64x2x4_t src", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "poly64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnm_f32", + "name": "vld4q_lane_p8", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "poly8_t const * ptr", + "poly8x16x4_t src", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnm_f64", + "name": "vld4q_lane_s16", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int16_t const * ptr", + "int16x8x4_t src", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "int16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Dm" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmh_f16", + "name": "vld4q_lane_s32", "arguments": [ - "float16_t a", - "float16_t b" + "int32_t const * ptr", + "int32x4x4_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "int32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Hm" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmq_f16", + "name": "vld4q_lane_s64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int64_t const * ptr", + "int64x2x4_t src", + "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "int64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmq_f32", + "name": "vld4q_lane_s8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int8_t const * ptr", + "int8x16x4_t src", + "const int lane" ], "return_type": { - "value": "float32x4_t" + "value": "int8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmq_f64", + "name": "vld4q_lane_u16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint16_t const * ptr", + "uint16x8x4_t src", + "const int lane" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2D" + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNM" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmv_f16", + "name": "vld4q_lane_u32", "arguments": [ - "float16x4_t a" + "uint32_t const * ptr", + "uint32x4x4_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "uint32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmv_f32", + "name": "vld4q_lane_u64", "arguments": [ - "float32x2_t a" + "uint64_t const * ptr", + "uint64x2x4_t src", + "const int lane" ], "return_type": { - "value": "float32_t" + "value": "uint64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ @@ -46977,22 +242050,40 @@ ], "instructions": [ [ - "FMAXNMP" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmvq_f16", + "name": "vld4q_lane_u8", "arguments": [ - "float16x8_t a" + "uint8_t const * ptr", + "uint8x16x4_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "uint8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 15 + }, + "ptr": { + "register": "Xn" + }, + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -47000,45 +242091,47 @@ ], "instructions": [ [ - "FMAXNMP" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmvq_f32", + "name": "vld4q_p16", "arguments": [ - "float32x4_t a" + "poly16_t const * ptr" ], "return_type": { - "value": "float32_t" + "value": "poly16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMV" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxnmvq_f64", + "name": "vld4q_p64", "arguments": [ - "float64x2_t a" + "poly64_t const * ptr" ], "return_type": { - "value": "float64_t" + "value": "poly64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47046,54 +242139,47 @@ ], "instructions": [ [ - "FMAXNMP" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_f16", + "name": "vld4q_p8", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly8_t const * ptr" ], "return_type": { - "value": "float16x8_t" + "value": "poly8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_f32", + "name": "vld4q_s16", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int16_t const * ptr" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47103,82 +242189,70 @@ ], "instructions": [ [ - "FMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_f64", + "name": "vld4q_s32", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int32_t const * ptr" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_s16", + "name": "vld4q_s64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int64_t const * ptr" ], "return_type": { - "value": "int16x8_t" + "value": "int64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_s32", + "name": "vld4q_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int8_t const * ptr" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47188,26 +242262,22 @@ ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_s8", + "name": "vld4q_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16_t const * ptr" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x8x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47217,26 +242287,22 @@ ], "instructions": [ [ - "SMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_u16", + "name": "vld4q_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint32_t const * ptr" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47246,55 +242312,45 @@ ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_u32", + "name": "vld4q_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint64_t const * ptr" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxq_u8", + "name": "vld4q_u8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint8_t const * ptr" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" } }, "Architectures": [ @@ -47304,22 +242360,31 @@ ], "instructions": [ [ - "UMAX" + "LD4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_f16", + "name": "vldap1_lane_f64", "arguments": [ - "float16x4_t a" + "float64_t const * ptr", + "float64x1_t src", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -47327,22 +242392,31 @@ ], "instructions": [ [ - "FMAXP" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_f32", + "name": "vldap1_lane_p64", "arguments": [ - "float32x2_t a" + "poly64_t const * ptr", + "poly64x1_t src", + "const int lane" ], "return_type": { - "value": "float32_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -47350,22 +242424,31 @@ ], "instructions": [ [ - "FMAXP" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_s16", + "name": "vldap1_lane_s64", "arguments": [ - "int16x4_t a" + "int64_t const * ptr", + "int64x1_t src", + "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -47373,22 +242456,31 @@ ], "instructions": [ [ - "SMAXV" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_s32", + "name": "vldap1_lane_u64", "arguments": [ - "int32x2_t a" + "uint64_t const * ptr", + "uint64x1_t src", + "const int lane" ], "return_type": { - "value": "int32_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" } }, "Architectures": [ @@ -47396,22 +242488,31 @@ ], "instructions": [ [ - "SMAXP" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_s8", + "name": "vldap1q_lane_f64", "arguments": [ - "int8x8_t a" + "float64_t const * ptr", + "float64x2_t src", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -47419,22 +242520,31 @@ ], "instructions": [ [ - "SMAXV" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_u16", + "name": "vldap1q_lane_p64", "arguments": [ - "uint16x4_t a" + "poly64_t const * ptr", + "poly64x2_t src", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -47442,22 +242552,31 @@ ], "instructions": [ [ - "UMAXV" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_u32", + "name": "vldap1q_lane_s64", "arguments": [ - "uint32x2_t a" + "int64_t const * ptr", + "int64x2_t src", + "const int lane" ], "return_type": { - "value": "uint32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -47465,22 +242584,31 @@ ], "instructions": [ [ - "UMAXP" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxv_u8", + "name": "vldap1q_lane_u64", "arguments": [ - "uint8x8_t a" + "uint64_t const * ptr", + "uint64x2_t src", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" } }, "Architectures": [ @@ -47488,45 +242616,55 @@ ], "instructions": [ [ - "UMAXV" + "LDAP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_f16", + "name": "vldrq_p128", "arguments": [ - "float16x8_t a" + "poly128_t const * ptr" ], "return_type": { - "value": "float16_t" + "value": "poly128_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "LDR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_f32", + "name": "vluti2_lane_f16", "arguments": [ - "float32x4_t a" + "float16x4_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float32_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47534,22 +242672,31 @@ ], "instructions": [ [ - "FMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_f64", + "name": "vluti2_lane_p16", "arguments": [ - "float64x2_t a" + "poly16x4_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float64_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47557,22 +242704,31 @@ ], "instructions": [ [ - "FMAXP" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_s16", + "name": "vluti2_lane_p8", "arguments": [ - "int16x8_t a" + "poly8x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int16_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -47580,22 +242736,31 @@ ], "instructions": [ [ - "SMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_s32", + "name": "vluti2_lane_s16", "arguments": [ - "int32x4_t a" + "int16x4_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int32_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47603,21 +242768,30 @@ ], "instructions": [ [ - "SMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_s8", + "name": "vluti2_lane_s8", "arguments": [ - "int8x16_t a" + "int8x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { "register": "Vn.16B" } }, @@ -47626,21 +242800,30 @@ ], "instructions": [ [ - "SMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_u16", + "name": "vluti2_lane_u16", "arguments": [ - "uint16x8_t a" + "uint16x4_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { "register": "Vn.8H" } }, @@ -47649,22 +242832,31 @@ ], "instructions": [ [ - "UMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_u32", + "name": "vluti2_lane_u8", "arguments": [ - "uint32x4_t a" + "uint8x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint32_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -47672,22 +242864,31 @@ ], "instructions": [ [ - "UMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmaxvq_u8", + "name": "vluti2_laneq_f16", "arguments": [ - "uint8x16_t a" + "float16x4_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "uint8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47695,83 +242896,95 @@ ], "instructions": [ [ - "UMAXV" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_f16", + "name": "vluti2_laneq_p16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly16x4_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16x4_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.4H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_f32", + "name": "vluti2_laneq_p8", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "poly8x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_f64", + "name": "vluti2_laneq_s16", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int16x4_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Dm" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47779,200 +242992,223 @@ ], "instructions": [ [ - "FMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_s16", + "name": "vluti2_laneq_s8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int8x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_s32", + "name": "vluti2_laneq_u16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint16x4_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_s8", + "name": "vluti2_laneq_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8B" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_u16", + "name": "vluti2q_lane_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float16x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_u32", + "name": "vluti2q_lane_p16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "poly16x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint32x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmin_u8", + "name": "vluti2q_lane_p8", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "uint8x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8B" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminh_f16", + "name": "vluti2q_lane_s16", "arguments": [ - "float16_t a", - "float16_t b" + "int16x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Hm" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -47980,82 +243216,95 @@ ], "instructions": [ [ - "FMIN" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnm_f16", + "name": "vluti2q_lane_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnm_f32", + "name": "vluti2q_lane_u16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint16x8_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnm_f64", + "name": "vluti2q_lane_u8", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "uint8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Dm" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48063,110 +243312,127 @@ ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmh_f16", + "name": "vluti2q_laneq_f16", "arguments": [ - "float16_t a", - "float16_t b" + "float16x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Hm" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmq_f16", + "name": "vluti2q_laneq_p16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly16x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16x8_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.8H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmq_f32", + "name": "vluti2q_laneq_p8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "poly8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmq_f64", + "name": "vluti2q_laneq_s16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int16x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "index": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2D" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -48174,22 +243440,31 @@ ], "instructions": [ [ - "FMINNM" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmv_f16", + "name": "vluti2q_laneq_s8", "arguments": [ - "float16x4_t a" + "int8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48197,22 +243472,31 @@ ], "instructions": [ [ - "FMINNMP" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmv_f32", + "name": "vluti2q_laneq_u16", "arguments": [ - "float32x2_t a" + "uint16x8_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float32_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" } }, "Architectures": [ @@ -48220,22 +243504,31 @@ ], "instructions": [ [ - "FMINNMP" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmvq_f16", + "name": "vluti2q_laneq_u8", "arguments": [ - "float16x8_t a" + "uint8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48243,22 +243536,34 @@ ], "instructions": [ [ - "FMINNMP" + "LUTI2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmvq_f32", + "name": "vluti4q_lane_f16_x2", "arguments": [ - "float32x4_t a" + "float16x8x2_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float32_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ @@ -48266,22 +243571,34 @@ ], "instructions": [ [ - "FMINNMV" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminnmvq_f64", + "name": "vluti4q_lane_p16_x2", "arguments": [ - "float64x2_t a" + "poly16x8x2_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float64_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ @@ -48289,83 +243606,98 @@ ], "instructions": [ [ - "FMINNMP" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_f16", + "name": "vluti4q_lane_p8", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.8H" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_f32", + "name": "vluti4q_lane_s16_x2", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int16x8x2_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_f64", + "name": "vluti4q_lane_s8", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "float64x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "index": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.2D" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48373,196 +243705,235 @@ ], "instructions": [ [ - "FMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_s16", + "name": "vluti4q_lane_u16_x2", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint16x8x2_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8H" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_s32", + "name": "vluti4q_lane_u8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint8x16_t vn", + "uint8x8_t vm", + "const int index" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.4S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_s8", + "name": "vluti4q_laneq_f16_x2", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float16x8x2_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.16B" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_u16", + "name": "vluti4q_laneq_p16_x2", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly16x8x2_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "uint16x8_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_u32", + "name": "vluti4q_laneq_p8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "poly8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "index": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminq_u8", + "name": "vluti4q_laneq_s16_x2", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int16x8x2_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "index": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.16B" + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMIN" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_f16", + "name": "vluti4q_laneq_s8", "arguments": [ - "float16x4_t a" + "int8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48570,22 +243941,34 @@ ], "instructions": [ [ - "FMINP" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_f32", + "name": "vluti4q_laneq_u16_x2", "arguments": [ - "float32x2_t a" + "uint16x8x2_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "float32_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" } }, "Architectures": [ @@ -48593,22 +243976,31 @@ ], "instructions": [ [ - "FMINP" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_s16", + "name": "vluti4q_laneq_u8", "arguments": [ - "int16x4_t a" + "uint8x16_t vn", + "uint8x16_t vm", + "const int index" ], "return_type": { - "value": "int16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" } }, "Architectures": [ @@ -48616,68 +244008,83 @@ ], "instructions": [ [ - "SMINV" + "LUTI4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_s32", + "name": "vmax_f16", "arguments": [ - "int32x2_t a" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SMINP" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_s8", + "name": "vmax_f32", "arguments": [ - "int8x8_t a" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINV" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_u16", + "name": "vmax_f64", "arguments": [ - "uint16x4_t a" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "uint16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ @@ -48685,160 +244092,200 @@ ], "instructions": [ [ - "UMINV" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_u32", + "name": "vmax_s16", "arguments": [ - "uint32x2_t a" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint32_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINP" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminv_u8", + "name": "vmax_s32", "arguments": [ - "uint8x8_t a" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINV" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_f16", + "name": "vmax_s8", "arguments": [ - "float16x8_t a" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_f32", + "name": "vmax_u16", "arguments": [ - "float32x4_t a" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "float32_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINV" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_f64", + "name": "vmax_u32", "arguments": [ - "float64x2_t a" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float64_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_s16", + "name": "vmax_u8", "arguments": [ - "int16x8_t a" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINV" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_s32", + "name": "vmaxh_f16", "arguments": [ - "int32x4_t a" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "int32_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ @@ -48846,68 +244293,82 @@ ], "instructions": [ [ - "SMINV" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_s8", + "name": "vmaxnm_f16", "arguments": [ - "int8x16_t a" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SMINV" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_u16", + "name": "vmaxnm_f32", "arguments": [ - "uint16x8_t a" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "uint16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMINV" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_u32", + "name": "vmaxnm_f64", "arguments": [ - "uint32x4_t a" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "uint32_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ @@ -48915,408 +244376,309 @@ ], "instructions": [ [ - "UMINV" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vminvq_u8", + "name": "vmaxnmh_f16", "arguments": [ - "uint8x16_t a" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMINV" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_f32", + "name": "vmaxnmq_f16", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x2_t c" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "float32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.8H" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_f64", + "name": "vmaxnmq_f32", "arguments": [ - "float64x1_t a", - "float64x1_t b", - "float64x1_t c" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "float64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.4S" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_f32", + "name": "vmaxnmq_f64", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x2_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "float32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.2D" }, - "v": {} + "b": { + "register": "Vm.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "FMAXNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_s16", + "name": "vmaxnmv_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x4_t v", - "const int lane" + "float16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_s32", + "name": "vmaxnmv_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x2_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_u16", + "name": "vmaxnmvq_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x4_t v", - "const int lane" + "float16x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_lane_u32", + "name": "vmaxnmvq_f32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x2_t v", - "const int lane" + "float32x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXNMV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_f32", + "name": "vmaxnmvq_f64", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32x4_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "float32x2_t" + "value": "float64_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": {} + "a": { + "register": "Vn.2D" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_s16", + "name": "vmaxq_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x8_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { "register": "Vm.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_s32", + "name": "vmaxq_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x4_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_u16", + "name": "vmaxq_f64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x8_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.2D" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.2D" } }, "Architectures": [ @@ -49324,66 +244686,55 @@ ], "instructions": [ [ - "MLA" + "FMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_laneq_u32", + "name": "vmaxq_s16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x4_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8H" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MLA" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_f32", + "name": "vmaxq_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b", - "float32_t c" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.4S" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.4S" } }, "Architectures": [ @@ -49393,30 +244744,26 @@ ], "instructions": [ [ - "RESULT[I]" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_s16", + "name": "vmaxq_s8", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16_t c" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.16B" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.16B" } }, "Architectures": [ @@ -49426,30 +244773,26 @@ ], "instructions": [ [ - "MLA" + "SMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_s32", + "name": "vmaxq_u16", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32_t c" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8H" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.8H" } }, "Architectures": [ @@ -49459,30 +244802,26 @@ ], "instructions": [ [ - "MLA" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_u16", + "name": "vmaxq_u32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16_t c" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.4S" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.4S" } }, "Architectures": [ @@ -49492,30 +244831,26 @@ ], "instructions": [ [ - "MLA" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_n_u32", + "name": "vmaxq_u8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32_t c" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.16B" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.16B" } }, "Architectures": [ @@ -49525,233 +244860,160 @@ ], "instructions": [ [ - "MLA" + "UMAX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_s16", + "name": "vmaxv_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x4_t c" + "float16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_s32", + "name": "vmaxv_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x2_t c" + "float32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_s8", + "name": "vmaxv_s16", "arguments": [ - "int8x8_t a", - "int8x8_t b", - "int8x8_t c" + "int16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" - }, - "c": { - "register": "Vm.8B" + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_u16", + "name": "vmaxv_s32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "int32x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_u32", + "name": "vmaxv_s8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "int8x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmla_u8", + "name": "vmaxv_u16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "uint16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" - }, - "c": { - "register": "Vm.8B" + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_lane_s16", + "name": "vmaxv_u32", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x4_t v", - "const int lane" + "uint32x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -49759,35 +245021,22 @@ ], "instructions": [ [ - "SMLAL2" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_lane_s32", + "name": "vmaxv_u8", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x2_t v", - "const int lane" + "uint8x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.8B" } }, "Architectures": [ @@ -49795,35 +245044,22 @@ ], "instructions": [ [ - "SMLAL2" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_lane_u16", + "name": "vmaxvq_f16", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16x4_t v", - "const int lane" + "float16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ @@ -49831,35 +245067,22 @@ ], "instructions": [ [ - "UMLAL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_lane_u32", + "name": "vmaxvq_f32", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32x2_t v", - "const int lane" + "float32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ @@ -49867,35 +245090,22 @@ ], "instructions": [ [ - "UMLAL2" + "FMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_laneq_s16", + "name": "vmaxvq_f64", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.2D" } }, "Architectures": [ @@ -49903,35 +245113,22 @@ ], "instructions": [ [ - "SMLAL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_laneq_s32", + "name": "vmaxvq_s16", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ @@ -49939,35 +245136,22 @@ ], "instructions": [ [ - "SMLAL2" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_laneq_u16", + "name": "vmaxvq_s32", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16x8_t v", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.4S" } }, "Architectures": [ @@ -49975,35 +245159,22 @@ ], "instructions": [ [ - "UMLAL2" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_laneq_u32", + "name": "vmaxvq_s8", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32x4_t v", - "const int lane" + "int8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.16B" } }, "Architectures": [ @@ -50011,30 +245182,22 @@ ], "instructions": [ [ - "UMLAL2" + "SMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_n_s16", + "name": "vmaxvq_u16", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16_t c" + "uint16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" } }, "Architectures": [ @@ -50042,30 +245205,22 @@ ], "instructions": [ [ - "SMLAL2" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_n_s32", + "name": "vmaxvq_u32", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32_t c" + "uint32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" } }, "Architectures": [ @@ -50073,30 +245228,22 @@ ], "instructions": [ [ - "SMLAL2" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_n_u16", + "name": "vmaxvq_u8", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16_t c" + "uint8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vn.16B" } }, "Architectures": [ @@ -50104,92 +245251,83 @@ ], "instructions": [ [ - "UMLAL2" + "UMAXV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_n_u32", + "name": "vmin_f16", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32_t c" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMLAL2" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_s16", + "name": "vmin_f32", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t c" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMLAL2" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_s32", + "name": "vmin_f64", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t c" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dn" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" + "register": "Dm" } }, "Architectures": [ @@ -50197,159 +245335,142 @@ ], "instructions": [ [ - "SMLAL2" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_s8", + "name": "vmin_s16", "arguments": [ - "int16x8_t a", - "int8x16_t b", - "int8x16_t c" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4H" }, "b": { - "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMLAL2" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_u16", + "name": "vmin_s32", "arguments": [ - "uint32x4_t a", - "uint16x8_t b", - "uint16x8_t c" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMLAL2" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_u32", + "name": "vmin_s8", "arguments": [ - "uint64x2_t a", - "uint32x4_t b", - "uint32x4_t c" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMLAL2" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_high_u8", + "name": "vmin_u16", "arguments": [ - "uint16x8_t a", - "uint8x16_t b", - "uint8x16_t c" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4H" }, "b": { - "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMLAL2" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_lane_s16", + "name": "vmin_u32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t v", - "const int lane" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -50359,35 +245480,26 @@ ], "instructions": [ [ - "SMLAL" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_lane_s32", + "name": "vmin_u8", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t v", - "const int lane" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.8B" } }, "Architectures": [ @@ -50397,147 +245509,109 @@ ], "instructions": [ [ - "SMLAL" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_lane_u16", + "name": "vminh_f16", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16x4_t v", - "const int lane" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Hn" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_lane_u32", + "name": "vminnm_f16", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32x2_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_laneq_s16", + "name": "vminnm_f32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x8_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_laneq_s32", + "name": "vminnm_f64", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x4_t v", - "const int lane" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dn" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Dm" } }, "Architectures": [ @@ -50545,366 +245619,280 @@ ], "instructions": [ [ - "SMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_laneq_u16", + "name": "vminnmh_f16", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16x8_t v", - "const int lane" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Hn" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Hm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_laneq_u32", + "name": "vminnmq_f16", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32x4_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_n_s16", + "name": "vminnmq_f32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16_t c" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_n_s32", + "name": "vminnmq_f64", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32_t c" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2D" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_n_u16", + "name": "vminnmv_f16", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16_t c" + "float16x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_n_u32", + "name": "vminnmv_f32", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32_t c" + "float32x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_s16", + "name": "vminnmvq_f16", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t c" + "float16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_s32", + "name": "vminnmvq_f32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t c" + "float32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNMV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_s8", + "name": "vminnmvq_f64", "arguments": [ - "int16x8_t a", - "int8x8_t b", - "int8x8_t c" + "float64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8B" - }, - "c": { - "register": "Vm.8B" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMLAL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_u16", + "name": "vminq_f16", "arguments": [ - "uint32x4_t a", - "uint16x4_t b", - "uint16x4_t c" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8H" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_u32", + "name": "vminq_f32", "arguments": [ - "uint64x2_t a", - "uint32x2_t b", - "uint32x2_t c" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4S" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -50914,63 +245902,53 @@ ], "instructions": [ [ - "UMLAL" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlal_u8", + "name": "vminq_f64", "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "uint8x8_t c" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.2D" }, "b": { - "register": "Vn.8B" - }, - "c": { - "register": "Vm.8B" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMLAL" + "FMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_f32", + "name": "vminq_s16", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32x4_t c" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.8H" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.8H" } }, "Architectures": [ @@ -50980,61 +245958,56 @@ ], "instructions": [ [ - "RESULT[I]" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_f64", + "name": "vminq_s32", "arguments": [ - "float64x2_t a", - "float64x2_t b", - "float64x2_t c" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" + "register": "Vn.4S" }, "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_f32", + "name": "vminq_s8", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32x2_t v", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.16B" }, - "v": {} + "b": { + "register": "Vm.16B" + } }, "Architectures": [ "v7", @@ -51043,35 +246016,26 @@ ], "instructions": [ [ - "RESULT[I]" + "SMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_s16", + "name": "vminq_u16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x4_t v", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -51081,35 +246045,26 @@ ], "instructions": [ [ - "MLA" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_s32", + "name": "vminq_u32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x2_t v", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -51119,35 +246074,26 @@ ], "instructions": [ [ - "MLA" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_u16", + "name": "vminq_u8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x4_t v", - "const int lane" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.16B" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ @@ -51157,103 +246103,68 @@ ], "instructions": [ [ - "MLA" + "UMIN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_lane_u32", + "name": "vminv_f16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x2_t v", - "const int lane" + "float16x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_f32", + "name": "vminv_f32", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32x4_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": {} + "a": { + "register": "Vn.2S" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_s16", + "name": "vminv_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t v", - "const int lane" + "int16x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.4H" } }, "Architectures": [ @@ -51261,35 +246172,22 @@ ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_s32", + "name": "vminv_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t v", - "const int lane" + "int32x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ @@ -51297,35 +246195,22 @@ ], "instructions": [ [ - "MLA" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_u16", + "name": "vminv_s8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t v", - "const int lane" + "int8x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.8B" } }, "Architectures": [ @@ -51333,35 +246218,22 @@ ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_laneq_u32", + "name": "vminv_u16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t v", - "const int lane" + "uint16x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.4H" } }, "Architectures": [ @@ -51369,376 +246241,266 @@ ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_f32", + "name": "vminv_u32", "arguments": [ - "float32x4_t a", - "float32x4_t b", - "float32_t c" + "uint32x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "N/A" - }, - "b": { - "register": "N/A" - }, - "c": { - "register": "N/A" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RESULT[I]" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_s16", + "name": "vminv_u8", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16_t c" + "uint8x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_s32", + "name": "vminvq_f16", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32_t c" + "float16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_u16", + "name": "vminvq_f32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16_t c" + "float32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_n_u32", + "name": "vminvq_f64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32_t c" + "float64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_s16", + "name": "vminvq_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "int16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_s32", + "name": "vminvq_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "int32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_s8", + "name": "vminvq_s8", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "int8x16_t c" + "int8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "SMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_u16", + "name": "vminvq_u16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" + "uint16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_u32", + "name": "vminvq_u32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "uint32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlaq_u8", + "name": "vminvq_u8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "uint8x16_t c" + "uint8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MLA" + "UMINV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_f32", + "name": "vmla_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -51765,13 +246527,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_f64", + "name": "vmla_f64", "arguments": [ "float64x1_t a", "float64x1_t b", @@ -51796,13 +246558,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_f32", + "name": "vmla_lane_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -51813,13 +246575,10 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -51828,13 +246587,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_s16", + "name": "vmla_lane_s16", "arguments": [ "int16x4_t a", "int16x4_t b", @@ -51866,13 +246625,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_s32", + "name": "vmla_lane_s32", "arguments": [ "int32x2_t a", "int32x2_t b", @@ -51904,13 +246663,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_u16", + "name": "vmla_lane_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b", @@ -51942,13 +246701,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_lane_u32", + "name": "vmla_lane_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b", @@ -51980,13 +246739,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_f32", + "name": "vmla_laneq_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -51997,26 +246756,23 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_s16", + "name": "vmla_laneq_s16", "arguments": [ "int16x4_t a", "int16x4_t b", @@ -52046,13 +246802,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_s32", + "name": "vmla_laneq_s32", "arguments": [ "int32x2_t a", "int32x2_t b", @@ -52082,13 +246838,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_u16", + "name": "vmla_laneq_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b", @@ -52118,13 +246874,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_laneq_u32", + "name": "vmla_laneq_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b", @@ -52154,13 +246910,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_f32", + "name": "vmla_n_f32", "arguments": [ "float32x2_t a", "float32x2_t b", @@ -52187,13 +246943,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_s16", + "name": "vmla_n_s16", "arguments": [ "int16x4_t a", "int16x4_t b", @@ -52220,13 +246976,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_s32", + "name": "vmla_n_s32", "arguments": [ "int32x2_t a", "int32x2_t b", @@ -52253,13 +247009,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_u16", + "name": "vmla_n_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b", @@ -52286,13 +247042,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_n_u32", + "name": "vmla_n_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b", @@ -52319,13 +247075,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_s16", + "name": "vmla_s16", "arguments": [ "int16x4_t a", "int16x4_t b", @@ -52352,13 +247108,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_s32", + "name": "vmla_s32", "arguments": [ "int32x2_t a", "int32x2_t b", @@ -52385,13 +247141,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_s8", + "name": "vmla_s8", "arguments": [ "int8x8_t a", "int8x8_t b", @@ -52418,13 +247174,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_u16", + "name": "vmla_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b", @@ -52451,13 +247207,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_u32", + "name": "vmla_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b", @@ -52484,13 +247240,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmls_u8", + "name": "vmla_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b", @@ -52517,13 +247273,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_lane_s16", + "name": "vmlal_high_lane_s16", "arguments": [ "int32x4_t a", "int16x8_t b", @@ -52553,13 +247309,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_lane_s32", + "name": "vmlal_high_lane_s32", "arguments": [ "int64x2_t a", "int32x4_t b", @@ -52589,13 +247345,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_lane_u16", + "name": "vmlal_high_lane_u16", "arguments": [ "uint32x4_t a", "uint16x8_t b", @@ -52625,13 +247381,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_lane_u32", + "name": "vmlal_high_lane_u32", "arguments": [ "uint64x2_t a", "uint32x4_t b", @@ -52661,13 +247417,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_laneq_s16", + "name": "vmlal_high_laneq_s16", "arguments": [ "int32x4_t a", "int16x8_t b", @@ -52697,13 +247453,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_laneq_s32", + "name": "vmlal_high_laneq_s32", "arguments": [ "int64x2_t a", "int32x4_t b", @@ -52733,13 +247489,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_laneq_u16", + "name": "vmlal_high_laneq_u16", "arguments": [ "uint32x4_t a", "uint16x8_t b", @@ -52769,13 +247525,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_laneq_u32", + "name": "vmlal_high_laneq_u32", "arguments": [ "uint64x2_t a", "uint32x4_t b", @@ -52805,13 +247561,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_n_s16", + "name": "vmlal_high_n_s16", "arguments": [ "int32x4_t a", "int16x8_t b", @@ -52836,13 +247592,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_n_s32", + "name": "vmlal_high_n_s32", "arguments": [ "int64x2_t a", "int32x4_t b", @@ -52867,13 +247623,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_n_u16", + "name": "vmlal_high_n_u16", "arguments": [ "uint32x4_t a", "uint16x8_t b", @@ -52898,13 +247654,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_n_u32", + "name": "vmlal_high_n_u32", "arguments": [ "uint64x2_t a", "uint32x4_t b", @@ -52929,13 +247685,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_s16", + "name": "vmlal_high_s16", "arguments": [ "int32x4_t a", "int16x8_t b", @@ -52960,13 +247716,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_s32", + "name": "vmlal_high_s32", "arguments": [ "int64x2_t a", "int32x4_t b", @@ -52991,13 +247747,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_s8", + "name": "vmlal_high_s8", "arguments": [ "int16x8_t a", "int8x16_t b", @@ -53022,13 +247778,13 @@ ], "instructions": [ [ - "SMLSL2" + "SMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_u16", + "name": "vmlal_high_u16", "arguments": [ "uint32x4_t a", "uint16x8_t b", @@ -53053,13 +247809,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_u32", + "name": "vmlal_high_u32", "arguments": [ "uint64x2_t a", "uint32x4_t b", @@ -53084,13 +247840,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_high_u8", + "name": "vmlal_high_u8", "arguments": [ "uint16x8_t a", "uint8x16_t b", @@ -53115,13 +247871,13 @@ ], "instructions": [ [ - "UMLSL2" + "UMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_lane_s16", + "name": "vmlal_lane_s16", "arguments": [ "int32x4_t a", "int16x4_t b", @@ -53153,13 +247909,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_lane_s32", + "name": "vmlal_lane_s32", "arguments": [ "int64x2_t a", "int32x2_t b", @@ -53191,13 +247947,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_lane_u16", + "name": "vmlal_lane_u16", "arguments": [ "uint32x4_t a", "uint16x4_t b", @@ -53229,13 +247985,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_lane_u32", + "name": "vmlal_lane_u32", "arguments": [ "uint64x2_t a", "uint32x2_t b", @@ -53267,13 +248023,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_laneq_s16", + "name": "vmlal_laneq_s16", "arguments": [ "int32x4_t a", "int16x4_t b", @@ -53303,13 +248059,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_laneq_s32", + "name": "vmlal_laneq_s32", "arguments": [ "int64x2_t a", "int32x2_t b", @@ -53339,13 +248095,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_laneq_u16", + "name": "vmlal_laneq_u16", "arguments": [ "uint32x4_t a", "uint16x4_t b", @@ -53375,13 +248131,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_laneq_u32", + "name": "vmlal_laneq_u32", "arguments": [ "uint64x2_t a", "uint32x2_t b", @@ -53411,13 +248167,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_n_s16", + "name": "vmlal_n_s16", "arguments": [ "int32x4_t a", "int16x4_t b", @@ -53444,13 +248200,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_n_s32", + "name": "vmlal_n_s32", "arguments": [ "int64x2_t a", "int32x2_t b", @@ -53477,13 +248233,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_n_u16", + "name": "vmlal_n_u16", "arguments": [ "uint32x4_t a", "uint16x4_t b", @@ -53510,13 +248266,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_n_u32", + "name": "vmlal_n_u32", "arguments": [ "uint64x2_t a", "uint32x2_t b", @@ -53543,13 +248299,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_s16", + "name": "vmlal_s16", "arguments": [ "int32x4_t a", "int16x4_t b", @@ -53576,13 +248332,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_s32", + "name": "vmlal_s32", "arguments": [ "int64x2_t a", "int32x2_t b", @@ -53609,13 +248365,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_s8", + "name": "vmlal_s8", "arguments": [ "int16x8_t a", "int8x8_t b", @@ -53642,13 +248398,13 @@ ], "instructions": [ [ - "SMLSL" + "SMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_u16", + "name": "vmlal_u16", "arguments": [ "uint32x4_t a", "uint16x4_t b", @@ -53675,13 +248431,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_u32", + "name": "vmlal_u32", "arguments": [ "uint64x2_t a", "uint32x2_t b", @@ -53708,13 +248464,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsl_u8", + "name": "vmlal_u8", "arguments": [ "uint16x8_t a", "uint8x8_t b", @@ -53741,13 +248497,13 @@ ], "instructions": [ [ - "UMLSL" + "UMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_f32", + "name": "vmlaq_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -53774,13 +248530,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_f64", + "name": "vmlaq_f64", "arguments": [ "float64x2_t a", "float64x2_t b", @@ -53805,13 +248561,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_f32", + "name": "vmlaq_lane_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -53822,13 +248578,10 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -53837,13 +248590,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_s16", + "name": "vmlaq_lane_s16", "arguments": [ "int16x8_t a", "int16x8_t b", @@ -53875,13 +248628,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_s32", + "name": "vmlaq_lane_s32", "arguments": [ "int32x4_t a", "int32x4_t b", @@ -53913,13 +248666,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_u16", + "name": "vmlaq_lane_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b", @@ -53951,13 +248704,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_lane_u32", + "name": "vmlaq_lane_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b", @@ -53989,13 +248742,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_f32", + "name": "vmlaq_laneq_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -54006,26 +248759,23 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_s16", + "name": "vmlaq_laneq_s16", "arguments": [ "int16x8_t a", "int16x8_t b", @@ -54055,13 +248805,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_s32", + "name": "vmlaq_laneq_s32", "arguments": [ "int32x4_t a", "int32x4_t b", @@ -54091,13 +248841,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_u16", + "name": "vmlaq_laneq_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b", @@ -54127,13 +248877,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_laneq_u32", + "name": "vmlaq_laneq_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b", @@ -54163,13 +248913,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_f32", + "name": "vmlaq_n_f32", "arguments": [ "float32x4_t a", "float32x4_t b", @@ -54196,13 +248946,13 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_s16", + "name": "vmlaq_n_s16", "arguments": [ "int16x8_t a", "int16x8_t b", @@ -54229,13 +248979,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_s32", + "name": "vmlaq_n_s32", "arguments": [ "int32x4_t a", "int32x4_t b", @@ -54262,13 +249012,13 @@ ], "instructions": [ [ - "MLS" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmlsq_n_u16", + "name": "vmlaq_n_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b", @@ -54285,500 +249035,7 @@ "register": "Vn.8H" }, "c": { - "register": "Vm.H[0]" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "MLS" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmlsq_n_u32", - "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32_t c" - ], - "return_type": { - "value": "uint32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "MLS" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmlsq_s16", - "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "MLS" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmlsq_s32", - "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" - ], - "return_type": { - "value": "int32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "MLS" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmlsq_s8", - "arguments": [ - "int8x16_t a", - "int8x16_t b", - "int8x16_t c" - ], - "return_type": { - "value": "int8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "MLS" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmlsq_u16", - "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "uint16x8_t c" - ], - "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "MLS" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmlsq_u32", - "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" - ], - "return_type": { - "value": "uint32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "MLS" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmlsq_u8", - "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "uint8x16_t c" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" - }, - "c": { - "register": "Vm.16B" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "MLS" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmmlaq_s32", - "arguments": [ - "int32x4_t r", - "int8x16_t a", - "int8x16_t b" - ], - "return_type": { - "value": "int32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "r": { - "register": "Vd.4S" - } - }, - "Architectures": [ - "A32", - "A64" - ], - "instructions": [ - [ - "SMMLA" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmmlaq_u32", - "arguments": [ - "uint32x4_t r", - "uint8x16_t a", - "uint8x16_t b" - ], - "return_type": { - "value": "uint32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" - }, - "r": { - "register": "Vd.4S" - } - }, - "Architectures": [ - "A32", - "A64" - ], - "instructions": [ - [ - "UMMLA" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_f16", - "arguments": [ - "float16_t value" - ], - "return_type": { - "value": "float16x4_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_f32", - "arguments": [ - "float32_t value" - ], - "return_type": { - "value": "float32x2_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_f64", - "arguments": [ - "float64_t value" - ], - "return_type": { - "value": "float64x1_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_p16", - "arguments": [ - "poly16_t value" - ], - "return_type": { - "value": "poly16x4_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_p8", - "arguments": [ - "poly8_t value" - ], - "return_type": { - "value": "poly8x8_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_s16", - "arguments": [ - "int16_t value" - ], - "return_type": { - "value": "int16x4_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_s32", - "arguments": [ - "int32_t value" - ], - "return_type": { - "value": "int32x2_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "DUP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmov_n_s64", - "arguments": [ - "int64_t value" - ], - "return_type": { - "value": "int64x1_t" - }, - "Arguments_Preparation": { - "value": { - "register": "rn" + "register": "Vm.H[0]" } }, "Architectures": [ @@ -54788,22 +249045,30 @@ ], "instructions": [ [ - "DUP" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmov_n_s8", + "name": "vmlaq_n_u32", "arguments": [ - "int8_t value" + "uint32x4_t a", + "uint32x4_t b", + "uint32_t c" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -54813,22 +249078,30 @@ ], "instructions": [ [ - "DUP" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmov_n_u16", + "name": "vmlaq_s16", "arguments": [ - "uint16_t value" + "int16x8_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ @@ -54838,22 +249111,30 @@ ], "instructions": [ [ - "DUP" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmov_n_u32", + "name": "vmlaq_s32", "arguments": [ - "uint32_t value" + "int32x4_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ @@ -54863,22 +249144,30 @@ ], "instructions": [ [ - "DUP" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmov_n_u64", + "name": "vmlaq_s8", "arguments": [ - "uint64_t value" + "int8x16_t a", + "int8x16_t b", + "int8x16_t c" ], "return_type": { - "value": "uint64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.16B" + }, + "b": { + "register": "Vn.16B" + }, + "c": { + "register": "Vm.16B" } }, "Architectures": [ @@ -54888,22 +249177,30 @@ ], "instructions": [ [ - "DUP" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmov_n_u8", + "name": "vmlaq_u16", "arguments": [ - "uint8_t value" + "uint16x8_t a", + "uint16x8_t b", + "uint16x8_t c" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ @@ -54913,91 +249210,129 @@ ], "instructions": [ [ - "DUP" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_high_s16", + "name": "vmlaq_u32", "arguments": [ - "int16x8_t a" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHLL2" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_high_s32", + "name": "vmlaq_u8", "arguments": [ - "int32x4_t a" + "uint8x16_t a", + "uint8x16_t b", + "uint8x16_t c" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.16B" + }, + "b": { + "register": "Vn.16B" + }, + "c": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHLL2" + "MLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_high_s8", + "name": "vmls_f32", "arguments": [ - "int8x16_t a" + "float32x2_t a", + "float32x2_t b", + "float32x2_t c" ], "return_type": { - "value": "int16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "N/A" + }, + "b": { + "register": "N/A" + }, + "c": { + "register": "N/A" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHLL2" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_high_u16", + "name": "vmls_f64", "arguments": [ - "uint16x8_t a" + "float64x1_t a", + "float64x1_t b", + "float64x1_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "N/A" + }, + "b": { + "register": "N/A" + }, + "c": { + "register": "N/A" } }, "Architectures": [ @@ -55005,68 +249340,102 @@ ], "instructions": [ [ - "USHLL2" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_high_u32", + "name": "vmls_lane_f32", "arguments": [ - "uint32x4_t a" + "float32x2_t a", + "float32x2_t b", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USHLL2" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_high_u8", + "name": "vmls_lane_s16", "arguments": [ - "uint8x16_t a" + "int16x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USHLL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_s16", + "name": "vmls_lane_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55076,22 +249445,35 @@ ], "instructions": [ [ - "SSHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_s32", + "name": "vmls_lane_u16", "arguments": [ - "int32x2_t a" + "uint16x4_t a", + "uint16x4_t b", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -55101,22 +249483,35 @@ ], "instructions": [ [ - "SSHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_s8", + "name": "vmls_lane_u32", "arguments": [ - "int8x8_t a" + "uint32x2_t a", + "uint32x2_t b", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55126,159 +249521,201 @@ ], "instructions": [ [ - "SSHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_u16", + "name": "vmls_laneq_f32", "arguments": [ - "uint16x4_t a" + "float32x2_t a", + "float32x2_t b", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_u32", + "name": "vmls_laneq_s16", "arguments": [ - "uint32x2_t a" + "int16x4_t a", + "int16x4_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovl_u8", + "name": "vmls_laneq_s32", "arguments": [ - "uint8x8_t a" + "int32x2_t a", + "int32x2_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHLL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_s16", + "name": "vmls_laneq_u16", "arguments": [ - "int8x8_t r", - "int16x8_t a" + "uint16x4_t a", + "uint16x4_t b", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4H" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_s32", + "name": "vmls_laneq_u32", "arguments": [ - "int16x4_t r", - "int32x4_t a" + "uint32x2_t a", + "uint32x2_t b", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2S" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_s64", + "name": "vmls_n_f32", "arguments": [ - "int32x2_t r", - "int64x2_t a" + "float32x2_t a", + "float32x2_t b", + "float32_t c" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "N/A" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "N/A" + }, + "c": { + "register": "N/A" } }, "Architectures": [ @@ -55288,26 +249725,30 @@ ], "instructions": [ [ - "XTN2" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_u16", + "name": "vmls_n_s16", "arguments": [ - "uint8x8_t r", - "uint16x8_t a" + "int16x4_t a", + "int16x4_t b", + "int16_t c" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4H" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -55317,26 +249758,30 @@ ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_u32", + "name": "vmls_n_s32", "arguments": [ - "uint16x4_t r", - "uint32x4_t a" + "int32x2_t a", + "int32x2_t b", + "int32_t c" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2S" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -55346,26 +249791,30 @@ ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_high_u64", + "name": "vmls_n_u16", "arguments": [ - "uint32x2_t r", - "uint64x2_t a" + "uint16x4_t a", + "uint16x4_t b", + "uint16_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4H" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -55375,22 +249824,30 @@ ], "instructions": [ [ - "XTN2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_s16", + "name": "vmls_n_u32", "arguments": [ - "int16x8_t a" + "uint32x2_t a", + "uint32x2_t b", + "uint32_t c" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -55400,22 +249857,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_s32", + "name": "vmls_s16", "arguments": [ - "int32x4_t a" + "int16x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -55425,22 +249890,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_s64", + "name": "vmls_s32", "arguments": [ - "int64x2_t a" + "int32x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55450,22 +249923,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_u16", + "name": "vmls_s8", "arguments": [ - "uint16x8_t a" + "int8x8_t a", + "int8x8_t b", + "int8x8_t c" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8B" + }, + "b": { + "register": "Vn.8B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -55475,22 +249956,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_u32", + "name": "vmls_u16", "arguments": [ - "uint32x4_t a" + "uint16x4_t a", + "uint16x4_t b", + "uint16x4_t c" ], "return_type": { "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -55500,22 +249989,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovn_u64", + "name": "vmls_u32", "arguments": [ - "uint64x2_t a" + "uint32x2_t a", + "uint32x2_t b", + "uint32x2_t c" ], "return_type": { "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55525,22 +250022,30 @@ ], "instructions": [ [ - "XTN" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_f16", + "name": "vmls_u8", "arguments": [ - "float16_t value" + "uint8x8_t a", + "uint8x8_t b", + "uint8x8_t c" ], "return_type": { - "value": "float16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.8B" + }, + "b": { + "register": "Vn.8B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -55550,47 +250055,71 @@ ], "instructions": [ [ - "DUP" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_f32", + "name": "vmlsl_high_lane_s16", "arguments": [ - "float32_t value" + "int32x4_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "float32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_f64", + "name": "vmlsl_high_lane_s32", "arguments": [ - "float64_t value" + "int64x2_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "float64x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -55598,333 +250127,432 @@ ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_p16", + "name": "vmlsl_high_lane_u16", "arguments": [ - "poly16_t value" + "uint32x4_t a", + "uint16x8_t b", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "poly16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_p8", + "name": "vmlsl_high_lane_u32", "arguments": [ - "poly8_t value" + "uint64x2_t a", + "uint32x4_t b", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "poly8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_s16", + "name": "vmlsl_high_laneq_s16", "arguments": [ - "int16_t value" + "int32x4_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_s32", + "name": "vmlsl_high_laneq_s32", "arguments": [ - "int32_t value" + "int64x2_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_s64", + "name": "vmlsl_high_laneq_u16", "arguments": [ - "int64_t value" + "uint32x4_t a", + "uint16x8_t b", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_s8", + "name": "vmlsl_high_laneq_u32", "arguments": [ - "int8_t value" + "uint64x2_t a", + "uint32x4_t b", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_u16", + "name": "vmlsl_high_n_s16", "arguments": [ - "uint16_t value" + "int32x4_t a", + "int16x8_t b", + "int16_t c" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_u32", + "name": "vmlsl_high_n_s32", "arguments": [ - "uint32_t value" + "int64x2_t a", + "int32x4_t b", + "int32_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_u64", + "name": "vmlsl_high_n_u16", "arguments": [ - "uint64_t value" + "uint32x4_t a", + "uint16x8_t b", + "uint16_t c" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmovq_n_u8", + "name": "vmlsl_high_n_u32", "arguments": [ - "uint8_t value" + "uint64x2_t a", + "uint32x4_t b", + "uint32_t c" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "value": { - "register": "rn" + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "DUP" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_f16", + "name": "vmlsl_high_s16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int32x4_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "float16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4S" }, "b": { - "register": "Vm.4H" + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMUL" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_f32", + "name": "vmlsl_high_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int64x2_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "float32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, "b": { - "register": "Vm.2S" + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMUL" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_f64", + "name": "vmlsl_high_s8", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int16x8_t a", + "int8x16_t b", + "int8x16_t c" ], "return_type": { - "value": "float64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, "b": { - "register": "Dm" + "register": "Vn.16B" + }, + "c": { + "register": "Vm.16B" } }, "Architectures": [ @@ -55932,98 +250560,92 @@ ], "instructions": [ [ - "FMUL" + "SMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_f16", + "name": "vmlsl_high_u16", "arguments": [ - "float16x4_t a", - "float16x4_t v", - "const int lane" + "uint32x4_t a", + "uint16x8_t b", + "uint16x8_t c" ], "return_type": { - "value": "float16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.8H" }, - "v": { - "register": "Vm.4H" + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMUL" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_f32", + "name": "vmlsl_high_u32", "arguments": [ - "float32x2_t a", - "float32x2_t v", - "const int lane" + "uint64x2_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, - "lane": { - "minimum": 0, - "maximum": 1 + "b": { + "register": "Vn.4S" }, - "v": { - "register": "Vm.2S" + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FMUL" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_f64", + "name": "vmlsl_high_u8", "arguments": [ - "float64x1_t a", - "float64x1_t v", - "const int lane" + "uint16x8_t a", + "uint8x16_t b", + "uint8x16_t c" ], "return_type": { - "value": "float64x1_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 0 + "b": { + "register": "Vn.16B" }, - "v": { - "register": "Vm.1D" + "c": { + "register": "Vm.16B" } }, "Architectures": [ @@ -56031,23 +250653,27 @@ ], "instructions": [ [ - "FMUL" + "UMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_s16", + "name": "vmlsl_lane_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", + "int16x4_t b", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4H" }, "lane": { @@ -56065,23 +250691,27 @@ ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_s32", + "name": "vmlsl_lane_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", + "int32x2_t b", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.2S" }, "lane": { @@ -56099,23 +250729,27 @@ ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_u16", + "name": "vmlsl_lane_u16", "arguments": [ - "uint16x4_t a", + "uint32x4_t a", + "uint16x4_t b", "uint16x4_t v", "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4H" }, "lane": { @@ -56133,23 +250767,27 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_lane_u32", + "name": "vmlsl_lane_u32", "arguments": [ - "uint32x2_t a", + "uint64x2_t a", + "uint32x2_t b", "uint32x2_t v", "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.2S" }, "lane": { @@ -56167,23 +250805,27 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_f16", + "name": "vmlsl_laneq_s16", "arguments": [ - "float16x4_t a", - "float16x8_t v", + "int32x4_t a", + "int16x4_t b", + "int16x8_t v", "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4H" }, "lane": { @@ -56199,23 +250841,27 @@ ], "instructions": [ [ - "FMUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_f32", + "name": "vmlsl_laneq_s32", "arguments": [ - "float32x2_t a", - "float32x4_t v", + "int64x2_t a", + "int32x2_t b", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.2S" }, "lane": { @@ -56231,55 +250877,27 @@ ], "instructions": [ [ - "FMUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_f64", + "name": "vmlsl_laneq_u16", "arguments": [ - "float64x1_t a", - "float64x2_t v", + "uint32x4_t a", + "uint16x4_t b", + "uint16x8_t v", "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vd.4S" }, - "v": { - "register": "Vm.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FMUL" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vmul_laneq_s16", - "arguments": [ - "int16x4_t a", - "int16x8_t v", - "const int lane" - ], - "return_type": { - "value": "int16x4_t" - }, - "Arguments_Preparation": { - "a": { + "b": { "register": "Vn.4H" }, "lane": { @@ -56295,23 +250913,27 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_s32", + "name": "vmlsl_laneq_u32", "arguments": [ - "int32x2_t a", - "int32x4_t v", + "uint64x2_t a", + "uint32x2_t b", + "uint32x4_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.2S" }, "lane": { @@ -56327,117 +250949,128 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_u16", + "name": "vmlsl_n_s16", "arguments": [ - "uint16x4_t a", - "uint16x8_t v", - "const int lane" + "int32x4_t a", + "int16x4_t b", + "int16_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vn.4H" }, - "v": { - "register": "Vm.8H" + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_laneq_u32", + "name": "vmlsl_n_s32", "arguments": [ - "uint32x2_t a", - "uint32x4_t v", - "const int lane" + "int64x2_t a", + "int32x2_t b", + "int32_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.2S" }, - "v": { - "register": "Vm.4S" + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_f16", + "name": "vmlsl_n_u16", "arguments": [ - "float16x4_t a", - "float16_t n" + "uint32x4_t a", + "uint16x4_t b", + "uint16_t c" ], "return_type": { - "value": "float16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.4H" }, - "n": { + "c": { "register": "Vm.H[0]" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_f32", + "name": "vmlsl_n_u32", "arguments": [ - "float32x2_t a", - "float32_t b" + "uint64x2_t a", + "uint32x2_t b", + "uint32_t c" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, "b": { + "register": "Vn.2S" + }, + "c": { "register": "Vm.S[0]" } }, @@ -56448,53 +251081,63 @@ ], "instructions": [ [ - "FMUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_f64", + "name": "vmlsl_s16", "arguments": [ - "float64x1_t a", - "float64_t b" + "int32x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { - "value": "float64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" }, "b": { - "register": "Vm.D[0]" + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_s16", + "name": "vmlsl_s32", "arguments": [ - "int16x4_t a", - "int16_t b" + "int64x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { - "value": "int16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.2D" }, "b": { - "register": "Vm.H[0]" + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -56504,26 +251147,30 @@ ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_s32", + "name": "vmlsl_s8", "arguments": [ - "int32x2_t a", - "int32_t b" + "int16x8_t a", + "int8x8_t b", + "int8x8_t c" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.8H" }, "b": { - "register": "Vm.S[0]" + "register": "Vn.8B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -56533,26 +251180,30 @@ ], "instructions": [ [ - "MUL" + "SMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_u16", + "name": "vmlsl_u16", "arguments": [ - "uint16x4_t a", - "uint16_t b" + "uint32x4_t a", + "uint16x4_t b", + "uint16x4_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4S" }, "b": { - "register": "Vm.H[0]" + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -56562,26 +251213,30 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_n_u32", + "name": "vmlsl_u32", "arguments": [ - "uint32x2_t a", - "uint32_t b" + "uint64x2_t a", + "uint32x2_t b", + "uint32x2_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2D" }, "b": { - "register": "Vm.S[0]" + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -56591,25 +251246,29 @@ ], "instructions": [ [ - "MUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_p8", + "name": "vmlsl_u8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint16x8_t a", + "uint8x8_t b", + "uint8x8_t c" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.8H" }, "b": { + "register": "Vn.8B" + }, + "c": { "register": "Vm.8B" } }, @@ -56620,26 +251279,30 @@ ], "instructions": [ [ - "PMUL" + "UMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_s16", + "name": "vmlsq_f32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float32x4_t a", + "float32x4_t b", + "float32x4_t c" ], "return_type": { - "value": "int16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "N/A" }, "b": { - "register": "Vm.4H" + "register": "N/A" + }, + "c": { + "register": "N/A" } }, "Architectures": [ @@ -56649,55 +251312,57 @@ ], "instructions": [ [ - "MUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_s32", + "name": "vmlsq_f64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float64x2_t a", + "float64x2_t b", + "float64x2_t c" ], "return_type": { - "value": "int32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "N/A" }, "b": { - "register": "Vm.2S" + "register": "N/A" + }, + "c": { + "register": "N/A" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_s8", + "name": "vmlsq_lane_f32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "float32x4_t a", + "float32x4_t b", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 1 } }, "Architectures": [ @@ -56707,25 +251372,34 @@ ], "instructions": [ [ - "MUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_u16", + "name": "vmlsq_lane_s16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int16x8_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.8H" }, "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { "register": "Vm.4H" } }, @@ -56736,25 +251410,34 @@ ], "instructions": [ [ - "MUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_u32", + "name": "vmlsq_lane_s32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int32x4_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.4S" }, "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { "register": "Vm.2S" } }, @@ -56765,26 +251448,35 @@ ], "instructions": [ [ - "MUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmul_u8", + "name": "vmlsq_lane_u16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "uint16x8_t a", + "uint16x8_t b", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.8H" }, "b": { - "register": "Vm.8B" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -56794,63 +251486,64 @@ ], "instructions": [ [ - "MUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmuld_lane_f64", + "name": "vmlsq_lane_u32", "arguments": [ - "float64_t a", - "float64x1_t v", + "uint32x4_t a", + "uint32x4_t b", + "uint32x2_t v", "const int lane" ], "return_type": { - "value": "float64_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "v": { - "register": "Vm.1D" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmuld_laneq_f64", + "name": "vmlsq_laneq_f32", "arguments": [ - "float64_t a", - "float64x2_t v", + "float32x4_t a", + "float32x4_t b", + "float32x4_t v", "const int lane" ], "return_type": { - "value": "float64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" - }, "lane": { "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2D" + "maximum": 3 } }, "Architectures": [ @@ -56858,59 +251551,71 @@ ], "instructions": [ [ - "FMUL" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulh_f16", + "name": "vmlsq_laneq_s16", "arguments": [ - "float16_t a", - "float16_t b" + "int16x8_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "float16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.8H" }, "b": { - "register": "Hm" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FMUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulh_lane_f16", + "name": "vmlsq_laneq_s32", "arguments": [ - "float16_t a", - "float16x4_t v", + "int32x4_t a", + "int32x4_t b", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "float16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" }, "lane": { "minimum": 0, "maximum": 3 }, "v": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -56918,24 +251623,28 @@ ], "instructions": [ [ - "FMUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulh_laneq_f16", + "name": "vmlsq_laneq_u16", "arguments": [ - "float16_t a", - "float16x8_t v", + "uint16x8_t a", + "uint16x8_t b", + "uint16x8_t v", "const int lane" ], "return_type": { - "value": "float16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" }, "lane": { "minimum": 0, @@ -56950,31 +251659,35 @@ ], "instructions": [ [ - "FMUL" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_lane_s16", + "name": "vmlsq_laneq_u32", "arguments": [ - "int16x8_t a", - "int16x4_t v", + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" }, "lane": { "minimum": 0, "maximum": 3 }, "v": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -56982,358 +251695,393 @@ ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_lane_s32", + "name": "vmlsq_n_f32", "arguments": [ - "int32x4_t a", - "int32x2_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b", + "float32_t c" ], "return_type": { - "value": "int64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "N/A" }, - "lane": { - "minimum": 0, - "maximum": 1 + "b": { + "register": "N/A" }, - "v": { - "register": "Vm.2S" + "c": { + "register": "N/A" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "result" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_lane_u16", + "name": "vmlsq_n_s16", "arguments": [ - "uint16x8_t a", - "uint16x4_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b", + "int16_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.8H" }, - "v": { - "register": "Vm.4H" + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_lane_u32", + "name": "vmlsq_n_s32", "arguments": [ - "uint32x4_t a", - "uint32x2_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b", + "int32_t c" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "b": { + "register": "Vn.4S" }, - "v": { - "register": "Vm.2S" + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_laneq_s16", + "name": "vmlsq_n_u16", "arguments": [ - "int16x8_t a", - "int16x8_t v", - "const int lane" + "uint16x8_t a", + "uint16x8_t b", + "uint16_t c" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vn.8H" }, - "v": { - "register": "Vm.8H" + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_laneq_s32", + "name": "vmlsq_n_u32", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32_t c" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.4S" }, - "v": { - "register": "Vm.4S" + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_laneq_u16", + "name": "vmlsq_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8H" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vn.8H" }, - "v": { + "c": { "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_laneq_u32", + "name": "vmlsq_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "b": { + "register": "Vn.4S" }, - "v": { + "c": { "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_n_s16", + "name": "vmlsq_s8", "arguments": [ - "int16x8_t a", - "int16_t b" + "int8x16_t a", + "int8x16_t b", + "int8x16_t c" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.16B" }, "b": { - "register": "Vm.H[0]" + "register": "Vn.16B" + }, + "c": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_n_s32", + "name": "vmlsq_u16", "arguments": [ - "int32x4_t a", - "int32_t b" + "uint16x8_t a", + "uint16x8_t b", + "uint16x8_t c" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.8H" }, "b": { - "register": "Vm.S[0]" + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_n_u16", + "name": "vmlsq_u32", "arguments": [ - "uint16x8_t a", - "uint16_t b" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4S" }, "b": { - "register": "Vm.H[0]" + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_n_u32", + "name": "vmlsq_u8", "arguments": [ - "uint32x4_t a", - "uint32_t b" + "uint8x16_t a", + "uint8x16_t b", + "uint8x16_t c" ], "return_type": { - "value": "uint64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.16B" }, "b": { - "register": "Vm.S[0]" + "register": "Vn.16B" + }, + "c": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "MLS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_p64", + "name": "vmmlaq_s32", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "int32x4_t r", + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "poly128_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, "b": { - "register": "Vm.2D" + "register": "Vm.16B" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ @@ -57342,19 +252090,20 @@ ], "instructions": [ [ - "PMULL2" + "SMMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_p8", + "name": "vmmlaq_u32", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "uint32x4_t r", + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -57362,87 +252111,83 @@ }, "b": { "register": "Vm.16B" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "PMULL2" + "UMMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_s16", + "name": "vmov_n_f16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float16_t value" ], "return_type": { - "value": "int32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_s32", + "name": "vmov_n_f32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float32_t value" ], "return_type": { - "value": "int64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_s8", + "name": "vmov_n_f64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float64_t value" ], "return_type": { - "value": "int16x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57450,112 +252195,147 @@ ], "instructions": [ [ - "SMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_u16", + "name": "vmov_n_p16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly16_t value" ], "return_type": { - "value": "uint32x4_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_u32", + "name": "vmov_n_p8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "poly8_t value" ], "return_type": { - "value": "uint64x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_high_u8", + "name": "vmov_n_s16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int16_t value" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMULL2" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_lane_s16", + "name": "vmov_n_s32", "arguments": [ - "int16x4_t a", - "int16x4_t v", - "const int lane" + "int32_t value" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "value": { + "register": "rn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmov_n_s64", + "arguments": [ + "int64_t value" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "value": { + "register": "rn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmov_n_s8", + "arguments": [ + "int8_t value" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "value": { + "register": "rn" } }, "Architectures": [ @@ -57565,31 +252345,22 @@ ], "instructions": [ [ - "SMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_lane_s32", + "name": "vmov_n_u16", "arguments": [ - "int32x2_t a", - "int32x2_t v", - "const int lane" + "uint16_t value" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57599,31 +252370,22 @@ ], "instructions": [ [ - "SMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_lane_u16", + "name": "vmov_n_u32", "arguments": [ - "uint16x4_t a", - "uint16x4_t v", - "const int lane" + "uint32_t value" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57633,31 +252395,22 @@ ], "instructions": [ [ - "UMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_lane_u32", + "name": "vmov_n_u64", "arguments": [ - "uint32x2_t a", - "uint32x2_t v", - "const int lane" + "uint64_t value" ], "return_type": { - "value": "uint64x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "value": { + "register": "rn" } }, "Architectures": [ @@ -57667,63 +252420,47 @@ ], "instructions": [ [ - "UMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_laneq_s16", + "name": "vmov_n_u8", "arguments": [ - "int16x4_t a", - "int16x8_t v", - "const int lane" + "uint8_t value" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMULL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_laneq_s32", + "name": "vmovl_high_s16", "arguments": [ - "int32x2_t a", - "int32x4_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ @@ -57731,31 +252468,22 @@ ], "instructions": [ [ - "SMULL" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_laneq_u16", + "name": "vmovl_high_s32", "arguments": [ - "uint16x4_t a", - "uint16x8_t v", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.4S" } }, "Architectures": [ @@ -57763,31 +252491,22 @@ ], "instructions": [ [ - "UMULL" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_laneq_u32", + "name": "vmovl_high_s8", "arguments": [ - "uint32x2_t a", - "uint32x4_t v", - "const int lane" + "int8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.16B" } }, "Architectures": [ @@ -57795,113 +252514,91 @@ ], "instructions": [ [ - "UMULL" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_n_s16", + "name": "vmovl_high_u16", "arguments": [ - "int16x4_t a", - "int16_t b" + "uint16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.H[0]" + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMULL" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_n_s32", + "name": "vmovl_high_u32", "arguments": [ - "int32x2_t a", - "int32_t b" + "uint32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.S[0]" + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMULL" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_n_u16", + "name": "vmovl_high_u8", "arguments": [ - "uint16x4_t a", - "uint16_t b" + "uint8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.H[0]" + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMULL" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_n_u32", + "name": "vmovl_s16", "arguments": [ - "uint32x2_t a", - "uint32_t b" + "int16x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.S[0]" + "register": "Vn.4H" } }, "Architectures": [ @@ -57911,54 +252608,47 @@ ], "instructions": [ [ - "UMULL" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_p64", + "name": "vmovl_s32", "arguments": [ - "poly64_t a", - "poly64_t b" + "int32x2_t a" ], "return_type": { - "value": "poly128_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.1D" - }, - "b": { - "register": "Vm.1D" + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "PMULL" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_p8", + "name": "vmovl_s8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "int8x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" } }, "Architectures": [ @@ -57968,26 +252658,22 @@ ], "instructions": [ [ - "PMULL" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_s16", + "name": "vmovl_u16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint16x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" } }, "Architectures": [ @@ -57997,26 +252683,22 @@ ], "instructions": [ [ - "SMULL" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_s32", + "name": "vmovl_u32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint32x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" } }, "Architectures": [ @@ -58026,26 +252708,22 @@ ], "instructions": [ [ - "SMULL" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_s8", + "name": "vmovl_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" } }, "Architectures": [ @@ -58055,26 +252733,26 @@ ], "instructions": [ [ - "SMULL" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_u16", + "name": "vmovn_high_s16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int8x8_t r", + "int16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, - "b": { - "register": "Vm.4H" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -58084,26 +252762,26 @@ ], "instructions": [ [ - "UMULL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_u32", + "name": "vmovn_high_s32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int16x4_t r", + "int32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, - "b": { - "register": "Vm.2S" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -58113,26 +252791,26 @@ ], "instructions": [ [ - "UMULL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmull_u8", + "name": "vmovn_high_s64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "int32x2_t r", + "int64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, - "b": { - "register": "Vm.8B" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -58142,54 +252820,55 @@ ], "instructions": [ [ - "UMULL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_f16", + "name": "vmovn_high_u16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint8x8_t r", + "uint16x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "b": { - "register": "Vm.8H" + "r": { + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMUL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_f32", + "name": "vmovn_high_u32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "uint16x4_t r", + "uint32x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "b": { - "register": "Vm.4S" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -58199,91 +252878,76 @@ ], "instructions": [ [ - "FMUL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_f64", + "name": "vmovn_high_u64", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint32x2_t r", + "uint64x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" }, - "b": { - "register": "Vm.2D" + "r": { + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "XTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_f16", + "name": "vmovn_s16", "arguments": [ - "float16x8_t a", - "float16x4_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_f32", + "name": "vmovn_s32", "arguments": [ - "float32x4_t a", - "float32x2_t v", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ @@ -58293,63 +252957,47 @@ ], "instructions": [ [ - "FMUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_f64", + "name": "vmovn_s64", "arguments": [ - "float64x2_t a", - "float64x1_t v", - "const int lane" + "int64x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" - }, - "lane": { - "minimum": 0, - "maximum": 0 - }, - "v": { - "register": "Vm.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_s16", + "name": "vmovn_u16", "arguments": [ - "int16x8_t a", - "int16x4_t v", - "const int lane" + "uint16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ @@ -58359,31 +253007,22 @@ ], "instructions": [ [ - "MUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_s32", + "name": "vmovn_u32", "arguments": [ - "int32x4_t a", - "int32x2_t v", - "const int lane" + "uint32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ @@ -58393,31 +253032,22 @@ ], "instructions": [ [ - "MUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_u16", + "name": "vmovn_u64", "arguments": [ - "uint16x8_t a", - "uint16x4_t v", - "const int lane" + "uint64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vn.2D" } }, "Architectures": [ @@ -58427,31 +253057,22 @@ ], "instructions": [ [ - "MUL" + "XTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_lane_u32", + "name": "vmovq_n_f16", "arguments": [ - "uint32x4_t a", - "uint32x2_t v", - "const int lane" + "float16_t value" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58461,63 +253082,47 @@ ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_f16", + "name": "vmovq_n_f32", "arguments": [ - "float16x8_t a", - "float16x8_t v", - "const int lane" + "float32_t value" ], "return_type": { - "value": "float16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_f32", + "name": "vmovq_n_f64", "arguments": [ - "float32x4_t a", - "float32x4_t v", - "const int lane" + "float64_t value" ], "return_type": { - "value": "float32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58525,214 +253130,172 @@ ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_f64", + "name": "vmovq_n_p16", "arguments": [ - "float64x2_t a", - "float64x2_t v", - "const int lane" + "poly16_t value" ], "return_type": { - "value": "float64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2D" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_s16", + "name": "vmovq_n_p8", "arguments": [ - "int16x8_t a", - "int16x8_t v", - "const int lane" + "poly8_t value" ], "return_type": { - "value": "int16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_s32", + "name": "vmovq_n_s16", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "int16_t value" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_u16", + "name": "vmovq_n_s32", "arguments": [ - "uint16x8_t a", - "uint16x8_t v", - "const int lane" + "int32_t value" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_laneq_u32", + "name": "vmovq_n_s64", "arguments": [ - "uint32x4_t a", - "uint32x4_t v", - "const int lane" + "int64_t value" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_f16", + "name": "vmovq_n_s8", "arguments": [ - "float16x8_t a", - "float16_t n" + "int8_t value" ], "return_type": { - "value": "float16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "n": { - "register": "Vm.H[0]" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_f32", + "name": "vmovq_n_u16", "arguments": [ - "float32x4_t a", - "float32_t b" + "uint16_t value" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.S[0]" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58742,53 +253305,47 @@ ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_f64", + "name": "vmovq_n_u32", "arguments": [ - "float64x2_t a", - "float64_t b" + "uint32_t value" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.D[0]" + "value": { + "register": "rn" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_s16", + "name": "vmovq_n_u64", "arguments": [ - "int16x8_t a", - "int16_t b" + "uint64_t value" ], "return_type": { - "value": "int16x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.H[0]" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58798,26 +253355,22 @@ ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_s32", + "name": "vmovq_n_u8", "arguments": [ - "int32x4_t a", - "int32_t b" + "uint8_t value" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.S[0]" + "value": { + "register": "rn" } }, "Architectures": [ @@ -58827,55 +253380,54 @@ ], "instructions": [ [ - "MUL" + "DUP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_u16", + "name": "vmul_f16", "arguments": [ - "uint16x8_t a", - "uint16_t b" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.H[0]" + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_n_u32", + "name": "vmul_f32", "arguments": [ - "uint32x4_t a", - "uint32_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.S[0]" + "register": "Vm.2S" } }, "Architectures": [ @@ -58885,84 +253437,91 @@ ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_p8", + "name": "vmul_f64", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, "b": { - "register": "Vm.16B" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "PMUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_s16", + "name": "vmul_lane_f16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float16x4_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, - "b": { - "register": "Vm.8H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_s32", + "name": "vmul_lane_f32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float32x2_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, - "b": { - "register": "Vm.4S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -58972,55 +253531,63 @@ ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_s8", + "name": "vmul_lane_f64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float64x1_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MUL" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulq_u16", + "name": "vmul_lane_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int16x4_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, - "b": { - "register": "Vm.8H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -59036,20 +253603,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vmulq_u32", + "name": "vmul_lane_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x2_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, - "b": { - "register": "Vm.4S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -59065,20 +253637,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vmulq_u8", + "name": "vmul_lane_u16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint16x4_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -59094,18 +253671,18 @@ }, { "SIMD_ISA": "Neon", - "name": "vmuls_lane_f32", + "name": "vmul_lane_u32", "arguments": [ - "float32_t a", - "float32x2_t v", + "uint32x2_t a", + "uint32x2_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.2S" }, "lane": { "minimum": 0, @@ -59116,35 +253693,37 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMUL" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmuls_laneq_f32", + "name": "vmul_laneq_f16", "arguments": [ - "float32_t a", - "float32x4_t v", + "float16x4_t a", + "float16x8_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4H" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -59158,20 +253737,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vmulx_f16", + "name": "vmul_laneq_f32", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "float32x2_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, - "b": { - "register": "Vm.4H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -59179,26 +253763,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_f32", + "name": "vmul_laneq_f64", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "float64x1_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, - "b": { - "register": "Vm.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ @@ -59206,26 +253795,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_f64", + "name": "vmul_laneq_s16", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int16x4_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" }, - "b": { - "register": "Dm" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -59233,31 +253827,31 @@ ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_lane_f16", + "name": "vmul_laneq_s32", "arguments": [ - "float16x4_t a", - "float16x4_t v", + "int32x2_t a", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, "lane": { "minimum": 0, "maximum": 3 }, "v": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -59265,31 +253859,31 @@ ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_lane_f32", + "name": "vmul_laneq_u16", "arguments": [ - "float32x2_t a", - "float32x2_t v", + "uint16x4_t a", + "uint16x8_t v", "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "v": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ @@ -59297,31 +253891,31 @@ ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_lane_f64", + "name": "vmul_laneq_u32", "arguments": [ - "float64x1_t a", - "float64x1_t v", + "uint32x2_t a", + "uint32x4_t v", "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 3 }, "v": { - "register": "Vm.1D" + "register": "Vm.4S" } }, "Architectures": [ @@ -59329,17 +253923,16 @@ ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_laneq_f16", + "name": "vmul_n_f16", "arguments": [ "float16x4_t a", - "float16x8_t v", - "const int lane" + "float16_t n" ], "return_type": { "value": "float16x4_t" @@ -59348,30 +253941,26 @@ "a": { "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_laneq_f32", + "name": "vmul_n_f32", "arguments": [ "float32x2_t a", - "float32x4_t v", - "const int lane" + "float32_t b" ], "return_type": { "value": "float32x2_t" @@ -59380,30 +253969,27 @@ "a": { "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_laneq_f64", + "name": "vmul_n_f64", "arguments": [ "float64x1_t a", - "float64x2_t v", - "const int lane" + "float64_t b" ], "return_type": { "value": "float64x1_t" @@ -59412,12 +253998,8 @@ "a": { "register": "Dn" }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2D" + "b": { + "register": "Vm.D[0]" } }, "Architectures": [ @@ -59425,321 +254007,350 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulx_n_f16", + "name": "vmul_n_s16", "arguments": [ - "float16x4_t a", - "float16_t n" + "int16x4_t a", + "int16_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" }, - "n": { + "b": { "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxd_f64", + "name": "vmul_n_s32", "arguments": [ - "float64_t a", - "float64_t b" + "int32x2_t a", + "int32_t b" ], "return_type": { - "value": "float64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, "b": { - "register": "Dm" + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxd_lane_f64", + "name": "vmul_n_u16", "arguments": [ - "float64_t a", - "float64x1_t v", - "const int lane" + "uint16x4_t a", + "uint16_t b" ], "return_type": { - "value": "float64_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Vn.4H" }, - "v": { - "register": "Vm.1D" + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxd_laneq_f64", + "name": "vmul_n_u32", "arguments": [ - "float64_t a", - "float64x2_t v", - "const int lane" + "uint32x2_t a", + "uint32_t b" ], "return_type": { - "value": "float64_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.2S" }, - "v": { - "register": "Vm.2D" + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxh_f16", + "name": "vmul_p8", "arguments": [ - "float16_t a", - "float16_t b" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "float16_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8B" }, "b": { - "register": "Hm" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "PMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxh_lane_f16", + "name": "vmul_s16", "arguments": [ - "float16_t a", - "float16x4_t v", - "const int lane" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "float16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4H" }, - "v": { + "b": { "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxh_laneq_f16", + "name": "vmul_s32", "arguments": [ - "float16_t a", - "float16x8_t v", - "const int lane" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.2S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "MUL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmul_s8", + "arguments": [ + "int8x8_t a", + "int8x8_t b" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_f16", + "name": "vmul_u16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.8H" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_f32", + "name": "vmul_u32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_f64", + "name": "vmul_u8", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "float64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" }, "b": { - "register": "Vm.2D" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMULX" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_lane_f16", + "name": "vmuld_lane_f64", "arguments": [ - "float16x8_t a", - "float16x4_t v", + "float64_t a", + "float64x1_t v", "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Dn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 0 }, "v": { - "register": "Vm.4H" + "register": "Vm.1D" } }, "Architectures": [ @@ -59747,31 +254358,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_lane_f32", + "name": "vmuld_laneq_f64", "arguments": [ - "float32x4_t a", - "float32x2_t v", + "float64_t a", + "float64x2_t v", "const int lane" ], "return_type": { - "value": "float32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Dn" }, "lane": { "minimum": 0, "maximum": 1 }, "v": { - "register": "Vm.2S" + "register": "Vm.2D" } }, "Architectures": [ @@ -59779,31 +254390,59 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_lane_f64", + "name": "vmulh_f16", "arguments": [ - "float64x2_t a", - "float64x1_t v", + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmulh_lane_f16", + "arguments": [ + "float16_t a", + "float16x4_t v", "const int lane" ], "return_type": { - "value": "float64x2_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hn" }, "lane": { "minimum": 0, - "maximum": 0 + "maximum": 3 }, "v": { - "register": "Vm.1D" + "register": "Vm.4H" } }, "Architectures": [ @@ -59811,24 +254450,24 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_laneq_f16", + "name": "vmulh_laneq_f16", "arguments": [ - "float16x8_t a", + "float16_t a", "float16x8_t v", "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Hn" }, "lane": { "minimum": 0, @@ -59843,31 +254482,31 @@ ], "instructions": [ [ - "FMULX" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_laneq_f32", + "name": "vmull_high_lane_s16", "arguments": [ - "float32x4_t a", - "float32x4_t v", + "int16x8_t a", + "int16x4_t v", "const int lane" ], "return_type": { - "value": "float32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8H" }, "lane": { "minimum": 0, "maximum": 3 }, "v": { - "register": "Vm.4S" + "register": "Vm.4H" } }, "Architectures": [ @@ -59875,31 +254514,31 @@ ], "instructions": [ [ - "FMULX" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_laneq_f64", + "name": "vmull_high_lane_s32", "arguments": [ - "float64x2_t a", - "float64x2_t v", + "int32x4_t a", + "int32x2_t v", "const int lane" ], "return_type": { - "value": "float64x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "lane": { "minimum": 0, "maximum": 1 }, "v": { - "register": "Vm.2D" + "register": "Vm.2S" } }, "Architectures": [ @@ -59907,26 +254546,31 @@ ], "instructions": [ [ - "FMULX" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxq_n_f16", + "name": "vmull_high_lane_u16", "arguments": [ - "float16x8_t a", - "float16_t n" + "uint16x8_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "float16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "n": { - "register": "Vm.H[0]" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -59934,26 +254578,31 @@ ], "instructions": [ [ - "FMULX" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxs_f32", + "name": "vmull_high_lane_u32", "arguments": [ - "float32_t a", - "float32_t b" + "uint32x4_t a", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "float32_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4S" }, - "b": { - "register": "Sm" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -59961,31 +254610,31 @@ ], "instructions": [ [ - "FMULX" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxs_lane_f32", + "name": "vmull_high_laneq_s16", "arguments": [ - "float32_t a", - "float32x2_t v", + "int16x8_t a", + "int16x8_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.8H" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "v": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ @@ -59993,24 +254642,24 @@ ], "instructions": [ [ - "FMULX" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmulxs_laneq_f32", + "name": "vmull_high_laneq_s32", "arguments": [ - "float32_t a", - "float32x4_t v", + "int32x4_t a", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "float32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4S" }, "lane": { "minimum": 0, @@ -60025,396 +254674,454 @@ ], "instructions": [ [ - "FMULX" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_p8", + "name": "vmull_high_laneq_u16", "arguments": [ - "poly8x8_t a" + "uint16x8_t a", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_s16", + "name": "vmull_high_laneq_u32", "arguments": [ - "int16x4_t a" + "uint32x4_t a", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_s32", + "name": "vmull_high_n_s16", "arguments": [ - "int32x2_t a" + "int16x8_t a", + "int16_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_s8", + "name": "vmull_high_n_s32", "arguments": [ - "int8x8_t a" + "int32x4_t a", + "int32_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_u16", + "name": "vmull_high_n_u16", "arguments": [ - "uint16x4_t a" + "uint16x8_t a", + "uint16_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_u32", + "name": "vmull_high_n_u32", "arguments": [ - "uint32x2_t a" + "uint32x4_t a", + "uint32_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvn_u8", + "name": "vmull_high_p64", "arguments": [ - "uint8x8_t a" + "poly64x2_t a", + "poly64x2_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MVN" + "PMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_p8", + "name": "vmull_high_p8", "arguments": [ - "poly8x16_t a" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "PMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_s16", + "name": "vmull_high_s16", "arguments": [ - "int16x8_t a" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_s32", + "name": "vmull_high_s32", "arguments": [ - "int32x4_t a" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_s8", + "name": "vmull_high_s8", "arguments": [ - "int8x16_t a" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "SMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_u16", + "name": "vmull_high_u16", "arguments": [ - "uint16x8_t a" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_u32", + "name": "vmull_high_u32", "arguments": [ - "uint32x4_t a" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vmvnq_u8", + "name": "vmull_high_u8", "arguments": [ - "uint8x16_t a" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MVN" + "UMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_f16", + "name": "vmull_lane_s16", "arguments": [ - "float16x4_t a" + "int16x4_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FNEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_f32", + "name": "vmull_lane_s32", "arguments": [ - "float32x2_t a" + "int32x2_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -60424,45 +255131,65 @@ ], "instructions": [ [ - "FNEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_f64", + "name": "vmull_lane_u16", "arguments": [ - "float64x1_t a" + "uint16x4_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FNEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_s16", + "name": "vmull_lane_u32", "arguments": [ - "int16x4_t a" + "uint32x2_t a", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -60472,47 +255199,63 @@ ], "instructions": [ [ - "NEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_s32", + "name": "vmull_laneq_s16", "arguments": [ - "int32x2_t a" + "int16x4_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_s64", + "name": "vmull_laneq_s32", "arguments": [ - "int64x1_t a" + "int32x2_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -60520,47 +255263,63 @@ ], "instructions": [ [ - "NEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vneg_s8", + "name": "vmull_laneq_u16", "arguments": [ - "int8x8_t a" + "uint16x4_t a", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegd_s64", + "name": "vmull_laneq_u32", "arguments": [ - "int64_t a" + "uint32x2_t a", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -60568,70 +255327,84 @@ ], "instructions": [ [ - "NEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegh_f16", + "name": "vmull_n_s16", "arguments": [ - "float16_t a" + "int16x4_t a", + "int16_t b" ], "return_type": { - "value": "float16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FNEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_f16", + "name": "vmull_n_s32", "arguments": [ - "float16x8_t a" + "int32x2_t a", + "int32_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FNEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_f32", + "name": "vmull_n_u16", "arguments": [ - "float32x4_t a" + "uint16x4_t a", + "uint16_t b" ], "return_type": { - "value": "float32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -60641,70 +255414,83 @@ ], "instructions": [ [ - "FNEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_f64", + "name": "vmull_n_u32", "arguments": [ - "float64x2_t a" + "uint32x2_t a", + "uint32_t b" ], "return_type": { - "value": "float64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FNEG" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_s16", + "name": "vmull_p64", "arguments": [ - "int16x8_t a" + "poly64_t a", + "poly64_t b" ], "return_type": { - "value": "int16x8_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.1D" + }, + "b": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "NEG" + "PMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_s32", + "name": "vmull_p8", "arguments": [ - "int32x4_t a" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ @@ -60714,45 +255500,55 @@ ], "instructions": [ [ - "NEG" + "PMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_s64", + "name": "vmull_s16", "arguments": [ - "int64x2_t a" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "NEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vnegq_s8", + "name": "vmull_s32", "arguments": [ - "int8x16_t a" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ @@ -60762,19 +255558,19 @@ ], "instructions": [ [ - "NEG" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_s16", + "name": "vmull_s8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -60791,26 +255587,26 @@ ], "instructions": [ [ - "ORN" + "SMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_s32", + "name": "vmull_u16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, "b": { - "register": "Vm.8B" + "register": "Vm.4H" } }, "Architectures": [ @@ -60820,26 +255616,26 @@ ], "instructions": [ [ - "ORN" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_s64", + "name": "vmull_u32", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" }, "b": { - "register": "Vm.8B" + "register": "Vm.2S" } }, "Architectures": [ @@ -60849,19 +255645,19 @@ ], "instructions": [ [ - "ORN" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_s8", + "name": "vmull_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -60878,55 +255674,54 @@ ], "instructions": [ [ - "ORN" + "UMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_u16", + "name": "vmulq_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { - "register": "Vm.8B" + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_u32", + "name": "vmulq_f32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, "b": { - "register": "Vm.8B" + "register": "Vm.4S" } }, "Architectures": [ @@ -60936,84 +255731,91 @@ ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_u64", + "name": "vmulq_f64", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, "b": { - "register": "Vm.8B" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorn_u8", + "name": "vmulq_lane_f16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float16x8_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_s16", + "name": "vmulq_lane_f32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float32x4_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -61023,55 +255825,63 @@ ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_s32", + "name": "vmulq_lane_f64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float64x2_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_s64", + "name": "vmulq_lane_s16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int16x8_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -61081,26 +255891,31 @@ ], "instructions": [ [ - "ORN" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_s8", + "name": "vmulq_lane_s32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int32x4_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -61110,26 +255925,31 @@ ], "instructions": [ [ - "ORN" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_u16", + "name": "vmulq_lane_u16", "arguments": [ "uint16x8_t a", - "uint16x8_t b" + "uint16x4_t v", + "const int lane" ], "return_type": { "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -61139,26 +255959,31 @@ ], "instructions": [ [ - "ORN" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_u32", + "name": "vmulq_lane_u32", "arguments": [ "uint32x4_t a", - "uint32x4_t b" + "uint32x2_t v", + "const int lane" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -61168,258 +255993,278 @@ ], "instructions": [ [ - "ORN" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_u64", + "name": "vmulq_laneq_f16", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "float16x8_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vornq_u8", + "name": "vmulq_laneq_f32", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "float32x4_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORN" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_s16", + "name": "vmulq_laneq_f64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float64x2_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_s32", + "name": "vmulq_laneq_s16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int16x8_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_s64", + "name": "vmulq_laneq_s32", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int32x4_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_s8", + "name": "vmulq_laneq_u16", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint16x8_t a", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_u16", + "name": "vmulq_laneq_u32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint32x4_t a", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_u32", + "name": "vmulq_n_f16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "float16x8_t a", + "float16_t n" ], "return_type": { - "value": "uint32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vm.8B" + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_u64", + "name": "vmulq_n_f32", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "float32x4_t a", + "float32_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, "b": { - "register": "Vm.8B" + "register": "Vm.S[0]" } }, "Architectures": [ @@ -61429,55 +256274,53 @@ ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorr_u8", + "name": "vmulq_n_f64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float64x2_t a", + "float64_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, "b": { - "register": "Vm.8B" + "register": "Vm.D[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ORR" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_s16", + "name": "vmulq_n_s16", "arguments": [ "int16x8_t a", - "int16x8_t b" + "int16_t b" ], "return_type": { "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.H[0]" } }, "Architectures": [ @@ -61487,26 +256330,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_s32", + "name": "vmulq_n_s32", "arguments": [ "int32x4_t a", - "int32x4_t b" + "int32_t b" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.S[0]" } }, "Architectures": [ @@ -61516,26 +256359,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_s64", + "name": "vmulq_n_u16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "uint16x8_t a", + "uint16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.H[0]" } }, "Architectures": [ @@ -61545,26 +256388,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_s8", + "name": "vmulq_n_u32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint32x4_t a", + "uint32_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.S[0]" } }, "Architectures": [ @@ -61574,19 +256417,19 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_u16", + "name": "vmulq_p8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -61603,26 +256446,26 @@ ], "instructions": [ [ - "ORR" + "PMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_u32", + "name": "vmulq_s16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.8H" } }, "Architectures": [ @@ -61632,26 +256475,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_u64", + "name": "vmulq_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.4S" } }, "Architectures": [ @@ -61661,19 +256504,19 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vorrq_u8", + "name": "vmulq_s8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { @@ -61690,26 +256533,26 @@ ], "instructions": [ [ - "ORR" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_s16", + "name": "vmulq_u16", "arguments": [ - "int32x2_t a", - "int16x4_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8H" }, "b": { - "register": "Vn.4H" + "register": "Vm.8H" } }, "Architectures": [ @@ -61719,26 +256562,26 @@ ], "instructions": [ [ - "SADALP" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_s32", + "name": "vmulq_u32", "arguments": [ - "int64x1_t a", - "int32x2_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.4S" }, "b": { - "register": "Vn.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -61748,26 +256591,26 @@ ], "instructions": [ [ - "SADALP" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_s8", + "name": "vmulq_u8", "arguments": [ - "int16x4_t a", - "int8x8_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.16B" }, "b": { - "register": "Vn.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -61777,277 +256620,258 @@ ], "instructions": [ [ - "SADALP" + "MUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_u16", + "name": "vmuls_lane_f32", "arguments": [ - "uint32x2_t a", - "uint16x4_t b" + "float32_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Sn" }, - "b": { - "register": "Vn.4H" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "UADALP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vpadal_u32", - "arguments": [ - "uint64x1_t a", - "uint32x2_t b" - ], - "return_type": { - "value": "uint64x1_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.1D" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vn.2S" + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadal_u8", + "name": "vmuls_laneq_f32", "arguments": [ - "uint16x4_t a", - "uint8x8_t b" + "float32_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Sn" }, - "b": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMUL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_s16", + "name": "vmulx_f16", "arguments": [ - "int32x4_t a", - "int16x8_t b" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4H" }, "b": { - "register": "Vn.8H" + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_s32", + "name": "vmulx_f32", "arguments": [ - "int64x2_t a", - "int32x4_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2S" }, "b": { - "register": "Vn.4S" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_s8", + "name": "vmulx_f64", "arguments": [ - "int16x8_t a", - "int8x16_t b" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "int16x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dn" }, "b": { - "register": "Vn.16B" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_u16", + "name": "vmulx_lane_f16", "arguments": [ - "uint32x4_t a", - "uint16x8_t b" + "float16x4_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4H" }, - "b": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_u32", + "name": "vmulx_lane_f32", "arguments": [ - "uint64x2_t a", - "uint32x4_t b" + "float32x2_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2S" }, - "b": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadalq_u8", + "name": "vmulx_lane_f64", "arguments": [ - "uint16x8_t a", - "uint8x16_t b" + "float64x1_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dn" }, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADALP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_f16", + "name": "vmulx_laneq_f16", "arguments": [ "float16x4_t a", - "float16x4_t b" + "float16x8_t v", + "const int lane" ], "return_type": { "value": "float16x4_t" @@ -62056,26 +256880,30 @@ "a": { "register": "Vn.4H" }, - "b": { - "register": "Vm.4H" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_f32", + "name": "vmulx_laneq_f32", "arguments": [ "float32x2_t a", - "float32x2_t b" + "float32x4_t v", + "const int lane" ], "return_type": { "value": "float32x2_t" @@ -62084,207 +256912,221 @@ "a": { "register": "Vn.2S" }, - "b": { - "register": "Vm.2S" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_s16", + "name": "vmulx_laneq_f64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float64x1_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, - "b": { - "register": "Vm.4H" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_s32", + "name": "vmulx_n_f16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float16x4_t a", + "float16_t n" ], "return_type": { - "value": "int32x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4H" }, - "b": { - "register": "Vm.2S" + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_s8", + "name": "vmulxd_f64", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "float64_t a", + "float64_t b" ], "return_type": { - "value": "int8x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Dn" }, "b": { - "register": "Vm.8B" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_u16", + "name": "vmulxd_lane_f64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "float64_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, - "b": { - "register": "Vm.4H" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_u32", + "name": "vmulxd_laneq_f64", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "float64_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, - "b": { - "register": "Vm.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadd_u8", + "name": "vmulxh_f16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Hn" }, "b": { - "register": "Vm.8B" + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddd_f64", + "name": "vmulxh_lane_f16", "arguments": [ - "float64x2_t a" + "float16_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "float64_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -62292,22 +257134,31 @@ ], "instructions": [ [ - "FADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddd_s64", + "name": "vmulxh_laneq_f16", "arguments": [ - "int64x2_t a" + "float16_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -62315,22 +257166,26 @@ ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddd_u64", + "name": "vmulxq_f16", "arguments": [ - "uint64x2_t a" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint64_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -62338,674 +257193,711 @@ ], "instructions": [ [ - "ADDP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_s16", + "name": "vmulxq_f32", "arguments": [ - "int16x4_t a" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_s32", + "name": "vmulxq_f64", "arguments": [ - "int32x2_t a" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_s8", + "name": "vmulxq_lane_f16", "arguments": [ - "int8x8_t a" + "float16x8_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_u16", + "name": "vmulxq_lane_f32", "arguments": [ - "uint16x4_t a" + "float32x4_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_u32", + "name": "vmulxq_lane_f64", "arguments": [ - "uint32x2_t a" + "float64x2_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" + }, + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vm.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddl_u8", + "name": "vmulxq_laneq_f16", "arguments": [ - "uint8x8_t a" + "float16x8_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_s16", + "name": "vmulxq_laneq_f32", "arguments": [ - "int16x8_t a" + "float32x4_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_s32", + "name": "vmulxq_laneq_f64", "arguments": [ - "int32x4_t a" + "float64x2_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_s8", + "name": "vmulxq_n_f16", "arguments": [ - "int8x16_t a" + "float16x8_t a", + "float16_t n" ], "return_type": { - "value": "int16x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" + }, + "n": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_u16", + "name": "vmulxs_f32", "arguments": [ - "uint16x8_t a" + "float32_t a", + "float32_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_u32", + "name": "vmulxs_lane_f32", "arguments": [ - "uint32x4_t a" + "float32_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddlq_u8", + "name": "vmulxs_laneq_f32", "arguments": [ - "uint8x16_t a" + "float32_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UADDLP" + "FMULX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_f16", + "name": "vmvn_p8", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly8x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_f32", + "name": "vmvn_s16", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_f64", + "name": "vmvn_s32", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_s16", + "name": "vmvn_s8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int8x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_s32", + "name": "vmvn_u16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint16x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_s64", + "name": "vmvn_u32", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "uint32x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_s8", + "name": "vmvn_u8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint8x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_u16", + "name": "vmvnq_p8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly8x16_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_u32", + "name": "vmvnq_s16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_u64", + "name": "vmvnq_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpaddq_u8", + "name": "vmvnq_s8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpadds_f32", + "name": "vmvnq_u16", "arguments": [ - "float32x2_t a" + "uint16x8_t a" ], "return_type": { - "value": "float32_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FADDP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_f16", + "name": "vmvnq_u32", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "uint32x4_t a" ], "return_type": { - "value": "float16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMAXP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_f32", + "name": "vmvnq_u8", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint8x16_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.16B" } }, "Architectures": [ @@ -63015,55 +257907,46 @@ ], "instructions": [ [ - "FMAXP" + "MVN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_s16", + "name": "vneg_f16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SMAXP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_s32", + "name": "vneg_f32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "float32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" } }, "Architectures": [ @@ -63073,55 +257956,45 @@ ], "instructions": [ [ - "SMAXP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_s8", + "name": "vneg_f64", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "float64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SMAXP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_u16", + "name": "vneg_s16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" } }, "Architectures": [ @@ -63131,26 +258004,22 @@ ], "instructions": [ [ - "UMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_u32", + "name": "vneg_s32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" } }, "Architectures": [ @@ -63160,82 +258029,70 @@ ], "instructions": [ [ - "UMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmax_u8", + "name": "vneg_s64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "int64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnm_f16", + "name": "vneg_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int8x8_t a" ], "return_type": { - "value": "float16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnm_f32", + "name": "vnegd_s64", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int64_t a" ], "return_type": { - "value": "float32x2_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Dn" } }, "Architectures": [ @@ -63243,99 +258100,91 @@ ], "instructions": [ [ - "FMAXNMP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnmq_f16", + "name": "vnegh_f16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "float16_t a" ], "return_type": { - "value": "float16x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Hn" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnmq_f32", + "name": "vnegq_f16", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "float16x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnmq_f64", + "name": "vnegq_f32", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "float32x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnmqd_f64", + "name": "vnegq_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "float64_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -63347,76 +258196,72 @@ ], "instructions": [ [ - "FMAXNMP" + "FNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxnms_f32", + "name": "vnegq_s16", "arguments": [ - "float32x2_t a" + "int16x8_t a" ], "return_type": { - "value": "float32_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXNMP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_f16", + "name": "vnegq_s32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int32x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_f32", + "name": "vnegq_s64", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int64x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.2D" } }, "Architectures": [ @@ -63424,289 +258269,312 @@ ], "instructions": [ [ - "FMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_f64", + "name": "vnegq_s8", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int8x16_t a" ], "return_type": { - "value": "float64x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "NEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_s16", + "name": "vorn_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_s32", + "name": "vorn_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_s8", + "name": "vorn_s64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_u16", + "name": "vorn_s8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_u32", + "name": "vorn_u16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxq_u8", + "name": "vorn_u32", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxqd_f64", + "name": "vorn_u64", "arguments": [ - "float64x2_t a" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "float64_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmaxs_f32", + "name": "vorn_u8", "arguments": [ - "float32x2_t a" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "float32_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMAXP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_f16", + "name": "vornq_s16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" }, "b": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_f32", + "name": "vornq_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" }, "b": { - "register": "Vm.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -63716,26 +258584,26 @@ ], "instructions": [ [ - "FMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_s16", + "name": "vornq_s64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" }, "b": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ @@ -63745,26 +258613,26 @@ ], "instructions": [ [ - "SMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_s32", + "name": "vornq_s8", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" }, "b": { - "register": "Vm.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -63774,26 +258642,26 @@ ], "instructions": [ [ - "SMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_s8", + "name": "vornq_u16", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.16B" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -63803,26 +258671,26 @@ ], "instructions": [ [ - "SMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_u16", + "name": "vornq_u32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" }, "b": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ @@ -63832,26 +258700,26 @@ ], "instructions": [ [ - "UMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_u32", + "name": "vornq_u64", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" }, "b": { - "register": "Vm.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -63861,26 +258729,26 @@ ], "instructions": [ [ - "UMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmin_u8", + "name": "vornq_u8", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.16B" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -63890,335 +258758,367 @@ ], "instructions": [ [ - "UMINP" + "ORN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnm_f16", + "name": "vorr_s16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8B" }, "b": { - "register": "Vm.4H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnm_f32", + "name": "vorr_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8B" }, "b": { - "register": "Vm.2S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnmq_f16", + "name": "vorr_s64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnmq_f32", + "name": "vorr_s8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnmq_f64", + "name": "vorr_u16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" }, "b": { - "register": "Vm.2D" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnmqd_f64", + "name": "vorr_u32", "arguments": [ - "float64x2_t a" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float64_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminnms_f32", + "name": "vorr_u64", "arguments": [ - "float32x2_t a" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "float32_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINNMP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_f16", + "name": "vorr_u8", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_f32", + "name": "vorrq_s16", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_f64", + "name": "vorrq_s32", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, "b": { - "register": "Vm.2D" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_s16", + "name": "vorrq_s64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_s32", + "name": "vorrq_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_s8", + "name": "vorrq_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -64229,71 +259129,77 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_u16", + "name": "vorrq_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_u32", + "name": "vorrq_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminq_u8", + "name": "vorrq_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -64310,72 +259216,90 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UMINP" + "ORR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpminqd_f64", + "name": "vpadal_s16", "arguments": [ - "float64x2_t a" + "int32x2_t a", + "int16x4_t b" ], "return_type": { - "value": "float64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vpmins_f32", + "name": "vpadal_s32", "arguments": [ - "float32x2_t a" + "int64x1_t a", + "int32x2_t b" ], "return_type": { - "value": "float32_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.1D" + }, + "b": { "register": "Vn.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FMINP" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabs_s16", + "name": "vpadal_s8", "arguments": [ - "int16x4_t a" + "int16x4_t a", + "int8x8_t b" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4H" + }, + "b": { + "register": "Vn.8B" } }, "Architectures": [ @@ -64385,22 +259309,26 @@ ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabs_s32", + "name": "vpadal_u16", "arguments": [ - "int32x2_t a" + "uint32x2_t a", + "uint16x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2S" + }, + "b": { + "register": "Vn.4H" } }, "Architectures": [ @@ -64410,44 +259338,54 @@ ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabs_s64", + "name": "vpadal_u32", "arguments": [ - "int64x1_t a" + "uint64x1_t a", + "uint32x2_t b" ], "return_type": { - "value": "int64x1_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.1D" + }, + "b": { + "register": "Vn.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabs_s8", + "name": "vpadal_u8", "arguments": [ - "int8x8_t a" + "uint16x4_t a", + "uint8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4H" + }, + "b": { "register": "Vn.8B" } }, @@ -64458,90 +259396,112 @@ ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsb_s8", + "name": "vpadalq_s16", "arguments": [ - "int8_t a" + "int32x4_t a", + "int16x8_t b" ], "return_type": { - "value": "int8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsd_s64", + "name": "vpadalq_s32", "arguments": [ - "int64_t a" + "int64x2_t a", + "int32x4_t b" ], "return_type": { - "value": "int64_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsh_s16", + "name": "vpadalq_s8", "arguments": [ - "int16_t a" + "int16x8_t a", + "int8x16_t b" ], "return_type": { - "value": "int16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.8H" + }, + "b": { + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "SADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsq_s16", + "name": "vpadalq_u16", "arguments": [ - "int16x8_t a" + "uint32x4_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.8H" } }, @@ -64552,21 +259512,25 @@ ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsq_s32", + "name": "vpadalq_u32", "arguments": [ - "int32x4_t a" + "uint64x2_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.4S" } }, @@ -64577,84 +259541,99 @@ ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsq_s64", + "name": "vpadalq_u8", "arguments": [ - "int64x2_t a" + "uint16x8_t a", + "uint8x16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.8H" + }, + "b": { + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "UADALP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabsq_s8", + "name": "vpadd_f16", "arguments": [ - "int8x16_t a" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int8x16_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SQABS" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqabss_s32", + "name": "vpadd_f32", "arguments": [ - "int32_t a" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int32_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQABS" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_s16", + "name": "vpadd_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -64677,13 +259656,13 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_s32", + "name": "vpadd_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -64706,26 +259685,26 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_s64", + "name": "vpadd_s8", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8B" }, "b": { - "register": "Dm" + "register": "Vm.8B" } }, "Architectures": [ @@ -64735,26 +259714,26 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_s8", + "name": "vpadd_u16", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, "b": { - "register": "Vm.8B" + "register": "Vm.4H" } }, "Architectures": [ @@ -64764,26 +259743,26 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_u16", + "name": "vpadd_u32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, "b": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -64793,26 +259772,26 @@ ], "instructions": [ [ - "UQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_u32", + "name": "vpadd_u8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8B" }, "b": { - "register": "Vm.2S" + "register": "Vm.8B" } }, "Architectures": [ @@ -64822,84 +259801,68 @@ ], "instructions": [ [ - "UQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_u64", + "name": "vpaddd_f64", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "float64x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQADD" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadd_u8", + "name": "vpaddd_s64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "int64x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddb_s8", + "name": "vpaddd_u64", "arguments": [ - "int8_t a", - "int8_t b" + "uint64x2_t a" ], "return_type": { - "value": "int8_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" - }, - "b": { - "register": "Bm" + "register": "Vn.2D" } }, "Architectures": [ @@ -64907,161 +259870,147 @@ ], "instructions": [ [ - "SQADD" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddb_u8", + "name": "vpaddl_s16", "arguments": [ - "uint8_t a", - "uint8_t b" + "int16x4_t a" ], "return_type": { - "value": "uint8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" - }, - "b": { - "register": "Bm" + "register": "Vn.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddd_s64", + "name": "vpaddl_s32", "arguments": [ - "int64_t a", - "int64_t b" + "int32x2_t a" ], "return_type": { - "value": "int64_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddd_u64", + "name": "vpaddl_s8", "arguments": [ - "uint64_t a", - "uint64_t b" + "int8x8_t a" ], "return_type": { - "value": "uint64_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddh_s16", + "name": "vpaddl_u16", "arguments": [ - "int16_t a", - "int16_t b" + "uint16x4_t a" ], "return_type": { - "value": "int16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "b": { - "register": "Hm" + "register": "Vn.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddh_u16", + "name": "vpaddl_u32", "arguments": [ - "uint16_t a", - "uint16_t b" + "uint32x2_t a" ], "return_type": { - "value": "uint16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "b": { - "register": "Hm" + "register": "Vn.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_s16", + "name": "vpaddl_u8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint8x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.8B" } }, "Architectures": [ @@ -65071,26 +260020,22 @@ ], "instructions": [ [ - "SQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_s32", + "name": "vpaddlq_s16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int16x8_t a" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ @@ -65100,26 +260045,22 @@ ], "instructions": [ [ - "SQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_s64", + "name": "vpaddlq_s32", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int32x4_t a" ], "return_type": { "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.4S" } }, "Architectures": [ @@ -65129,26 +260070,22 @@ ], "instructions": [ [ - "SQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_s8", + "name": "vpaddlq_s8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" } }, "Architectures": [ @@ -65158,26 +260095,22 @@ ], "instructions": [ [ - "SQADD" + "SADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_u16", + "name": "vpaddlq_u16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" } }, "Architectures": [ @@ -65187,26 +260120,22 @@ ], "instructions": [ [ - "UQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_u32", + "name": "vpaddlq_u32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" } }, "Architectures": [ @@ -65216,26 +260145,22 @@ ], "instructions": [ [ - "UQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_u64", + "name": "vpaddlq_u8", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "uint8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.16B" } }, "Architectures": [ @@ -65245,55 +260170,53 @@ ], "instructions": [ [ - "UQADD" + "UADDLP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqaddq_u8", + "name": "vpaddq_f16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQADD" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadds_s32", + "name": "vpaddq_f32", "arguments": [ - "int32_t a", - "int32_t b" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.4S" }, "b": { - "register": "Sm" + "register": "Vm.4S" } }, "Architectures": [ @@ -65301,26 +260224,26 @@ ], "instructions": [ [ - "SQADD" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqadds_u32", + "name": "vpaddq_f64", "arguments": [ - "uint32_t a", - "uint32_t b" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint32_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.2D" }, "b": { - "register": "Sm" + "register": "Vm.2D" } }, "Architectures": [ @@ -65328,35 +260251,53 @@ ], "instructions": [ [ - "UQADD" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_lane_s16", + "name": "vpaddq_s16", + "arguments": [ + "int16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vpaddq_s32", "arguments": [ "int32x4_t a", - "int16x8_t b", - "int16x4_t v", - "const int lane" + "int32x4_t b" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -65364,35 +260305,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_lane_s32", + "name": "vpaddq_s64", "arguments": [ "int64x2_t a", - "int32x4_t b", - "int32x2_t v", - "const int lane" + "int64x2_t b" ], "return_type": { "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2D" }, "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.2D" } }, "Architectures": [ @@ -65400,35 +260332,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_laneq_s16", + "name": "vpaddq_s8", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t v", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ @@ -65436,35 +260359,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_laneq_s32", + "name": "vpaddq_u16", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t v", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -65472,30 +260386,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_n_s16", + "name": "vpaddq_u32", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16_t c" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.4S" } }, "Architectures": [ @@ -65503,30 +260413,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_n_s32", + "name": "vpaddq_u64", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32_t c" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.2D" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.2D" } }, "Architectures": [ @@ -65534,30 +260440,26 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_s16", + "name": "vpaddq_u8", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t c" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ @@ -65565,30 +260467,22 @@ ], "instructions": [ [ - "SQDMLAL2" + "ADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_high_s32", + "name": "vpadds_f32", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t c" + "float32x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.4S" + "register": "Vn.2S" } }, "Architectures": [ @@ -65596,72 +260490,53 @@ ], "instructions": [ [ - "SQDMLAL2" + "FADDP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_lane_s16", + "name": "vpmax_f16", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { + "b": { "register": "Vm.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_lane_s32", + "name": "vpmax_f32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { + "b": { "register": "Vm.2S" } }, @@ -65672,102 +260547,84 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_laneq_s16", + "name": "vpmax_s16", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x8_t v", - "const int lane" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_laneq_s32", + "name": "vpmax_s32", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x4_t v", - "const int lane" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLAL" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_n_s16", + "name": "vpmax_s8", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16_t c" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8B" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.8B" } }, "Architectures": [ @@ -65777,30 +260634,26 @@ ], "instructions": [ [ - "SQDMLAL" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_n_s32", + "name": "vpmax_u16", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32_t c" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.4H" } }, "Architectures": [ @@ -65810,30 +260663,26 @@ ], "instructions": [ [ - "SQDMLAL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_s16", + "name": "vpmax_u32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t c" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -65843,30 +260692,26 @@ ], "instructions": [ [ - "SQDMLAL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlal_s32", + "name": "vpmax_u8", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t c" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vm.8B" } }, "Architectures": [ @@ -65876,34 +260721,25 @@ ], "instructions": [ [ - "SQDMLAL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlalh_lane_s16", + "name": "vpmaxnm_f16", "arguments": [ - "int32_t a", - "int16_t b", - "int16x4_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int32_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.4H" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { "register": "Vm.4H" } }, @@ -65912,35 +260748,26 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlalh_laneq_s16", + "name": "vpmaxnm_f32", "arguments": [ - "int32_t a", - "int16_t b", - "int16x8_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int32_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.2S" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ @@ -65948,30 +260775,26 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlalh_s16", + "name": "vpmaxnmq_f16", "arguments": [ - "int32_t a", - "int16_t b", - "int16_t c" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int32_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.8H" }, "b": { - "register": "Hn" - }, - "c": { - "register": "Hm" + "register": "Vm.8H" } }, "Architectures": [ @@ -65979,35 +260802,26 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlals_lane_s32", + "name": "vpmaxnmq_f32", "arguments": [ - "int64_t a", - "int32_t b", - "int32x2_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int64_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.4S" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -66015,35 +260829,26 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlals_laneq_s32", + "name": "vpmaxnmq_f64", "arguments": [ - "int64_t a", - "int32_t b", - "int32x4_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int64_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2D" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.2D" } }, "Architectures": [ @@ -66051,30 +260856,45 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlals_s32", + "name": "vpmaxnmqd_f64", + "arguments": [ + "float64x2_t a" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vpmaxnms_f32", "arguments": [ - "int64_t a", - "int32_t b", - "int32_t c" + "float32x2_t a" ], "return_type": { - "value": "int64_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Sn" - }, - "c": { - "register": "Sm" + "register": "Vn.2S" } }, "Architectures": [ @@ -66082,35 +260902,26 @@ ], "instructions": [ [ - "SQDMLAL" + "FMAXNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_lane_s16", + "name": "vpmaxq_f16", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x4_t v", - "const int lane" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -66118,35 +260929,26 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_lane_s32", + "name": "vpmaxq_f32", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x2_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -66154,35 +260956,26 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_laneq_s16", + "name": "vpmaxq_f64", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2D" }, "b": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.2D" } }, "Architectures": [ @@ -66190,35 +260983,26 @@ ], "instructions": [ [ - "SQDMLSL2" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_laneq_s32", + "name": "vpmaxq_s16", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -66226,30 +261010,26 @@ ], "instructions": [ [ - "SQDMLSL2" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_n_s16", + "name": "vpmaxq_s32", "arguments": [ "int32x4_t a", - "int16x8_t b", - "int16_t c" + "int32x4_t b" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.4S" } }, "Architectures": [ @@ -66257,30 +261037,26 @@ ], "instructions": [ [ - "SQDMLSL2" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_n_s32", + "name": "vpmaxq_s8", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32_t c" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.16B" }, "b": { - "register": "Vn.4S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.16B" } }, "Architectures": [ @@ -66288,29 +261064,25 @@ ], "instructions": [ [ - "SQDMLSL2" + "SMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_s16", + "name": "vpmaxq_u16", "arguments": [ - "int32x4_t a", - "int16x8_t b", - "int16x8_t c" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.8H" }, - "c": { + "b": { "register": "Vm.8H" } }, @@ -66319,29 +261091,25 @@ ], "instructions": [ [ - "SQDMLSL2" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_high_s32", + "name": "vpmaxq_u32", "arguments": [ - "int64x2_t a", - "int32x4_t b", - "int32x4_t c" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.4S" }, - "c": { + "b": { "register": "Vm.4S" } }, @@ -66350,111 +261118,72 @@ ], "instructions": [ [ - "SQDMLSL2" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_lane_s16", + "name": "vpmaxq_u8", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t v", - "const int lane" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "UMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_lane_s32", + "name": "vpmaxqd_f64", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_laneq_s16", + "name": "vpmaxs_f32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x8_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.2S" } }, "Architectures": [ @@ -66462,66 +261191,54 @@ ], "instructions": [ [ - "SQDMLSL" + "FMAXP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_laneq_s32", + "name": "vpmin_f16", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x4_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_n_s16", + "name": "vpmin_f32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16_t c" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.H[0]" + "register": "Vm.2S" } }, "Architectures": [ @@ -66531,30 +261248,26 @@ ], "instructions": [ [ - "SQDMLSL" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_n_s32", + "name": "vpmin_s16", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32_t c" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.S[0]" + "register": "Vm.4H" } }, "Architectures": [ @@ -66564,30 +261277,26 @@ ], "instructions": [ [ - "SQDMLSL" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_s16", + "name": "vpmin_s32", "arguments": [ - "int32x4_t a", - "int16x4_t b", - "int16x4_t c" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -66597,30 +261306,26 @@ ], "instructions": [ [ - "SQDMLSL" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsl_s32", + "name": "vpmin_s8", "arguments": [ - "int64x2_t a", - "int32x2_t b", - "int32x2_t c" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.2S" - }, - "c": { - "register": "Vm.2S" + "register": "Vm.8B" } }, "Architectures": [ @@ -66630,138 +261335,113 @@ ], "instructions": [ [ - "SQDMLSL" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlslh_lane_s16", + "name": "vpmin_u16", "arguments": [ - "int32_t a", - "int16_t b", - "int16x4_t v", - "const int lane" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int32_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.4H" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlslh_laneq_s16", + "name": "vpmin_u32", "arguments": [ - "int32_t a", - "int16_t b", - "int16x8_t v", - "const int lane" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int32_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.2S" }, "b": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlslh_s16", + "name": "vpmin_u8", "arguments": [ - "int32_t a", - "int16_t b", - "int16_t c" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int32_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.8B" }, "b": { - "register": "Hn" - }, - "c": { - "register": "Hm" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMLSL" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsls_lane_s32", + "name": "vpminnm_f16", "arguments": [ - "int64_t a", - "int32_t b", - "int32x2_t v", - "const int lane" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "int64_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.4H" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.4H" } }, "Architectures": [ @@ -66769,35 +261449,26 @@ ], "instructions": [ [ - "SQDMLSL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsls_laneq_s32", + "name": "vpminnm_f32", "arguments": [ - "int64_t a", - "int32_t b", - "int32x4_t v", - "const int lane" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int64_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2S" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ @@ -66805,30 +261476,26 @@ ], "instructions": [ [ - "SQDMLSL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmlsls_s32", + "name": "vpminnmq_f16", "arguments": [ - "int64_t a", - "int32_t b", - "int32_t c" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int64_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8H" }, "b": { - "register": "Sn" - }, - "c": { - "register": "Sm" + "register": "Vm.8H" } }, "Architectures": [ @@ -66836,99 +261503,76 @@ ], "instructions": [ [ - "SQDMLSL" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_lane_s16", + "name": "vpminnmq_f32", "arguments": [ - "int16x4_t a", - "int16x4_t v", - "const int lane" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4S" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_lane_s32", + "name": "vpminnmq_f64", "arguments": [ - "int32x2_t a", - "int32x2_t v", - "const int lane" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.2D" }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_laneq_s16", + "name": "vpminnmqd_f64", "arguments": [ - "int16x4_t a", - "int16x8_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.2D" } }, "Architectures": [ @@ -66936,31 +261580,22 @@ ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_laneq_s32", + "name": "vpminnms_f32", "arguments": [ - "int32x2_t a", - "int32x4_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" } }, "Architectures": [ @@ -66968,147 +261603,134 @@ ], "instructions": [ [ - "SQDMULH" + "FMINNMP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_n_s16", + "name": "vpminq_f16", "arguments": [ - "int16x4_t a", - "int16_t b" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, "b": { - "register": "Vm.H[0]" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_n_s32", + "name": "vpminq_f32", "arguments": [ - "int32x2_t a", - "int32_t b" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, "b": { - "register": "Vm.S[0]" + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_s16", + "name": "vpminq_f64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2D" }, "b": { - "register": "Vm.4H" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulh_s32", + "name": "vpminq_s16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8H" }, "b": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhh_lane_s16", + "name": "vpminq_s32", "arguments": [ - "int16_t a", - "int16x4_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4S" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -67116,31 +261738,26 @@ ], "instructions": [ [ - "SQDMULH" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhh_laneq_s16", + "name": "vpminq_s8", "arguments": [ - "int16_t a", - "int16x8_t v", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.16B" }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -67148,26 +261765,26 @@ ], "instructions": [ [ - "SQDMULH" + "SMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhh_s16", + "name": "vpminq_u16", "arguments": [ - "int16_t a", - "int16_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8H" }, "b": { - "register": "Hm" + "register": "Vm.8H" } }, "Architectures": [ @@ -67175,99 +261792,76 @@ ], "instructions": [ [ - "SQDMULH" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_lane_s16", + "name": "vpminq_u32", "arguments": [ - "int16x8_t a", - "int16x4_t v", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4S" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_lane_s32", + "name": "vpminq_u8", "arguments": [ - "int32x4_t a", - "int32x2_t v", - "const int lane" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.16B" }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "UMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_laneq_s16", + "name": "vpminqd_f64", "arguments": [ - "int16x8_t a", - "int16x8_t v", - "const int lane" + "float64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.2D" } }, "Architectures": [ @@ -67275,31 +261869,22 @@ ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_laneq_s32", + "name": "vpmins_f32", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.2S" } }, "Architectures": [ @@ -67307,26 +261892,22 @@ ], "instructions": [ [ - "SQDMULH" + "FMINP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_n_s16", + "name": "vqabs_s16", "arguments": [ - "int16x8_t a", - "int16_t b" + "int16x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.H[0]" + "register": "Vn.4H" } }, "Architectures": [ @@ -67336,26 +261917,22 @@ ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_n_s32", + "name": "vqabs_s32", "arguments": [ - "int32x4_t a", - "int32_t b" + "int32x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.S[0]" + "register": "Vn.2S" } }, "Architectures": [ @@ -67365,55 +261942,45 @@ ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_s16", + "name": "vqabs_s64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int64x1_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhq_s32", + "name": "vqabs_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int8x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8B" } }, "Architectures": [ @@ -67423,31 +261990,22 @@ ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhs_lane_s32", + "name": "vqabsb_s8", "arguments": [ - "int32_t a", - "int32x2_t v", - "const int lane" + "int8_t a" ], "return_type": { - "value": "int32_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Bn" } }, "Architectures": [ @@ -67455,31 +262013,22 @@ ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhs_laneq_s32", + "name": "vqabsd_s64", "arguments": [ - "int32_t a", - "int32x4_t v", - "const int lane" + "int64_t a" ], "return_type": { - "value": "int32_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Dn" } }, "Architectures": [ @@ -67487,26 +262036,22 @@ ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulhs_s32", + "name": "vqabsh_s16", "arguments": [ - "int32_t a", - "int32_t b" + "int16_t a" ], "return_type": { - "value": "int32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Hn" } }, "Architectures": [ @@ -67514,95 +262059,72 @@ ], "instructions": [ [ - "SQDMULH" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_lane_s16", + "name": "vqabsq_s16", "arguments": [ - "int16x8_t a", - "int16x4_t v", - "const int lane" + "int16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_lane_s32", + "name": "vqabsq_s32", "arguments": [ - "int32x4_t a", - "int32x2_t v", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_laneq_s16", + "name": "vqabsq_s64", "arguments": [ - "int16x8_t a", - "int16x8_t v", - "const int lane" + "int64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "register": "Vn.2D" } }, "Architectures": [ @@ -67610,58 +262132,47 @@ ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_laneq_s32", + "name": "vqabsq_s8", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "int8x16_t a" ], "return_type": { - "value": "int64x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_n_s16", + "name": "vqabss_s32", "arguments": [ - "int16x8_t a", - "int16_t b" + "int32_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.H[0]" + "register": "Sn" } }, "Architectures": [ @@ -67669,112 +262180,113 @@ ], "instructions": [ [ - "SQDMULL2" + "SQABS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_n_s32", + "name": "vqadd_s16", "arguments": [ - "int32x4_t a", - "int32_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" }, "b": { - "register": "Vm.S[0]" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_s16", + "name": "vqadd_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_high_s32", + "name": "vqadd_s64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Dn" }, "b": { - "register": "Vm.4S" + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL2" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_lane_s16", + "name": "vqadd_s8", "arguments": [ - "int16x4_t a", - "int16x4_t v", - "const int lane" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.8B" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Vm.8B" } }, "Architectures": [ @@ -67784,31 +262296,26 @@ ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_lane_s32", + "name": "vqadd_u16", "arguments": [ - "int32x2_t a", - "int32x2_t v", - "const int lane" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.4H" }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Vm.4H" } }, "Architectures": [ @@ -67818,90 +262325,84 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_laneq_s16", + "name": "vqadd_u32", "arguments": [ - "int16x4_t a", - "int16x8_t v", - "const int lane" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.2S" }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_laneq_s32", + "name": "vqadd_u64", "arguments": [ - "int32x2_t a", - "int32x4_t v", - "const int lane" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Dn" }, - "v": { - "register": "Vm.4S" + "b": { + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_n_s16", + "name": "vqadd_u8", "arguments": [ - "int16x4_t a", - "int16_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8B" }, "b": { - "register": "Vm.H[0]" + "register": "Vm.8B" } }, "Architectures": [ @@ -67911,118 +262412,107 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_n_s32", + "name": "vqaddb_s8", "arguments": [ - "int32x2_t a", - "int32_t b" + "int8_t a", + "int8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Bn" }, "b": { - "register": "Vm.S[0]" + "register": "Bm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_s16", + "name": "vqaddb_u8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint8_t a", + "uint8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Bn" }, "b": { - "register": "Vm.4H" + "register": "Bm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmull_s32", + "name": "vqaddd_s64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmullh_lane_s16", + "name": "vqaddd_u64", "arguments": [ - "int16_t a", - "int16x4_t v", - "const int lane" + "uint64_t a", + "uint64_t b" ], "return_type": { - "value": "int32_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Dn" }, - "v": { - "register": "Vm.4H" + "b": { + "register": "Dm" } }, "Architectures": [ @@ -68030,31 +262520,26 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmullh_laneq_s16", + "name": "vqaddh_s16", "arguments": [ "int16_t a", - "int16x8_t v", - "const int lane" + "int16_t b" ], "return_type": { - "value": "int32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { "register": "Hn" }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "b": { + "register": "Hm" } }, "Architectures": [ @@ -68062,19 +262547,19 @@ ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmullh_s16", + "name": "vqaddh_u16", "arguments": [ - "int16_t a", - "int16_t b" + "uint16_t a", + "uint16_t b" ], "return_type": { - "value": "int32_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { @@ -68089,252 +262574,258 @@ ], "instructions": [ [ - "SQDMULL" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulls_lane_s32", + "name": "vqaddq_s16", "arguments": [ - "int32_t a", - "int32x2_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int64_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.8H" }, - "v": { - "register": "Vm.2S" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulls_laneq_s32", + "name": "vqaddq_s32", "arguments": [ - "int32_t a", - "int32x4_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int64_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4S" }, - "v": { + "b": { "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqdmulls_s32", + "name": "vqaddq_s64", "arguments": [ - "int32_t a", - "int32_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int64_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vn.2D" }, "b": { - "register": "Sm" + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQDMULL" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_s16", + "name": "vqaddq_s8", "arguments": [ - "int8x8_t r", - "int16x8_t a" + "int8x16_t a", + "int8x16_t b" ], "return_type": { "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTN2" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_s32", + "name": "vqaddq_u16", "arguments": [ - "int16x4_t r", - "int32x4_t a" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8H" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTN2" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_s64", + "name": "vqaddq_u32", "arguments": [ - "int32x2_t r", - "int64x2_t a" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTN2" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_u16", + "name": "vqaddq_u64", "arguments": [ - "uint8x8_t r", - "uint16x8_t a" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQXTN2" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_u32", + "name": "vqaddq_u8", "arguments": [ - "uint16x4_t r", - "uint32x4_t a" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQXTN2" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_high_u64", + "name": "vqadds_s32", "arguments": [ - "uint32x2_t r", - "uint64x2_t a" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Sn" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Sm" } }, "Architectures": [ @@ -68342,172 +262833,232 @@ ], "instructions": [ [ - "UQXTN2" + "SQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_s16", + "name": "vqadds_u32", "arguments": [ - "int16x8_t a" + "uint32_t a", + "uint32_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQXTN" + "UQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_s32", + "name": "vqdmlal_high_lane_s16", "arguments": [ - "int32x4_t a" + "int32x4_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_s64", + "name": "vqdmlal_high_lane_s32", "arguments": [ - "int64x2_t a" + "int64x2_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_u16", + "name": "vqdmlal_high_laneq_s16", "arguments": [ - "uint16x8_t a" + "int32x4_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4S" + }, + "b": { "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_u32", + "name": "vqdmlal_high_laneq_s32", "arguments": [ - "uint32x4_t a" + "int64x2_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2D" + }, + "b": { "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovn_u64", + "name": "vqdmlal_high_n_s16", "arguments": [ - "uint64x2_t a" + "int32x4_t a", + "int16x8_t b", + "int16_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovnd_s64", + "name": "vqdmlal_high_n_s32", "arguments": [ - "int64_t a" + "int64x2_t a", + "int32x4_t b", + "int32_t c" ], "return_type": { - "value": "int32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -68515,22 +263066,30 @@ ], "instructions": [ [ - "SQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovnd_u64", + "name": "vqdmlal_high_s16", "arguments": [ - "uint64_t a" + "int32x4_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "uint32_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ @@ -68538,22 +263097,30 @@ ], "instructions": [ [ - "UQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovnh_s16", + "name": "vqdmlal_high_s32", "arguments": [ - "int16_t a" + "int64x2_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "int8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ @@ -68561,68 +263128,111 @@ ], "instructions": [ [ - "SQXTN" + "SQDMLAL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovnh_u16", + "name": "vqdmlal_lane_s16", "arguments": [ - "uint16_t a" + "int32x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQXTN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovns_s32", + "name": "vqdmlal_lane_s32", "arguments": [ - "int32_t a" + "int64x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovns_u32", + "name": "vqdmlal_laneq_s16", "arguments": [ - "uint32_t a" + "int32x4_t a", + "int16x4_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -68630,26 +263240,35 @@ ], "instructions": [ [ - "UQXTN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_high_s16", + "name": "vqdmlal_laneq_s32", "arguments": [ - "uint8x8_t r", - "int16x8_t a" + "int64x2_t a", + "int32x2_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2D" }, - "r": { - "register": "Vd.8B" + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -68657,76 +263276,96 @@ ], "instructions": [ [ - "SQXTUN2" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_high_s32", + "name": "vqdmlal_n_s16", "arguments": [ - "uint16x4_t r", - "int32x4_t a" + "int32x4_t a", + "int16x4_t b", + "int16_t c" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "r": { - "register": "Vd.4H" + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTUN2" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_high_s64", + "name": "vqdmlal_n_s32", "arguments": [ - "uint32x2_t r", - "int64x2_t a" + "int64x2_t a", + "int32x2_t b", + "int32_t c" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2D" }, - "r": { - "register": "Vd.2S" + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQXTUN2" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_s16", + "name": "vqdmlal_s16", "arguments": [ - "int16x8_t a" + "int32x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ @@ -68736,22 +263375,30 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_s32", + "name": "vqdmlal_s32", "arguments": [ - "int32x4_t a" + "int64x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ @@ -68761,47 +263408,71 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovun_s64", + "name": "vqdmlalh_lane_s16", "arguments": [ - "int64x2_t a" + "int32_t a", + "int16_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Sd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovund_s64", + "name": "vqdmlalh_laneq_s16", "arguments": [ - "int64_t a" + "int32_t a", + "int16_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint32_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Sd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -68809,22 +263480,30 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovunh_s16", + "name": "vqdmlalh_s16", "arguments": [ - "int16_t a" + "int32_t a", + "int16_t b", + "int16_t c" ], "return_type": { - "value": "uint8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { + "register": "Sd" + }, + "b": { "register": "Hn" + }, + "c": { + "register": "Hm" } }, "Architectures": [ @@ -68832,22 +263511,35 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqmovuns_s32", + "name": "vqdmlals_lane_s32", "arguments": [ - "int32_t a" + "int64_t a", + "int32_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { + "register": "Dd" + }, + "b": { "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -68855,72 +263547,102 @@ ], "instructions": [ [ - "SQXTUN" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqneg_s16", + "name": "vqdmlals_laneq_s32", "arguments": [ - "int16x4_t a" + "int64_t a", + "int32_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dd" + }, + "b": { + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqneg_s32", + "name": "vqdmlals_s32", "arguments": [ - "int32x2_t a" + "int64_t a", + "int32_t b", + "int32_t c" ], "return_type": { - "value": "int32x2_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dd" + }, + "b": { + "register": "Sn" + }, + "c": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLAL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqneg_s64", + "name": "vqdmlsl_high_lane_s16", "arguments": [ - "int64x1_t a" + "int32x4_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -68928,47 +263650,71 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqneg_s8", + "name": "vqdmlsl_high_lane_s32", "arguments": [ - "int8x8_t a" + "int64x2_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegb_s8", + "name": "vqdmlsl_high_laneq_s16", "arguments": [ - "int8_t a" + "int32x4_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -68976,22 +263722,35 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegd_s64", + "name": "vqdmlsl_high_laneq_s32", "arguments": [ - "int64_t a" + "int64x2_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -68999,22 +263758,30 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegh_s16", + "name": "vqdmlsl_high_n_s16", "arguments": [ - "int16_t a" + "int32x4_t a", + "int16x8_t b", + "int16_t c" ], "return_type": { - "value": "int16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -69022,72 +263789,92 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegq_s16", + "name": "vqdmlsl_high_n_s32", "arguments": [ - "int16x8_t a" + "int64x2_t a", + "int32x4_t b", + "int32_t c" ], "return_type": { - "value": "int16x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegq_s32", + "name": "vqdmlsl_high_s16", "arguments": [ - "int32x4_t a" + "int32x4_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegq_s64", + "name": "vqdmlsl_high_s32", "arguments": [ - "int64x2_t a" + "int64x2_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ @@ -69095,22 +263882,35 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegq_s8", + "name": "vqdmlsl_lane_s16", "arguments": [ - "int8x16_t a" + "int32x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -69120,58 +263920,73 @@ ], "instructions": [ [ - "SQNEG" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqnegs_s32", + "name": "vqdmlsl_lane_s32", "arguments": [ - "int32_t a" + "int64x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQNEG" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_lane_s16", + "name": "vqdmlsl_laneq_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", "int16x4_t b", - "int16x4_t v", + "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.4S" }, "b": { "register": "Vn.4H" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "v": { - "register": "Vm.4H" + "register": "Vm.8H" } }, "Architectures": [ @@ -69179,35 +263994,35 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_lane_s32", + "name": "vqdmlsl_laneq_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", "int32x2_t b", - "int32x2_t v", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.2D" }, "b": { "register": "Vn.2S" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "v": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -69215,96 +264030,90 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_laneq_s16", + "name": "vqdmlsl_n_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", "int16x4_t b", - "int16x8_t v", - "const int lane" + "int16_t c" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.4S" }, "b": { "register": "Vn.4H" }, - "lane": { - "minimum": 0, - "maximum": 7 - }, - "v": { - "register": "Vm.8H" + "c": { + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_laneq_s32", + "name": "vqdmlsl_n_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", "int32x2_t b", - "int32x4_t v", - "const int lane" + "int32_t c" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.2D" }, "b": { "register": "Vn.2S" }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "c": { + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_s16", + "name": "vqdmlsl_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", "int16x4_t b", "int16x4_t c" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.4S" }, "b": { "register": "Vn.4H" @@ -69314,28 +264123,30 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlah_s32", + "name": "vqdmlsl_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", "int32x2_t b", "int32x2_t c" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.2D" }, "b": { "register": "Vn.2S" @@ -69345,29 +264156,31 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahh_lane_s16", + "name": "vqdmlslh_lane_s16", "arguments": [ - "int16_t a", + "int32_t a", "int16_t b", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Sd" }, "b": { "register": "Hn" @@ -69385,25 +264198,25 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahh_laneq_s16", + "name": "vqdmlslh_laneq_s16", "arguments": [ - "int16_t a", + "int32_t a", "int16_t b", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Sd" }, "b": { "register": "Hn" @@ -69421,24 +264234,24 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahh_s16", + "name": "vqdmlslh_s16", "arguments": [ - "int16_t a", + "int32_t a", "int16_t b", "int16_t c" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Sd" }, "b": { "register": "Hn" @@ -69452,28 +264265,127 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMLSL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_lane_s16", + "name": "vqdmlsls_lane_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x4_t v", + "int64_t a", + "int32_t b", + "int32x2_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dd" }, "b": { - "register": "Vn.8H" + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmlsls_laneq_s32", + "arguments": [ + "int64_t a", + "int32_t b", + "int32x4_t v", + "const int lane" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dd" + }, + "b": { + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmlsls_s32", + "arguments": [ + "int64_t a", + "int32_t b", + "int32_t c" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dd" + }, + "b": { + "register": "Sn" + }, + "c": { + "register": "Sm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulh_lane_s16", + "arguments": [ + "int16x4_t a", + "int16x4_t v", + "const int lane" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" }, "lane": { "minimum": 0, @@ -69484,32 +264396,30 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_lane_s32", + "name": "vqdmulh_lane_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", + "int32x2_t a", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" + "register": "Vn.2S" }, "lane": { "minimum": 0, @@ -69520,31 +264430,29 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_laneq_s16", + "name": "vqdmulh_laneq_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", + "int16x4_t a", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "lane": { @@ -69560,27 +264468,23 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_laneq_s32", + "name": "vqdmulh_laneq_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", + "int32x2_t a", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "lane": { @@ -69596,97 +264500,147 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_s16", + "name": "vqdmulh_n_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "int16x4_t a", + "int16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4H" }, "b": { - "register": "Vn.8H" - }, - "c": { - "register": "Vm.8H" + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahq_s32", + "name": "vqdmulh_n_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "int32x2_t a", + "int32_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2S" }, "b": { - "register": "Vn.4S" + "register": "Vm.S[0]" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulh_s16", + "arguments": [ + "int16x4_t a", + "int16x4_t b" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" }, - "c": { - "register": "Vm.4S" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahs_lane_s32", + "name": "vqdmulh_s32", "arguments": [ - "int32_t a", - "int32_t b", - "int32x2_t v", - "const int lane" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int32_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.2S" }, "b": { - "register": "Sn" + "register": "Vm.2S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulhh_lane_s16", + "arguments": [ + "int16_t a", + "int16x4_t v", + "const int lane" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "v": { - "register": "Vm.2S" + "register": "Vm.4H" } }, "Architectures": [ @@ -69694,35 +264648,31 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahs_laneq_s32", + "name": "vqdmulhh_laneq_s16", "arguments": [ - "int32_t a", - "int32_t b", - "int32x4_t v", + "int16_t a", + "int16x8_t v", "const int lane" ], "return_type": { - "value": "int32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" - }, - "b": { - "register": "Sn" + "register": "Hn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -69730,30 +264680,26 @@ ], "instructions": [ [ - "SQRDMLAH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlahs_s32", + "name": "vqdmulhh_s16", "arguments": [ - "int32_t a", - "int32_t b", - "int32_t c" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "int32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Hn" }, "b": { - "register": "Sn" - }, - "c": { - "register": "Sm" + "register": "Hm" } }, "Architectures": [ @@ -69761,28 +264707,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_lane_s16", + "name": "vqdmulhq_lane_s16", "arguments": [ - "int16x4_t a", - "int16x4_t b", + "int16x8_t a", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "lane": { "minimum": 0, @@ -69793,32 +264735,30 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_lane_s32", + "name": "vqdmulhq_lane_s32", "arguments": [ - "int32x2_t a", - "int32x2_t b", + "int32x4_t a", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.4S" }, "lane": { "minimum": 0, @@ -69829,32 +264769,30 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_laneq_s16", + "name": "vqdmulhq_laneq_s16", "arguments": [ - "int16x4_t a", - "int16x4_t b", + "int16x8_t a", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "lane": { "minimum": 0, @@ -69869,28 +264807,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_laneq_s32", + "name": "vqdmulhq_laneq_s32", "arguments": [ - "int32x2_t a", - "int32x2_t b", + "int32x4_t a", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.4S" }, "lane": { "minimum": 0, @@ -69905,97 +264839,147 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_s16", + "name": "vqdmulhq_n_s16", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "int16x4_t c" + "int16x8_t a", + "int16_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" }, "b": { - "register": "Vn.4H" - }, - "c": { - "register": "Vm.4H" + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlsh_s32", + "name": "vqdmulhq_n_s32", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "int32x2_t c" + "int32x4_t a", + "int32_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" }, "b": { - "register": "Vn.2S" + "register": "Vm.S[0]" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulhq_s16", + "arguments": [ + "int16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" }, - "c": { - "register": "Vm.2S" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshh_lane_s16", + "name": "vqdmulhq_s32", "arguments": [ - "int16_t a", - "int16_t b", - "int16x4_t v", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Vn.4S" }, "b": { - "register": "Hn" + "register": "Vm.4S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqdmulhs_lane_s32", + "arguments": [ + "int32_t a", + "int32x2_t v", + "const int lane" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "v": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ @@ -70003,35 +264987,31 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshh_laneq_s16", + "name": "vqdmulhs_laneq_s32", "arguments": [ - "int16_t a", - "int16_t b", - "int16x8_t v", + "int32_t a", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" - }, - "b": { - "register": "Hn" + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "v": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -70039,30 +265019,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshh_s16", + "name": "vqdmulhs_s32", "arguments": [ - "int16_t a", - "int16_t b", - "int16_t c" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Sn" }, "b": { - "register": "Hn" - }, - "c": { - "register": "Hm" + "register": "Sm" } }, "Architectures": [ @@ -70070,27 +265046,23 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_lane_s16", + "name": "vqdmull_high_lane_s16", "arguments": [ "int16x8_t a", - "int16x8_t b", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" }, "lane": { @@ -70106,27 +265078,23 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_lane_s32", + "name": "vqdmull_high_lane_s32", "arguments": [ "int32x4_t a", - "int32x4_t b", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" }, "lane": { @@ -70142,28 +265110,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_laneq_s16", + "name": "vqdmull_high_laneq_s16", "arguments": [ "int16x8_t a", - "int16x8_t b", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.8H" }, "lane": { "minimum": 0, @@ -70178,28 +265142,24 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_laneq_s32", + "name": "vqdmull_high_laneq_s32", "arguments": [ "int32x4_t a", - "int32x4_t b", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.4S" }, "lane": { "minimum": 0, @@ -70214,30 +265174,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_s16", + "name": "vqdmull_high_n_s16", "arguments": [ "int16x8_t a", - "int16x8_t b", - "int16x8_t c" + "int16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" }, - "c": { - "register": "Vm.8H" + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -70245,66 +265201,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshq_s32", + "name": "vqdmull_high_n_s32", "arguments": [ "int32x4_t a", - "int32x4_t b", - "int32x4_t c" + "int32_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" }, - "c": { - "register": "Vm.4S" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "SQRDMLSH" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vqrdmlshs_lane_s32", - "arguments": [ - "int32_t a", - "int32_t b", - "int32x2_t v", - "const int lane" - ], - "return_type": { - "value": "int32_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Sd" - }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vm.S[0]" } }, "Architectures": [ @@ -70312,35 +265228,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshs_laneq_s32", + "name": "vqdmull_high_s16", "arguments": [ - "int32_t a", - "int32_t b", - "int32x4_t v", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int32_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.8H" }, "b": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -70348,30 +265255,26 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmlshs_s32", + "name": "vqdmull_high_s32", "arguments": [ - "int32_t a", - "int32_t b", - "int32_t c" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int32_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.4S" }, "b": { - "register": "Sn" - }, - "c": { - "register": "Sm" + "register": "Vm.4S" } }, "Architectures": [ @@ -70379,20 +265282,20 @@ ], "instructions": [ [ - "SQRDMLSH" + "SQDMULL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_lane_s16", + "name": "vqdmull_lane_s16", "arguments": [ "int16x4_t a", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -70413,20 +265316,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_lane_s32", + "name": "vqdmull_lane_s32", "arguments": [ "int32x2_t a", "int32x2_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -70447,20 +265350,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_laneq_s16", + "name": "vqdmull_laneq_s16", "arguments": [ "int16x4_t a", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -70479,20 +265382,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_laneq_s32", + "name": "vqdmull_laneq_s32", "arguments": [ "int32x2_t a", "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -70511,19 +265414,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_n_s16", + "name": "vqdmull_n_s16", "arguments": [ "int16x4_t a", "int16_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -70540,19 +265443,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_n_s32", + "name": "vqdmull_n_s32", "arguments": [ "int32x2_t a", "int32_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -70569,19 +265472,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_s16", + "name": "vqdmull_s16", "arguments": [ "int16x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -70598,19 +265501,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulh_s32", + "name": "vqdmull_s32", "arguments": [ "int32x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -70627,20 +265530,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhh_lane_s16", + "name": "vqdmullh_lane_s16", "arguments": [ "int16_t a", "int16x4_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { @@ -70659,20 +265562,20 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhh_laneq_s16", + "name": "vqdmullh_laneq_s16", "arguments": [ "int16_t a", "int16x8_t v", "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { @@ -70691,19 +265594,19 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhh_s16", + "name": "vqdmullh_s16", "arguments": [ "int16_t a", "int16_t b" ], "return_type": { - "value": "int16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { @@ -70718,99 +265621,117 @@ ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_lane_s16", + "name": "vqdmulls_lane_s32", "arguments": [ - "int16x8_t a", - "int16x4_t v", + "int32_t a", + "int32x2_t v", "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "v": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_lane_s32", + "name": "vqdmulls_laneq_s32", "arguments": [ - "int32x4_t a", - "int32x2_t v", + "int32_t a", + "int32x4_t v", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Sn" }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "v": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQDMULL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_laneq_s16", + "name": "vqdmulls_s32", "arguments": [ - "int16x8_t a", - "int16x8_t v", - "const int lane" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Sn" }, - "lane": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Sm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqmovn_high_s16", + "arguments": [ + "int8x8_t r", + "int16x8_t a" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" }, - "v": { - "register": "Vm.8H" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -70818,31 +265739,53 @@ ], "instructions": [ [ - "SQRDMULH" + "SQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_laneq_s32", + "name": "vqmovn_high_s32", "arguments": [ - "int32x4_t a", - "int32x4_t v", - "const int lane" + "int16x4_t r", + "int32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTN2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqmovn_high_s64", + "arguments": [ + "int32x2_t r", + "int64x2_t a" + ], + "return_type": { + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" }, - "v": { - "register": "Vm.4S" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -70850,113 +265793,103 @@ ], "instructions": [ [ - "SQRDMULH" + "SQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_n_s16", + "name": "vqmovn_high_u16", "arguments": [ - "int16x8_t a", - "int16_t b" + "uint8x8_t r", + "uint16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, - "b": { - "register": "Vm.H[0]" + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "UQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_n_s32", + "name": "vqmovn_high_u32", "arguments": [ - "int32x4_t a", - "int32_t b" + "uint16x4_t r", + "uint32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, - "b": { - "register": "Vm.S[0]" + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "UQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_s16", + "name": "vqmovn_high_u64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint32x2_t r", + "uint64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, - "b": { - "register": "Vm.8H" + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "UQXTN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhq_s32", + "name": "vqmovn_s16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.8H" } }, "Architectures": [ @@ -70966,117 +265899,97 @@ ], "instructions": [ [ - "SQRDMULH" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhs_lane_s32", + "name": "vqmovn_s32", "arguments": [ - "int32_t a", - "int32x2_t v", - "const int lane" + "int32x4_t a" ], "return_type": { - "value": "int32_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vm.2S" + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhs_laneq_s32", + "name": "vqmovn_s64", "arguments": [ - "int32_t a", - "int32x4_t v", - "const int lane" + "int64x2_t a" ], "return_type": { - "value": "int32_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "v": { - "register": "Vm.4S" + "register": "Vn.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrdmulhs_s32", + "name": "vqmovn_u16", "arguments": [ - "int32_t a", - "int32_t b" + "uint16x8_t a" ], "return_type": { - "value": "int32_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRDMULH" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_s16", + "name": "vqmovn_u32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint32x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vn.4S" } }, "Architectures": [ @@ -71086,26 +265999,22 @@ ], "instructions": [ [ - "SQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_s32", + "name": "vqmovn_u64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint64x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vn.2D" } }, "Architectures": [ @@ -71115,200 +266024,164 @@ ], "instructions": [ [ - "SQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_s64", + "name": "vqmovnd_s64", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int64_t a" ], "return_type": { - "value": "int64x1_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { "register": "Dn" - }, - "b": { - "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHL" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_s8", + "name": "vqmovnd_u64", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint64_t a" ], "return_type": { - "value": "int8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_u16", + "name": "vqmovnh_s16", "arguments": [ - "uint16x4_t a", - "int16x4_t b" + "int16_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Hn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_u32", + "name": "vqmovnh_u16", "arguments": [ - "uint32x2_t a", - "int32x2_t b" + "uint16_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Hn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_u64", + "name": "vqmovns_s32", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "int32_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Sn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshl_u8", + "name": "vqmovns_u32", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "uint32_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Sn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "UQXTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlb_s8", + "name": "vqmovun_high_s16", "arguments": [ - "int8_t a", - "int8_t b" + "uint8x8_t r", + "int16x8_t a" ], "return_type": { - "value": "int8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.8H" }, - "b": { - "register": "Bm" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -71316,26 +266189,26 @@ ], "instructions": [ [ - "SQRSHL" + "SQXTUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlb_u8", + "name": "vqmovun_high_s32", "arguments": [ - "uint8_t a", - "int8_t b" + "uint16x4_t r", + "int32x4_t a" ], "return_type": { - "value": "uint8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.4S" }, - "b": { - "register": "Bm" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -71343,26 +266216,26 @@ ], "instructions": [ [ - "UQRSHL" + "SQXTUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshld_s64", + "name": "vqmovun_high_s64", "arguments": [ - "int64_t a", - "int64_t b" + "uint32x2_t r", + "int64x2_t a" ], "return_type": { - "value": "int64_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2D" }, - "b": { - "register": "Dm" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -71370,194 +266243,166 @@ ], "instructions": [ [ - "SQRSHL" + "SQXTUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshld_u64", + "name": "vqmovun_s16", "arguments": [ - "uint64_t a", - "int64_t b" + "int16x8_t a" ], "return_type": { - "value": "uint64_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlh_s16", + "name": "vqmovun_s32", "arguments": [ - "int16_t a", - "int16_t b" + "int32x4_t a" ], "return_type": { - "value": "int16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "b": { - "register": "Hm" + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlh_u16", + "name": "vqmovun_s64", "arguments": [ - "uint16_t a", - "int16_t b" + "int64x2_t a" ], "return_type": { - "value": "uint16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "b": { - "register": "Hm" + "register": "Vn.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_s16", + "name": "vqmovund_s64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int64_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_s32", + "name": "vqmovunh_s16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Hn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_s64", + "name": "vqmovuns_s32", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int32_t a" ], "return_type": { - "value": "int64x2_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Sn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHL" + "SQXTUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_s8", + "name": "vqneg_s16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int16x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vn.4H" } }, "Architectures": [ @@ -71567,26 +266412,22 @@ ], "instructions": [ [ - "SQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_u16", + "name": "vqneg_s32", "arguments": [ - "uint16x8_t a", - "int16x8_t b" + "int32x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.2S" } }, "Architectures": [ @@ -71596,55 +266437,45 @@ ], "instructions": [ [ - "UQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_u32", + "name": "vqneg_s64", "arguments": [ - "uint32x4_t a", - "int32x4_t b" + "int64x1_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_u64", + "name": "vqneg_s8", "arguments": [ - "uint64x2_t a", - "int64x2_t b" + "int8x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.8B" } }, "Architectures": [ @@ -71654,55 +266485,45 @@ ], "instructions": [ [ - "UQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshlq_u8", + "name": "vqnegb_s8", "arguments": [ - "uint8x16_t a", - "int8x16_t b" + "int8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Bn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshls_s32", + "name": "vqnegd_s64", "arguments": [ - "int32_t a", - "int32_t b" + "int64_t a" ], "return_type": { - "value": "int32_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Dn" } }, "Architectures": [ @@ -71710,26 +266531,22 @@ ], "instructions": [ [ - "SQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshls_u32", + "name": "vqnegh_s16", "arguments": [ - "uint32_t a", - "int32_t b" + "int16_t a" ], "return_type": { - "value": "uint32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Hn" } }, "Architectures": [ @@ -71737,95 +266554,72 @@ ], "instructions": [ [ - "UQRSHL" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_s16", + "name": "vqnegq_s16", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "const int n" + "int16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 - }, - "r": { - "register": "Vd.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_s32", + "name": "vqnegq_s32", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "const int n" + "int32x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 - }, - "r": { - "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_s64", + "name": "vqnegq_s64", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "const int n" + "int64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 - }, - "r": { - "register": "Vd.2S" } }, "Architectures": [ @@ -71833,63 +266627,47 @@ ], "instructions": [ [ - "SQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_u16", + "name": "vqnegq_s8", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "const int n" + "int8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 - }, - "r": { - "register": "Vd.8B" + "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_u32", + "name": "vqnegs_s32", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "const int n" + "int32_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 - }, - "r": { - "register": "Vd.4H" + "register": "Sn" } }, "Architectures": [ @@ -71897,31 +266675,35 @@ ], "instructions": [ [ - "UQRSHRN2" + "SQNEG" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_high_n_u64", + "name": "vqrdmlah_lane_s16", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.4H" }, - "r": { - "register": "Vd.2S" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -71929,207 +266711,241 @@ ], "instructions": [ [ - "UQRSHRN2" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_s16", + "name": "vqrdmlah_lane_s32", "arguments": [ - "int16x8_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_s32", + "name": "vqrdmlah_laneq_s16", "arguments": [ - "int32x4_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x8_t v", + "const int lane" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_s64", + "name": "vqrdmlah_laneq_s32", "arguments": [ - "int64x2_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x4_t v", + "const int lane" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_u16", + "name": "vqrdmlah_s16", "arguments": [ - "uint16x8_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x4_t c" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_u32", + "name": "vqrdmlah_s32", "arguments": [ - "uint32x4_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x2_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.2S" + }, + "c": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrn_n_u64", + "name": "vqrdmlahh_lane_s16", "arguments": [ - "uint64x2_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hd" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrnd_n_s64", + "name": "vqrdmlahh_laneq_s16", "arguments": [ - "int64_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Hd" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -72137,27 +266953,30 @@ ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrnd_n_u64", + "name": "vqrdmlahh_s16", "arguments": [ - "uint64_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16_t c" ], "return_type": { - "value": "uint32_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Hd" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Hn" + }, + "c": { + "register": "Hm" } }, "Architectures": [ @@ -72165,27 +266984,35 @@ ], "instructions": [ [ - "UQRSHRN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrnh_n_s16", + "name": "vqrdmlahq_lane_s16", "arguments": [ - "int16_t a", - "const int n" + "int16x8_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.8H" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -72193,27 +267020,35 @@ ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrnh_n_u16", + "name": "vqrdmlahq_lane_s32", "arguments": [ - "uint16_t a", - "const int n" + "int32x4_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Vn.4S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -72221,27 +267056,35 @@ ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrns_n_s32", + "name": "vqrdmlahq_laneq_s16", "arguments": [ - "int32_t a", - "const int n" + "int16x8_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -72249,27 +267092,35 @@ ], "instructions": [ [ - "SQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrns_n_u32", + "name": "vqrdmlahq_laneq_s32", "arguments": [ - "uint32_t a", - "const int n" + "int32x4_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -72277,31 +267128,30 @@ ], "instructions": [ [ - "UQRSHRN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_high_n_s16", + "name": "vqrdmlahq_s16", "arguments": [ - "uint8x8_t r", "int16x8_t a", - "const int n" + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.8H" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.8B" + "c": { + "register": "Vm.8H" } }, "Architectures": [ @@ -72309,31 +267159,30 @@ ], "instructions": [ [ - "SQRSHRUN2" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_high_n_s32", + "name": "vqrdmlahq_s32", "arguments": [ - "uint16x4_t r", "int32x4_t a", - "const int n" + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.4S" }, - "r": { - "register": "Vd.4H" + "c": { + "register": "Vm.4S" } }, "Architectures": [ @@ -72341,31 +267190,35 @@ ], "instructions": [ [ - "SQRSHRUN2" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_high_n_s64", + "name": "vqrdmlahs_lane_s32", "arguments": [ - "uint32x2_t r", - "int64x2_t a", - "const int n" + "int32_t a", + "int32_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Sd" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Sn" }, - "r": { - "register": "Vd.2S" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -72373,117 +267226,138 @@ ], "instructions": [ [ - "SQRSHRUN2" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_n_s16", + "name": "vqrdmlahs_laneq_s32", "arguments": [ - "int16x8_t a", - "const int n" + "int32_t a", + "int32_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Sd" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLAH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_n_s32", - "arguments": [ - "int32x4_t a", - "const int n" + "name": "vqrdmlahs_s32", + "arguments": [ + "int32_t a", + "int32_t b", + "int32_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Sd" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Sn" + }, + "c": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrun_n_s64", + "name": "vqrdmlsh_lane_s16", "arguments": [ - "int64x2_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrund_n_s64", + "name": "vqrdmlsh_lane_s32", "arguments": [ - "int64_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 32 + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -72491,27 +267365,35 @@ ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshrunh_n_s16", + "name": "vqrdmlsh_laneq_s16", "arguments": [ - "int16_t a", - "const int n" + "int16x4_t a", + "int16x4_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.4H" }, - "n": { - "minimum": 1, - "maximum": 8 + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -72519,27 +267401,35 @@ ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqrshruns_n_s32", + "name": "vqrdmlsh_laneq_s32", "arguments": [ - "int32_t a", - "const int n" + "int32x2_t a", + "int32x2_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.2S" }, - "n": { - "minimum": 1, - "maximum": 16 + "b": { + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -72547,440 +267437,505 @@ ], "instructions": [ [ - "SQRSHRUN" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_s16", + "name": "vqrdmlsh_s16", "arguments": [ "int16x4_t a", - "const int n" + "int16x4_t b", + "int16x4_t c" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4H" + }, + "b": { "register": "Vn.4H" }, - "n": { - "minimum": 0, - "maximum": 15 + "c": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_s32", + "name": "vqrdmlsh_s32", "arguments": [ "int32x2_t a", - "const int n" + "int32x2_t b", + "int32x2_t c" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2S" + }, + "b": { "register": "Vn.2S" }, - "n": { - "minimum": 0, - "maximum": 31 + "c": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_s64", + "name": "vqrdmlshh_lane_s16", "arguments": [ - "int64x1_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Hd" }, - "n": { + "b": { + "register": "Hn" + }, + "lane": { "minimum": 0, - "maximum": 63 + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_s8", + "name": "vqrdmlshh_laneq_s16", "arguments": [ - "int8x8_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Hd" }, - "n": { + "b": { + "register": "Hn" + }, + "lane": { "minimum": 0, "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_u16", + "name": "vqrdmlshh_s16", "arguments": [ - "uint16x4_t a", - "const int n" + "int16_t a", + "int16_t b", + "int16_t c" ], "return_type": { - "value": "uint16x4_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Hd" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Hn" + }, + "c": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_u32", + "name": "vqrdmlshq_lane_s16", "arguments": [ - "uint32x2_t a", - "const int n" + "int16x8_t a", + "int16x8_t b", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.8H" }, - "n": { + "b": { + "register": "Vn.8H" + }, + "lane": { "minimum": 0, - "maximum": 31 + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_u64", + "name": "vqrdmlshq_lane_s32", "arguments": [ - "uint64x1_t a", - "const int n" + "int32x4_t a", + "int32x4_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" }, - "n": { + "b": { + "register": "Vn.4S" + }, + "lane": { "minimum": 0, - "maximum": 63 + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_n_u8", + "name": "vqrdmlshq_laneq_s16", "arguments": [ - "uint8x8_t a", - "const int n" + "int16x8_t a", + "int16x8_t b", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.4H" }, - "n": { + "b": { + "register": "Vn.4H" + }, + "lane": { "minimum": 0, "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_s16", + "name": "vqrdmlshq_laneq_s32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int32x4_t a", + "int32x4_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.2S" }, "b": { - "register": "Vm.4H" + "register": "Vn.2S" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_s32", + "name": "vqrdmlshq_s16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int16x8_t a", + "int16x8_t b", + "int16x8_t c" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.8H" }, "b": { - "register": "Vm.2S" + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_s64", + "name": "vqrdmlshq_s32", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int32x4_t a", + "int32x4_t b", + "int32x4_t c" ], "return_type": { - "value": "int64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" }, "b": { - "register": "Dm" + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_s8", + "name": "vqrdmlshs_lane_s32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int32_t a", + "int32_t b", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Sd" }, "b": { - "register": "Vm.8B" + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_u16", + "name": "vqrdmlshs_laneq_s32", "arguments": [ - "uint16x4_t a", - "int16x4_t b" + "int32_t a", + "int32_t b", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Sd" }, "b": { - "register": "Vm.4H" + "register": "Sn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_u32", + "name": "vqrdmlshs_s32", "arguments": [ - "uint32x2_t a", - "int32x2_t b" + "int32_t a", + "int32_t b", + "int32_t c" ], "return_type": { - "value": "uint32x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Sd" }, "b": { - "register": "Vm.2S" + "register": "Sn" + }, + "c": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMLSH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_u64", + "name": "vqrdmulh_lane_s16", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "int16x4_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" }, - "b": { - "register": "Dm" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -72990,26 +267945,31 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshl_u8", + "name": "vqrdmulh_lane_s32", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "int32x2_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2S" }, - "b": { - "register": "Vm.8B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ @@ -73019,27 +267979,31 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlb_n_s8", + "name": "vqrdmulh_laneq_s16", "arguments": [ - "int8_t a", - "const int n" + "int16x4_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "int8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.4H" }, - "n": { + "lane": { "minimum": 0, "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -73047,27 +268011,31 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlb_n_u8", + "name": "vqrdmulh_laneq_s32", "arguments": [ - "uint8_t a", - "const int n" + "int32x2_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.2S" }, - "n": { + "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ @@ -73075,136 +268043,147 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlb_s8", + "name": "vqrdmulh_n_s16", "arguments": [ - "int8_t a", - "int8_t b" + "int16x4_t a", + "int16_t b" ], "return_type": { - "value": "int8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.4H" }, "b": { - "register": "Bm" + "register": "Vm.H[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlb_u8", + "name": "vqrdmulh_n_s32", "arguments": [ - "uint8_t a", - "int8_t b" + "int32x2_t a", + "int32_t b" ], "return_type": { - "value": "uint8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.2S" }, "b": { - "register": "Bm" + "register": "Vm.S[0]" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshld_n_s64", + "name": "vqrdmulh_s16", "arguments": [ - "int64_t a", - "const int n" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int64_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshld_n_u64", + "name": "vqrdmulh_s32", "arguments": [ - "uint64_t a", - "const int n" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2S" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshld_s64", + "name": "vqrdmulhh_lane_s16", "arguments": [ - "int64_t a", - "int64_t b" + "int16_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Hn" }, - "b": { - "register": "Dm" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ @@ -73212,26 +268191,31 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshld_u64", + "name": "vqrdmulhh_laneq_s16", "arguments": [ - "uint64_t a", - "int64_t b" + "int16_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint64_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Hn" }, - "b": { - "register": "Dm" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -73239,16 +268223,16 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlh_n_s16", + "name": "vqrdmulhh_s16", "arguments": [ "int16_t a", - "const int n" + "int16_t b" ], "return_type": { "value": "int16_t" @@ -73257,9 +268241,8 @@ "a": { "register": "Hn" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Hm" } }, "Architectures": [ @@ -73267,81 +268250,99 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlh_n_u16", + "name": "vqrdmulhq_lane_s16", "arguments": [ - "uint16_t a", - "const int n" + "int16x8_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8H" }, - "n": { + "lane": { "minimum": 0, - "maximum": 15 + "maximum": 3 + }, + "v": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlh_s16", + "name": "vqrdmulhq_lane_s32", "arguments": [ - "int16_t a", - "int16_t b" + "int32x4_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "int16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.4S" }, - "b": { - "register": "Hm" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlh_u16", + "name": "vqrdmulhq_laneq_s16", "arguments": [ - "uint16_t a", - "int16_t b" + "int16x8_t a", + "int16x8_t v", + "const int lane" ], "return_type": { - "value": "uint16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8H" }, - "b": { - "register": "Hm" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" } }, "Architectures": [ @@ -73349,57 +268350,58 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_s16", + "name": "vqrdmulhq_laneq_s32", "arguments": [ - "int16x8_t a", - "const int n" + "int32x4_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, - "n": { + "lane": { "minimum": 0, - "maximum": 15 + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_s32", + "name": "vqrdmulhq_n_s16", "arguments": [ - "int32x4_t a", - "const int n" + "int16x8_t a", + "int16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.H[0]" } }, "Architectures": [ @@ -73409,27 +268411,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_s64", + "name": "vqrdmulhq_n_s32", "arguments": [ - "int64x2_t a", - "const int n" + "int32x4_t a", + "int32_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.S[0]" } }, "Architectures": [ @@ -73439,27 +268440,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_s8", + "name": "vqrdmulhq_s16", "arguments": [ - "int8x16_t a", - "const int n" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -73469,27 +268469,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_u16", + "name": "vqrdmulhq_s32", "arguments": [ - "uint16x8_t a", - "const int n" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -73499,116 +268498,117 @@ ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_u32", + "name": "vqrdmulhs_lane_s32", "arguments": [ - "uint32x4_t a", - "const int n" + "int32_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Sn" }, - "n": { + "lane": { "minimum": 0, - "maximum": 31 + "maximum": 1 + }, + "v": { + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_u64", + "name": "vqrdmulhs_laneq_s32", "arguments": [ - "uint64x2_t a", - "const int n" + "int32_t a", + "int32x4_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Sn" }, - "n": { + "lane": { "minimum": 0, - "maximum": 63 + "maximum": 3 + }, + "v": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_n_u8", + "name": "vqrdmulhs_s32", "arguments": [ - "uint8x16_t a", - "const int n" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Sn" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UQSHL" + "SQRDMULH" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_s16", + "name": "vqrshl_s16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -73618,26 +268618,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_s32", + "name": "vqrshl_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ @@ -73647,26 +268647,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_s64", + "name": "vqrshl_s64", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Dn" }, "b": { - "register": "Vm.2D" + "register": "Dm" } }, "Architectures": [ @@ -73676,26 +268676,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_s8", + "name": "vqrshl_s8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" } }, "Architectures": [ @@ -73705,26 +268705,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_u16", + "name": "vqrshl_u16", "arguments": [ - "uint16x8_t a", - "int16x8_t b" + "uint16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -73734,26 +268734,26 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_u32", + "name": "vqrshl_u32", "arguments": [ - "uint32x4_t a", - "int32x4_t b" + "uint32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ @@ -73763,26 +268763,26 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_u64", + "name": "vqrshl_u64", "arguments": [ - "uint64x2_t a", - "int64x2_t b" + "uint64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Dn" }, "b": { - "register": "Vm.2D" + "register": "Dm" } }, "Architectures": [ @@ -73792,26 +268792,26 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlq_u8", + "name": "vqrshl_u8", "arguments": [ - "uint8x16_t a", - "int8x16_t b" + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" } }, "Architectures": [ @@ -73821,27 +268821,26 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshls_n_s32", + "name": "vqrshlb_s8", "arguments": [ - "int32_t a", - "const int n" + "int8_t a", + "int8_t b" ], "return_type": { - "value": "int32_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Bn" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Bm" } }, "Architectures": [ @@ -73849,27 +268848,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshls_n_u32", + "name": "vqrshlb_u8", "arguments": [ - "uint32_t a", - "const int n" + "uint8_t a", + "int8_t b" ], "return_type": { - "value": "uint32_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Bn" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Bm" } }, "Architectures": [ @@ -73877,26 +268875,26 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshls_s32", + "name": "vqrshld_s64", "arguments": [ - "int32_t a", - "int32_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "int32_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Dn" }, "b": { - "register": "Sm" + "register": "Dm" } }, "Architectures": [ @@ -73904,26 +268902,26 @@ ], "instructions": [ [ - "SQSHL" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshls_u32", + "name": "vqrshld_u64", "arguments": [ - "uint32_t a", - "int32_t b" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "uint32_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Dn" }, "b": { - "register": "Sm" + "register": "Dm" } }, "Architectures": [ @@ -73931,87 +268929,80 @@ ], "instructions": [ [ - "UQSHL" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlu_n_s16", + "name": "vqrshlh_s16", "arguments": [ - "int16x4_t a", - "const int n" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Hn" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlu_n_s32", + "name": "vqrshlh_u16", "arguments": [ - "int32x2_t a", - "const int n" + "uint16_t a", + "int16_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Hn" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Hm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlu_n_s64", + "name": "vqrshlq_s16", "arguments": [ - "int64x1_t a", - "const int n" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -74021,27 +269012,26 @@ ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlu_n_s8", + "name": "vqrshlq_s32", "arguments": [ - "int8x8_t a", - "const int n" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -74051,111 +269041,113 @@ ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlub_n_s8", + "name": "vqrshlq_s64", "arguments": [ - "int8_t a", - "const int n" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Bn" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlud_n_s64", + "name": "vqrshlq_s8", "arguments": [ - "int64_t a", - "const int n" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint64_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.16B" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluh_n_s16", + "name": "vqrshlq_u16", "arguments": [ - "int16_t a", - "const int n" + "uint16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluq_n_s16", + "name": "vqrshlq_u32", "arguments": [ - "int16x8_t a", - "const int n" + "uint32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -74165,27 +269157,26 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluq_n_s32", + "name": "vqrshlq_u64", "arguments": [ - "int32x4_t a", - "const int n" + "uint64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -74195,27 +269186,26 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluq_n_s64", + "name": "vqrshlq_u8", "arguments": [ - "int64x2_t a", - "const int n" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -74225,46 +269215,43 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshluq_n_s8", + "name": "vqrshls_s32", "arguments": [ - "int8x16_t a", - "const int n" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Sn" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SQSHLU" + "SQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshlus_n_s32", + "name": "vqrshls_u32", "arguments": [ - "int32_t a", - "const int n" + "uint32_t a", + "int32_t b" ], "return_type": { "value": "uint32_t" @@ -74273,9 +269260,8 @@ "a": { "register": "Sn" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Sm" } }, "Architectures": [ @@ -74283,13 +269269,13 @@ ], "instructions": [ [ - "SQSHLU" + "UQRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_s16", + "name": "vqrshrn_high_n_s16", "arguments": [ "int8x8_t r", "int16x8_t a", @@ -74315,13 +269301,13 @@ ], "instructions": [ [ - "SQSHRN2" + "SQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_s32", + "name": "vqrshrn_high_n_s32", "arguments": [ "int16x4_t r", "int32x4_t a", @@ -74347,13 +269333,13 @@ ], "instructions": [ [ - "SQSHRN2" + "SQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_s64", + "name": "vqrshrn_high_n_s64", "arguments": [ "int32x2_t r", "int64x2_t a", @@ -74379,13 +269365,13 @@ ], "instructions": [ [ - "SQSHRN2" + "SQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_u16", + "name": "vqrshrn_high_n_u16", "arguments": [ "uint8x8_t r", "uint16x8_t a", @@ -74411,13 +269397,13 @@ ], "instructions": [ [ - "UQSHRN2" + "UQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_u32", + "name": "vqrshrn_high_n_u32", "arguments": [ "uint16x4_t r", "uint32x4_t a", @@ -74443,13 +269429,13 @@ ], "instructions": [ [ - "UQSHRN2" + "UQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_high_n_u64", + "name": "vqrshrn_high_n_u64", "arguments": [ "uint32x2_t r", "uint64x2_t a", @@ -74475,13 +269461,13 @@ ], "instructions": [ [ - "UQSHRN2" + "UQRSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_s16", + "name": "vqrshrn_n_s16", "arguments": [ "int16x8_t a", "const int n" @@ -74505,13 +269491,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_s32", + "name": "vqrshrn_n_s32", "arguments": [ "int32x4_t a", "const int n" @@ -74535,13 +269521,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_s64", + "name": "vqrshrn_n_s64", "arguments": [ "int64x2_t a", "const int n" @@ -74565,13 +269551,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_u16", + "name": "vqrshrn_n_u16", "arguments": [ "uint16x8_t a", "const int n" @@ -74595,13 +269581,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_u32", + "name": "vqrshrn_n_u32", "arguments": [ "uint32x4_t a", "const int n" @@ -74625,13 +269611,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrn_n_u64", + "name": "vqrshrn_n_u64", "arguments": [ "uint64x2_t a", "const int n" @@ -74655,13 +269641,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrnd_n_s64", + "name": "vqrshrnd_n_s64", "arguments": [ "int64_t a", "const int n" @@ -74683,13 +269669,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrnd_n_u64", + "name": "vqrshrnd_n_u64", "arguments": [ "uint64_t a", "const int n" @@ -74711,13 +269697,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrnh_n_s16", + "name": "vqrshrnh_n_s16", "arguments": [ "int16_t a", "const int n" @@ -74739,13 +269725,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrnh_n_u16", + "name": "vqrshrnh_n_u16", "arguments": [ "uint16_t a", "const int n" @@ -74767,13 +269753,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrns_n_s32", + "name": "vqrshrns_n_s32", "arguments": [ "int32_t a", "const int n" @@ -74795,13 +269781,13 @@ ], "instructions": [ [ - "SQSHRN" + "SQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrns_n_u32", + "name": "vqrshrns_n_u32", "arguments": [ "uint32_t a", "const int n" @@ -74823,13 +269809,13 @@ ], "instructions": [ [ - "UQSHRN" + "UQRSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_high_n_s16", + "name": "vqrshrun_high_n_s16", "arguments": [ "uint8x8_t r", "int16x8_t a", @@ -74855,13 +269841,13 @@ ], "instructions": [ [ - "SQSHRUN2" + "SQRSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_high_n_s32", + "name": "vqrshrun_high_n_s32", "arguments": [ "uint16x4_t r", "int32x4_t a", @@ -74887,13 +269873,13 @@ ], "instructions": [ [ - "SQSHRUN2" + "SQRSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_high_n_s64", + "name": "vqrshrun_high_n_s64", "arguments": [ "uint32x2_t r", "int64x2_t a", @@ -74919,13 +269905,13 @@ ], "instructions": [ [ - "SQSHRUN2" + "SQRSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_n_s16", + "name": "vqrshrun_n_s16", "arguments": [ "int16x8_t a", "const int n" @@ -74949,13 +269935,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_n_s32", + "name": "vqrshrun_n_s32", "arguments": [ "int32x4_t a", "const int n" @@ -74979,13 +269965,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrun_n_s64", + "name": "vqrshrun_n_s64", "arguments": [ "int64x2_t a", "const int n" @@ -75009,13 +269995,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrund_n_s64", + "name": "vqrshrund_n_s64", "arguments": [ "int64_t a", "const int n" @@ -75037,13 +270023,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshrunh_n_s16", + "name": "vqrshrunh_n_s16", "arguments": [ "int16_t a", "const int n" @@ -75065,13 +270051,13 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqshruns_n_s32", + "name": "vqrshruns_n_s32", "arguments": [ "int32_t a", "const int n" @@ -75093,13 +270079,253 @@ ], "instructions": [ [ - "SQSHRUN" + "SQRSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_s16", + "name": "vqshl_n_s16", + "arguments": [ + "int16x4_t a", + "const int n" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "minimum": 0, + "maximum": 15 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_s32", + "arguments": [ + "int32x2_t a", + "const int n" + ], + "return_type": { + "value": "int32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" + }, + "n": { + "minimum": 0, + "maximum": 31 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_s64", + "arguments": [ + "int64x1_t a", + "const int n" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dn" + }, + "n": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_s8", + "arguments": [ + "int8x8_t a", + "const int n" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_u16", + "arguments": [ + "uint16x4_t a", + "const int n" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "minimum": 0, + "maximum": 15 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_u32", + "arguments": [ + "uint32x2_t a", + "const int n" + ], + "return_type": { + "value": "uint32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" + }, + "n": { + "minimum": 0, + "maximum": 31 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_u64", + "arguments": [ + "uint64x1_t a", + "const int n" + ], + "return_type": { + "value": "uint64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dn" + }, + "n": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_n_u8", + "arguments": [ + "uint8x8_t a", + "const int n" + ], + "return_type": { + "value": "uint8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshl_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -75122,13 +270348,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_s32", + "name": "vqshl_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -75151,13 +270377,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_s64", + "name": "vqshl_s64", "arguments": [ "int64x1_t a", "int64x1_t b" @@ -75180,13 +270406,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_s8", + "name": "vqshl_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -75209,16 +270435,16 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_u16", + "name": "vqshl_u16", "arguments": [ "uint16x4_t a", - "uint16x4_t b" + "int16x4_t b" ], "return_type": { "value": "uint16x4_t" @@ -75238,16 +270464,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_u32", + "name": "vqshl_u32", "arguments": [ "uint32x2_t a", - "uint32x2_t b" + "int32x2_t b" ], "return_type": { "value": "uint32x2_t" @@ -75267,16 +270493,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_u64", + "name": "vqshl_u64", "arguments": [ "uint64x1_t a", - "uint64x1_t b" + "int64x1_t b" ], "return_type": { "value": "uint64x1_t" @@ -75296,16 +270522,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsub_u8", + "name": "vqshl_u8", "arguments": [ "uint8x8_t a", - "uint8x8_t b" + "int8x8_t b" ], "return_type": { "value": "uint8x8_t" @@ -75325,13 +270551,69 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubb_s8", + "name": "vqshlb_n_s8", + "arguments": [ + "int8_t a", + "const int n" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Bn" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlb_n_u8", + "arguments": [ + "uint8_t a", + "const int n" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Bn" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlb_s8", "arguments": [ "int8_t a", "int8_t b" @@ -75352,16 +270634,16 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubb_u8", + "name": "vqshlb_u8", "arguments": [ "uint8_t a", - "uint8_t b" + "int8_t b" ], "return_type": { "value": "uint8_t" @@ -75379,121 +270661,473 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubd_s64", + "name": "vqshld_n_s64", + "arguments": [ + "int64_t a", + "const int n" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dn" + }, + "n": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshld_n_u64", + "arguments": [ + "uint64_t a", + "const int n" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dn" + }, + "n": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshld_s64", "arguments": [ "int64_t a", "int64_t b" ], "return_type": { - "value": "int64_t" + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dn" + }, + "b": { + "register": "Dm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshld_u64", + "arguments": [ + "uint64_t a", + "int64_t b" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dn" + }, + "b": { + "register": "Dm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlh_n_s16", + "arguments": [ + "int16_t a", + "const int n" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 0, + "maximum": 15 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlh_n_u16", + "arguments": [ + "uint16_t a", + "const int n" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 0, + "maximum": 15 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlh_s16", + "arguments": [ + "int16_t a", + "int16_t b" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlh_u16", + "arguments": [ + "uint16_t a", + "int16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlq_n_s16", + "arguments": [ + "int16x8_t a", + "const int n" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "n": { + "minimum": 0, + "maximum": 15 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlq_n_s32", + "arguments": [ + "int32x4_t a", + "const int n" + ], + "return_type": { + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4S" + }, + "n": { + "minimum": 0, + "maximum": 31 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlq_n_s64", + "arguments": [ + "int64x2_t a", + "const int n" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "n": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlq_n_s8", + "arguments": [ + "int8x16_t a", + "const int n" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshlq_n_u16", + "arguments": [ + "uint16x8_t a", + "const int n" + ], + "return_type": { + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8H" }, - "b": { - "register": "Dm" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubd_u64", + "name": "vqshlq_n_u32", "arguments": [ - "uint64_t a", - "uint64_t b" + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "uint64_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4S" }, - "b": { - "register": "Dm" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubh_s16", + "name": "vqshlq_n_u64", "arguments": [ - "int16_t a", - "int16_t b" + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "int16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.2D" }, - "b": { - "register": "Hm" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubh_u16", + "name": "vqshlq_n_u8", "arguments": [ - "uint16_t a", - "uint16_t b" + "uint8x16_t a", + "const int n" ], "return_type": { - "value": "uint16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.16B" }, - "b": { - "register": "Hm" + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_s16", + "name": "vqshlq_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -75516,13 +271150,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_s32", + "name": "vqshlq_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -75545,13 +271179,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_s64", + "name": "vqshlq_s64", "arguments": [ "int64x2_t a", "int64x2_t b" @@ -75574,13 +271208,13 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_s8", + "name": "vqshlq_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -75603,16 +271237,16 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_u16", + "name": "vqshlq_u16", "arguments": [ "uint16x8_t a", - "uint16x8_t b" + "int16x8_t b" ], "return_type": { "value": "uint16x8_t" @@ -75632,16 +271266,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_u32", + "name": "vqshlq_u32", "arguments": [ "uint32x4_t a", - "uint32x4_t b" + "int32x4_t b" ], "return_type": { "value": "uint32x4_t" @@ -75661,16 +271295,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_u64", + "name": "vqshlq_u64", "arguments": [ "uint64x2_t a", - "uint64x2_t b" + "int64x2_t b" ], "return_type": { "value": "uint64x2_t" @@ -75690,16 +271324,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubq_u8", + "name": "vqshlq_u8", "arguments": [ "uint8x16_t a", - "uint8x16_t b" + "int8x16_t b" ], "return_type": { "value": "uint8x16_t" @@ -75719,16 +271353,16 @@ ], "instructions": [ [ - "UQSUB" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubs_s32", + "name": "vqshls_n_s32", "arguments": [ "int32_t a", - "int32_t b" + "const int n" ], "return_type": { "value": "int32_t" @@ -75737,8 +271371,9 @@ "a": { "register": "Sn" }, - "b": { - "register": "Sm" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -75746,20 +271381,48 @@ ], "instructions": [ [ - "SQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqsubs_u32", + "name": "vqshls_n_u32", "arguments": [ "uint32_t a", - "uint32_t b" + "const int n" ], "return_type": { "value": "uint32_t" }, + "Arguments_Preparation": { + "a": { + "register": "Sn" + }, + "n": { + "minimum": 0, + "maximum": 31 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqshls_s32", + "arguments": [ + "int32_t a", + "int32_t b" + ], + "return_type": { + "value": "int32_t" + }, "Arguments_Preparation": { "a": { "register": "Sn" @@ -75773,26 +271436,26 @@ ], "instructions": [ [ - "UQSUB" + "SQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1_p8", + "name": "vqshls_u32", "arguments": [ - "poly8x16_t t", - "uint8x8_t idx" + "uint32_t a", + "int32_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Sm" } }, "Architectures": [ @@ -75800,134 +271463,147 @@ ], "instructions": [ [ - "TBL" + "UQSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1_s8", + "name": "vqshlu_n_s16", "arguments": [ - "int8x16_t t", - "uint8x8_t idx" + "int16x4_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.4H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1_u8", + "name": "vqshlu_n_s32", "arguments": [ - "uint8x16_t t", - "uint8x8_t idx" + "int32x2_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.2S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1q_p8", + "name": "vqshlu_n_s64", "arguments": [ - "poly8x16_t t", - "uint8x16_t idx" + "int64x1_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1q_s8", + "name": "vqshlu_n_s8", "arguments": [ - "int8x16_t t", - "uint8x16_t idx" + "int8x8_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.8B" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl1q_u8", + "name": "vqshlub_n_s8", "arguments": [ - "uint8x16_t t", - "uint8x16_t idx" + "int8_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Bn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -75935,26 +271611,27 @@ ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2_p8", + "name": "vqshlud_n_s64", "arguments": [ - "poly8x16x2_t t", - "uint8x8_t idx" + "int64_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint64_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -75962,26 +271639,27 @@ ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2_s8", + "name": "vqshluh_n_s16", "arguments": [ - "int8x16x2_t t", - "uint8x8_t idx" + "int16_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Hn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -75989,134 +271667,147 @@ ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2_u8", + "name": "vqshluq_n_s16", "arguments": [ - "uint8x16x2_t t", - "uint8x8_t idx" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2q_p8", + "name": "vqshluq_n_s32", "arguments": [ - "poly8x16x2_t t", - "uint8x16_t idx" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2q_s8", + "name": "vqshluq_n_s64", "arguments": [ - "int8x16x2_t t", - "uint8x16_t idx" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl2q_u8", + "name": "vqshluq_n_s8", "arguments": [ - "uint8x16x2_t t", - "uint8x16_t idx" + "int8x16_t a", + "const int n" ], "return_type": { "value": "uint8x16_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" - }, - "t": { + "a": { "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3_p8", + "name": "vqshlus_n_s32", "arguments": [ - "poly8x16x3_t t", - "uint8x8_t idx" + "int32_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -76124,26 +271815,31 @@ ], "instructions": [ [ - "TBL" + "SQSHLU" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3_s8", + "name": "vqshrn_high_n_s16", "arguments": [ - "int8x16x3_t t", - "uint8x8_t idx" + "int8x8_t r", + "int16x8_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -76151,26 +271847,31 @@ ], "instructions": [ [ - "TBL" + "SQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3_u8", + "name": "vqshrn_high_n_s32", "arguments": [ - "uint8x16x3_t t", - "uint8x8_t idx" + "int16x4_t r", + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -76178,26 +271879,31 @@ ], "instructions": [ [ - "TBL" + "SQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3q_p8", + "name": "vqshrn_high_n_s64", "arguments": [ - "poly8x16x3_t t", - "uint8x16_t idx" + "int32x2_t r", + "int64x2_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -76205,26 +271911,31 @@ ], "instructions": [ [ - "TBL" + "SQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3q_s8", + "name": "vqshrn_high_n_u16", "arguments": [ - "int8x16x3_t t", - "uint8x16_t idx" + "uint8x8_t r", + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -76232,26 +271943,31 @@ ], "instructions": [ [ - "TBL" + "UQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl3q_u8", + "name": "vqshrn_high_n_u32", "arguments": [ - "uint8x16x3_t t", - "uint8x16_t idx" + "uint16x4_t r", + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -76259,26 +271975,31 @@ ], "instructions": [ [ - "TBL" + "UQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4_p8", + "name": "vqshrn_high_n_u64", "arguments": [ - "poly8x16x4_t t", - "uint8x8_t idx" + "uint32x2_t r", + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -76286,196 +272007,207 @@ ], "instructions": [ [ - "TBL" + "UQSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4_s8", + "name": "vqshrn_n_s16", "arguments": [ - "int8x16x4_t t", - "uint8x8_t idx" + "int16x8_t a", + "const int n" ], "return_type": { "value": "int8x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4_u8", + "name": "vqshrn_n_s32", "arguments": [ - "uint8x16x4_t t", - "uint8x8_t idx" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.8B" + "a": { + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4q_p8", + "name": "vqshrn_n_s64", "arguments": [ - "poly8x16x4_t t", - "uint8x16_t idx" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4q_s8", + "name": "vqshrn_n_u16", "arguments": [ - "int8x16x4_t t", - "uint8x16_t idx" + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbl4q_u8", + "name": "vqshrn_n_u32", "arguments": [ - "uint8x16x4_t t", - "uint8x16_t idx" + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "idx": { - "register": "Vm.16B" + "a": { + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBL" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1_p8", + "name": "vqshrn_n_u64", "arguments": [ - "poly8x8_t a", - "poly8x16_t t", - "uint8x8_t idx" + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1_s8", + "name": "vqshrnd_n_s64", "arguments": [ - "int8x8_t a", - "int8x16_t t", - "uint8x8_t idx" + "int64_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -76483,30 +272215,27 @@ ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1_u8", + "name": "vqshrnd_n_u64", "arguments": [ - "uint8x8_t a", - "uint8x16_t t", - "uint8x8_t idx" + "uint64_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -76514,30 +272243,27 @@ ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1q_p8", + "name": "vqshrnh_n_s16", "arguments": [ - "poly8x16_t a", - "poly8x16_t t", - "uint8x16_t idx" + "int16_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Hn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -76545,30 +272271,27 @@ ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1q_s8", + "name": "vqshrnh_n_u16", "arguments": [ - "int8x16_t a", - "int8x16_t t", - "uint8x16_t idx" + "uint16_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Hn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -76576,30 +272299,27 @@ ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx1q_u8", + "name": "vqshrns_n_s32", "arguments": [ - "uint8x16_t a", - "uint8x16_t t", - "uint8x16_t idx" + "int32_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -76607,30 +272327,27 @@ ], "instructions": [ [ - "TBX" + "SQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2_p8", + "name": "vqshrns_n_u32", "arguments": [ - "poly8x8_t a", - "poly8x16x2_t t", - "uint8x8_t idx" + "uint32_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -76638,30 +272355,31 @@ ], "instructions": [ [ - "TBX" + "UQSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2_s8", + "name": "vqshrun_high_n_s16", "arguments": [ - "int8x8_t a", - "int8x16x2_t t", - "uint8x8_t idx" + "uint8x8_t r", + "int16x8_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.8H" }, - "idx": { - "register": "Vm.8B" + "n": { + "minimum": 1, + "maximum": 8 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -76669,30 +272387,31 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2_u8", + "name": "vqshrun_high_n_s32", "arguments": [ - "uint8x8_t a", - "uint8x16x2_t t", - "uint8x8_t idx" + "uint16x4_t r", + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.4S" }, - "idx": { - "register": "Vm.8B" + "n": { + "minimum": 1, + "maximum": 16 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -76700,30 +272419,31 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2q_p8", + "name": "vqshrun_high_n_s64", "arguments": [ - "poly8x16_t a", - "poly8x16x2_t t", - "uint8x16_t idx" + "uint32x2_t r", + "int64x2_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.2D" }, - "idx": { - "register": "Vm.16B" + "n": { + "minimum": 1, + "maximum": 32 }, - "t": { - "register": "Vn.16B" + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -76731,123 +272451,117 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2q_s8", + "name": "vqshrun_n_s16", "arguments": [ - "int8x16_t a", - "int8x16x2_t t", - "uint8x16_t idx" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.8H" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx2q_u8", + "name": "vqshrun_n_s32", "arguments": [ - "uint8x16_t a", - "uint8x16x2_t t", - "uint8x16_t idx" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.4S" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3_p8", + "name": "vqshrun_n_s64", "arguments": [ - "poly8x8_t a", - "poly8x16x3_t t", - "uint8x8_t idx" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Vn.2D" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3_s8", + "name": "vqshrund_n_s64", "arguments": [ - "int8x8_t a", - "int8x16x3_t t", - "uint8x8_t idx" + "int64_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -76855,30 +272569,27 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3_u8", + "name": "vqshrunh_n_s16", "arguments": [ - "uint8x8_t a", - "uint8x16x3_t t", - "uint8x8_t idx" + "int16_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Hn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -76886,30 +272597,27 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3q_p8", + "name": "vqshruns_n_s32", "arguments": [ - "poly8x16_t a", - "poly8x16x3_t t", - "uint8x16_t idx" + "int32_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Sn" }, - "t": { - "register": "Vn.16B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -76917,278 +272625,258 @@ ], "instructions": [ [ - "TBX" + "SQSHRUN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3q_s8", + "name": "vqsub_s16", "arguments": [ - "int8x16_t a", - "int8x16x3_t t", - "uint8x16_t idx" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.4H" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx3q_u8", + "name": "vqsub_s32", "arguments": [ - "uint8x16_t a", - "uint8x16x3_t t", - "uint8x16_t idx" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.2S" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4_p8", + "name": "vqsub_s64", "arguments": [ - "poly8x8_t a", - "poly8x16x4_t t", - "uint8x8_t idx" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4_s8", + "name": "vqsub_s8", "arguments": [ "int8x8_t a", - "int8x16x4_t t", - "uint8x8_t idx" + "int8x8_t b" ], "return_type": { "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.8B" }, - "idx": { + "b": { "register": "Vm.8B" - }, - "t": { - "register": "Vn.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4_u8", + "name": "vqsub_u16", "arguments": [ - "uint8x8_t a", - "uint8x16x4_t t", - "uint8x8_t idx" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "idx": { - "register": "Vm.8B" + "register": "Vn.4H" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4q_p8", + "name": "vqsub_u32", "arguments": [ - "poly8x16_t a", - "poly8x16x4_t t", - "uint8x16_t idx" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.2S" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4q_s8", + "name": "vqsub_u64", "arguments": [ - "int8x16_t a", - "int8x16x4_t t", - "uint8x16_t idx" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Dn" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vqtbx4q_u8", + "name": "vqsub_u8", "arguments": [ - "uint8x16_t a", - "uint8x16x4_t t", - "uint8x16_t idx" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "idx": { - "register": "Vm.16B" + "register": "Vn.8B" }, - "t": { - "register": "Vn.16B" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TBX" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_s16", + "name": "vqsubb_s8", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "int16x8_t b" + "int8_t a", + "int8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Bn" }, "b": { - "register": "Vm.8H" - }, - "r": { - "register": "Vd.8B" + "register": "Bm" } }, "Architectures": [ @@ -77196,30 +272884,26 @@ ], "instructions": [ [ - "RADDHN2" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_s32", + "name": "vqsubb_u8", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "int32x4_t b" + "uint8_t a", + "uint8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Bn" }, "b": { - "register": "Vm.4S" - }, - "r": { - "register": "Vd.4H" + "register": "Bm" } }, "Architectures": [ @@ -77227,30 +272911,26 @@ ], "instructions": [ [ - "RADDHN2" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_s64", + "name": "vqsubd_s64", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "int64x2_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Dn" }, "b": { - "register": "Vm.2D" - }, - "r": { - "register": "Vd.2S" + "register": "Dm" } }, "Architectures": [ @@ -77258,30 +272938,26 @@ ], "instructions": [ [ - "RADDHN2" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_u16", + "name": "vqsubd_u64", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "uint16x8_t b" + "uint64_t a", + "uint64_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Dn" }, "b": { - "register": "Vm.8H" - }, - "r": { - "register": "Vd.8B" + "register": "Dm" } }, "Architectures": [ @@ -77289,30 +272965,26 @@ ], "instructions": [ [ - "RADDHN2" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_u32", + "name": "vqsubh_s16", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "uint32x4_t b" + "int16_t a", + "int16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Hn" }, "b": { - "register": "Vm.4S" - }, - "r": { - "register": "Vd.4H" + "register": "Hm" } }, "Architectures": [ @@ -77320,30 +272992,26 @@ ], "instructions": [ [ - "RADDHN2" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_high_u64", + "name": "vqsubh_u16", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "uint64x2_t b" + "uint16_t a", + "uint16_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Hn" }, "b": { - "register": "Vm.2D" - }, - "r": { - "register": "Vd.2S" + "register": "Hm" } }, "Architectures": [ @@ -77351,19 +273019,19 @@ ], "instructions": [ [ - "RADDHN2" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_s16", + "name": "vqsubq_s16", "arguments": [ "int16x8_t a", "int16x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -77380,19 +273048,19 @@ ], "instructions": [ [ - "RADDHN" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_s32", + "name": "vqsubq_s32", "arguments": [ "int32x4_t a", "int32x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -77409,19 +273077,19 @@ ], "instructions": [ [ - "RADDHN" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_s64", + "name": "vqsubq_s64", "arguments": [ "int64x2_t a", "int64x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -77438,19 +273106,48 @@ ], "instructions": [ [ - "RADDHN" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_u16", + "name": "vqsubq_s8", + "arguments": [ + "int8x16_t a", + "int8x16_t b" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vqsubq_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -77467,19 +273164,19 @@ ], "instructions": [ [ - "RADDHN" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_u32", + "name": "vqsubq_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -77496,19 +273193,19 @@ ], "instructions": [ [ - "RADDHN" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vraddhn_u64", + "name": "vqsubq_u64", "arguments": [ "uint64x2_t a", "uint64x2_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { @@ -77525,47 +273222,55 @@ ], "instructions": [ [ - "RADDHN" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrax1q_u64", + "name": "vqsubq_u8", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, - "b": {} + "b": { + "register": "Vm.16B" + } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RAX1" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbit_p8", + "name": "vqsubs_s32", "arguments": [ - "poly8x8_t a" + "int32_t a", + "int32_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "int32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ @@ -77573,22 +273278,26 @@ ], "instructions": [ [ - "RBIT" + "SQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbit_s8", + "name": "vqsubs_u32", "arguments": [ - "int8x8_t a" + "uint32_t a", + "uint32_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ @@ -77596,22 +273305,26 @@ ], "instructions": [ [ - "RBIT" + "UQSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbit_u8", + "name": "vqtbl1_p8", "arguments": [ - "uint8x8_t a" + "poly8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "uint8x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "idx": { + "register": "Vm.8B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -77619,21 +273332,25 @@ ], "instructions": [ [ - "RBIT" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbitq_p8", + "name": "vqtbl1_s8", "arguments": [ - "poly8x16_t a" + "int8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "poly8x16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "idx": { + "register": "Vm.8B" + }, + "t": { "register": "Vn.16B" } }, @@ -77642,21 +273359,25 @@ ], "instructions": [ [ - "RBIT" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbitq_s8", + "name": "vqtbl1_u8", "arguments": [ - "int8x16_t a" + "uint8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "idx": { + "register": "Vm.8B" + }, + "t": { "register": "Vn.16B" } }, @@ -77665,21 +273386,25 @@ ], "instructions": [ [ - "RBIT" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrbitq_u8", + "name": "vqtbl1q_p8", "arguments": [ - "uint8x16_t a" + "poly8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "uint8x16_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { + "idx": { + "register": "Vm.16B" + }, + "t": { "register": "Vn.16B" } }, @@ -77688,71 +273413,83 @@ ], "instructions": [ [ - "RBIT" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpe_f16", + "name": "vqtbl1q_s8", "arguments": [ - "float16x4_t a" + "int8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "idx": { + "register": "Vm.16B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpe_f32", + "name": "vqtbl1q_u8", "arguments": [ - "float32x2_t a" + "uint8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "idx": { + "register": "Vm.16B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpe_f64", + "name": "vqtbl2_p8", "arguments": [ - "float64x1_t a" + "poly8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -77760,47 +273497,59 @@ ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpe_u32", + "name": "vqtbl2_s8", "arguments": [ - "uint32x2_t a" + "int8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "uint32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecped_f64", + "name": "vqtbl2_u8", "arguments": [ - "float64_t a" + "uint8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -77808,22 +273557,29 @@ ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeh_f16", + "name": "vqtbl2q_p8", "arguments": [ - "float16_t a" + "poly8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -77831,71 +273587,92 @@ ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeq_f16", + "name": "vqtbl2q_s8", "arguments": [ - "float16x8_t a" + "int8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeq_f32", + "name": "vqtbl2q_u8", "arguments": [ - "float32x4_t a" + "uint8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeq_f64", + "name": "vqtbl3_p8", "arguments": [ - "float64x2_t a" + "poly8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -77903,47 +273680,65 @@ ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpeq_u32", + "name": "vqtbl3_s8", "arguments": [ - "uint32x4_t a" + "int8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "uint32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpes_f32", + "name": "vqtbl3_u8", "arguments": [ - "float32_t a" + "uint8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -77951,83 +273746,98 @@ ], "instructions": [ [ - "FRECPE" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecps_f16", + "name": "vqtbl3q_p8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Vm.4H" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecps_f32", + "name": "vqtbl3q_s8", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Vm.2S" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecps_f64", + "name": "vqtbl3q_u8", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "uint8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Dm" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -78035,26 +273845,35 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsd_f64", + "name": "vqtbl4_p8", "arguments": [ - "float64_t a", - "float64_t b" + "poly8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "idx": { + "register": "Vm.8B" }, - "b": { - "register": "Dm" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -78062,26 +273881,35 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsh_f16", + "name": "vqtbl4_s8", "arguments": [ - "float16_t a", - "float16_t b" + "int8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "idx": { + "register": "Vm.8B" }, - "b": { - "register": "Hm" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -78089,83 +273917,107 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsq_f16", + "name": "vqtbl4_u8", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "idx": { + "register": "Vm.8B" }, - "b": { - "register": "Vm.8H" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsq_f32", + "name": "vqtbl4q_p8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "poly8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Vm.4S" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpsq_f64", + "name": "vqtbl4q_s8", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float64x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Vm.2D" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -78173,26 +274025,35 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpss_f32", + "name": "vqtbl4q_u8", "arguments": [ - "float32_t a", - "float32_t b" + "uint8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Sn" + "idx": { + "register": "Vm.16B" }, - "b": { - "register": "Sm" + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -78200,22 +274061,30 @@ ], "instructions": [ [ - "FRECPS" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpxd_f64", + "name": "vqtbx1_p8", "arguments": [ - "float64_t a" + "poly8x8_t a", + "poly8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float64_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -78223,22 +274092,30 @@ ], "instructions": [ [ - "FRECPX" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpxh_f16", + "name": "vqtbx1_s8", "arguments": [ - "float16_t a" + "int8x8_t a", + "int8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -78246,22 +274123,30 @@ ], "instructions": [ [ - "FRECPX" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrecpxs_f32", + "name": "vqtbx1_u8", "arguments": [ - "float32_t a" + "uint8x8_t a", + "uint8x16_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -78269,47 +274154,61 @@ ], "instructions": [ [ - "FRECPX" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_f32", + "name": "vqtbx1q_p8", "arguments": [ - "float32x2_t a" + "poly8x16_t a", + "poly8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_f64", + "name": "vqtbx1q_s8", "arguments": [ - "float64x1_t a" + "int8x16_t a", + "int8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ @@ -78317,321 +274216,456 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_p16", + "name": "vqtbx1q_u8", "arguments": [ - "poly16x4_t a" + "uint8x16_t a", + "uint8x16_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t": { + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_p64", + "name": "vqtbx2_p8", "arguments": [ - "poly64x1_t a" + "poly8x8_t a", + "poly8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_p8", + "name": "vqtbx2_s8", "arguments": [ - "poly8x8_t a" + "int8x8_t a", + "int8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_s16", + "name": "vqtbx2_u8", "arguments": [ - "int16x4_t a" + "uint8x8_t a", + "uint8x16x2_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_s32", + "name": "vqtbx2q_p8", "arguments": [ - "int32x2_t a" + "poly8x16_t a", + "poly8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_s64", + "name": "vqtbx2q_s8", "arguments": [ - "int64x1_t a" + "int8x16_t a", + "int8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_s8", + "name": "vqtbx2q_u8", "arguments": [ - "int8x8_t a" + "uint8x16_t a", + "uint8x16x2_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_u16", + "name": "vqtbx3_p8", "arguments": [ - "uint16x4_t a" + "poly8x8_t a", + "poly8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_u32", + "name": "vqtbx3_s8", "arguments": [ - "uint32x2_t a" + "int8x8_t a", + "int8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_u64", + "name": "vqtbx3_u8", "arguments": [ - "uint64x1_t a" + "uint8x8_t a", + "uint8x16x3_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f16_u8", + "name": "vqtbx3q_p8", "arguments": [ - "uint8x8_t a" + "poly8x16_t a", + "poly8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float16x4_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_f16", + "name": "vqtbx3q_s8", "arguments": [ - "float16x4_t a" + "int8x16_t a", + "int8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_f64", + "name": "vqtbx3q_u8", "arguments": [ - "float64x1_t a" + "uint8x16_t a", + "uint8x16x3_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -78639,271 +274673,393 @@ ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_p16", + "name": "vqtbx4_p8", "arguments": [ - "poly16x4_t a" + "poly8x8_t a", + "poly8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_p8", + "name": "vqtbx4_s8", "arguments": [ - "poly8x8_t a" + "int8x8_t a", + "int8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_s16", + "name": "vqtbx4_u8", "arguments": [ - "int16x4_t a" + "uint8x8_t a", + "uint8x16x4_t t", + "uint8x8_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_s32", + "name": "vqtbx4q_p8", "arguments": [ - "int32x2_t a" + "poly8x16_t a", + "poly8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_s64", + "name": "vqtbx4q_s8", "arguments": [ - "int64x1_t a" + "int8x16_t a", + "int8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_s8", + "name": "vqtbx4q_u8", "arguments": [ - "int8x8_t a" + "uint8x16_t a", + "uint8x16x4_t t", + "uint8x16_t idx" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.16B" + }, + "idx": { + "register": "Vm.16B" + }, + "t.val[0]": { + "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_u16", + "name": "vraddhn_high_s16", "arguments": [ - "uint16x4_t a" + "int8x8_t r", + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_u32", + "name": "vraddhn_high_s32", "arguments": [ - "uint32x2_t a" + "int16x4_t r", + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_u64", + "name": "vraddhn_high_s64", "arguments": [ - "uint64x1_t a" + "int32x2_t r", + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f32_u8", + "name": "vraddhn_high_u16", "arguments": [ - "uint8x8_t a" + "uint8x8_t r", + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, + "r": { "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_f16", + "name": "vraddhn_high_u32", "arguments": [ - "float16x4_t a" + "uint16x4_t r", + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "float64x1_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, + "r": { "register": "Vd.4H" } }, @@ -78912,21 +275068,29 @@ ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_f32", + "name": "vraddhn_high_u64", "arguments": [ - "float32x2_t a" + "uint32x2_t r", + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, + "r": { "register": "Vd.2S" } }, @@ -78935,160 +275099,200 @@ ], "instructions": [ [ - "NOP" + "RADDHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_p16", + "name": "vraddhn_s16", "arguments": [ - "poly16x4_t a" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_p64", + "name": "vraddhn_s32", "arguments": [ - "poly64x1_t a" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_p8", + "name": "vraddhn_s64", "arguments": [ - "poly8x8_t a" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_s16", + "name": "vraddhn_u16", "arguments": [ - "int16x4_t a" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_s32", + "name": "vraddhn_u32", "arguments": [ - "int32x2_t a" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "float64x1_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_s64", + "name": "vraddhn_u64", "arguments": [ - "int64x1_t a" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "NOP" + "RADDHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_s8", + "name": "vrax1q_u64", "arguments": [ - "int8x8_t a" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "float64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -79096,22 +275300,22 @@ ], "instructions": [ [ - "NOP" + "RAX1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_u16", + "name": "vrbit_p8", "arguments": [ - "uint16x4_t a" + "poly8x8_t a" ], "return_type": { - "value": "float64x1_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8B" } }, "Architectures": [ @@ -79119,22 +275323,22 @@ ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_u32", + "name": "vrbit_s8", "arguments": [ - "uint32x2_t a" + "int8x8_t a" ], "return_type": { - "value": "float64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.8B" } }, "Architectures": [ @@ -79142,22 +275346,22 @@ ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_u64", + "name": "vrbit_u8", "arguments": [ - "uint64x1_t a" + "uint8x8_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.8B" } }, "Architectures": [ @@ -79165,22 +275369,22 @@ ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_f64_u8", + "name": "vrbitq_p8", "arguments": [ - "uint8x8_t a" + "poly8x16_t a" ], "return_type": { - "value": "float64x1_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.16B" } }, "Architectures": [ @@ -79188,144 +275392,140 @@ ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_f16", + "name": "vrbitq_s8", "arguments": [ - "float16x4_t a" + "int8x16_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_f32", + "name": "vrbitq_u8", "arguments": [ - "float32x2_t a" + "uint8x16_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "RBIT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_f64", + "name": "vrecpe_f16", "arguments": [ - "float64x1_t a" + "float16x4_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_p64", + "name": "vrecpe_f32", "arguments": [ - "poly64x1_t a" + "float32x2_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_p8", + "name": "vrecpe_f64", "arguments": [ - "poly8x8_t a" + "float64x1_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_s16", + "name": "vrecpe_u32", "arguments": [ - "int16x4_t a" + "uint32x2_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.2S" } }, "Architectures": [ @@ -79335,97 +275535,92 @@ ], "instructions": [ [ - "NOP" + "URECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_s32", + "name": "vrecped_f64", "arguments": [ - "int32x2_t a" + "float64_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_s64", + "name": "vrecpeh_f16", "arguments": [ - "int64x1_t a" + "float16_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Hn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_s8", + "name": "vrecpeq_f16", "arguments": [ - "int8x8_t a" + "float16x8_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_u16", + "name": "vrecpeq_f32", "arguments": [ - "uint16x4_t a" + "float32x4_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.4S" } }, "Architectures": [ @@ -79435,47 +275630,45 @@ ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_u32", + "name": "vrecpeq_f64", "arguments": [ - "uint32x2_t a" + "float64x2_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_u64", + "name": "vrecpeq_u32", "arguments": [ - "uint64x1_t a" + "uint32x4_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vn.4S" } }, "Architectures": [ @@ -79485,47 +275678,49 @@ ], "instructions": [ [ - "NOP" + "URECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p16_u8", + "name": "vrecpes_f32", "arguments": [ - "uint8x8_t a" + "float32_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Sn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_f16", + "name": "vrecps_f16", "arguments": [ - "float16x4_t a" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ @@ -79534,46 +275729,55 @@ ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_f32", + "name": "vrecps_f32", "arguments": [ - "float32x2_t a" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_f64", + "name": "vrecps_f64", "arguments": [ - "float64x1_t a" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ @@ -79581,70 +275785,80 @@ ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_p16", + "name": "vrecpsd_f64", "arguments": [ - "poly16x4_t a" + "float64_t a", + "float64_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Dn" + }, + "b": { + "register": "Dm" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_p8", + "name": "vrecpsh_f16", "arguments": [ - "poly8x8_t a" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Hn" + }, + "b": { + "register": "Hm" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_s16", + "name": "vrecpsq_f16", "arguments": [ - "int16x4_t a" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -79653,166 +275867,174 @@ ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_s32", + "name": "vrecpsq_f32", "arguments": [ - "int32x2_t a" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_s8", + "name": "vrecpsq_f64", "arguments": [ - "int8x8_t a" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_u16", + "name": "vrecpss_f32", "arguments": [ - "uint16x4_t a" + "float32_t a", + "float32_t b" ], "return_type": { - "value": "poly64x1_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Sn" + }, + "b": { + "register": "Sm" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_u32", + "name": "vrecpxd_f64", "arguments": [ - "uint32x2_t a" + "float64_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Dn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_u64", + "name": "vrecpxh_f16", "arguments": [ - "uint64x1_t a" + "float16_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Hn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p64_u8", + "name": "vrecpxs_f32", "arguments": [ - "uint8x8_t a" + "float32_t a" ], "return_type": { - "value": "poly64x1_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Sn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "NOP" + "FRECPX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_f16", + "name": "vreinterpret_f16_f32", "arguments": [ - "float16x4_t a" + "float32x2_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -79828,21 +276050,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_f32", + "name": "vreinterpret_f16_f64", "arguments": [ - "float32x2_t a" + "float64x1_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -79853,19 +276073,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_f64", + "name": "vreinterpret_f16_p16", "arguments": [ - "float64x1_t a" + "poly16x4_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -79876,20 +276098,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_p16", + "name": "vreinterpret_f16_p64", "arguments": [ - "poly16x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -79901,19 +276122,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_p64", + "name": "vreinterpret_f16_p8", "arguments": [ - "poly64x1_t a" + "poly8x8_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -79925,12 +276147,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_s16", + "name": "vreinterpret_f16_s16", "arguments": [ "int16x4_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -79950,12 +276172,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_s32", + "name": "vreinterpret_f16_s32", "arguments": [ "int32x2_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -79975,12 +276197,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_s64", + "name": "vreinterpret_f16_s64", "arguments": [ "int64x1_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80000,12 +276222,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_s8", + "name": "vreinterpret_f16_s8", "arguments": [ "int8x8_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80025,12 +276247,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_u16", + "name": "vreinterpret_f16_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80050,12 +276272,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_u32", + "name": "vreinterpret_f16_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80075,12 +276297,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_u64", + "name": "vreinterpret_f16_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80100,12 +276322,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_p8_u8", + "name": "vreinterpret_f16_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { @@ -80125,12 +276347,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_f16", + "name": "vreinterpret_f32_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80150,37 +276372,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_f32", - "arguments": [ - "float32x2_t a" - ], - "return_type": { - "value": "int16x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2S" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_f64", + "name": "vreinterpret_f32_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80198,12 +276395,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_p16", + "name": "vreinterpret_f32_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80223,19 +276420,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_p64", + "name": "vreinterpret_f32_p8", "arguments": [ - "poly64x1_t a" + "poly8x8_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -80247,16 +276445,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_p8", + "name": "vreinterpret_f32_s16", "arguments": [ - "poly8x8_t a" + "int16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -80272,12 +276470,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_s32", + "name": "vreinterpret_f32_s32", "arguments": [ "int32x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80297,12 +276495,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_s64", + "name": "vreinterpret_f32_s64", "arguments": [ "int64x1_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80322,12 +276520,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_s8", + "name": "vreinterpret_f32_s8", "arguments": [ "int8x8_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80347,12 +276545,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_u16", + "name": "vreinterpret_f32_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80372,12 +276570,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_u32", + "name": "vreinterpret_f32_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80397,12 +276595,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_u64", + "name": "vreinterpret_f32_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80422,12 +276620,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s16_u8", + "name": "vreinterpret_f32_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -80447,12 +276645,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_f16", + "name": "vreinterpret_f64_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80460,8 +276658,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80472,12 +276668,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_f32", + "name": "vreinterpret_f64_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80485,8 +276681,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80497,16 +276691,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_f64", + "name": "vreinterpret_f64_p16", "arguments": [ - "float64x1_t a" + "poly16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.4H" } }, "Architectures": [ @@ -80520,21 +276714,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_p16", + "name": "vreinterpret_f64_p64", "arguments": [ - "poly16x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80545,20 +276737,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_p64", + "name": "vreinterpret_f64_p8", "arguments": [ - "poly64x1_t a" + "poly8x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -80569,21 +276760,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_p8", + "name": "vreinterpret_f64_s16", "arguments": [ - "poly8x8_t a" + "int16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80594,21 +276783,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_s16", + "name": "vreinterpret_f64_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80619,12 +276806,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_s64", + "name": "vreinterpret_f64_s64", "arguments": [ "int64x1_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80632,8 +276819,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80644,12 +276829,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_s8", + "name": "vreinterpret_f64_s8", "arguments": [ "int8x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80657,8 +276842,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80669,12 +276852,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_u16", + "name": "vreinterpret_f64_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80682,8 +276865,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80694,12 +276875,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_u32", + "name": "vreinterpret_f64_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80707,8 +276888,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80719,12 +276898,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_u64", + "name": "vreinterpret_f64_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80732,8 +276911,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80744,12 +276921,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s32_u8", + "name": "vreinterpret_f64_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -80757,8 +276934,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -80769,12 +276944,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_f16", + "name": "vreinterpret_p16_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -80794,12 +276969,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_f32", + "name": "vreinterpret_p16_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -80819,12 +276994,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_f64", + "name": "vreinterpret_p16_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -80842,20 +277017,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_p16", + "name": "vreinterpret_p16_p64", "arguments": [ - "poly16x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -80867,19 +277041,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_p64", + "name": "vreinterpret_p16_p8", "arguments": [ - "poly64x1_t a" + "poly8x8_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -80891,16 +277066,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_p8", + "name": "vreinterpret_p16_s16", "arguments": [ - "poly8x8_t a" + "int16x4_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -80916,16 +277091,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_s16", + "name": "vreinterpret_p16_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -80941,16 +277116,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_s32", + "name": "vreinterpret_p16_s64", "arguments": [ - "int32x2_t a" + "int64x1_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -80966,12 +277141,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_s8", + "name": "vreinterpret_p16_s8", "arguments": [ "int8x8_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -80991,12 +277166,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_u16", + "name": "vreinterpret_p16_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81016,12 +277191,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_u32", + "name": "vreinterpret_p16_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81041,12 +277216,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_u64", + "name": "vreinterpret_p16_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81066,12 +277241,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s64_u8", + "name": "vreinterpret_p16_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "int64x1_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { @@ -81091,12 +277266,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_f16", + "name": "vreinterpret_p64_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81104,7 +277279,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81116,12 +277290,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_f32", + "name": "vreinterpret_p64_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81129,7 +277303,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81141,12 +277314,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_f64", + "name": "vreinterpret_p64_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81164,43 +277337,18 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_p16", + "name": "vreinterpret_p64_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { "register": "Vd.4H" } }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_p64", - "arguments": [ - "poly64x1_t a" - ], - "return_type": { - "value": "int8x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.1D" - } - }, "Architectures": [ "A32", "A64" @@ -81213,12 +277361,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_p8", + "name": "vreinterpret_p64_p8", "arguments": [ "poly8x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81226,7 +277374,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81238,12 +277385,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_s16", + "name": "vreinterpret_p64_s16", "arguments": [ "int16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81251,7 +277398,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81263,12 +277409,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_s32", + "name": "vreinterpret_p64_s32", "arguments": [ "int32x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81276,7 +277422,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81288,20 +277433,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_s64", + "name": "vreinterpret_p64_s8", "arguments": [ - "int64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81313,12 +277457,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_u16", + "name": "vreinterpret_p64_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81326,7 +277470,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81338,12 +277481,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_u32", + "name": "vreinterpret_p64_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81351,7 +277494,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81363,12 +277505,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_u64", + "name": "vreinterpret_p64_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81376,7 +277518,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81388,12 +277529,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_s8_u8", + "name": "vreinterpret_p64_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { @@ -81401,7 +277542,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -81413,12 +277553,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_f16", + "name": "vreinterpret_p8_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81438,12 +277578,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_f32", + "name": "vreinterpret_p8_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81463,12 +277603,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_f64", + "name": "vreinterpret_p8_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81486,12 +277626,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_p16", + "name": "vreinterpret_p8_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81511,12 +277651,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_p64", + "name": "vreinterpret_p8_p64", "arguments": [ "poly64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81535,16 +277675,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_p8", + "name": "vreinterpret_p8_s16", "arguments": [ - "poly8x8_t a" + "int16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -81560,16 +277700,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_s16", + "name": "vreinterpret_p8_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -81585,16 +277725,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_s32", + "name": "vreinterpret_p8_s64", "arguments": [ - "int32x2_t a" + "int64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -81610,16 +277750,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_s64", + "name": "vreinterpret_p8_s8", "arguments": [ - "int64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ @@ -81635,16 +277775,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_s8", + "name": "vreinterpret_p8_u16", "arguments": [ - "int8x8_t a" + "uint16x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -81660,12 +277800,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_u32", + "name": "vreinterpret_p8_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81685,12 +277825,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_u64", + "name": "vreinterpret_p8_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81710,12 +277850,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u16_u8", + "name": "vreinterpret_p8_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { @@ -81735,12 +277875,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_f16", + "name": "vreinterpret_s16_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -81760,12 +277900,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_f32", + "name": "vreinterpret_s16_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -81785,12 +277925,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_f64", + "name": "vreinterpret_s16_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -81808,12 +277948,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_p16", + "name": "vreinterpret_s16_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -81833,12 +277973,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_p64", + "name": "vreinterpret_s16_p64", "arguments": [ "poly64x1_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -81857,12 +277997,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_p8", + "name": "vreinterpret_s16_p8", "arguments": [ "poly8x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -81882,16 +278022,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_s16", + "name": "vreinterpret_s16_s32", "arguments": [ - "int16x4_t a" + "int32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -81907,16 +278047,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_s32", + "name": "vreinterpret_s16_s64", "arguments": [ - "int32x2_t a" + "int64x1_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -81932,16 +278072,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_s64", + "name": "vreinterpret_s16_s8", "arguments": [ - "int64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ @@ -81957,16 +278097,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_s8", + "name": "vreinterpret_s16_u16", "arguments": [ - "int8x8_t a" + "uint16x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -81982,16 +278122,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_u16", + "name": "vreinterpret_s16_u32", "arguments": [ - "uint16x4_t a" + "uint32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -82007,12 +278147,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_u64", + "name": "vreinterpret_s16_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82032,12 +278172,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u32_u8", + "name": "vreinterpret_s16_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -82057,12 +278197,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_f16", + "name": "vreinterpret_s32_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82082,12 +278222,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_f32", + "name": "vreinterpret_s32_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82107,12 +278247,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_f64", + "name": "vreinterpret_s32_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82130,12 +278270,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_p16", + "name": "vreinterpret_s32_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82155,12 +278295,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_p64", + "name": "vreinterpret_s32_p64", "arguments": [ "poly64x1_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82179,12 +278319,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_p8", + "name": "vreinterpret_s32_p8", "arguments": [ "poly8x8_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82204,12 +278344,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_s16", + "name": "vreinterpret_s32_s16", "arguments": [ "int16x4_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82229,16 +278369,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_s32", + "name": "vreinterpret_s32_s64", "arguments": [ - "int32x2_t a" + "int64x1_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -82254,16 +278394,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_s64", + "name": "vreinterpret_s32_s8", "arguments": [ - "int64x1_t a" + "int8x8_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1D" + "register": "Vd.8B" } }, "Architectures": [ @@ -82279,16 +278419,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_s8", + "name": "vreinterpret_s32_u16", "arguments": [ - "int8x8_t a" + "uint16x4_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vd.4H" } }, "Architectures": [ @@ -82304,16 +278444,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_u16", + "name": "vreinterpret_s32_u32", "arguments": [ - "uint16x4_t a" + "uint32x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vd.2S" } }, "Architectures": [ @@ -82329,16 +278469,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_u32", + "name": "vreinterpret_s32_u64", "arguments": [ - "uint32x2_t a" + "uint64x1_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vd.1D" } }, "Architectures": [ @@ -82354,12 +278494,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u64_u8", + "name": "vreinterpret_s32_u8", "arguments": [ "uint8x8_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -82379,12 +278519,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_f16", + "name": "vreinterpret_s64_f16", "arguments": [ "float16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82404,12 +278544,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_f32", + "name": "vreinterpret_s64_f32", "arguments": [ "float32x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82429,12 +278569,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_f64", + "name": "vreinterpret_s64_f64", "arguments": [ "float64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82452,12 +278592,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_p16", + "name": "vreinterpret_s64_p16", "arguments": [ "poly16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82477,12 +278617,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_p64", + "name": "vreinterpret_s64_p64", "arguments": [ "poly64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82501,12 +278641,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_p8", + "name": "vreinterpret_s64_p8", "arguments": [ "poly8x8_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82526,12 +278666,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_s16", + "name": "vreinterpret_s64_s16", "arguments": [ "int16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82551,12 +278691,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_s32", + "name": "vreinterpret_s64_s32", "arguments": [ "int32x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82576,37 +278716,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_s64", - "arguments": [ - "int64x1_t a" - ], - "return_type": { - "value": "uint8x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.1D" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_s8", + "name": "vreinterpret_s64_s8", "arguments": [ "int8x8_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82626,12 +278741,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_u16", + "name": "vreinterpret_s64_u16", "arguments": [ "uint16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82651,12 +278766,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_u32", + "name": "vreinterpret_s64_u32", "arguments": [ "uint32x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82676,12 +278791,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpret_u8_u64", + "name": "vreinterpret_s64_u64", "arguments": [ "uint64x1_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { @@ -82701,16 +278816,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_f32", + "name": "vreinterpret_s64_u8", "arguments": [ - "float32x4_t a" + "uint8x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -82726,42 +278841,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_f64", - "arguments": [ - "float64x2_t a" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_p128", + "name": "vreinterpret_s8_f16", "arguments": [ - "poly128_t a" + "float16x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -82773,16 +278866,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_p16", + "name": "vreinterpret_s8_f32", "arguments": [ - "poly16x8_t a" + "float32x2_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ @@ -82798,20 +278891,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_p64", + "name": "vreinterpret_s8_f64", "arguments": [ - "poly64x2_t a" + "float64x1_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -82822,16 +278914,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_p8", + "name": "vreinterpret_s8_p16", "arguments": [ - "poly8x16_t a" + "poly16x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ @@ -82847,20 +278939,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_s16", + "name": "vreinterpret_s8_p64", "arguments": [ - "int16x8_t a" + "poly64x1_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -82872,16 +278963,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_s32", + "name": "vreinterpret_s8_p8", "arguments": [ - "int32x4_t a" + "poly8x8_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -82897,16 +278988,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_s64", + "name": "vreinterpret_s8_s16", "arguments": [ - "int64x2_t a" + "int16x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ @@ -82922,16 +279013,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_s8", + "name": "vreinterpret_s8_s32", "arguments": [ - "int8x16_t a" + "int32x2_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ @@ -82947,16 +279038,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_u16", + "name": "vreinterpret_s8_s64", "arguments": [ - "uint16x8_t a" + "int64x1_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ @@ -82972,16 +279063,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_u32", + "name": "vreinterpret_s8_u16", "arguments": [ - "uint32x4_t a" + "uint16x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.4H" } }, "Architectures": [ @@ -82997,16 +279088,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_u64", + "name": "vreinterpret_s8_u32", "arguments": [ - "uint64x2_t a" + "uint32x2_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.2S" } }, "Architectures": [ @@ -83022,16 +279113,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f16_u8", + "name": "vreinterpret_s8_u64", "arguments": [ - "uint8x16_t a" + "uint64x1_t a" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.1D" } }, "Architectures": [ @@ -83047,16 +279138,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_f16", + "name": "vreinterpret_s8_u8", "arguments": [ - "float16x8_t a" + "uint8x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.8B" } }, "Architectures": [ @@ -83072,39 +279163,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_f64", - "arguments": [ - "float64x2_t a" - ], - "return_type": { - "value": "float32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_p16", + "name": "vreinterpret_u16_f16", "arguments": [ - "poly16x8_t a" + "float16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ @@ -83120,16 +279188,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_p8", + "name": "vreinterpret_u16_f32", "arguments": [ - "poly8x16_t a" + "float32x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ @@ -83145,21 +279213,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_s16", + "name": "vreinterpret_u16_f64", "arguments": [ - "int16x8_t a" + "float64x1_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -83170,16 +279236,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_s32", + "name": "vreinterpret_u16_p16", "arguments": [ - "int32x4_t a" + "poly16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.4H" } }, "Architectures": [ @@ -83195,20 +279261,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_s64", + "name": "vreinterpret_u16_p64", "arguments": [ - "int64x2_t a" + "poly64x1_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -83220,16 +279285,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_s8", + "name": "vreinterpret_u16_p8", "arguments": [ - "int8x16_t a" + "poly8x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8B" } }, "Architectures": [ @@ -83245,16 +279310,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_u16", + "name": "vreinterpret_u16_s16", "arguments": [ - "uint16x8_t a" + "int16x4_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ @@ -83270,16 +279335,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_u32", + "name": "vreinterpret_u16_s32", "arguments": [ - "uint32x4_t a" + "int32x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2S" } }, "Architectures": [ @@ -83295,16 +279360,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_u64", + "name": "vreinterpret_u16_s64", "arguments": [ - "uint64x2_t a" + "int64x1_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1D" } }, "Architectures": [ @@ -83320,16 +279385,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f32_u8", + "name": "vreinterpret_u16_s8", "arguments": [ - "uint8x16_t a" + "int8x8_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8B" } }, "Architectures": [ @@ -83345,19 +279410,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_f16", + "name": "vreinterpret_u16_u32", "arguments": [ - "float16x8_t a" + "uint32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83368,19 +279435,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_f32", + "name": "vreinterpret_u16_u64", "arguments": [ - "float32x4_t a" + "uint64x1_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83391,19 +279460,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_p128", + "name": "vreinterpret_u16_u8", "arguments": [ - "poly128_t a" + "uint8x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83414,19 +279485,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_p16", + "name": "vreinterpret_u32_f16", "arguments": [ - "poly16x8_t a" + "float16x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83437,19 +279510,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_p64", + "name": "vreinterpret_u32_f32", "arguments": [ - "poly64x2_t a" + "float32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83460,16 +279535,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_p8", + "name": "vreinterpret_u32_f64", "arguments": [ - "poly8x16_t a" + "float64x1_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.1D" } }, "Architectures": [ @@ -83483,19 +279558,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_s16", + "name": "vreinterpret_u32_p16", "arguments": [ - "int16x8_t a" + "poly16x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83506,19 +279583,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_s32", + "name": "vreinterpret_u32_p64", "arguments": [ - "int32x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ @@ -83529,19 +279607,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_s64", + "name": "vreinterpret_u32_p8", "arguments": [ - "int64x2_t a" + "poly8x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83552,19 +279632,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_s8", + "name": "vreinterpret_u32_s16", "arguments": [ - "int8x16_t a" + "int16x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83575,19 +279657,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_u16", + "name": "vreinterpret_u32_s32", "arguments": [ - "uint16x8_t a" + "int32x2_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83598,19 +279682,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_u32", + "name": "vreinterpret_u32_s64", "arguments": [ - "uint32x4_t a" + "int64x1_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83621,16 +279707,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_u64", + "name": "vreinterpret_u32_s8", "arguments": [ - "uint64x2_t a" + "int8x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8B" } }, "Architectures": [ @@ -83646,19 +279732,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_f64_u8", + "name": "vreinterpret_u32_u16", "arguments": [ - "uint8x16_t a" + "uint16x4_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83669,19 +279757,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_f16", + "name": "vreinterpret_u32_u64", "arguments": [ - "float16x8_t a" + "uint64x1_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83693,19 +279782,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_f32", + "name": "vreinterpret_u32_u8", "arguments": [ - "float32x4_t a" + "uint8x8_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83717,19 +279807,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_f64", + "name": "vreinterpret_u64_f16", "arguments": [ - "float64x2_t a" + "float16x4_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -83740,19 +279832,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_p16", + "name": "vreinterpret_u64_f32", "arguments": [ - "poly16x8_t a" + "float32x2_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83764,20 +279857,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_p8", + "name": "vreinterpret_u64_f64", "arguments": [ - "poly8x16_t a" + "float64x1_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -83788,19 +279880,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_s16", + "name": "vreinterpret_u64_p16", "arguments": [ - "int16x8_t a" + "poly16x4_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83812,16 +279905,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_s32", + "name": "vreinterpret_u64_p64", "arguments": [ - "int32x4_t a" + "poly64x1_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ @@ -83836,19 +279929,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_s64", + "name": "vreinterpret_u64_p8", "arguments": [ - "int64x2_t a" + "poly8x8_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83860,19 +279954,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_s8", + "name": "vreinterpret_u64_s16", "arguments": [ - "int8x16_t a" + "int16x4_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83884,19 +279979,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_u16", + "name": "vreinterpret_u64_s32", "arguments": [ - "uint16x8_t a" + "int32x2_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83908,19 +280004,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_u32", + "name": "vreinterpret_u64_s64", "arguments": [ - "uint32x4_t a" + "int64x1_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83932,19 +280029,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_u64", + "name": "vreinterpret_u64_s8", "arguments": [ - "uint64x2_t a" + "int8x8_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83956,19 +280054,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p128_u8", + "name": "vreinterpret_u64_u16", "arguments": [ - "uint8x16_t a" + "uint16x4_t a" ], "return_type": { - "value": "poly128_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -83980,16 +280079,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_f16", + "name": "vreinterpret_u64_u32", "arguments": [ - "float16x8_t a" + "uint32x2_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" } }, "Architectures": [ @@ -84005,16 +280104,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_f32", + "name": "vreinterpret_u64_u8", "arguments": [ - "float32x4_t a" + "uint8x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -84030,19 +280129,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_f64", + "name": "vreinterpret_u8_f16", "arguments": [ - "float64x2_t a" + "float16x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -84053,19 +280154,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_p128", + "name": "vreinterpret_u8_f32", "arguments": [ - "poly128_t a" + "float32x2_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84077,20 +280179,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_p64", + "name": "vreinterpret_u8_f64", "arguments": [ - "poly64x2_t a" + "float64x1_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -84101,16 +280202,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_p8", + "name": "vreinterpret_u8_p16", "arguments": [ - "poly8x16_t a" + "poly16x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" } }, "Architectures": [ @@ -84126,20 +280227,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_s16", + "name": "vreinterpret_u8_p64", "arguments": [ - "int16x8_t a" + "poly64x1_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -84151,16 +280251,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_s32", + "name": "vreinterpret_u8_p8", "arguments": [ - "int32x4_t a" + "poly8x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -84176,16 +280276,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_s64", + "name": "vreinterpret_u8_s16", "arguments": [ - "int64x2_t a" + "int16x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ @@ -84201,16 +280301,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_s8", + "name": "vreinterpret_u8_s32", "arguments": [ - "int8x16_t a" + "int32x2_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ @@ -84226,16 +280326,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_u16", + "name": "vreinterpret_u8_s64", "arguments": [ - "uint16x8_t a" + "int64x1_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ @@ -84251,16 +280351,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_u32", + "name": "vreinterpret_u8_s8", "arguments": [ - "uint32x4_t a" + "int8x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8B" } }, "Architectures": [ @@ -84276,16 +280376,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_u64", + "name": "vreinterpret_u8_u16", "arguments": [ - "uint64x2_t a" + "uint16x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4H" } }, "Architectures": [ @@ -84301,16 +280401,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p16_u8", + "name": "vreinterpret_u8_u32", "arguments": [ - "uint8x16_t a" + "uint32x2_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2S" } }, "Architectures": [ @@ -84326,19 +280426,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_f16", + "name": "vreinterpret_u8_u64", "arguments": [ - "float16x8_t a" + "uint64x1_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84350,12 +280451,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_f32", + "name": "vreinterpretq_f16_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { @@ -84363,6 +280464,7 @@ } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84374,12 +280476,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_f64", + "name": "vreinterpretq_f16_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { @@ -84397,16 +280499,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_p16", + "name": "vreinterpretq_f16_p128", "arguments": [ - "poly16x8_t a" + "poly128_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.1Q" } }, "Architectures": [ @@ -84421,19 +280523,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_p8", + "name": "vreinterpretq_f16_p16", "arguments": [ - "poly8x16_t a" + "poly16x8_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84445,16 +280548,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_s16", + "name": "vreinterpretq_f16_p64", "arguments": [ - "int16x8_t a" + "poly64x2_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ @@ -84469,19 +280572,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_s32", + "name": "vreinterpretq_f16_p8", "arguments": [ - "int32x4_t a" + "poly8x16_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84493,19 +280597,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_s64", + "name": "vreinterpretq_f16_s16", "arguments": [ - "int64x2_t a" + "int16x8_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84517,19 +280622,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_s8", + "name": "vreinterpretq_f16_s32", "arguments": [ - "int8x16_t a" + "int32x4_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84541,19 +280647,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_u16", + "name": "vreinterpretq_f16_s64", "arguments": [ - "uint16x8_t a" + "int64x2_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84565,19 +280672,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_u32", + "name": "vreinterpretq_f16_s8", "arguments": [ - "uint32x4_t a" + "int8x16_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84589,19 +280697,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_u64", + "name": "vreinterpretq_f16_u16", "arguments": [ - "uint64x2_t a" + "uint16x8_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84613,19 +280722,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p64_u8", + "name": "vreinterpretq_f16_u32", "arguments": [ - "uint8x16_t a" + "uint32x4_t a" ], "return_type": { - "value": "poly64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84637,16 +280747,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_f16", + "name": "vreinterpretq_f16_u64", "arguments": [ - "float16x8_t a" + "uint64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ @@ -84662,16 +280772,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_f32", + "name": "vreinterpretq_f16_u8", "arguments": [ - "float32x4_t a" + "uint8x16_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.16B" } }, "Architectures": [ @@ -84687,19 +280797,21 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_f64", + "name": "vreinterpretq_f32_f16", "arguments": [ - "float64x2_t a" + "float16x8_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -84710,20 +280822,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_p128", + "name": "vreinterpretq_f32_f64", "arguments": [ - "poly128_t a" + "float64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -84734,12 +280845,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_p16", + "name": "vreinterpretq_f32_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84759,19 +280870,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_p64", + "name": "vreinterpretq_f32_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -84783,12 +280895,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_s16", + "name": "vreinterpretq_f32_s16", "arguments": [ "int16x8_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84808,12 +280920,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_s32", + "name": "vreinterpretq_f32_s32", "arguments": [ "int32x4_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84833,12 +280945,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_s64", + "name": "vreinterpretq_f32_s64", "arguments": [ "int64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84858,12 +280970,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_s8", + "name": "vreinterpretq_f32_s8", "arguments": [ "int8x16_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84883,12 +280995,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_u16", + "name": "vreinterpretq_f32_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84908,12 +281020,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_u32", + "name": "vreinterpretq_f32_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84933,12 +281045,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_u64", + "name": "vreinterpretq_f32_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84958,12 +281070,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_p8_u8", + "name": "vreinterpretq_f32_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { @@ -84983,12 +281095,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_f16", + "name": "vreinterpretq_f64_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -84996,8 +281108,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85008,12 +281118,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_f32", + "name": "vreinterpretq_f64_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85021,8 +281131,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85033,16 +281141,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_f64", + "name": "vreinterpretq_f64_p128", "arguments": [ - "float64x2_t a" + "poly128_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1Q" } }, "Architectures": [ @@ -85056,20 +281164,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_p128", + "name": "vreinterpretq_f64_p16", "arguments": [ - "poly128_t a" + "poly16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.1Q" + "register": "Vd.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -85080,21 +281187,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_p16", + "name": "vreinterpretq_f64_p64", "arguments": [ - "poly16x8_t a" + "poly64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85105,20 +281210,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_p64", + "name": "vreinterpretq_f64_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -85129,21 +281233,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_p8", + "name": "vreinterpretq_f64_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85154,12 +281256,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_s32", + "name": "vreinterpretq_f64_s32", "arguments": [ "int32x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85167,8 +281269,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85179,12 +281279,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_s64", + "name": "vreinterpretq_f64_s64", "arguments": [ "int64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85192,8 +281292,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85204,12 +281302,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_s8", + "name": "vreinterpretq_f64_s8", "arguments": [ "int8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85217,8 +281315,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85229,12 +281325,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_u16", + "name": "vreinterpretq_f64_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85242,8 +281338,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85254,12 +281348,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_u32", + "name": "vreinterpretq_f64_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85267,8 +281361,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85279,12 +281371,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_u64", + "name": "vreinterpretq_f64_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85304,12 +281396,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s16_u8", + "name": "vreinterpretq_f64_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { @@ -85317,8 +281409,6 @@ } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -85329,12 +281419,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_f16", + "name": "vreinterpretq_p128_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85342,7 +281432,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85354,12 +281443,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_f32", + "name": "vreinterpretq_p128_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85367,7 +281456,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85379,35 +281467,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_f64", + "name": "vreinterpretq_p128_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "int32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_p128", - "arguments": [ - "poly128_t a" - ], - "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85415,7 +281480,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -85426,12 +281490,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_p16", + "name": "vreinterpretq_p128_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85439,7 +281503,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85451,16 +281514,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_p64", + "name": "vreinterpretq_p128_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -85475,20 +281538,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_p8", + "name": "vreinterpretq_p128_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85500,20 +281562,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_s16", + "name": "vreinterpretq_p128_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85525,20 +281586,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_s64", + "name": "vreinterpretq_p128_s64", "arguments": [ "int64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85550,12 +281610,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_s8", + "name": "vreinterpretq_p128_s8", "arguments": [ "int8x16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85563,7 +281623,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85575,12 +281634,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_u16", + "name": "vreinterpretq_p128_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85588,7 +281647,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85600,12 +281658,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_u32", + "name": "vreinterpretq_p128_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85613,7 +281671,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85625,20 +281682,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_u64", + "name": "vreinterpretq_p128_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85650,12 +281706,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s32_u8", + "name": "vreinterpretq_p128_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "int32x4_t" + "value": "poly128_t" }, "Arguments_Preparation": { "a": { @@ -85663,7 +281719,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85675,12 +281730,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_f16", + "name": "vreinterpretq_p16_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -85700,12 +281755,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_f32", + "name": "vreinterpretq_p16_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -85725,12 +281780,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_f64", + "name": "vreinterpretq_p16_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -85748,12 +281803,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_p128", + "name": "vreinterpretq_p16_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -85772,20 +281827,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_p16", + "name": "vreinterpretq_p16_p64", "arguments": [ - "poly16x8_t a" + "poly64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -85797,19 +281851,20 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_p64", + "name": "vreinterpretq_p16_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -85821,16 +281876,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_p8", + "name": "vreinterpretq_p16_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -85846,16 +281901,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_s16", + "name": "vreinterpretq_p16_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -85871,16 +281926,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_s32", + "name": "vreinterpretq_p16_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -85896,12 +281951,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_s8", + "name": "vreinterpretq_p16_s8", "arguments": [ "int8x16_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -85921,12 +281976,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_u16", + "name": "vreinterpretq_p16_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -85946,12 +282001,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_u32", + "name": "vreinterpretq_p16_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -85971,12 +282026,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_u64", + "name": "vreinterpretq_p16_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -85996,12 +282051,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s64_u8", + "name": "vreinterpretq_p16_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { @@ -86021,12 +282076,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_f16", + "name": "vreinterpretq_p64_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86034,7 +282089,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86046,12 +282100,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_f32", + "name": "vreinterpretq_p64_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86059,7 +282113,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86071,12 +282124,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_f64", + "name": "vreinterpretq_p64_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86094,36 +282147,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_p128", - "arguments": [ - "poly128_t a" - ], - "return_type": { - "value": "int8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.1Q" - } - }, - "Architectures": [ - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_p16", + "name": "vreinterpretq_p64_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86131,7 +282160,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86143,16 +282171,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_p64", + "name": "vreinterpretq_p64_p8", "arguments": [ - "poly64x2_t a" + "poly8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -86167,20 +282195,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_p8", + "name": "vreinterpretq_p64_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86192,20 +282219,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_s16", + "name": "vreinterpretq_p64_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86217,20 +282243,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_s32", + "name": "vreinterpretq_p64_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86242,20 +282267,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_s64", + "name": "vreinterpretq_p64_s8", "arguments": [ - "int64x2_t a" + "int8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86267,12 +282291,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_u16", + "name": "vreinterpretq_p64_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86280,7 +282304,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86292,12 +282315,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_u32", + "name": "vreinterpretq_p64_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86305,7 +282328,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86317,12 +282339,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_u64", + "name": "vreinterpretq_p64_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86330,7 +282352,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86342,12 +282363,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_s8_u8", + "name": "vreinterpretq_p64_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { @@ -86355,7 +282376,6 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -86367,12 +282387,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_f16", + "name": "vreinterpretq_p8_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86392,12 +282412,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_f32", + "name": "vreinterpretq_p8_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86417,12 +282437,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_f64", + "name": "vreinterpretq_p8_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86440,12 +282460,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_p128", + "name": "vreinterpretq_p8_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86464,12 +282484,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_p16", + "name": "vreinterpretq_p8_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86489,12 +282509,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_p64", + "name": "vreinterpretq_p8_p64", "arguments": [ "poly64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86513,16 +282533,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_p8", + "name": "vreinterpretq_p8_s16", "arguments": [ - "poly8x16_t a" + "int16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -86538,16 +282558,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_s16", + "name": "vreinterpretq_p8_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -86563,16 +282583,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_s32", + "name": "vreinterpretq_p8_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -86588,16 +282608,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_s64", + "name": "vreinterpretq_p8_s8", "arguments": [ - "int64x2_t a" + "int8x16_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -86613,16 +282633,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_s8", + "name": "vreinterpretq_p8_u16", "arguments": [ - "int8x16_t a" + "uint16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -86638,12 +282658,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_u32", + "name": "vreinterpretq_p8_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86663,12 +282683,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_u64", + "name": "vreinterpretq_p8_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86688,12 +282708,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u16_u8", + "name": "vreinterpretq_p8_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { @@ -86713,12 +282733,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_f16", + "name": "vreinterpretq_s16_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -86738,12 +282758,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_f32", + "name": "vreinterpretq_s16_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -86763,12 +282783,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_f64", + "name": "vreinterpretq_s16_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -86786,12 +282806,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_p128", + "name": "vreinterpretq_s16_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -86810,12 +282830,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_p16", + "name": "vreinterpretq_s16_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -86835,12 +282855,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_p64", + "name": "vreinterpretq_s16_p64", "arguments": [ "poly64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -86859,12 +282879,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_p8", + "name": "vreinterpretq_s16_p8", "arguments": [ "poly8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -86884,16 +282904,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_s16", + "name": "vreinterpretq_s16_s32", "arguments": [ - "int16x8_t a" + "int32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -86909,16 +282929,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_s32", + "name": "vreinterpretq_s16_s64", "arguments": [ - "int32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -86934,16 +282954,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_s64", + "name": "vreinterpretq_s16_s8", "arguments": [ - "int64x2_t a" + "int8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.16B" } }, "Architectures": [ @@ -86959,16 +282979,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_s8", + "name": "vreinterpretq_s16_u16", "arguments": [ - "int8x16_t a" + "uint16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.8H" } }, "Architectures": [ @@ -86984,16 +283004,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_u16", + "name": "vreinterpretq_s16_u32", "arguments": [ - "uint16x8_t a" + "uint32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.4S" } }, "Architectures": [ @@ -87009,12 +283029,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_u64", + "name": "vreinterpretq_s16_u64", "arguments": [ "uint64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87034,12 +283054,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u32_u8", + "name": "vreinterpretq_s16_u8", "arguments": [ "uint8x16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -87059,12 +283079,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_f16", + "name": "vreinterpretq_s32_f16", "arguments": [ "float16x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87084,12 +283104,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_f32", + "name": "vreinterpretq_s32_f32", "arguments": [ "float32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87109,12 +283129,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_f64", + "name": "vreinterpretq_s32_f64", "arguments": [ "float64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87132,12 +283152,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_p128", + "name": "vreinterpretq_s32_p128", "arguments": [ "poly128_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87156,12 +283176,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_p16", + "name": "vreinterpretq_s32_p16", "arguments": [ "poly16x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87181,12 +283201,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_p64", + "name": "vreinterpretq_s32_p64", "arguments": [ "poly64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87205,12 +283225,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_p8", + "name": "vreinterpretq_s32_p8", "arguments": [ "poly8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87230,12 +283250,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_s16", + "name": "vreinterpretq_s32_s16", "arguments": [ "int16x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87255,37 +283275,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_s32", - "arguments": [ - "int32x4_t a" - ], - "return_type": { - "value": "uint64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_s64", + "name": "vreinterpretq_s32_s64", "arguments": [ "int64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87305,12 +283300,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_s8", + "name": "vreinterpretq_s32_s8", "arguments": [ "int8x16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87330,12 +283325,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_u16", + "name": "vreinterpretq_s32_u16", "arguments": [ "uint16x8_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87355,12 +283350,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_u32", + "name": "vreinterpretq_s32_u32", "arguments": [ "uint32x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -87380,41 +283375,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u64_u8", - "arguments": [ - "uint8x16_t a" - ], - "return_type": { - "value": "uint64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_f16", + "name": "vreinterpretq_s32_u64", "arguments": [ - "float16x8_t a" + "uint64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ @@ -87430,16 +283400,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_f32", + "name": "vreinterpretq_s32_u8", "arguments": [ - "float32x4_t a" + "uint8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.16B" } }, "Architectures": [ @@ -87455,59 +283425,12 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_f64", - "arguments": [ - "float64x2_t a" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_p128", - "arguments": [ - "poly128_t a" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.1Q" - } - }, - "Architectures": [ - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_p16", + "name": "vreinterpretq_s64_f16", "arguments": [ - "poly16x8_t a" + "float16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -87527,40 +283450,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_p64", - "arguments": [ - "poly64x2_t a" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.2D" - } - }, - "Architectures": [ - "A32", - "A64" - ], - "instructions": [ - [ - "NOP" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_p8", + "name": "vreinterpretq_s64_f32", "arguments": [ - "poly8x16_t a" + "float32x4_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4S" } }, "Architectures": [ @@ -87576,21 +283475,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_s16", + "name": "vreinterpretq_s64_f64", "arguments": [ - "int16x8_t a" + "float64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -87601,20 +283498,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_s32", + "name": "vreinterpretq_s64_p128", "arguments": [ - "int32x4_t a" + "poly128_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -87626,16 +283522,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_s64", + "name": "vreinterpretq_s64_p16", "arguments": [ - "int64x2_t a" + "poly16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8H" } }, "Architectures": [ @@ -87651,20 +283547,19 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_s8", + "name": "vreinterpretq_s64_p64", "arguments": [ - "int8x16_t a" + "poly64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -87676,16 +283571,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_u16", + "name": "vreinterpretq_s64_p8", "arguments": [ - "uint16x8_t a" + "poly8x16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -87701,16 +283596,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_u32", + "name": "vreinterpretq_s64_s16", "arguments": [ - "uint32x4_t a" + "int16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vd.8H" } }, "Architectures": [ @@ -87726,16 +283621,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vreinterpretq_u8_u64", + "name": "vreinterpretq_s64_s32", "arguments": [ - "uint64x2_t a" + "int32x4_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.4S" } }, "Architectures": [ @@ -87751,16 +283646,16 @@ }, { "SIMD_ISA": "Neon", - "name": "vrev16_p8", + "name": "vreinterpretq_s64_s8", "arguments": [ - "poly8x8_t vec" + "int8x16_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -87770,22 +283665,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16_s8", + "name": "vreinterpretq_s64_u16", "arguments": [ - "int8x8_t vec" + "uint16x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -87795,22 +283690,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16_u8", + "name": "vreinterpretq_s64_u32", "arguments": [ - "uint8x8_t vec" + "uint32x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -87820,22 +283715,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16q_p8", + "name": "vreinterpretq_s64_u64", "arguments": [ - "poly8x16_t vec" + "uint64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -87845,22 +283740,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16q_s8", + "name": "vreinterpretq_s64_u8", "arguments": [ - "int8x16_t vec" + "uint8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -87870,22 +283765,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev16q_u8", + "name": "vreinterpretq_s8_f16", "arguments": [ - "uint8x16_t vec" + "float16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -87895,22 +283790,22 @@ ], "instructions": [ [ - "REV16" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_p16", + "name": "vreinterpretq_s8_f32", "arguments": [ - "poly16x4_t vec" + "float32x4_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -87920,72 +283815,69 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_p8", + "name": "vreinterpretq_s8_f64", "arguments": [ - "poly8x8_t vec" + "float64x2_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_s16", + "name": "vreinterpretq_s8_p128", "arguments": [ - "int16x4_t vec" + "poly128_t a" ], "return_type": { - "value": "int16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_s8", + "name": "vreinterpretq_s8_p16", "arguments": [ - "int8x8_t vec" + "poly16x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -87995,47 +283887,46 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_u16", + "name": "vreinterpretq_s8_p64", "arguments": [ - "uint16x4_t vec" + "poly64x2_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32_u8", + "name": "vreinterpretq_s8_p8", "arguments": [ - "uint8x8_t vec" + "poly8x16_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88045,22 +283936,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_p16", + "name": "vreinterpretq_s8_s16", "arguments": [ - "poly16x8_t vec" + "int16x8_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88070,22 +283961,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_p8", + "name": "vreinterpretq_s8_s32", "arguments": [ - "poly8x16_t vec" + "int32x4_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88095,22 +283986,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_s16", + "name": "vreinterpretq_s8_s64", "arguments": [ - "int16x8_t vec" + "int64x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -88120,22 +284011,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_s8", + "name": "vreinterpretq_s8_u16", "arguments": [ - "int8x16_t vec" + "uint16x8_t a" ], "return_type": { "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88145,22 +284036,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_u16", + "name": "vreinterpretq_s8_u32", "arguments": [ - "uint16x8_t vec" + "uint32x4_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88170,22 +284061,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev32q_u8", + "name": "vreinterpretq_s8_u64", "arguments": [ - "uint8x16_t vec" + "uint64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -88195,22 +284086,22 @@ ], "instructions": [ [ - "REV32" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_f16", + "name": "vreinterpretq_s8_u8", "arguments": [ - "float16x4_t vec" + "uint8x16_t a" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88220,22 +284111,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_f32", + "name": "vreinterpretq_u16_f16", "arguments": [ - "float32x2_t vec" + "float16x8_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.2S" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88245,22 +284136,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_p16", + "name": "vreinterpretq_u16_f32", "arguments": [ - "poly16x4_t vec" + "float32x4_t a" ], "return_type": { - "value": "poly16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88270,72 +284161,69 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_p8", + "name": "vreinterpretq_u16_f64", "arguments": [ - "poly8x8_t vec" + "float64x2_t a" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_s16", + "name": "vreinterpretq_u16_p128", "arguments": [ - "int16x4_t vec" + "poly128_t a" ], "return_type": { - "value": "int16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_s32", + "name": "vreinterpretq_u16_p16", "arguments": [ - "int32x2_t vec" + "poly16x8_t a" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.2S" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88345,47 +284233,46 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_s8", + "name": "vreinterpretq_u16_p64", "arguments": [ - "int8x8_t vec" + "poly64x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_u16", + "name": "vreinterpretq_u16_p8", "arguments": [ - "uint16x4_t vec" + "poly8x16_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4H" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88395,22 +284282,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_u32", + "name": "vreinterpretq_u16_s16", "arguments": [ - "uint32x2_t vec" + "int16x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.2S" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88420,22 +284307,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64_u8", + "name": "vreinterpretq_u16_s32", "arguments": [ - "uint8x8_t vec" + "int32x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8B" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88445,22 +284332,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_f16", + "name": "vreinterpretq_u16_s64", "arguments": [ - "float16x8_t vec" + "int64x2_t a" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -88470,22 +284357,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_f32", + "name": "vreinterpretq_u16_s8", "arguments": [ - "float32x4_t vec" + "int8x16_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4S" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88495,22 +284382,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_p16", + "name": "vreinterpretq_u16_u32", "arguments": [ - "poly16x8_t vec" + "uint32x4_t a" ], "return_type": { - "value": "poly16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88520,22 +284407,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_p8", + "name": "vreinterpretq_u16_u64", "arguments": [ - "poly8x16_t vec" + "uint64x2_t a" ], "return_type": { - "value": "poly8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.2D" } }, "Architectures": [ @@ -88545,22 +284432,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_s16", + "name": "vreinterpretq_u16_u8", "arguments": [ - "int16x8_t vec" + "uint8x16_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.16B" } }, "Architectures": [ @@ -88570,22 +284457,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_s32", + "name": "vreinterpretq_u32_f16", "arguments": [ - "int32x4_t vec" + "float16x8_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4S" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88595,22 +284482,22 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_s8", + "name": "vreinterpretq_u32_f32", "arguments": [ - "int8x16_t vec" + "float32x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.4S" } }, "Architectures": [ @@ -88620,72 +284507,69 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_u16", + "name": "vreinterpretq_u32_f64", "arguments": [ - "uint16x8_t vec" + "float64x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.8H" + "a": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_u32", + "name": "vreinterpretq_u32_p128", "arguments": [ - "uint32x4_t vec" + "poly128_t a" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.4S" + "a": { + "register": "Vd.1Q" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrev64q_u8", + "name": "vreinterpretq_u32_p16", "arguments": [ - "uint8x16_t vec" + "poly16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "vec": { - "register": "Vn.16B" + "a": { + "register": "Vd.8H" } }, "Architectures": [ @@ -88695,55 +284579,46 @@ ], "instructions": [ [ - "REV64" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_s16", + "name": "vreinterpretq_u32_p64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "poly64x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vd.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_s32", + "name": "vreinterpretq_u32_p8", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "poly8x16_t a" ], "return_type": { - "value": "int32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vd.16B" } }, "Architectures": [ @@ -88753,26 +284628,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_s8", + "name": "vreinterpretq_u32_s16", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int16x8_t a" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vd.8H" } }, "Architectures": [ @@ -88782,26 +284653,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_u16", + "name": "vreinterpretq_u32_s32", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int32x4_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" + "register": "Vd.4S" } }, "Architectures": [ @@ -88811,26 +284678,22 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_u32", + "name": "vreinterpretq_u32_s64", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int64x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" + "register": "Vd.2D" } }, "Architectures": [ @@ -88840,26 +284703,22 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhadd_u8", + "name": "vreinterpretq_u32_s8", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "int8x16_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.8B" + "register": "Vd.16B" } }, "Architectures": [ @@ -88869,26 +284728,22 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_s16", + "name": "vreinterpretq_u32_u16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vd.8H" } }, "Architectures": [ @@ -88898,26 +284753,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_s32", + "name": "vreinterpretq_u32_u64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint64x2_t a" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vd.2D" } }, "Architectures": [ @@ -88927,26 +284778,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_s8", + "name": "vreinterpretq_u32_u8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint8x16_t a" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vd.16B" } }, "Architectures": [ @@ -88956,26 +284803,22 @@ ], "instructions": [ [ - "SRHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_u16", + "name": "vreinterpretq_u64_f16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "float16x8_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vd.8H" } }, "Architectures": [ @@ -88985,26 +284828,22 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_u32", + "name": "vreinterpretq_u64_f32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "float32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vd.4S" } }, "Architectures": [ @@ -89014,350 +284853,368 @@ ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrhaddq_u8", + "name": "vreinterpretq_u64_f64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "float64x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URHADD" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32x_f32", + "name": "vreinterpretq_u64_p128", "arguments": [ - "float32x2_t a" + "poly128_t a" ], "return_type": { - "value": "float32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.1Q" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRINT32X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32x_f64", + "name": "vreinterpretq_u64_p16", "arguments": [ - "float64x1_t a" + "poly16x8_t a" ], "return_type": { - "value": "float64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32X" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32xq_f32", + "name": "vreinterpretq_u64_p64", "arguments": [ - "float32x4_t a" + "poly64x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.2D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRINT32X" + "NOP" ] ] }, { "SIMD_ISA": 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"register": "Vd.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32zq_f32", + "name": "vreinterpretq_u64_s64", "arguments": [ - "float32x4_t a" + "int64x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd32zq_f64", + "name": "vreinterpretq_u64_s8", "arguments": [ - "float64x2_t a" + "int8x16_t a" ], "return_type": { - "value": "float64x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn" + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINT32Z" + "NOP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrnd64x_f32", + "name": "vreinterpretq_u64_u16", "arguments": [ - "float32x2_t a" + "uint16x8_t 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"vec": { + "register": "Vn.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndp_f64", + "name": "vrev64_u32", "arguments": [ - "float64x1_t a" + "uint32x2_t vec" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "vec": { + "register": "Vn.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndph_f16", + "name": "vrev64_u8", "arguments": [ - "float16_t a" + "uint8x8_t vec" ], "return_type": { - "value": "float16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "vec": { + "register": "Vn.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndpq_f16", + "name": "vrev64q_f16", "arguments": [ - "float16x8_t a" + "float16x8_t vec" ], "return_type": { "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { + "vec": { "register": "Vn.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndpq_f32", + "name": "vrev64q_f32", "arguments": [ - "float32x4_t a" + "float32x4_t vec" ], "return_type": { "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { + "vec": { "register": "Vn.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndpq_f64", + "name": "vrev64q_p16", "arguments": [ - "float64x2_t a" + "poly16x8_t vec" ], "return_type": { - "value": "float64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "vec": { + "register": "Vn.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTP" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndq_f16", + "name": "vrev64q_p8", "arguments": [ - "float16x8_t a" + "poly8x16_t vec" ], "return_type": { - "value": "float16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "vec": { + "register": "Vn.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTZ" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndq_f32", + "name": "vrev64q_s16", "arguments": [ - "float32x4_t a" + "int16x8_t vec" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "vec": { + "register": "Vn.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTZ" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndq_f64", + "name": "vrev64q_s32", "arguments": [ - "float64x2_t a" + "int32x4_t vec" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "vec": { + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTZ" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndx_f16", + "name": "vrev64q_s8", "arguments": [ - "float16x4_t a" + "int8x16_t vec" ], "return_type": { - "value": "float16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "vec": { + "register": "Vn.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTX" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndx_f32", + "name": "vrev64q_u16", "arguments": [ - "float32x2_t a" + "uint16x8_t vec" ], "return_type": { - "value": "float32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "vec": { + "register": "Vn.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTX" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndx_f64", + "name": "vrev64q_u32", "arguments": [ - "float64x1_t a" + "uint32x4_t vec" ], "return_type": { - "value": "float64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "vec": { + "register": "Vn.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTX" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndxh_f16", + "name": "vrev64q_u8", "arguments": [ - "float16_t a" + "uint8x16_t vec" ], "return_type": { - "value": "float16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "vec": { + "register": "Vn.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTX" + "REV64" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndxq_f16", + "name": "vrhadd_s16", "arguments": [ - "float16x8_t a" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTX" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndxq_f32", + "name": "vrhadd_s32", "arguments": [ - "float32x4_t a" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FRINTX" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrndxq_f64", + "name": "vrhadd_s8", "arguments": [ - "float64x2_t a" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FRINTX" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_s16", + "name": "vrhadd_u16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { @@ -90626,19 +286561,19 @@ ], "instructions": [ [ - "SRSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_s32", + "name": "vrhadd_u32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { @@ -90655,26 +286590,26 @@ ], "instructions": [ [ - "SRSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_s64", + "name": "vrhadd_u8", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8B" }, "b": { - "register": "Dm" + "register": "Vm.8B" } }, "Architectures": [ @@ -90684,26 +286619,26 @@ ], "instructions": [ [ - "SRSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_s8", + "name": "vrhaddq_s16", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { - "register": "Vm.8B" + "register": "Vm.8H" } }, "Architectures": [ @@ -90713,26 +286648,26 @@ ], "instructions": [ [ - "SRSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_u16", + "name": "vrhaddq_s32", "arguments": [ - "uint16x4_t a", - "int16x4_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, "b": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -90742,26 +286677,26 @@ ], "instructions": [ [ - "URSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_u32", + "name": "vrhaddq_s8", "arguments": [ - "uint32x2_t a", - "int32x2_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.16B" }, "b": { - "register": "Vm.2S" + "register": "Vm.16B" } }, "Architectures": [ @@ -90771,26 +286706,26 @@ ], "instructions": [ [ - "URSHL" + "SRHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_u64", + "name": "vrhaddq_u16", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "uint64x1_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.8H" }, "b": { - "register": "Dm" + "register": "Vm.8H" } }, "Architectures": [ @@ -90800,26 +286735,26 @@ ], "instructions": [ [ - "URSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshl_u8", + "name": "vrhaddq_u32", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, "b": { - "register": "Vm.8B" + "register": "Vm.4S" } }, "Architectures": [ @@ -90829,53 +286764,51 @@ ], "instructions": [ [ - "URSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshld_s64", + "name": "vrhaddq_u8", "arguments": [ - "int64_t a", - "int64_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int64_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.16B" }, "b": { - "register": "Dm" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SRSHL" + "URHADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshld_u64", + "name": "vrnd32x_f32", "arguments": [ - "uint64_t a", - "int64_t b" + "float32x2_t a" ], "return_type": { - "value": "uint64_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Vn" } }, "Architectures": [ @@ -90883,527 +286816,415 @@ ], "instructions": [ [ - "URSHL" + "FRINT32X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_s16", + "name": "vrnd32x_f64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float64x1_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHL" + "FRINT32X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_s32", + "name": "vrnd32xq_f32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHL" + "FRINT32X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_s64", + "name": "vrnd32xq_f64", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "float64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHL" + "FRINT32X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_s8", + "name": "vrnd32z_f32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "float32x2_t a" ], "return_type": { - "value": "int8x16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHL" + "FRINT32Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_u16", + "name": "vrnd32z_f64", "arguments": [ - "uint16x8_t a", - "int16x8_t b" + "float64x1_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHL" + "FRINT32Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_u32", + "name": "vrnd32zq_f32", "arguments": [ - "uint32x4_t a", - "int32x4_t b" + "float32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHL" + "FRINT32Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_u64", + "name": "vrnd32zq_f64", "arguments": [ - "uint64x2_t a", - "int64x2_t b" + "float64x2_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHL" + "FRINT32Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshlq_u8", + "name": "vrnd64x_f32", "arguments": [ - "uint8x16_t a", - "int8x16_t b" + "float32x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm.16B" + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHL" + "FRINT64X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_s16", + "name": "vrnd64x_f64", "arguments": [ - "int16x4_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINT64X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_s32", + "name": "vrnd64xq_f32", "arguments": [ - "int32x2_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINT64X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_s64", + "name": "vrnd64xq_f64", "arguments": [ - "int64x1_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINT64X" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_s8", + "name": "vrnd64z_f32", "arguments": [ - "int8x8_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINT64Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_u16", + "name": "vrnd64z_f64", "arguments": [ - "uint16x4_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINT64Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_u32", + "name": "vrnd64zq_f32", "arguments": [ - "uint32x2_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINT64Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_u64", + "name": "vrnd64zq_f64", "arguments": [ - "uint64x1_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINT64Z" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshr_n_u8", + "name": "vrnd_f16", "arguments": [ - "uint8x8_t a", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrd_n_s64", + "name": "vrnd_f32", "arguments": [ - "int64_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "int64_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrd_n_u64", + "name": "vrnd_f64", "arguments": [ - "uint64_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "uint64_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 } }, "Architectures": [ @@ -91411,95 +287232,70 @@ ], "instructions": [ [ - "URSHR" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_s16", + "name": "vrnda_f16", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 - }, - "r": { - "register": "Vd.8B" + "register": "Vn.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RSHRN2" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_s32", + "name": "vrnda_f32", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 - }, - "r": { - "register": "Vd.4H" + "register": "Vn.2S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RSHRN2" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_s64", + "name": "vrnda_f64", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 - }, - "r": { - "register": "Vd.2S" + "register": "Dn" } }, "Architectures": [ @@ -91507,538 +287303,424 @@ ], "instructions": [ [ - "RSHRN2" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_u16", + "name": "vrndah_f16", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "const int n" + "float16_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 - }, - "r": { - "register": "Vd.8B" + "register": "Hn" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RSHRN2" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_u32", + "name": "vrndaq_f16", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 - }, - "r": { - "register": "Vd.4H" + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RSHRN2" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_high_n_u64", + "name": "vrndaq_f32", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 - }, - "r": { - "register": "32(Vd)" + "register": "Vn.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "RSHRN2" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_s16", + "name": "vrndaq_f64", "arguments": [ - "int16x8_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "int8x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_s32", + "name": "vrndh_f16", "arguments": [ - "int32x4_t a", - "const int n" + "float16_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_s64", + "name": "vrndi_f16", "arguments": [ - "int64x2_t a", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_u16", + "name": "vrndi_f32", "arguments": [ - "uint16x8_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_u32", + "name": "vrndi_f64", "arguments": [ - "uint32x4_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrn_n_u64", + "name": "vrndih_f16", "arguments": [ - "uint64x2_t a", - "const int n" + "float16_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "RSHRN" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_s16", + "name": "vrndiq_f16", "arguments": [ - "int16x8_t a", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "int16x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 16 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_s32", + "name": "vrndiq_f32", "arguments": [ - "int32x4_t a", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "int32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 32 } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_s64", + "name": "vrndiq_f64", "arguments": [ - "int64x2_t a", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "int64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_s8", + "name": "vrndm_f16", "arguments": [ - "int8x16_t a", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "int8x16_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSHR" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_u16", + "name": "vrndm_f32", "arguments": [ - "uint16x8_t a", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "uint16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vn.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_u32", + "name": "vrndm_f64", "arguments": [ - "uint32x4_t a", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_u64", + "name": "vrndmh_f16", "arguments": [ - "uint64x2_t a", - "const int n" + "float16_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrshrq_n_u8", + "name": "vrndmq_f16", "arguments": [ - "uint8x16_t a", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSHR" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrte_f16", + "name": "vrndmq_f32", "arguments": [ - "float16x4_t a" + "float32x4_t a" ], "return_type": { - "value": "float16x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" } }, "Architectures": [ @@ -92047,66 +287729,65 @@ ], "instructions": [ [ - "FRSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrte_f32", + "name": "vrndmq_f64", "arguments": [ - "float32x2_t a" + "float64x2_t a" ], "return_type": { - "value": "float32x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTM" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrte_f64", + "name": "vrndn_f16", "arguments": [ - "float64x1_t a" + "float16x4_t a" ], "return_type": { - "value": "float64x1_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.4H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrte_u32", + "name": "vrndn_f32", "arguments": [ - "uint32x2_t a" + "float32x2_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { @@ -92114,24 +287795,23 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrted_f64", + "name": "vrndn_f64", "arguments": [ - "float64_t a" + "float64x1_t a" ], "return_type": { - "value": "float64_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { @@ -92139,17 +287819,18 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteh_f16", + "name": "vrndnh_f16", "arguments": [ "float16_t a" ], @@ -92162,17 +287843,18 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteq_f16", + "name": "vrndnq_f16", "arguments": [ "float16x8_t a" ], @@ -92190,13 +287872,13 @@ ], "instructions": [ [ - "FRSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteq_f32", + "name": "vrndnq_f32", "arguments": [ "float32x4_t a" ], @@ -92209,19 +287891,18 @@ } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrteq_f64", + "name": "vrndnq_f64", "arguments": [ "float64x2_t a" ], @@ -92234,42 +287915,18 @@ } }, "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FRSQRTE" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vrsqrteq_u32", - "arguments": [ - "uint32x4_t a" - ], - "return_type": { - "value": "uint32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - } - }, - "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtes_f32", + "name": "vrndns_f32", "arguments": [ "float32_t a" ], @@ -92282,20 +287939,20 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTE" + "FRINTN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrts_f16", + "name": "vrndp_f16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "float16x4_t a" ], "return_type": { "value": "float16x4_t" @@ -92303,9 +287960,6 @@ "Arguments_Preparation": { "a": { "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" } }, "Architectures": [ @@ -92314,16 +287968,15 @@ ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrts_f32", + "name": "vrndp_f32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "float32x2_t a" ], "return_type": { "value": "float32x2_t" @@ -92331,28 +287984,23 @@ "Arguments_Preparation": { "a": { "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrts_f64", + "name": "vrndp_f64", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "float64x1_t a" ], "return_type": { "value": "float64x1_t" @@ -92360,9 +288008,6 @@ "Arguments_Preparation": { "a": { "register": "Dn" - }, - "b": { - "register": "Dm" } }, "Architectures": [ @@ -92370,80 +288015,70 @@ ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsd_f64", + "name": "vrndph_f16", "arguments": [ - "float64_t a", - "float64_t b" + "float16_t a" ], "return_type": { - "value": "float64_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" - }, - "b": { - "register": "Dm" + "register": "Hn" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsh_f16", + "name": "vrndpq_f16", "arguments": [ - "float16_t a", - "float16_t b" + "float16x8_t a" ], "return_type": { - "value": "float16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" - }, - "b": { - "register": "Hm" + "register": "Vn.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsq_f16", + "name": "vrndpq_f32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "float32x4_t a" ], "return_type": { - "value": "float16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" + "register": "Vn.4S" } }, "Architectures": [ @@ -92452,450 +288087,344 @@ ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsq_f32", + "name": "vrndpq_f64", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "float64x2_t a" ], "return_type": { - "value": "float32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTP" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtsq_f64", + "name": "vrndq_f16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "float16x8_t a" ], "return_type": { - "value": "float64x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" + "register": "Vn.8H" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsqrtss_f32", + "name": "vrndq_f32", "arguments": [ - "float32_t a", - "float32_t b" + "float32x4_t a" ], "return_type": { - "value": "float32_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Sn" - }, - "b": { - "register": "Sm" + "register": "Vn.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "FRSQRTS" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_s16", + "name": "vrndq_f64", "arguments": [ - "int16x4_t a", - "int16x4_t b", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "int16x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTZ" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_s32", + "name": "vrndx_f16", "arguments": [ - "int32x2_t a", - "int32x2_t b", - "const int n" + "float16x4_t a" ], "return_type": { - "value": "int32x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_s64", + "name": "vrndx_f32", "arguments": [ - "int64x1_t a", - "int64x1_t b", - "const int n" + "float32x2_t a" ], "return_type": { - "value": "int64x1_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_s8", + "name": "vrndx_f64", "arguments": [ - "int8x8_t a", - "int8x8_t b", - "const int n" + "float64x1_t a" ], "return_type": { - "value": "int8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_u16", + "name": "vrndxh_f16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", - "const int n" + "float16_t a" ], "return_type": { - "value": "uint16x4_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_u32", + "name": "vrndxq_f16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", - "const int n" + "float16x8_t a" ], "return_type": { - "value": "uint32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vn.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_u64", + "name": "vrndxq_f32", "arguments": [ - "uint64x1_t a", - "uint64x1_t b", - "const int n" + "float32x4_t a" ], "return_type": { - "value": "uint64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "URSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsra_n_u8", + "name": "vrndxq_f64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "const int n" + "float64x2_t a" ], "return_type": { - "value": "uint8x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSRA" + "FRINTX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsrad_n_s64", + "name": "vrshl_s16", "arguments": [ - "int64_t a", - "int64_t b", - "const int n" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int64_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.4H" }, "b": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SRSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsrad_n_u64", + "name": "vrshl_s32", "arguments": [ - "uint64_t a", - "uint64_t b", - "const int n" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2S" }, "b": { - "register": "Dn" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "URSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_s16", + "name": "vrshl_s64", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "const int n" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dn" }, "b": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Dm" } }, "Architectures": [ @@ -92905,31 +288434,26 @@ ], "instructions": [ [ - "SRSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_s32", + "name": "vrshl_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "const int n" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8B" }, "b": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vm.8B" } }, "Architectures": [ @@ -92939,31 +288463,26 @@ ], "instructions": [ [ - "SRSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_s64", + "name": "vrshl_u16", "arguments": [ - "int64x2_t a", - "int64x2_t b", - "const int n" + "uint16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.4H" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Vm.4H" } }, "Architectures": [ @@ -92973,31 +288492,26 @@ ], "instructions": [ [ - "SRSRA" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_s8", + "name": "vrshl_u32", "arguments": [ - "int8x16_t a", - "int8x16_t b", - "const int n" + "uint32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.2S" }, "b": { - "register": "Vn.16B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Vm.2S" } }, "Architectures": [ @@ -93007,31 +288521,26 @@ ], "instructions": [ [ - "SRSRA" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_u16", + "name": "vrshl_u64", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", - "const int n" + "uint64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dn" }, "b": { - "register": "Vn.8H" - }, - "n": { - "minimum": 1, - "maximum": 16 + "register": "Dm" } }, "Architectures": [ @@ -93041,31 +288550,26 @@ ], "instructions": [ [ - "URSRA" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_u32", + "name": "vrshl_u8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "const int n" + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8B" }, "b": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 32 + "register": "Vm.8B" } }, "Architectures": [ @@ -93075,88 +288579,73 @@ ], "instructions": [ [ - "URSRA" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_u64", + "name": "vrshld_s64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "const int n" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dn" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 1, - "maximum": 64 + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSRA" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsraq_n_u8", + "name": "vrshld_u64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "const int n" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Dn" }, "b": { - "register": "Vn.16B" - }, - "n": { - "minimum": 1, - "maximum": 8 + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "URSRA" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_s16", + "name": "vrshlq_s16", "arguments": [ - "int8x8_t r", "int16x8_t a", "int16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -93164,30 +288653,28 @@ }, "b": { "register": "Vm.8H" - }, - "r": { - "register": "Vd.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_s32", + "name": "vrshlq_s32", "arguments": [ - "int16x4_t r", "int32x4_t a", "int32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -93195,30 +288682,28 @@ }, "b": { "register": "Vm.4S" - }, - "r": { - "register": "Vd.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_s64", + "name": "vrshlq_s64", "arguments": [ - "int32x2_t r", "int64x2_t a", "int64x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -93226,129 +288711,122 @@ }, "b": { "register": "Vm.2D" - }, - "r": { - "register": "Vd.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_u16", + "name": "vrshlq_s8", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "uint16x8_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" - }, - "r": { - "register": "Vd.8B" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "SRSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_u32", + "name": "vrshlq_u16", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "uint32x4_t b" + "uint16x8_t a", + "int16x8_t b" ], "return_type": { "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8H" }, "b": { - "register": "Vm.4S" - }, - "r": { - "register": "Vd.4H" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_high_u64", + "name": "vrshlq_u32", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "uint64x2_t b" + "uint32x4_t a", + "int32x4_t b" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" - }, - "r": { - "register": "Vd.2S" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "RSUBHN2" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_s16", + "name": "vrshlq_u64", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, "b": { - "register": "Vm.8H" + "register": "Vm.2D" } }, "Architectures": [ @@ -93358,26 +288836,26 @@ ], "instructions": [ [ - "RSUBHN" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_s32", + "name": "vrshlq_u8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int16x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.16B" } }, "Architectures": [ @@ -93387,26 +288865,27 @@ ], "instructions": [ [ - "RSUBHN" + "URSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_s64", + "name": "vrshr_n_s16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int16x4_t a", + "const int n" ], "return_type": { - "value": "int32x2_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4H" }, - "b": { - "register": "Vm.2D" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -93416,26 +288895,27 @@ ], "instructions": [ [ - "RSUBHN" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_u16", + "name": "vrshr_n_s32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int32x2_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, - "b": { - "register": "Vm.8H" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -93445,26 +288925,27 @@ ], "instructions": [ [ - "RSUBHN" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_u32", + "name": "vrshr_n_s64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int64x1_t a", + "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Dn" }, - "b": { - "register": "Vm.4S" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -93474,26 +288955,27 @@ ], "instructions": [ [ - "RSUBHN" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vrsubhn_u64", + "name": "vrshr_n_s8", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int8x8_t a", + "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8B" }, - "b": { - "register": "Vm.2D" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -93503,31 +288985,27 @@ ], "instructions": [ [ - "RSUBHN" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_f16", + "name": "vrshr_n_u16", "arguments": [ - "float16_t a", - "float16x4_t v", - "const int lane" + "uint16x4_t a", + "const int n" ], "return_type": { - "value": "float16x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "VnH" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.4H" }, - "v": { - "register": "Vd.4H" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -93537,31 +289015,27 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_f32", + "name": "vrshr_n_u32", "arguments": [ - "float32_t a", - "float32x2_t v", - "const int lane" + "uint32x2_t a", + "const int n" ], "return_type": { - "value": "float32x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.2S" }, - "v": { - "register": "Vd.2S" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -93571,63 +289045,57 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_f64", + "name": "vrshr_n_u64", "arguments": [ - "float64_t a", - "float64x1_t v", - "const int lane" + "uint64x1_t a", + "const int n" ], "return_type": { - "value": "float64x1_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Dn" }, - "v": { - "register": "Vd.1D" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_p16", + "name": "vrshr_n_u8", "arguments": [ - "poly16_t a", - "poly16x4_t v", - "const int lane" + "uint8x8_t a", + "const int n" ], "return_type": { - "value": "poly16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.8B" }, - "v": { - "register": "Vd.4H" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -93637,302 +289105,275 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_p64", + "name": "vrshrd_n_s64", "arguments": [ - "poly64_t a", - "poly64x1_t v", - "const int lane" + "int64_t a", + "const int n" ], "return_type": { - "value": "poly64x1_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Dn" }, - "v": { - "register": "Vd.1D" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_p8", + "name": "vrshrd_n_u64", "arguments": [ - "poly8_t a", - "poly8x8_t v", - "const int lane" + "uint64_t a", + "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Dn" }, - "v": { - "register": "Vd.8B" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_s16", + "name": "vrshrn_high_n_s16", "arguments": [ - "int16_t a", - "int16x4_t v", - "const int lane" + "int8x8_t r", + "int16x8_t a", + "const int n" ], "return_type": { - "value": "int16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.8H" }, - "lane": { - "minimum": 0, - "maximum": 3 + "n": { + "minimum": 1, + "maximum": 8 }, - "v": { - "register": "Vd.4H" + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_s32", + "name": "vrshrn_high_n_s32", "arguments": [ - "int32_t a", - "int32x2_t v", - "const int lane" + "int16x4_t r", + "int32x4_t a", + "const int n" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 1 + "n": { + "minimum": 1, + "maximum": 16 }, - "v": { - "register": "Vd.2S" + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_s64", + "name": "vrshrn_high_n_s64", "arguments": [ - "int64_t a", - "int64x1_t v", - "const int lane" + "int32x2_t r", + "int64x2_t a", + "const int n" ], "return_type": { - "value": "int64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.2D" }, - "lane": { - "minimum": 0, - "maximum": 0 + "n": { + "minimum": 1, + "maximum": 32 }, - "v": { - "register": "Vd.1D" + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_s8", + "name": "vrshrn_high_n_u16", "arguments": [ - "int8_t a", - "int8x8_t v", - "const int lane" + "uint8x8_t r", + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.8H" }, - "lane": { - "minimum": 0, - "maximum": 7 + "n": { + "minimum": 1, + "maximum": 8 }, - "v": { + "r": { "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_u16", + "name": "vrshrn_high_n_u32", "arguments": [ - "uint16_t a", - "uint16x4_t v", - "const int lane" + "uint16x4_t r", + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.4S" }, - "lane": { - "minimum": 0, - "maximum": 3 + "n": { + "minimum": 1, + "maximum": 16 }, - "v": { + "r": { "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_u32", + "name": "vrshrn_high_n_u64", "arguments": [ - "uint32_t a", - "uint32x2_t v", - "const int lane" + "uint32x2_t r", + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" + "register": "Vn.2D" }, - "lane": { - "minimum": 0, - "maximum": 1 + "n": { + "minimum": 1, + "maximum": 32 }, - "v": { - "register": "Vd.2S" + "r": { + "register": "32(Vd)" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_u64", + "name": "vrshrn_n_s16", "arguments": [ - "uint64_t a", - "uint64x1_t v", - "const int lane" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 0 + "register": "Vn.8H" }, - "v": { - "register": "Vd.1D" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -93942,31 +289383,27 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vset_lane_u8", + "name": "vrshrn_n_s32", "arguments": [ - "uint8_t a", - "uint8x8_t v", - "const int lane" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.4S" }, - "v": { - "register": "Vd.8B" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -93976,31 +289413,27 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_f16", + "name": "vrshrn_n_s64", "arguments": [ - "float16_t a", - "float16x8_t v", - "const int lane" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "float16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "VnH" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.2D" }, - "v": { - "register": "Vd.8H" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -94010,31 +289443,27 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_f32", + "name": "vrshrn_n_u16", "arguments": [ - "float32_t a", - "float32x4_t v", - "const int lane" + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "float32x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.8H" }, - "v": { - "register": "Vd.4S" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -94044,63 +289473,57 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_f64", + "name": "vrshrn_n_u32", "arguments": [ - "float64_t a", - "float64x2_t v", - "const int lane" + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "float64x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.4S" }, - "v": { - "register": "Vd.2D" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_p16", + "name": "vrshrn_n_u64", "arguments": [ - "poly16_t a", - "poly16x8_t v", - "const int lane" + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "poly16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.2D" }, - "v": { - "register": "Vd.8H" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -94110,64 +289533,57 @@ ], "instructions": [ [ - "MOV" + "RSHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_p64", + "name": "vrshrq_n_s16", "arguments": [ - "poly64_t a", - "poly64x2_t v", - "const int lane" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "poly64x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.8H" }, - "v": { - "register": "Vd.2D" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_p8", + "name": "vrshrq_n_s32", "arguments": [ - "poly8_t a", - "poly8x16_t v", - "const int lane" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 15 + "register": "Vn.4S" }, - "v": { - "register": "Vd.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -94177,31 +289593,27 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_s16", + "name": "vrshrq_n_s64", "arguments": [ - "int16_t a", - "int16x8_t v", - "const int lane" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.2D" }, - "v": { - "register": "Vd.8H" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -94211,31 +289623,27 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_s32", + "name": "vrshrq_n_s8", "arguments": [ - "int32_t a", - "int32x4_t v", - "const int lane" + "int8x16_t a", + "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.16B" }, - "v": { - "register": "Vd.4S" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -94245,31 +289653,27 @@ ], "instructions": [ [ - "MOV" + "SRSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_s64", + "name": "vrshrq_n_u16", "arguments": [ - "int64_t a", - "int64x2_t v", - "const int lane" + "uint16x8_t a", + "const int n" ], "return_type": { - "value": "int64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 + "register": "Vn.8H" }, - "v": { - "register": "Vd.2D" + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -94279,31 +289683,27 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_s8", + "name": "vrshrq_n_u32", "arguments": [ - "int8_t a", - "int8x16_t v", - "const int lane" + "uint32x4_t a", + "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 15 + "register": "Vn.4S" }, - "v": { - "register": "Vd.16B" + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -94313,31 +289713,27 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_u16", + "name": "vrshrq_n_u64", "arguments": [ - "uint16_t a", - "uint16x8_t v", - "const int lane" + "uint64x2_t a", + "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 7 + "register": "Vn.2D" }, - "v": { - "register": "Vd.8H" + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -94347,31 +289743,27 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_u32", + "name": "vrshrq_n_u8", "arguments": [ - "uint32_t a", - "uint32x4_t v", - "const int lane" + "uint8x16_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 3 + "register": "Vn.16B" }, - "v": { - "register": "Vd.4S" + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -94381,65 +289773,46 @@ ], "instructions": [ [ - "MOV" + "URSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_u64", + "name": "vrsqrte_f16", "arguments": [ - "uint64_t a", - "uint64x2_t v", - "const int lane" + "float16x4_t a" ], "return_type": { - "value": "uint64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "v": { - "register": "Vd.2D" + "register": "Vn.4H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MOV" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsetq_lane_u8", + "name": "vrsqrte_f32", "arguments": [ - "uint8_t a", - "uint8x16_t v", - "const int lane" + "float32x2_t a" ], "return_type": { - "value": "uint8x16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Rn" - }, - "lane": { - "minimum": 0, - "maximum": 15 - }, - "v": { - "register": "Vd.16B" + "register": "Vn.2S" } }, "Architectures": [ @@ -94449,150 +289822,116 @@ ], "instructions": [ [ - "MOV" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1cq_u32", + "name": "vrsqrte_f64", "arguments": [ - "uint32x4_t hash_abcd", - "uint32_t hash_e", - "uint32x4_t wk" + "float64x1_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qd" - }, - "hash_e": { - "register": "Sn" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Dn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SHA1C" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1h_u32", + "name": "vrsqrte_u32", "arguments": [ - "uint32_t hash_e" + "uint32x2_t a" ], "return_type": { - "value": "uint32_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "hash_e": { - "register": "Sn" + "a": { + "register": "Vn.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SHA1H" + "URSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1mq_u32", + "name": "vrsqrted_f64", "arguments": [ - "uint32x4_t hash_abcd", - "uint32_t hash_e", - "uint32x4_t wk" + "float64_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qd" - }, - "hash_e": { - "register": "Sn" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Dn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SHA1M" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1pq_u32", + "name": "vrsqrteh_f16", "arguments": [ - "uint32x4_t hash_abcd", - "uint32_t hash_e", - "uint32x4_t wk" + "float16_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qd" - }, - "hash_e": { - "register": "Sn" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Hn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SHA1P" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1su0q_u32", + "name": "vrsqrteq_f16", "arguments": [ - "uint32x4_t w0_3", - "uint32x4_t w4_7", - "uint32x4_t w8_11" + "float16x8_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "w0_3": { - "register": "Vd.4S" - }, - "w4_7": { - "register": "Vn.4S" - }, - "w8_11": { - "register": "Vm.4S" + "a": { + "register": "Vn.8H" } }, "Architectures": [ @@ -94601,150 +289940,122 @@ ], "instructions": [ [ - "SHA1SU0" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha1su1q_u32", + "name": "vrsqrteq_f32", "arguments": [ - "uint32x4_t tw0_3", - "uint32x4_t w12_15" + "float32x4_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "tw0_3": { - "register": "Vd.4S" - }, - "w12_15": { + "a": { "register": "Vn.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SHA1SU1" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha256h2q_u32", + "name": "vrsqrteq_f64", "arguments": [ - "uint32x4_t hash_efgh", - "uint32x4_t hash_abcd", - "uint32x4_t wk" + "float64x2_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qn" - }, - "hash_efgh": { - "register": "Qd" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Vn.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SHA256H2" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha256hq_u32", + "name": "vrsqrteq_u32", "arguments": [ - "uint32x4_t hash_abcd", - "uint32x4_t hash_efgh", - "uint32x4_t wk" + "uint32x4_t a" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { - "hash_abcd": { - "register": "Qd" - }, - "hash_efgh": { - "register": "Qn" - }, - "wk": { - "register": "Vm.4S" + "a": { + "register": "Vn.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SHA256H" + "URSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha256su0q_u32", + "name": "vrsqrtes_f32", "arguments": [ - "uint32x4_t w0_3", - "uint32x4_t w4_7" + "float32_t a" ], "return_type": { - "value": "uint32x4_t" + "value": "float32_t" }, "Arguments_Preparation": { - "w0_3": { - "register": "Vd.4S" - }, - "w4_7": { - "register": "Vn.4S" + "a": { + "register": "Sn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SHA256SU0" + "FRSQRTE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha256su1q_u32", + "name": "vrsqrts_f16", "arguments": [ - "uint32x4_t tw0_3", - "uint32x4_t w8_11", - "uint32x4_t w12_15" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "tw0_3": { - "register": "Vd.4S" - }, - "w12_15": { - "register": "Vm.4S" + "a": { + "register": "Vn.4H" }, - "w8_11": { - "register": "Vn.4S" + "b": { + "register": "Vm.4H" } }, "Architectures": [ @@ -94753,84 +290064,82 @@ ], "instructions": [ [ - "SHA256SU1" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha512h2q_u64", + "name": "vrsqrts_f32", "arguments": [ - "uint64x2_t sum_ab", - "uint64x2_t hash_c_", - "uint64x2_t hash_ab" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "hash_ab": {}, - "hash_c_": { - "register": "Qn" + "a": { + "register": "Vn.2S" }, - "sum_ab": { - "register": "Qd" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHA512H2" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha512hq_u64", + "name": "vrsqrts_f64", "arguments": [ - "uint64x2_t hash_ed", - "uint64x2_t hash_gf", - "uint64x2_t kwh_kwh2" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "hash_ed": { - "register": "Qd" - }, - "hash_gf": { - "register": "Qn" + "a": { + "register": "Dn" }, - "kwh_kwh2": {} + "b": { + "register": "Dm" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "SHA512H" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha512su0q_u64", + "name": "vrsqrtsd_f64", "arguments": [ - "uint64x2_t w0_1", - "uint64x2_t w2_" + "float64_t a", + "float64_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float64_t" }, "Arguments_Preparation": { - "w0_1": { - "register": "Vd.2D" + "a": { + "register": "Dn" }, - "w2_": { - "register": "Vn.2D" + "b": { + "register": "Dm" } }, "Architectures": [ @@ -94838,86 +290147,81 @@ ], "instructions": [ [ - "SHA512SU0" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsha512su1q_u64", + "name": "vrsqrtsh_f16", "arguments": [ - "uint64x2_t s01_s02", - "uint64x2_t w14_15", - "uint64x2_t w9_10" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "float16_t" }, "Arguments_Preparation": { - "s01_s02": { - "register": "Vd.2D" - }, - "w14_15": { - "register": "Vn.2D" + "a": { + "register": "Hn" }, - "w9_10": {} + "b": { + "register": "Hm" + } }, "Architectures": [ "A64" ], "instructions": [ [ - "SHA512SU1" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_s16", + "name": "vrsqrtsq_f16", "arguments": [ - "int16x4_t a", - "const int n" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int16x4_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.8H" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_s32", + "name": "vrsqrtsq_f32", "arguments": [ - "int32x2_t a", - "const int n" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -94927,87 +290231,85 @@ ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_s64", + "name": "vrsqrtsq_f64", "arguments": [ - "int64x1_t a", - "const int n" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int64x1_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_s8", + "name": "vrsqrtss_f32", "arguments": [ - "int8x8_t a", - "const int n" + "float32_t a", + "float32_t b" ], "return_type": { - "value": "int8x8_t" + "value": "float32_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Sn" }, - "n": { - "minimum": 0, - "maximum": 7 + "b": { + "register": "Sm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FRSQRTS" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_u16", + "name": "vrsra_n_s16", "arguments": [ - "uint16x4_t a", + "int16x4_t a", + "int16x4_t b", "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.4H" + }, + "b": { "register": "Vn.4H" }, "n": { - "minimum": 0, - "maximum": 15 + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -95017,27 +290319,31 @@ ], "instructions": [ [ - "SHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_u32", + "name": "vrsra_n_s32", "arguments": [ - "uint32x2_t a", + "int32x2_t a", + "int32x2_t b", "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.2S" + }, + "b": { "register": "Vn.2S" }, "n": { - "minimum": 0, - "maximum": 31 + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -95047,27 +290353,31 @@ ], "instructions": [ [ - "SHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_u64", + "name": "vrsra_n_s64", "arguments": [ - "uint64x1_t a", + "int64x1_t a", + "int64x1_t b", "const int n" ], "return_type": { - "value": "uint64x1_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { + "register": "Dd" + }, + "b": { "register": "Dn" }, "n": { - "minimum": 0, - "maximum": 63 + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -95077,27 +290387,31 @@ ], "instructions": [ [ - "SHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_n_u8", + "name": "vrsra_n_s8", "arguments": [ - "uint8x8_t a", + "int8x8_t a", + "int8x8_t b", "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.8B" + }, + "b": { "register": "Vn.8B" }, "n": { - "minimum": 0, - "maximum": 7 + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -95107,26 +290421,31 @@ ], "instructions": [ [ - "SHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_s16", + "name": "vrsra_n_u16", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint16x4_t a", + "uint16x4_t b", + "const int n" ], "return_type": { - "value": "int16x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vd.4H" }, "b": { - "register": "Vm.4H" + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -95136,26 +290455,31 @@ ], "instructions": [ [ - "SSHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_s32", + "name": "vrsra_n_u32", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint32x2_t a", + "uint32x2_t b", + "const int n" ], "return_type": { - "value": "int32x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vd.2S" }, "b": { - "register": "Vm.2S" + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -95165,26 +290489,31 @@ ], "instructions": [ [ - "SSHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_s64", + "name": "vrsra_n_u64", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "uint64x1_t a", + "uint64x1_t b", + "const int n" ], "return_type": { - "value": "int64x1_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Dd" }, "b": { - "register": "Dm" + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -95194,26 +290523,31 @@ ], "instructions": [ [ - "SSHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_s8", + "name": "vrsra_n_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8_t a", + "uint8x8_t b", + "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.8B" }, "b": { - "register": "Vm.8B" + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -95223,84 +290557,95 @@ ], "instructions": [ [ - "SSHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_u16", + "name": "vrsrad_n_s64", "arguments": [ - "uint16x4_t a", - "int16x4_t b" + "int64_t a", + "int64_t b", + "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dd" }, "b": { - "register": "Vm.4H" + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_u32", + "name": "vrsrad_n_u64", "arguments": [ - "uint32x2_t a", - "int32x2_t b" + "uint64_t a", + "uint64_t b", + "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dd" }, "b": { - "register": "Vm.2S" + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_u64", + "name": "vrsraq_n_s16", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "uint64x1_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, "b": { - "register": "Dm" + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -95310,26 +290655,31 @@ ], "instructions": [ [ - "USHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshl_u8", + "name": "vrsraq_n_s32", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.4S" }, "b": { - "register": "Vm.8B" + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -95339,193 +290689,234 @@ ], "instructions": [ [ - "USHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshld_n_s64", + "name": "vrsraq_n_s64", "arguments": [ - "int64_t a", + "int64x2_t a", + "int64x2_t b", "const int n" ], "return_type": { - "value": "int64_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" }, "n": { - "minimum": 0, - "maximum": 63 + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshld_n_u64", + "name": "vrsraq_n_s8", "arguments": [ - "uint64_t a", + "int8x16_t a", + "int8x16_t b", "const int n" ], "return_type": { - "value": "uint64_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.16B" + }, + "b": { + "register": "Vn.16B" }, "n": { - "minimum": 0, - "maximum": 63 + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHL" + "SRSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshld_s64", + "name": "vrsraq_n_u16", "arguments": [ - "int64_t a", - "int64_t b" + "uint16x8_t a", + "uint16x8_t b", + "const int n" ], "return_type": { - "value": "int64_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8H" }, "b": { - "register": "Dm" + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshld_u64", + "name": "vrsraq_n_u32", "arguments": [ - "uint64_t a", - "int64_t b" + "uint32x4_t a", + "uint32x4_t b", + "const int n" ], "return_type": { - "value": "uint64_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.4S" }, "b": { - "register": "Dm" + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USHL" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_s16", + "name": "vrsraq_n_u64", "arguments": [ - "int16x8_t a", + "uint64x2_t a", + "uint64x2_t b", "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" }, "n": { - "minimum": 0, - "maximum": 16 + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHLL2" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_s32", + "name": "vrsraq_n_u8", "arguments": [ - "int32x4_t a", + "uint8x16_t a", + "uint8x16_t b", "const int n" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.16B" + }, + "b": { + "register": "Vn.16B" }, "n": { - "minimum": 0, - "maximum": 32 + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHLL2" + "URSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_s8", + "name": "vrsubhn_high_s16", "arguments": [ - "int8x16_t a", - "const int n" + "int8x8_t r", + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 8 + "b": { + "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -95533,27 +290924,30 @@ ], "instructions": [ [ - "SSHLL2" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_u16", + "name": "vrsubhn_high_s32", "arguments": [ - "uint16x8_t a", - "const int n" + "int16x4_t r", + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 16 + "b": { + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -95561,27 +290955,30 @@ ], "instructions": [ [ - "USHLL2" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_u32", + "name": "vrsubhn_high_s64", "arguments": [ - "uint32x4_t a", - "const int n" + "int32x2_t r", + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 32 + "b": { + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -95589,27 +290986,30 @@ ], "instructions": [ [ - "USHLL2" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_high_n_u8", + "name": "vrsubhn_high_u16", "arguments": [ - "uint8x16_t a", - "const int n" + "uint8x8_t r", + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 8 + "b": { + "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -95617,87 +291017,88 @@ ], "instructions": [ [ - "USHLL2" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_s16", + "name": "vrsubhn_high_u32", "arguments": [ - "int16x4_t a", - "const int n" + "uint16x4_t r", + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 16 + "b": { + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSHLL" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_s32", + "name": "vrsubhn_high_u64", "arguments": [ - "int32x2_t a", - "const int n" + "uint32x2_t r", + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 32 + "b": { + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSHLL" + "RSUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_s8", + "name": "vrsubhn_s16", "arguments": [ - "int8x8_t a", - "const int n" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 8 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -95707,27 +291108,26 @@ ], "instructions": [ [ - "SSHLL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_u16", + "name": "vrsubhn_s32", "arguments": [ - "uint16x4_t a", - "const int n" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 16 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -95737,27 +291137,26 @@ ], "instructions": [ [ - "USHLL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_u32", + "name": "vrsubhn_s64", "arguments": [ - "uint32x2_t a", - "const int n" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 32 + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -95767,27 +291166,26 @@ ], "instructions": [ [ - "USHLL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshll_n_u8", + "name": "vrsubhn_u16", "arguments": [ - "uint8x8_t a", - "const int n" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, - "n": { - "minimum": 0, - "maximum": 8 + "b": { + "register": "Vm.8H" } }, "Architectures": [ @@ -95797,27 +291195,26 @@ ], "instructions": [ [ - "USHLL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_s16", + "name": "vrsubhn_u32", "arguments": [ - "int16x8_t a", - "const int n" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, - "n": { - "minimum": 0, - "maximum": 15 + "b": { + "register": "Vm.4S" } }, "Architectures": [ @@ -95827,27 +291224,26 @@ ], "instructions": [ [ - "SHL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_s32", + "name": "vrsubhn_u64", "arguments": [ - "int32x4_t a", - "const int n" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 31 + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -95857,177 +291253,166 @@ ], "instructions": [ [ - "SHL" + "RSUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_s64", + "name": "vscale_f16", "arguments": [ - "int64x2_t a", - "const int n" + "float16x4_t vn", + "int16x4_t vm" ], "return_type": { - "value": "int64x2_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "vm": { + "register": "Vm.4H" }, - "n": { - "minimum": 0, - "maximum": 63 + "vn": { + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_s8", + "name": "vscale_f32", "arguments": [ - "int8x16_t a", - "const int n" + "float32x2_t vn", + "int32x2_t vm" ], "return_type": { - "value": "int8x16_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "vm": { + "register": "Vm.2S" }, - "n": { - "minimum": 0, - "maximum": 7 + "vn": { + "register": "Vn.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_u16", + "name": "vscaleq_f16", "arguments": [ - "uint16x8_t a", - "const int n" + "float16x8_t vn", + "int16x8_t vm" ], "return_type": { - "value": "uint16x8_t" + "value": "float16x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "vm": { + "register": "Vm.8H" }, - "n": { - "minimum": 0, - "maximum": 15 + "vn": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_u32", + "name": "vscaleq_f32", "arguments": [ - "uint32x4_t a", - "const int n" + "float32x4_t vn", + "int32x4_t vm" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "vm": { + "register": "Vm.4S" }, - "n": { - "minimum": 0, - "maximum": 31 + "vn": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_u64", + "name": "vscaleq_f64", "arguments": [ - "uint64x2_t a", - "const int n" + "float64x2_t vn", + "int64x2_t vm" ], "return_type": { - "value": "uint64x2_t" + "value": "float64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "vm": { + "register": "Vm.2D" }, - "n": { - "minimum": 0, - "maximum": 63 + "vn": { + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SHL" + "FSCALE" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_n_u8", + "name": "vset_lane_f16", "arguments": [ - "uint8x16_t a", - "const int n" + "float16_t a", + "float16x4_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "VnH" }, - "n": { + "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 + }, + "v": { + "register": "Vd.4H" } }, "Architectures": [ @@ -96037,26 +291422,31 @@ ], "instructions": [ [ - "SHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_s16", + "name": "vset_lane_f32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float32_t a", + "float32x2_t v", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "b": { - "register": "Vm.8H" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2S" } }, "Architectures": [ @@ -96066,55 +291456,63 @@ ], "instructions": [ [ - "SSHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_s32", + "name": "vset_lane_f64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float64_t a", + "float64x1_t v", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "float64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "b": { - "register": "Vm.4S" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vd.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_s64", + "name": "vset_lane_p16", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "poly16_t a", + "poly16x4_t v", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "b": { - "register": "Vm.2D" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4H" } }, "Architectures": [ @@ -96124,55 +291522,64 @@ ], "instructions": [ [ - "SSHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_s8", + "name": "vset_lane_p64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "poly64_t a", + "poly64x1_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Rn" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vd.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_u16", + "name": "vset_lane_p8", "arguments": [ - "uint16x8_t a", - "int16x8_t b" + "poly8_t a", + "poly8x8_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "b": { - "register": "Vm.8H" + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8B" } }, "Architectures": [ @@ -96182,26 +291589,31 @@ ], "instructions": [ [ - "USHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_u32", + "name": "vset_lane_s16", "arguments": [ - "uint32x4_t a", - "int32x4_t b" + "int16_t a", + "int16x4_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "b": { - "register": "Vm.4S" + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4H" } }, "Architectures": [ @@ -96211,26 +291623,31 @@ ], "instructions": [ [ - "USHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_u64", + "name": "vset_lane_s32", "arguments": [ - "uint64x2_t a", - "int64x2_t b" + "int32_t a", + "int32x2_t v", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "b": { - "register": "Vm.2D" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2S" } }, "Architectures": [ @@ -96240,26 +291657,31 @@ ], "instructions": [ [ - "USHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshlq_u8", + "name": "vset_lane_s64", "arguments": [ - "uint8x16_t a", - "int8x16_t b" + "int64_t a", + "int64x1_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Rn" }, - "b": { - "register": "Vm.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vd.1D" } }, "Architectures": [ @@ -96269,27 +291691,31 @@ ], "instructions": [ [ - "USHL" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_s16", + "name": "vset_lane_s8", "arguments": [ - "int16x4_t a", - "const int n" + "int8_t a", + "int8x8_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8B" } }, "Architectures": [ @@ -96299,27 +291725,31 @@ ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_s32", + "name": "vset_lane_u16", "arguments": [ - "int32x2_t a", - "const int n" + "uint16_t a", + "uint16x4_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4H" } }, "Architectures": [ @@ -96329,27 +291759,31 @@ ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_s64", + "name": "vset_lane_u32", "arguments": [ - "int64x1_t a", - "const int n" + "uint32_t a", + "uint32x2_t v", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 64 + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2S" } }, "Architectures": [ @@ -96359,27 +291793,31 @@ ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_s8", + "name": "vset_lane_u64", "arguments": [ - "int8x8_t a", - "const int n" + "uint64_t a", + "uint64x1_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 0 + }, + "v": { + "register": "Vd.1D" } }, "Architectures": [ @@ -96389,27 +291827,31 @@ ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_u16", + "name": "vset_lane_u8", "arguments": [ - "uint16x4_t a", - "const int n" + "uint8_t a", + "uint8x8_t v", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8B" } }, "Architectures": [ @@ -96419,27 +291861,31 @@ ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_u32", + "name": "vsetq_lane_f16", "arguments": [ - "uint32x2_t a", - "const int n" + "float16_t a", + "float16x8_t v", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "VnH" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8H" } }, "Architectures": [ @@ -96449,27 +291895,31 @@ ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_u64", + "name": "vsetq_lane_f32", "arguments": [ - "uint64x1_t a", - "const int n" + "float32_t a", + "float32x4_t v", + "const int lane" ], "return_type": { - "value": "uint64x1_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 64 + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4S" } }, "Architectures": [ @@ -96479,305 +291929,334 @@ ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshr_n_u8", + "name": "vsetq_lane_f64", "arguments": [ - "uint8x8_t a", - "const int n" + "float64_t a", + "float64x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrd_n_s64", + "name": "vsetq_lane_p16", "arguments": [ - "int64_t a", - "const int n" + "poly16_t a", + "poly16x8_t v", + "const int lane" ], "return_type": { - "value": "int64_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 64 + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrd_n_u64", + "name": "vsetq_lane_p64", "arguments": [ - "uint64_t a", - "const int n" + "poly64_t a", + "poly64x2_t v", + "const int lane" ], "return_type": { - "value": "uint64_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 64 + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "USHR" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_s16", + "name": "vsetq_lane_p8", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "const int n" + "poly8_t a", + "poly8x16_t v", + "const int lane" ], "return_type": { - "value": "int8x16_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 15 }, - "r": { - "register": "Vd.8B" + "v": { + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_s32", + "name": "vsetq_lane_s16", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "const int n" + "int16_t a", + "int16x8_t v", + "const int lane" ], "return_type": { "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 7 }, - "r": { - "register": "Vd.4H" + "v": { + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_s64", + "name": "vsetq_lane_s32", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "const int n" + "int32_t a", + "int32x4_t v", + "const int lane" ], "return_type": { "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 3 }, - "r": { - "register": "Vd.2S" + "v": { + "register": "Vd.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_u16", + "name": "vsetq_lane_s64", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "const int n" + "int64_t a", + "int64x2_t v", + "const int lane" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 1 }, - "r": { - "register": "Vd.8B" + "v": { + "register": "Vd.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_u32", + "name": "vsetq_lane_s8", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "const int n" + "int8_t a", + "int8x16_t v", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 15 }, - "r": { - "register": "Vd.4H" + "v": { + "register": "Vd.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_high_n_u64", + "name": "vsetq_lane_u16", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "const int n" + "uint16_t a", + "uint16x8_t v", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 7 }, - "r": { - "register": "Vd.2S" + "v": { + "register": "Vd.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SHRN2" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_s16", + "name": "vsetq_lane_u32", "arguments": [ - "int16x8_t a", - "const int n" + "uint32_t a", + "uint32x4_t v", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 8 + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4S" } }, "Architectures": [ @@ -96787,27 +292266,31 @@ ], "instructions": [ [ - "SHRN" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_s32", + "name": "vsetq_lane_u64", "arguments": [ - "int32x4_t a", - "const int n" + "uint64_t a", + "uint64x2_t v", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 16 + "lane": { + "minimum": 0, + "maximum": 1 + }, + "v": { + "register": "Vd.2D" } }, "Architectures": [ @@ -96817,27 +292300,31 @@ ], "instructions": [ [ - "SHRN" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_s64", + "name": "vsetq_lane_u8", "arguments": [ - "int64x2_t a", - "const int n" + "uint8_t a", + "uint8x16_t v", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Rn" }, - "n": { - "minimum": 1, - "maximum": 32 + "lane": { + "minimum": 0, + "maximum": 15 + }, + "v": { + "register": "Vd.16B" } }, "Architectures": [ @@ -96847,447 +292334,439 @@ ], "instructions": [ [ - "SHRN" + "MOV" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_u16", + "name": "vsha1cq_u32", "arguments": [ - "uint16x8_t a", - "const int n" + "uint32x4_t hash_abcd", + "uint32_t hash_e", + "uint32x4_t wk" ], "return_type": { - "value": "uint8x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "hash_abcd": { + "register": "Qd" }, - "n": { - "minimum": 1, - "maximum": 8 + "hash_e": { + "register": "Sn" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SHRN" + "SHA1C" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_u32", + "name": "vsha1h_u32", "arguments": [ - "uint32x4_t a", - "const int n" + "uint32_t hash_e" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "n": { - "minimum": 1, - "maximum": 16 + "hash_e": { + "register": "Sn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SHRN" + "SHA1H" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrn_n_u64", + "name": "vsha1mq_u32", "arguments": [ - "uint64x2_t a", - "const int n" + "uint32x4_t hash_abcd", + "uint32_t hash_e", + "uint32x4_t wk" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "hash_abcd": { + "register": "Qd" }, - "n": { - "minimum": 1, - "maximum": 32 + "hash_e": { + "register": "Sn" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SHRN" + "SHA1M" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_s16", + "name": "vsha1pq_u32", "arguments": [ - "int16x8_t a", - "const int n" + "uint32x4_t hash_abcd", + "uint32_t hash_e", + "uint32x4_t wk" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "hash_abcd": { + "register": "Qd" }, - "n": { - "minimum": 1, - "maximum": 16 + "hash_e": { + "register": "Sn" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHR" + "SHA1P" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_s32", + "name": "vsha1su0q_u32", "arguments": [ - "int32x4_t a", - "const int n" + "uint32x4_t w0_3", + "uint32x4_t w4_7", + "uint32x4_t w8_11" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { + "w0_3": { + "register": "Vd.4S" + }, + "w4_7": { "register": "Vn.4S" }, - "n": { - "minimum": 1, - "maximum": 32 + "w8_11": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHR" + "SHA1SU0" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_s64", + "name": "vsha1su1q_u32", "arguments": [ - "int64x2_t a", - "const int n" + "uint32x4_t tw0_3", + "uint32x4_t w12_15" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "tw0_3": { + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 64 + "w12_15": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHR" + "SHA1SU1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_s8", + "name": "vsha256h2q_u32", "arguments": [ - "int8x16_t a", - "const int n" + "uint32x4_t hash_efgh", + "uint32x4_t hash_abcd", + "uint32x4_t wk" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "hash_abcd": { + "register": "Qn" }, - "n": { - "minimum": 1, - "maximum": 8 + "hash_efgh": { + "register": "Qd" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SSHR" + "SHA256H2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_u16", + "name": "vsha256hq_u32", "arguments": [ - "uint16x8_t a", - "const int n" + "uint32x4_t hash_abcd", + "uint32x4_t hash_efgh", + "uint32x4_t wk" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "hash_abcd": { + "register": "Qd" }, - "n": { - "minimum": 1, - "maximum": 16 + "hash_efgh": { + "register": "Qn" + }, + "wk": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "USHR" + "SHA256H" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_u32", + "name": "vsha256su0q_u32", "arguments": [ - "uint32x4_t a", - "const int n" + "uint32x4_t w0_3", + "uint32x4_t w4_7" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "w0_3": { + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 32 + "w4_7": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "USHR" + "SHA256SU0" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_u64", + "name": "vsha256su1q_u32", "arguments": [ - "uint64x2_t a", - "const int n" + "uint32x4_t tw0_3", + "uint32x4_t w8_11", + "uint32x4_t w12_15" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "tw0_3": { + "register": "Vd.4S" }, - "n": { - "minimum": 1, - "maximum": 64 + "w12_15": { + "register": "Vm.4S" + }, + "w8_11": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "USHR" + "SHA256SU1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vshrq_n_u8", + "name": "vsha512h2q_u64", "arguments": [ - "uint8x16_t a", - "const int n" + "uint64x2_t sum_ab", + "uint64x2_t hash_c_", + "uint64x2_t hash_ab" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "hash_ab": { + "register": "Vm.2D" }, - "n": { - "minimum": 1, - "maximum": 8 + "hash_c_": { + "register": "Qn" + }, + "sum_ab": { + "register": "Qd" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USHR" + "SHA512H2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_p16", + "name": "vsha512hq_u64", "arguments": [ - "poly16x4_t a", - "poly16x4_t b", - "const int n" + "uint64x2_t hash_ed", + "uint64x2_t hash_gf", + "uint64x2_t kwh_kwh2" ], "return_type": { - "value": "poly16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.4H" + "hash_ed": { + "register": "Qd" }, - "b": { - "register": "Vn.4H" + "hash_gf": { + "register": "Qn" }, - "n": { - "minimum": 0, - "maximum": 15 + "kwh_kwh2": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHA512H" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_p64", + "name": "vsha512su0q_u64", "arguments": [ - "poly64x1_t a", - "poly64x1_t b", - "const int n" + "uint64x2_t w0_1", + "uint64x2_t w2_" ], "return_type": { - "value": "poly64x1_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "w0_1": { + "register": "Vd.2D" }, - "n": { - "minimum": 0, - "maximum": 63 + "w2_": { + "register": "Vn.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHA512SU0" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_p8", + "name": "vsha512su1q_u64", "arguments": [ - "poly8x8_t a", - "poly8x8_t b", - "const int n" + "uint64x2_t s01_s02", + "uint64x2_t w14_15", + "uint64x2_t w9_10" ], "return_type": { - "value": "poly8x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "a": { - "register": "Vd.8B" + "s01_s02": { + "register": "Vd.2D" }, - "b": { - "register": "Vn.8B" + "w14_15": { + "register": "Vn.2D" }, - "n": { - "minimum": 0, - "maximum": 7 + "w9_10": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHA512SU1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_s16", + "name": "vshl_n_s16", "arguments": [ "int16x4_t a", - "int16x4_t b", "const int n" ], "return_type": { @@ -97295,9 +292774,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "n": { @@ -97312,16 +292788,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_s32", + "name": "vshl_n_s32", "arguments": [ "int32x2_t a", - "int32x2_t b", "const int n" ], "return_type": { @@ -97329,9 +292804,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "n": { @@ -97346,16 +292818,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_s64", + "name": "vshl_n_s64", "arguments": [ "int64x1_t a", - "int64x1_t b", "const int n" ], "return_type": { @@ -97363,9 +292834,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -97380,16 +292848,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_s8", + "name": "vshl_n_s8", "arguments": [ "int8x8_t a", - "int8x8_t b", "const int n" ], "return_type": { @@ -97397,9 +292864,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { "register": "Vn.8B" }, "n": { @@ -97414,16 +292878,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_u16", + "name": "vshl_n_u16", "arguments": [ "uint16x4_t a", - "uint16x4_t b", "const int n" ], "return_type": { @@ -97431,9 +292894,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "n": { @@ -97448,16 +292908,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_u32", + "name": "vshl_n_u32", "arguments": [ "uint32x2_t a", - "uint32x2_t b", "const int n" ], "return_type": { @@ -97465,9 +292924,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "n": { @@ -97482,16 +292938,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_u64", + "name": "vshl_n_u64", "arguments": [ "uint64x1_t a", - "uint64x1_t b", "const int n" ], "return_type": { @@ -97499,9 +292954,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -97516,16 +292968,15 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsli_n_u8", + "name": "vshl_n_u8", "arguments": [ "uint8x8_t a", - "uint8x8_t b", "const int n" ], "return_type": { @@ -97533,9 +292984,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { "register": "Vn.8B" }, "n": { @@ -97550,95 +292998,84 @@ ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vslid_n_s64", + "name": "vshl_s16", "arguments": [ - "int64_t a", - "int64_t b", - "const int n" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "int64_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.4H" }, "b": { - "register": "Dn" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vslid_n_u64", + "name": "vshl_s32", "arguments": [ - "uint64_t a", - "uint64_t b", - "const int n" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint64_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2S" }, "b": { - "register": "Dn" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_p16", + "name": "vshl_s64", "arguments": [ - "poly16x8_t a", - "poly16x8_t b", - "const int n" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dn" }, "b": { - "register": "Vn.8H" - }, - "n": { - "minimum": 0, - "maximum": 15 + "register": "Dm" } }, "Architectures": [ @@ -97648,64 +293085,55 @@ ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_p64", + "name": "vshl_s8", "arguments": [ - "poly64x2_t a", - "poly64x2_t b", - "const int n" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "poly64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_p8", + "name": "vshl_u16", "arguments": [ - "poly8x16_t a", - "poly8x16_t b", - "const int n" + "uint16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.4H" }, "b": { - "register": "Vn.16B" - }, - "n": { - "minimum": 0, - "maximum": 7 + "register": "Vm.4H" } }, "Architectures": [ @@ -97715,31 +293143,26 @@ ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_s16", + "name": "vshl_u32", "arguments": [ - "int16x8_t a", - "int16x8_t b", - "const int n" + "uint32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.2S" }, "b": { - "register": "Vn.8H" - }, - "n": { - "minimum": 0, - "maximum": 15 + "register": "Vm.2S" } }, "Architectures": [ @@ -97749,31 +293172,26 @@ ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_s32", + "name": "vshl_u64", "arguments": [ - "int32x4_t a", - "int32x4_t b", - "const int n" + "uint64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Dn" }, "b": { - "register": "Vn.4S" - }, - "n": { - "minimum": 0, - "maximum": 31 + "register": "Dm" } }, "Architectures": [ @@ -97783,31 +293201,26 @@ ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_s64", + "name": "vshl_u8", "arguments": [ - "int64x2_t a", - "int64x2_t b", - "const int n" + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8B" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Vm.8B" } }, "Architectures": [ @@ -97817,282 +293230,221 @@ ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_s8", + "name": "vshld_n_s64", "arguments": [ - "int8x16_t a", - "int8x16_t b", + "int64_t a", "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "register": "Dn" }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 63 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_u16", + "name": "vshld_n_u64", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", + "uint64_t a", "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "register": "Dn" }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 63 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_u32", + "name": "vshld_s64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "const int n" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Dn" }, "b": { - "register": "Vn.4S" - }, - "n": { - "minimum": 0, - "maximum": 31 + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_u64", + "name": "vshld_u64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "const int n" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Dn" }, "b": { - "register": "Vn.2D" - }, - "n": { - "minimum": 0, - "maximum": 63 + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SLI" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsliq_n_u8", + "name": "vshll_high_n_s16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", + "int16x8_t a", "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "register": "Vn.8H" }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 16 } }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "SLI" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vsm3partw1q_u32", - "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" - ], - "return_type": { - "value": "uint32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vd.4S" - }, - "b": {}, - "c": {} - }, "Architectures": [ "A64" ], "instructions": [ [ - "SM3PARTW1" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3partw2q_u32", + "name": "vshll_high_n_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, - "b": {}, - "c": {} + "n": { + "minimum": 0, + "maximum": 32 + } }, "Architectures": [ "A64" ], "instructions": [ [ - "SM3PARTW2" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3ss1q_u32", + "name": "vshll_high_n_s8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c" + "int8x16_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, - "b": {}, - "c": {} + "n": { + "minimum": 0, + "maximum": 8 + } }, "Architectures": [ "A64" ], "instructions": [ [ - "SM3SS1" + "SSHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3tt1aq_u32", + "name": "vshll_high_n_u16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c", - "const int imm2" + "uint16x8_t a", + "const int n" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8H" }, - "b": {}, - "c": {}, - "imm2": { + "n": { "minimum": 0, - "maximum": 3 + "maximum": 16 } }, "Architectures": [ @@ -98100,31 +293452,27 @@ ], "instructions": [ [ - "SM3TT1A" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3tt1bq_u32", + "name": "vshll_high_n_u32", "arguments": [ "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c", - "const int imm2" + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4S" }, - "b": {}, - "c": {}, - "imm2": { + "n": { "minimum": 0, - "maximum": 3 + "maximum": 32 } }, "Architectures": [ @@ -98132,31 +293480,27 @@ ], "instructions": [ [ - "SM3TT1B" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3tt2aq_u32", + "name": "vshll_high_n_u8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c", - "const int imm2" + "uint8x16_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.16B" }, - "b": {}, - "c": {}, - "imm2": { + "n": { "minimum": 0, - "maximum": 3 + "maximum": 8 } }, "Architectures": [ @@ -98164,584 +293508,667 @@ ], "instructions": [ [ - "SM3TT2A" + "USHLL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm3tt2bq_u32", + "name": "vshll_n_s16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", - "uint32x4_t c", - "const int imm2" + "int16x4_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.4H" }, - "b": {}, - "c": {}, - "imm2": { + "n": { "minimum": 0, - "maximum": 3 + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SM3TT2B" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm4ekeyq_u32", + "name": "vshll_n_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x2_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, - "b": {} + "n": { + "minimum": 0, + "maximum": 32 + } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SM4EKEY" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsm4eq_u32", - "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "name": "vshll_n_s8", + "arguments": [ + "int8x8_t a", + "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.8B" }, - "b": {} + "n": { + "minimum": 0, + "maximum": 8 + } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SM4E" + "SSHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadd_u16", + "name": "vshll_n_u16", "arguments": [ "uint16x4_t a", - "int16x4_t b" + "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" + }, + "n": { + "minimum": 0, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadd_u32", + "name": "vshll_n_u32", "arguments": [ "uint32x2_t a", - "int32x2_t b" + "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" + }, + "n": { + "minimum": 0, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadd_u64", + "name": "vshll_n_u8", "arguments": [ - "uint64x1_t a", - "int64x1_t b" + "uint8x8_t a", + "const int n" ], "return_type": { - "value": "uint64x1_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8B" }, - "b": { - "register": "Dn" + "n": { + "minimum": 0, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "USHLL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadd_u8", + "name": "vshlq_n_s16", "arguments": [ - "uint8x8_t a", - "int8x8_t b" + "int16x8_t a", + "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.8H" }, - "b": { - "register": "Vn.8B" + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddb_u8", + "name": "vshlq_n_s32", "arguments": [ - "uint8_t a", - "int8_t b" + "int32x4_t a", + "const int n" ], "return_type": { - "value": "uint8_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Bd" + "register": "Vn.4S" }, - "b": { - "register": "Bn" + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddd_u64", + "name": "vshlq_n_s64", "arguments": [ - "uint64_t a", - "int64_t b" + "int64x2_t a", + "const int n" ], "return_type": { - "value": "uint64_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.2D" }, - "b": { - "register": "Dn" + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddh_u16", + "name": "vshlq_n_s8", "arguments": [ - "uint16_t a", - "int16_t b" + "int8x16_t a", + "const int n" ], "return_type": { - "value": "uint16_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Vn.16B" }, - "b": { - "register": "Hn" + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddq_u16", + "name": "vshlq_n_u16", "arguments": [ "uint16x8_t a", - "int16x8_t b" + "const int n" ], "return_type": { "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddq_u32", + "name": "vshlq_n_u32", "arguments": [ "uint32x4_t a", - "int32x4_t b" + "const int n" ], "return_type": { "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" + }, + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddq_u64", + "name": "vshlq_n_u64", "arguments": [ "uint64x2_t a", - "int64x2_t b" + "const int n" ], "return_type": { "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2D" + }, + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqaddq_u8", + "name": "vshlq_n_u8", "arguments": [ "uint8x16_t a", - "int8x16_t b" + "const int n" ], "return_type": { "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqadds_u32", + "name": "vshlq_s16", "arguments": [ - "uint32_t a", - "int32_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint32_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.8H" }, "b": { - "register": "Sn" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USQADD" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrt_f16", + "name": "vshlq_s32", "arguments": [ - "float16x4_t a" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrt_f32", + "name": "vshlq_s64", "arguments": [ - "float32x2_t a" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrt_f64", + "name": "vshlq_s8", "arguments": [ - "float64x1_t a" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float64x1_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "SSHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrth_f16", + "name": "vshlq_u16", "arguments": [ - "float16_t a" + "uint16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hn" + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FSQRT" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrtq_f16", + "name": "vshlq_u32", "arguments": [ - "float16x8_t a" + "uint32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrtq_f32", + "name": "vshlq_u64", "arguments": [ - "float32x4_t a" + "uint64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float32x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsqrtq_f64", + "name": "vshlq_u8", "arguments": [ - "float64x2_t a" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float64x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSQRT" + "USHL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_s16", + "name": "vshr_n_s16", "arguments": [ "int16x4_t a", - "int16x4_t b", "const int n" ], "return_type": { @@ -98749,9 +294176,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "n": { @@ -98766,16 +294190,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_s32", + "name": "vshr_n_s32", "arguments": [ "int32x2_t a", - "int32x2_t b", "const int n" ], "return_type": { @@ -98783,9 +294206,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "n": { @@ -98800,16 +294220,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_s64", + "name": "vshr_n_s64", "arguments": [ "int64x1_t a", - "int64x1_t b", "const int n" ], "return_type": { @@ -98817,9 +294236,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -98834,16 +294250,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_s8", + "name": "vshr_n_s8", "arguments": [ "int8x8_t a", - "int8x8_t b", "const int n" ], "return_type": { @@ -98851,9 +294266,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { "register": "Vn.8B" }, "n": { @@ -98868,16 +294280,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_u16", + "name": "vshr_n_u16", "arguments": [ "uint16x4_t a", - "uint16x4_t b", "const int n" ], "return_type": { @@ -98885,9 +294296,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { "register": "Vn.4H" }, "n": { @@ -98902,16 +294310,15 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_u32", + "name": "vshr_n_u32", "arguments": [ "uint32x2_t a", - "uint32x2_t b", "const int n" ], "return_type": { @@ -98919,9 +294326,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { "register": "Vn.2S" }, "n": { @@ -98936,16 +294340,15 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_u64", + "name": "vshr_n_u64", "arguments": [ "uint64x1_t a", - "uint64x1_t b", "const int n" ], "return_type": { @@ -98953,9 +294356,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -98970,16 +294370,15 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsra_n_u8", + "name": "vshr_n_u8", "arguments": [ "uint8x8_t a", - "uint8x8_t b", "const int n" ], "return_type": { @@ -98987,9 +294386,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { "register": "Vn.8B" }, "n": { @@ -99004,16 +294400,15 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsrad_n_s64", + "name": "vshrd_n_s64", "arguments": [ "int64_t a", - "int64_t b", "const int n" ], "return_type": { @@ -99021,9 +294416,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -99036,16 +294428,15 @@ ], "instructions": [ [ - "SSRA" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsrad_n_u64", + "name": "vshrd_n_u64", "arguments": [ "uint64_t a", - "uint64_t b", "const int n" ], "return_type": { @@ -99053,9 +294444,6 @@ }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { "register": "Dn" }, "n": { @@ -99068,152 +294456,144 @@ ], "instructions": [ [ - "USRA" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_s16", + "name": "vshrn_high_n_s16", "arguments": [ + "int8x8_t r", "int16x8_t a", - "int16x8_t b", "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { "register": "Vn.8H" }, "n": { "minimum": 1, - "maximum": 16 + "maximum": 8 + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_s32", + "name": "vshrn_high_n_s32", "arguments": [ + "int16x4_t r", "int32x4_t a", - "int32x4_t b", "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { "register": "Vn.4S" }, "n": { "minimum": 1, - "maximum": 32 + "maximum": 16 + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_s64", + "name": "vshrn_high_n_s64", "arguments": [ + "int32x2_t r", "int64x2_t a", - "int64x2_t b", "const int n" ], "return_type": { - "value": "int64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { "register": "Vn.2D" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 32 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_s8", + "name": "vshrn_high_n_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b", + "uint8x8_t r", + "uint16x8_t a", "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "register": "Vn.8H" }, "n": { "minimum": 1, "maximum": 8 + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_u16", + "name": "vshrn_high_n_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", + "uint16x4_t r", + "uint32x4_t a", "const int n" ], "return_type": { @@ -99221,33 +294601,31 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" - }, - "b": { - "register": "Vn.8H" + "register": "Vn.4S" }, "n": { "minimum": 1, "maximum": 16 + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_u32", + "name": "vshrn_high_n_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", + "uint32x2_t r", + "uint64x2_t a", "const int n" ], "return_type": { @@ -99255,48 +294633,42 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" - }, - "b": { - "register": "Vn.4S" + "register": "Vn.2D" }, "n": { "minimum": 1, "maximum": 32 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USRA" + "SHRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_u64", + "name": "vshrn_n_s16", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", + "int16x8_t a", "const int n" ], "return_type": { - "value": "uint64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" - }, - "b": { - "register": "Vn.2D" + "register": "Vn.8H" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 8 } }, "Architectures": [ @@ -99306,31 +294678,27 @@ ], "instructions": [ [ - "USRA" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsraq_n_u8", + "name": "vshrn_n_s32", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", + "int32x4_t a", "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" - }, - "b": { - "register": "Vn.16B" + "register": "Vn.4S" }, "n": { "minimum": 1, - "maximum": 8 + "maximum": 16 } }, "Architectures": [ @@ -99340,31 +294708,27 @@ ], "instructions": [ [ - "USRA" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_p16", + "name": "vshrn_n_s64", "arguments": [ - "poly16x4_t a", - "poly16x4_t b", + "int64x2_t a", "const int n" ], "return_type": { - "value": "poly16x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.2D" }, "n": { "minimum": 1, - "maximum": 16 + "maximum": 32 } }, "Architectures": [ @@ -99374,64 +294738,57 @@ ], "instructions": [ [ - "SRI" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_p64", + "name": "vshrn_n_u16", "arguments": [ - "poly64x1_t a", - "poly64x1_t b", + "uint16x8_t a", "const int n" ], "return_type": { - "value": "poly64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "register": "Vn.8H" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 8 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SRI" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_p8", + "name": "vshrn_n_u32", "arguments": [ - "poly8x8_t a", - "poly8x8_t b", + "uint32x4_t a", "const int n" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" + "register": "Vn.4S" }, "n": { "minimum": 1, - "maximum": 8 + "maximum": 16 } }, "Architectures": [ @@ -99441,31 +294798,27 @@ ], "instructions": [ [ - "SRI" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_s16", + "name": "vshrn_n_u64", "arguments": [ - "int16x4_t a", - "int16x4_t b", + "uint64x2_t a", "const int n" ], "return_type": { - "value": "int16x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.2D" }, "n": { "minimum": 1, - "maximum": 16 + "maximum": 32 } }, "Architectures": [ @@ -99475,31 +294828,27 @@ ], "instructions": [ [ - "SRI" + "SHRN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_s32", + "name": "vshrq_n_s16", "arguments": [ - "int32x2_t a", - "int32x2_t b", + "int16x8_t a", "const int n" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.8H" }, "n": { "minimum": 1, - "maximum": 32 + "maximum": 16 } }, "Architectures": [ @@ -99509,31 +294858,27 @@ ], "instructions": [ [ - "SRI" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_s64", + "name": "vshrq_n_s32", "arguments": [ - "int64x1_t a", - "int64x1_t b", + "int32x4_t a", "const int n" ], "return_type": { - "value": "int64x1_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "register": "Vn.4S" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 32 } }, "Architectures": [ @@ -99543,31 +294888,27 @@ ], "instructions": [ [ - "SRI" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_s8", + "name": "vshrq_n_s64", "arguments": [ - "int8x8_t a", - "int8x8_t b", + "int64x2_t a", "const int n" ], "return_type": { - "value": "int8x8_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" + "register": "Vn.2D" }, "n": { "minimum": 1, - "maximum": 8 + "maximum": 64 } }, "Architectures": [ @@ -99577,31 +294918,27 @@ ], "instructions": [ [ - "SRI" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_u16", + "name": "vshrq_n_s8", "arguments": [ - "uint16x4_t a", - "uint16x4_t b", + "int8x16_t a", "const int n" ], "return_type": { - "value": "uint16x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" - }, - "b": { - "register": "Vn.4H" + "register": "Vn.16B" }, "n": { "minimum": 1, - "maximum": 16 + "maximum": 8 } }, "Architectures": [ @@ -99611,31 +294948,27 @@ ], "instructions": [ [ - "SRI" + "SSHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_u32", + "name": "vshrq_n_u16", "arguments": [ - "uint32x2_t a", - "uint32x2_t b", + "uint16x8_t a", "const int n" ], "return_type": { - "value": "uint32x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" - }, - "b": { - "register": "Vn.2S" + "register": "Vn.8H" }, "n": { "minimum": 1, - "maximum": 32 + "maximum": 16 } }, "Architectures": [ @@ -99645,31 +294978,27 @@ ], "instructions": [ [ - "SRI" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_u64", + "name": "vshrq_n_u32", "arguments": [ - "uint64x1_t a", - "uint64x1_t b", + "uint32x4_t a", "const int n" ], "return_type": { - "value": "uint64x1_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "register": "Vn.4S" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 32 } }, "Architectures": [ @@ -99679,31 +295008,27 @@ ], "instructions": [ [ - "SRI" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsri_n_u8", + "name": "vshrq_n_u64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", + "uint64x2_t a", "const int n" ], "return_type": { - "value": "uint8x8_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" - }, - "b": { - "register": "Vn.8B" + "register": "Vn.2D" }, "n": { "minimum": 1, - "maximum": 8 + "maximum": 64 } }, "Architectures": [ @@ -99713,162 +295038,162 @@ ], "instructions": [ [ - "SRI" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsrid_n_s64", + "name": "vshrq_n_u8", "arguments": [ - "int64_t a", - "int64_t b", + "uint8x16_t a", "const int n" ], "return_type": { - "value": "int64_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" - }, - "b": { - "register": "Dn" + "register": "Vn.16B" }, "n": { "minimum": 1, - "maximum": 64 + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SRI" + "USHR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsrid_n_u64", + "name": "vsli_n_p16", "arguments": [ - "uint64_t a", - "uint64_t b", + "poly16x4_t a", + "poly16x4_t b", "const int n" ], "return_type": { - "value": "uint64_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vd.4H" }, "b": { - "register": "Dn" + "register": "Vn.4H" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_p16", + "name": "vsli_n_p64", "arguments": [ - "poly16x8_t a", - "poly16x8_t b", + "poly64x1_t a", + "poly64x1_t b", "const int n" ], "return_type": { - "value": "poly16x8_t" + "value": "poly64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Dd" }, "b": { - "register": "Vn.8H" + "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 16 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_p64", + "name": "vsli_n_p8", "arguments": [ - "poly64x2_t a", - "poly64x2_t b", + "poly8x8_t a", + "poly8x8_t b", "const int n" ], "return_type": { - "value": "poly64x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8B" }, "b": { - "register": "Vn.2D" + "register": "Vn.8B" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_p8", + "name": "vsli_n_s16", "arguments": [ - "poly8x16_t a", - "poly8x16_t b", + "int16x4_t a", + "int16x4_t b", "const int n" ], "return_type": { - "value": "poly8x16_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" }, "b": { - "register": "Vn.16B" + "register": "Vn.4H" }, "n": { - "minimum": 1, - "maximum": 8 + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -99878,31 +295203,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_s16", + "name": "vsli_n_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b", + "int32x2_t a", + "int32x2_t b", "const int n" ], "return_type": { - "value": "int16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" }, "b": { - "register": "Vn.8H" + "register": "Vn.2S" }, "n": { - "minimum": 1, - "maximum": 16 + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -99912,31 +295237,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_s32", + "name": "vsli_n_s64", "arguments": [ - "int32x4_t a", - "int32x4_t b", + "int64x1_t a", + "int64x1_t b", "const int n" ], "return_type": { - "value": "int32x4_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Dd" }, "b": { - "register": "Vn.4S" + "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 32 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -99946,31 +295271,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_s64", + "name": "vsli_n_s8", "arguments": [ - "int64x2_t a", - "int64x2_t b", + "int8x8_t a", + "int8x8_t b", "const int n" ], "return_type": { - "value": "int64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8B" }, "b": { - "register": "Vn.2D" + "register": "Vn.8B" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -99980,31 +295305,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_s8", + "name": "vsli_n_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b", + "uint16x4_t a", + "uint16x4_t b", "const int n" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vd.4H" }, "b": { - "register": "Vn.16B" + "register": "Vn.4H" }, "n": { - "minimum": 1, - "maximum": 8 + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -100014,31 +295339,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_u16", + "name": "vsli_n_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b", + "uint32x2_t a", + "uint32x2_t b", "const int n" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vd.2S" }, "b": { - "register": "Vn.8H" + "register": "Vn.2S" }, "n": { - "minimum": 1, - "maximum": 16 + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -100048,31 +295373,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_u32", + "name": "vsli_n_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b", + "uint64x1_t a", + "uint64x1_t b", "const int n" ], "return_type": { - "value": "uint32x4_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Dd" }, "b": { - "register": "Vn.4S" + "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 32 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -100082,31 +295407,31 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_u64", + "name": "vsli_n_u8", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", + "uint8x8_t a", + "uint8x8_t b", "const int n" ], "return_type": { - "value": "uint64x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vd.8B" }, "b": { - "register": "Vn.2D" + "register": "Vn.8B" }, "n": { - "minimum": 1, - "maximum": 64 + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -100116,89 +295441,95 @@ ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsriq_n_u8", + "name": "vslid_n_s64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", + "int64_t a", + "int64_t b", "const int n" ], "return_type": { - "value": "uint8x16_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Dd" }, "b": { - "register": "Vn.16B" + "register": "Dn" }, "n": { - "minimum": 1, - "maximum": 8 + "minimum": 0, + "maximum": 63 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SRI" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f16", + "name": "vslid_n_u64", "arguments": [ - "float16_t * ptr", - "float16x4_t val" + "uint64_t a", + "uint64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.4H" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f16_x2", + "name": "vsliq_n_p16", "arguments": [ - "float16_t * ptr", - "float16x4x2_t val" + "poly16x8_t a", + "poly16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt2.4H" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -100208,55 +295539,64 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f16_x3", + "name": "vsliq_n_p64", "arguments": [ - "float16_t * ptr", - "float16x4x3_t val" + "poly64x2_t a", + "poly64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt3.4H" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f16_x4", + "name": "vsliq_n_p8", "arguments": [ - "float16_t * ptr", - "float16x4x4_t val" + "poly8x16_t a", + "poly8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt4.4H" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -100266,26 +295606,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f32", + "name": "vsliq_n_s16", "arguments": [ - "float32_t * ptr", - "float32x2_t val" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ @@ -100295,26 +295640,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f32_x2", + "name": "vsliq_n_s32", "arguments": [ - "float32_t * ptr", - "float32x2x2_t val" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt2.2S" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ @@ -100324,26 +295674,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f32_x3", + "name": "vsliq_n_s64", "arguments": [ - "float32_t * ptr", - "float32x2x3_t val" + "int64x2_t a", + "int64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt3.2S" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ @@ -100353,26 +295708,31 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f32_x4", + "name": "vsliq_n_s8", "arguments": [ - "float32_t * ptr", - "float32x2x4_t val" + "int8x16_t a", + "int8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt4.2S" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ @@ -100382,207 +295742,228 @@ ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f64", + "name": "vsliq_n_u16", "arguments": [ - "float64_t * ptr", - "float64x1_t val" + "uint16x8_t a", + "uint16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 0, + "maximum": 15 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f64_x2", + "name": "vsliq_n_u32", "arguments": [ - "float64_t * ptr", - "float64x1x2_t val" + "uint32x4_t a", + "uint32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt2.1D" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 0, + "maximum": 31 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f64_x3", + "name": "vsliq_n_u64", "arguments": [ - "float64_t * ptr", - "float64x1x3_t val" + "uint64x2_t a", + "uint64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt3.1D" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 0, + "maximum": 63 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_f64_x4", + "name": "vsliq_n_u8", "arguments": [ - "float64_t * ptr", - "float64x1x4_t val" + "uint8x16_t a", + "uint8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt4.1D" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SLI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_f16", + "name": "vsm3partw1q_u32", "arguments": [ - "float16_t * ptr", - "float16x4_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.4H" + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3PARTW1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_f32", + "name": "vsm3partw2q_u32", "arguments": [ - "float32_t * ptr", - "float32x2_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.2S" + "c": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3PARTW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_f64", + "name": "vsm3ss1q_u32", "arguments": [ - "float64_t * ptr", - "float64x1_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vn.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vm.4S" }, - "val": { - "register": "Vt.1D" + "c": { + "register": "Va.4S" } }, "Architectures": [ @@ -100590,801 +295971,715 @@ ], "instructions": [ [ - "ST1" + "SM3SS1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_p16", + "name": "vsm3tt1aq_u32", "arguments": [ - "poly16_t * ptr", - "poly16x4_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c", + "const int imm2" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.4H" + "c": { + "register": "Vm.4S" + }, + "imm2": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3TT1A" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_p64", + "name": "vsm3tt1bq_u32", "arguments": [ - "poly64_t * ptr", - "poly64x1_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c", + "const int imm2" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.1D" + "c": { + "register": "Vm.4S" + }, + "imm2": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3TT1B" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_p8", + "name": "vsm3tt2aq_u32", "arguments": [ - "poly8_t * ptr", - "poly8x8_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c", + "const int imm2" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.8B" + "c": { + "register": "Vm.4S" + }, + "imm2": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3TT2A" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_s16", + "name": "vsm3tt2bq_u32", "arguments": [ - "int16_t * ptr", - "int16x4_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b", + "uint32x4_t c", + "const int imm2" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vd.4S" }, - "ptr": { - "register": "Xn" + "b": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.4H" + "c": { + "register": "Vm.4S" + }, + "imm2": { + "minimum": 0, + "maximum": 3 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM3TT2B" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_s32", + "name": "vsm4ekeyq_u32", "arguments": [ - "int32_t * ptr", - "int32x2_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vn.4S" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM4EKEY" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_s64", + "name": "vsm4eq_u32", "arguments": [ - "int64_t * ptr", - "int64x1_t val", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SM4E" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_s8", + "name": "vsqadd_u16", "arguments": [ - "int8_t * ptr", - "int8x8_t val", - "const int lane" + "uint16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "void" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt.8B" + "b": { + "register": "Vn.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_u16", + "name": "vsqadd_u32", "arguments": [ - "uint16_t * ptr", - "uint16x4_t val", - "const int lane" + "uint32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "void" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt.4H" + "b": { + "register": "Vn.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_u32", + "name": "vsqadd_u64", "arguments": [ - "uint32_t * ptr", - "uint32x2_t val", - "const int lane" + "uint64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "void" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_u64", + "name": "vsqadd_u8", "arguments": [ - "uint64_t * ptr", - "uint64x1_t val", - "const int lane" + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "void" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_lane_u8", + "name": "vsqaddb_u8", "arguments": [ - "uint8_t * ptr", - "uint8x8_t val", - "const int lane" + "uint8_t a", + "int8_t b" ], "return_type": { - "value": "void" + "value": "uint8_t" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, - "ptr": { - "register": "Xn" + "a": { + "register": "Bd" }, - "val": { - "register": "Vt.8B" + "b": { + "register": "Bn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p16", + "name": "vsqaddd_u64", "arguments": [ - "poly16_t * ptr", - "poly16x4_t val" + "uint64_t a", + "int64_t b" ], "return_type": { - "value": "void" + "value": "uint64_t" }, "Arguments_Preparation": { - "ptr": { - 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- "register": "Vt3.4H" + "b": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p16_x4", + "name": "vsqaddq_u32", "arguments": [ - "poly16_t * ptr", - "poly16x4x4_t val" + "uint32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt4.4H" + "b": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p64", + "name": "vsqaddq_u64", "arguments": [ - "poly64_t * ptr", - "poly64x1_t val" + "uint64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "void" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p64_x2", + "name": "vsqaddq_u8", "arguments": [ - "poly64_t * ptr", - "poly64x1x2_t val" + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "void" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt2.1D" + "b": { + "register": "Vn.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p64_x3", + "name": "vsqadds_u32", "arguments": [ - "poly64_t * ptr", - "poly64x1x3_t val" + "uint32_t a", + "int32_t b" ], "return_type": { - "value": "void" + "value": "uint32_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Sd" }, - "val": { - "register": "Vt3.1D" + "b": { + "register": "Sn" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "USQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p64_x4", + "name": "vsqrt_f16", "arguments": [ - "poly64_t * ptr", - "poly64x1x4_t val" + "float16x4_t a" ], "return_type": { - "value": "void" + "value": "float16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt4.1D" + "a": { + "register": "Vn.4H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p8", + "name": "vsqrt_f32", "arguments": [ - "poly8_t * ptr", - "poly8x8_t val" + "float32x2_t a" ], "return_type": { - "value": "void" + "value": "float32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt.8B" + "a": { + "register": "Vn.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p8_x2", + "name": "vsqrt_f64", "arguments": [ - "poly8_t * ptr", - "poly8x8x2_t val" + "float64x1_t a" ], "return_type": { - "value": "void" + "value": "float64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt2.8B" + "a": { + "register": "Dn" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p8_x3", + "name": "vsqrth_f16", "arguments": [ - "poly8_t * ptr", - "poly8x8x3_t val" + "float16_t a" ], "return_type": { - "value": "void" + "value": "float16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt3.8B" + "a": { + "register": "Hn" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_p8_x4", + "name": "vsqrtq_f16", "arguments": [ - "poly8_t * ptr", - "poly8x8x4_t val" + "float16x8_t a" ], "return_type": { - "value": "void" + "value": "float16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt4.8B" + "a": { + "register": "Vn.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s16", + "name": "vsqrtq_f32", "arguments": [ - "int16_t * ptr", - "int16x4_t val" + "float32x4_t a" ], "return_type": { - "value": "void" + "value": "float32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt.4H" + "a": { + "register": "Vn.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s16_x2", + "name": "vsqrtq_f64", "arguments": [ - "int16_t * ptr", - "int16x4x2_t val" + "float64x2_t a" ], "return_type": { - "value": "void" + "value": "float64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt2.4H" + "a": { + "register": "Vn.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "FSQRT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s16_x3", + "name": "vsra_n_s16", "arguments": [ - "int16_t * ptr", - "int16x4x3_t val" + "int16x4_t a", + "int16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt3.4H" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101394,26 +296689,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s16_x4", + "name": "vsra_n_s32", "arguments": [ - "int16_t * ptr", - "int16x4x4_t val" + "int32x2_t a", + "int32x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt4.4H" + "b": { + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -101423,26 +296723,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s32", + "name": "vsra_n_s64", "arguments": [ - "int32_t * ptr", - "int32x2_t val" + "int64x1_t a", + "int64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -101452,26 +296757,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s32_x2", + "name": "vsra_n_s8", "arguments": [ - "int32_t * ptr", - "int32x2x2_t val" + "int8x8_t a", + "int8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt2.2S" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101481,26 +296791,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s32_x3", + "name": "vsra_n_u16", "arguments": [ - "int32_t * ptr", - "int32x2x3_t val" + "uint16x4_t a", + "uint16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt3.2S" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101510,26 +296825,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s32_x4", + "name": "vsra_n_u32", "arguments": [ - "int32_t * ptr", - "int32x2x4_t val" + "uint32x2_t a", + "uint32x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt4.2S" + "b": { + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -101539,26 +296859,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s64", + "name": "vsra_n_u64", "arguments": [ - "int64_t * ptr", - "int64x1_t val" + "uint64x1_t a", + "uint64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x1_t" }, - "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "Arguments_Preparation": { + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -101568,26 +296893,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s64_x2", + "name": "vsra_n_u8", "arguments": [ - "int64_t * ptr", - "int64x1x2_t val" + "uint8x8_t a", + "uint8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt2.1D" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101597,84 +296927,95 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s64_x3", + "name": "vsrad_n_s64", "arguments": [ - "int64_t * ptr", - "int64x1x3_t val" + "int64_t a", + "int64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt3.1D" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s64_x4", + "name": "vsrad_n_u64", "arguments": [ - "int64_t * ptr", - "int64x1x4_t val" + "uint64_t a", + "uint64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt4.1D" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s8", + "name": "vsraq_n_s16", "arguments": [ - "int8_t * ptr", - "int8x8_t val" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt.8B" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101684,26 +297025,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s8_x2", + "name": "vsraq_n_s32", "arguments": [ - "int8_t * ptr", - "int8x8x2_t val" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt2.8B" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -101713,26 +297059,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s8_x3", + "name": "vsraq_n_s64", "arguments": [ - "int8_t * ptr", - "int8x8x3_t val" + "int64x2_t a", + "int64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt3.8B" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -101742,26 +297093,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_s8_x4", + "name": "vsraq_n_s8", "arguments": [ - "int8_t * ptr", - "int8x8x4_t val" + "int8x16_t a", + "int8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt4.8B" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101771,26 +297127,31 @@ ], "instructions": [ [ - "ST1" + "SSRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u16", + "name": "vsraq_n_u16", "arguments": [ - "uint16_t * ptr", - "uint16x4_t val" + "uint16x8_t a", + "uint16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt.4H" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101800,26 +297161,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u16_x2", + "name": "vsraq_n_u32", "arguments": [ - "uint16_t * ptr", - "uint16x4x2_t val" + "uint32x4_t a", + "uint32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt2.4H" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -101829,26 +297195,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u16_x3", + "name": "vsraq_n_u64", "arguments": [ - "uint16_t * ptr", - "uint16x4x3_t val" + "uint64x2_t a", + "uint64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt3.4H" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -101858,26 +297229,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u16_x4", + "name": "vsraq_n_u8", "arguments": [ - "uint16_t * ptr", - "uint16x4x4_t val" + "uint8x16_t a", + "uint8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt4.4H" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101887,26 +297263,31 @@ ], "instructions": [ [ - "ST1" + "USRA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u32", + "name": "vsri_n_p16", "arguments": [ - "uint32_t * ptr", - "uint32x2_t val" + "poly16x4_t a", + "poly16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt.2S" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -101916,55 +297297,64 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u32_x2", + "name": "vsri_n_p64", "arguments": [ - "uint32_t * ptr", - "uint32x2x2_t val" + "poly64x1_t a", + "poly64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt2.2S" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u32_x3", + "name": "vsri_n_p8", "arguments": [ - "uint32_t * ptr", - "uint32x2x3_t val" + "poly8x8_t a", + "poly8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt3.2S" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -101974,26 +297364,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u32_x4", + "name": "vsri_n_s16", "arguments": [ - "uint32_t * ptr", - "uint32x2x4_t val" + "int16x4_t a", + "int16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt4.2S" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -102003,26 +297398,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u64", + "name": "vsri_n_s32", "arguments": [ - "uint64_t * ptr", - "uint64x1_t val" + "int32x2_t a", + "int32x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt.1D" + "b": { + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -102032,26 +297432,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u64_x2", + "name": "vsri_n_s64", "arguments": [ - "uint64_t * ptr", - "uint64x1x2_t val" + "int64x1_t a", + "int64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt2.1D" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -102061,26 +297466,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u64_x3", + "name": "vsri_n_s8", "arguments": [ - "uint64_t * ptr", - "uint64x1x3_t val" + "int8x8_t a", + "int8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt3.1D" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -102090,26 +297500,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u64_x4", + "name": "vsri_n_u16", "arguments": [ - "uint64_t * ptr", - "uint64x1x4_t val" + "uint16x4_t a", + "uint16x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4H" }, - "val": { - "register": "Vt4.1D" + "b": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -102119,26 +297534,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u8", + "name": "vsri_n_u32", "arguments": [ - "uint8_t * ptr", - "uint8x8_t val" + "uint32x2_t a", + "uint32x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2S" }, - "val": { - "register": "Vt.8B" + "b": { + "register": "Vn.2S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -102148,26 +297568,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u8_x2", + "name": "vsri_n_u64", "arguments": [ - "uint8_t * ptr", - "uint8x8x2_t val" + "uint64x1_t a", + "uint64x1_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x1_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt2.8B" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -102177,26 +297602,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u8_x3", + "name": "vsri_n_u8", "arguments": [ - "uint8_t * ptr", - "uint8x8x3_t val" + "uint8x8_t a", + "uint8x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8B" }, - "val": { - "register": "Vt3.8B" + "b": { + "register": "Vn.8B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -102206,84 +297636,95 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1_u8_x4", + "name": "vsrid_n_s64", "arguments": [ - "uint8_t * ptr", - "uint8x8x4_t val" + "int64_t a", + "int64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt4.8B" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f16", + "name": "vsrid_n_u64", "arguments": [ - "float16_t * ptr", - "float16x8_t val" + "uint64_t a", + "uint64_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Dd" }, - "val": { - "register": "Vt.8H" + "b": { + "register": "Dn" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f16_x2", + "name": "vsriq_n_p16", "arguments": [ - "float16_t * ptr", - "float16x8x2_t val" + "poly16x8_t a", + "poly16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt2.8H" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -102293,55 +297734,64 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f16_x3", + "name": "vsriq_n_p64", "arguments": [ - "float16_t * ptr", - "float16x8x3_t val" + "poly64x2_t a", + "poly64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt3.8H" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f16_x4", + "name": "vsriq_n_p8", "arguments": [ - "float16_t * ptr", - "float16x8x4_t val" + "poly8x16_t a", + "poly8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "poly8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt4.8H" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -102351,26 +297801,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f32", + "name": "vsriq_n_s16", "arguments": [ - "float32_t * ptr", - "float32x4_t val" + "int16x8_t a", + "int16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt.4S" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ @@ -102380,26 +297835,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f32_x2", + "name": "vsriq_n_s32", "arguments": [ - "float32_t * ptr", - "float32x4x2_t val" + "int32x4_t a", + "int32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt2.4S" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ @@ -102409,26 +297869,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f32_x3", + "name": "vsriq_n_s64", "arguments": [ - "float32_t * ptr", - "float32x4x3_t val" + "int64x2_t a", + "int64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt3.4S" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ @@ -102438,26 +297903,31 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f32_x4", + "name": "vsriq_n_s8", "arguments": [ - "float32_t * ptr", - "float32x4x4_t val" + "int8x16_t a", + "int8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "int8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt4.4S" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ @@ -102467,139 +297937,162 @@ ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f64", + "name": "vsriq_n_u16", "arguments": [ - "float64_t * ptr", - "float64x2_t val" + "uint16x8_t a", + "uint16x8_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint16x8_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.8H" }, - "val": { - "register": "Vt.2D" + "b": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f64_x2", + "name": "vsriq_n_u32", "arguments": [ - "float64_t * ptr", - "float64x2x2_t val" + "uint32x4_t a", + "uint32x4_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint32x4_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.4S" }, - "val": { - "register": "Vt2.2D" + "b": { + "register": "Vn.4S" + }, + "n": { + "minimum": 1, + "maximum": 32 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f64_x3", + "name": "vsriq_n_u64", "arguments": [ - "float64_t * ptr", - "float64x2x3_t val" + "uint64x2_t a", + "uint64x2_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint64x2_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.2D" }, - "val": { - "register": "Vt3.2D" + "b": { + "register": "Vn.2D" + }, + "n": { + "minimum": 1, + "maximum": 64 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_f64_x4", + "name": "vsriq_n_u8", "arguments": [ - "float64_t * ptr", - "float64x2x4_t val" + "uint8x16_t a", + "uint8x16_t b", + "const int n" ], "return_type": { - "value": "void" + "value": "uint8x16_t" }, "Arguments_Preparation": { - "ptr": { - "register": "Xn" + "a": { + "register": "Vd.16B" }, - "val": { - "register": "Vt4.2D" + "b": { + "register": "Vn.16B" + }, + "n": { + "minimum": 1, + "maximum": 8 } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST1" + "SRI" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_f16", + "name": "vst1_f16", "arguments": [ "float16_t * ptr", - "float16x8_t val", - "const int lane" + "float16x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.8H" + "register": "Vt.4H" } }, "Architectures": [ @@ -102615,25 +298108,23 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_f32", + "name": "vst1_f16_x2", "arguments": [ - "float32_t * ptr", - "float32x4_t val", - "const int lane" + "float16_t * ptr", + "float16x4x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.4S" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -102649,28 +298140,31 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_f64", + "name": "vst1_f16_x3", "arguments": [ - "float64_t * ptr", - "float64x2_t val", - "const int lane" + "float16_t * ptr", + "float16x4x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.2D" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -102681,25 +298175,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_p16", + "name": "vst1_f16_x4", "arguments": [ - "poly16_t * ptr", - "poly16x8_t val", - "const int lane" + "float16_t * ptr", + "float16x4x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -102715,28 +298213,24 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_p64", + "name": "vst1_f32", "arguments": [ - "poly64_t * ptr", - "poly64x2_t val", - "const int lane" + "float32_t * ptr", + "float32x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.2D" + "register": "Vt.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -102748,25 +298242,23 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_p8", + "name": "vst1_f32_x2", "arguments": [ - "poly8_t * ptr", - "poly8x16_t val", - "const int lane" + "float32_t * ptr", + "float32x2x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.16B" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -102782,25 +298274,26 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_s16", + "name": "vst1_f32_x3", "arguments": [ - "int16_t * ptr", - "int16x8_t val", - "const int lane" + "float32_t * ptr", + "float32x2x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -102816,25 +298309,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_s32", + "name": "vst1_f32_x4", "arguments": [ - "int32_t * ptr", - "int32x4_t val", - "const int lane" + "float32_t * ptr", + "float32x2x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -102850,30 +298347,23 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_s64", + "name": "vst1_f64", "arguments": [ - "int64_t * ptr", - "int64x2_t val", - "const int lane" + "float64_t * ptr", + "float64x1_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.2D" + "register": "Vt.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -102884,30 +298374,26 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_s8", + "name": "vst1_f64_x2", "arguments": [ - "int8_t * ptr", - "int8x16_t val", - "const int lane" + "float64_t * ptr", + "float64x1x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.16B" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -102918,30 +298404,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_u16", + "name": "vst1_f64_x3", "arguments": [ - "uint16_t * ptr", - "uint16x8_t val", - "const int lane" + "float64_t * ptr", + "float64x1x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.8H" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -102952,30 +298437,32 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_u32", + "name": "vst1_f64_x4", "arguments": [ - "uint32_t * ptr", - "uint32x4_t val", - "const int lane" + "float64_t * ptr", + "float64x1x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -102986,10 +298473,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_u64", + "name": "vst1_lane_f16", "arguments": [ - "uint64_t * ptr", - "uint64x2_t val", + "float16_t * ptr", + "float16x4_t val", "const int lane" ], "return_type": { @@ -102998,13 +298485,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.2D" + "register": "Vt.4H" } }, "Architectures": [ @@ -103020,10 +298507,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_lane_u8", + "name": "vst1_lane_f32", "arguments": [ - "uint8_t * ptr", - "uint8x16_t val", + "float32_t * ptr", + "float32x2_t val", "const int lane" ], "return_type": { @@ -103032,13 +298519,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 1 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.16B" + "register": "Vt.2S" } }, "Architectures": [ @@ -103054,25 +298541,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p16", + "name": "vst1_lane_f64", "arguments": [ - "poly16_t * ptr", - "poly16x8_t val" + "float64_t * ptr", + "float64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.8H" + "register": "Vt.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -103083,20 +298573,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p16_x2", + "name": "vst1_lane_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x2_t val" + "poly16x4_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.4H" } }, "Architectures": [ @@ -103112,24 +298607,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p16_x3", + "name": "vst1_lane_p64", "arguments": [ - "poly16_t * ptr", - "poly16x8x3_t val" + "poly64_t * ptr", + "poly64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.8H" + "register": "Vt.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103141,20 +298640,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p16_x4", + "name": "vst1_lane_p8", "arguments": [ - "poly16_t * ptr", - "poly16x8x4_t val" + "poly8_t * ptr", + "poly8x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt4.8H" + "register": "Vt.8B" } }, "Architectures": [ @@ -103170,23 +298674,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p64", + "name": "vst1_lane_s16", "arguments": [ - "poly64_t * ptr", - "poly64x2_t val" + "int16_t * ptr", + "int16x4_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.2D" + "register": "Vt.4H" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -103198,23 +298708,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p64_x2", + "name": "vst1_lane_s32", "arguments": [ - "poly64_t * ptr", - "poly64x2x2_t val" + "int32_t * ptr", + "int32x2_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.2S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -103226,20 +298742,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p64_x3", + "name": "vst1_lane_s64", "arguments": [ - "poly64_t * ptr", - "poly64x2x3_t val" + "int64_t * ptr", + "int64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.2D" + "register": "Vt.1D" } }, "Architectures": [ @@ -103255,23 +298776,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p64_x4", + "name": "vst1_lane_s8", "arguments": [ - "poly64_t * ptr", - "poly64x2x4_t val" + "int8_t * ptr", + "int8x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt4.2D" + "register": "Vt.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -103283,20 +298810,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p8", + "name": "vst1_lane_u16", "arguments": [ - "poly8_t * ptr", - "poly8x16_t val" + "uint16_t * ptr", + "uint16x4_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.16B" + "register": "Vt.4H" } }, "Architectures": [ @@ -103312,20 +298844,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p8_x2", + "name": "vst1_lane_u32", "arguments": [ - "poly8_t * ptr", - "poly8x16x2_t val" + "uint32_t * ptr", + "uint32x2_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.2S" } }, "Architectures": [ @@ -103341,20 +298878,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p8_x3", + "name": "vst1_lane_u64", "arguments": [ - "poly8_t * ptr", - "poly8x16x3_t val" + "uint64_t * ptr", + "uint64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.16B" + "register": "Vt.1D" } }, "Architectures": [ @@ -103370,20 +298912,25 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_p8_x4", + "name": "vst1_lane_u8", "arguments": [ - "poly8_t * ptr", - "poly8x16x4_t val" + "uint8_t * ptr", + "uint8x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt4.16B" + "register": "Vt.8B" } }, "Architectures": [ @@ -103399,10 +298946,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s16", + "name": "vst1_mf8_x4", "arguments": [ - "int16_t * ptr", - "int16x8_t val" + "int8_t * ptr", + "int8x8x4_t val" ], "return_type": { "value": "void" @@ -103411,13 +298958,20 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.8H" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -103428,10 +298982,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s16_x2", + "name": "vst1_p16", "arguments": [ - "int16_t * ptr", - "int16x8x2_t val" + "poly16_t * ptr", + "poly16x4_t val" ], "return_type": { "value": "void" @@ -103441,7 +298995,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.4H" } }, "Architectures": [ @@ -103457,10 +299011,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s16_x3", + "name": "vst1_p16_x2", "arguments": [ - "int16_t * ptr", - "int16x8x3_t val" + "poly16_t * ptr", + "poly16x4x2_t val" ], "return_type": { "value": "void" @@ -103469,8 +299023,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -103486,10 +299043,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s16_x4", + "name": "vst1_p16_x3", "arguments": [ - "int16_t * ptr", - "int16x8x4_t val" + "poly16_t * ptr", + "poly16x4x3_t val" ], "return_type": { "value": "void" @@ -103498,8 +299055,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -103515,10 +299078,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s32", + "name": "vst1_p16_x4", "arguments": [ - "int32_t * ptr", - "int32x4_t val" + "poly16_t * ptr", + "poly16x4x4_t val" ], "return_type": { "value": "void" @@ -103527,8 +299090,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.4S" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -103544,10 +299116,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s32_x2", + "name": "vst1_p64", "arguments": [ - "int32_t * ptr", - "int32x4x2_t val" + "poly64_t * ptr", + "poly64x1_t val" ], "return_type": { "value": "void" @@ -103557,11 +299129,10 @@ "register": "Xn" }, "val": { - "register": "Vt2.4S" + "register": "Vt.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103573,10 +299144,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s32_x3", + "name": "vst1_p64_x2", "arguments": [ - "int32_t * ptr", - "int32x4x3_t val" + "poly64_t * ptr", + "poly64x1x2_t val" ], "return_type": { "value": "void" @@ -103585,12 +299156,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103602,10 +299175,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s32_x4", + "name": "vst1_p64_x3", "arguments": [ - "int32_t * ptr", - "int32x4x4_t val" + "poly64_t * ptr", + "poly64x1x3_t val" ], "return_type": { "value": "void" @@ -103614,12 +299187,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103631,10 +299209,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s64", + "name": "vst1_p64_x4", "arguments": [ - "int64_t * ptr", - "int64x2_t val" + "poly64_t * ptr", + "poly64x1x4_t val" ], "return_type": { "value": "void" @@ -103643,12 +299221,20 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", "A32", "A64" ], @@ -103660,10 +299246,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s64_x2", + "name": "vst1_p8", "arguments": [ - "int64_t * ptr", - "int64x2x2_t val" + "poly8_t * ptr", + "poly8x8_t val" ], "return_type": { "value": "void" @@ -103673,7 +299259,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.8B" } }, "Architectures": [ @@ -103689,10 +299275,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s64_x3", + "name": "vst1_p8_x2", "arguments": [ - "int64_t * ptr", - "int64x2x3_t val" + "poly8_t * ptr", + "poly8x8x2_t val" ], "return_type": { "value": "void" @@ -103701,8 +299287,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -103718,10 +299307,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s64_x4", + "name": "vst1_p8_x3", "arguments": [ - "int64_t * ptr", - "int64x2x4_t val" + "poly8_t * ptr", + "poly8x8x3_t val" ], "return_type": { "value": "void" @@ -103730,8 +299319,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -103747,10 +299342,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s8", + "name": "vst1_p8_x4", "arguments": [ - "int8_t * ptr", - "int8x16_t val" + "poly8_t * ptr", + "poly8x8x4_t val" ], "return_type": { "value": "void" @@ -103759,8 +299354,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -103776,10 +299380,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s8_x2", + "name": "vst1_s16", "arguments": [ - "int8_t * ptr", - "int8x16x2_t val" + "int16_t * ptr", + "int16x4_t val" ], "return_type": { "value": "void" @@ -103789,7 +299393,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.4H" } }, "Architectures": [ @@ -103805,10 +299409,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s8_x3", + "name": "vst1_s16_x2", "arguments": [ - "int8_t * ptr", - "int8x16x3_t val" + "int16_t * ptr", + "int16x4x2_t val" ], "return_type": { "value": "void" @@ -103817,8 +299421,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -103834,10 +299441,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_s8_x4", + "name": "vst1_s16_x3", "arguments": [ - "int8_t * ptr", - "int8x16x4_t val" + "int16_t * ptr", + "int16x4x3_t val" ], "return_type": { "value": "void" @@ -103846,8 +299453,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -103863,10 +299476,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u16", + "name": "vst1_s16_x4", "arguments": [ - "uint16_t * ptr", - "uint16x8_t val" + "int16_t * ptr", + "int16x4x4_t val" ], "return_type": { "value": "void" @@ -103875,8 +299488,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -103892,10 +299514,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u16_x2", + "name": "vst1_s32", "arguments": [ - "uint16_t * ptr", - "uint16x8x2_t val" + "int32_t * ptr", + "int32x2_t val" ], "return_type": { "value": "void" @@ -103905,7 +299527,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.2S" } }, "Architectures": [ @@ -103921,10 +299543,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u16_x3", + "name": "vst1_s32_x2", "arguments": [ - "uint16_t * ptr", - "uint16x8x3_t val" + "int32_t * ptr", + "int32x2x2_t val" ], "return_type": { "value": "void" @@ -103933,8 +299555,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -103950,10 +299575,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u16_x4", + "name": "vst1_s32_x3", "arguments": [ - "uint16_t * ptr", - "uint16x8x4_t val" + "int32_t * ptr", + "int32x2x3_t val" ], "return_type": { "value": "void" @@ -103962,8 +299587,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -103979,10 +299610,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u32", + "name": "vst1_s32_x4", "arguments": [ - "uint32_t * ptr", - "uint32x4_t val" + "int32_t * ptr", + "int32x2x4_t val" ], "return_type": { "value": "void" @@ -103991,8 +299622,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -104008,10 +299648,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u32_x2", + "name": "vst1_s64", "arguments": [ - "uint32_t * ptr", - "uint32x4x2_t val" + "int64_t * ptr", + "int64x1_t val" ], "return_type": { "value": "void" @@ -104021,7 +299661,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.4S" + "register": "Vt.1D" } }, "Architectures": [ @@ -104037,10 +299677,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u32_x3", + "name": "vst1_s64_x2", "arguments": [ - "uint32_t * ptr", - "uint32x4x3_t val" + "int64_t * ptr", + "int64x1x2_t val" ], "return_type": { "value": "void" @@ -104049,8 +299689,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -104066,10 +299709,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u32_x4", + "name": "vst1_s64_x3", "arguments": [ - "uint32_t * ptr", - "uint32x4x4_t val" + "int64_t * ptr", + "int64x1x3_t val" ], "return_type": { "value": "void" @@ -104078,8 +299721,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -104095,10 +299744,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u64", + "name": "vst1_s64_x4", "arguments": [ - "uint64_t * ptr", - "uint64x2_t val" + "int64_t * ptr", + "int64x1x4_t val" ], "return_type": { "value": "void" @@ -104107,8 +299756,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -104124,10 +299782,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u64_x2", + "name": "vst1_s8", "arguments": [ - "uint64_t * ptr", - "uint64x2x2_t val" + "int8_t * ptr", + "int8x8_t val" ], "return_type": { "value": "void" @@ -104137,7 +299795,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.8B" } }, "Architectures": [ @@ -104153,10 +299811,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u64_x3", + "name": "vst1_s8_x2", "arguments": [ - "uint64_t * ptr", - "uint64x2x3_t val" + "int8_t * ptr", + "int8x8x2_t val" ], "return_type": { "value": "void" @@ -104165,8 +299823,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -104182,10 +299843,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u64_x4", + "name": "vst1_s8_x3", "arguments": [ - "uint64_t * ptr", - "uint64x2x4_t val" + "int8_t * ptr", + "int8x8x3_t val" ], "return_type": { "value": "void" @@ -104194,8 +299855,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -104211,10 +299878,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u8", + "name": "vst1_s8_x4", "arguments": [ - "uint8_t * ptr", - "uint8x16_t val" + "int8_t * ptr", + "int8x8x4_t val" ], "return_type": { "value": "void" @@ -104223,8 +299890,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -104240,10 +299916,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u8_x2", + "name": "vst1_u16", "arguments": [ - "uint8_t * ptr", - "uint8x16x2_t val" + "uint16_t * ptr", + "uint16x4_t val" ], "return_type": { "value": "void" @@ -104253,7 +299929,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.4H" } }, "Architectures": [ @@ -104269,10 +299945,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u8_x3", + "name": "vst1_u16_x2", "arguments": [ - "uint8_t * ptr", - "uint8x16x3_t val" + "uint16_t * ptr", + "uint16x4x2_t val" ], "return_type": { "value": "void" @@ -104281,8 +299957,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -104298,10 +299977,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst1q_u8_x4", + "name": "vst1_u16_x3", "arguments": [ - "uint8_t * ptr", - "uint8x16x4_t val" + "uint16_t * ptr", + "uint16x4x3_t val" ], "return_type": { "value": "void" @@ -104310,8 +299989,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -104327,10 +300012,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_f16", + "name": "vst1_u16_x4", "arguments": [ - "float16_t * ptr", - "float16x4x2_t val" + "uint16_t * ptr", + "uint16x4x4_t val" ], "return_type": { "value": "void" @@ -104339,8 +300024,17 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -104350,16 +300044,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_f32", + "name": "vst1_u32", "arguments": [ - "float32_t * ptr", - "float32x2x2_t val" + "uint32_t * ptr", + "uint32x2_t val" ], "return_type": { "value": "void" @@ -104369,7 +300063,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.2S" + "register": "Vt.2S" } }, "Architectures": [ @@ -104379,16 +300073,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_f64", + "name": "vst1_u32_x2", "arguments": [ - "float64_t * ptr", - "float64x1x2_t val" + "uint32_t * ptr", + "uint32x2x2_t val" ], "return_type": { "value": "void" @@ -104397,11 +300091,16 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -104412,25 +300111,26 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_f16", + "name": "vst1_u32_x3", "arguments": [ - "float16_t * ptr", - "float16x4x2_t val", - "const int lane" + "uint32_t * ptr", + "uint32x2x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -104440,31 +300140,35 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_f32", + "name": "vst1_u32_x4", "arguments": [ - "float32_t * ptr", - "float32x2x2_t val", - "const int lane" + "uint32_t * ptr", + "uint32x2x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -104474,63 +300178,58 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_f64", + "name": "vst1_u64", "arguments": [ - "float64_t * ptr", - "float64x1x2_t val", - "const int lane" + "uint64_t * ptr", + "uint64x1_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.1D" + "register": "Vt.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_p16", + "name": "vst1_u64_x2", "arguments": [ - "poly16_t * ptr", - "poly16x4x2_t val", - "const int lane" + "uint64_t * ptr", + "uint64x1x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4H" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -104540,63 +300239,70 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_p64", + "name": "vst1_u64_x3", "arguments": [ - "poly64_t * ptr", - "poly64x1x2_t val", - "const int lane" + "uint64_t * ptr", + "uint64x1x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_p8", + "name": "vst1_u64_x4", "arguments": [ - "poly8_t * ptr", - "poly8x8x2_t val", - "const int lane" + "uint64_t * ptr", + "uint64x1x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8B" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -104606,31 +300312,26 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_s16", + "name": "vst1_u8", "arguments": [ - "int16_t * ptr", - "int16x4x2_t val", - "const int lane" + "uint8_t * ptr", + "uint8x8_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.4H" + "register": "Vt.8B" } }, "Architectures": [ @@ -104640,31 +300341,29 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_s32", + "name": "vst1_u8_x2", "arguments": [ - "int32_t * ptr", - "int32x2x2_t val", - "const int lane" + "uint8_t * ptr", + "uint8x8x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2S" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -104674,63 +300373,70 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_s64", + "name": "vst1_u8_x3", "arguments": [ - "int64_t * ptr", - "int64x1x2_t val", - "const int lane" + "uint8_t * ptr", + "uint8x8x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_s8", + "name": "vst1_u8_x4", "arguments": [ - "int8_t * ptr", - "int8x8x2_t val", - "const int lane" + "uint8_t * ptr", + "uint8x8x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -104740,31 +300446,26 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_u16", + "name": "vst1q_f16", "arguments": [ - "uint16_t * ptr", - "uint16x4x2_t val", - "const int lane" + "float16_t * ptr", + "float16x8_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.4H" + "register": "Vt.8H" } }, "Architectures": [ @@ -104774,31 +300475,29 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_u32", + "name": "vst1q_f16_x2", "arguments": [ - "uint32_t * ptr", - "uint32x2x2_t val", - "const int lane" + "float16_t * ptr", + "float16x8x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2S" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -104808,63 +300507,70 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_u64", + "name": "vst1q_f16_x3", "arguments": [ - "uint64_t * ptr", - "uint64x1x2_t val", - "const int lane" + "float16_t * ptr", + "float16x8x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_lane_u8", + "name": "vst1q_f16_x4", "arguments": [ - "uint8_t * ptr", - "uint8x8x2_t val", - "const int lane" + "float16_t * ptr", + "float16x8x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8B" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -104874,16 +300580,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_p16", + "name": "vst1q_f32", "arguments": [ - "poly16_t * ptr", - "poly16x4x2_t val" + "float32_t * ptr", + "float32x4_t val" ], "return_type": { "value": "void" @@ -104893,7 +300599,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.4H" + "register": "Vt.4S" } }, "Architectures": [ @@ -104903,16 +300609,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_p64", + "name": "vst1q_f32_x2", "arguments": [ - "poly64_t * ptr", - "poly64x1x2_t val" + "float32_t * ptr", + "float32x4x2_t val" ], "return_type": { "value": "void" @@ -104921,11 +300627,15 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -104937,10 +300647,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_p8", + "name": "vst1q_f32_x3", "arguments": [ - "poly8_t * ptr", - "poly8x8x2_t val" + "float32_t * ptr", + "float32x4x3_t val" ], "return_type": { "value": "void" @@ -104949,8 +300659,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8B" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ @@ -104960,16 +300676,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_s16", + "name": "vst1q_f32_x4", "arguments": [ - "int16_t * ptr", - "int16x4x2_t val" + "float32_t * ptr", + "float32x4x4_t val" ], "return_type": { "value": "void" @@ -104978,8 +300694,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4H" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -104989,16 +300714,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_s32", + "name": "vst1q_f64", "arguments": [ - "int32_t * ptr", - "int32x2x2_t val" + "float64_t * ptr", + "float64x2_t val" ], "return_type": { "value": "void" @@ -105008,26 +300733,24 @@ "register": "Xn" }, "val": { - "register": "Vt2.2S" + "register": "Vt.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_s64", + "name": "vst1q_f64_x2", "arguments": [ - "int64_t * ptr", - "int64x1x2_t val" + "float64_t * ptr", + "float64x2x2_t val" ], "return_type": { "value": "void" @@ -105036,13 +300759,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ @@ -105053,10 +300777,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_s8", + "name": "vst1q_f64_x3", "arguments": [ - "int8_t * ptr", - "int8x8x2_t val" + "float64_t * ptr", + "float64x2x3_t val" ], "return_type": { "value": "void" @@ -105065,27 +300789,31 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8B" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_u16", + "name": "vst1q_f64_x4", "arguments": [ - "uint16_t * ptr", - "uint16x4x2_t val" + "float64_t * ptr", + "float64x2x4_t val" ], "return_type": { "value": "void" @@ -105094,37 +300822,49 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4H" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_u32", + "name": "vst1q_lane_f16", "arguments": [ - "uint32_t * ptr", - "uint32x2x2_t val" + "float16_t * ptr", + "float16x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2S" + "register": "Vt.8H" } }, "Architectures": [ @@ -105134,26 +300874,31 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2_u64", + "name": "vst1q_lane_f32", "arguments": [ - "uint64_t * ptr", - "uint64x1x2_t val" + "float32_t * ptr", + "float32x4_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.1D" + "register": "Vt.4S" } }, "Architectures": [ @@ -105169,49 +300914,57 @@ }, { "SIMD_ISA": "Neon", - "name": "vst2_u8", + "name": "vst1q_lane_f64", "arguments": [ - "uint8_t * ptr", - "uint8x8x2_t val" + "float64_t * ptr", + "float64x2_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8B" + "register": "Vt.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_f16", + "name": "vst1q_lane_p16", "arguments": [ - "float16_t * ptr", - "float16x8x2_t val" + "poly16_t * ptr", + "poly16x8_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.8H" } }, "Architectures": [ @@ -105221,72 +300974,83 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_f32", + "name": "vst1q_lane_p64", "arguments": [ - "float32_t * ptr", - "float32x4x2_t val" + "poly64_t * ptr", + "poly64x2_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.4S" + "register": "Vt.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_f64", + "name": "vst1q_lane_p8", "arguments": [ - "float64_t * ptr", - "float64x2x2_t val" + "poly8_t * ptr", + "poly8x16_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 15 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_f16", + "name": "vst1q_lane_s16", "arguments": [ - "float16_t * ptr", - "float16x8x2_t val", + "int16_t * ptr", + "int16x8_t val", "const int lane" ], "return_type": { @@ -105301,7 +301065,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.8H" } }, "Architectures": [ @@ -105311,16 +301075,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_f32", + "name": "vst1q_lane_s32", "arguments": [ - "float32_t * ptr", - "float32x4x2_t val", + "int32_t * ptr", + "int32x4_t val", "const int lane" ], "return_type": { @@ -105335,7 +301099,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.4S" + "register": "Vt.4S" } }, "Architectures": [ @@ -105345,16 +301109,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_f64", + "name": "vst1q_lane_s64", "arguments": [ - "float64_t * ptr", - "float64x2x2_t val", + "int64_t * ptr", + "int64x2_t val", "const int lane" ], "return_type": { @@ -105363,30 +301127,32 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 2 + "maximum": 1 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_p16", + "name": "vst1q_lane_s8", "arguments": [ - "poly16_t * ptr", - "poly16x8x2_t val", + "int8_t * ptr", + "int8x16_t val", "const int lane" ], "return_type": { @@ -105395,13 +301161,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.16B" } }, "Architectures": [ @@ -105411,16 +301177,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_p64", + "name": "vst1q_lane_u16", "arguments": [ - "poly64_t * ptr", - "poly64x2x2_t val", + "uint16_t * ptr", + "uint16x8_t val", "const int lane" ], "return_type": { @@ -105429,30 +301195,32 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.2D" + "register": "Vt.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_p8", + "name": "vst1q_lane_u32", "arguments": [ - "poly8_t * ptr", - "poly8x16x2_t val", + "uint32_t * ptr", + "uint32x4_t val", "const int lane" ], "return_type": { @@ -105461,30 +301229,32 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 3 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_s16", + "name": "vst1q_lane_u64", "arguments": [ - "int16_t * ptr", - "int16x8x2_t val", + "uint64_t * ptr", + "uint64x2_t val", "const int lane" ], "return_type": { @@ -105493,13 +301263,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 1 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.2D" } }, "Architectures": [ @@ -105509,16 +301279,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_s32", + "name": "vst1q_lane_u8", "arguments": [ - "int32_t * ptr", - "int32x4x2_t val", + "uint8_t * ptr", + "uint8x16_t val", "const int lane" ], "return_type": { @@ -105527,13 +301297,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 15 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.4S" + "register": "Vt.16B" } }, "Architectures": [ @@ -105543,31 +301313,35 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_s64", + "name": "vst1q_mf8_x4", "arguments": [ - "int64_t * ptr", - "int64x2x2_t val", - "const int lane" + "int8_t * ptr", + "int8x16x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -105575,62 +301349,57 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_s8", + "name": "vst1q_p16", "arguments": [ - "int8_t * ptr", - "int8x16x2_t val", - "const int lane" + "poly16_t * ptr", + "poly16x8_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_u16", + "name": "vst1q_p16_x2", "arguments": [ - "uint16_t * ptr", - "uint16x8x2_t val", - "const int lane" + "poly16_t * ptr", + "poly16x8x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105641,31 +301410,32 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_u32", + "name": "vst1q_p16_x3", "arguments": [ - "uint32_t * ptr", - "uint32x4x2_t val", - "const int lane" + "poly16_t * ptr", + "poly16x8x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4S" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -105675,80 +301445,82 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_u64", + "name": "vst1q_p16_x4", "arguments": [ - "uint64_t * ptr", - "uint64x2x2_t val", - "const int lane" + "poly16_t * ptr", + "poly16x8x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_lane_u8", + "name": "vst1q_p64", "arguments": [ - "uint8_t * ptr", - "uint8x16x2_t val", - "const int lane" + "poly64_t * ptr", + "poly64x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 15 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt2.16B" + "register": "Vt.2D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_p16", + "name": "vst1q_p64_x2", "arguments": [ - "poly16_t * ptr", - "poly16x8x2_t val" + "poly64_t * ptr", + "poly64x2x2_t val" ], "return_type": { "value": "void" @@ -105757,27 +301529,29 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.8H" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_p64", + "name": "vst1q_p64_x3", "arguments": [ "poly64_t * ptr", - "poly64x2x2_t val" + "poly64x2x3_t val" ], "return_type": { "value": "void" @@ -105786,25 +301560,33 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_p8", + "name": "vst1q_p64_x4", "arguments": [ - "poly8_t * ptr", - "poly8x16x2_t val" + "poly64_t * ptr", + "poly64x2x4_t val" ], "return_type": { "value": "void" @@ -105813,27 +301595,35 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.16B" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_s16", + "name": "vst1q_p8", "arguments": [ - "int16_t * ptr", - "int16x8x2_t val" + "poly8_t * ptr", + "poly8x16_t val" ], "return_type": { "value": "void" @@ -105843,7 +301633,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.16B" } }, "Architectures": [ @@ -105853,16 +301643,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_s32", + "name": "vst1q_p8_x2", "arguments": [ - "int32_t * ptr", - "int32x4x2_t val" + "poly8_t * ptr", + "poly8x16x2_t val" ], "return_type": { "value": "void" @@ -105871,8 +301661,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4S" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -105882,16 +301675,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_s64", + "name": "vst1q_p8_x3", "arguments": [ - "int64_t * ptr", - "int64x2x2_t val" + "poly8_t * ptr", + "poly8x16x3_t val" ], "return_type": { "value": "void" @@ -105900,25 +301693,33 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_s8", + "name": "vst1q_p8_x4", "arguments": [ - "int8_t * ptr", - "int8x16x2_t val" + "poly8_t * ptr", + "poly8x16x4_t val" ], "return_type": { "value": "void" @@ -105927,8 +301728,17 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -105938,16 +301748,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_u16", + "name": "vst1q_s16", "arguments": [ - "uint16_t * ptr", - "uint16x8x2_t val" + "int16_t * ptr", + "int16x8_t val" ], "return_type": { "value": "void" @@ -105957,7 +301767,7 @@ "register": "Xn" }, "val": { - "register": "Vt2.8H" + "register": "Vt.8H" } }, "Architectures": [ @@ -105967,16 +301777,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_u32", + "name": "vst1q_s16_x2", "arguments": [ - "uint32_t * ptr", - "uint32x4x2_t val" + "int16_t * ptr", + "int16x8x2_t val" ], "return_type": { "value": "void" @@ -105985,8 +301795,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.4S" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -105996,16 +301809,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_u64", + "name": "vst1q_s16_x3", "arguments": [ - "uint64_t * ptr", - "uint64x2x2_t val" + "int16_t * ptr", + "int16x8x3_t val" ], "return_type": { "value": "void" @@ -106014,25 +301827,33 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.2D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst2q_u8", + "name": "vst1q_s16_x4", "arguments": [ - "uint8_t * ptr", - "uint8x16x2_t val" + "int16_t * ptr", + "int16x8x4_t val" ], "return_type": { "value": "void" @@ -106041,8 +301862,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt2.16B" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -106052,16 +301882,16 @@ ], "instructions": [ [ - "ST2" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_f16", + "name": "vst1q_s32", "arguments": [ - "float16_t * ptr", - "float16x4x3_t val" + "int32_t * ptr", + "int32x4_t val" ], "return_type": { "value": "void" @@ -106071,7 +301901,7 @@ "register": "Xn" }, "val": { - "register": "Vt3.4H" + "register": "Vt.4S" } }, "Architectures": [ @@ -106081,16 +301911,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_f32", + "name": "vst1q_s32_x2", "arguments": [ - "float32_t * ptr", - "float32x2x3_t val" + "int32_t * ptr", + "int32x4x2_t val" ], "return_type": { "value": "void" @@ -106099,8 +301929,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -106110,16 +301943,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_f64", + "name": "vst1q_s32_x3", "arguments": [ - "float64_t * ptr", - "float64x1x3_t val" + "int32_t * ptr", + "int32x4x3_t val" ], "return_type": { "value": "void" @@ -106128,11 +301961,19 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ @@ -106143,25 +301984,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_f16", + "name": "vst1q_s32_x4", "arguments": [ - "float16_t * ptr", - "float16x4x3_t val", - "const int lane" + "int32_t * ptr", + "int32x4x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -106171,31 +302016,26 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_f32", + "name": "vst1q_s64", "arguments": [ - "float32_t * ptr", - "float32x2x3_t val", - "const int lane" + "int64_t * ptr", + "int64x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.2S" + "register": "Vt.2D" } }, "Architectures": [ @@ -106205,63 +302045,64 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_f64", + "name": "vst1q_s64_x2", "arguments": [ - "float64_t * ptr", - "float64x1x3_t val", - "const int lane" + "int64_t * ptr", + "int64x2x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_p16", + "name": "vst1q_s64_x3", "arguments": [ - "poly16_t * ptr", - "poly16x4x3_t val", - "const int lane" + "int64_t * ptr", + "int64x2x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -106271,63 +302112,64 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_p64", + "name": "vst1q_s64_x4", "arguments": [ - "poly64_t * ptr", - "poly64x1x3_t val", - "const int lane" + "int64_t * ptr", + "int64x2x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_p8", + "name": "vst1q_s8", "arguments": [ - "poly8_t * ptr", - "poly8x8x3_t val", - "const int lane" + "int8_t * ptr", + "int8x16_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.8B" + "register": "Vt.16B" } }, "Architectures": [ @@ -106337,31 +302179,29 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_s16", + "name": "vst1q_s8_x2", "arguments": [ - "int16_t * ptr", - "int16x4x3_t val", - "const int lane" + "int8_t * ptr", + "int8x16x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -106371,31 +302211,32 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_s32", + "name": "vst1q_s8_x3", "arguments": [ - "int32_t * ptr", - "int32x2x3_t val", - "const int lane" + "int8_t * ptr", + "int8x16x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ @@ -106405,63 +302246,64 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_s64", + "name": "vst1q_s8_x4", "arguments": [ - "int64_t * ptr", - "int64x1x3_t val", - "const int lane" + "int8_t * ptr", + "int8x16x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_s8", + "name": "vst1q_u16", "arguments": [ - "int8_t * ptr", - "int8x8x3_t val", - "const int lane" + "uint16_t * ptr", + "uint16x8_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.8B" + "register": "Vt.8H" } }, "Architectures": [ @@ -106471,31 +302313,29 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_u16", + "name": "vst1q_u16_x2", "arguments": [ "uint16_t * ptr", - "uint16x4x3_t val", - "const int lane" + "uint16x8x2_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 3 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -106505,31 +302345,32 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_u32", + "name": "vst1q_u16_x3", "arguments": [ - "uint32_t * ptr", - "uint32x2x3_t val", - "const int lane" + "uint16_t * ptr", + "uint16x8x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -106539,63 +302380,64 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_u64", + "name": "vst1q_u16_x4", "arguments": [ - "uint64_t * ptr", - "uint64x1x3_t val", - "const int lane" + "uint16_t * ptr", + "uint16x8x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_lane_u8", + "name": "vst1q_u32", "arguments": [ - "uint8_t * ptr", - "uint8x8x3_t val", - "const int lane" + "uint32_t * ptr", + "uint32x4_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 7 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt3.8B" + "register": "Vt.4S" } }, "Architectures": [ @@ -106605,16 +302447,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_p16", + "name": "vst1q_u32_x2", "arguments": [ - "poly16_t * ptr", - "poly16x4x3_t val" + "uint32_t * ptr", + "uint32x4x2_t val" ], "return_type": { "value": "void" @@ -106623,8 +302465,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4H" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -106634,16 +302479,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_p64", + "name": "vst1q_u32_x3", "arguments": [ - "poly64_t * ptr", - "poly64x1x3_t val" + "uint32_t * ptr", + "uint32x4x3_t val" ], "return_type": { "value": "void" @@ -106652,11 +302497,18 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], @@ -106668,10 +302520,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst3_p8", + "name": "vst1q_u32_x4", "arguments": [ - "poly8_t * ptr", - "poly8x8x3_t val" + "uint32_t * ptr", + "uint32x4x4_t val" ], "return_type": { "value": "void" @@ -106680,8 +302532,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8B" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -106691,16 +302552,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_s16", + "name": "vst1q_u64", "arguments": [ - "int16_t * ptr", - "int16x4x3_t val" + "uint64_t * ptr", + "uint64x2_t val" ], "return_type": { "value": "void" @@ -106710,7 +302571,7 @@ "register": "Xn" }, "val": { - "register": "Vt3.4H" + "register": "Vt.2D" } }, "Architectures": [ @@ -106720,16 +302581,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_s32", + "name": "vst1q_u64_x2", "arguments": [ - "int32_t * ptr", - "int32x2x3_t val" + "uint64_t * ptr", + "uint64x2x2_t val" ], "return_type": { "value": "void" @@ -106738,8 +302599,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -106749,16 +302613,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_s64", + "name": "vst1q_u64_x3", "arguments": [ - "int64_t * ptr", - "int64x1x3_t val" + "uint64_t * ptr", + "uint64x2x3_t val" ], "return_type": { "value": "void" @@ -106767,8 +302631,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -106784,10 +302654,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst3_s8", + "name": "vst1q_u64_x4", "arguments": [ - "int8_t * ptr", - "int8x8x3_t val" + "uint64_t * ptr", + "uint64x2x4_t val" ], "return_type": { "value": "void" @@ -106796,8 +302666,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8B" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ @@ -106807,16 +302686,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_u16", + "name": "vst1q_u8", "arguments": [ - "uint16_t * ptr", - "uint16x4x3_t val" + "uint8_t * ptr", + "uint8x16_t val" ], "return_type": { "value": "void" @@ -106826,7 +302705,7 @@ "register": "Xn" }, "val": { - "register": "Vt3.4H" + "register": "Vt.16B" } }, "Architectures": [ @@ -106836,16 +302715,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_u32", + "name": "vst1q_u8_x2", "arguments": [ - "uint32_t * ptr", - "uint32x2x3_t val" + "uint8_t * ptr", + "uint8x16x2_t val" ], "return_type": { "value": "void" @@ -106854,8 +302733,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2S" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -106865,16 +302747,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3_u64", + "name": "vst1q_u8_x3", "arguments": [ - "uint64_t * ptr", - "uint64x1x3_t val" + "uint8_t * ptr", + "uint8x16x3_t val" ], "return_type": { "value": "void" @@ -106883,8 +302765,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.1D" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ @@ -106900,10 +302788,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vst3_u8", + "name": "vst1q_u8_x4", "arguments": [ "uint8_t * ptr", - "uint8x8x3_t val" + "uint8x16x4_t val" ], "return_type": { "value": "void" @@ -106912,8 +302800,17 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -106923,16 +302820,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_f16", + "name": "vst2_f16", "arguments": [ "float16_t * ptr", - "float16x8x3_t val" + "float16x4x2_t val" ], "return_type": { "value": "void" @@ -106941,8 +302838,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -106952,16 +302852,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_f32", + "name": "vst2_f32", "arguments": [ "float32_t * ptr", - "float32x4x3_t val" + "float32x2x2_t val" ], "return_type": { "value": "void" @@ -106970,8 +302870,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -106981,16 +302884,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_f64", + "name": "vst2_f64", "arguments": [ "float64_t * ptr", - "float64x2x3_t val" + "float64x1x2_t val" ], "return_type": { "value": "void" @@ -106999,8 +302902,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107008,16 +302914,16 @@ ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_f16", + "name": "vst2_lane_f16", "arguments": [ "float16_t * ptr", - "float16x8x3_t val", + "float16x4x2_t val", "const int lane" ], "return_type": { @@ -107026,13 +302932,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107042,16 +302951,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_f32", + "name": "vst2_lane_f32", "arguments": [ "float32_t * ptr", - "float32x4x3_t val", + "float32x2x2_t val", "const int lane" ], "return_type": { @@ -107060,13 +302969,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107076,16 +302988,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_f64", + "name": "vst2_lane_f64", "arguments": [ "float64_t * ptr", - "float64x2x3_t val", + "float64x1x2_t val", "const int lane" ], "return_type": { @@ -107094,13 +303006,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107108,16 +303023,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_p16", + "name": "vst2_lane_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x3_t val", + "poly16x4x2_t val", "const int lane" ], "return_type": { @@ -107126,13 +303041,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107142,16 +303060,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_p64", + "name": "vst2_lane_p64", "arguments": [ "poly64_t * ptr", - "poly64x2x3_t val", + "poly64x1x2_t val", "const int lane" ], "return_type": { @@ -107160,13 +303078,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107174,16 +303095,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_p8", + "name": "vst2_lane_p8", "arguments": [ "poly8_t * ptr", - "poly8x16x3_t val", + "poly8x8x2_t val", "const int lane" ], "return_type": { @@ -107192,13 +303113,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107208,16 +303132,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_s16", + "name": "vst2_lane_s16", "arguments": [ "int16_t * ptr", - "int16x8x3_t val", + "int16x4x2_t val", "const int lane" ], "return_type": { @@ -107226,13 +303150,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107242,16 +303169,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_s32", + "name": "vst2_lane_s32", "arguments": [ "int32_t * ptr", - "int32x4x3_t val", + "int32x2x2_t val", "const int lane" ], "return_type": { @@ -107260,13 +303187,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107276,16 +303206,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_s64", + "name": "vst2_lane_s64", "arguments": [ "int64_t * ptr", - "int64x2x3_t val", + "int64x1x2_t val", "const int lane" ], "return_type": { @@ -107294,13 +303224,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107308,16 +303241,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_s8", + "name": "vst2_lane_s8", "arguments": [ "int8_t * ptr", - "int8x16x3_t val", + "int8x8x2_t val", "const int lane" ], "return_type": { @@ -107326,13 +303259,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107342,16 +303278,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_u16", + "name": "vst2_lane_u16", "arguments": [ "uint16_t * ptr", - "uint16x8x3_t val", + "uint16x4x2_t val", "const int lane" ], "return_type": { @@ -107360,13 +303296,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107376,16 +303315,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_u32", + "name": "vst2_lane_u32", "arguments": [ "uint32_t * ptr", - "uint32x4x3_t val", + "uint32x2x2_t val", "const int lane" ], "return_type": { @@ -107394,13 +303333,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107410,16 +303352,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_u64", + "name": "vst2_lane_u64", "arguments": [ "uint64_t * ptr", - "uint64x2x3_t val", + "uint64x1x2_t val", "const int lane" ], "return_type": { @@ -107428,13 +303370,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ @@ -107442,16 +303387,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_lane_u8", + "name": "vst2_lane_u8", "arguments": [ "uint8_t * ptr", - "uint8x16x3_t val", + "uint8x8x2_t val", "const int lane" ], "return_type": { @@ -107460,13 +303405,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107476,16 +303424,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_p16", + "name": "vst2_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x3_t val" + "poly16x4x2_t val" ], "return_type": { "value": "void" @@ -107494,8 +303442,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107505,16 +303456,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_p64", + "name": "vst2_p64", "arguments": [ "poly64_t * ptr", - "poly64x2x3_t val" + "poly64x1x2_t val" ], "return_type": { "value": "void" @@ -107523,25 +303474,29 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_p8", + "name": "vst2_p8", "arguments": [ "poly8_t * ptr", - "poly8x16x3_t val" + "poly8x8x2_t val" ], "return_type": { "value": "void" @@ -107550,8 +303505,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107561,16 +303519,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_s16", + "name": "vst2_s16", "arguments": [ "int16_t * ptr", - "int16x8x3_t val" + "int16x4x2_t val" ], "return_type": { "value": "void" @@ -107579,8 +303537,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107590,16 +303551,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_s32", + "name": "vst2_s32", "arguments": [ "int32_t * ptr", - "int32x4x3_t val" + "int32x2x2_t val" ], "return_type": { "value": "void" @@ -107608,8 +303569,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107619,16 +303583,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_s64", + "name": "vst2_s64", "arguments": [ "int64_t * ptr", - "int64x2x3_t val" + "int64x1x2_t val" ], "return_type": { "value": "void" @@ -107637,25 +303601,30 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_s8", + "name": "vst2_s8", "arguments": [ "int8_t * ptr", - "int8x16x3_t val" + "int8x8x2_t val" ], "return_type": { "value": "void" @@ -107664,8 +303633,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107675,16 +303647,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_u16", + "name": "vst2_u16", "arguments": [ "uint16_t * ptr", - "uint16x8x3_t val" + "uint16x4x2_t val" ], "return_type": { "value": "void" @@ -107693,8 +303665,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" } }, "Architectures": [ @@ -107704,16 +303679,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_u32", + "name": "vst2_u32", "arguments": [ "uint32_t * ptr", - "uint32x4x3_t val" + "uint32x2x2_t val" ], "return_type": { "value": "void" @@ -107722,8 +303697,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" } }, "Architectures": [ @@ -107733,16 +303711,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_u64", + "name": "vst2_u64", "arguments": [ "uint64_t * ptr", - "uint64x2x3_t val" + "uint64x1x2_t val" ], "return_type": { "value": "void" @@ -107751,25 +303729,30 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST3" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst3q_u8", + "name": "vst2_u8", "arguments": [ "uint8_t * ptr", - "uint8x16x3_t val" + "uint8x8x2_t val" ], "return_type": { "value": "void" @@ -107778,8 +303761,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt3.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" } }, "Architectures": [ @@ -107789,16 +303775,16 @@ ], "instructions": [ [ - "ST3" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_f16", + "name": "vst2q_f16", "arguments": [ "float16_t * ptr", - "float16x4x4_t val" + "float16x8x2_t val" ], "return_type": { "value": "void" @@ -107807,8 +303793,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -107818,16 +303807,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_f32", + "name": "vst2q_f32", "arguments": [ "float32_t * ptr", - "float32x2x4_t val" + "float32x4x2_t val" ], "return_type": { "value": "void" @@ -107836,8 +303825,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -107847,16 +303839,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_f64", + "name": "vst2q_f64", "arguments": [ "float64_t * ptr", - "float64x1x4_t val" + "float64x2x2_t val" ], "return_type": { "value": "void" @@ -107865,8 +303857,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -107874,16 +303869,16 @@ ], "instructions": [ [ - "ST1" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_f16", + "name": "vst2q_lane_f16", "arguments": [ "float16_t * ptr", - "float16x4x4_t val", + "float16x8x2_t val", "const int lane" ], "return_type": { @@ -107892,13 +303887,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -107908,16 +303906,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_f32", + "name": "vst2q_lane_f32", "arguments": [ "float32_t * ptr", - "float32x2x4_t val", + "float32x4x2_t val", "const int lane" ], "return_type": { @@ -107926,13 +303924,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -107942,16 +303943,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_f64", + "name": "vst2q_lane_f64", "arguments": [ "float64_t * ptr", - "float64x1x4_t val", + "float64x2x2_t val", "const int lane" ], "return_type": { @@ -107960,13 +303961,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -107974,16 +303978,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_p16", + "name": "vst2q_lane_p16", "arguments": [ "poly16_t * ptr", - "poly16x4x4_t val", + "poly16x8x2_t val", "const int lane" ], "return_type": { @@ -107992,13 +303996,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108008,16 +304015,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_p64", + "name": "vst2q_lane_p64", "arguments": [ "poly64_t * ptr", - "poly64x1x4_t val", + "poly64x2x2_t val", "const int lane" ], "return_type": { @@ -108026,13 +304033,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -108040,16 +304050,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_p8", + "name": "vst2q_lane_p8", "arguments": [ "poly8_t * ptr", - "poly8x8x4_t val", + "poly8x16x2_t val", "const int lane" ], "return_type": { @@ -108058,32 +304068,33 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_s16", + "name": "vst2q_lane_s16", "arguments": [ "int16_t * ptr", - "int16x4x4_t val", + "int16x8x2_t val", "const int lane" ], "return_type": { @@ -108092,13 +304103,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108108,16 +304122,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_s32", + "name": "vst2q_lane_s32", "arguments": [ "int32_t * ptr", - "int32x2x4_t val", + "int32x4x2_t val", "const int lane" ], "return_type": { @@ -108126,13 +304140,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -108142,16 +304159,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_s64", + "name": "vst2q_lane_s64", "arguments": [ "int64_t * ptr", - "int64x1x4_t val", + "int64x2x2_t val", "const int lane" ], "return_type": { @@ -108160,13 +304177,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -108174,16 +304194,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_s8", + "name": "vst2q_lane_s8", "arguments": [ "int8_t * ptr", - "int8x8x4_t val", + "int8x16x2_t val", "const int lane" ], "return_type": { @@ -108192,32 +304212,33 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_u16", + "name": "vst2q_lane_u16", "arguments": [ "uint16_t * ptr", - "uint16x4x4_t val", + "uint16x8x2_t val", "const int lane" ], "return_type": { @@ -108226,13 +304247,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108242,16 +304266,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_u32", + "name": "vst2q_lane_u32", "arguments": [ "uint32_t * ptr", - "uint32x2x4_t val", + "uint32x4x2_t val", "const int lane" ], "return_type": { @@ -108260,13 +304284,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -108276,16 +304303,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_u64", + "name": "vst2q_lane_u64", "arguments": [ "uint64_t * ptr", - "uint64x1x4_t val", + "uint64x2x2_t val", "const int lane" ], "return_type": { @@ -108294,13 +304321,16 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ @@ -108308,16 +304338,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_lane_u8", + "name": "vst2q_lane_u8", "arguments": [ "uint8_t * ptr", - "uint8x8x4_t val", + "uint8x16x2_t val", "const int lane" ], "return_type": { @@ -108326,32 +304356,33 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 15 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_p16", + "name": "vst2q_p16", "arguments": [ "poly16_t * ptr", - "poly16x4x4_t val" + "poly16x8x2_t val" ], "return_type": { "value": "void" @@ -108360,8 +304391,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108371,16 +304405,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_p64", + "name": "vst2q_p64", "arguments": [ "poly64_t * ptr", - "poly64x1x4_t val" + "poly64x2x2_t val" ], "return_type": { "value": "void" @@ -108389,26 +304423,28 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "ST1" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_p8", + "name": "vst2q_p8", "arguments": [ "poly8_t * ptr", - "poly8x8x4_t val" + "poly8x16x2_t val" ], "return_type": { "value": "void" @@ -108417,8 +304453,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -108428,16 +304467,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_s16", + "name": "vst2q_s16", "arguments": [ "int16_t * ptr", - "int16x4x4_t val" + "int16x8x2_t val" ], "return_type": { "value": "void" @@ -108446,8 +304485,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108457,16 +304499,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_s32", + "name": "vst2q_s32", "arguments": [ "int32_t * ptr", - "int32x2x4_t val" + "int32x4x2_t val" ], "return_type": { "value": "void" @@ -108475,8 +304517,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -108486,16 +304531,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_s64", + "name": "vst2q_s64", "arguments": [ "int64_t * ptr", - "int64x1x4_t val" + "int64x2x2_t val" ], "return_type": { "value": "void" @@ -108504,27 +304549,28 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_s8", + "name": "vst2q_s8", "arguments": [ "int8_t * ptr", - "int8x8x4_t val" + "int8x16x2_t val" ], "return_type": { "value": "void" @@ -108533,8 +304579,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -108544,16 +304593,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_u16", + "name": "vst2q_u16", "arguments": [ "uint16_t * ptr", - "uint16x4x4_t val" + "uint16x8x2_t val" ], "return_type": { "value": "void" @@ -108562,8 +304611,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4H" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" } }, "Architectures": [ @@ -108573,16 +304625,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_u32", + "name": "vst2q_u32", "arguments": [ "uint32_t * ptr", - "uint32x2x4_t val" + "uint32x4x2_t val" ], "return_type": { "value": "void" @@ -108591,8 +304643,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2S" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" } }, "Architectures": [ @@ -108602,16 +304657,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_u64", + "name": "vst2q_u64", "arguments": [ "uint64_t * ptr", - "uint64x1x4_t val" + "uint64x2x2_t val" ], "return_type": { "value": "void" @@ -108620,27 +304675,28 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "ST1" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4_u8", + "name": "vst2q_u8", "arguments": [ "uint8_t * ptr", - "uint8x8x4_t val" + "uint8x16x2_t val" ], "return_type": { "value": "void" @@ -108649,8 +304705,11 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8B" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" } }, "Architectures": [ @@ -108660,16 +304719,16 @@ ], "instructions": [ [ - "ST4" + "ST2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_f16", + "name": "vst3_f16", "arguments": [ "float16_t * ptr", - "float16x8x4_t val" + "float16x4x3_t val" ], "return_type": { "value": "void" @@ -108678,8 +304737,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -108689,16 +304754,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_f32", + "name": "vst3_f32", "arguments": [ "float32_t * ptr", - "float32x4x4_t val" + "float32x2x3_t val" ], "return_type": { "value": "void" @@ -108707,8 +304772,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -108718,16 +304789,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_f64", + "name": "vst3_f64", "arguments": [ "float64_t * ptr", - "float64x2x4_t val" + "float64x1x3_t val" ], "return_type": { "value": "void" @@ -108736,8 +304807,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -108745,16 +304822,16 @@ ], "instructions": [ [ - "ST4" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_f16", + "name": "vst3_lane_f16", "arguments": [ "float16_t * ptr", - "float16x8x4_t val", + "float16x4x3_t val", "const int lane" ], "return_type": { @@ -108763,13 +304840,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -108779,16 +304862,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_f32", + "name": "vst3_lane_f32", "arguments": [ "float32_t * ptr", - "float32x4x4_t val", + "float32x2x3_t val", "const int lane" ], "return_type": { @@ -108797,13 +304880,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -108813,16 +304902,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_f64", + "name": "vst3_lane_f64", "arguments": [ "float64_t * ptr", - "float64x2x4_t val", + "float64x1x3_t val", "const int lane" ], "return_type": { @@ -108831,13 +304920,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -108845,16 +304940,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_p16", + "name": "vst3_lane_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x4_t val", + "poly16x4x3_t val", "const int lane" ], "return_type": { @@ -108863,13 +304958,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -108879,16 +304980,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_p64", + "name": "vst3_lane_p64", "arguments": [ "poly64_t * ptr", - "poly64x2x4_t val", + "poly64x1x3_t val", "const int lane" ], "return_type": { @@ -108897,13 +304998,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -108911,16 +305018,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_p8", + "name": "vst3_lane_p8", "arguments": [ "poly8_t * ptr", - "poly8x16x4_t val", + "poly8x8x3_t val", "const int lane" ], "return_type": { @@ -108929,30 +305036,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_s16", + "name": "vst3_lane_s16", "arguments": [ "int16_t * ptr", - "int16x8x4_t val", + "int16x4x3_t val", "const int lane" ], "return_type": { @@ -108961,13 +305076,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -108977,16 +305098,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_s32", + "name": "vst3_lane_s32", "arguments": [ "int32_t * ptr", - "int32x4x4_t val", + "int32x2x3_t val", "const int lane" ], "return_type": { @@ -108995,13 +305116,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -109011,16 +305138,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_s64", + "name": "vst3_lane_s64", "arguments": [ "int64_t * ptr", - "int64x2x4_t val", + "int64x1x3_t val", "const int lane" ], "return_type": { @@ -109029,13 +305156,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -109043,16 +305176,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_s8", + "name": "vst3_lane_s8", "arguments": [ "int8_t * ptr", - "int8x16x4_t val", + "int8x8x3_t val", "const int lane" ], "return_type": { @@ -109061,30 +305194,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_u16", + "name": "vst3_lane_u16", "arguments": [ "uint16_t * ptr", - "uint16x8x4_t val", + "uint16x4x3_t val", "const int lane" ], "return_type": { @@ -109093,13 +305234,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 7 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -109109,16 +305256,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_u32", + "name": "vst3_lane_u32", "arguments": [ "uint32_t * ptr", - "uint32x4x4_t val", + "uint32x2x3_t val", "const int lane" ], "return_type": { @@ -109127,13 +305274,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 3 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -109143,16 +305296,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_u64", + "name": "vst3_lane_u64", "arguments": [ "uint64_t * ptr", - "uint64x2x4_t val", + "uint64x1x3_t val", "const int lane" ], "return_type": { @@ -109161,13 +305314,19 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 0 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ @@ -109175,16 +305334,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_lane_u8", + "name": "vst3_lane_u8", "arguments": [ "uint8_t * ptr", - "uint8x16x4_t val", + "uint8x8x3_t val", "const int lane" ], "return_type": { @@ -109193,30 +305352,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 15 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_p16", + "name": "vst3_p16", "arguments": [ "poly16_t * ptr", - "poly16x8x4_t val" + "poly16x4x3_t val" ], "return_type": { "value": "void" @@ -109225,8 +305392,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -109236,16 +305409,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_p64", + "name": "vst3_p64", "arguments": [ "poly64_t * ptr", - "poly64x2x4_t val" + "poly64x1x3_t val" ], "return_type": { "value": "void" @@ -109254,25 +305427,32 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_p8", + "name": "vst3_p8", "arguments": [ "poly8_t * ptr", - "poly8x16x4_t val" + "poly8x8x3_t val" ], "return_type": { "value": "void" @@ -109281,8 +305461,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -109292,16 +305478,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_s16", + "name": "vst3_s16", "arguments": [ "int16_t * ptr", - "int16x8x4_t val" + "int16x4x3_t val" ], "return_type": { "value": "void" @@ -109310,8 +305496,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -109321,16 +305513,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_s32", + "name": "vst3_s32", "arguments": [ "int32_t * ptr", - "int32x4x4_t val" + "int32x2x3_t val" ], "return_type": { "value": "void" @@ -109339,8 +305531,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -109350,16 +305548,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_s64", + "name": "vst3_s64", "arguments": [ "int64_t * ptr", - "int64x2x4_t val" + "int64x1x3_t val" ], "return_type": { "value": "void" @@ -109368,25 +305566,33 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_s8", + "name": "vst3_s8", "arguments": [ "int8_t * ptr", - "int8x16x4_t val" + "int8x8x3_t val" ], "return_type": { "value": "void" @@ -109395,8 +305601,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -109406,16 +305618,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_u16", + "name": "vst3_u16", "arguments": [ "uint16_t * ptr", - "uint16x8x4_t val" + "uint16x4x3_t val" ], "return_type": { "value": "void" @@ -109424,8 +305636,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" } }, "Architectures": [ @@ -109435,16 +305653,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_u32", + "name": "vst3_u32", "arguments": [ "uint32_t * ptr", - "uint32x4x4_t val" + "uint32x2x3_t val" ], "return_type": { "value": "void" @@ -109453,8 +305671,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" } }, "Architectures": [ @@ -109464,16 +305688,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_u64", + "name": "vst3_u64", "arguments": [ "uint64_t * ptr", - "uint64x2x4_t val" + "uint64x1x3_t val" ], "return_type": { "value": "void" @@ -109482,25 +305706,33 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "ST4" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vst4q_u8", + "name": "vst3_u8", "arguments": [ "uint8_t * ptr", - "uint8x16x4_t val" + "uint8x8x3_t val" ], "return_type": { "value": "void" @@ -109509,8 +305741,14 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Vt4.16B" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" } }, "Architectures": [ @@ -109520,16 +305758,16 @@ ], "instructions": [ [ - "ST4" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstrq_p128", + "name": "vst3q_f16", "arguments": [ - "poly128_t * ptr", - "poly128_t val" + "float16_t * ptr", + "float16x8x3_t val" ], "return_type": { "value": "void" @@ -109538,105 +305776,84 @@ "ptr": { "register": "Xn" }, - "val": { - "register": "Qt" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "STR" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_f64", + "name": "vst3q_f32", "arguments": [ - "float64_t * ptr", - "float64x1_t val", - "const int lane" + "float32_t * ptr", + "float32x4x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "STL1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vstl1q_lane_f64", - "arguments": [ - "float64_t * ptr", - "float64x2_t val", - "const int lane" - ], - "return_type": { - "value": "void" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 + "val.val[0]": { + "register": "Vt.4S" }, - "ptr": { - "register": "Xn" + "val.val[1]": { + "register": "Vt2.4S" }, - "val": { - "register": "Vt.2D" + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_p64", + "name": "vst3q_f64", "arguments": [ - "poly64_t * ptr", - "poly64x1_t val", - "const int lane" + "float64_t * ptr", + "float64x2x3_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.1D" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -109644,16 +305861,16 @@ ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1q_lane_p64", + "name": "vst3q_lane_f16", "arguments": [ - "poly64_t * ptr", - "poly64x2_t val", + "float16_t * ptr", + "float16x8x3_t val", "const int lane" ], "return_type": { @@ -109662,30 +305879,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.2D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_u64", + "name": "vst3q_lane_f32", "arguments": [ - "uint64_t * ptr", - "uint64x1_t val", + "float32_t * ptr", + "float32x4x3_t val", "const int lane" ], "return_type": { @@ -109694,30 +305919,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 3 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.1D" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1q_lane_u64", + "name": "vst3q_lane_f64", "arguments": [ - "uint64_t * ptr", - "uint64x2_t val", + "float64_t * ptr", + "float64x2x3_t val", "const int lane" ], "return_type": { @@ -109731,8 +305964,14 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -109740,16 +305979,16 @@ ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_s64", + "name": "vst3q_lane_p16", "arguments": [ - "int64_t * ptr", - "int64x1_t val", + "poly16_t * ptr", + "poly16x8x3_t val", "const int lane" ], "return_type": { @@ -109758,30 +305997,38 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 7 }, "ptr": { "register": "Xn" }, - "val": { - "register": "Vt.1D" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1q_lane_s64", + "name": "vst3q_lane_p64", "arguments": [ - "int64_t * ptr", - "int64x2_t val", + "poly64_t * ptr", + "poly64x2x3_t val", "const int lane" ], "return_type": { @@ -109795,8 +306042,14 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -109804,54 +306057,77 @@ ], "instructions": [ [ - "STL1" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_f16", + "name": "vst3q_lane_p8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly8_t * ptr", + "poly8x16x3_t val", + "const int lane" ], "return_type": { - "value": "float16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FSUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_f32", + "name": "vst3q_lane_s16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int16_t * ptr", + "int16x8x3_t val", + "const int lane" ], "return_type": { - "value": "float32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -109861,82 +306137,115 @@ ], "instructions": [ [ - "FSUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_f64", + "name": "vst3q_lane_s32", "arguments": [ - "float64x1_t a", - "float64x1_t b" + "int32_t * ptr", + "int32x4x3_t val", + "const int lane" ], "return_type": { - "value": "float64x1_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Dm" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_s16", + "name": "vst3q_lane_s64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int64_t * ptr", + "int64x2x3_t val", + "const int lane" ], "return_type": { - "value": "int16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_s32", + "name": "vst3q_lane_s8", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "int8_t * ptr", + "int8x16x3_t val", + "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ @@ -109946,26 +306255,37 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_s64", + "name": "vst3q_lane_u16", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "uint16_t * ptr", + "uint16x8x3_t val", + "const int lane" ], "return_type": { - "value": "int64x1_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Dm" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -109975,26 +306295,37 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_s8", + "name": "vst3q_lane_u32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint32_t * ptr", + "uint32x4x3_t val", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ @@ -110004,55 +306335,75 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_u16", + "name": "vst3q_lane_u64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint64_t * ptr", + "uint64x2x3_t val", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_u32", + "name": "vst3q_lane_u8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint8_t * ptr", + "uint8x16x3_t val", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ @@ -110062,26 +306413,32 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_u64", + "name": "vst3q_p16", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "poly16_t * ptr", + "poly16x8x3_t val" ], "return_type": { - "value": "uint64x1_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Dm" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ @@ -110091,141 +306448,170 @@ ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsub_u8", + "name": "vst3q_p64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly64_t * ptr", + "poly64x2x3_t val" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8B" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubd_s64", + "name": "vst3q_p8", "arguments": [ - "int64_t a", - "int64_t b" + "poly8_t * ptr", + "poly8x16x3_t val" ], "return_type": { - "value": "int64_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Dm" + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubd_u64", + "name": "vst3q_s16", "arguments": [ - "uint64_t a", - "uint64_t b" + "int16_t * ptr", + "int16x8x3_t val" ], "return_type": { - "value": "uint64_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Dm" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubh_f16", + "name": "vst3q_s32", "arguments": [ - "float16_t a", - "float16_t b" + "int32_t * ptr", + "int32x4x3_t val" ], "return_type": { - "value": "float16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Hn" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Hm" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "FSUB" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_s16", + "name": "vst3q_s64", "arguments": [ - "int8x8_t r", - "int16x8_t a", - "int16x8_t b" + "int64_t * ptr", + "int64x2x3_t val" ], "return_type": { - "value": "int8x16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.2D" }, - "r": { - "register": "Vd.8B" + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -110233,123 +306619,137 @@ ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_s32", + "name": "vst3q_s8", "arguments": [ - "int16x4_t r", - "int32x4_t a", - "int32x4_t b" + "int8_t * ptr", + "int8x16x3_t val" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.16B" }, - "r": { - "register": "Vd.4H" + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_s64", + "name": "vst3q_u16", "arguments": [ - "int32x2_t r", - "int64x2_t a", - "int64x2_t b" + "uint16_t * ptr", + "uint16x8x3_t val" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.8H" }, - "r": { - "register": "Vd.2S" + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_u16", + "name": "vst3q_u32", "arguments": [ - "uint8x8_t r", - "uint16x8_t a", - "uint16x8_t b" + "uint32_t * ptr", + "uint32x4x3_t val" ], "return_type": { - "value": "uint8x16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.4S" }, - "r": { - "register": "Vd.8B" + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_u32", + "name": "vst3q_u64", "arguments": [ - "uint16x4_t r", - "uint32x4_t a", - "uint32x4_t b" + "uint64_t * ptr", + "uint64x2x3_t val" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.2D" }, - "r": { - "register": "Vd.4H" + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" } }, "Architectures": [ @@ -110357,57 +306757,70 @@ ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_high_u64", + "name": "vst3q_u8", "arguments": [ - "uint32x2_t r", - "uint64x2_t a", - "uint64x2_t b" + "uint8_t * ptr", + "uint8x16x3_t val" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.16B" }, - "r": { - "register": "Vd.2S" + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUBHN2" + "ST3" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_s16", + "name": "vst4_f16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "float16_t * ptr", + "float16x4x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -110417,26 +306830,35 @@ ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_s32", + "name": "vst4_f32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "float32_t * ptr", + "float32x2x4_t val" ], "return_type": { - "value": "int16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -110446,55 +306868,76 @@ ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_s64", + "name": "vst4_f64", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "float64_t * ptr", + "float64x1x4_t val" ], "return_type": { - "value": "int32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUBHN" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_u16", + "name": "vst4_lane_f16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "float16_t * ptr", + "float16x4x4_t val", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -110504,26 +306947,40 @@ ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_u32", + "name": "vst4_lane_f32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "float32_t * ptr", + "float32x2x4_t val", + "const int lane" ], "return_type": { - "value": "uint16x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -110533,82 +306990,124 @@ ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubhn_u64", + "name": "vst4_lane_f64", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "float64_t * ptr", + "float64x1x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.2D" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SUBHN" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_s16", + "name": "vst4_lane_p16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "poly16_t * ptr", + "poly16x4x4_t val", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_s32", + "name": "vst4_lane_p64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "poly64_t * ptr", + "poly64x1x4_t val", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -110616,107 +307115,169 @@ ], "instructions": [ [ - "SSUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_s8", + "name": "vst4_lane_p8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "poly8_t * ptr", + "poly8x8x4_t val", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_u16", + "name": "vst4_lane_s16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int16_t * ptr", + "int16x4x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_u32", + "name": "vst4_lane_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32_t * ptr", + "int32x2x4_t val", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_high_u8", + "name": "vst4_lane_s64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int64_t * ptr", + "int64x1x4_t val", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -110724,26 +307285,40 @@ ], "instructions": [ [ - "USUBL2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_s16", + "name": "vst4_lane_s8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int8_t * ptr", + "int8x8x4_t val", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -110753,26 +307328,40 @@ ], "instructions": [ [ - "SSUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_s32", + "name": "vst4_lane_u16", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint16_t * ptr", + "uint16x4x4_t val", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -110782,26 +307371,40 @@ ], "instructions": [ [ - "SSUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_s8", + "name": "vst4_lane_u32", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint32_t * ptr", + "uint32x2x4_t val", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -110811,55 +307414,81 @@ ], "instructions": [ [ - "SSUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_u16", + "name": "vst4_lane_u64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "uint64_t * ptr", + "uint64x1x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "lane": { + "minimum": 0, + "maximum": 0 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_u32", + "name": "vst4_lane_u8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint8_t * ptr", + "uint8x8x4_t val", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -110869,26 +307498,35 @@ ], "instructions": [ [ - "USUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubl_u8", + "name": "vst4_p16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly16_t * ptr", + "poly16x4x4_t val" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -110898,26 +307536,35 @@ ], "instructions": [ [ - "USUBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_f16", + "name": "vst4_p64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly64_t * ptr", + "poly64x1x4_t val" ], "return_type": { - "value": "float16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -110926,26 +307573,35 @@ ], "instructions": [ [ - "FSUB" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_f32", + "name": "vst4_p8", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "poly8_t * ptr", + "poly8x8x4_t val" ], "return_type": { - "value": "float32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -110955,53 +307611,73 @@ ], "instructions": [ [ - "FSUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_f64", + "name": "vst4_s16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int16_t * ptr", + "int16x4x4_t val" ], "return_type": { - "value": "float64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "FSUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_s16", + "name": "vst4_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32_t * ptr", + "int32x2x4_t val" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -111011,26 +307687,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_s32", + "name": "vst4_s64", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int64_t * ptr", + "int64x1x4_t val" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -111040,26 +307725,35 @@ ], "instructions": [ [ - "SUB" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_s64", + "name": "vst4_s8", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int8_t * ptr", + "int8x8x4_t val" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -111069,26 +307763,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_s8", + "name": "vst4_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16_t * ptr", + "uint16x4x4_t val" ], "return_type": { - "value": "int8x16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.16B" + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { + "register": "Vt4.4H" } }, "Architectures": [ @@ -111098,26 +307801,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_u16", + "name": "vst4_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint32_t * ptr", + "uint32x2x4_t val" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { + "register": "Vt4.2S" } }, "Architectures": [ @@ -111127,26 +307839,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_u32", + "name": "vst4_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint64_t * ptr", + "uint64x1x4_t val" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { + "register": "Vt4.1D" } }, "Architectures": [ @@ -111156,26 +307877,35 @@ ], "instructions": [ [ - "SUB" + "ST1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_u64", + "name": "vst4_u8", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "uint8_t * ptr", + "uint8x8x4_t val" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.2D" + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" } }, "Architectures": [ @@ -111185,26 +307915,35 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubq_u8", + "name": "vst4q_f16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "float16_t * ptr", + "float16x8x4_t val" ], "return_type": { - "value": "uint8x16_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.16B" + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -111214,53 +307953,73 @@ ], "instructions": [ [ - "SUB" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_s16", + "name": "vst4q_f32", "arguments": [ - "int32x4_t a", - "int16x8_t b" + "float32_t * ptr", + "float32x4x4_t val" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.8H" + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_s32", + "name": "vst4q_f64", "arguments": [ - "int64x2_t a", - "int32x4_t b" + "float64_t * ptr", + "float64x2x4_t val" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "ptr": { + "register": "Xn" }, - "b": { - "register": "Vm.4S" + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ @@ -111268,80 +308027,126 @@ ], "instructions": [ [ - "SSUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_s8", + "name": "vst4q_lane_f16", "arguments": [ - "int16x8_t a", - "int8x16_t b" + "float16_t * ptr", + "float16x8x4_t val", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SSUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_u16", + "name": "vst4q_lane_f32", "arguments": [ - "uint32x4_t a", - "uint16x8_t b" + "float32_t * ptr", + "float32x4x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.8H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_u32", + "name": "vst4q_lane_f64", "arguments": [ - "uint64x2_t a", - "uint32x4_t b" + "float64_t * ptr", + "float64x2x4_t val", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ @@ -111349,111 +308154,165 @@ ], "instructions": [ [ - "USUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_high_u8", + "name": "vst4q_lane_p16", "arguments": [ - "uint16x8_t a", - "uint8x16_t b" + "poly16_t * ptr", + "poly16x8x4_t val", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "USUBW2" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_s16", + "name": "vst4q_lane_p64", "arguments": [ - "int32x4_t a", - "int16x4_t b" + "poly64_t * ptr", + "poly64x2x4_t val", + "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_s32", + "name": "vst4q_lane_p8", "arguments": [ - "int64x2_t a", - "int32x2_t b" + "poly8_t * ptr", + "poly8x16x4_t val", + "const int lane" ], "return_type": { - "value": "int64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "SSUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_s8", + "name": "vst4q_lane_s16", "arguments": [ - "int16x8_t a", - "int8x8_t b" + "int16_t * ptr", + "int16x8x4_t val", + "const int lane" ], "return_type": { - "value": "int16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 7 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ @@ -111463,26 +308322,40 @@ ], "instructions": [ [ - "SSUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_u16", + "name": "vst4q_lane_s32", "arguments": [ - "uint32x4_t a", - "uint16x4_t b" + "int32_t * ptr", + "int32x4x4_t val", + "const int lane" ], "return_type": { - "value": "uint32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "lane": { + "minimum": 0, + "maximum": 3 }, - "b": { - "register": "Vm.4H" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ @@ -111492,203 +308365,249 @@ ], "instructions": [ [ - "USUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_u32", + "name": "vst4q_lane_s64", "arguments": [ - "uint64x2_t a", - "uint32x2_t b" + "int64_t * ptr", + "int64x2x4_t val", + "const int lane" ], "return_type": { - "value": "uint64x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "lane": { + "minimum": 0, + "maximum": 1 }, - "b": { - "register": "Vm.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsubw_u8", + "name": "vst4q_lane_s8", "arguments": [ - "uint16x8_t a", - "uint8x8_t b" + "int8_t * ptr", + "int8x16x4_t val", + "const int lane" ], "return_type": { - "value": "uint16x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "lane": { + "minimum": 0, + "maximum": 15 }, - "b": { - "register": "Vm.8B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "USUBW" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsudot_lane_s32", + "name": "vst4q_lane_u16", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "uint8x8_t b", + "uint16_t * ptr", + "uint16x8x4_t val", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" - }, "lane": { "minimum": 0, - "maximum": 1 + "maximum": 7 }, - "r": { - "register": "Vd.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "SUDOT" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsudot_laneq_s32", + "name": "vst4q_lane_u32", "arguments": [ - "int32x2_t r", - "int8x8_t a", - "uint8x16_t b", + "uint32_t * ptr", + "uint32x4x4_t val", "const int lane" ], "return_type": { - "value": "int32x2_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" - }, "lane": { "minimum": 0, "maximum": 3 }, - "r": { - "register": "Vd.2S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "SUDOT" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsudotq_lane_s32", + "name": "vst4q_lane_u64", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "uint8x8_t b", + "uint64_t * ptr", + "uint64x2x4_t val", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" - }, "lane": { "minimum": 0, "maximum": 1 }, - "r": { - "register": "Vd.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "SUDOT" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vsudotq_laneq_s32", + "name": "vst4q_lane_u8", "arguments": [ - "int32x4_t r", - "int8x16_t a", - "uint8x16_t b", + "uint8_t * ptr", + "uint8x16x4_t val", "const int lane" ], "return_type": { - "value": "int32x4_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" - }, - "b": { - "register": "Vm.4B" - }, "lane": { "minimum": 0, - "maximum": 3 + "maximum": 15 }, - "r": { - "register": "Vd.4S" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" } }, "Architectures": [ @@ -111696,25 +308615,36 @@ ], "instructions": [ [ - "SUDOT" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl1_p8", + "name": "vst4q_p16", "arguments": [ - "poly8x8_t a", - "uint8x8_t idx" + "poly16_t * ptr", + "poly16x8x4_t val" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" }, - "idx": {} + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" + } }, "Architectures": [ "v7", @@ -111723,52 +308653,72 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl1_s8", + "name": "vst4q_p64", "arguments": [ - "int8x8_t a", - "int8x8_t idx" + "poly64_t * ptr", + "poly64x2x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" }, - "idx": {} + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl1_u8", + "name": "vst4q_p8", "arguments": [ - "uint8x8_t a", - "uint8x8_t idx" + "poly8_t * ptr", + "poly8x16x4_t val" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" }, - "idx": {} + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" + } }, "Architectures": [ "v7", @@ -111777,25 +308727,36 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl2_p8", + "name": "vst4q_s16", "arguments": [ - "poly8x8x2_t a", - "uint8x8_t idx" + "int16_t * ptr", + "int16x8x4_t val" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" }, - "idx": {} + "val.val[3]": { + "register": "Vt4.8H" + } }, "Architectures": [ "v7", @@ -111804,25 +308765,36 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl2_s8", + "name": "vst4q_s32", "arguments": [ - "int8x8x2_t a", - "int8x8_t idx" + "int32_t * ptr", + "int32x4x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "idx": {} + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { + "register": "Vt4.4S" + } }, "Architectures": [ "v7", @@ -111831,52 +308803,72 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl2_u8", + "name": "vst4q_s64", "arguments": [ - "uint8x8x2_t a", - "uint8x8_t idx" + "int64_t * ptr", + "int64x2x4_t val" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.2D" }, - "idx": {} + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl3_p8", + "name": "vst4q_s8", "arguments": [ - "poly8x8x3_t a", - "uint8x8_t idx" + "int8_t * ptr", + "int8x16x4_t val" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" }, - "idx": {} + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" + } }, "Architectures": [ "v7", @@ -111885,25 +308877,36 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl3_s8", + "name": "vst4q_u16", "arguments": [ - "int8x8x3_t a", - "int8x8_t idx" + "uint16_t * ptr", + "uint16x8x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" }, - "idx": {} + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { + "register": "Vt4.8H" + } }, "Architectures": [ "v7", @@ -111912,25 +308915,36 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl3_u8", + "name": "vst4q_u32", "arguments": [ - "uint8x8x3_t a", - "uint8x8_t idx" + "uint32_t * ptr", + "uint32x4x4_t val" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" }, - "idx": {} + "val.val[3]": { + "register": "Vt4.4S" + } }, "Architectures": [ "v7", @@ -111939,52 +308953,72 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl4_p8", + "name": "vst4q_u64", "arguments": [ - "poly8x8x4_t a", - "uint8x8_t idx" + "uint64_t * ptr", + "uint64x2x4_t val" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "idx": {} + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { + "register": "Vt4.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl4_s8", + "name": "vst4q_u8", "arguments": [ - "int8x8x4_t a", - "int8x8_t idx" + "uint8_t * ptr", + "uint8x16x4_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "idx": {} + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" + } }, "Architectures": [ "v7", @@ -111993,333 +309027,339 @@ ], "instructions": [ [ - "TBL" + "ST4" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbl4_u8", + "name": "vstl1_lane_f64", "arguments": [ - "uint8x8x4_t a", - "uint8x8_t idx" + "float64_t * ptr", + "float64x1_t val", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 }, - "idx": {} + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBL" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx1_p8", + "name": "vstl1_lane_p64", "arguments": [ - "poly8x8_t a", - "poly8x8_t b", - "uint8x8_t idx" + "poly64_t * ptr", + "poly64x1_t val", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.1D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx1_s8", + "name": "vstl1_lane_s64", "arguments": [ - "int8x8_t a", - "int8x8_t b", - "int8x8_t idx" + "int64_t * ptr", + "int64x1_t val", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.1D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx1_u8", + "name": "vstl1_lane_u64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "uint8x8_t idx" + "uint64_t * ptr", + "uint64x1_t val", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.1D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx2_p8", + "name": "vstl1q_lane_f64", "arguments": [ - "poly8x8_t a", - "poly8x8x2_t b", - "uint8x8_t idx" + "float64_t * ptr", + "float64x2_t val", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBX" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx2_s8", + "name": "vstl1q_lane_p64", "arguments": [ - "int8x8_t a", - "int8x8x2_t b", - "int8x8_t idx" + "poly64_t * ptr", + "poly64x2_t val", + "const int lane" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBX" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx2_u8", + "name": "vstl1q_lane_s64", "arguments": [ - "uint8x8_t a", - "uint8x8x2_t b", - "uint8x8_t idx" + "int64_t * ptr", + "int64x2_t val", + "const int lane" ], "return_type": { - "value": "uint8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Vt.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBX" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx3_p8", + "name": "vstl1q_lane_u64", "arguments": [ - "poly8x8_t a", - "poly8x8x3_t b", - "uint8x8_t idx" + "uint64_t * ptr", + "uint64x2_t val", + "const int lane" ], "return_type": { - "value": "poly8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "lane": { + "minimum": 0, + "maximum": 1 }, - "idx": {} + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx3_s8", + "name": "vstrq_p128", "arguments": [ - "int8x8_t a", - "int8x8x3_t b", - "int8x8_t idx" + "poly128_t * ptr", + "poly128_t val" ], "return_type": { - "value": "int8x8_t" + "value": "void" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "ptr": { + "register": "Xn" }, - "idx": {} + "val": { + "register": "Qt" + } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "STR" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx3_u8", + "name": "vsub_f16", "arguments": [ - "uint8x8_t a", - "uint8x8x3_t b", - "uint8x8_t idx" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "a": { + "register": "Vn.4H" }, - "idx": {} + "b": { + "register": "Vm.4H" + } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "MOVI", - "CMHS", - "TBL", - "BIF" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx4_p8", + "name": "vsub_f32", "arguments": [ - "poly8x8_t a", - "poly8x8x4_t b", - "uint8x8_t idx" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "a": { + "register": "Vn.2S" }, - "idx": {} + "b": { + "register": "Vm.2S" + } }, "Architectures": [ "v7", @@ -112328,56 +309368,54 @@ ], "instructions": [ [ - "TBX" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx4_s8", + "name": "vsub_f64", "arguments": [ - "int8x8_t a", - "int8x8x4_t b", - "int8x8_t idx" + "float64x1_t a", + "float64x1_t b" ], "return_type": { - "value": "int8x8_t" + "value": "float64x1_t" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "a": { + "register": "Dn" }, - "idx": {} + "b": { + "register": "Dm" + } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TBX" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtbx4_u8", + "name": "vsub_s16", "arguments": [ - "uint8x8_t a", - "uint8x8x4_t b", - "uint8x8_t idx" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": { - "register": "Vn.16B" + "a": { + "register": "Vn.4H" }, - "idx": {} + "b": { + "register": "Vm.4H" + } }, "Architectures": [ "v7", @@ -112386,181 +309424,193 @@ ], "instructions": [ [ - "TBX" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_f16", + "name": "vsub_s32", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, "b": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_f32", + "name": "vsub_s64", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_p16", + "name": "vsub_s8", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8B" }, "b": { - "register": "Vm.4H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_p8", + "name": "vsub_u16", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4H" }, "b": { - "register": "Vm.8B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_s16", + "name": "vsub_u32", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int16x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2S" }, "b": { - "register": "Vm.4H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_s32", + "name": "vsub_u64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "int32x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_s8", + "name": "vsub_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { @@ -112571,30 +309621,32 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_u16", + "name": "vsubd_s64", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "int64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, "b": { - "register": "Vm.4H" + "register": "Dm" } }, "Architectures": [ @@ -112602,26 +309654,26 @@ ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_u32", + "name": "vsubd_u64", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "uint64_t a", + "uint64_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" } }, "Architectures": [ @@ -112629,46 +309681,48 @@ ], "instructions": [ [ - "TRN1" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1_u8", + "name": "vsubh_f16", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "float16_t a", + "float16_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "float16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Hn" }, "b": { - "register": "Vm.8B" + "register": "Hm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "TRN1" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_f16", + "name": "vsubhn_high_s16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int8x8_t r", + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { @@ -112676,6 +309730,9 @@ }, "b": { "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -112683,19 +309740,20 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_f32", + "name": "vsubhn_high_s32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int16x4_t r", + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -112703,6 +309761,9 @@ }, "b": { "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -112710,19 +309771,20 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_f64", + "name": "vsubhn_high_s64", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "int32x2_t r", + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -112730,6 +309792,9 @@ }, "b": { "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -112737,19 +309802,20 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_p16", + "name": "vsubhn_high_u16", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "uint8x8_t r", + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { @@ -112757,6 +309823,9 @@ }, "b": { "register": "Vm.8H" + }, + "r": { + "register": "Vd.8B" } }, "Architectures": [ @@ -112764,26 +309833,30 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_p64", + "name": "vsubhn_high_u32", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "uint16x4_t r", + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly64x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" + }, + "r": { + "register": "Vd.4H" } }, "Architectures": [ @@ -112791,26 +309864,30 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_p8", + "name": "vsubhn_high_u64", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "uint32x2_t r", + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm.16B" + "register": "Vm.2D" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ @@ -112818,19 +309895,19 @@ ], "instructions": [ [ - "TRN1" + "SUBHN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_s16", + "name": "vsubhn_s16", "arguments": [ "int16x8_t a", "int16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { @@ -112841,23 +309918,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_s32", + "name": "vsubhn_s32", "arguments": [ "int32x4_t a", "int32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { @@ -112868,23 +309947,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_s64", + "name": "vsubhn_s64", "arguments": [ "int64x2_t a", "int64x2_t b" ], "return_type": { - "value": "int64x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -112895,111 +309976,119 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_s8", + "name": "vsubhn_u16", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.16B" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_u16", + "name": "vsubhn_u32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, "b": { - "register": "Vm.8H" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_u32", + "name": "vsubhn_u64", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2D" }, "b": { - "register": "Vm.4S" + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN1" + "SUBHN" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_u64", + "name": "vsubl_high_s16", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8H" }, "b": { - "register": "Vm.2D" + "register": "Vm.8H" } }, "Architectures": [ @@ -113007,26 +310096,26 @@ ], "instructions": [ [ - "TRN1" + "SSUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn1q_u8", + "name": "vsubl_high_s32", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.4S" } }, "Architectures": [ @@ -113034,26 +310123,26 @@ ], "instructions": [ [ - "TRN1" + "SSUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_f16", + "name": "vsubl_high_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float16x4_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.16B" }, "b": { - "register": "Vm.4H" + "register": "Vm.16B" } }, "Architectures": [ @@ -113061,26 +310150,26 @@ ], "instructions": [ [ - "TRN2" + "SSUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_f32", + "name": "vsubl_high_u16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float32x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.8H" }, "b": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ @@ -113088,26 +310177,26 @@ ], "instructions": [ [ - "TRN2" + "USUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_p16", + "name": "vsubl_high_u32", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, "b": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ @@ -113115,26 +310204,26 @@ ], "instructions": [ [ - "TRN2" + "USUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_p8", + "name": "vsubl_high_u8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.16B" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -113142,19 +310231,19 @@ ], "instructions": [ [ - "TRN2" + "USUBL2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_s16", + "name": "vsubl_s16", "arguments": [ "int16x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -113165,23 +310254,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SSUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_s32", + "name": "vsubl_s32", "arguments": [ "int32x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { @@ -113192,23 +310283,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SSUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_s8", + "name": "vsubl_s8", "arguments": [ "int8x8_t a", "int8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -113219,23 +310312,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SSUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_u16", + "name": "vsubl_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -113246,23 +310341,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "USUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_u32", + "name": "vsubl_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { @@ -113273,23 +310370,25 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "USUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2_u8", + "name": "vsubl_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -113300,17 +310399,19 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "USUBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_f16", + "name": "vsubq_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -113327,17 +310428,18 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "TRN2" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_f32", + "name": "vsubq_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -113354,17 +310456,19 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_f64", + "name": "vsubq_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -113385,19 +310489,19 @@ ], "instructions": [ [ - "TRN2" + "FSUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_p16", + "name": "vsubq_s16", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -113408,219 +310512,235 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_p64", + "name": "vsubq_s32", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "poly64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_p8", + "name": "vsubq_s64", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm.16B" + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_s16", + "name": "vsubq_s8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_s32", + "name": "vsubq_u16", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8H" }, "b": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_s64", + "name": "vsubq_u32", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_s8", + "name": "vsubq_u64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm.16B" + "register": "Vm.2D" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_u16", + "name": "vsubq_u8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "TRN2" + "SUB" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_u32", + "name": "vsubw_high_s16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x4_t a", + "int16x8_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { "register": "Vn.4S" }, "b": { - "register": "Vm.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -113628,26 +310748,26 @@ ], "instructions": [ [ - "TRN2" + "SSUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_u64", + "name": "vsubw_high_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int64x2_t a", + "int32x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { "register": "Vn.2D" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ @@ -113655,23 +310775,23 @@ ], "instructions": [ [ - "TRN2" + "SSUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn2q_u8", + "name": "vsubw_high_s8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int16x8_t a", + "int8x16_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { "register": "Vm.16B" @@ -113682,143 +310802,104 @@ ], "instructions": [ [ - "TRN2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vtrn_f16", - "arguments": [ - "float16x4_t a", - "float16x4_t b" - ], - "return_type": { - "value": "float16x4x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" - } - }, - "Architectures": [ - "v7", - "A32", - "A64" - ], - "instructions": [ - [ - "TRN1", - "TRN2" + "SSUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_f32", + "name": "vsubw_high_u16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint32x4_t a", + "uint16x8_t b" ], "return_type": { - "value": "float32x2x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, "b": { - "register": "Vm.2S" + "register": "Vm.8H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_p16", + "name": "vsubw_high_u32", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "uint64x2_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x4x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.2D" }, "b": { - "register": "Vm.4H" + "register": "Vm.4S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_p8", + "name": "vsubw_high_u8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint16x8_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly8x8x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_s16", + "name": "vsubw_s16", "arguments": [ - "int16x4_t a", + "int32x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, "b": { "register": "Vm.4H" @@ -113831,24 +310912,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "SSUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_s32", + "name": "vsubw_s32", "arguments": [ - "int32x2_t a", + "int64x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" }, "b": { "register": "Vm.2S" @@ -113861,24 +310941,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "SSUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_s8", + "name": "vsubw_s8", "arguments": [ - "int8x8_t a", + "int16x8_t a", "int8x8_t b" ], "return_type": { - "value": "int8x8x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { "register": "Vm.8B" @@ -113891,24 +310970,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "SSUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_u16", + "name": "vsubw_u16", "arguments": [ - "uint16x4_t a", + "uint32x4_t a", "uint16x4_t b" ], "return_type": { - "value": "uint16x4x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.4S" }, "b": { "register": "Vm.4H" @@ -113921,24 +310999,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_u32", + "name": "vsubw_u32", "arguments": [ - "uint32x2_t a", + "uint64x2_t a", "uint32x2_t b" ], "return_type": { - "value": "uint32x2x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.2D" }, "b": { "register": "Vm.2S" @@ -113951,24 +311028,23 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrn_u8", + "name": "vsubw_u8", "arguments": [ - "uint8x8_t a", + "uint16x8_t a", "uint8x8_t b" ], "return_type": { - "value": "uint8x8x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { "register": "Vm.8B" @@ -113981,147 +311057,174 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "USUBW" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_f16", + "name": "vsudot_lane_s32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "int32x2_t r", + "int8x8_t a", + "uint8x8_t b", + "const int lane" ], "return_type": { - "value": "float16x8x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "SUDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_f32", + "name": "vsudot_laneq_s32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int32x2_t r", + "int8x8_t a", + "uint8x16_t b", + "const int lane" ], "return_type": { - "value": "float32x4x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "SUDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_p16", + "name": "vsudotq_lane_s32", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "int32x4_t r", + "int8x16_t a", + "uint8x8_t b", + "const int lane" ], "return_type": { - "value": "poly16x8x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "SUDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_p8", + "name": "vsudotq_laneq_s32", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "int32x4_t r", + "int8x16_t a", + "uint8x16_t b", + "const int lane" ], "return_type": { - "value": "poly8x16x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "TRN1", - "TRN2" + "SUDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_s16", + "name": "vtbl1_p8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "poly8x8_t a", + "uint8x8_t idx" ], "return_type": { - "value": "int16x8x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "Zeros(64):a": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.8H" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114131,27 +311234,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_s32", + "name": "vtbl1_s8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int8x8_t a", + "int8x8_t idx" ], "return_type": { - "value": "int32x4x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "Zeros(64):a": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.4S" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114161,27 +311263,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_s8", + "name": "vtbl1_u8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint8x8_t a", + "uint8x8_t idx" ], "return_type": { - "value": "int8x16x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114191,27 +311292,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_u16", + "name": "vtbl2_p8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly8x8x2_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint16x8x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.8H" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114221,27 +311321,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_u32", + "name": "vtbl2_s8", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int8x8x2_t a", + "int8x8_t idx" ], "return_type": { - "value": "uint32x4x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.4S" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114251,27 +311350,26 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtrnq_u8", + "name": "vtbl2_u8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "uint8x8x2_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint8x16x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114281,54 +311379,60 @@ ], "instructions": [ [ - "TRN1", - "TRN2" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_p64", + "name": "vtbl3_p8", "arguments": [ - "poly64x1_t a", - "poly64x1_t b" + "poly8x8x3_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint64x1_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" }, - "b": { - "register": "Dm" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_p8", + "name": "vtbl3_s8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "int8x8x3_t a", + "int8x8_t idx" ], "return_type": { - "value": "uint8x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" }, - "b": { + "a.val[1]:a.val[0]": { + "register": "Vn.16B" + }, + "idx": { "register": "Vm.8B" } }, @@ -114339,26 +311443,29 @@ ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_s16", + "name": "vtbl3_u8", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "uint8x8x3_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint16x4_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" }, - "b": { - "register": "Vm.4H" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114368,26 +311475,29 @@ ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_s32", + "name": "vtbl4_p8", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "poly8x8x4_t a", + "uint8x8_t idx" ], "return_type": { - "value": "uint32x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { - "register": "Vm.2S" + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114397,52 +311507,60 @@ ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_s64", + "name": "vtbl4_s8", "arguments": [ - "int64x1_t a", - "int64x1_t b" + "int8x8x4_t a", + "int8x8_t idx" ], "return_type": { - "value": "uint64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Dn" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { - "register": "Dm" + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_s8", + "name": "vtbl4_u8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "uint8x8x4_t a", + "uint8x8_t idx" ], "return_type": { "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8B" + "a.val[1]:a.val[0]": { + "register": "Vn.16B" }, - "b": { + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { "register": "Vm.8B" } }, @@ -114453,26 +311571,30 @@ ], "instructions": [ [ - "CMTST" + "TBL" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_u16", + "name": "vtbx1_p8", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "poly8x8_t a", + "poly8x8_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint16x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b": { + "register": "Vn.16B" + }, "a": { - "register": "Vn.4H" + "register": "Vd.8B" }, - "b": { - "register": "Vm.4H" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114482,26 +311604,33 @@ ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_u32", + "name": "vtbx1_s8", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int8x8_t a", + "int8x8_t b", + "int8x8_t idx" ], "return_type": { - "value": "uint32x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b": { + "register": "Vn.16B" + }, "a": { - "register": "Vn.2S" + "register": "Vd.8B" }, - "b": { - "register": "Vm.2S" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114511,52 +311640,68 @@ ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_u64", + "name": "vtbx1_u8", "arguments": [ - "uint64x1_t a", - "uint64x1_t b" + "uint8x8_t a", + "uint8x8_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint64x1_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b": { + "register": "Vn.16B" + }, "a": { - "register": "Dn" + "register": "Vd.8B" }, - "b": { - "register": "Dm" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtst_u8", + "name": "vtbx2_p8", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "poly8x8_t a", + "poly8x8x2_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint8x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vd.8B" }, - "b": { + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { "register": "Vm.8B" } }, @@ -114567,108 +311712,138 @@ ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstd_s64", + "name": "vtbx2_s8", "arguments": [ - "int64_t a", - "int64_t b" + "int8x8_t a", + "int8x8x2_t b", + "int8x8_t idx" ], "return_type": { - "value": "uint64_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8B" }, - "b": { - "register": "Dm" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstd_u64", + "name": "vtbx2_u8", "arguments": [ - "uint64_t a", - "uint64_t b" + "uint8x8_t a", + "uint8x8x2_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint64_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dn" + "register": "Vd.8B" }, - "b": { - "register": "Dm" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_p64", + "name": "vtbx3_p8", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "poly8x8_t a", + "poly8x8x3_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint64x2_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, "a": { - "register": "Vn.2D" + "register": "Vd.8B" }, - "b": { - "register": "Vm.2D" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", "A32", "A64" ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_p8", + "name": "vtbx3_s8", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "int8x8_t a", + "int8x8x3_t b", + "int8x8_t idx" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114678,26 +311853,36 @@ ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_s16", + "name": "vtbx3_u8", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint8x8_t a", + "uint8x8x3_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, "a": { - "register": "Vn.8H" + "register": "Vd.8B" }, - "b": { - "register": "Vm.8H" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "idx": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114707,26 +311892,36 @@ ], "instructions": [ [ - "CMTST" + "MOVI", + "CMHS", + "TBL", + "BIF" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_s32", + "name": "vtbx4_p8", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "poly8x8_t a", + "poly8x8x4_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint32x4_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vd.8B" }, - "b": { - "register": "Vm.4S" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114736,53 +311931,69 @@ ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_s64", + "name": "vtbx4_s8", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "int8x8_t a", + "int8x8x4_t b", + "int8x8_t idx" ], "return_type": { - "value": "uint64x2_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vd.8B" }, - "b": { - "register": "Vm.2D" + "b.val[1]:b.val[0]": { + "register": "Vn.16B" + }, + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_s8", + "name": "vtbx4_u8", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "uint8x8_t a", + "uint8x8x4_t b", + "uint8x8_t idx" ], "return_type": { - "value": "uint8x16_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "b": { - "register": "Vm.16B" + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" } }, "Architectures": [ @@ -114792,84 +312003,80 @@ ], "instructions": [ [ - "CMTST" + "TBX" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_u16", + "name": "vtrn1_f16", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "float16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm.8H" + "register": "Vm.4H" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMTST" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_u32", + "name": "vtrn1_f32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.2S" }, "b": { - "register": "Vm.4S" + "register": "Vm.2S" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMTST" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_u64", + "name": "vtrn1_p16", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "poly16x4_t a", + "poly16x4_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4H" }, "b": { - "register": "Vm.2D" + "register": "Vm.4H" } }, "Architectures": [ @@ -114877,55 +312084,53 @@ ], "instructions": [ [ - "CMTST" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vtstq_u8", + "name": "vtrn1_p8", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "CMTST" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadd_s16", + "name": "vtrn1_s16", "arguments": [ "int16x4_t a", - "uint16x4_t b" + "int16x4_t b" ], "return_type": { "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4H" + "register": "Vn.4H" }, "b": { - "register": "Vn.4H" + "register": "Vm.4H" } }, "Architectures": [ @@ -114933,26 +312138,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadd_s32", + "name": "vtrn1_s32", "arguments": [ "int32x2_t a", - "uint32x2_t b" + "int32x2_t b" ], "return_type": { "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2S" + "register": "Vn.2S" }, "b": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -114960,26 +312165,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadd_s64", + "name": "vtrn1_s8", "arguments": [ - "int64x1_t a", - "uint64x1_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int64x1_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8B" }, "b": { - "register": "Dn" + "register": "Vm.8B" } }, "Architectures": [ @@ -114987,26 +312192,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadd_s8", + "name": "vtrn1_u16", "arguments": [ - "int8x8_t a", - "uint8x8_t b" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int8x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8B" + "register": "Vn.4H" }, "b": { - "register": "Vn.8B" + "register": "Vm.4H" } }, "Architectures": [ @@ -115014,26 +312219,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddb_s8", + "name": "vtrn1_u32", "arguments": [ - "int8_t a", - "uint8_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Bd" + "register": "Vn.2S" }, "b": { - "register": "Bn" + "register": "Vm.2S" } }, "Architectures": [ @@ -115041,26 +312246,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddd_s64", + "name": "vtrn1_u8", "arguments": [ - "int64_t a", - "uint64_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int64_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Dd" + "register": "Vn.8B" }, "b": { - "register": "Dn" + "register": "Vm.8B" } }, "Architectures": [ @@ -115068,26 +312273,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddh_s16", + "name": "vtrn1q_f16", "arguments": [ - "int16_t a", - "uint16_t b" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "int16_t" + "value": "float16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Hd" + "register": "Vn.8H" }, "b": { - "register": "Hn" + "register": "Vm.8H" } }, "Architectures": [ @@ -115095,26 +312300,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddq_s16", + "name": "vtrn1q_f32", "arguments": [ - "int16x8_t a", - "uint16x8_t b" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.8H" + "register": "Vn.4S" }, "b": { - "register": "Vn.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -115122,26 +312327,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddq_s32", + "name": "vtrn1q_f64", "arguments": [ - "int32x4_t a", - "uint32x4_t b" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "int32x4_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.4S" + "register": "Vn.2D" }, "b": { - "register": "Vn.4S" + "register": "Vm.2D" } }, "Architectures": [ @@ -115149,26 +312354,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddq_s64", + "name": "vtrn1q_p16", "arguments": [ - "int64x2_t a", - "uint64x2_t b" + "poly16x8_t a", + "poly16x8_t b" ], "return_type": { - "value": "int64x2_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.2D" + "register": "Vn.8H" }, "b": { - "register": "Vn.2D" + "register": "Vm.8H" } }, "Architectures": [ @@ -115176,26 +312381,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqaddq_s8", + "name": "vtrn1q_p64", "arguments": [ - "int8x16_t a", - "uint8x16_t b" + "poly64x2_t a", + "poly64x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vd.16B" + "register": "Vn.2D" }, "b": { - "register": "Vn.16B" + "register": "Vm.2D" } }, "Architectures": [ @@ -115203,26 +312408,26 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuqadds_s32", + "name": "vtrn1q_p8", "arguments": [ - "int32_t a", - "uint32_t b" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "int32_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Sd" + "register": "Vn.16B" }, "b": { - "register": "Sn" + "register": "Vm.16B" } }, "Architectures": [ @@ -115230,72 +312435,53 @@ ], "instructions": [ [ - "SUQADD" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdot_lane_s32", + "name": "vtrn1q_s16", "arguments": [ - "int32x2_t r", - "uint8x8_t a", - "int8x8_t b", - "const int lane" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.8H" }, "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.2S" + "register": "Vm.8H" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdot_laneq_s32", + "name": "vtrn1q_s32", "arguments": [ - "int32x2_t r", - "uint8x8_t a", - "int8x16_t b", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.4S" }, "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -115303,104 +312489,80 @@ ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdot_s32", + "name": "vtrn1q_s64", "arguments": [ - "int32x2_t r", - "uint8x8_t a", - "int8x8_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, "b": { - "register": "Vm.8B" - }, - "r": { - "register": "Vd.2S" + "register": "Vm.2D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdotq_lane_s32", + "name": "vtrn1q_s8", "arguments": [ - "int32x4_t r", - "uint8x16_t a", - "int8x8_t b", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { "register": "Vn.16B" }, "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.4S" + "register": "Vm.16B" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdotq_laneq_s32", + "name": "vtrn1q_u16", "arguments": [ - "int32x4_t r", - "uint8x16_t a", - "int8x16_t b", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm.4B" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.4S" + "register": "Vm.8H" } }, "Architectures": [ @@ -115408,30 +312570,53 @@ ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusdotq_s32", + "name": "vtrn1q_u32", "arguments": [ - "int32x4_t r", - "uint8x16_t a", - "int8x16_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm.16B" + "register": "Vm.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtrn1q_u64", + "arguments": [ + "uint64x2_t a", + "uint64x2_t b" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" }, - "r": { - "register": "Vd.4S" + "b": { + "register": "Vm.2D" } }, "Architectures": [ @@ -115439,20 +312624,19 @@ ], "instructions": [ [ - "USDOT" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vusmmlaq_s32", + "name": "vtrn1q_u8", "arguments": [ - "int32x4_t r", "uint8x16_t a", - "int8x16_t b" + "uint8x16_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { @@ -115460,24 +312644,20 @@ }, "b": { "register": "Vm.16B" - }, - "r": { - "register": "Vd.4S" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "USMMLA" + "TRN1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_f16", + "name": "vtrn2_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -115498,13 +312678,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_f32", + "name": "vtrn2_f32", "arguments": [ "float32x2_t a", "float32x2_t b" @@ -115525,13 +312705,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_p16", + "name": "vtrn2_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" @@ -115552,13 +312732,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_p8", + "name": "vtrn2_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" @@ -115579,13 +312759,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_s16", + "name": "vtrn2_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -115606,13 +312786,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_s32", + "name": "vtrn2_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -115633,13 +312813,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_s8", + "name": "vtrn2_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -115660,13 +312840,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_u16", + "name": "vtrn2_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -115687,13 +312867,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_u32", + "name": "vtrn2_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -115714,13 +312894,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1_u8", + "name": "vtrn2_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" @@ -115741,13 +312921,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_f16", + "name": "vtrn2q_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -115768,13 +312948,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_f32", + "name": "vtrn2q_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -115795,13 +312975,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_f64", + "name": "vtrn2q_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -115822,13 +313002,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_p16", + "name": "vtrn2q_p16", "arguments": [ "poly16x8_t a", "poly16x8_t b" @@ -115849,13 +313029,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_p64", + "name": "vtrn2q_p64", "arguments": [ "poly64x2_t a", "poly64x2_t b" @@ -115876,13 +313056,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_p8", + "name": "vtrn2q_p8", "arguments": [ "poly8x16_t a", "poly8x16_t b" @@ -115903,13 +313083,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_s16", + "name": "vtrn2q_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -115930,13 +313110,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_s32", + "name": "vtrn2q_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -115957,13 +313137,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_s64", + "name": "vtrn2q_s64", "arguments": [ "int64x2_t a", "int64x2_t b" @@ -115984,13 +313164,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_s8", + "name": "vtrn2q_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -116011,13 +313191,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_u16", + "name": "vtrn2q_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -116038,13 +313218,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_u32", + "name": "vtrn2q_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -116065,13 +313245,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_u64", + "name": "vtrn2q_u64", "arguments": [ "uint64x2_t a", "uint64x2_t b" @@ -116092,13 +313272,13 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp1q_u8", + "name": "vtrn2q_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -116119,19 +313299,19 @@ ], "instructions": [ [ - "UZP1" + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_f16", + "name": "vtrn_f16", "arguments": [ "float16x4_t a", "float16x4_t b" ], "return_type": { - "value": "float16x4_t" + "value": "float16x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116142,23 +313322,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_f32", + "name": "vtrn_f32", "arguments": [ "float32x2_t a", "float32x2_t b" ], "return_type": { - "value": "float32x2_t" + "value": "float32x2x2_t" }, "Arguments_Preparation": { "a": { @@ -116169,23 +313352,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_p16", + "name": "vtrn_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" ], "return_type": { - "value": "poly16x4_t" + "value": "poly16x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116196,23 +313382,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_p8", + "name": "vtrn_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" ], "return_type": { - "value": "poly8x8_t" + "value": "poly8x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116223,23 +313412,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_s16", + "name": "vtrn_s16", "arguments": [ "int16x4_t a", "int16x4_t b" ], "return_type": { - "value": "int16x4_t" + "value": "int16x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116250,23 +313442,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_s32", + "name": "vtrn_s32", "arguments": [ "int32x2_t a", "int32x2_t b" ], "return_type": { - "value": "int32x2_t" + "value": "int32x2x2_t" }, "Arguments_Preparation": { "a": { @@ -116277,23 +313472,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_s8", + "name": "vtrn_s8", "arguments": [ "int8x8_t a", "int8x8_t b" ], "return_type": { - "value": "int8x8_t" + "value": "int8x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116304,23 +313502,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_u16", + "name": "vtrn_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" ], "return_type": { - "value": "uint16x4_t" + "value": "uint16x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116331,23 +313532,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_u32", + "name": "vtrn_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" ], "return_type": { - "value": "uint32x2_t" + "value": "uint32x2x2_t" }, "Arguments_Preparation": { "a": { @@ -116358,23 +313562,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2_u8", + "name": "vtrn_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" ], "return_type": { - "value": "uint8x8_t" + "value": "uint8x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116385,23 +313592,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_f16", + "name": "vtrnq_f16", "arguments": [ "float16x8_t a", "float16x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "float16x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116412,23 +313622,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_f32", + "name": "vtrnq_f32", "arguments": [ "float32x4_t a", "float32x4_t b" ], "return_type": { - "value": "float32x4_t" + "value": "float32x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116439,50 +313652,86 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_f64", + "name": "vtrnq_p16", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "poly16x8_t a", + "poly16x8_t b" ], "return_type": { - "value": "float64x2_t" + "value": "poly16x8x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.8H" }, "b": { - "register": "Vm.2D" + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_p16", + "name": "vtrnq_p8", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "poly8x16x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "TRN1", + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtrnq_s16", + "arguments": [ + "int16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "int16x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116493,50 +313742,56 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_p64", + "name": "vtrnq_s32", "arguments": [ - "poly64x2_t a", - "poly64x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "poly64x2_t" + "value": "int32x4x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.4S" }, "b": { - "register": "Vm.2D" + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_p8", + "name": "vtrnq_s8", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "int8x16x2_t" }, "Arguments_Preparation": { "a": { @@ -116547,23 +313802,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_s16", + "name": "vtrnq_u16", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x8x2_t" }, "Arguments_Preparation": { "a": { @@ -116574,23 +313832,26 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_s32", + "name": "vtrnq_u32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "int32x4_t" + "value": "uint32x4x2_t" }, "Arguments_Preparation": { "a": { @@ -116601,165 +313862,178 @@ } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_s64", + "name": "vtrnq_u8", "arguments": [ - "int64x2_t a", - "int64x2_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "int64x2_t" + "value": "uint8x16x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, "b": { - "register": "Vm.2D" + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "TRN1", + "TRN2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_s8", + "name": "vtst_p64", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "poly64x1_t a", + "poly64x1_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, "b": { - "register": "Vm.16B" + "register": "Dm" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_u16", + "name": "vtst_p8", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_u32", + "name": "vtst_s16", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint32x4_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.4H" }, "b": { - "register": "Vm.4S" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_u64", + "name": "vtst_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" }, "b": { - "register": "Vm.2D" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp2q_u8", + "name": "vtst_s64", "arguments": [ - "uint8x16_t a", - "uint8x16_t b" + "int64x1_t a", + "int64x1_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Dn" }, "b": { - "register": "Vm.16B" + "register": "Dm" } }, "Architectures": [ @@ -116767,19 +314041,48 @@ ], "instructions": [ [ - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_f16", + "name": "vtst_s8", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float16x4x2_t" + "value": "uint8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "CMTST" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtst_u16", + "arguments": [ + "uint16x4_t a", + "uint16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { @@ -116796,20 +314099,19 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_f32", + "name": "vtst_u32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "float32x2x2_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { @@ -116826,50 +314128,46 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_p16", + "name": "vtst_u64", "arguments": [ - "poly16x4_t a", - "poly16x4_t b" + "uint64x1_t a", + "uint64x1_t b" ], "return_type": { - "value": "poly16x4x2_t" + "value": "uint64x1_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, "b": { - "register": "Vm.4H" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_p8", + "name": "vtst_u8", "arguments": [ - "poly8x8_t a", - "poly8x8_t b" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "poly8x8x2_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { @@ -116886,87 +314184,108 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_s16", + "name": "vtstd_s64", "arguments": [ - "int16x4_t a", - "int16x4_t b" + "int64_t a", + "int64_t b" ], "return_type": { - "value": "int16x4x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Dn" }, "b": { - "register": "Vm.4H" + "register": "Dm" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_s32", + "name": "vtstd_u64", "arguments": [ - "int32x2_t a", - "int32x2_t b" + "uint64_t a", + "uint64_t b" ], "return_type": { - "value": "int32x2x2_t" + "value": "uint64_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Dn" }, "b": { - "register": "Vm.2S" + "register": "Dm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMTST" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtstq_p64", + "arguments": [ + "poly64x2_t a", + "poly64x2_t b" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_s8", + "name": "vtstq_p8", "arguments": [ - "int8x8_t a", - "int8x8_t b" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "int8x8x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.16B" }, "b": { - "register": "Vm.8B" + "register": "Vm.16B" } }, "Architectures": [ @@ -116976,27 +314295,26 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_u16", + "name": "vtstq_s16", "arguments": [ - "uint16x4_t a", - "uint16x4_t b" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint16x4x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, "b": { - "register": "Vm.4H" + "register": "Vm.8H" } }, "Architectures": [ @@ -117006,27 +314324,26 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_u32", + "name": "vtstq_s32", "arguments": [ - "uint32x2_t a", - "uint32x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint32x2x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, "b": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -117036,27 +314353,53 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzp_u8", + "name": "vtstq_s64", "arguments": [ - "uint8x8_t a", - "uint8x8_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint8x8x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8B" + "register": "Vn.2D" }, "b": { - "register": "Vm.8B" + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMTST" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vtstq_s8", + "arguments": [ + "int8x16_t a", + "int8x16_t b" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" } }, "Architectures": [ @@ -117066,20 +314409,19 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_f16", + "name": "vtstq_u16", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float16x8x2_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { @@ -117096,20 +314438,19 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_f32", + "name": "vtstq_u32", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "float32x4x2_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -117126,50 +314467,46 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_p16", + "name": "vtstq_u64", "arguments": [ - "poly16x8_t a", - "poly16x8_t b" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly16x8x2_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, "b": { - "register": "Vm.8H" + "register": "Vm.2D" } }, "Architectures": [ - "v7", - "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_p8", + "name": "vtstq_u8", "arguments": [ - "poly8x16_t a", - "poly8x16_t b" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly8x16x2_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { @@ -117186,170 +314523,524 @@ ], "instructions": [ [ - "UZP1", - "UZP2" + "CMTST" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadd_s16", + "arguments": [ + "int16x4_t a", + "uint16x4_t b" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadd_s32", + "arguments": [ + "int32x2_t a", + "uint32x2_t b" + ], + "return_type": { + "value": "int32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2S" + }, + "b": { + "register": "Vn.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadd_s64", + "arguments": [ + "int64x1_t a", + "uint64x1_t b" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dd" + }, + "b": { + "register": "Dn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadd_s8", + "arguments": [ + "int8x8_t a", + "uint8x8_t b" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8B" + }, + "b": { + "register": "Vn.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddb_s8", + "arguments": [ + "int8_t a", + "uint8_t b" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Bd" + }, + "b": { + "register": "Bn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddd_s64", + "arguments": [ + "int64_t a", + "uint64_t b" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Dd" + }, + "b": { + "register": "Dn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddh_s16", + "arguments": [ + "int16_t a", + "uint16_t b" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hd" + }, + "b": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddq_s16", + "arguments": [ + "int16x8_t a", + "uint16x8_t b" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddq_s32", + "arguments": [ + "int32x4_t a", + "uint32x4_t b" + ], + "return_type": { + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4S" + }, + "b": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddq_s64", + "arguments": [ + "int64x2_t a", + "uint64x2_t b" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + }, + "b": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqaddq_s8", + "arguments": [ + "int8x16_t a", + "uint8x16_t b" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.16B" + }, + "b": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vuqadds_s32", + "arguments": [ + "int32_t a", + "uint32_t b" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Sd" + }, + "b": { + "register": "Sn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_s16", + "name": "vusdot_lane_s32", "arguments": [ - "int16x8_t a", - "int16x8_t b" + "int32x2_t r", + "uint8x8_t a", + "int8x8_t b", + "const int lane" ], "return_type": { - "value": "int16x8x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm.8H" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_s32", + "name": "vusdot_laneq_s32", "arguments": [ - "int32x4_t a", - "int32x4_t b" + "int32x2_t r", + "uint8x8_t a", + "int8x16_t b", + "const int lane" ], "return_type": { - "value": "int32x4x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.8B" }, "b": { - "register": "Vm.4S" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_s8", + "name": "vusdot_s32", "arguments": [ - "int8x16_t a", - "int8x16_t b" + "int32x2_t r", + "uint8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "int8x16x2_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm.16B" + "register": "Vm.8B" + }, + "r": { + "register": "Vd.2S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_u16", + "name": "vusdotq_lane_s32", "arguments": [ - "uint16x8_t a", - "uint16x8_t b" + "int32x4_t r", + "uint8x16_t a", + "int8x8_t b", + "const int lane" ], "return_type": { - "value": "uint16x8x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm.8H" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_u32", + "name": "vusdotq_laneq_s32", "arguments": [ - "uint32x4_t a", - "uint32x4_t b" + "int32x4_t r", + "uint8x16_t a", + "int8x16_t b", + "const int lane" ], "return_type": { - "value": "uint32x4x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vn.16B" }, "b": { - "register": "Vm.4S" + "register": "Vm.4B" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vuzpq_u8", + "name": "vusdotq_s32", "arguments": [ + "int32x4_t r", "uint8x16_t a", - "uint8x16_t b" + "int8x16_t b" ], "return_type": { - "value": "uint8x16x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { @@ -117357,53 +315048,56 @@ }, "b": { "register": "Vm.16B" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ - "v7", "A32", "A64" ], "instructions": [ [ - "UZP1", - "UZP2" + "USDOT" ] ] }, { "SIMD_ISA": "Neon", - "name": "vxarq_u64", + "name": "vusmmlaq_s32", "arguments": [ - "uint64x2_t a", - "uint64x2_t b", - "const int imm6" + "int32x4_t r", + "uint8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "uint64x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.16B" }, - "b": {}, - "imm6": { - "minimum": 0, - "maximum": 63 + "b": { + "register": "Vm.16B" + }, + "r": { + "register": "Vd.4S" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "XAR" + "USMMLA" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_f16", + "name": "vuzp1_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -117424,13 +315118,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_f32", + "name": "vuzp1_f32", "arguments": [ "float32x2_t a", "float32x2_t b" @@ -117451,13 +315145,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_p16", + "name": "vuzp1_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" @@ -117478,13 +315172,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_p8", + "name": "vuzp1_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" @@ -117505,13 +315199,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_s16", + "name": "vuzp1_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -117532,13 +315226,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_s32", + "name": "vuzp1_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -117559,13 +315253,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_s8", + "name": "vuzp1_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -117586,13 +315280,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_u16", + "name": "vuzp1_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -117613,13 +315307,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_u32", + "name": "vuzp1_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -117640,13 +315334,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1_u8", + "name": "vuzp1_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" @@ -117667,13 +315361,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_f16", + "name": "vuzp1q_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -117694,13 +315388,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_f32", + "name": "vuzp1q_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -117721,13 +315415,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_f64", + "name": "vuzp1q_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -117748,13 +315442,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_p16", + "name": "vuzp1q_p16", "arguments": [ "poly16x8_t a", "poly16x8_t b" @@ -117775,13 +315469,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_p64", + "name": "vuzp1q_p64", "arguments": [ "poly64x2_t a", "poly64x2_t b" @@ -117802,13 +315496,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_p8", + "name": "vuzp1q_p8", "arguments": [ "poly8x16_t a", "poly8x16_t b" @@ -117829,13 +315523,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_s16", + "name": "vuzp1q_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -117856,13 +315550,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_s32", + "name": "vuzp1q_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -117883,13 +315577,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_s64", + "name": "vuzp1q_s64", "arguments": [ "int64x2_t a", "int64x2_t b" @@ -117910,13 +315604,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_s8", + "name": "vuzp1q_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -117937,13 +315631,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_u16", + "name": "vuzp1q_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -117964,13 +315658,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_u32", + "name": "vuzp1q_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -117991,13 +315685,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_u64", + "name": "vuzp1q_u64", "arguments": [ "uint64x2_t a", "uint64x2_t b" @@ -118018,13 +315712,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip1q_u8", + "name": "vuzp1q_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -118045,13 +315739,13 @@ ], "instructions": [ [ - "ZIP1" + "UZP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_f16", + "name": "vuzp2_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -118072,13 +315766,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_f32", + "name": "vuzp2_f32", "arguments": [ "float32x2_t a", "float32x2_t b" @@ -118099,13 +315793,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_p16", + "name": "vuzp2_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" @@ -118126,13 +315820,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_p8", + "name": "vuzp2_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" @@ -118153,13 +315847,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_s16", + "name": "vuzp2_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -118180,13 +315874,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_s32", + "name": "vuzp2_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -118207,13 +315901,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_s8", + "name": "vuzp2_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -118234,13 +315928,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_u16", + "name": "vuzp2_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -118261,13 +315955,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_u32", + "name": "vuzp2_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -118288,13 +315982,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2_u8", + "name": "vuzp2_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" @@ -118315,13 +316009,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_f16", + "name": "vuzp2q_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -118342,13 +316036,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_f32", + "name": "vuzp2q_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -118369,13 +316063,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_f64", + "name": "vuzp2q_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -118396,13 +316090,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_p16", + "name": "vuzp2q_p16", "arguments": [ "poly16x8_t a", "poly16x8_t b" @@ -118423,13 +316117,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_p64", + "name": "vuzp2q_p64", "arguments": [ "poly64x2_t a", "poly64x2_t b" @@ -118450,13 +316144,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_p8", + "name": "vuzp2q_p8", "arguments": [ "poly8x16_t a", "poly8x16_t b" @@ -118477,13 +316171,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_s16", + "name": "vuzp2q_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -118504,13 +316198,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_s32", + "name": "vuzp2q_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -118531,13 +316225,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_s64", + "name": "vuzp2q_s64", "arguments": [ "int64x2_t a", "int64x2_t b" @@ -118558,13 +316252,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_s8", + "name": "vuzp2q_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -118585,13 +316279,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_u16", + "name": "vuzp2q_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -118612,13 +316306,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_u32", + "name": "vuzp2q_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -118639,13 +316333,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_u64", + "name": "vuzp2q_u64", "arguments": [ "uint64x2_t a", "uint64x2_t b" @@ -118666,13 +316360,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip2q_u8", + "name": "vuzp2q_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -118693,13 +316387,13 @@ ], "instructions": [ [ - "ZIP2" + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_f16", + "name": "vuzp_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -118722,14 +316416,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_f32", + "name": "vuzp_f32", "arguments": [ "float32x2_t a", "float32x2_t b" @@ -118752,14 +316446,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_p16", + "name": "vuzp_p16", "arguments": [ "poly16x4_t a", "poly16x4_t b" @@ -118782,14 +316476,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_p8", + "name": "vuzp_p8", "arguments": [ "poly8x8_t a", "poly8x8_t b" @@ -118812,14 +316506,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_s16", + "name": "vuzp_s16", "arguments": [ "int16x4_t a", "int16x4_t b" @@ -118842,14 +316536,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_s32", + "name": "vuzp_s32", "arguments": [ "int32x2_t a", "int32x2_t b" @@ -118872,14 +316566,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_s8", + "name": "vuzp_s8", "arguments": [ "int8x8_t a", "int8x8_t b" @@ -118902,14 +316596,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_u16", + "name": "vuzp_u16", "arguments": [ "uint16x4_t a", "uint16x4_t b" @@ -118932,14 +316626,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_u32", + "name": "vuzp_u32", "arguments": [ "uint32x2_t a", "uint32x2_t b" @@ -118962,14 +316656,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzip_u8", + "name": "vuzp_u8", "arguments": [ "uint8x8_t a", "uint8x8_t b" @@ -118992,14 +316686,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_f16", + "name": "vuzpq_f16", "arguments": [ "float16x8_t a", "float16x8_t b" @@ -119022,14 +316716,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_f32", + "name": "vuzpq_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -119052,14 +316746,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_p16", + "name": "vuzpq_p16", "arguments": [ "poly16x8_t a", "poly16x8_t b" @@ -119082,14 +316776,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_p8", + "name": "vuzpq_p8", "arguments": [ "poly8x16_t a", "poly8x16_t b" @@ -119112,14 +316806,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_s16", + "name": "vuzpq_s16", "arguments": [ "int16x8_t a", "int16x8_t b" @@ -119142,14 +316836,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_s32", + "name": "vuzpq_s32", "arguments": [ "int32x4_t a", "int32x4_t b" @@ -119172,14 +316866,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_s8", + "name": "vuzpq_s8", "arguments": [ "int8x16_t a", "int8x16_t b" @@ -119202,14 +316896,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_u16", + "name": "vuzpq_u16", "arguments": [ "uint16x8_t a", "uint16x8_t b" @@ -119232,14 +316926,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_u32", + "name": "vuzpq_u32", "arguments": [ "uint32x4_t a", "uint32x4_t b" @@ -119262,14 +316956,14 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vzipq_u8", + "name": "vuzpq_u8", "arguments": [ "uint8x16_t a", "uint8x16_t b" @@ -119292,14 +316986,46 @@ ], "instructions": [ [ - "ZIP1", - "ZIP2" + "UZP1", + "UZP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamin_f16", + "name": "vxarq_u64", + "arguments": [ + "uint64x2_t a", + "uint64x2_t b", + "const int imm6" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, + "imm6": { + "minimum": 0, + "maximum": 63 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_f16", "arguments": [ "float16x4_t a", "float16x4_t b" @@ -119320,26 +317046,26 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vaminq_f16", + "name": "vzip1_f32", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "float16x8_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm.8H" + "register": "Vm.2S" } }, "Architectures": [ @@ -119347,19 +317073,100 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamin_f32", + "name": "vzip1_p16", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "poly16x4_t a", + "poly16x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "poly16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_p8", + "arguments": [ + "poly8x8_t a", + "poly8x8_t b" + ], + "return_type": { + "value": "poly8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_s16", + "arguments": [ + "int16x4_t a", + "int16x4_t b" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_s32", + "arguments": [ + "int32x2_t a", + "int32x2_t b" + ], + "return_type": { + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { @@ -119374,13 +317181,148 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vaminq_f32", + "name": "vzip1_s8", + "arguments": [ + "int8x8_t a", + "int8x8_t b" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_u16", + "arguments": [ + "uint16x4_t a", + "uint16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_u32", + "arguments": [ + "uint32x2_t a", + "uint32x2_t b" + ], + "return_type": { + "value": "uint32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_u8", + "arguments": [ + "uint8x8_t a", + "uint8x8_t b" + ], + "return_type": { + "value": "uint8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_f32", "arguments": [ "float32x4_t a", "float32x4_t b" @@ -119401,13 +317343,13 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vaminq_f64", + "name": "vzip1q_f64", "arguments": [ "float64x2_t a", "float64x2_t b" @@ -119428,26 +317370,26 @@ ], "instructions": [ [ - "FAMIN" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamax_f16", + "name": "vzip1q_p16", "arguments": [ - "float16x4_t a", - "float16x4_t b" + "poly16x8_t a", + "poly16x8_t b" ], "return_type": { - "value": "float16x4_t" + "value": "poly16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.4H" + "register": "Vn.8H" }, "b": { - "register": "Vm.4H" + "register": "Vm.8H" } }, "Architectures": [ @@ -119455,19 +317397,73 @@ ], "instructions": [ [ - "FAMAX" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamaxq_f16", + "name": "vzip1q_p64", "arguments": [ - "float16x8_t a", - "float16x8_t b" + "poly64x2_t a", + "poly64x2_t b" ], "return_type": { - "value": "float16x8_t" + "value": "poly64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_p8", + "arguments": [ + "poly8x16_t a", + "poly8x16_t b" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_s16", + "arguments": [ + "int16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { @@ -119482,26 +317478,26 @@ ], "instructions": [ [ - "FAMAX" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamax_f32", + "name": "vzip1q_s32", "arguments": [ - "float32x2_t a", - "float32x2_t b" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "float32x2_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vn.4S" }, "b": { - "register": "Vm.2S" + "register": "Vm.4S" } }, "Architectures": [ @@ -119509,19 +317505,100 @@ ], "instructions": [ [ - "FAMAX" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamaxq_f32", + "name": "vzip1q_s64", "arguments": [ - "float32x4_t a", - "float32x4_t b" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "float32x4_t" + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_s8", + "arguments": [ + "int8x16_t a", + "int8x16_t b" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_u16", + "arguments": [ + "uint16x8_t a", + "uint16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_u32", + "arguments": [ + "uint32x4_t a", + "uint32x4_t b" + ], + "return_type": { + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { @@ -119536,26 +317613,107 @@ ], "instructions": [ [ - "FAMAX" + "ZIP1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vamaxq_f64", + "name": "vzip1q_u64", "arguments": [ - "float64x2_t a", - "float64x2_t b" + "uint64x2_t a", + "uint64x2_t b" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_u8", + "arguments": [ + "uint8x16_t a", + "uint8x16_t b" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip2_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vzip2_f32", + "arguments": [ + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "float64x2_t" + "value": "float32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.2D" + "register": "Vn.2S" }, "b": { - "register": "Vm.2D" + "register": "Vm.2S" } }, "Architectures": [ @@ -119563,34 +317721,26 @@ ], "instructions": [ [ - "FAMAX" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_f16", + "name": "vzip2_p16", "arguments": [ - "float16x4_t a", - "uint8x8_t b", - "const int index" + "poly16x4_t a", + "poly16x4_t b" ], "return_type": { - "value": "float16x8_t" + "value": "poly16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -119598,34 +317748,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_s16", + "name": "vzip2_p8", "arguments": [ - "int16x4_t a", - "uint8x8_t b", - "const int index" + "poly8x8_t a", + "poly8x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "poly8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8B" } }, "Architectures": [ @@ -119633,34 +317775,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_u16", + "name": "vzip2_s16", "arguments": [ - "uint16x4_t a", - "uint8x8_t b", - "const int index" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -119668,34 +317802,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_p16", + "name": "vzip2_s32", "arguments": [ - "poly16x4_t a", - "uint8x8_t b", - "const int index" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "int32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2S" } }, "Architectures": [ @@ -119703,34 +317829,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_f16", + "name": "vzip2_s8", "arguments": [ - "float16x4_t a", - "uint8x16_t b", - "const int index" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8B" } }, "Architectures": [ @@ -119738,34 +317856,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_s16", + "name": "vzip2_u16", "arguments": [ - "int16x4_t a", - "uint8x16_t b", - "const int index" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "uint16x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.4H" } }, "Architectures": [ @@ -119773,34 +317883,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_u16", + "name": "vzip2_u32", "arguments": [ - "uint16x4_t a", - "uint8x16_t b", - "const int index" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "uint32x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2S" } }, "Architectures": [ @@ -119808,34 +317910,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_p16", + "name": "vzip2_u8", "arguments": [ - "poly16x4_t a", - "uint8x16_t b", - "const int index" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.8B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8B" } }, "Architectures": [ @@ -119843,17 +317937,16 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_f16", + "name": "vzip2q_f16", "arguments": [ "float16x8_t a", - "uint8x8_t b", - "const int index" + "float16x8_t b" ], "return_type": { "value": "float16x8_t" @@ -119863,14 +317956,7 @@ "register": "Vn.8H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8H" } }, "Architectures": [ @@ -119878,34 +317964,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_s16", + "name": "vzip2q_f32", "arguments": [ - "int16x8_t a", - "uint8x8_t b", - "const int index" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "float32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.4S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.4S" } }, "Architectures": [ @@ -119913,34 +317991,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_u16", + "name": "vzip2q_f64", "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "const int index" + "float64x2_t a", + "float64x2_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "float64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2D" } }, "Architectures": [ @@ -119948,17 +318018,16 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_p16", + "name": "vzip2q_p16", "arguments": [ "poly16x8_t a", - "uint8x8_t b", - "const int index" + "poly16x8_t b" ], "return_type": { "value": "poly16x8_t" @@ -119968,14 +318037,7 @@ "register": "Vn.8H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8H" } }, "Architectures": [ @@ -119983,34 +318045,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_f16", + "name": "vzip2q_p64", "arguments": [ - "float16x8_t a", - "uint8x16_t b", - "const int index" + "poly64x2_t a", + "poly64x2_t b" ], "return_type": { - "value": "float16x8_t" + "value": "poly64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2D" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2D" } }, "Architectures": [ @@ -120018,34 +318072,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_s16", + "name": "vzip2q_p8", "arguments": [ - "int16x8_t a", - "uint8x16_t b", - "const int index" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "int16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.16B" } }, "Architectures": [ @@ -120053,34 +318099,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_u16", + "name": "vzip2q_s16", "arguments": [ - "uint16x8_t a", - "uint8x16_t b", - "const int index" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "int16x8_t" }, "Arguments_Preparation": { "a": { "register": "Vn.8H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.8H" } }, "Architectures": [ @@ -120088,34 +318126,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_u8", + "name": "vzip2q_s32", "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "const int lane" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4S" } }, "Architectures": [ @@ -120123,34 +318153,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_u8", + "name": "vzip2q_s64", "arguments": [ - "uint8x16_t a", - "uint8x8_t b", - "const int lane" + "int64x2_t a", + "int64x2_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.2D" } }, "Architectures": [ @@ -120158,17 +318180,16 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_s8", + "name": "vzip2q_s8", "arguments": [ - "int8x8_t a", - "uint8x8_t b", - "const int lane" + "int8x16_t a", + "int8x16_t b" ], "return_type": { "value": "int8x16_t" @@ -120178,14 +318199,7 @@ "register": "Vn.16B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.16B" } }, "Architectures": [ @@ -120193,34 +318207,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_s8", + "name": "vzip2q_u16", "arguments": [ - "int8x16_t a", - "uint8x8_t b", - "const int lane" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint16x8_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.8H" } }, "Architectures": [ @@ -120228,34 +318234,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_p8", + "name": "vzip2q_u32", "arguments": [ - "poly8x8_t a", - "uint8x8_t b", - "const int lane" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint32x4_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4S" } }, "Architectures": [ @@ -120263,34 +318261,26 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_p8", + "name": "vzip2q_u64", "arguments": [ - "poly8x16_t a", - "uint8x8_t b", - "const int lane" + "uint64x2_t a", + "uint64x2_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "uint64x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2D" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.2D" } }, "Architectures": [ @@ -120298,17 +318288,16 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_u8", + "name": "vzip2q_u8", "arguments": [ - "uint8x8_t a", - "uint8x16_t b", - "const int index" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { "value": "uint8x16_t" @@ -120318,14 +318307,7 @@ "register": "Vn.16B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.16B" } }, "Architectures": [ @@ -120333,707 +318315,607 @@ ], "instructions": [ [ - "LUTI2" + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_u8", + "name": "vzip_f16", "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "const int index" + "float16x4_t a", + "float16x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "float16x4x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_s8", + "name": "vzip_f32", "arguments": [ - "int8x8_t a", - "uint8x16_t b", - "const int index" + "float32x2_t a", + "float32x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "float32x2x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.2S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_s8", + "name": "vzip_p16", "arguments": [ - "int8x16_t a", - "uint8x16_t b", - "const int index" + "poly16x4_t a", + "poly16x4_t b" ], "return_type": { - "value": "int8x16_t" + "value": "poly16x4x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2_laneq_p8", + "name": "vzip_p8", "arguments": [ "poly8x8_t a", - "uint8x16_t b", - "const int index" + "poly8x8_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "poly8x8x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.8B" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_p8", + "name": "vzip_s16", "arguments": [ - "poly8x16_t a", - "uint8x16_t b", - "const int index" + "int16x4_t a", + "int16x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "int16x4x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.16B" + "register": "Vn.4H" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_p16", + "name": "vzip_s32", "arguments": [ - "poly16x8_t a", - "uint8x16_t b", - "const int index" + "int32x2_t a", + "int32x2_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "int32x2x2_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.2S" }, "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI2" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_u8", + "name": "vzip_s8", "arguments": [ - "uint8x16_t vn", - "uint8x8_t vm", - "const int index" + "int8x8_t a", + "int8x8_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "int8x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vn.8B" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_u8", + "name": "vzip_u16", "arguments": [ - "uint8x16_t vn", - "uint8x16_t vm", - "const int index" + "uint16x4_t a", + "uint16x4_t b" ], "return_type": { - "value": "uint8x16_t" + "value": "uint16x4x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.4H" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.4H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_s8", + "name": "vzip_u32", "arguments": [ - "int8x16_t vn", - "uint8x8_t vm", - "const int index" + "uint32x2_t a", + "uint32x2_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint32x2x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vn.2S" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.2S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_s8", + "name": "vzip_u8", "arguments": [ - "int8x16_t vn", - "uint8x16_t vm", - "const int index" + "uint8x8_t a", + "uint8x8_t b" ], "return_type": { - "value": "int8x16_t" + "value": "uint8x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.8B" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.8B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_p8", + "name": "vzipq_f16", "arguments": [ - "poly8x16_t vn", - "uint8x8_t vm", - "const int index" + "float16x8_t a", + "float16x8_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "float16x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 + "a": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_p8", + "name": "vzipq_f32", "arguments": [ - "poly8x16_t vn", - "uint8x16_t vm", - "const int index" + "float32x4_t a", + "float32x4_t b" ], "return_type": { - "value": "poly8x16_t" + "value": "float32x4x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.4S" }, - "r": { - "register": "Vd.16B" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_u16_x2", + "name": "vzipq_p16", "arguments": [ - "uint16x8x2_t vn", - "uint8x8_t vm", - "const int index" + "poly16x8_t a", + "poly16x8_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "poly16x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_u16_x2", + "name": "vzipq_p8", "arguments": [ - "uint16x8x2_t vn", - "uint8x16_t vm", - "const int index" + "poly8x16_t a", + "poly8x16_t b" ], "return_type": { - "value": "uint16x8_t" + "value": "poly8x16x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_s16_x2", + "name": "vzipq_s16", "arguments": [ - "int16x8x2_t vn", - "uint8x8_t vm", - "const int index" + "int16x8_t a", + "int16x8_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int16x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_s16_x2", + "name": "vzipq_s32", "arguments": [ - "int16x8x2_t vn", - "uint8x16_t vm", - "const int index" + "int32x4_t a", + "int32x4_t b" ], "return_type": { - "value": "int16x8_t" + "value": "int32x4x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.4S" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_f16_x2", + "name": "vzipq_s8", "arguments": [ - "float16x8x2_t vn", - "uint8x8_t vm", - "const int index" + "int8x16_t a", + "int8x16_t b" ], "return_type": { - "value": "float16x8_t" + "value": "int8x16x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_f16_x2", + "name": "vzipq_u16", "arguments": [ - "float16x8x2_t vn", - "uint8x16_t vm", - "const int index" + "uint16x8_t a", + "uint16x8_t b" ], "return_type": { - "value": "float16x8_t" + "value": "uint16x8x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.8H" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.8H" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_lane_p16_x2", + "name": "vzipq_u32", "arguments": [ - "poly16x8x2_t vn", - "uint8x8_t vm", - "const int index" + "uint32x4_t a", + "uint32x4_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint32x4x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 + "a": { + "register": "Vn.4S" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.4S" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, { "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_p16_x2", + "name": "vzipq_u8", "arguments": [ - "poly16x8x2_t vn", - "uint8x16_t vm", - "const int index" + "uint8x16_t a", + "uint8x16_t b" ], "return_type": { - "value": "poly16x8_t" + "value": "uint8x16x2_t" }, "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 + "a": { + "register": "Vn.16B" }, - "r": { - "register": "Vd.8H" + "b": { + "register": "Vm.16B" } }, "Architectures": [ + "v7", + "A32", "A64" ], "instructions": [ [ - "LUTI4" + "ZIP1", + "ZIP2" ] ] }, diff --git a/stdarch/rust-version b/stdarch/rust-version index db9492636f6ac..59e9e5a0e6ee9 100644 --- a/stdarch/rust-version +++ b/stdarch/rust-version @@ -1 +1 @@ -eda4fc7733ee89e484d7120cafbd80dcb2fce66e +045b17737dab5fcc28e4cbee0cfe2ce4ed363b32 diff --git a/stdarch/triagebot.toml b/stdarch/triagebot.toml index 621f39b2cbbf3..5b178f0cdf456 100644 --- a/stdarch/triagebot.toml +++ b/stdarch/triagebot.toml @@ -1,7 +1,7 @@ [assign] [assign.owners] -"*" = ["@Amanieu", "@folkertdev", "@sayantn"] +"*" = ["@Amanieu", "@folkertdev", "@sayantn", "@davidtwco", "@adamgemmell"] [ping.windows] message = """\ diff --git a/test/src/console.rs b/test/src/console.rs index 13b2b3d502c81..b1c5404a7160c 100644 --- a/test/src/console.rs +++ b/test/src/console.rs @@ -16,7 +16,7 @@ use super::helpers::metrics::MetricMap; use super::options::{Options, OutputFormat}; use super::test_result::TestResult; use super::time::{TestExecTime, TestSuiteExecTime}; -use super::types::{NamePadding, TestDesc, TestDescAndFn}; +use super::types::{NamePadding, TestDesc, TestDescAndFn, TestList}; use super::{filter_tests, run_tests, term}; /// Generic wrapper over stdout. @@ -170,7 +170,7 @@ impl ConsoleTestState { } // List the tests to console, and optionally to logfile. Filters are honored. -pub(crate) fn list_tests_console(opts: &TestOpts, tests: Vec) -> io::Result<()> { +pub(crate) fn list_tests_console(opts: &TestOpts, tests: TestList) -> io::Result<()> { let output = match term::stdout() { None => OutputLocation::Raw(io::stdout().lock()), Some(t) => OutputLocation::Pretty(t), @@ -186,7 +186,7 @@ pub(crate) fn list_tests_console(opts: &TestOpts, tests: Vec) -> let mut st = ConsoleTestDiscoveryState::new(opts)?; out.write_discovery_start()?; - for test in filter_tests(opts, tests).into_iter() { + for test in filter_tests(opts, tests) { use crate::TestFn::*; let TestDescAndFn { desc, testfn } = test; @@ -307,8 +307,9 @@ pub(crate) fn get_formatter(opts: &TestOpts, max_name_len: usize) -> Box) -> io::Result { +pub fn run_tests_console(opts: &TestOpts, tests: TestList) -> io::Result { let max_name_len = tests + .tests .iter() .max_by_key(|t| len_if_padded(t)) .map(|t| t.desc.name.as_slice().len()) diff --git a/test/src/lib.rs b/test/src/lib.rs index f3dbd3d0556ab..791af5f8ee2a9 100644 --- a/test/src/lib.rs +++ b/test/src/lib.rs @@ -49,7 +49,7 @@ pub mod test { pub use crate::time::{TestExecTime, TestTimeOptions}; pub use crate::types::{ DynTestFn, DynTestName, StaticBenchFn, StaticTestFn, StaticTestName, TestDesc, - TestDescAndFn, TestId, TestName, TestType, + TestDescAndFn, TestId, TestList, TestListOrder, TestName, TestType, }; pub use crate::{assert_test_result, filter_tests, run_test, test_main, test_main_static}; } @@ -106,6 +106,16 @@ pub fn test_main_with_exit_callback( tests: Vec, options: Option, exit_callback: F, +) { + let tests = TestList::new(tests, TestListOrder::Unsorted); + test_main_inner(args, tests, options, exit_callback) +} + +fn test_main_inner( + args: &[String], + tests: TestList, + options: Option, + exit_callback: F, ) { let mut opts = match cli::parse_opts(args) { Some(Ok(o)) => o, @@ -180,7 +190,9 @@ pub fn test_main_with_exit_callback( pub fn test_main_static(tests: &[&TestDescAndFn]) { let args = env::args().collect::>(); let owned_tests: Vec<_> = tests.iter().map(make_owned_test).collect(); - test_main(&args, owned_tests, None) + // Tests are sorted by name at compile time by mk_tests_slice. + let tests = TestList::new(owned_tests, TestListOrder::Sorted); + test_main_inner(&args, tests, None, || {}) } /// A variant optimized for invocation with a static test vector. @@ -229,7 +241,9 @@ pub fn test_main_static_abort(tests: &[&TestDescAndFn]) { let args = env::args().collect::>(); let owned_tests: Vec<_> = tests.iter().map(make_owned_test).collect(); - test_main(&args, owned_tests, Some(Options::new().panic_abort(true))) + // Tests are sorted by name at compile time by mk_tests_slice. + let tests = TestList::new(owned_tests, TestListOrder::Sorted); + test_main_inner(&args, tests, Some(Options::new().panic_abort(true)), || {}) } /// Clones static values for putting into a dynamic vector, which test_main() @@ -298,7 +312,7 @@ impl FilteredTests { pub fn run_tests( opts: &TestOpts, - tests: Vec, + tests: TestList, mut notify_about_test_event: F, ) -> io::Result<()> where @@ -334,7 +348,7 @@ where timeout: Instant, } - let tests_len = tests.len(); + let tests_len = tests.tests.len(); let mut filtered = FilteredTests { tests: Vec::new(), benches: Vec::new(), next_id: 0 }; @@ -512,25 +526,48 @@ where Ok(()) } -pub fn filter_tests(opts: &TestOpts, tests: Vec) -> Vec { +pub fn filter_tests(opts: &TestOpts, tests: TestList) -> Vec { + let TestList { tests, order } = tests; let mut filtered = tests; - let matches_filter = |test: &TestDescAndFn, filter: &str| { - let test_name = test.desc.name.as_slice(); - - match opts.filter_exact { - true => test_name == filter, - false => test_name.contains(filter), - } - }; - // Remove tests that don't match the test filter + // Remove tests that don't match the test filter. if !opts.filters.is_empty() { - filtered.retain(|test| opts.filters.iter().any(|filter| matches_filter(test, filter))); + if opts.filter_exact && order == TestListOrder::Sorted { + // Let's say that `f` is the number of filters and `n` is the number + // of tests. + // + // The test array is sorted by name (guaranteed by the caller via + // TestListOrder::Sorted), so use binary search for O(f log n) + // exact-match lookups instead of an O(n) linear scan. + // + // This is important for Miri, where the interpreted execution makes + // the linear scan very expensive. + filtered = filter_exact_match(filtered, &opts.filters); + } else { + filtered.retain(|test| { + let test_name = test.desc.name.as_slice(); + opts.filters.iter().any(|filter| { + if opts.filter_exact { + test_name == filter.as_str() + } else { + test_name.contains(filter.as_str()) + } + }) + }); + } } // Skip tests that match any of the skip filters + // + // After exact positive filtering above, the filtered set is small, so a + // linear scan is acceptable even under Miri. if !opts.skip.is_empty() { - filtered.retain(|test| !opts.skip.iter().any(|sf| matches_filter(test, sf))); + filtered.retain(|test| { + let name = test.desc.name.as_slice(); + !opts.skip.iter().any(|sf| { + if opts.filter_exact { name == sf.as_str() } else { name.contains(sf.as_str()) } + }) + }); } // Excludes #[should_panic] tests @@ -553,6 +590,30 @@ pub fn filter_tests(opts: &TestOpts, tests: Vec) -> Vec, filters: &[String]) -> Vec { + // Binary search for each filter in the sorted test list. + let mut indexes: Vec = filters + .iter() + .filter_map(|f| tests.binary_search_by(|t| t.desc.name.as_slice().cmp(f.as_str())).ok()) + .collect(); + indexes.sort_unstable(); + indexes.dedup(); + + // Extract matching tests. Process indexes in descending order so that + // swap_remove (which replaces the removed element with the last) does not + // invalidate indexes we haven't visited yet. + let mut result = Vec::with_capacity(indexes.len()); + for &idx in indexes.iter().rev() { + result.push(tests.swap_remove(idx)); + } + // Reverse to restore the original sorted order, since we extracted the + // matching tests in descending index order. + result.reverse(); + result +} + pub fn convert_benchmarks_to_tests(tests: Vec) -> Vec { // convert benchmarks to tests, if we're not benchmarking them tests diff --git a/test/src/tests.rs b/test/src/tests.rs index d986bd74f772b..b25462cce1f99 100644 --- a/test/src/tests.rs +++ b/test/src/tests.rs @@ -477,7 +477,7 @@ fn filter_for_ignored_option() { opts.run_tests = true; opts.run_ignored = RunIgnored::Only; - let tests = one_ignored_one_unignored_test(); + let tests = TestList::new(one_ignored_one_unignored_test(), TestListOrder::Unsorted); let filtered = filter_tests(&opts, tests); assert_eq!(filtered.len(), 1); @@ -494,7 +494,7 @@ fn run_include_ignored_option() { opts.run_tests = true; opts.run_ignored = RunIgnored::Yes; - let tests = one_ignored_one_unignored_test(); + let tests = TestList::new(one_ignored_one_unignored_test(), TestListOrder::Unsorted); let filtered = filter_tests(&opts, tests); assert_eq!(filtered.len(), 2); @@ -527,7 +527,7 @@ fn exclude_should_panic_option() { testfn: DynTestFn(Box::new(move || Ok(()))), }); - let filtered = filter_tests(&opts, tests); + let filtered = filter_tests(&opts, TestList::new(tests, TestListOrder::Unsorted)); assert_eq!(filtered.len(), 2); assert!(filtered.iter().all(|test| test.desc.should_panic == ShouldPanic::No)); @@ -535,8 +535,8 @@ fn exclude_should_panic_option() { #[test] fn exact_filter_match() { - fn tests() -> Vec { - ["base", "base::test", "base::test1", "base::test2"] + fn tests() -> TestList { + let tests = ["base", "base::test", "base::test1", "base::test2"] .into_iter() .map(|name| TestDescAndFn { desc: TestDesc { @@ -555,7 +555,8 @@ fn exact_filter_match() { }, testfn: DynTestFn(Box::new(move || Ok(()))), }) - .collect() + .collect(); + TestList::new(tests, TestListOrder::Sorted) } let substr = @@ -908,7 +909,8 @@ fn test_dyn_bench_returning_err_fails_when_run_as_test() { } Ok(()) }; - run_tests(&TestOpts { run_tests: true, ..TestOpts::new() }, vec![desc], notify).unwrap(); + let tests = TestList::new(vec![desc], TestListOrder::Unsorted); + run_tests(&TestOpts { run_tests: true, ..TestOpts::new() }, tests, notify).unwrap(); let result = rx.recv().unwrap().result; assert_eq!(result, TrFailed); } diff --git a/test/src/types.rs b/test/src/types.rs index 802cab989c6a9..14c81bc2d1cf1 100644 --- a/test/src/types.rs +++ b/test/src/types.rs @@ -284,3 +284,30 @@ impl TestDescAndFn { } } } + +/// Whether a [`TestList`]'s tests are known to be sorted by name. +/// +/// When tests are sorted, `filter_tests` can use binary search for `--exact` +/// matches instead of a linear scan. +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TestListOrder { + /// Tests are sorted by name. This is guaranteed for tests generated by + /// `rustc --test` (see `mk_tests_slice` in + /// `compiler/rustc_builtin_macros/src/test_harness.rs`). + Sorted, + /// Test order is unknown; binary search must not be used. + Unsorted, +} + +/// A list of tests, tagged with whether they are sorted by name. +#[derive(Debug)] +pub struct TestList { + pub tests: Vec, + pub order: TestListOrder, +} + +impl TestList { + pub fn new(tests: Vec, order: TestListOrder) -> Self { + Self { tests, order } + } +} diff --git a/unwind/src/lib.rs b/unwind/src/lib.rs index cce6ca748cccd..22568d5f6f1f9 100644 --- a/unwind/src/lib.rs +++ b/unwind/src/lib.rs @@ -33,6 +33,7 @@ cfg_select! { target_os = "psp", target_os = "solid_asp3", all(target_vendor = "fortanix", target_env = "sgx"), + all(target_os = "wasi", panic = "unwind"), ) => { mod libunwind; pub use libunwind::*; diff --git a/unwind/src/libunwind.rs b/unwind/src/libunwind.rs index 091efa9c51292..ead6e0827501d 100644 --- a/unwind/src/libunwind.rs +++ b/unwind/src/libunwind.rs @@ -75,7 +75,7 @@ pub const unwinder_private_data_size: usize = 2; #[cfg(all(target_arch = "wasm32", target_os = "emscripten"))] pub const unwinder_private_data_size: usize = 20; -#[cfg(all(target_arch = "wasm32", target_os = "linux"))] +#[cfg(all(target_arch = "wasm32", any(target_os = "linux", target_os = "wasi")))] pub const unwinder_private_data_size: usize = 2; #[cfg(target_arch = "hexagon")] @@ -111,6 +111,13 @@ pub type _Unwind_Exception_Cleanup_Fn = ), link(name = "unwind", kind = "static", modifiers = "-bundle") )] +// Explicitly link the `unwind` library on WASI targets. +// +// This is provided in the self-contained sysroot for WASI targets by default. +// Note that Rust defaults to `-Cpanic=abort` on WASI targets meaning that this +// doesn't end up getting used by default, but this does mean that with +// `-Zbuild-std` this'll automatically link it in. +#[cfg_attr(target_os = "wasi", link(name = "unwind"))] unsafe extern "C-unwind" { pub fn _Unwind_Resume(exception: *mut _Unwind_Exception) -> !; } diff --git a/windows-sys/Cargo.toml b/windows-sys/Cargo.toml new file mode 100644 index 0000000000000..eb27eff15e842 --- /dev/null +++ b/windows-sys/Cargo.toml @@ -0,0 +1,16 @@ +# dlmalloc has a dependency on windows-sys for when it gets compiled for Windows. +# std however never actually uses dlmalloc on Windows. As dlmalloc is the only +# user of windows-sys in the standard library, the windows-sys crate unnecessarily +# increases the size of the vendored crates. By replacing it with an empty crate +# we save about 19MB. + +[package] +name = "windows-sys" +version = "0.61.100" +edition = "2024" + +[features] +Win32_Foundation = [] +Win32_System_Memory = [] +Win32_System_Threading = [] +Win32_System_SystemInformation = [] diff --git a/windows-sys/src/lib.rs b/windows-sys/src/lib.rs new file mode 100644 index 0000000000000..112740ab2d1b4 --- /dev/null +++ b/windows-sys/src/lib.rs @@ -0,0 +1 @@ +compile_error!("This crate should never be compiled");

::Metadata ); -define!("mir_retag", fn Retag(place: T)); define!("mir_move", fn Move(place: T) -> T); define!("mir_static", fn Static(s: T) -> &'static T); define!("mir_static_mut", fn StaticMut(s: T) -> *mut T); diff --git a/core/src/intrinsics/mod.rs b/core/src/intrinsics/mod.rs index 6f9d351300168..78d7314c58110 100644 --- a/core/src/intrinsics/mod.rs +++ b/core/src/intrinsics/mod.rs @@ -53,7 +53,7 @@ issue = "none" )] -use crate::ffi::va_list::{VaArgSafe, VaList}; +use crate::ffi::{VaArgSafe, VaList}; use crate::marker::{ConstParamTy, DiscriminantKind, PointeeSized, Tuple}; use crate::{mem, ptr}; @@ -364,6 +364,8 @@ pub fn rustc_peek(_: T) -> T; /// On Unix, the /// process will probably terminate with a signal like `SIGABRT`, `SIGILL`, `SIGTRAP`, `SIGSEGV` or /// `SIGBUS`. The precise behavior is not guaranteed and not stable. +/// +/// The stabilization-track version of this intrinsic is [`core::process::abort_immediate`]. #[rustc_nounwind] #[rustc_intrinsic] pub fn abort() -> !; @@ -2230,7 +2232,7 @@ pub const fn discriminant_value(v: &T) -> ::Discrimina /// Rust's "try catch" construct for unwinding. Invokes the function pointer `try_fn` with the /// data pointer `data`, and calls `catch_fn` if unwinding occurs while `try_fn` runs. -/// Returns `1` if unwinding occurred and `catch_fn` was called; returns `0` otherwise. +/// Returns `true` if unwinding occurred and `catch_fn` was called; returns `false` otherwise. /// /// `catch_fn` must not unwind. /// @@ -2247,11 +2249,11 @@ pub const fn discriminant_value(v: &T) -> ::Discrimina /// version of this intrinsic, `std::panic::catch_unwind`. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn catch_unwind( - _try_fn: fn(*mut u8), - _data: *mut u8, - _catch_fn: fn(*mut u8, *mut u8), -) -> i32; +pub unsafe fn catch_unwind( + _try_fn: unsafe fn(*mut Data), + _data: *mut Data, + _catch_fn: unsafe fn(*mut Data, *mut u8), +) -> bool; /// Emits a `nontemporal` store, which gives a hint to the CPU that the data should not be held /// in cache. Except for performance, this is fully equivalent to `ptr.write(val)`. @@ -2932,7 +2934,64 @@ pub const fn type_id() -> crate::any::TypeId; #[rustc_intrinsic] #[rustc_do_not_const_check] pub const fn type_id_eq(a: crate::any::TypeId, b: crate::any::TypeId) -> bool { - a.data == b.data + // SAFETY: we know `TypeId` is 16 bytes of initialized data. + // This is runtime-only code so we do not have to worry about provenance. + unsafe { crate::mem::transmute::<_, u128>(a) == crate::mem::transmute::<_, u128>(b) } +} + +/// Gets the size of the type represented by this `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::size`]. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +pub const fn size_of_type_id(_id: crate::any::TypeId) -> Option { + panic!("`TypeId::size` can only be called at compile-time") +} + +/// Gets the number of variants of the type represented by this `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::variants`]. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +pub const fn type_id_variants(_id: crate::any::TypeId) -> usize { + panic!("`TypeId::variants` can only be called at compile-time") +} + +/// Gets the number of fields at the given `variant_index` represented by this `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::fields`]. +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +pub const fn type_id_fields(_id: crate::any::TypeId, _variant_index: usize) -> usize { + panic!("`TypeId::fields` can only be called at compile-time") +} + +/// Gets the [`FieldRepresentingType`]'s `TypeId` at the given index of the type represented by this `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::any::TypeId::field`]. +/// +/// [`FieldRepresentingType`]: crate::field::FieldRepresentingType +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +pub const fn type_id_field_representing_type( + _id: crate::any::TypeId, + _variant_index: usize, + _field_index: usize, +) -> crate::any::TypeId { + panic!("`TypeId::field` can only be called at compile-time") +} + +/// Gets the actual field `TypeId` of the [`FieldRepresentingType`]'s `TypeId`. +/// +/// The more user-friendly version of this intrinsic is [`core::mem::type_info::FieldId::type_id`]. +/// +/// [`FieldRepresentingType`]: crate::field::FieldRepresentingType +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +pub const fn field_representing_type_actual_type_id( + _frt_type_id: crate::any::TypeId, +) -> crate::any::TypeId { + panic!("`FieldId::type_id` can only be called at compile-time") } /// Lowers in MIR to `Rvalue::Aggregate` with `AggregateKind::RawPtr`. @@ -3510,6 +3569,7 @@ pub const fn offload( f: F, workgroup_dim: [u32; 3], thread_dim: [u32; 3], + dyn_cache: u32, args: T, ) -> R; @@ -3587,3 +3647,16 @@ pub const fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { pub const unsafe fn va_end(ap: &mut VaList<'_>) { /* deliberately does nothing */ } + +/// Returns the return address of the caller function (after inlining) in a best-effort manner or a null pointer if it is not supported on the current backend. +/// Returning an accurate value is a quality-of-implementation concern, but no hard guarantees are +/// made about the return value: formally, the intrinsic non-deterministically returns +/// an arbitrary pointer without provenance. +/// +/// Note that unlike most intrinsics, this is safe to call. This is because it only finds the return address of the immediate caller, which is guaranteed to be possible. +/// Other forms of the corresponding gcc or llvm intrinsic (which can have wildly unpredictable results or even crash at runtime) are not exposed. +#[rustc_intrinsic] +#[rustc_nounwind] +pub fn return_address() -> *const () { + core::ptr::null() +} diff --git a/core/src/intrinsics/simd.rs b/core/src/intrinsics/simd/mod.rs similarity index 98% rename from core/src/intrinsics/simd.rs rename to core/src/intrinsics/simd/mod.rs index ae86690dc418d..9311dcc9bd00e 100644 --- a/core/src/intrinsics/simd.rs +++ b/core/src/intrinsics/simd/mod.rs @@ -2,6 +2,8 @@ //! //! In this module, a "vector" is any `repr(simd)` type. +pub mod scalable; + use crate::marker::ConstParamTy; /// Inserts an element into a vector, returning the updated vector. @@ -518,7 +520,7 @@ pub unsafe fn simd_reduce_mul_unordered(x: T) -> U; /// Checks if all mask values are true. /// -/// `T` must be a vector of integer primitive types. +/// `T` must be a vector of integers. /// /// # Safety /// `x` must contain only `0` or `!0`. @@ -528,7 +530,7 @@ pub const unsafe fn simd_reduce_all(x: T) -> bool; /// Checks if any mask value is true. /// -/// `T` must be a vector of integer primitive types. +/// `T` must be a vector of integers. /// /// # Safety /// `x` must contain only `0` or `!0`. @@ -538,29 +540,25 @@ pub const unsafe fn simd_reduce_any(x: T) -> bool; /// Returns the maximum element of a vector. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. -/// -/// For floating-point values, uses IEEE-754 `maxNum`. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_reduce_max(x: T) -> U; /// Returns the minimum element of a vector. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. -/// -/// For floating-point values, uses IEEE-754 `minNum`. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_reduce_min(x: T) -> U; /// Logical "and"s all elements together. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. #[rustc_intrinsic] @@ -569,7 +567,7 @@ pub const unsafe fn simd_reduce_and(x: T) -> U; /// Logical "ors" all elements together. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. #[rustc_intrinsic] @@ -578,7 +576,7 @@ pub const unsafe fn simd_reduce_or(x: T) -> U; /// Logical "exclusive ors" all elements together. /// -/// `T` must be a vector of integers or floats. +/// `T` must be a vector of integers. /// /// `U` must be the element type of `T`. #[rustc_intrinsic] diff --git a/core/src/intrinsics/simd/scalable.rs b/core/src/intrinsics/simd/scalable.rs new file mode 100644 index 0000000000000..a8984b3a2f7db --- /dev/null +++ b/core/src/intrinsics/simd/scalable.rs @@ -0,0 +1,66 @@ +//! Scalable vector compiler intrinsics. +//! +//! In this module, a "vector" is any `#[rustc_scalable_vector]`-annotated type. + +/// Create a tuple of two vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svcreate2*` builtins. +#[rustc_nounwind] +#[rustc_intrinsic] +pub unsafe fn sve_tuple_create2(x0: SVec, x1: SVec) -> SVecTup; + +/// Create a tuple of three vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svcreate3*` builtins. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn sve_tuple_create3(x0: SVec, x1: SVec, x2: SVec) -> SVecTup; + +/// Create a tuple of four vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svcreate4*` builtins. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn sve_tuple_create4(x0: SVec, x1: SVec, x2: SVec, x3: SVec) -> SVecTup; + +/// Get one vector from a tuple of vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svget*` builtins. +/// +/// # Safety +/// +/// `IDX` must be in-bounds of the tuple. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn sve_tuple_get(tuple: SVecTup) -> SVec; + +/// Change one vector in a tuple of vectors. +/// +/// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a +/// scalable vector (`#[rustc_scalable_vector(N)]`). `SVecTup` must be a tuple of vectors of +/// type `SVec`. +/// +/// Corresponds to Clang's `__builtin_sve_svset*` builtins. +/// +/// # Safety +/// +/// `IDX` must be in-bounds of the tuple. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn sve_tuple_set(tuple: SVecTup, x: SVec) -> SVecTup; diff --git a/core/src/io/borrowed_buf.rs b/core/src/io/borrowed_buf.rs index 088dea7812945..6b85e89551b69 100644 --- a/core/src/io/borrowed_buf.rs +++ b/core/src/io/borrowed_buf.rs @@ -2,20 +2,18 @@ use crate::fmt::{self, Debug, Formatter}; use crate::mem::{self, MaybeUninit}; -use crate::{cmp, ptr}; +use crate::ptr; -/// A borrowed byte buffer which is incrementally filled and initialized. +/// A borrowed byte buffer which is incrementally filled. /// -/// This type is a sort of "double cursor". It tracks three regions in the buffer: a region at the beginning of the -/// buffer that has been logically filled with data, a region that has been initialized at some point but not yet -/// logically filled, and a region at the end that is fully uninitialized. The filled region is guaranteed to be a -/// subset of the initialized region. +/// This type makes it safer to work with `MaybeUninit` buffers, such as to read into a buffer +/// without having to initialize it first. It tracks the region of bytes that have been filled and +/// whether the unfilled region was initialized. /// /// In summary, the contents of the buffer can be visualized as: /// ```not_rust -/// [ capacity ] -/// [ filled | unfilled ] -/// [ initialized | uninitialized ] +/// [ capacity ] +/// [ filled | unfilled (may be initialized) ] /// ``` /// /// A `BorrowedBuf` is created around some existing data (or capacity for data) via a unique reference @@ -30,8 +28,8 @@ pub struct BorrowedBuf<'data> { buf: &'data mut [MaybeUninit], /// The length of `self.buf` which is known to be filled. filled: usize, - /// The length of `self.buf` which is known to be initialized. - init: usize, + /// Whether the entire unfilled part of `self.buf` has explicitly been initialized. + init: bool, } impl Debug for BorrowedBuf<'_> { @@ -48,24 +46,20 @@ impl Debug for BorrowedBuf<'_> { impl<'data> From<&'data mut [u8]> for BorrowedBuf<'data> { #[inline] fn from(slice: &'data mut [u8]) -> BorrowedBuf<'data> { - let len = slice.len(); - BorrowedBuf { // SAFETY: initialized data never becoming uninitialized is an invariant of BorrowedBuf - buf: unsafe { (slice as *mut [u8]).as_uninit_slice_mut().unwrap() }, + buf: unsafe { &mut *(slice as *mut [u8] as *mut [MaybeUninit]) }, filled: 0, - init: len, + init: true, } } } /// Creates a new `BorrowedBuf` from an uninitialized buffer. -/// -/// Use `set_init` if part of the buffer is known to be already initialized. impl<'data> From<&'data mut [MaybeUninit]> for BorrowedBuf<'data> { #[inline] fn from(buf: &'data mut [MaybeUninit]) -> BorrowedBuf<'data> { - BorrowedBuf { buf, filled: 0, init: 0 } + BorrowedBuf { buf, filled: 0, init: false } } } @@ -74,14 +68,13 @@ impl<'data> From<&'data mut [MaybeUninit]> for BorrowedBuf<'data> { /// Use `BorrowedCursor::with_unfilled_buf` instead for a safer alternative. impl<'data> From> for BorrowedBuf<'data> { #[inline] - fn from(mut buf: BorrowedCursor<'data>) -> BorrowedBuf<'data> { - let init = buf.init_mut().len(); + fn from(buf: BorrowedCursor<'data>) -> BorrowedBuf<'data> { BorrowedBuf { // SAFETY: no initialized byte is ever uninitialized as per // `BorrowedBuf`'s invariant buf: unsafe { buf.buf.buf.get_unchecked_mut(buf.buf.filled..) }, filled: 0, - init, + init: buf.buf.init, } } } @@ -99,9 +92,10 @@ impl<'data> BorrowedBuf<'data> { self.filled } - /// Returns the length of the initialized part of the buffer. + /// Returns `true` if the buffer is initialized. + #[unstable(feature = "borrowed_buf_init", issue = "78485")] #[inline] - pub fn init_len(&self) -> usize { + pub fn is_init(&self) -> bool { self.init } @@ -159,32 +153,29 @@ impl<'data> BorrowedBuf<'data> { /// Clears the buffer, resetting the filled region to empty. /// - /// The number of initialized bytes is not changed, and the contents of the buffer are not modified. + /// The contents of the buffer are not modified. #[inline] pub fn clear(&mut self) -> &mut Self { self.filled = 0; self } - /// Asserts that the first `n` bytes of the buffer are initialized. - /// - /// `BorrowedBuf` assumes that bytes are never de-initialized, so this method does nothing when called with fewer - /// bytes than are already known to be initialized. + /// Asserts that the unfilled part of the buffer is initialized. /// /// # Safety /// - /// The caller must ensure that the first `n` unfilled bytes of the buffer have already been initialized. + /// All the bytes of the buffer must be initialized. + #[unstable(feature = "borrowed_buf_init", issue = "78485")] #[inline] - pub unsafe fn set_init(&mut self, n: usize) -> &mut Self { - self.init = cmp::max(self.init, n); + pub unsafe fn set_init(&mut self) -> &mut Self { + self.init = true; self } } /// A writeable view of the unfilled portion of a [`BorrowedBuf`]. /// -/// The unfilled portion consists of an initialized and an uninitialized part; see [`BorrowedBuf`] -/// for details. +/// The unfilled portion may be uninitialized; see [`BorrowedBuf`] for details. /// /// Data can be written directly to the cursor by using [`append`](BorrowedCursor::append) or /// indirectly by getting a slice of part or all of the cursor and writing into the slice. In the @@ -238,21 +229,29 @@ impl<'a> BorrowedCursor<'a> { self.buf.filled } - /// Returns a mutable reference to the initialized portion of the cursor. + /// Returns `true` if the buffer is initialized. + #[unstable(feature = "borrowed_buf_init", issue = "78485")] #[inline] - pub fn init_mut(&mut self) -> &mut [u8] { - // SAFETY: We only slice the initialized part of the buffer, which is always valid - unsafe { - let buf = self.buf.buf.get_unchecked_mut(self.buf.filled..self.buf.init); - buf.assume_init_mut() - } + pub fn is_init(&self) -> bool { + self.buf.init + } + + /// Set the buffer as fully initialized. + /// + /// # Safety + /// + /// All the bytes of the cursor must be initialized. + #[unstable(feature = "borrowed_buf_init", issue = "78485")] + #[inline] + pub unsafe fn set_init(&mut self) { + self.buf.init = true; } /// Returns a mutable reference to the whole cursor. /// /// # Safety /// - /// The caller must not uninitialize any bytes in the initialized portion of the cursor. + /// The caller must not uninitialize any bytes of the cursor if it is initialized. #[inline] pub unsafe fn as_mut(&mut self) -> &mut [MaybeUninit] { // SAFETY: always in bounds @@ -271,10 +270,12 @@ impl<'a> BorrowedCursor<'a> { /// # Panics /// /// Panics if there are less than `n` bytes initialized. + #[unstable(feature = "borrowed_buf_init", issue = "78485")] #[inline] - pub fn advance(&mut self, n: usize) -> &mut Self { + pub fn advance_checked(&mut self, n: usize) -> &mut Self { // The subtraction cannot underflow by invariant of this type. - assert!(n <= self.buf.init - self.buf.filled); + let init_unfilled = if self.buf.init { self.buf.buf.len() - self.buf.filled } else { 0 }; + assert!(n <= init_unfilled); self.buf.filled += n; self @@ -291,40 +292,29 @@ impl<'a> BorrowedCursor<'a> { /// The caller must ensure that the first `n` bytes of the cursor have been properly /// initialised. #[inline] - pub unsafe fn advance_unchecked(&mut self, n: usize) -> &mut Self { + pub unsafe fn advance(&mut self, n: usize) -> &mut Self { self.buf.filled += n; - self.buf.init = cmp::max(self.buf.init, self.buf.filled); self } - /// Initializes all bytes in the cursor. + /// Initializes all bytes in the cursor and returns them. + #[unstable(feature = "borrowed_buf_init", issue = "78485")] #[inline] - pub fn ensure_init(&mut self) -> &mut Self { + pub fn ensure_init(&mut self) -> &mut [u8] { // SAFETY: always in bounds and we never uninitialize these bytes. - let uninit = unsafe { self.buf.buf.get_unchecked_mut(self.buf.init..) }; - - // SAFETY: 0 is a valid value for MaybeUninit and the length matches the allocation - // since it is comes from a slice reference. - unsafe { - ptr::write_bytes(uninit.as_mut_ptr(), 0, uninit.len()); + let unfilled = unsafe { self.buf.buf.get_unchecked_mut(self.buf.filled..) }; + + if !self.buf.init { + // SAFETY: 0 is a valid value for MaybeUninit and the length matches the allocation + // since it is comes from a slice reference. + unsafe { + ptr::write_bytes(unfilled.as_mut_ptr(), 0, unfilled.len()); + } + self.buf.init = true; } - self.buf.init = self.buf.capacity(); - - self - } - /// Asserts that the first `n` unfilled bytes of the cursor are initialized. - /// - /// `BorrowedBuf` assumes that bytes are never de-initialized, so this method does nothing when - /// called with fewer bytes than are already known to be initialized. - /// - /// # Safety - /// - /// The caller must ensure that the first `n` bytes of the buffer have already been initialized. - #[inline] - pub unsafe fn set_init(&mut self, n: usize) -> &mut Self { - self.buf.init = cmp::max(self.buf.init, self.buf.filled + n); - self + // SAFETY: these bytes have just been initialized if they weren't before + unsafe { unfilled.assume_init_mut() } } /// Appends data to the cursor, advancing position within its buffer. @@ -341,10 +331,6 @@ impl<'a> BorrowedCursor<'a> { self.as_mut()[..buf.len()].write_copy_of_slice(buf); } - // SAFETY: We just added the entire contents of buf to the filled section. - unsafe { - self.set_init(buf.len()); - } self.buf.filled += buf.len(); } @@ -365,7 +351,7 @@ impl<'a> BorrowedCursor<'a> { // Check that the caller didn't replace the `BorrowedBuf`. // This is necessary for the safety of the code below: if the check wasn't // there, one could mark some bytes as initialized even though there aren't. - assert!(core::ptr::addr_eq(prev_ptr, buf.buf)); + assert!(core::ptr::eq(prev_ptr, buf.buf)); let filled = buf.filled; let init = buf.init; @@ -376,7 +362,7 @@ impl<'a> BorrowedCursor<'a> { // SAFETY: These amounts of bytes were initialized/filled in the `BorrowedBuf`, // and therefore they are initialized/filled in the cursor too, because the // buffer wasn't replaced. - self.buf.init = self.buf.filled + init; + self.buf.init = init; self.buf.filled += filled; res diff --git a/core/src/io/cursor.rs b/core/src/io/cursor.rs new file mode 100644 index 0000000000000..ebbec6c5e8210 --- /dev/null +++ b/core/src/io/cursor.rs @@ -0,0 +1,291 @@ +/// A `Cursor` wraps an in-memory buffer and provides it with a +/// [`Seek`] implementation. +/// +/// `Cursor`s are used with in-memory buffers, anything implementing +/// [AsRef]<\[u8]>, to allow them to implement [`Read`] and/or [`Write`], +/// allowing these buffers to be used anywhere you might use a reader or writer +/// that does actual I/O. +/// +/// The standard library implements some I/O traits on various types which +/// are commonly used as a buffer, like Cursor<[Vec]\> and +/// Cursor<[&\[u8\]][bytes]>. +/// +/// # Examples +/// +/// We may want to write bytes to a [`File`] in our production +/// code, but use an in-memory buffer in our tests. We can do this with +/// `Cursor`: +/// +/// [bytes]: crate::slice "slice" +/// [`File`]: ../../std/fs/struct.File.html +/// [`Read`]: ../../std/io/trait.Read.html +/// [`Write`]: ../../std/io/trait.Write.html +/// [`Seek`]: ../../std/io/trait.Seek.html +/// [Vec]: ../../alloc/vec/struct.Vec.html +/// +/// ```no_run +/// use std::io::prelude::*; +/// use std::io::{self, SeekFrom}; +/// use std::fs::File; +/// +/// // a library function we've written +/// fn write_ten_bytes_at_end(mut writer: W) -> io::Result<()> { +/// writer.seek(SeekFrom::End(-10))?; +/// +/// for i in 0..10 { +/// writer.write(&[i])?; +/// } +/// +/// // all went well +/// Ok(()) +/// } +/// +/// # fn foo() -> io::Result<()> { +/// // Here's some code that uses this library function. +/// // +/// // We might want to use a BufReader here for efficiency, but let's +/// // keep this example focused. +/// let mut file = File::create("foo.txt")?; +/// // First, we need to allocate 10 bytes to be able to write into. +/// file.set_len(10)?; +/// +/// write_ten_bytes_at_end(&mut file)?; +/// # Ok(()) +/// # } +/// +/// // now let's write a test +/// #[test] +/// fn test_writes_bytes() { +/// // setting up a real File is much slower than an in-memory buffer, +/// // let's use a cursor instead +/// use std::io::Cursor; +/// let mut buff = Cursor::new(vec![0; 15]); +/// +/// write_ten_bytes_at_end(&mut buff).unwrap(); +/// +/// assert_eq!(&buff.get_ref()[5..15], &[0, 1, 2, 3, 4, 5, 6, 7, 8, 9]); +/// } +/// ``` +#[stable(feature = "rust1", since = "1.0.0")] +#[derive(Debug, Default, Eq, PartialEq)] +pub struct Cursor { + inner: T, + pos: u64, +} + +impl Cursor { + /// Creates a new cursor wrapping the provided underlying in-memory buffer. + /// + /// Cursor initial position is `0` even if underlying buffer (e.g., [`Vec`]) + /// is not empty. So writing to cursor starts with overwriting [`Vec`] + /// content, not with appending to it. + /// + /// [`Vec`]: ../../alloc/vec/struct.Vec.html + /// + /// # Examples + /// + /// ``` + /// use std::io::Cursor; + /// + /// let buff = Cursor::new(Vec::new()); + /// # fn force_inference(_: &Cursor>) {} + /// # force_inference(&buff); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] + pub const fn new(inner: T) -> Cursor { + Cursor { pos: 0, inner } + } + + /// Consumes this cursor, returning the underlying value. + /// + /// # Examples + /// + /// ``` + /// use std::io::Cursor; + /// + /// let buff = Cursor::new(Vec::new()); + /// # fn force_inference(_: &Cursor>) {} + /// # force_inference(&buff); + /// + /// let vec = buff.into_inner(); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + pub fn into_inner(self) -> T { + self.inner + } + + /// Gets a reference to the underlying value in this cursor. + /// + /// # Examples + /// + /// ``` + /// use std::io::Cursor; + /// + /// let buff = Cursor::new(Vec::new()); + /// # fn force_inference(_: &Cursor>) {} + /// # force_inference(&buff); + /// + /// let reference = buff.get_ref(); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] + pub const fn get_ref(&self) -> &T { + &self.inner + } + + /// Gets a mutable reference to the underlying value in this cursor. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying value as it may corrupt this cursor's position. + /// + /// # Examples + /// + /// ``` + /// use std::io::Cursor; + /// + /// let mut buff = Cursor::new(Vec::new()); + /// # fn force_inference(_: &Cursor>) {} + /// # force_inference(&buff); + /// + /// let reference = buff.get_mut(); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_stable(feature = "const_mut_cursor", since = "1.86.0")] + pub const fn get_mut(&mut self) -> &mut T { + &mut self.inner + } + + /// Returns the current position of this cursor. + /// + /// # Examples + /// + /// ``` + /// use std::io::Cursor; + /// use std::io::prelude::*; + /// use std::io::SeekFrom; + /// + /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]); + /// + /// assert_eq!(buff.position(), 0); + /// + /// buff.seek(SeekFrom::Current(2)).unwrap(); + /// assert_eq!(buff.position(), 2); + /// + /// buff.seek(SeekFrom::Current(-1)).unwrap(); + /// assert_eq!(buff.position(), 1); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] + pub const fn position(&self) -> u64 { + self.pos + } + + /// Sets the position of this cursor. + /// + /// # Examples + /// + /// ``` + /// use std::io::Cursor; + /// + /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]); + /// + /// assert_eq!(buff.position(), 0); + /// + /// buff.set_position(2); + /// assert_eq!(buff.position(), 2); + /// + /// buff.set_position(4); + /// assert_eq!(buff.position(), 4); + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_const_stable(feature = "const_mut_cursor", since = "1.86.0")] + pub const fn set_position(&mut self, pos: u64) { + self.pos = pos; + } + + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[inline] + pub const fn into_parts_mut(&mut self) -> (&mut u64, &mut T) { + (&mut self.pos, &mut self.inner) + } +} + +impl Cursor +where + T: AsRef<[u8]>, +{ + /// Splits the underlying slice at the cursor position and returns them. + /// + /// # Examples + /// + /// ``` + /// #![feature(cursor_split)] + /// use std::io::Cursor; + /// + /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]); + /// + /// assert_eq!(buff.split(), ([].as_slice(), [1, 2, 3, 4, 5].as_slice())); + /// + /// buff.set_position(2); + /// assert_eq!(buff.split(), ([1, 2].as_slice(), [3, 4, 5].as_slice())); + /// + /// buff.set_position(6); + /// assert_eq!(buff.split(), ([1, 2, 3, 4, 5].as_slice(), [].as_slice())); + /// ``` + #[unstable(feature = "cursor_split", issue = "86369")] + pub fn split(&self) -> (&[u8], &[u8]) { + let slice = self.inner.as_ref(); + let pos = self.pos.min(slice.len() as u64); + slice.split_at(pos as usize) + } +} + +impl Cursor +where + T: AsMut<[u8]>, +{ + /// Splits the underlying slice at the cursor position and returns them + /// mutably. + /// + /// # Examples + /// + /// ``` + /// #![feature(cursor_split)] + /// use std::io::Cursor; + /// + /// let mut buff = Cursor::new(vec![1, 2, 3, 4, 5]); + /// + /// assert_eq!(buff.split_mut(), ([].as_mut_slice(), [1, 2, 3, 4, 5].as_mut_slice())); + /// + /// buff.set_position(2); + /// assert_eq!(buff.split_mut(), ([1, 2].as_mut_slice(), [3, 4, 5].as_mut_slice())); + /// + /// buff.set_position(6); + /// assert_eq!(buff.split_mut(), ([1, 2, 3, 4, 5].as_mut_slice(), [].as_mut_slice())); + /// ``` + #[unstable(feature = "cursor_split", issue = "86369")] + pub fn split_mut(&mut self) -> (&mut [u8], &mut [u8]) { + let slice = self.inner.as_mut(); + let pos = self.pos.min(slice.len() as u64); + slice.split_at_mut(pos as usize) + } +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Clone for Cursor +where + T: Clone, +{ + #[inline] + fn clone(&self) -> Self { + Cursor { inner: self.inner.clone(), pos: self.pos } + } + + #[inline] + fn clone_from(&mut self, other: &Self) { + self.inner.clone_from(&other.inner); + self.pos = other.pos; + } +} diff --git a/core/src/io/error.rs b/core/src/io/error.rs new file mode 100644 index 0000000000000..67cd1eebf44f2 --- /dev/null +++ b/core/src/io/error.rs @@ -0,0 +1,401 @@ +#![unstable(feature = "core_io", issue = "154046")] + +use crate::fmt; + +/// The type of raw OS error codes. +/// +/// This is an [`i32`] on all currently supported platforms, but platforms +/// added in the future (such as UEFI) may use a different primitive type like +/// [`usize`]. Use `as` or [`into`] conversions where applicable to ensure maximum +/// portability. +/// +/// [`into`]: Into::into +#[unstable(feature = "raw_os_error_ty", issue = "107792")] +pub type RawOsError = cfg_select! { + target_os = "uefi" => usize, + _ => i32, +}; + +/// A list specifying general categories of I/O error. +/// +/// This list is intended to grow over time and it is not recommended to +/// exhaustively match against it. +/// +/// It is used with the [`io::Error`][error] type. +/// +/// [error]: ../../std/io/struct.Error.html +/// +/// # Handling errors and matching on `ErrorKind` +/// +/// In application code, use `match` for the `ErrorKind` values you are +/// expecting; use `_` to match "all other errors". +/// +/// In comprehensive and thorough tests that want to verify that a test doesn't +/// return any known incorrect error kind, you may want to cut-and-paste the +/// current full list of errors from here into your test code, and then match +/// `_` as the correct case. This seems counterintuitive, but it will make your +/// tests more robust. In particular, if you want to verify that your code does +/// produce an unrecognized error kind, the robust solution is to check for all +/// the recognized error kinds and fail in those cases. +#[derive(Clone, Copy, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)] +#[stable(feature = "rust1", since = "1.0.0")] +#[cfg_attr(not(test), rustc_diagnostic_item = "io_errorkind")] +#[allow(deprecated)] +#[non_exhaustive] +pub enum ErrorKind { + /// An entity was not found, often a file. + #[stable(feature = "rust1", since = "1.0.0")] + NotFound, + /// The operation lacked the necessary privileges to complete. + #[stable(feature = "rust1", since = "1.0.0")] + PermissionDenied, + /// The connection was refused by the remote server. + #[stable(feature = "rust1", since = "1.0.0")] + ConnectionRefused, + /// The connection was reset by the remote server. + #[stable(feature = "rust1", since = "1.0.0")] + ConnectionReset, + /// The remote host is not reachable. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + HostUnreachable, + /// The network containing the remote host is not reachable. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + NetworkUnreachable, + /// The connection was aborted (terminated) by the remote server. + #[stable(feature = "rust1", since = "1.0.0")] + ConnectionAborted, + /// The network operation failed because it was not connected yet. + #[stable(feature = "rust1", since = "1.0.0")] + NotConnected, + /// A socket address could not be bound because the address is already in + /// use elsewhere. + #[stable(feature = "rust1", since = "1.0.0")] + AddrInUse, + /// A nonexistent interface was requested or the requested address was not + /// local. + #[stable(feature = "rust1", since = "1.0.0")] + AddrNotAvailable, + /// The system's networking is down. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + NetworkDown, + /// The operation failed because a pipe was closed. + #[stable(feature = "rust1", since = "1.0.0")] + BrokenPipe, + /// An entity already exists, often a file. + #[stable(feature = "rust1", since = "1.0.0")] + AlreadyExists, + /// The operation needs to block to complete, but the blocking operation was + /// requested to not occur. + #[stable(feature = "rust1", since = "1.0.0")] + WouldBlock, + /// A filesystem object is, unexpectedly, not a directory. + /// + /// For example, a filesystem path was specified where one of the intermediate directory + /// components was, in fact, a plain file. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + NotADirectory, + /// The filesystem object is, unexpectedly, a directory. + /// + /// A directory was specified when a non-directory was expected. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + IsADirectory, + /// A non-empty directory was specified where an empty directory was expected. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + DirectoryNotEmpty, + /// The filesystem or storage medium is read-only, but a write operation was attempted. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + ReadOnlyFilesystem, + /// Loop in the filesystem or IO subsystem; often, too many levels of symbolic links. + /// + /// There was a loop (or excessively long chain) resolving a filesystem object + /// or file IO object. + /// + /// On Unix this is usually the result of a symbolic link loop; or, of exceeding the + /// system-specific limit on the depth of symlink traversal. + #[unstable(feature = "io_error_more", issue = "86442")] + FilesystemLoop, + /// Stale network file handle. + /// + /// With some network filesystems, notably NFS, an open file (or directory) can be invalidated + /// by problems with the network or server. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + StaleNetworkFileHandle, + /// A parameter was incorrect. + #[stable(feature = "rust1", since = "1.0.0")] + InvalidInput, + /// Data not valid for the operation were encountered. + /// + /// Unlike [`InvalidInput`], this typically means that the operation + /// parameters were valid, however the error was caused by malformed + /// input data. + /// + /// For example, a function that reads a file into a string will error with + /// `InvalidData` if the file's contents are not valid UTF-8. + /// + /// [`InvalidInput`]: ErrorKind::InvalidInput + #[stable(feature = "io_invalid_data", since = "1.2.0")] + InvalidData, + /// The I/O operation's timeout expired, causing it to be canceled. + #[stable(feature = "rust1", since = "1.0.0")] + TimedOut, + /// An error returned when an operation could not be completed because a + /// call to [`write`][write] returned [`Ok(0)`]. + /// + /// This typically means that an operation could only succeed if it wrote a + /// particular number of bytes but only a smaller number of bytes could be + /// written. + /// + /// [write]: ../../std/io/trait.Write.html#tymethod.write + /// [`Ok(0)`]: Ok + #[stable(feature = "rust1", since = "1.0.0")] + WriteZero, + /// The underlying storage (typically, a filesystem) is full. + /// + /// This does not include out of quota errors. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + StorageFull, + /// Seek on unseekable file. + /// + /// Seeking was attempted on an open file handle which is not suitable for seeking - for + /// example, on Unix, a named pipe opened with `File::open`. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + NotSeekable, + /// Filesystem quota or some other kind of quota was exceeded. + #[stable(feature = "io_error_quota_exceeded", since = "1.85.0")] + QuotaExceeded, + /// File larger than allowed or supported. + /// + /// This might arise from a hard limit of the underlying filesystem or file access API, or from + /// an administratively imposed resource limitation. Simple disk full, and out of quota, have + /// their own errors. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + FileTooLarge, + /// Resource is busy. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + ResourceBusy, + /// Executable file is busy. + /// + /// An attempt was made to write to a file which is also in use as a running program. (Not all + /// operating systems detect this situation.) + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + ExecutableFileBusy, + /// Deadlock (avoided). + /// + /// A file locking operation would result in deadlock. This situation is typically detected, if + /// at all, on a best-effort basis. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + Deadlock, + /// Cross-device or cross-filesystem (hard) link or rename. + #[stable(feature = "io_error_crosses_devices", since = "1.85.0")] + CrossesDevices, + /// Too many (hard) links to the same filesystem object. + /// + /// The filesystem does not support making so many hardlinks to the same file. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + TooManyLinks, + /// A filename was invalid. + /// + /// This error can also occur if a length limit for a name was exceeded. + #[stable(feature = "io_error_invalid_filename", since = "1.87.0")] + InvalidFilename, + /// Program argument list too long. + /// + /// When trying to run an external program, a system or process limit on the size of the + /// arguments would have been exceeded. + #[stable(feature = "io_error_a_bit_more", since = "1.83.0")] + ArgumentListTooLong, + /// This operation was interrupted. + /// + /// Interrupted operations can typically be retried. + #[stable(feature = "rust1", since = "1.0.0")] + Interrupted, + + /// This operation is unsupported on this platform. + /// + /// This means that the operation can never succeed. + #[stable(feature = "unsupported_error", since = "1.53.0")] + Unsupported, + + // ErrorKinds which are primarily categorisations for OS error + // codes should be added above. + // + /// An error returned when an operation could not be completed because an + /// "end of file" was reached prematurely. + /// + /// This typically means that an operation could only succeed if it read a + /// particular number of bytes but only a smaller number of bytes could be + /// read. + #[stable(feature = "read_exact", since = "1.6.0")] + UnexpectedEof, + + /// An operation could not be completed, because it failed + /// to allocate enough memory. + #[stable(feature = "out_of_memory_error", since = "1.54.0")] + OutOfMemory, + + /// The operation was partially successful and needs to be checked + /// later on due to not blocking. + #[unstable(feature = "io_error_inprogress", issue = "130840")] + InProgress, + + // "Unusual" error kinds which do not correspond simply to (sets + // of) OS error codes, should be added just above this comment. + // `Other` and `Uncategorized` should remain at the end: + // + /// A custom error that does not fall under any other I/O error kind. + /// + /// This can be used to construct your own [`Error`][error]s that do not match any + /// [`ErrorKind`]. + /// + /// This [`ErrorKind`] is not used by the standard library. + /// + /// Errors from the standard library that do not fall under any of the I/O + /// error kinds cannot be `match`ed on, and will only match a wildcard (`_`) pattern. + /// New [`ErrorKind`]s might be added in the future for some of those. + /// + /// [error]: ../../std/io/struct.Error.html + #[stable(feature = "rust1", since = "1.0.0")] + Other, + + /// Any I/O error from the standard library that's not part of this list. + /// + /// Errors that are `Uncategorized` now may move to a different or a new + /// [`ErrorKind`] variant in the future. It is not recommended to match + /// an error against `Uncategorized`; use a wildcard match (`_`) instead. + #[unstable(feature = "io_error_uncategorized", issue = "none")] + #[doc(hidden)] + Uncategorized, +} + +impl ErrorKind { + pub(crate) const fn as_str(&self) -> &'static str { + use ErrorKind::*; + match *self { + // tidy-alphabetical-start + AddrInUse => "address in use", + AddrNotAvailable => "address not available", + AlreadyExists => "entity already exists", + ArgumentListTooLong => "argument list too long", + BrokenPipe => "broken pipe", + ConnectionAborted => "connection aborted", + ConnectionRefused => "connection refused", + ConnectionReset => "connection reset", + CrossesDevices => "cross-device link or rename", + Deadlock => "deadlock", + DirectoryNotEmpty => "directory not empty", + ExecutableFileBusy => "executable file busy", + FileTooLarge => "file too large", + FilesystemLoop => "filesystem loop or indirection limit (e.g. symlink loop)", + HostUnreachable => "host unreachable", + InProgress => "in progress", + Interrupted => "operation interrupted", + InvalidData => "invalid data", + InvalidFilename => "invalid filename", + InvalidInput => "invalid input parameter", + IsADirectory => "is a directory", + NetworkDown => "network down", + NetworkUnreachable => "network unreachable", + NotADirectory => "not a directory", + NotConnected => "not connected", + NotFound => "entity not found", + NotSeekable => "seek on unseekable file", + Other => "other error", + OutOfMemory => "out of memory", + PermissionDenied => "permission denied", + QuotaExceeded => "quota exceeded", + ReadOnlyFilesystem => "read-only filesystem or storage medium", + ResourceBusy => "resource busy", + StaleNetworkFileHandle => "stale network file handle", + StorageFull => "no storage space", + TimedOut => "timed out", + TooManyLinks => "too many links", + Uncategorized => "uncategorized error", + UnexpectedEof => "unexpected end of file", + Unsupported => "unsupported", + WouldBlock => "operation would block", + WriteZero => "write zero", + // tidy-alphabetical-end + } + } + + // This compiles to the same code as the check+transmute, but doesn't require + // unsafe, or to hard-code max ErrorKind or its size in a way the compiler + // couldn't verify. + #[inline] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + #[doc(hidden)] + pub const fn from_prim(ek: u32) -> Option { + macro_rules! from_prim { + ($prim:expr => $Enum:ident { $($Variant:ident),* $(,)? }) => {{ + // Force a compile error if the list gets out of date. + const _: fn(e: $Enum) = |e: $Enum| match e { + $($Enum::$Variant => (),)* + }; + match $prim { + $(v if v == ($Enum::$Variant as _) => Some($Enum::$Variant),)* + _ => None, + } + }} + } + from_prim!(ek => ErrorKind { + NotFound, + PermissionDenied, + ConnectionRefused, + ConnectionReset, + HostUnreachable, + NetworkUnreachable, + ConnectionAborted, + NotConnected, + AddrInUse, + AddrNotAvailable, + NetworkDown, + BrokenPipe, + AlreadyExists, + WouldBlock, + NotADirectory, + IsADirectory, + DirectoryNotEmpty, + ReadOnlyFilesystem, + FilesystemLoop, + StaleNetworkFileHandle, + InvalidInput, + InvalidData, + TimedOut, + WriteZero, + StorageFull, + NotSeekable, + QuotaExceeded, + FileTooLarge, + ResourceBusy, + ExecutableFileBusy, + Deadlock, + CrossesDevices, + TooManyLinks, + InvalidFilename, + ArgumentListTooLong, + Interrupted, + Other, + UnexpectedEof, + Unsupported, + OutOfMemory, + InProgress, + Uncategorized, + }) + } +} + +#[stable(feature = "io_errorkind_display", since = "1.60.0")] +impl fmt::Display for ErrorKind { + /// Shows a human-readable description of the [`ErrorKind`]. + /// + /// This is similar to `impl Display for Error`, but doesn't require first converting to Error. + /// + /// # Examples + /// ``` + /// use core::io::ErrorKind; + /// assert_eq!("entity not found", ErrorKind::NotFound.to_string()); + /// ``` + fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt.write_str(self.as_str()) + } +} diff --git a/core/src/io/io_slice.rs b/core/src/io/io_slice.rs new file mode 100644 index 0000000000000..0bdd410d3e964 --- /dev/null +++ b/core/src/io/io_slice.rs @@ -0,0 +1,339 @@ +use crate::fmt; +use crate::mem::take; +use crate::ops::{Deref, DerefMut}; + +cfg_select! { + any(target_family = "unix", target_os = "hermit", target_os = "solid_asp3", target_os = "trusty", target_os = "wasi") => { + #[path = "io_slice/repr_iovec.rs"] + mod repr; + } + target_os = "windows" => { + #[path = "io_slice/repr_windows.rs"] + mod repr; + } + target_os = "uefi" => { + #[path = "io_slice/repr_uefi.rs"] + mod repr; + } + _ => { + #[path = "io_slice/repr_generic.rs"] + mod repr; + } +} + +/// A buffer type used with `Read::read_vectored`. +/// +/// It is semantically a wrapper around a `&mut [u8]`, but is guaranteed to be +/// ABI compatible with the `iovec` type on Unix platforms and `WSABUF` on +/// Windows. +#[stable(feature = "iovec", since = "1.36.0")] +#[repr(transparent)] +pub struct IoSliceMut<'a>(repr::IoSliceMut<'a>); + +#[stable(feature = "iovec_send_sync", since = "1.44.0")] +unsafe impl<'a> Send for IoSliceMut<'a> {} + +#[stable(feature = "iovec_send_sync", since = "1.44.0")] +unsafe impl<'a> Sync for IoSliceMut<'a> {} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> fmt::Debug for IoSliceMut<'a> { + fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Debug::fmt(self.0.as_slice(), fmt) + } +} + +impl<'a> IoSliceMut<'a> { + /// Creates a new `IoSliceMut` wrapping a byte slice. + /// + /// # Panics + /// + /// Panics on Windows if the slice is larger than 4GB. + #[stable(feature = "iovec", since = "1.36.0")] + #[inline] + pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + IoSliceMut(repr::IoSliceMut::new(buf)) + } + + /// Advance the internal cursor of the slice. + /// + /// Also see [`IoSliceMut::advance_slices`] to advance the cursors of + /// multiple buffers. + /// + /// # Panics + /// + /// Panics when trying to advance beyond the end of the slice. + /// + /// # Examples + /// + /// ``` + /// use std::io::IoSliceMut; + /// use std::ops::Deref; + /// + /// let mut data = [1; 8]; + /// let mut buf = IoSliceMut::new(&mut data); + /// + /// // Mark 3 bytes as read. + /// buf.advance(3); + /// assert_eq!(buf.deref(), [1; 5].as_ref()); + /// ``` + #[stable(feature = "io_slice_advance", since = "1.81.0")] + #[inline] + pub fn advance(&mut self, n: usize) { + self.0.advance(n) + } + + /// Advance a slice of slices. + /// + /// Shrinks the slice to remove any `IoSliceMut`s that are fully advanced over. + /// If the cursor ends up in the middle of an `IoSliceMut`, it is modified + /// to start at that cursor. + /// + /// For example, if we have a slice of two 8-byte `IoSliceMut`s, and we advance by 10 bytes, + /// the result will only include the second `IoSliceMut`, advanced by 2 bytes. + /// + /// # Panics + /// + /// Panics when trying to advance beyond the end of the slices. + /// + /// # Examples + /// + /// ``` + /// use std::io::IoSliceMut; + /// use std::ops::Deref; + /// + /// let mut buf1 = [1; 8]; + /// let mut buf2 = [2; 16]; + /// let mut buf3 = [3; 8]; + /// let mut bufs = &mut [ + /// IoSliceMut::new(&mut buf1), + /// IoSliceMut::new(&mut buf2), + /// IoSliceMut::new(&mut buf3), + /// ][..]; + /// + /// // Mark 10 bytes as read. + /// IoSliceMut::advance_slices(&mut bufs, 10); + /// assert_eq!(bufs[0].deref(), [2; 14].as_ref()); + /// assert_eq!(bufs[1].deref(), [3; 8].as_ref()); + /// ``` + #[stable(feature = "io_slice_advance", since = "1.81.0")] + #[inline] + pub fn advance_slices(bufs: &mut &mut [IoSliceMut<'a>], n: usize) { + // Number of buffers to remove. + let mut remove = 0; + // Remaining length before reaching n. + let mut left = n; + for buf in bufs.iter() { + if let Some(remainder) = left.checked_sub(buf.len()) { + left = remainder; + remove += 1; + } else { + break; + } + } + + *bufs = &mut take(bufs)[remove..]; + if bufs.is_empty() { + assert!(left == 0, "advancing io slices beyond their length"); + } else { + bufs[0].advance(left); + } + } + + /// Get the underlying bytes as a mutable slice with the original lifetime. + /// + /// # Examples + /// + /// ``` + /// #![feature(io_slice_as_bytes)] + /// use std::io::IoSliceMut; + /// + /// let mut data = *b"abcdef"; + /// let io_slice = IoSliceMut::new(&mut data); + /// io_slice.into_slice()[0] = b'A'; + /// + /// assert_eq!(&data, b"Abcdef"); + /// ``` + #[unstable(feature = "io_slice_as_bytes", issue = "132818")] + pub const fn into_slice(self) -> &'a mut [u8] { + self.0.into_slice() + } +} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> Deref for IoSliceMut<'a> { + type Target = [u8]; + + #[inline] + fn deref(&self) -> &[u8] { + self.0.as_slice() + } +} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> DerefMut for IoSliceMut<'a> { + #[inline] + fn deref_mut(&mut self) -> &mut [u8] { + self.0.as_mut_slice() + } +} + +/// A buffer type used with `Write::write_vectored`. +/// +/// It is semantically a wrapper around a `&[u8]`, but is guaranteed to be +/// ABI compatible with the `iovec` type on Unix platforms and `WSABUF` on +/// Windows. +#[stable(feature = "iovec", since = "1.36.0")] +#[derive(Copy, Clone)] +#[repr(transparent)] +pub struct IoSlice<'a>(repr::IoSlice<'a>); + +#[stable(feature = "iovec_send_sync", since = "1.44.0")] +unsafe impl<'a> Send for IoSlice<'a> {} + +#[stable(feature = "iovec_send_sync", since = "1.44.0")] +unsafe impl<'a> Sync for IoSlice<'a> {} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> fmt::Debug for IoSlice<'a> { + fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Debug::fmt(self.0.as_slice(), fmt) + } +} + +impl<'a> IoSlice<'a> { + /// Creates a new `IoSlice` wrapping a byte slice. + /// + /// # Panics + /// + /// Panics on Windows if the slice is larger than 4GB. + #[stable(feature = "iovec", since = "1.36.0")] + #[must_use] + #[inline] + pub fn new(buf: &'a [u8]) -> IoSlice<'a> { + IoSlice(repr::IoSlice::new(buf)) + } + + /// Advance the internal cursor of the slice. + /// + /// Also see [`IoSlice::advance_slices`] to advance the cursors of multiple + /// buffers. + /// + /// # Panics + /// + /// Panics when trying to advance beyond the end of the slice. + /// + /// # Examples + /// + /// ``` + /// use std::io::IoSlice; + /// use std::ops::Deref; + /// + /// let data = [1; 8]; + /// let mut buf = IoSlice::new(&data); + /// + /// // Mark 3 bytes as read. + /// buf.advance(3); + /// assert_eq!(buf.deref(), [1; 5].as_ref()); + /// ``` + #[stable(feature = "io_slice_advance", since = "1.81.0")] + #[inline] + pub fn advance(&mut self, n: usize) { + self.0.advance(n) + } + + /// Advance a slice of slices. + /// + /// Shrinks the slice to remove any `IoSlice`s that are fully advanced over. + /// If the cursor ends up in the middle of an `IoSlice`, it is modified + /// to start at that cursor. + /// + /// For example, if we have a slice of two 8-byte `IoSlice`s, and we advance by 10 bytes, + /// the result will only include the second `IoSlice`, advanced by 2 bytes. + /// + /// # Panics + /// + /// Panics when trying to advance beyond the end of the slices. + /// + /// # Examples + /// + /// ``` + /// use std::io::IoSlice; + /// use std::ops::Deref; + /// + /// let buf1 = [1; 8]; + /// let buf2 = [2; 16]; + /// let buf3 = [3; 8]; + /// let mut bufs = &mut [ + /// IoSlice::new(&buf1), + /// IoSlice::new(&buf2), + /// IoSlice::new(&buf3), + /// ][..]; + /// + /// // Mark 10 bytes as written. + /// IoSlice::advance_slices(&mut bufs, 10); + /// assert_eq!(bufs[0].deref(), [2; 14].as_ref()); + /// assert_eq!(bufs[1].deref(), [3; 8].as_ref()); + #[stable(feature = "io_slice_advance", since = "1.81.0")] + #[inline] + pub fn advance_slices(bufs: &mut &mut [IoSlice<'a>], n: usize) { + // Number of buffers to remove. + let mut remove = 0; + // Remaining length before reaching n. This prevents overflow + // that could happen if the length of slices in `bufs` were instead + // accumulated. Those slice may be aliased and, if they are large + // enough, their added length may overflow a `usize`. + let mut left = n; + for buf in bufs.iter() { + if let Some(remainder) = left.checked_sub(buf.len()) { + left = remainder; + remove += 1; + } else { + break; + } + } + + *bufs = &mut take(bufs)[remove..]; + if bufs.is_empty() { + assert!(left == 0, "advancing io slices beyond their length"); + } else { + bufs[0].advance(left); + } + } + + /// Get the underlying bytes as a slice with the original lifetime. + /// + /// This doesn't borrow from `self`, so is less restrictive than calling + /// `.deref()`, which does. + /// + /// # Examples + /// + /// ``` + /// #![feature(io_slice_as_bytes)] + /// use std::io::IoSlice; + /// + /// let data = b"abcdef"; + /// + /// let mut io_slice = IoSlice::new(data); + /// let tail = &io_slice.as_slice()[3..]; + /// + /// // This works because `tail` doesn't borrow `io_slice` + /// io_slice = IoSlice::new(tail); + /// + /// assert_eq!(io_slice.as_slice(), b"def"); + /// ``` + #[unstable(feature = "io_slice_as_bytes", issue = "132818")] + pub const fn as_slice(self) -> &'a [u8] { + self.0.as_slice() + } +} + +#[stable(feature = "iovec", since = "1.36.0")] +impl<'a> Deref for IoSlice<'a> { + type Target = [u8]; + + #[inline] + fn deref(&self) -> &[u8] { + self.0.as_slice() + } +} diff --git a/std/src/sys/io/io_slice/unsupported.rs b/core/src/io/io_slice/repr_generic.rs similarity index 50% rename from std/src/sys/io/io_slice/unsupported.rs rename to core/src/io/io_slice/repr_generic.rs index 1572cac6cd771..fdeb4978aedea 100644 --- a/std/src/sys/io/io_slice/unsupported.rs +++ b/core/src/io/io_slice/repr_generic.rs @@ -1,52 +1,52 @@ use crate::mem; #[derive(Copy, Clone)] -pub struct IoSlice<'a>(&'a [u8]); +pub(crate) struct IoSlice<'a>(&'a [u8]); impl<'a> IoSlice<'a> { #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { + pub(crate) fn new(buf: &'a [u8]) -> IoSlice<'a> { IoSlice(buf) } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { self.0 = &self.0[n..] } #[inline] - pub const fn as_slice(&self) -> &'a [u8] { + pub(crate) const fn as_slice(&self) -> &'a [u8] { self.0 } } -pub struct IoSliceMut<'a>(&'a mut [u8]); +pub(crate) struct IoSliceMut<'a>(&'a mut [u8]); impl<'a> IoSliceMut<'a> { #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + pub(crate) fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { IoSliceMut(buf) } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { let slice = mem::take(&mut self.0); let (_, remaining) = slice.split_at_mut(n); self.0 = remaining; } #[inline] - pub fn as_slice(&self) -> &[u8] { + pub(crate) fn as_slice(&self) -> &[u8] { self.0 } #[inline] - pub const fn into_slice(self) -> &'a mut [u8] { + pub(crate) const fn into_slice(self) -> &'a mut [u8] { self.0 } #[inline] - pub fn as_mut_slice(&mut self) -> &mut [u8] { + pub(crate) fn as_mut_slice(&mut self) -> &mut [u8] { self.0 } } diff --git a/std/src/sys/io/io_slice/iovec.rs b/core/src/io/io_slice/repr_iovec.rs similarity index 54% rename from std/src/sys/io/io_slice/iovec.rs rename to core/src/io/io_slice/repr_iovec.rs index d549aca250d5f..cd8f5d539ecce 100644 --- a/std/src/sys/io/io_slice/iovec.rs +++ b/core/src/io/io_slice/repr_iovec.rs @@ -1,24 +1,24 @@ -#[cfg(target_os = "hermit")] -use hermit_abi::iovec; -#[cfg(any(target_family = "unix", target_os = "trusty", target_os = "wasi"))] -use libc::iovec; - use crate::ffi::c_void; use crate::marker::PhantomData; use crate::slice; -#[cfg(target_os = "solid_asp3")] -use crate::sys::pal::abi::sockets::iovec; + +#[derive(Copy, Clone)] +#[repr(C)] +struct iovec { + iov_base: *mut c_void, + iov_len: usize, +} #[derive(Copy, Clone)] #[repr(transparent)] -pub struct IoSlice<'a> { +pub(crate) struct IoSlice<'a> { vec: iovec, _p: PhantomData<&'a [u8]>, } impl<'a> IoSlice<'a> { #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { + pub(crate) fn new(buf: &'a [u8]) -> IoSlice<'a> { IoSlice { vec: iovec { iov_base: buf.as_ptr() as *mut u8 as *mut c_void, iov_len: buf.len() }, _p: PhantomData, @@ -26,11 +26,14 @@ impl<'a> IoSlice<'a> { } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { if self.vec.iov_len < n { panic!("advancing IoSlice beyond its length"); } + // SAFETY: + // * `n <= iov_len` as asserted above. + // * The allocation pointed to by `iov_base` is valid up to `iov_base + iov_len`. unsafe { self.vec.iov_len -= n; self.vec.iov_base = self.vec.iov_base.add(n); @@ -38,20 +41,22 @@ impl<'a> IoSlice<'a> { } #[inline] - pub const fn as_slice(&self) -> &'a [u8] { + pub(crate) const fn as_slice(&self) -> &'a [u8] { + // SAFETY: + // * `iov_base` and `iov_len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts(self.vec.iov_base as *mut u8, self.vec.iov_len) } } } #[repr(transparent)] -pub struct IoSliceMut<'a> { +pub(crate) struct IoSliceMut<'a> { vec: iovec, _p: PhantomData<&'a mut [u8]>, } impl<'a> IoSliceMut<'a> { #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + pub(crate) fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { IoSliceMut { vec: iovec { iov_base: buf.as_mut_ptr() as *mut c_void, iov_len: buf.len() }, _p: PhantomData, @@ -59,11 +64,14 @@ impl<'a> IoSliceMut<'a> { } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { if self.vec.iov_len < n { panic!("advancing IoSliceMut beyond its length"); } + // SAFETY: + // * `n <= iov_len` as asserted above. + // * The allocation pointed to by `iov_base` is valid up to `iov_base + iov_len`. unsafe { self.vec.iov_len -= n; self.vec.iov_base = self.vec.iov_base.add(n); @@ -71,17 +79,23 @@ impl<'a> IoSliceMut<'a> { } #[inline] - pub fn as_slice(&self) -> &[u8] { + pub(crate) fn as_slice(&self) -> &[u8] { + // SAFETY: + // * `iov_base` and `iov_len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts(self.vec.iov_base as *mut u8, self.vec.iov_len) } } #[inline] - pub const fn into_slice(self) -> &'a mut [u8] { + pub(crate) const fn into_slice(self) -> &'a mut [u8] { + // SAFETY: + // * `iov_base` and `iov_len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts_mut(self.vec.iov_base as *mut u8, self.vec.iov_len) } } #[inline] - pub fn as_mut_slice(&mut self) -> &mut [u8] { + pub(crate) fn as_mut_slice(&mut self) -> &mut [u8] { + // SAFETY: + // * `iov_base` and `iov_len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts_mut(self.vec.iov_base as *mut u8, self.vec.iov_len) } } } diff --git a/std/src/sys/io/io_slice/uefi.rs b/core/src/io/io_slice/repr_uefi.rs similarity index 56% rename from std/src/sys/io/io_slice/uefi.rs rename to core/src/io/io_slice/repr_uefi.rs index 909cfbea0b7ba..3698eea733837 100644 --- a/std/src/sys/io/io_slice/uefi.rs +++ b/core/src/io/io_slice/repr_uefi.rs @@ -6,7 +6,7 @@ use crate::slice; #[derive(Copy, Clone)] #[repr(C)] -pub struct IoSlice<'a> { +pub(crate) struct IoSlice<'a> { len: u32, data: *const u8, _p: PhantomData<&'a [u8]>, @@ -14,28 +14,34 @@ pub struct IoSlice<'a> { impl<'a> IoSlice<'a> { #[inline] - pub fn new(buf: &'a [u8]) -> IoSlice<'a> { + pub(crate) fn new(buf: &'a [u8]) -> IoSlice<'a> { let len = buf.len().try_into().unwrap(); Self { len, data: buf.as_ptr(), _p: PhantomData } } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { self.len = u32::try_from(n) .ok() .and_then(|n| self.len.checked_sub(n)) .expect("advancing IoSlice beyond its length"); + + // SAFETY: + // * `n <= len` as asserted above. + // * The allocation pointed to by `data` is valid up to `data + len`. unsafe { self.data = self.data.add(n) }; } #[inline] - pub const fn as_slice(&self) -> &'a [u8] { + pub(crate) const fn as_slice(&self) -> &'a [u8] { + // SAFETY: + // * `data` and `len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts(self.data, self.len as usize) } } } #[repr(C)] -pub struct IoSliceMut<'a> { +pub(crate) struct IoSliceMut<'a> { len: u32, data: *mut u8, _p: PhantomData<&'a mut [u8]>, @@ -43,32 +49,42 @@ pub struct IoSliceMut<'a> { impl<'a> IoSliceMut<'a> { #[inline] - pub fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + pub(crate) fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { let len = buf.len().try_into().unwrap(); Self { len, data: buf.as_mut_ptr(), _p: PhantomData } } #[inline] - pub fn advance(&mut self, n: usize) { + pub(crate) fn advance(&mut self, n: usize) { self.len = u32::try_from(n) .ok() .and_then(|n| self.len.checked_sub(n)) .expect("advancing IoSlice beyond its length"); + + // SAFETY: + // * `n <= len` as asserted above. + // * The allocation pointed to by `data` is valid up to `data + len`. unsafe { self.data = self.data.add(n) }; } #[inline] - pub fn as_slice(&self) -> &[u8] { + pub(crate) fn as_slice(&self) -> &[u8] { + // SAFETY: + // * `data` and `len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts(self.data, self.len as usize) } } #[inline] - pub const fn into_slice(self) -> &'a mut [u8] { + pub(crate) const fn into_slice(self) -> &'a mut [u8] { + // SAFETY: + // * `data` and `len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts_mut(self.data, self.len as usize) } } #[inline] - pub fn as_mut_slice(&mut self) -> &mut [u8] { + pub(crate) fn as_mut_slice(&mut self) -> &mut [u8] { + // SAFETY: + // * `data` and `len` come from a prior decomposition of a valid slice. unsafe { slice::from_raw_parts_mut(self.data, self.len as usize) } } } diff --git a/core/src/io/io_slice/repr_windows.rs b/core/src/io/io_slice/repr_windows.rs new file mode 100644 index 0000000000000..6162d86de8e59 --- /dev/null +++ b/core/src/io/io_slice/repr_windows.rs @@ -0,0 +1,99 @@ +use crate::marker::PhantomData; +use crate::slice; + +#[repr(C)] +#[derive(Clone, Copy)] +struct WSABUF { + len: u32, + buf: *mut u8, +} + +#[derive(Copy, Clone)] +#[repr(transparent)] +pub(crate) struct IoSlice<'a> { + vec: WSABUF, + _p: PhantomData<&'a [u8]>, +} + +impl<'a> IoSlice<'a> { + #[inline] + pub(crate) fn new(buf: &'a [u8]) -> IoSlice<'a> { + assert!(buf.len() <= u32::MAX as usize); + IoSlice { + vec: WSABUF { len: buf.len() as u32, buf: buf.as_ptr() as *mut u8 }, + _p: PhantomData, + } + } + + #[inline] + pub(crate) fn advance(&mut self, n: usize) { + if (self.vec.len as usize) < n { + panic!("advancing IoSlice beyond its length"); + } + + // SAFETY: + // * `n <= len` as asserted above. + // * The allocation pointed to by `buf` is valid up to `buf + len`. + unsafe { + self.vec.len -= n as u32; + self.vec.buf = self.vec.buf.add(n); + } + } + + #[inline] + pub(crate) const fn as_slice(&self) -> &'a [u8] { + // SAFETY: + // * `buf` and `len` come from a prior decomposition of a valid slice. + unsafe { slice::from_raw_parts(self.vec.buf, self.vec.len as usize) } + } +} + +#[repr(transparent)] +pub(crate) struct IoSliceMut<'a> { + vec: WSABUF, + _p: PhantomData<&'a mut [u8]>, +} + +impl<'a> IoSliceMut<'a> { + #[inline] + pub(crate) fn new(buf: &'a mut [u8]) -> IoSliceMut<'a> { + assert!(buf.len() <= u32::MAX as usize); + IoSliceMut { vec: WSABUF { len: buf.len() as u32, buf: buf.as_mut_ptr() }, _p: PhantomData } + } + + #[inline] + pub(crate) fn advance(&mut self, n: usize) { + if (self.vec.len as usize) < n { + panic!("advancing IoSliceMut beyond its length"); + } + + // SAFETY: + // * `n <= len` as asserted above. + // * The allocation pointed to by `buf` is valid up to `buf + len`. + unsafe { + self.vec.len -= n as u32; + self.vec.buf = self.vec.buf.add(n); + } + } + + #[inline] + pub(crate) fn as_slice(&self) -> &[u8] { + // SAFETY: + // * `buf` and `len` come from a prior decomposition of a valid slice. + unsafe { slice::from_raw_parts(self.vec.buf, self.vec.len as usize) } + } + + #[inline] + pub(crate) const fn into_slice(self) -> &'a mut [u8] { + // SAFETY: + // * `buf` and `len` come from a prior decomposition of a valid slice. + unsafe { slice::from_raw_parts_mut(self.vec.buf, self.vec.len as usize) } + } + + #[inline] + pub(crate) fn as_mut_slice(&mut self) -> &mut [u8] { + // SAFETY: + // * `buf` and `len` come from a prior decomposition of a valid slice. + unsafe { slice::from_raw_parts_mut(self.vec.buf, self.vec.len as usize) } + } +} diff --git a/core/src/io/mod.rs b/core/src/io/mod.rs index 2f20180cdc9a2..43b6e09bfc4f0 100644 --- a/core/src/io/mod.rs +++ b/core/src/io/mod.rs @@ -1,6 +1,23 @@ //! Traits, helpers, and type definitions for core I/O functionality. mod borrowed_buf; +mod cursor; +mod error; +mod io_slice; +mod util; #[unstable(feature = "core_io_borrowed_buf", issue = "117693")] pub use self::borrowed_buf::{BorrowedBuf, BorrowedCursor}; +#[unstable(feature = "core_io", issue = "154046")] +pub use self::cursor::Cursor; +#[unstable(feature = "core_io", issue = "154046")] +pub use self::error::ErrorKind; +#[unstable(feature = "raw_os_error_ty", issue = "107792")] +pub use self::error::RawOsError; +#[unstable(feature = "core_io", issue = "154046")] +pub use self::io_slice::{IoSlice, IoSliceMut}; +#[unstable(feature = "core_io", issue = "154046")] +pub use self::util::{Chain, Empty, Repeat, Sink, Take, empty, repeat, sink}; +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +pub use self::util::{chain, take}; diff --git a/core/src/io/util.rs b/core/src/io/util.rs new file mode 100644 index 0000000000000..232e388433fb0 --- /dev/null +++ b/core/src/io/util.rs @@ -0,0 +1,415 @@ +use crate::fmt; + +/// `Empty` ignores any data written via [`Write`], and will always be empty +/// (returning zero bytes) when read via [`Read`]. +/// +/// [`Write`]: ../../std/io/trait.Write.html +/// [`Read`]: ../../std/io/trait.Read.html +/// +/// This struct is generally created by calling [`empty()`]. Please +/// see the documentation of [`empty()`] for more details. +#[stable(feature = "rust1", since = "1.0.0")] +#[non_exhaustive] +#[derive(Copy, Clone, Debug, Default)] +pub struct Empty; + +/// Creates a value that is always at EOF for reads, and ignores all data written. +/// +/// All calls to [`write`] on the returned instance will return [`Ok(buf.len())`] +/// and the contents of the buffer will not be inspected. +/// +/// All calls to [`read`] from the returned reader will return [`Ok(0)`]. +/// +/// [`Ok(buf.len())`]: Ok +/// [`Ok(0)`]: Ok +/// +/// [`write`]: ../../std/io/trait.Write.html#tymethod.write +/// [`read`]: ../../std/io/trait.Read.html#tymethod.read +/// +/// # Examples +/// +/// ```rust +/// use std::io::{self, Write}; +/// +/// let buffer = vec![1, 2, 3, 5, 8]; +/// let num_bytes = io::empty().write(&buffer).unwrap(); +/// assert_eq!(num_bytes, 5); +/// ``` +/// +/// +/// ```rust +/// use std::io::{self, Read}; +/// +/// let mut buffer = String::new(); +/// io::empty().read_to_string(&mut buffer).unwrap(); +/// assert!(buffer.is_empty()); +/// ``` +#[must_use] +#[stable(feature = "rust1", since = "1.0.0")] +#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] +pub const fn empty() -> Empty { + Empty +} + +/// A reader which yields one byte over and over and over and over and over and... +/// +/// This struct is generally created by calling [`repeat()`]. Please +/// see the documentation of [`repeat()`] for more details. +#[stable(feature = "rust1", since = "1.0.0")] +#[non_exhaustive] +pub struct Repeat { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub byte: u8, +} + +/// Creates an instance of a reader that infinitely repeats one byte. +/// +/// All reads from this reader will succeed by filling the specified buffer with +/// the given byte. +/// +/// # Examples +/// +/// ``` +/// use std::io::{self, Read}; +/// +/// let mut buffer = [0; 3]; +/// io::repeat(0b101).read_exact(&mut buffer).unwrap(); +/// assert_eq!(buffer, [0b101, 0b101, 0b101]); +/// ``` +#[must_use] +#[stable(feature = "rust1", since = "1.0.0")] +#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] +pub const fn repeat(byte: u8) -> Repeat { + Repeat { byte } +} + +#[stable(feature = "std_debug", since = "1.16.0")] +impl fmt::Debug for Repeat { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Repeat").finish_non_exhaustive() + } +} + +/// A writer which will move data into the void. +/// +/// This struct is generally created by calling [`sink()`]. Please +/// see the documentation of [`sink()`] for more details. +#[stable(feature = "rust1", since = "1.0.0")] +#[non_exhaustive] +#[derive(Copy, Clone, Debug, Default)] +pub struct Sink; + +/// Creates an instance of a writer which will successfully consume all data. +/// +/// All calls to [`write`] on the returned instance will return [`Ok(buf.len())`] +/// and the contents of the buffer will not be inspected. +/// +/// [`write`]: ../../std/io/trait.Write.html#tymethod.write +/// [`Ok(buf.len())`]: Ok +/// +/// # Examples +/// +/// ```rust +/// use std::io::{self, Write}; +/// +/// let buffer = vec![1, 2, 3, 5, 8]; +/// let num_bytes = io::sink().write(&buffer).unwrap(); +/// assert_eq!(num_bytes, 5); +/// ``` +#[must_use] +#[stable(feature = "rust1", since = "1.0.0")] +#[rustc_const_stable(feature = "const_io_structs", since = "1.79.0")] +pub const fn sink() -> Sink { + Sink +} + +/// Adapter to chain together two readers. +/// +/// This struct is generally created by calling [`chain`] on a reader. +/// Please see the documentation of [`chain`] for more details. +/// +/// [`chain`]: ../../std/io/trait.Read.html#method.chain +#[stable(feature = "rust1", since = "1.0.0")] +#[derive(Debug)] +#[non_exhaustive] +pub struct Chain { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub first: T, + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub second: U, + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub done_first: bool, +} + +impl Chain { + /// Consumes the `Chain`, returning the wrapped readers. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut foo_file = File::open("foo.txt")?; + /// let mut bar_file = File::open("bar.txt")?; + /// + /// let chain = foo_file.chain(bar_file); + /// let (foo_file, bar_file) = chain.into_inner(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn into_inner(self) -> (T, U) { + (self.first, self.second) + } + + /// Gets references to the underlying readers in this `Chain`. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying readers as doing so may corrupt the internal state of this + /// `Chain`. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut foo_file = File::open("foo.txt")?; + /// let mut bar_file = File::open("bar.txt")?; + /// + /// let chain = foo_file.chain(bar_file); + /// let (foo_file, bar_file) = chain.get_ref(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn get_ref(&self) -> (&T, &U) { + (&self.first, &self.second) + } + + /// Gets mutable references to the underlying readers in this `Chain`. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying readers as doing so may corrupt the internal state of this + /// `Chain`. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut foo_file = File::open("foo.txt")?; + /// let mut bar_file = File::open("bar.txt")?; + /// + /// let mut chain = foo_file.chain(bar_file); + /// let (foo_file, bar_file) = chain.get_mut(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn get_mut(&mut self) -> (&mut T, &mut U) { + (&mut self.first, &mut self.second) + } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +#[must_use] +#[inline] +pub const fn chain(first: T, second: U) -> Chain { + Chain { first, second, done_first: false } +} + +/// Reader adapter which limits the bytes read from an underlying reader. +/// +/// This struct is generally created by calling [`take`] on a reader. +/// Please see the documentation of [`take`] for more details. +/// +/// [`take`]: ../../std/io/trait.Read.html#method.take +#[stable(feature = "rust1", since = "1.0.0")] +#[derive(Debug)] +#[non_exhaustive] +pub struct Take { + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub inner: T, + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub len: u64, + #[doc(hidden)] + #[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] + pub limit: u64, +} + +impl Take { + /// Returns the number of bytes that can be read before this instance will + /// return EOF. + /// + /// # Note + /// + /// This instance may reach `EOF` after reading fewer bytes than indicated by + /// this method if the underlying [`Read`] instance reaches EOF. + /// + /// [`Read`]: ../../std/io/trait.Read.html + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let f = File::open("foo.txt")?; + /// + /// // read at most five bytes + /// let handle = f.take(5); + /// + /// println!("limit: {}", handle.limit()); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "rust1", since = "1.0.0")] + pub fn limit(&self) -> u64 { + self.limit + } + + /// Returns the number of bytes read so far. + #[unstable(feature = "seek_io_take_position", issue = "97227")] + #[inline] + pub fn position(&self) -> u64 { + self.len - self.limit + } + + /// Sets the number of bytes that can be read before this instance will + /// return EOF. This is the same as constructing a new `Take` instance, so + /// the amount of bytes read and the previous limit value don't matter when + /// calling this method. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let f = File::open("foo.txt")?; + /// + /// // read at most five bytes + /// let mut handle = f.take(5); + /// handle.set_limit(10); + /// + /// assert_eq!(handle.limit(), 10); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "take_set_limit", since = "1.27.0")] + pub fn set_limit(&mut self, limit: u64) { + self.len = limit; + self.limit = limit; + } + + /// Consumes the `Take`, returning the wrapped reader. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut file = File::open("foo.txt")?; + /// + /// let mut buffer = [0; 5]; + /// let mut handle = file.take(5); + /// handle.read(&mut buffer)?; + /// + /// let file = handle.into_inner(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "io_take_into_inner", since = "1.15.0")] + pub fn into_inner(self) -> T { + self.inner + } + + /// Gets a reference to the underlying reader. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying reader as doing so may corrupt the internal limit of this + /// `Take`. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut file = File::open("foo.txt")?; + /// + /// let mut buffer = [0; 5]; + /// let mut handle = file.take(5); + /// handle.read(&mut buffer)?; + /// + /// let file = handle.get_ref(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn get_ref(&self) -> &T { + &self.inner + } + + /// Gets a mutable reference to the underlying reader. + /// + /// Care should be taken to avoid modifying the internal I/O state of the + /// underlying reader as doing so may corrupt the internal limit of this + /// `Take`. + /// + /// # Examples + /// + /// ```no_run + /// use std::io; + /// use std::io::prelude::*; + /// use std::fs::File; + /// + /// fn main() -> io::Result<()> { + /// let mut file = File::open("foo.txt")?; + /// + /// let mut buffer = [0; 5]; + /// let mut handle = file.take(5); + /// handle.read(&mut buffer)?; + /// + /// let file = handle.get_mut(); + /// Ok(()) + /// } + /// ``` + #[stable(feature = "more_io_inner_methods", since = "1.20.0")] + pub fn get_mut(&mut self) -> &mut T { + &mut self.inner + } +} + +#[doc(hidden)] +#[unstable(feature = "core_io_internals", reason = "exposed only for libstd", issue = "none")] +#[must_use] +#[inline] +pub const fn take(inner: T, limit: u64) -> Take { + Take { inner, limit, len: limit } +} diff --git a/core/src/iter/adapters/array_chunks.rs b/core/src/iter/adapters/array_chunks.rs index 7c003cff10c7b..a3e5ae5e7698b 100644 --- a/core/src/iter/adapters/array_chunks.rs +++ b/core/src/iter/adapters/array_chunks.rs @@ -26,7 +26,7 @@ where I: Iterator, { #[track_caller] - pub(in crate::iter) fn new(iter: I) -> Self { + pub(in crate::iter) const fn new(iter: I) -> Self { assert!(N != 0, "chunk size must be non-zero"); Self { iter, remainder: None } } diff --git a/core/src/iter/adapters/chain.rs b/core/src/iter/adapters/chain.rs index 0ece54554d464..d143b67fd4353 100644 --- a/core/src/iter/adapters/chain.rs +++ b/core/src/iter/adapters/chain.rs @@ -33,7 +33,7 @@ pub struct Chain { b: Option, } impl Chain { - pub(in super::super) fn new(a: A, b: B) -> Chain { + pub(in super::super) const fn new(a: A, b: B) -> Chain { Chain { a: Some(a), b: Some(b) } } } diff --git a/core/src/iter/adapters/cloned.rs b/core/src/iter/adapters/cloned.rs index aea6d64281aec..c0b6a4053c825 100644 --- a/core/src/iter/adapters/cloned.rs +++ b/core/src/iter/adapters/cloned.rs @@ -2,7 +2,7 @@ use core::num::NonZero; use crate::iter::adapters::zip::try_get_unchecked; use crate::iter::adapters::{SourceIter, TrustedRandomAccess, TrustedRandomAccessNoCoerce}; -use crate::iter::{FusedIterator, InPlaceIterable, TrustedLen, UncheckedIterator}; +use crate::iter::{FusedIterator, InPlaceIterable, TrustedLen}; use crate::ops::Try; /// An iterator that clones the elements of an underlying iterator. @@ -20,7 +20,7 @@ pub struct Cloned { } impl Cloned { - pub(in crate::iter) fn new(it: I) -> Cloned { + pub(in crate::iter) const fn new(it: I) -> Cloned { Cloned { it } } } @@ -142,19 +142,6 @@ where { } -impl<'a, I, T: 'a> UncheckedIterator for Cloned -where - I: UncheckedIterator, - T: Clone, -{ - unsafe fn next_unchecked(&mut self) -> T { - // SAFETY: `Cloned` is 1:1 with the inner iterator, so if the caller promised - // that there's an element left, the inner iterator has one too. - let item = unsafe { self.it.next_unchecked() }; - item.clone() - } -} - #[stable(feature = "default_iters", since = "1.70.0")] impl Default for Cloned { /// Creates a `Cloned` iterator from the default value of `I` diff --git a/core/src/iter/adapters/copied.rs b/core/src/iter/adapters/copied.rs index 9627ace29795c..ba87fb7216059 100644 --- a/core/src/iter/adapters/copied.rs +++ b/core/src/iter/adapters/copied.rs @@ -21,7 +21,7 @@ pub struct Copied { } impl Copied { - pub(in crate::iter) fn new(it: I) -> Copied { + pub(in crate::iter) const fn new(it: I) -> Copied { Copied { it } } diff --git a/core/src/iter/adapters/cycle.rs b/core/src/iter/adapters/cycle.rs index 6cb1a3a46763e..86a6966ebf85b 100644 --- a/core/src/iter/adapters/cycle.rs +++ b/core/src/iter/adapters/cycle.rs @@ -17,7 +17,8 @@ pub struct Cycle { iter: I, } -impl Cycle { +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl Cycle { pub(in crate::iter) fn new(iter: I) -> Cycle { Cycle { orig: iter.clone(), iter } } diff --git a/core/src/iter/adapters/enumerate.rs b/core/src/iter/adapters/enumerate.rs index f7b9f0b7a5e9d..916ba88e6160a 100644 --- a/core/src/iter/adapters/enumerate.rs +++ b/core/src/iter/adapters/enumerate.rs @@ -20,7 +20,7 @@ pub struct Enumerate { count: usize, } impl Enumerate { - pub(in crate::iter) fn new(iter: I) -> Enumerate { + pub(in crate::iter) const fn new(iter: I) -> Enumerate { Enumerate { iter, count: 0 } } diff --git a/core/src/iter/adapters/filter.rs b/core/src/iter/adapters/filter.rs index b22419ccf080a..cf21536784a28 100644 --- a/core/src/iter/adapters/filter.rs +++ b/core/src/iter/adapters/filter.rs @@ -24,7 +24,7 @@ pub struct Filter { predicate: P, } impl Filter { - pub(in crate::iter) fn new(iter: I, predicate: P) -> Filter { + pub(in crate::iter) const fn new(iter: I, predicate: P) -> Filter { Filter { iter, predicate } } } diff --git a/core/src/iter/adapters/filter_map.rs b/core/src/iter/adapters/filter_map.rs index 24ec6b1741ce1..3fd7e16d1c148 100644 --- a/core/src/iter/adapters/filter_map.rs +++ b/core/src/iter/adapters/filter_map.rs @@ -20,7 +20,7 @@ pub struct FilterMap { f: F, } impl FilterMap { - pub(in crate::iter) fn new(iter: I, f: F) -> FilterMap { + pub(in crate::iter) const fn new(iter: I, f: F) -> FilterMap { FilterMap { iter, f } } } diff --git a/core/src/iter/adapters/flatten.rs b/core/src/iter/adapters/flatten.rs index c50f07ff6bb66..7e3c69e29e96f 100644 --- a/core/src/iter/adapters/flatten.rs +++ b/core/src/iter/adapters/flatten.rs @@ -185,7 +185,8 @@ pub struct Flatten> { inner: FlattenCompat::IntoIter>, } -impl> Flatten { +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl> Flatten { pub(in super::super) fn new(iter: I) -> Flatten { Flatten { inner: FlattenCompat::new(iter) } } @@ -358,9 +359,11 @@ struct FlattenCompat { frontiter: Option, backiter: Option, } -impl FlattenCompat + +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const impl FlattenCompat where - I: Iterator, + I: [const] Iterator, { /// Adapts an iterator by flattening it, for use in `flatten()` and `flat_map()`. fn new(iter: I) -> FlattenCompat { diff --git a/core/src/iter/adapters/fuse.rs b/core/src/iter/adapters/fuse.rs index 0072a95e8dfe0..ef956e8bdef5d 100644 --- a/core/src/iter/adapters/fuse.rs +++ b/core/src/iter/adapters/fuse.rs @@ -21,7 +21,7 @@ pub struct Fuse { iter: Option, } impl Fuse { - pub(in crate::iter) fn new(iter: I) -> Fuse { + pub(in crate::iter) const fn new(iter: I) -> Fuse { Fuse { iter: Some(iter) } } diff --git a/core/src/iter/adapters/inspect.rs b/core/src/iter/adapters/inspect.rs index 0e2a68a503e44..de94951bc80ff 100644 --- a/core/src/iter/adapters/inspect.rs +++ b/core/src/iter/adapters/inspect.rs @@ -20,7 +20,7 @@ pub struct Inspect { f: F, } impl Inspect { - pub(in crate::iter) fn new(iter: I, f: F) -> Inspect { + pub(in crate::iter) const fn new(iter: I, f: F) -> Inspect { Inspect { iter, f } } } diff --git a/core/src/iter/adapters/intersperse.rs b/core/src/iter/adapters/intersperse.rs index f64dea2df862c..1669a32ae77d2 100644 --- a/core/src/iter/adapters/intersperse.rs +++ b/core/src/iter/adapters/intersperse.rs @@ -20,7 +20,7 @@ impl Intersperse where I::Item: Clone, { - pub(in crate::iter) fn new(iter: I, separator: I::Item) -> Self { + pub(in crate::iter) const fn new(iter: I, separator: I::Item) -> Self { Self { started: false, separator, next_item: None, iter } } } @@ -129,7 +129,7 @@ where I: Iterator, G: FnMut() -> I::Item, { - pub(in crate::iter) fn new(iter: I, separator: G) -> Self { + pub(in crate::iter) const fn new(iter: I, separator: G) -> Self { Self { started: false, separator, next_item: None, iter } } } diff --git a/core/src/iter/adapters/map.rs b/core/src/iter/adapters/map.rs index 007c2d5acc2d0..75f70dcd9b58f 100644 --- a/core/src/iter/adapters/map.rs +++ b/core/src/iter/adapters/map.rs @@ -1,7 +1,7 @@ use crate::fmt; use crate::iter::adapters::zip::try_get_unchecked; use crate::iter::adapters::{SourceIter, TrustedRandomAccess, TrustedRandomAccessNoCoerce}; -use crate::iter::{FusedIterator, InPlaceIterable, TrustedFused, TrustedLen, UncheckedIterator}; +use crate::iter::{FusedIterator, InPlaceIterable, TrustedFused, TrustedLen}; use crate::num::NonZero; use crate::ops::Try; @@ -65,7 +65,7 @@ pub struct Map { } impl Map { - pub(in crate::iter) fn new(iter: I, f: F) -> Map { + pub(in crate::iter) const fn new(iter: I, f: F) -> Map { Map { iter, f } } @@ -194,19 +194,6 @@ where { } -impl UncheckedIterator for Map -where - I: UncheckedIterator, - F: FnMut(I::Item) -> B, -{ - unsafe fn next_unchecked(&mut self) -> B { - // SAFETY: `Map` is 1:1 with the inner iterator, so if the caller promised - // that there's an element left, the inner iterator has one too. - let item = unsafe { self.iter.next_unchecked() }; - (self.f)(item) - } -} - #[doc(hidden)] #[unstable(feature = "trusted_random_access", issue = "none")] unsafe impl TrustedRandomAccess for Map where I: TrustedRandomAccess {} diff --git a/core/src/iter/adapters/map_while.rs b/core/src/iter/adapters/map_while.rs index c047c40de050e..3e34427da6142 100644 --- a/core/src/iter/adapters/map_while.rs +++ b/core/src/iter/adapters/map_while.rs @@ -20,7 +20,7 @@ pub struct MapWhile { } impl MapWhile { - pub(in crate::iter) fn new(iter: I, predicate: P) -> MapWhile { + pub(in crate::iter) const fn new(iter: I, predicate: P) -> MapWhile { MapWhile { iter, predicate } } } diff --git a/core/src/iter/adapters/map_windows.rs b/core/src/iter/adapters/map_windows.rs index 9398fbbe8a1cd..bcda315f7a4a0 100644 --- a/core/src/iter/adapters/map_windows.rs +++ b/core/src/iter/adapters/map_windows.rs @@ -1,5 +1,5 @@ use crate::iter::FusedIterator; -use crate::mem::MaybeUninit; +use crate::mem::{MaybeUninit, SizedTypeProperties}; use crate::{fmt, ptr}; /// An iterator over the mapped windows of another iterator. @@ -43,11 +43,11 @@ struct Buffer { } impl MapWindows { - pub(in crate::iter) fn new(iter: I, f: F) -> Self { + pub(in crate::iter) const fn new(iter: I, f: F) -> Self { assert!(N != 0, "array in `Iterator::map_windows` must contain more than 0 elements"); // Only ZST arrays' length can be so large. - if size_of::() == 0 { + if I::Item::IS_ZST { assert!( N.checked_mul(2).is_some(), "array size of `Iterator::map_windows` is too large" @@ -60,7 +60,7 @@ impl MapWindows { impl MapWindowsInner { #[inline] - fn new(iter: I) -> Self { + const fn new(iter: I) -> Self { Self { iter, buffer: None } } @@ -218,10 +218,8 @@ impl Drop for Buffer { // SAFETY: our invariant guarantees that N elements starting from // `self.start` are initialized. We drop them here. unsafe { - let initialized_part: *mut [T] = crate::ptr::slice_from_raw_parts_mut( - self.buffer_mut_ptr().add(self.start).cast(), - N, - ); + let initialized_part: *mut [T] = + self.buffer_mut_ptr().add(self.start).cast::().cast_slice(N); ptr::drop_in_place(initialized_part); } } diff --git a/core/src/iter/adapters/peekable.rs b/core/src/iter/adapters/peekable.rs index 9f6d1df57dbe8..4bddc2025c26e 100644 --- a/core/src/iter/adapters/peekable.rs +++ b/core/src/iter/adapters/peekable.rs @@ -21,7 +21,7 @@ pub struct Peekable { } impl Peekable { - pub(in crate::iter) fn new(iter: I) -> Peekable { + pub(in crate::iter) const fn new(iter: I) -> Peekable { Peekable { iter, peeked: None } } } diff --git a/core/src/iter/adapters/rev.rs b/core/src/iter/adapters/rev.rs index 17d3eef597dcb..b9ada504525f9 100644 --- a/core/src/iter/adapters/rev.rs +++ b/core/src/iter/adapters/rev.rs @@ -17,7 +17,7 @@ pub struct Rev { } impl Rev { - pub(in crate::iter) fn new(iter: T) -> Rev { + pub(in crate::iter) const fn new(iter: T) -> Rev { Rev { iter } } diff --git a/core/src/iter/adapters/scan.rs b/core/src/iter/adapters/scan.rs index e12375c94e067..7d084a89bd940 100644 --- a/core/src/iter/adapters/scan.rs +++ b/core/src/iter/adapters/scan.rs @@ -21,7 +21,7 @@ pub struct Scan { } impl Scan { - pub(in crate::iter) fn new(iter: I, state: St, f: F) -> Scan { + pub(in crate::iter) const fn new(iter: I, state: St, f: F) -> Scan { Scan { iter, state, f } } } diff --git a/core/src/iter/adapters/skip.rs b/core/src/iter/adapters/skip.rs index 55c4a7f14fbd6..f7a6beb2b8c63 100644 --- a/core/src/iter/adapters/skip.rs +++ b/core/src/iter/adapters/skip.rs @@ -24,7 +24,7 @@ pub struct Skip { } impl Skip { - pub(in crate::iter) fn new(iter: I, n: usize) -> Skip { + pub(in crate::iter) const fn new(iter: I, n: usize) -> Skip { Skip { iter, n } } } diff --git a/core/src/iter/adapters/skip_while.rs b/core/src/iter/adapters/skip_while.rs index 8ae453e76fa0d..ced4fd8f2abc4 100644 --- a/core/src/iter/adapters/skip_while.rs +++ b/core/src/iter/adapters/skip_while.rs @@ -21,7 +21,7 @@ pub struct SkipWhile { } impl SkipWhile { - pub(in crate::iter) fn new(iter: I, predicate: P) -> SkipWhile { + pub(in crate::iter) const fn new(iter: I, predicate: P) -> SkipWhile { SkipWhile { iter, flag: false, predicate } } } diff --git a/core/src/iter/adapters/take.rs b/core/src/iter/adapters/take.rs index b96335f415257..ecd462c60eda3 100644 --- a/core/src/iter/adapters/take.rs +++ b/core/src/iter/adapters/take.rs @@ -20,7 +20,7 @@ pub struct Take { } impl Take { - pub(in crate::iter) fn new(iter: I, n: usize) -> Take { + pub(in crate::iter) const fn new(iter: I, n: usize) -> Take { Take { iter, n } } } diff --git a/core/src/iter/adapters/take_while.rs b/core/src/iter/adapters/take_while.rs index 06028ea98e7fd..6e40629567a83 100644 --- a/core/src/iter/adapters/take_while.rs +++ b/core/src/iter/adapters/take_while.rs @@ -21,7 +21,7 @@ pub struct TakeWhile { } impl TakeWhile { - pub(in crate::iter) fn new(iter: I, predicate: P) -> TakeWhile { + pub(in crate::iter) const fn new(iter: I, predicate: P) -> TakeWhile { TakeWhile { iter, flag: false, predicate } } } diff --git a/core/src/iter/adapters/zip.rs b/core/src/iter/adapters/zip.rs index c5e199c30821d..4b19c7ffc00f8 100644 --- a/core/src/iter/adapters/zip.rs +++ b/core/src/iter/adapters/zip.rs @@ -1,8 +1,6 @@ use crate::cmp; use crate::fmt::{self, Debug}; -use crate::iter::{ - FusedIterator, InPlaceIterable, SourceIter, TrustedFused, TrustedLen, UncheckedIterator, -}; +use crate::iter::{FusedIterator, InPlaceIterable, SourceIter, TrustedFused, TrustedLen}; use crate::num::NonZero; /// An iterator that iterates two other iterators simultaneously. @@ -456,13 +454,6 @@ where { } -impl UncheckedIterator for Zip -where - A: UncheckedIterator, - B: UncheckedIterator, -{ -} - // Arbitrarily selects the left side of the zip iteration as extractable "source" // it would require negative trait bounds to be able to try both #[unstable(issue = "none", feature = "inplace_iteration")] diff --git a/core/src/iter/mod.rs b/core/src/iter/mod.rs index d532f1e568071..9ddafd47807f2 100644 --- a/core/src/iter/mod.rs +++ b/core/src/iter/mod.rs @@ -458,7 +458,6 @@ pub use self::traits::TrustedFused; pub use self::traits::TrustedLen; #[unstable(feature = "trusted_step", issue = "85731")] pub use self::traits::TrustedStep; -pub(crate) use self::traits::UncheckedIterator; #[stable(feature = "rust1", since = "1.0.0")] pub use self::traits::{ DoubleEndedIterator, ExactSizeIterator, Extend, FromIterator, IntoIterator, Product, Sum, diff --git a/core/src/iter/range.rs b/core/src/iter/range.rs index 951bb5d0029f6..949295a77bca6 100644 --- a/core/src/iter/range.rs +++ b/core/src/iter/range.rs @@ -15,13 +15,14 @@ macro_rules! unsafe_impl_trusted_step { )*}; } unsafe_impl_trusted_step![AsciiChar char i8 i16 i32 i64 i128 isize u8 u16 u32 u64 u128 usize Ipv4Addr Ipv6Addr]; +unsafe_impl_trusted_step![NonZero NonZero NonZero NonZero NonZero NonZero]; /// Objects that have a notion of *successor* and *predecessor* operations. /// /// The *successor* operation moves towards values that compare greater. /// The *predecessor* operation moves towards values that compare lesser. #[rustc_diagnostic_item = "range_step"] -#[rustc_on_unimplemented( +#[diagnostic::on_unimplemented( message = "`std::ops::Range<{Self}>` is not an iterator", label = "`Range<{Self}>` is not an iterator", note = "`Range` only implements `Iterator` for select types in the standard library, \ @@ -255,10 +256,8 @@ macro_rules! step_identical_methods { macro_rules! step_integer_impls { { - narrower than or same width as usize: - $( [ $u_narrower:ident $i_narrower:ident ] ),+; - wider than usize: - $( [ $u_wider:ident $i_wider:ident ] ),+; + [ $( [ $u_narrower:ident $i_narrower:ident ] ),+ ] <= usize < + [ $( [ $u_wider:ident $i_wider:ident ] ),+ ] } => { $( #[allow(unreachable_patterns)] @@ -437,25 +436,145 @@ macro_rules! step_integer_impls { #[cfg(target_pointer_width = "64")] step_integer_impls! { - narrower than or same width as usize: [u8 i8], [u16 i16], [u32 i32], [u64 i64], [usize isize]; - wider than usize: [u128 i128]; + [ [u8 i8], [u16 i16], [u32 i32], [u64 i64], [usize isize] ] <= usize < [ [u128 i128] ] } #[cfg(target_pointer_width = "32")] step_integer_impls! { - narrower than or same width as usize: [u8 i8], [u16 i16], [u32 i32], [usize isize]; - wider than usize: [u64 i64], [u128 i128]; + [ [u8 i8], [u16 i16], [u32 i32], [usize isize] ] <= usize < [ [u64 i64], [u128 i128] ] } #[cfg(target_pointer_width = "16")] step_integer_impls! { - narrower than or same width as usize: [u8 i8], [u16 i16], [usize isize]; - wider than usize: [u32 i32], [u64 i64], [u128 i128]; + [ [u8 i8], [u16 i16], [usize isize] ] <= usize < [ [u32 i32], [u64 i64], [u128 i128] ] +} + +// These are still macro-generated because the integer literals resolve to different types. +macro_rules! step_nonzero_identical_methods { + ($int:ident) => { + #[inline] + unsafe fn forward_unchecked(start: Self, n: usize) -> Self { + // SAFETY: the caller has to guarantee that `start + n` doesn't overflow. + unsafe { Self::new_unchecked(start.get().unchecked_add(n as $int)) } + } + + #[inline] + unsafe fn backward_unchecked(start: Self, n: usize) -> Self { + // SAFETY: the caller has to guarantee that `start - n` doesn't overflow or hit zero. + unsafe { Self::new_unchecked(start.get().unchecked_sub(n as $int)) } + } + + #[inline] + #[allow(arithmetic_overflow)] + #[rustc_inherit_overflow_checks] + fn forward(start: Self, n: usize) -> Self { + // In debug builds, trigger a panic on overflow. + // This should optimize completely out in release builds. + if Self::forward_checked(start, n).is_none() { + let _ = $int::MAX + 1; + } + // Do saturating math (wrapping math causes UB if it wraps to Zero) + start.saturating_add(n as $int) + } + + #[inline] + #[allow(arithmetic_overflow)] + #[rustc_inherit_overflow_checks] + fn backward(start: Self, n: usize) -> Self { + // In debug builds, trigger a panic on overflow. + // This should optimize completely out in release builds. + if Self::backward_checked(start, n).is_none() { + let _ = $int::MIN - 1; + } + // Do saturating math (wrapping math causes UB if it wraps to Zero) + Self::new(start.get().saturating_sub(n as $int)).unwrap_or(Self::MIN) + } + + #[inline] + fn steps_between(start: &Self, end: &Self) -> (usize, Option) { + if *start <= *end { + #[allow(irrefutable_let_patterns, reason = "happens on usize or narrower")] + if let Ok(steps) = usize::try_from(end.get() - start.get()) { + (steps, Some(steps)) + } else { + (usize::MAX, None) + } + } else { + (0, None) + } + } + }; +} + +macro_rules! step_nonzero_impls { + { + [$( $narrower:ident ),+] <= usize < [$( $wider:ident ),+] + } => { + $( + #[allow(unreachable_patterns)] + #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")] + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + impl const Step for NonZero<$narrower> { + step_nonzero_identical_methods!($narrower); + + #[inline] + fn forward_checked(start: Self, n: usize) -> Option { + match $narrower::try_from(n) { + Ok(n) => start.checked_add(n), + Err(_) => None, // if n is out of range, `unsigned_start + n` is too + } + } + + #[inline] + fn backward_checked(start: Self, n: usize) -> Option { + match $narrower::try_from(n) { + // *_sub() is not implemented on NonZero + Ok(n) => start.get().checked_sub(n).and_then(Self::new), + Err(_) => None, // if n is out of range, `unsigned_start - n` is too + } + } + } + )+ + + $( + #[allow(unreachable_patterns)] + #[unstable(feature = "step_trait", reason = "recently redesigned", issue = "42168")] + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + impl const Step for NonZero<$wider> { + step_nonzero_identical_methods!($wider); + + #[inline] + fn forward_checked(start: Self, n: usize) -> Option { + start.checked_add(n as $wider) + } + + #[inline] + fn backward_checked(start: Self, n: usize) -> Option { + start.get().checked_sub(n as $wider).and_then(Self::new) + } + } + )+ + }; +} + +#[cfg(target_pointer_width = "64")] +step_nonzero_impls! { + [u8, u16, u32, u64, usize] <= usize < [u128] +} + +#[cfg(target_pointer_width = "32")] +step_nonzero_impls! { + [u8, u16, u32, usize] <= usize < [u64, u128] +} + +#[cfg(target_pointer_width = "16")] +step_nonzero_impls! { + [u8, u16, usize] <= usize < [u32, u64, u128] } #[unstable(feature = "step_trait", issue = "42168")] #[rustc_const_unstable(feature = "step_trait", issue = "42168")] -impl const Step for char { +const impl Step for char { #[inline] fn steps_between(&start: &char, &end: &char) -> (usize, Option) { let start = start as u32; @@ -543,7 +662,7 @@ impl const Step for char { #[unstable(feature = "step_trait", issue = "42168")] #[rustc_const_unstable(feature = "step_trait", issue = "42168")] -impl const Step for AsciiChar { +const impl Step for AsciiChar { #[inline] fn steps_between(&start: &AsciiChar, &end: &AsciiChar) -> (usize, Option) { Step::steps_between(&start.to_u8(), &end.to_u8()) @@ -586,7 +705,7 @@ impl const Step for AsciiChar { #[unstable(feature = "step_trait", issue = "42168")] #[rustc_const_unstable(feature = "step_trait", issue = "42168")] -impl const Step for Ipv4Addr { +const impl Step for Ipv4Addr { #[inline] fn steps_between(&start: &Ipv4Addr, &end: &Ipv4Addr) -> (usize, Option) { u32::steps_between(&start.to_bits(), &end.to_bits()) @@ -619,7 +738,7 @@ impl const Step for Ipv4Addr { #[unstable(feature = "step_trait", issue = "42168")] #[rustc_const_unstable(feature = "step_trait", issue = "42168")] -impl const Step for Ipv6Addr { +const impl Step for Ipv6Addr { #[inline] fn steps_between(&start: &Ipv6Addr, &end: &Ipv6Addr) -> (usize, Option) { u128::steps_between(&start.to_bits(), &end.to_bits()) @@ -944,6 +1063,7 @@ impl Iterator for ops::Range { range_exact_iter_impl! { usize u8 u16 isize i8 i16 + NonZero NonZero NonZero // These are incorrect per the reasoning above, // but removing them would be a breaking change as they were stabilized in Rust 1.0.0. @@ -956,22 +1076,30 @@ range_exact_iter_impl! { unsafe_range_trusted_random_access_impl! { usize u8 u16 isize i8 i16 + NonZero NonZero NonZero } #[cfg(target_pointer_width = "32")] unsafe_range_trusted_random_access_impl! { u32 i32 + NonZero } #[cfg(target_pointer_width = "64")] unsafe_range_trusted_random_access_impl! { u32 i32 u64 i64 + NonZero + NonZero } range_incl_exact_iter_impl! { u8 i8 + NonZero + // Since RangeInclusive> can only be 1..=uN::MAX the length of this range is always + // <= uN::MAX, so they are always valid ExactSizeIterator unlike the ranges that include zero. + NonZero NonZero // These are incorrect per the reasoning above, // but removing them would be a breaking change as they were stabilized in Rust 1.26.0. diff --git a/core/src/iter/sources/empty.rs b/core/src/iter/sources/empty.rs index 1844c76e5df7e..7733c2babc550 100644 --- a/core/src/iter/sources/empty.rs +++ b/core/src/iter/sources/empty.rs @@ -82,7 +82,7 @@ impl Clone for Empty { // which isn't necessary. #[stable(feature = "iter_empty", since = "1.2.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] -impl const Default for Empty { +const impl Default for Empty { fn default() -> Empty { Empty(marker::PhantomData) } diff --git a/core/src/iter/sources/repeat_n.rs b/core/src/iter/sources/repeat_n.rs index c29ab24a08357..c89026c16c5c6 100644 --- a/core/src/iter/sources/repeat_n.rs +++ b/core/src/iter/sources/repeat_n.rs @@ -1,5 +1,5 @@ use crate::fmt; -use crate::iter::{FusedIterator, TrustedLen, UncheckedIterator}; +use crate::iter::{FusedIterator, TrustedLen}; use crate::num::NonZero; use crate::ops::Try; @@ -102,6 +102,15 @@ impl fmt::Debug for RepeatN { } } +/// Creates an empty iterator, like [`repeat_n(value, 0)`][`repeat_n`] +/// but without needing any such value at hand. +#[stable(feature = "iter_repeat_n_default", since = "1.97.0")] +impl Default for RepeatN { + fn default() -> Self { + RepeatN { inner: None } + } +} + #[stable(feature = "iter_repeat_n", since = "1.82.0")] impl Iterator for RepeatN { type Item = A; @@ -202,5 +211,3 @@ impl FusedIterator for RepeatN {} #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RepeatN {} -#[stable(feature = "iter_repeat_n", since = "1.82.0")] -impl UncheckedIterator for RepeatN {} diff --git a/core/src/iter/traits/accum.rs b/core/src/iter/traits/accum.rs index 375b5ef52859f..3787e41f0a0b1 100644 --- a/core/src/iter/traits/accum.rs +++ b/core/src/iter/traits/accum.rs @@ -10,11 +10,12 @@ use crate::num::{Saturating, Wrapping}; /// [`sum()`]: Iterator::sum /// [`FromIterator`]: iter::FromIterator #[stable(feature = "iter_arith_traits", since = "1.12.0")] +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] #[diagnostic::on_unimplemented( message = "a value of type `{Self}` cannot be made by summing an iterator over elements of type `{A}`", label = "value of type `{Self}` cannot be made by summing a `std::iter::Iterator`" )] -pub trait Sum: Sized { +pub const trait Sum: Sized { /// Takes an iterator and generates `Self` from the elements by "summing up" /// the items. #[stable(feature = "iter_arith_traits", since = "1.12.0")] @@ -31,11 +32,12 @@ pub trait Sum: Sized { /// [`product()`]: Iterator::product /// [`FromIterator`]: iter::FromIterator #[stable(feature = "iter_arith_traits", since = "1.12.0")] +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] #[diagnostic::on_unimplemented( message = "a value of type `{Self}` cannot be made by multiplying all elements of type `{A}` from an iterator", label = "value of type `{Self}` cannot be made by multiplying all elements from a `std::iter::Iterator`" )] -pub trait Product: Sized { +pub const trait Product: Sized { /// Takes an iterator and generates `Self` from the elements by multiplying /// the items. #[stable(feature = "iter_arith_traits", since = "1.12.0")] diff --git a/core/src/iter/traits/collect.rs b/core/src/iter/traits/collect.rs index 9c3edfd4192d5..e7e5e30b4eff5 100644 --- a/core/src/iter/traits/collect.rs +++ b/core/src/iter/traits/collect.rs @@ -314,7 +314,7 @@ pub const trait IntoIterator { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_iter", issue = "92476")] -impl const IntoIterator for I { +const impl IntoIterator for I { type Item = I::Item; type IntoIter = I; diff --git a/core/src/iter/traits/double_ended.rs b/core/src/iter/traits/double_ended.rs index 9f7ac7da2dbda..ce80874a23897 100644 --- a/core/src/iter/traits/double_ended.rs +++ b/core/src/iter/traits/double_ended.rs @@ -1,3 +1,4 @@ +use crate::marker::Destruct; use crate::num::NonZero; use crate::ops::{ControlFlow, Try}; @@ -38,7 +39,8 @@ use crate::ops::{ControlFlow, Try}; /// ``` #[stable(feature = "rust1", since = "1.0.0")] #[rustc_diagnostic_item = "DoubleEndedIterator"] -pub trait DoubleEndedIterator: Iterator { +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +pub const trait DoubleEndedIterator: [const] Iterator { /// Removes and returns an element from the end of the iterator. /// /// Returns `None` when there are no more elements. @@ -135,6 +137,7 @@ pub trait DoubleEndedIterator: Iterator { /// [`Err(k)`]: Err #[inline] #[unstable(feature = "iter_advance_by", issue = "77404")] + #[rustc_non_const_trait_method] fn advance_back_by(&mut self, n: usize) -> Result<(), NonZero> { for i in 0..n { if self.next_back().is_none() { @@ -188,6 +191,7 @@ pub trait DoubleEndedIterator: Iterator { /// ``` #[inline] #[stable(feature = "iter_nth_back", since = "1.37.0")] + #[rustc_non_const_trait_method] fn nth_back(&mut self, n: usize) -> Option { if self.advance_back_by(n).is_err() { return None; @@ -230,8 +234,8 @@ pub trait DoubleEndedIterator: Iterator { fn try_rfold(&mut self, init: B, mut f: F) -> R where Self: Sized, - F: FnMut(B, Self::Item) -> R, - R: Try, + F: [const] FnMut(B, Self::Item) -> R + [const] Destruct, + R: [const] Try, { let mut accum = init; while let Some(x) = self.next_back() { @@ -300,8 +304,8 @@ pub trait DoubleEndedIterator: Iterator { #[stable(feature = "iter_rfold", since = "1.27.0")] fn rfold(mut self, init: B, mut f: F) -> B where - Self: Sized, - F: FnMut(B, Self::Item) -> B, + Self: Sized + [const] Destruct, + F: [const] FnMut(B, Self::Item) -> B + [const] Destruct, { let mut accum = init; while let Some(x) = self.next_back() { @@ -363,6 +367,7 @@ pub trait DoubleEndedIterator: Iterator { /// ``` #[inline] #[stable(feature = "iter_rfind", since = "1.27.0")] + #[rustc_non_const_trait_method] fn rfind